82 lines
1.7 KiB
Verilog
82 lines
1.7 KiB
Verilog
`timescale 1ns / 1ns
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2024/04/26 17:05:11
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// Design Name:
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// Module Name: tb_tdma
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module tb_tdma ();
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reg clk = 1;
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reg clk_tx = 1;
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reg rst = 1;
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always #1 clk <= ~clk;
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initial begin
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#1000 rst <= 1'b0;
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end
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wire flag_frame_sync_m;
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reg flag_frame_sync_s = 0;
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wire intr_2ps_m;
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wire intr_2ps_s;
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wire tic_hop_m;
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wire tic_hop_s;
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wire tx_start_m;
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wire tx_start_s;
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assign flag_frame_sync_m = 1'b0;
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tdma #(
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.SLOT_LEN (1250000),
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.TIC_TO_PS_LEN (1200000),
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.TIC_FRAME_SYNC(42272)
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) u_tdma_master (
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.clk (clk),
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.rst (rst),
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.flag_is_master (1'b1),
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.flag_frame_sync(flag_frame_sync_m),
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.intr_2ps (intr_2ps_m),
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// .tic_hop (tic_hop_m),
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.tx_start (tx_start_m)
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);
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tdma #(
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.SLOT_LEN (20000),
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.TIC_TO_PS_LEN (18000),
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.TIC_FRAME_SYNC(2000)
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) u_tdma_slave (
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.clk (clk),
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.rst (rst),
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.flag_is_master (1'b0),
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.flag_frame_sync(flag_frame_sync_s),
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.intr_2ps (intr_2ps_s),
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// .tic_hop (tic_hop_s),
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.tx_start (tx_start_s)
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);
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initial begin
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#12000 flag_frame_sync_s <= 1'b1;
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#3 flag_frame_sync_s <= 1'b0;
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end
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endmodule
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