610 lines
23 KiB
Verilog
610 lines
23 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 17:42 11/14/2019
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// Design Name:
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// Module Name: RecvTop
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module RecvTop (
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input clk,
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input clk2,
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input clk_60M_mac,
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input rst,
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input rst2,
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input [11:0] dini,
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input [11:0] dinq,
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output [3:0] ad9361_ctrl_in,
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output flag_stop, //给shx，拉高8个clk表示当前时帧有效数据接收完毕
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output [16:0] addr_stop, //给shx，拉高8个clk,与flag_stop对齐，指示位置与最后1bit有效数据的位置对齐
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input [6:0] vio_stopbit, //寻找停止位，默认值为7'd60
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//debug
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//trigger
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output rst_TimeSync,
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output rst_freq,
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output DAGC_rdy,
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output framesync, //帧同步峰
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output framesync_delay, //帧同步峰，与频率补偿输出对应
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output framesync_tsync, //帧同步标志，与TSync输出对应
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output IntpARdy, //TSync输出nd
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output nd_SC_FDE_dout, //SC_FDE输出nd
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output framerdy, //一帧译码结果存储完毕标志
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output reg flag_bercount = 1'd0,
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output reg flag_badframe = 1'd0,
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output reg flag_ber = 1'd0,
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//各模块输出，星座图
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output [11:0] dc_removal_dout_i, //MGC_adaptation、去直流输出
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output [11:0] dc_removal_dout_q,
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output [ 9:0] matchfilterout_i, //MF输出
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output [ 9:0] matchfilterout_q,
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output [ 9:0] DAGC_out_i, //DAGC输出
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output [ 9:0] DAGC_out_q,
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output [ 9:0] freqdataout_i, //频率补偿输出
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output [ 9:0] freqdataout_q,
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output [ 9:0] IntpOuti, //TSync输出
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output [ 9:0] IntpOutq,
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output [ 9:0] SC_FDE_douti, //SC_FDE输出
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output [ 9:0] SC_FDE_doutq,
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//MGC_adaptation
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output [24:0] mean_temp,
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output [12:0] acc_mean,
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output [ 4:0] state_mgc,
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output mgc1_rdy,
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output flag_state_mgc,
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output [ 2:0] state_rst,
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output flag_overflow,
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output flag_small,
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//DC
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output [11:0] dc_value_i,
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output [11:0] dc_value_q,
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output flag_dc,
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//DAGC
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output flag_agch,
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output flag_agcl,
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output flag_agc_power,
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output [12:0] agc_ref,
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output [12:0] agc_check,
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//power test
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output flag_powerabsh,
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output flag_powerabsl,
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output flag_abs_power,
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output [10:0] abs_ref,
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output [10:0] abs_check,
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//TSync
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output [ 3:0] flag_clk_4bit, //位同步选取通道结果
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//SC_FDE,溢出标志
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output flagoverflow_fftpilot_26to14, //第1个fft结果截位，即导频fft结果的截位，26截到14
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output flagoverflow_ChnZF_26to18, //第2个fft结果截位，即ZF信道估计结果的截位，26截到18
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output flagoverflow_comdiv_34to20i, //第1个除法器结果截位，即复数除法结果的截位，得到没有去噪的ZF估计，34截到18
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output flagoverflow_comdiv_34to20q, //第1个除法器结果截位，即复数除法结果的截位，得到没有去噪的ZF估计，34截到18
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output flagoverflow_ifftzero_29to17i, //第1个ifft结果截位，即ZF零域估计处，结果先除掉低8位，29-8=21截到17
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output flagoverflow_ifftzero_29to17q, //第1个ifft结果截位，即ZF零域估计处，结果先除掉低8位，29-8=21截到17
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output flagoverflow_MMSEdiv_divisor_31to28, //第2个除法器，即MMSE除法的分母截位，31截到28
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output flagoverflow_divmmse_34to11, //第2个除法器结果截位，即MMSE信道估计结果的截位，34截到11
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output flagoverflow_ifftindata_28to20i, //均衡完毕后（频域结果）的截位，即乘法器输出结果的截位，28截到20
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output flagoverflow_ifftindata_28to20q, //均衡完毕后（频域结果）的截位，即乘法器输出结果的截位，28截到20
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output flagoverflow_fftdata_26to16i, //数据段ow的fft输出截位，26截到16
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output flagoverflow_fftdata_26to16q, //数据段ow的fft输出截位，26截到16
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output flagoverflow_FDE_dataout_29to10i, //ifft结果截位，即均衡结果处，结果先除掉低8位，29-7=22截到10
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output flagoverflow_FDE_dataout_29to10q, //ifft结果截位，即均衡结果处，结果先除掉低8位，29-7=22截到10
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output reg flagoverflow = 1'd0, //总溢出标志
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output Pilot_rdy_hide1_d1,
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output [63:0] recvNetData,
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output recvNetDataNd,
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input debug_loss
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);
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reg [7:0] cnt_mgc_delay;
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wire mgc_start;
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wire flag_mgc_done; // level flag
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wire flag_mgc_done_4x; // level flag
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always @(posedge clk) begin
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if (rst) begin
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cnt_mgc_delay <= 0;
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end
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else if (cnt_mgc_delay < 8'hff) begin
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cnt_mgc_delay <= cnt_mgc_delay + 1;
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end
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else begin
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cnt_mgc_delay <= cnt_mgc_delay;
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end
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end
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assign mgc_start = (cnt_mgc_delay == 8'hff);
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ad9361_mgc_pin_ctrl u_ad9361_mgc_pin_ctrl (
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.clk (clk),
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.rst (rst),
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.start (mgc_start),
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.rx_data_i (dini),
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.rx_data_q (dinq),
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.ad9361_ctrl_in(ad9361_ctrl_in),
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.flag_mgc_done (flag_mgc_done)
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);
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wire MF_rdy; // flag_mgc_done_d1
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wire MF_rst; // flag_mgc_done_pulse_d2
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wire fifo_out_valid;
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reg [ 2:0] cnt_fifo_out_valid;
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reg [ 2:0] cnt_fifo_out_valid_sel = 1; // 根据speed mode对应的计数器边界值
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wire [31:0] fifo_out;
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reg dmf_s_valid;
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wire dmf_tvalid_interp4_i;
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wire dmf_tvalid_interp4_q;
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wire [31:0] mf_data_interp4_i;
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wire [31:0] mf_data_interp4_q;
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wire [23:0] dmf_tdata_interp4_i;
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wire [23:0] dmf_tdata_interp4_q;
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// valid signal for dmf
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always @(posedge clk_4x) begin
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if (rst) begin
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dmf_s_valid <= 1'd0;
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end
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else if (flag_mgc_done_4x && fifo_out_valid && cnt_fifo_out_valid == cnt_fifo_out_valid_sel) begin
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// fifo_out_valid may be not trustable at the rst state
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dmf_s_valid <= 1'd1;
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end
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else begin
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dmf_s_valid <= 1'd0;
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end
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end
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always @(posedge clk_4x) begin
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if (rst) begin
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cnt_fifo_out_valid <= 3'd0;
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end
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else if (fifo_out_valid) begin
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if (cnt_fifo_out_valid == cnt_fifo_out_valid_sel) begin // refer to Receiver.v
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cnt_fifo_out_valid <= 3'd0;
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end
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else begin
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cnt_fifo_out_valid <= cnt_fifo_out_valid + 3'd1;
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end
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end
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else begin
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cnt_fifo_out_valid <= cnt_fifo_out_valid;
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end
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end
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// Match filter
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fir_match_interp4 u_fir_match_filter_interp4_i (
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.aclk (clk), // input wire aclk
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.s_axis_data_tvalid(flag_mgc_done), // input wire s_axis_data_tvalid
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.s_axis_data_tready(), // output wire s_axis_data_tready
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.s_axis_data_tdata ({4'd0, dini}), // input wire [15 : 0] s_axis_data_tdata
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.m_axis_data_tvalid(), // output wire m_axis_data_tvalid
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.m_axis_data_tdata (mf_data_interp4_i) // output wire [31 : 0] m_axis_data_tdata
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);
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fir_match_interp4 u_fir_match_filter_interp4_q (
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.aclk (clk), // input wire aclk
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.s_axis_data_tvalid(flag_mgc_done), // input wire s_axis_data_tvalid
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.s_axis_data_tready(), // output wire s_axis_data_tready
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.s_axis_data_tdata ({4'd0, dinq}), // input wire [15 : 0] s_axis_data_tdata
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.m_axis_data_tvalid(), // output wire m_axis_data_tvalid
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.m_axis_data_tdata (mf_data_interp4_q) // output wire [31 : 0] m_axis_data_tdata
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);
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// CDC into clk_4x
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fifo_shift u_fifo_shift (
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// input
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.s_aclk (clk), // input wire s_aclk
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.s_aresetn (flag_mgc_done), // input wire s_aresetn
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.s_axis_tvalid(flag_mgc_done), // input wire s_axis_tvalid
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.s_axis_tready(), // output wire s_axis_tready
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.s_axis_tdata ({8'd0, mf_data_interp4_q[29-:12], mf_data_interp4_i[29-:12]}), // input wire [31 : 0] s_axis_tdata
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// output
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.m_aclk (clk_4x), // input wire m_aclk
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.m_axis_tvalid(fifo_out_valid), // output wire m_axis_tvalid
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.m_axis_tready(1'b1), // input wire m_axis_tready
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.m_axis_tdata (fifo_out), // output wire [31 : 0] m_axis_tdata
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.wr_rst_busy (),
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.rd_rst_busy ()
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);
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fir_dmf_interp4 u_fir_dmf_interp4_i (
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.aclk (clk_4x),
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.s_axis_data_tvalid(dmf_s_valid),
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.s_axis_data_tready(),
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.s_axis_data_tdata ({4'd0, fifo_out[11:0]}),
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.m_axis_data_tvalid(dmf_tvalid_interp4_i),
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.m_axis_data_tdata (dmf_tdata_interp4_i)
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);
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fir_dmf_interp4 u_fir_dmf_interp4_q (
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.aclk (clk_4x),
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.s_axis_data_tvalid(dmf_s_valid),
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.s_axis_data_tready(),
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.s_axis_data_tdata ({4'd0, fifo_out[23:12]}),
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.m_axis_data_tvalid(dmf_tvalid_interp4_q),
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.m_axis_data_tdata (dmf_tdata_interp4_q)
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);
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wire [21:0] mag;
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wire mag_valid;
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wire frame_sync_4x;
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wire frame_sync_pulse; // in domain clk
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MagnitudeEstimator #(
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.VEC_WIDTH(21)
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) u_MagnitudeEstimator (
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.clk (clk_4x),
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.rst (rst),
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.vec_valid(dmf_tvalid_interp4_i),
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.I (dmf_tdata_interp4_i),
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.Q (dmf_tdata_interp4_q),
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.mag (mag),
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.mag_valid(mag_valid)
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);
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// frame sync threashold judgement
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PAPR #(
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.MAG_WIDTH (22),
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.WINDOW_DEPTH(1023)
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) u_PAPR (
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.clk (clk_4x),
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.rst (rst),
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.vec_mag (mag),
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.mag_valid (mag_valid),
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.frame_sync (frame_sync_4x),
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.frame_sync_pulse()
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);
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// wire [9:0] DAGC_out_i;
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// wire [9:0] DAGC_out_q;
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wire [9:0] FrameSync_douti;
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wire [9:0] FrameSync_doutq;
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wire dagc_rdy;
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wire mgc_rdy;
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wire rst_dagc;
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//帧同步模块
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assign FrameSync_dini = DAGC_out_i;
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assign FrameSync_dinq = DAGC_out_q;
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// wire framesync;
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wire Sync_rdy;
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wire Pilot_rdy;
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SCFDE_recv_FrameSync SCFDE_recv_FrameSync_inst (
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.clk (clk),
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.rst (MF_rst),
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.rst_ready (~MF_rdy),
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.datain_i (matchfilterout_i),
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.datain_q (matchfilterout_q),
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.Sync_i (FrameSync_douti),
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.Sync_q (FrameSync_doutq),
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.Sync_rdy (Sync_rdy), // 帧同步找到了过门限峰值
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.Pilot_rdy (Pilot_rdy), // 开始取导频的标志位 not used
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.flag_sync (framesync), // high level flag not used
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.Pilot_rdy_hide1_d1(Pilot_rdy_hide1_d1) // not used
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);
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//
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reg [20:0] cnt_lost;
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reg framelost;
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always @(posedge clk) begin
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if (Pilot_rdy_hide1_d1) begin
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cnt_lost <= 21'd0;
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framelost <= 1'b0;
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end
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else begin
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if (cnt_lost >= 21'd750000) begin
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cnt_lost <= 21'd0;
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framelost <= 1'b1;
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end
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else begin
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cnt_lost <= 21'd1 + cnt_lost;
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framelost <= 1'b0;
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end
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end
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end
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DAGC_v2 DAGC_v2 (
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.clk (clk),
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.rst (~mgc1_rdy),
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.mgc1_rdy (MF_rdy),
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.framesync_d0 (framesync),
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.vio_powertest_h (2'b00),
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.vio_powertest_l (2'b00),
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.matchfilterout_i(FrameSync_douti), // input,
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.matchfilterout_q(FrameSync_doutq), // input
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.DAGC_out_i(DAGC_out_i), // output
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.DAGC_out_q(DAGC_out_q), // output
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.flag_agch (flag_agch),
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.flag_agcl (flag_agcl),
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.flag_agc_power(flag_agc_power),
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.agc_ref (agc_ref),
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.agc_check (agc_check),
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.dagc_rdy (dagc_rdy),
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.mgc_rdy (mgc_rdy),
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.rst_dagc (rst_dagc)
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);
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//载波频偏补偿
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// wire [9:0] freqdataout_i;
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// wire [9:0] freqdataout_q;
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// wire framesync_delay;
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wire data_save; //debug用，暂不需使用
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// wire rst_freq;
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freqestm freqestm (
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.clk (clk),
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.rst (MF_rst),
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.mgc_rdy (mgc_rdy),
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.framesync (dagc_rdy),
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.datain_i (DAGC_out_i),
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.datain_q (DAGC_out_q),
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.dataout_i (freqdataout_i),
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.dataout_q (freqdataout_q),
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.framesync_delay(framesync_delay),
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.data_save (data_save),
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.rst_freq (rst_freq)
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);
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//位同步
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wire [1:0] cnt_tsync;
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// wire framesync_tsync; //帧同步标志
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TimeSync_top TimeSync_top (
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.clk (clk),
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.rst (Pilot_rdy_hide1_d1),
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.dini (freqdataout_i),
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.dinq (freqdataout_q),
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.rdy (IntpARdy),
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.douti (IntpOuti),
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.doutq (IntpOutq),
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.vio_tsync_inter16(vio_tsync_inter16),
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.framesync (framesync_delay), //帧同步标志
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.framesync_tsync (framesync_tsync), //帧同步标志
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//debug
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.cnt_tsync (cnt_tsync),
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.flag_clk_4bit (flag_clk_4bit)
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);
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// SC-FDE
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SC_FDE_TOP SC_FDE_TOP_djy (
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.clk(clk),
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.rst(Pilot_rdy_hide1_d1),
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.EQUenable_vio(EQUenable_vio), //为1时启用均衡
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.Zerozone_vio (Zerozone_vio), //零域估计，默认值为8'd29
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.flag_ow_left (framesync_tsync), //在一帧内，与第一个数据段的pilot的ow第一个nd对齐
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.nd (IntpARdy),
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.dini (IntpOuti),
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.dinq (IntpOutq),
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.nd_SC_FDE_dout (nd_SC_FDE_dout),
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.SC_FDE_douti (SC_FDE_douti),
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.SC_FDE_doutq (SC_FDE_doutq),
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// debug,溢出标志
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.flagoverflow_fftpilot_26to14 (flagoverflow_fftpilot_26to14),
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.flagoverflow_ChnZF_26to18 (flagoverflow_ChnZF_26to18),
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.flagoverflow_comdiv_34to20i (flagoverflow_comdiv_34to20i),
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.flagoverflow_comdiv_34to20q (flagoverflow_comdiv_34to20q),
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.flagoverflow_ifftzero_29to17i (flagoverflow_ifftzero_29to17i),
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.flagoverflow_ifftzero_29to17q (flagoverflow_ifftzero_29to17q),
|
|
.flagoverflow_MMSEdiv_divisor_31to28(flagoverflow_MMSEdiv_divisor_31to28),
|
|
.flagoverflow_divmmse_34to11 (flagoverflow_divmmse_34to11),
|
|
.flagoverflow_ifftindata_28to20i (flagoverflow_ifftindata_28to20i),
|
|
.flagoverflow_ifftindata_28to20q (flagoverflow_ifftindata_28to20q),
|
|
.flagoverflow_fftdata_26to16i (flagoverflow_fftdata_26to16i),
|
|
.flagoverflow_fftdata_26to16q (flagoverflow_fftdata_26to16q),
|
|
.flagoverflow_FDE_dataout_29to10i (flagoverflow_FDE_dataout_29to10i),
|
|
.flagoverflow_FDE_dataout_29to10q (flagoverflow_FDE_dataout_29to10q)
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|
);
|
|
|
|
|
|
wire phase_adjust_rdy;
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|
wire [9:0] phase_adjust_douti;
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|
wire [9:0] phase_adjust_doutq;
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|
phase_adjust phase_adjust (
|
|
.clk (clk),
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|
.rst (Pilot_rdy_hide1_d1),
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|
.din_i (SC_FDE_douti),
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|
.din_q (SC_FDE_doutq),
|
|
.nd (nd_SC_FDE_dout),
|
|
.framesync(framesync_tsync),
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|
.rdy (phase_adjust_rdy),
|
|
.dout_i (phase_adjust_douti),
|
|
.dout_q (phase_adjust_doutq)
|
|
);
|
|
|
|
wire IQmergerdy;
|
|
wire ldpcsyncin;
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|
wire [7:0] IQmergedout;
|
|
|
|
IQmerge IQmerge (
|
|
.clk (clk),
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|
.clk2 (clk2),
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|
.rst (rst2 || Pilot_rdy_hide1_d1),
|
|
.nd (phase_adjust_rdy),
|
|
.framesync (framesync_tsync),
|
|
.dini (phase_adjust_douti),
|
|
.dinq (phase_adjust_doutq),
|
|
.rdy (IQmergerdy),
|
|
.ldpcsyncin(ldpcsyncin),
|
|
.dout (IQmergedout)
|
|
);
|
|
|
|
wire LDPC_SyncOut;
|
|
wire LDPC_Rdy;
|
|
wire LDPC_Dout;
|
|
wire [8:0] good_frames;
|
|
wire [8:0] bad_frames;
|
|
wire [8:0] total_frames;
|
|
CCSDS_LDPC_DEC_K1024_R12_TOPP LDPC_decode (
|
|
.clk (clk2),
|
|
.Rst (rst2 || Pilot_rdy_hide1_d1),
|
|
.FrameSync (ldpcsyncin),
|
|
.Nd (IQmergerdy),
|
|
.Din (IQmergedout),
|
|
.LDPC_SyncOut(LDPC_SyncOut),
|
|
.Rdy (LDPC_Rdy),
|
|
.LDPC_Dout (LDPC_Dout),
|
|
.good_frames (good_frames),
|
|
.bad_frames (bad_frames),
|
|
.total_frames(total_frames)
|
|
);
|
|
|
|
|
|
|
|
|
|
|
|
wire flag_notbyte; //为1时说明得到的有效数据不以字节为单位
|
|
wire [ 1:0] state_ram;
|
|
wire berstart_1d;
|
|
wire bercompare;
|
|
wire [16:0] bercount;
|
|
wire [16:0] bercount_max;
|
|
wire [16:0] ROMaddra_d2;
|
|
wire RAMdout_d1;
|
|
wire validnd_new_new;
|
|
wire [63:0] stop_temp_new;
|
|
wire flag_stop_0; //给shx，拉高1个clk表示当前时帧有效数据接收完毕
|
|
wire [16:0] addr_stop_0;
|
|
wire [ 2:0] cnt_8;
|
|
wire state_8;
|
|
wire rdy_scramble;
|
|
wire dout_scramble;
|
|
wire [16:0] RAMaddra; //比较误码率
|
|
wire [16:0] ROMaddra; //比较误码率
|
|
wire nd_ber;
|
|
|
|
FrameMerge FrameMerge (
|
|
.clk (clk2),
|
|
.rst (Pilot_rdy_hide1_d1),
|
|
.rst2(rst2),
|
|
.sync(LDPC_SyncOut),
|
|
.nd (LDPC_Rdy),
|
|
.din (LDPC_Dout),
|
|
|
|
.vio_stopbit(vio_stopbit),
|
|
|
|
.frameIDnd(Pilot_rdy_hide1_d1),
|
|
.clk2 (clk_60M_mac),
|
|
.framerdy (framerdy),
|
|
|
|
.recv_addr_new_0 (recv_addr_new_0),
|
|
.recv_addr_new_1 (recv_addr_new_1),
|
|
.recv_addr_new_2 (recv_addr_new_2),
|
|
.recv_addr_new_3 (recv_addr_new_3),
|
|
.recv_data_new_0 (recv_data_new_0),
|
|
.recv_data_new_1 (recv_data_new_1),
|
|
.recv_data_new_2 (recv_data_new_2),
|
|
.recv_data_new_3 (recv_data_new_3),
|
|
.RAMaddra_write_0(RAMaddra_write_0),
|
|
.RAMaddra_write_1(RAMaddra_write_1),
|
|
.RAMaddra_write_2(RAMaddra_write_2),
|
|
.RAMaddra_write_3(RAMaddra_write_3),
|
|
.RAMaddra_new_0 (RAMaddra_new_0),
|
|
.RAMaddra_new_1 (RAMaddra_new_1),
|
|
.RAMaddra_new_2 (RAMaddra_new_2),
|
|
.RAMaddra_new_3 (RAMaddra_new_3),
|
|
|
|
.flag_notbyte(flag_notbyte),
|
|
.state_ram (state_ram),
|
|
.flag_stop (flag_stop), //给shx，拉高8个clk表示当前时帧有效数据接收完毕
|
|
.addr_stop (addr_stop), //给shx，拉高8个clk,与flag_stop对齐，指示位置与最后1bit有效数据的位置对齐
|
|
//debug
|
|
.berstart_1d (berstart_1d),
|
|
.bercompare (bercompare),
|
|
.bercount (bercount),
|
|
.bercount_max(bercount_max),
|
|
.ROMaddra_d2 (ROMaddra_d2),
|
|
.RAMdout_d1 (RAMdout_d1),
|
|
|
|
.validnd_new_new(validnd_new_new),
|
|
|
|
.stop_temp_new(stop_temp_new),
|
|
|
|
.flag_stop_0(flag_stop_0),
|
|
.addr_stop_0(addr_stop_0),
|
|
.cnt_8 (cnt_8),
|
|
.state_8 (state_8),
|
|
|
|
.rdy_scramble (rdy_scramble),
|
|
.dout_scramble(dout_scramble),
|
|
|
|
.RAMaddra (RAMaddra),
|
|
.ROMaddra (ROMaddra),
|
|
.nd_ber (nd_ber),
|
|
.recvNetData (recvNetData),
|
|
.recvNetDataNd(recvNetDataNd)
|
|
);
|
|
|
|
|
|
// **** cdc ****
|
|
xpm_cdc_single #(
|
|
.DEST_SYNC_FF (2), // DECIMAL; range: 2-10
|
|
.INIT_SYNC_FF (1), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values
|
|
.SIM_ASSERT_CHK(1), // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
|
|
.SRC_INPUT_REG (1) // DECIMAL; 0=do not register input, 1=register input
|
|
) xpm_cdc_startup_inst (
|
|
.dest_out(flag_mgc_done_4x), // 1-bit output: src_in synchronized to the destination clock domain. This output is
|
|
// registered.
|
|
.dest_clk(clk_4x), // 1-bit input: Clock signal for the destination clock domain.
|
|
.src_clk (clk), // 1-bit input: optional; required when SRC_INPUT_REG = 1
|
|
.src_in (flag_mgc_done) // 1-bit input: Input signal to be synchronized to dest_clk domain.
|
|
);
|
|
|
|
xpm_cdc_pulse #(
|
|
.DEST_SYNC_FF (4), // DECIMAL; range: 2-10
|
|
.INIT_SYNC_FF (0), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values
|
|
.REG_OUTPUT (0), // DECIMAL; 0=disable registered output, 1=enable registered output
|
|
.RST_USED (0), // DECIMAL; 0=no reset, 1=implement reset
|
|
.SIM_ASSERT_CHK(1) // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
|
|
) xpm_cdc_frame_sync_pulse_inst (
|
|
.dest_pulse(frame_sync_pulse), // 1-bit output: Outputs a pulse the size of one dest_clk period when a pulse
|
|
// transfer is correctly initiated on src_pulse input. This output is
|
|
// combinatorial unless REG_OUTPUT is set to 1.
|
|
.dest_clk (clk), // 1-bit input: Destination clock.
|
|
.dest_rst (), // 1-bit input: optional; required when RST_USED = 1
|
|
.src_clk (clk_4x), // 1-bit input: Source clock.
|
|
.src_pulse (frame_sync_4x), // 1-bit input: Rising edge of this signal initiates a pulse transfer to the
|
|
// destination clock domain. The minimum gap between each pulse transfer must be
|
|
// at the minimum 2*(larger(src_clk period, dest_clk period)). This is measured
|
|
// between the falling edge of a src_pulse to the rising edge of the next
|
|
// src_pulse. This minimum gap will guarantee that each rising edge of src_pulse
|
|
// will generate a pulse the size of one dest_clk period in the destination
|
|
// clock domain. When RST_USED = 1, pulse transfers will not be guaranteed while
|
|
// src_rst and/or dest_rst are asserted.
|
|
.src_rst () // 1-bit input: optional; required when RST_USED = 1
|
|
);
|
|
|
|
|
|
|
|
endmodule
|