576 lines
18 KiB
Verilog
576 lines
18 KiB
Verilog
`timescale 1ns / 1ns
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// * Engineer:
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// * *************************************************** *
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// * ███████╗ ██████╗ ██████╗ ██████╗ ██████╗ ██╗ ██╗ *
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// * ╚══███╔╝██╔═══██╗██╔══██╗██╔═══██╗██╔════╝ ██║ ██║ *
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// * ███╔╝ ██║ ██║██████╔╝██║ ██║██║ ███╗███████║ *
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// * ███╔╝ ██║ ██║██╔══██╗██║ ██║██║ ██║██╔══██║ *
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// * ███████╗╚██████╔╝██║ ██║╚██████╔╝╚██████╔╝██║ ██║ *
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// * ╚══════╝ ╚═════╝ ╚═╝ ╚═╝ ╚═════╝ ╚═════╝ ╚═╝ ╚═╝ *
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// * *************************************************** *
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// * Create Date: 2023/12/18
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// * Update Date: 2024/07/24
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// NOTE: 接口中的hop_wait和参数GAP_LEN均是为了等待，hop是为了跳频切换，gap是为了满足帧同步延迟,！！！将hop_wait设置为0并不能去掉改状态
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module Transmitter #(
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parameter AGC_HEADER_LEN = 10586,
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parameter FRAME_HEADER_LEN = 512,
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parameter BLOCK_NUM = 42,
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parameter PHASE1_LEN = 2880, // (32 cp + 256 sym)* 10 ( total 2880 valid sym)
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parameter PREFIX_LEN = 32,
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parameter CHU_SEQ_LEN = 256,
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parameter GAP_LEN = 160
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) (
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// general
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input wire clk,
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input wire rst,
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// control
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input wire [ 2:0] speed_mode,
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input wire send_data_ready,
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input wire send_start,
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output reg send_over,
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// data
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// source data from others
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output wire clk_data_src,
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input wire [31:0] tx_data_src_tdata,
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output reg tx_data_src_tready,
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input wire tx_data_src_tvalid,
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output reg [ 3:0] hopping_freq,
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output wire [11:0] ad9361_tx_data_i,
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output wire [11:0] ad9361_tx_data_q,
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input wire test,
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// param from ps
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input wire [15:0] hop_wait // this is the gap between 2 blocks freq (unit in clk period)
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);
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// ******** Wire & Reg ********
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reg [15:0] cnt_agc_send; // agc symbols have been sent
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reg [15:0] cnt_sym_send; // symbols have been sent
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reg [15:0] cnt_blocks_send; // blocks have been sent
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reg [15:0] cnt_wait; // wait cnt max 65535 period, 50M -> 1.3ms
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reg [15:0] cnt_chu_send;
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// fsm
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reg [ 3:0] cs;
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reg [ 3:0] ns;
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localparam [3:0] S_IDLE = 4'd0;
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localparam [3:0] S_SEND_AGC = 4'd1;
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localparam [3:0] S_SEND_FRAME_HEADER = 4'd2;
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localparam [3:0] S_SEND_CHU_POS = 4'd8;
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localparam [3:0] S_SEND_CHU_NEG = 4'd9;
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localparam [3:0] S_SEND_PHASE1 = 4'd3;
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localparam [3:0] S_WAIT_HOP = 4'd5;
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localparam [3:0] S_WAIT_GAP = 4'd6; // wait for freq switch
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localparam [3:0] S_TEST = 4'd7;
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reg [ 3:0] interp;
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reg [ 3:0] cnt_interp;
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reg [13:0] agc_addr;
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wire [ 1:0] agc_data;
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reg [ 8:0] mseqs_addr;
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reg [ 8:0] mseqs_addr_d1;
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reg [ 8:0] mseqs_addr_d2;
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reg [ 7:0] chu_seq_addr = 0;
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wire [31:0] chu_seq;
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wire mseqs;
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reg [31:0] bb_wave_out_i; // shape filter result
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reg [31:0] bb_wave_out_q; // shape filter result
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wire [31:0] bb_wave_out_i_interp16;
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wire [31:0] bb_wave_out_q_interp16;
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wire [31:0] bb_wave_out_i_interp8;
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wire [31:0] bb_wave_out_q_interp8;
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wire [31:0] bb_wave_out_i_interp4;
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wire [31:0] bb_wave_out_q_interp4;
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wire fir_tvalid_in; // shape filter input valid
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wire hand_shake; // not used
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reg [15:0] m_fir_tdata_i;
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reg [15:0] m_fir_tdata_q;
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reg [ 3:0] rtz; // return to zero
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reg [12:0] addr_tx_test = 'd0;
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wire [ 7:0] data_tx_test;
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// ******** Assingment ********
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assign clk_data_src = clk;
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assign fir_tvalid_in = (cnt_interp == interp);
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assign hand_shake = tx_data_src_tvalid && tx_data_src_tready; // not used
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assign ad9361_tx_data_i = bb_wave_out_i[31-:12];
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assign ad9361_tx_data_q = bb_wave_out_q[31-:12];
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// ******** Logic Block ********
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// fsm
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always @(posedge clk) begin
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if (rst) begin
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cs <= S_IDLE;
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end
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else begin
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cs <= ns;
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end
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end
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// state transition
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always @(*) begin
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case (cs)
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S_IDLE: begin
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if (send_start) begin
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ns = S_SEND_AGC;
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end
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else if (test) begin
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ns = S_TEST;
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end
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else begin
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ns = S_IDLE;
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end
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end
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S_SEND_AGC: begin
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if (cnt_sym_send == AGC_HEADER_LEN - 1 && fir_tvalid_in) begin
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ns = S_SEND_FRAME_HEADER;
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end
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else begin
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ns = S_SEND_AGC;
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end
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end
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S_SEND_FRAME_HEADER: begin
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if (cnt_sym_send == FRAME_HEADER_LEN - 1 && fir_tvalid_in) begin
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`ifdef TX_FRAME_WITH_GAP
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ns = S_WAIT_GAP;
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`else
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ns = S_SEND_CHU_POS;
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`endif
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end
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else begin
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ns = S_SEND_FRAME_HEADER;
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end
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end
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S_WAIT_GAP: begin
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if (cnt_wait == GAP_LEN - 1) begin
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ns = S_SEND_CHU_POS;
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end
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else begin
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ns = S_WAIT_GAP;
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end
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end
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S_SEND_CHU_POS: begin
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if (cnt_chu_send == CHU_SEQ_LEN + PREFIX_LEN - 1 && fir_tvalid_in) begin
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ns = S_SEND_CHU_NEG;
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end
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else begin
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ns = S_SEND_CHU_POS;
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end
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end
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S_SEND_CHU_NEG: begin
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if (cnt_chu_send == CHU_SEQ_LEN + PREFIX_LEN - 1 && fir_tvalid_in) begin
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ns = S_SEND_PHASE1;
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end
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else begin
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ns = S_SEND_CHU_NEG;
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end
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end
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S_SEND_PHASE1: begin
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if (cnt_sym_send == PHASE1_LEN - 1 && fir_tvalid_in) begin
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// send block num - 1 and send the final block
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if (cnt_blocks_send == BLOCK_NUM) begin
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ns = S_IDLE;
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end
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else begin
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`ifdef TX_FRAME_WITH_GAP
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ns = S_WAIT_HOP;
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`else
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ns = S_SEND_CHU_POS;
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`endif
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end
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end
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else begin
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ns = S_SEND_PHASE1;
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end
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end
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S_WAIT_HOP: begin
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if (cnt_wait == hop_wait - 1) begin
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ns = S_SEND_CHU_POS;
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end
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else begin
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ns = S_WAIT_HOP;
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end
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end
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S_TEST: begin
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if (~test) begin
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ns = S_IDLE;
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end
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else begin
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ns = S_TEST;
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end
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end
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default: begin
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ns = S_IDLE;
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end
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endcase
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end
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// speed mode select
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always @(*) begin
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case (speed_mode)
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3'd0: begin
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interp = 4'd15; // 16
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bb_wave_out_i = bb_wave_out_i_interp16;
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bb_wave_out_q = bb_wave_out_q_interp16;
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end
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3'd1: begin
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interp = 4'd7; // 8
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bb_wave_out_i = bb_wave_out_i_interp8;
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bb_wave_out_q = bb_wave_out_q_interp8;
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end
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3'd2: begin
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interp = 4'd3; // 4
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bb_wave_out_i = bb_wave_out_i_interp4;
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bb_wave_out_q = bb_wave_out_q_interp4;
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end
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// 3'd3: begin
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// interp = 4'd1; // 2
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// end
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default: begin
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interp = 4'd15;
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bb_wave_out_i = bb_wave_out_i_interp16;
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bb_wave_out_q = bb_wave_out_q_interp16;
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end
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endcase
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end
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// tx_data_src_tready for handshake
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always @(posedge clk) begin
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if (rst) begin
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tx_data_src_tready <= 1'd0;
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end
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// only when the phase 1 state , the transmitter will receive the data from outside(axis protocal)
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else if (cs == S_SEND_PHASE1) begin
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if (!tx_data_src_tready && tx_data_src_tvalid) begin // no handshake
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if (fir_tvalid_in) begin
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tx_data_src_tready <= 1'd1;
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end
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end
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else begin
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tx_data_src_tready <= 1'd0;
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end
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end
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else begin
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tx_data_src_tready <= 1'd0;
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end
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end
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// interpolation counter
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always @(posedge clk) begin
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if (rst) begin
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cnt_interp <= 4'd0;
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end
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else if (cs == S_IDLE && rtz == 4'd0) begin
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cnt_interp <= 4'd0;
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end
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else if (cs == S_SEND_AGC || cs == S_SEND_FRAME_HEADER || cs == S_SEND_PHASE1 || cs == S_SEND_CHU_POS || cs == S_SEND_CHU_NEG || cs == S_TEST || rtz > 4'd0) begin
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if (cnt_interp < interp) begin
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cnt_interp <= cnt_interp + 4'd1;
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end
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else begin
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cnt_interp <= 4'd0;
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end
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end
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else begin
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cnt_interp <= 4'd0;
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end
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end
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// return to zero
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always @(posedge clk) begin
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if (rst) begin
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rtz <= 4'd0;
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end
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else if (cs == S_SEND_AGC || cs == S_SEND_FRAME_HEADER || cs == S_SEND_PHASE1 || cs == S_SEND_CHU_POS || cs == S_SEND_CHU_NEG || cs == S_TEST) begin
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if (ns == S_WAIT_HOP || ns == S_WAIT_GAP || ns == S_IDLE) begin
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rtz <= 4'd1;
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end
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else begin
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rtz <= 4'd0;
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end
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end
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else if (fir_tvalid_in) begin
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if (rtz == 4'd7) begin
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rtz <= 4'd0;
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end
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else begin
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rtz <= rtz + 4'd1;
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end
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end
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end
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//cnt_sym_send
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always @(posedge clk) begin
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if (rst || ns != cs) begin
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cnt_sym_send <= 16'd0;
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end
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else if (cs == S_SEND_AGC || cs == S_SEND_FRAME_HEADER || cs == S_SEND_PHASE1 || cs == S_TEST) begin
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if (fir_tvalid_in) begin
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cnt_sym_send <= cnt_sym_send + 16'd1;
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end
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else begin
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cnt_sym_send <= cnt_sym_send;
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end
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end
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else begin
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cnt_sym_send <= 16'd0;
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end
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end
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// truncation
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always @(*) begin
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if (cs == S_SEND_AGC) begin
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m_fir_tdata_i = agc_data[0] ? 16'h8001 : 16'h7FFF;
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m_fir_tdata_q = agc_data[1] ? 16'h8001 : 16'h7FFF;
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end
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else if (cs == S_SEND_FRAME_HEADER) begin
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m_fir_tdata_i = mseqs ? 16'h8001 : 16'h7FFF;
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m_fir_tdata_q = mseqs ? 16'h8001 : 16'h7FFF;
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end
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else if (cs == S_SEND_PHASE1) begin
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m_fir_tdata_i = tx_data_src_tdata[15-:16];
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m_fir_tdata_q = tx_data_src_tdata[31-:16];
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end
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else if (cs == S_SEND_CHU_POS) begin
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m_fir_tdata_i = chu_seq[15-:16];
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m_fir_tdata_q = chu_seq[31-:16];
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end
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else if (cs == S_SEND_CHU_NEG) begin
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m_fir_tdata_i = -chu_seq[15-:16];
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m_fir_tdata_q = -chu_seq[31-:16];
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end
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else if (cs == S_TEST) begin
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m_fir_tdata_i = {data_tx_test[3:0], 12'b0};
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m_fir_tdata_q = {data_tx_test[7:4], 12'b0};
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end
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else begin
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m_fir_tdata_i = 16'd0;
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m_fir_tdata_q = 16'd0;
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end
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end
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// count the block have been sent
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always @(posedge clk) begin
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if (rst) begin
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cnt_blocks_send <= 4'd0;
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end
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else if (cs != S_SEND_PHASE1 && ns == S_SEND_PHASE1) begin
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cnt_blocks_send <= cnt_blocks_send + 4'd1;
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end
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else if (cs == S_IDLE) begin
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cnt_blocks_send <= 4'd0;
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end
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end
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// S_WAIT_HOP && S_WAIT_GAP
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always @(posedge clk) begin
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if (rst) begin
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cnt_wait <= 16'd0;
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end
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else if (cs == S_WAIT_HOP) begin
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if (cnt_wait == hop_wait) begin
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cnt_wait <= 1'd0;
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end
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else begin
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cnt_wait <= cnt_wait + 16'd1;
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end
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end
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else if (cs == S_WAIT_GAP) begin
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if (cnt_wait == GAP_LEN - 1) begin
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cnt_wait <= 1'd0;
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end
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else begin
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cnt_wait <= cnt_wait + 16'd1;
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end
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end
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else begin
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cnt_wait <= 16'd0;
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end
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end
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always @(posedge clk) begin
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if (cs == S_SEND_PHASE1 && ns == S_IDLE) begin
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send_over <= 1'd1;
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end
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else begin
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send_over <= 1'd0;
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end
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end
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// m seq addr control
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always @(posedge clk) begin
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mseqs_addr_d1 <= mseqs_addr;
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mseqs_addr_d2 <= mseqs_addr_d1;
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if (cs == S_IDLE) begin
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mseqs_addr <= 1'd0;
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end
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else if (cs == S_SEND_FRAME_HEADER || cs == S_TEST) begin
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if (fir_tvalid_in == 1'b1) begin
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mseqs_addr <= mseqs_addr + 9'd1;
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end
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end
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end
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// chu seq addr control
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always @(posedge clk) begin
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if (cs == S_IDLE) begin
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agc_addr <= 0;
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end
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else if (cs == S_SEND_AGC) begin
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if (fir_tvalid_in == 1'b1) begin
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agc_addr <= agc_addr + 1;
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end
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end
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end
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// chu seq addr control
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always @(posedge clk) begin
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if (ns != cs) begin
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// chu_seq_addr <= 7'h7F - 7'h7; // 8 cp
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chu_seq_addr <= CHU_SEQ_LEN - PREFIX_LEN; // 32 cp
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end
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else if (cs == S_SEND_CHU_POS || cs == S_SEND_AGC || cs == S_SEND_CHU_NEG) begin
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if (fir_tvalid_in == 1'b1) begin
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chu_seq_addr <= chu_seq_addr + 9'd1;
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end
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end
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end
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always @(posedge clk) begin
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if (cs != ns) begin
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cnt_chu_send <= 0;
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end
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else if (cs == S_SEND_CHU_POS || cs == S_SEND_CHU_NEG) begin
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if (fir_tvalid_in) begin
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cnt_chu_send <= cnt_chu_send + 1;
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end
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else begin
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cnt_chu_send <= cnt_chu_send;
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end
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end
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else begin
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cnt_chu_send <= 0;
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end
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end
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always @(posedge clk) begin
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if (fir_tvalid_in) begin
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addr_tx_test <= addr_tx_test + 1;
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end
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end
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// ******** Inst ********
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bram_agc_header u_bram_agc_header (
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.clka (clk), // input wire clka
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.addra(agc_addr), // input wire [13 : 0] addra
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.douta(agc_data) // output wire [1 : 0] douta
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);
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bram_m_seqs_512 u_bram_m_seqs_512 (
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.clka (clk),
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.addra(mseqs_addr),
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.douta(mseqs)
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);
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bram_chu_seq u_bram_chu_seq (
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.clka (clk), // input wire clka
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.addra(chu_seq_addr), // input wire [7 : 0] addra
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.douta(chu_seq) // output wire [31 : 0] douta
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);
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bram_tx_test u_bram_tx_test (
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.clka (clk), // input wire clka
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.addra(addr_tx_test), // input wire [17 : 0] addra
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.douta(data_tx_test) // output wire [31 : 0] douta
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);
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// fir i & q
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fir_shape_interp16 u_fir_shape_interp16_i (
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.aclk (clk), // input wire aclk
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.s_axis_data_tvalid(fir_tvalid_in), // input wire s_axis_data_tvalid
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.s_axis_data_tready(), // output wire s_axis_data_tready
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.s_axis_data_tdata (m_fir_tdata_i), // input wire [15 : 0] s_axis_data_tdata
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.m_axis_data_tvalid(), // output wire m_axis_data_tvalid
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.m_axis_data_tdata (bb_wave_out_i_interp16) // output wire [31 : 0] m_axis_data_tdata
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);
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fir_shape_interp16 u_fir_shape_interp16_q (
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.aclk (clk),
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.s_axis_data_tvalid(fir_tvalid_in),
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.s_axis_data_tready(),
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.s_axis_data_tdata (m_fir_tdata_q),
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|
.m_axis_data_tvalid(),
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.m_axis_data_tdata (bb_wave_out_q_interp16)
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);
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// fir_shape_interp8 u_fir_shape_interp8_i (
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// .aclk (clk),
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// .s_axis_data_tvalid(fir_tvalid_in),
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// .s_axis_data_tready(),
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// .s_axis_data_tdata (m_fir_tdata_i),
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// .m_axis_data_tvalid(),
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// .m_axis_data_tdata (bb_wave_out_i_interp8)
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// );
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|
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// fir_shape_interp8 u_fir_shape_interp8_q (
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// .aclk (clk),
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// .s_axis_data_tvalid(fir_tvalid_in),
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// .s_axis_data_tready(),
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// .s_axis_data_tdata (m_fir_tdata_q),
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// .m_axis_data_tvalid(),
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// .m_axis_data_tdata (bb_wave_out_q_interp8)
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// );
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|
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// fir_shape_interp4 u_fir_shape_interp4_i (
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// .aclk (clk),
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|
// .s_axis_data_tvalid(fir_tvalid_in),
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|
// .s_axis_data_tready(),
|
|
// .s_axis_data_tdata (m_fir_tdata_i),
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|
// .m_axis_data_tvalid(),
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// .m_axis_data_tdata (bb_wave_out_i_interp4)
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|
// );
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|
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// fir_shape_interp4 u_fir_shape_interp4_q (
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|
// .aclk (clk),
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|
// .s_axis_data_tvalid(fir_tvalid_in),
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|
// .s_axis_data_tready(),
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|
// .s_axis_data_tdata (m_fir_tdata_q),
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|
// .m_axis_data_tvalid(),
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|
// .m_axis_data_tdata (bb_wave_out_q_interp4)
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|
// );
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|
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|
|
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// ******** Debug ********
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|
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|
// ila_transmitter u_ila_transmitter (
|
|
// .clk (clk), // input wire clk
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|
// .probe0(cnt_sym_send), // input wire [15:0] probe0
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|
// .probe1(cs), // input wire [3:0] probe1
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|
// .probe2(ns), // input wire [3:0] probe2
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|
// .probe3(send_data_ready), // input wire [0:0] probe3
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|
// .probe4(send_start), // input wire [0:0] probe4
|
|
// .probe5(tx_data_src_tvalid) // input wire [0:0] probe5
|
|
// );
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|
|
|
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endmodule
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