194 lines
8.0 KiB
Verilog
194 lines
8.0 KiB
Verilog
`timescale 1ns / 1ns
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2019/11/18 23:18:07
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// Design Name:
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// Module Name: LDPC_TopManage_2
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module LDPC_TopManage_2 #(
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parameter WIDTH = 4'd8
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) (
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input clk, //工作时钟,100MHz
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input Rst, //同步复位信号,高有效
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input FrameSync_TM, //帧同步标志,高脉冲
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input Nd_TM, //译码输入数据有效标志,高有效
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input [WIDTH-1:0] Din_TM, //译码输入数据,软信息
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//A
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output FrameSync_A_TM, //帧同步标志,高脉冲
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output Nd_A_TM, //译码输入数据有效标志,高有效
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output [WIDTH-1:0] Din_A_TM, //译码输入数据,软信息
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//B
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output FrameSync_B_TM, //帧同步标志,高脉冲
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output Nd_B_TM, //译码输入数据有效标志,高有效
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output [WIDTH-1:0] Din_B_TM, //译码输入数据,软信息
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// flag A
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input LDPC_SyncOut_A_TM, //LDPC 模块帧同步输出信号,高脉冲,指示帧起点
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input Rdy_A_TM, //译码输出信号有效标志,高有效
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input [ 0:0] LDPC_Dout_A_TM, //译码输出信号
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input [ 8:0] good_frames_A_TM, //译码好帧计数
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input [ 8:0] bad_frames_A_TM, //译码坏帧计数
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input [ 8:0] total_frames_A_TM, //译码总帧数计数
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//flag B
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input LDPC_SyncOut_B_TM, //LDPC 模块帧同步输出信号,高脉冲,指示帧起点
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input Rdy_B_TM, //译码输出信号有效标志,高有效
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input [ 0:0] LDPC_Dout_B_TM, //译码输出信号
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input [ 8:0] good_frames_B_TM, //译码好帧计数
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input [ 8:0] bad_frames_B_TM, //译码坏帧计数
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input [ 8:0] total_frames_B_TM, //译码总帧数计数
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//result
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output LDPC_SyncOut_TM, //LDPC 模块帧同步输出信号,高脉冲,指示帧起点
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output Rdy_TM, //译码输出信号有效标志,高有效
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output [ 0:0] LDPC_Dout_TM, //译码输出信号
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output [ 8:0] good_frames_TM, //译码好帧计数
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output [ 8:0] bad_frames_TM, //译码坏帧计数
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output [ 8:0] total_frames_TM //译码总帧数计数
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);
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reg FrameSync_TM_reg0, FrameSync_TM_reg1;
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reg Nd_TM_reg0, Nd_TM_reg1;
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reg [WIDTH-1:0] Din_TM_reg0, Din_TM_reg1;
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//******输入过程控制
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always @(posedge clk) begin //接收数据缓存过程
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FrameSync_TM_reg0 <= FrameSync_TM;
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FrameSync_TM_reg1 <= FrameSync_TM_reg0;
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Nd_TM_reg0 <= Nd_TM;
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Nd_TM_reg1 <= Nd_TM_reg0;
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Din_TM_reg0 <= Din_TM;
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Din_TM_reg1 <= Din_TM_reg0;
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end
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reg [0:0] flag_switch_in = 1'b1;
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always @(posedge clk) begin //输入乒乓控制过程
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if (Rst) begin
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flag_switch_in <= 1'd1;
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end
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else begin
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if (FrameSync_TM) begin
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flag_switch_in <= ~flag_switch_in;
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end
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else flag_switch_in <= flag_switch_in;
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end
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end
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assign FrameSync_A_TM = (flag_switch_in == 1'b0) ? FrameSync_TM_reg1 : 1'b0;
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assign Nd_A_TM = (flag_switch_in == 1'b0) ? Nd_TM_reg1 : 1'b0;
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assign Din_A_TM = (flag_switch_in == 1'b0) ? Din_TM_reg1 : 8'd0;
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assign FrameSync_B_TM = (flag_switch_in == 1'b1) ? FrameSync_TM_reg1 : 1'b0;
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assign Nd_B_TM = (flag_switch_in == 1'b1) ? Nd_TM_reg1 : 1'b0;
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assign Din_B_TM = (flag_switch_in == 1'b1) ? Din_TM_reg1 : 8'd0;
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reg LDPC_SyncOut_A_TM_reg0, LDPC_SyncOut_A_TM_reg1;
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reg Rdy_A_TM_reg0, Rdy_A_TM_reg1;
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reg [0:0] LDPC_Dout_A_TM_reg0, LDPC_Dout_A_TM_reg1;
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reg [8:0] good_frames_A_TM_reg0, good_frames_A_TM_reg1;
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reg [8:0] bad_frames_A_TM_reg0, bad_frames_A_TM_reg1;
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reg [8:0] total_frames_A_TM_reg0, total_frames_A_TM_reg1;
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reg LDPC_SyncOut_B_TM_reg0, LDPC_SyncOut_B_TM_reg1;
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reg Rdy_B_TM_reg0, Rdy_B_TM_reg1;
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reg [0:0] LDPC_Dout_B_TM_reg0, LDPC_Dout_B_TM_reg1;
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reg [8:0] good_frames_B_TM_reg0, good_frames_B_TM_reg1;
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reg [8:0] bad_frames_B_TM_reg0, bad_frames_B_TM_reg1;
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reg [8:0] total_frames_B_TM_reg0, total_frames_B_TM_reg1;
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//******输入过程控制
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always @(posedge clk) begin //输出数据缓存过程
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if (Rst) begin
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LDPC_SyncOut_A_TM_reg0 <= 1'b0;
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LDPC_SyncOut_A_TM_reg1 <= 1'b0;
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Rdy_A_TM_reg0 <= 1'b0;
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Rdy_A_TM_reg1 <= 1'b0;
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LDPC_Dout_A_TM_reg0 <= 1'b0;
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LDPC_Dout_A_TM_reg1 <= 1'b0;
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good_frames_A_TM_reg0 <= 9'd0;
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good_frames_A_TM_reg1 <= 9'd0;
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bad_frames_A_TM_reg0 <= 9'd0;
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bad_frames_A_TM_reg1 <= 9'd0;
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total_frames_A_TM_reg0 <= 9'd0;
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total_frames_A_TM_reg1 <= 9'd0;
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LDPC_SyncOut_B_TM_reg0 <= 1'b0;
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LDPC_SyncOut_B_TM_reg1 <= 1'b0;
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Rdy_B_TM_reg0 <= 1'b0;
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Rdy_B_TM_reg1 <= 1'b0;
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LDPC_Dout_B_TM_reg0 <= 1'b0;
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LDPC_Dout_B_TM_reg1 <= 1'b0;
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good_frames_B_TM_reg0 <= 9'd0;
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good_frames_B_TM_reg1 <= 9'd0;
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bad_frames_B_TM_reg0 <= 9'd0;
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bad_frames_B_TM_reg1 <= 9'd0;
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total_frames_B_TM_reg0 <= 9'd0;
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total_frames_B_TM_reg1 <= 9'd0;
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end
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else begin
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LDPC_SyncOut_A_TM_reg0 <= LDPC_SyncOut_A_TM;
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LDPC_SyncOut_A_TM_reg1 <= LDPC_SyncOut_A_TM_reg0;
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Rdy_A_TM_reg0 <= Rdy_A_TM;
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Rdy_A_TM_reg1 <= Rdy_A_TM_reg0;
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LDPC_Dout_A_TM_reg0 <= LDPC_Dout_A_TM;
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LDPC_Dout_A_TM_reg1 <= LDPC_Dout_A_TM_reg0;
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good_frames_A_TM_reg0 <= good_frames_A_TM;
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good_frames_A_TM_reg1 <= good_frames_A_TM_reg0;
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bad_frames_A_TM_reg0 <= bad_frames_A_TM;
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bad_frames_A_TM_reg1 <= bad_frames_A_TM_reg0;
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total_frames_A_TM_reg0 <= total_frames_A_TM;
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total_frames_A_TM_reg1 <= total_frames_A_TM_reg0;
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LDPC_SyncOut_B_TM_reg0 <= LDPC_SyncOut_B_TM;
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LDPC_SyncOut_B_TM_reg1 <= LDPC_SyncOut_B_TM_reg0;
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Rdy_B_TM_reg0 <= Rdy_B_TM;
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Rdy_B_TM_reg1 <= Rdy_B_TM_reg0;
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LDPC_Dout_B_TM_reg0 <= LDPC_Dout_B_TM;
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LDPC_Dout_B_TM_reg1 <= LDPC_Dout_B_TM_reg0;
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good_frames_B_TM_reg0 <= good_frames_B_TM;
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good_frames_B_TM_reg1 <= good_frames_B_TM_reg0;
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bad_frames_B_TM_reg0 <= bad_frames_B_TM;
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bad_frames_B_TM_reg1 <= bad_frames_B_TM_reg0;
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total_frames_B_TM_reg0 <= total_frames_B_TM;
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total_frames_B_TM_reg1 <= total_frames_B_TM_reg0;
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end
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end
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reg [0:0] flag_switch_out = 1'b1;
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always @(posedge clk) begin //输出乒乓控制过程
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if (Rst) begin
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flag_switch_out <= 1'd1;
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end
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else begin
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if (LDPC_SyncOut_A_TM || LDPC_SyncOut_B_TM) flag_switch_out <= ~flag_switch_out;
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else flag_switch_out <= flag_switch_out;
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end
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end
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assign LDPC_SyncOut_TM = (flag_switch_out == 1'b0) ? LDPC_SyncOut_A_TM_reg1 : LDPC_SyncOut_B_TM_reg1;
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assign Rdy_TM = (flag_switch_out == 1'b0) ? Rdy_A_TM_reg1 : Rdy_B_TM_reg1;
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assign LDPC_Dout_TM = (flag_switch_out == 1'b0) ? LDPC_Dout_A_TM_reg1 : LDPC_Dout_B_TM_reg1;
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assign good_frames_TM = good_frames_B_TM_reg1 + good_frames_A_TM_reg1;
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assign bad_frames_TM = bad_frames_B_TM_reg1 + bad_frames_A_TM_reg1;
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assign total_frames_TM = total_frames_B_TM_reg1 + total_frames_A_TM_reg1;
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endmodule
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