79 lines
2.4 KiB
Verilog
79 lines
2.4 KiB
Verilog
`timescale 1ns / 1ns
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2019/11/18 23:18:07
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// Design Name:
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// Module Name: VNU_1din
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module VNU_1din(
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input clk,
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input [7:0] din01_CN_CU, //校验节点信息输入
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input [7:0] din02_CHNL_CU, //信道信息输入
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output reg [7:0] dout01_CU=8'd0,//校验节点更新输出
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output reg [0:0] dout02_result_CU=1'd0//判决结果输出
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);//输出相对输入延时8个周期(8)
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reg [8:0] sum=9'd0;
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reg [0:0] result_reg0=1'd0;
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reg [0:0] result_reg1=1'd0;
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reg [0:0] result_reg2=1'd0;
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reg [0:0] result_reg3=1'd0;
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reg [0:0] result_reg4=1'd0;
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reg [8:0] din01_CN_CU_9bit=9'd0;
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reg [8:0] din02_CHNL_CU_9bit=9'd0;
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reg [7:0] din02_CHNL_CU_reg0=8'd0;
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reg [7:0] din02_CHNL_CU_reg1=8'd0;
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reg [7:0] din02_CHNL_CU_reg2=8'd0;
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reg [7:0] din02_CHNL_CU_reg3=8'd0;
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reg [7:0] din02_CHNL_CU_reg4=8'd0;
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reg [7:0] din02_CHNL_CU_reg5=8'd0;
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reg [7:0] din02_CHNL_CU_reg6=8'd0;
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always @ (posedge clk) begin//先把输入转换为9bit
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din01_CN_CU_9bit <= {din01_CN_CU[7],din01_CN_CU[7:0]};
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din02_CHNL_CU_9bit <= {din02_CHNL_CU[7],din02_CHNL_CU[7:0]};
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end
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always @ (posedge clk) begin//结果更新过程
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sum <= din01_CN_CU_9bit + din02_CHNL_CU_9bit;
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result_reg0 <= {sum[8]};
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result_reg1 <= result_reg0;
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result_reg2 <= result_reg1;
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result_reg3 <= result_reg2;
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result_reg4 <= result_reg3;
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dout02_result_CU <= result_reg4;
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end
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always @ (posedge clk) begin
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din02_CHNL_CU_reg0 <= din02_CHNL_CU;
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din02_CHNL_CU_reg1 <= din02_CHNL_CU_reg0;
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din02_CHNL_CU_reg2 <= din02_CHNL_CU_reg1;
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din02_CHNL_CU_reg3 <= din02_CHNL_CU_reg2;
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din02_CHNL_CU_reg4 <= din02_CHNL_CU_reg3;
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din02_CHNL_CU_reg5 <= din02_CHNL_CU_reg4;
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din02_CHNL_CU_reg6 <= din02_CHNL_CU_reg5;
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dout01_CU <= din02_CHNL_CU_reg6;
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end
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endmodule
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