180 lines
5.9 KiB
Verilog
180 lines
5.9 KiB
Verilog
`timescale 1ns / 1ns
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2019/11/18 23:18:07
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// Design Name:
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// Module Name: VNU_3din
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module VNU_3din(
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input clk,
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input [7:0] din01_CN_CU, //校验节点信息输入
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input [7:0] din02_CN_CU, //校验节点信息输入
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input [7:0] din03_CN_CU, //校验节点信息输入
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input [7:0] din04_CHNL_CU, //信道信息输入
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output reg [7:0] dout01_CU=8'd0,//校验节点更新输出
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output reg [7:0] dout02_CU=8'd0,//校验节点更新输出
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output reg [7:0] dout03_CU=8'd0,//校验节点更新输出
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output reg [0:0] dout04_result_CU=1'd0//判决结果输出
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);//输出相对输入延时8个周期(8)
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reg [9:0] din01_CN_CU_10bit=10'd0;
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reg [9:0] din02_CN_CU_10bit=10'd0;
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reg [9:0] din03_CN_CU_10bit=10'd0;
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reg [9:0] din01_CN_CU_10bit_reg0=10'd0;
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reg [9:0] din02_CN_CU_10bit_reg0=10'd0;
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reg [9:0] din03_CN_CU_10bit_reg0=10'd0;
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reg [9:0] din01_CN_CU_10bit_reg1=10'd0;
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reg [9:0] din02_CN_CU_10bit_reg1=10'd0;
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reg [9:0] din03_CN_CU_10bit_reg1=10'd0;
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reg [9:0] din04_CHNL_CU_10bit=10'd0;
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reg [9:0] sum1=10'd0;
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reg [9:0] sum2=10'd0;
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reg [9:0] sum=10'd0;
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reg [9:0] minus1=10'd0;
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reg [9:0] minus2=10'd0;
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reg [9:0] minus3=10'd0;
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reg [9:0] minus1_reg0=10'd0;
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reg [9:0] minus2_reg0=10'd0;
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reg [9:0] minus3_reg0=10'd0;
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reg [9:0] minus1_reg1=10'd0;
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reg [9:0] minus2_reg1=10'd0;
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reg [9:0] minus3_reg1=10'd0;
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reg [9:0] minus1_reg2=10'd0;
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reg [9:0] minus2_reg2=10'd0;
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reg [9:0] minus3_reg2=10'd0;
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reg [9:0] minus1_abs=10'd0;
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reg [9:0] minus2_abs=10'd0;
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reg [9:0] minus3_abs=10'd0;
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reg [0:0] result_reg0=1'd0;
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reg [0:0] result_reg1=1'd0;
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reg [0:0] result_reg2=1'd0;
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reg [0:0] result_reg3=1'd0;
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always @ (posedge clk) begin//先把输入转换为10bit
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din01_CN_CU_10bit <= {{2{din01_CN_CU[7]}},din01_CN_CU[7:0]};
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din02_CN_CU_10bit <= {{2{din02_CN_CU[7]}},din02_CN_CU[7:0]};
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din03_CN_CU_10bit <= {{2{din03_CN_CU[7]}},din03_CN_CU[7:0]};
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din04_CHNL_CU_10bit <= {{2{din04_CHNL_CU[7]}},din04_CHNL_CU[7:0]};
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end
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always @ (posedge clk) begin//流水延时过程
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din01_CN_CU_10bit_reg0 <= din01_CN_CU_10bit;
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din02_CN_CU_10bit_reg0 <= din02_CN_CU_10bit;
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din03_CN_CU_10bit_reg0 <= din03_CN_CU_10bit;
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din01_CN_CU_10bit_reg1 <= din01_CN_CU_10bit_reg0;
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din02_CN_CU_10bit_reg1 <= din02_CN_CU_10bit_reg0;
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din03_CN_CU_10bit_reg1 <= din03_CN_CU_10bit_reg0;
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minus1_reg0 <= minus1;
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minus2_reg0 <= minus2;
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minus3_reg0 <= minus3;
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minus1_reg1 <= minus1_reg0;
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minus2_reg1 <= minus2_reg0;
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minus3_reg1 <= minus3_reg0;
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minus1_reg2 <= minus1_reg1;
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minus2_reg2 <= minus2_reg1;
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minus3_reg2 <= minus3_reg1;
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end
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always @ (posedge clk) begin//结果更新过程
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sum1 <= din01_CN_CU_10bit + din02_CN_CU_10bit;
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sum2 <= din03_CN_CU_10bit + din04_CHNL_CU_10bit;
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sum <= sum1 + sum2;
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result_reg0 <= {sum[9]};
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result_reg1 <= result_reg0;
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result_reg2 <= result_reg1;
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result_reg3 <= result_reg2;
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dout04_result_CU <= result_reg3;
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minus1 <= sum - din01_CN_CU_10bit_reg1;
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minus2 <= sum - din02_CN_CU_10bit_reg1;
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minus3 <= sum - din03_CN_CU_10bit_reg1;
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if(minus1_reg1[9])//限幅前求绝对值操作
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minus1_abs <= ~minus1_reg1 + 10'd1;
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else
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minus1_abs <= minus1_reg1;
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if(minus1_reg2[9]) begin//限幅操作
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if(minus1_abs>10'd127)
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dout01_CU <= -8'd127;
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else
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dout01_CU <= {minus1_reg2[9],minus1_reg2[6:0]};
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// dout01_CU <= minus1_reg2;
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end else begin
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if(minus1_abs>10'd127)
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dout01_CU <= 8'd127;
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else
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dout01_CU <= {minus1_reg2[9],minus1_reg2[6:0]};
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// dout01_CU <= minus1_reg2;
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end
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if(minus2_reg1[9])//限幅前求绝对值操作
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minus2_abs <= ~minus2_reg1 + 10'd1;
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else
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minus2_abs <= minus2_reg1;
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if(minus2_reg2[9]) begin//限幅操作
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if(minus2_abs>10'd127)
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dout02_CU <= -8'd127;
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else
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dout02_CU <= {minus2_reg2[9],minus2_reg2[6:0]};
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// dout02_CU <= minus2_reg2;
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end else begin
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if(minus2_abs>10'd127)
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dout02_CU <= 8'd127;
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else
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dout02_CU <= {minus2_reg2[9],minus2_reg2[6:0]};
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// dout02_CU <= minus2_reg2;
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end
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if(minus3_reg1[9])//限幅前求绝对值操作
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minus3_abs <= ~minus3_reg1 + 10'd1;
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else
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minus3_abs <= minus3_reg1;
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if(minus3_reg2[9]) begin//限幅操作
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if(minus3_abs>10'd127)
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dout03_CU <= -8'd127;
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else
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dout03_CU <= {minus3_reg2[9],minus3_reg2[6:0]};
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// dout03_CU <= minus3_reg2;
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end else begin
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if(minus3_abs>10'd127)
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dout03_CU <= 8'd127;
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else
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dout03_CU <= {minus3_reg2[9],minus3_reg2[6:0]};
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// dout03_CU <= minus3_reg2;
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end
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end
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endmodule
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