59 lines
2.6 KiB
Verilog
59 lines
2.6 KiB
Verilog
`timescale 1ns / 1ns
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module frame_sync #(
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parameter [511:0] M_SEQ =512'b11111111100001111011100001011001101101111010000111001100001001000101011101011110010010111001110000001110111010011110101001010000001010101011111010110100000110111011011010110000010111011111000111100110100110101110001101000101111111010010110001010011000110000000110011001010110010011111101101001001001101111110010110101000010100010011101100101111011000011010101001110010000110001000010000000010001000110010001110101011011000111000100101010001101100111110011110001011011100101001000001001100111010001111101111000000,
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parameter [511:0] M_SEQ_REVERSE =512'b00000011110111110001011100110010000010010100111011010001111001111100110110001010100100011100011011010101110001001100010001000000001000010001100001001110010101011000011011110100110111001000101000010101101001111110110010010010110111111001001101010011001100000001100011001010001101001011111110100010110001110101100101100111100011111011101000001101011011011101100000101101011111010101010000001010010101111001011101110000001110011101001001111010111010100010010000110011100001011110110110011010000111011110000111111111
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) (
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input clk,
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input rst,
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input [11:0] data_i,
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input [11:0] data_q,
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output [17:0] dmf_i,
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output [17:0] dmf_q
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);
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reg [ 9:0] data_i_reg[511:0];
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wire [17:0] sum_i [511:0];
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genvar i;
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generate
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for (i = 0; i < 512; i = i + 1) begin : adder_gen_block
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if (i == 0) begin
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always @(posedge clk) begin
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if (rst) begin
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data_i_reg[i] <= 10'd0;
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end
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else begin
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data_i_reg[i] <= data_i[11-:10];
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end
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end
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adder_iq u_adder_i (
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.A (18'd0),
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.B (data_i_reg[i]),
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.CLK(clk),
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.ADD(~M_SEQ_REVERSE[i]),
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.S (sum_i[i])
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);
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end
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else begin
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always @(posedge clk) begin
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if (rst) begin
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data_i_reg[i] <= 10'd0;
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end
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else begin
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data_i_reg[i] <= data_i_reg[i-1];
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end
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end
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adder_iq u_adder_i (
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.A (sum_i[i-1]),
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.B (data_i_reg[i]),
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.CLK(clk),
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.ADD(~M_SEQ_REVERSE[i]),
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.S (sum_i[i])
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);
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end
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end
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endgenerate
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endmodule
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