62 lines
1.2 KiB
Verilog
62 lines
1.2 KiB
Verilog
module ser2par #(
|
|
parameter PAR_WIDTH = 32
|
|
) (
|
|
input clk,
|
|
input rst,
|
|
input wire ser,
|
|
input wire ser_valid,
|
|
output reg [PAR_WIDTH -1:0] par,
|
|
output reg par_valid
|
|
);
|
|
|
|
// ******** Wire & Reg ********
|
|
reg [$clog2(PAR_WIDTH):0] cnt_idx;
|
|
|
|
// ******** Assingment ********
|
|
|
|
// ******** Logic Block ********
|
|
|
|
always @(posedge clk) begin
|
|
if (rst) begin
|
|
cnt_idx <= 0;
|
|
end
|
|
else if (ser_valid) begin
|
|
if (cnt_idx == PAR_WIDTH - 1) begin // force it return to 0
|
|
cnt_idx <= 0;
|
|
end
|
|
else begin
|
|
cnt_idx <= cnt_idx + 1;
|
|
end
|
|
end
|
|
end
|
|
|
|
always @(posedge clk) begin
|
|
if (rst) begin
|
|
par <= 0;
|
|
end
|
|
else if (ser_valid) begin
|
|
par[cnt_idx] <= ser;
|
|
end
|
|
end
|
|
|
|
always @(posedge clk) begin
|
|
if (cnt_idx == PAR_WIDTH - 1) begin
|
|
par_valid <= 1;
|
|
end
|
|
else begin
|
|
par_valid <= 0;
|
|
end
|
|
end
|
|
|
|
|
|
// ******** Inst ********
|
|
|
|
// ******** Debug ********
|
|
|
|
|
|
|
|
|
|
|
|
|
|
endmodule
|