434 lines
15 KiB
Verilog
434 lines
15 KiB
Verilog
`timescale 10ns / 10ns
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// * Micro7020
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module system_top (
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// rx data
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input ad9361_rx_clk, // ad9361 receive data clock output
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input ad9361_rx_frame, // ad9361 receive data frame output signal, indicates I & Q
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input [11:0] ad9361_rx_data, // ad9361 receive data
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// tx data
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output ad9361_tx_clk, // ad9361 feedback clock
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output ad9361_tx_frame, // ad9361 transmit data frame input signal, indicates I & Q
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output [11:0] ad9361_tx_data, // ad9361 transmit data
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// spi interface
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input ad9361_spi_miso,
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output ad9361_spi_csn,
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output ad9361_spi_clk,
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output ad9361_spi_mosi,
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// control signal
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output ad9361_reset_b, // asynchronous reset, active low
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output ad9361_en_agc, // enable AGC, active high
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output ad9361_enable, // enable ad9361, active high
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output ad9361_txnrx, // logic low selects the RX, logic high selects the TX
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output wire [ 3:0] ad9361_ctrl_in, // ad9361 control in pins, for fastlock control
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// fixed-io
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inout fixed_io_ddr_vrn,
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inout fixed_io_ddr_vrp,
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inout [53:0] fixed_io_mio,
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inout fixed_io_ps_clk,
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inout fixed_io_ps_porb,
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inout fixed_io_ps_srstb,
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// clock signal
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input clk_crystal,
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// ddr
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inout [14:0] ddr_addr,
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inout [ 2:0] ddr_ba,
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inout ddr_cas_n,
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inout ddr_ck_n,
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inout ddr_ck_p,
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inout ddr_cke,
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inout ddr_cs_n,
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inout [ 3:0] ddr_dm,
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inout [31:0] ddr_dq,
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inout [ 3:0] ddr_dqs_n,
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inout [ 3:0] ddr_dqs_p,
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inout ddr_odt,
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inout ddr_ras_n,
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inout ddr_reset_n,
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inout ddr_we_n,
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// uart
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input uart_rx,
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output uart_tx,
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// RF interface control signals
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output wire [ 5:0] rf_gpio,
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output wire led_red,
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output wire led_yellow,
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output wire led_blue
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);
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// ******** Wire & Reg ********
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// power on clock domain
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wire clk_poweron;
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(*max_fanout = 256 *)
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wire rst_sys;
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wire poweron_locked;
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// ad9361 clock domain
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wire locked;
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wire clk_1x;
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wire clk_2x;
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wire clk_4x;
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// emio
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wire [31:0] gpio_i;
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wire [31:0] gpio_o;
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wire [31:0] gpio_t;
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// enc signal
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wire enc_fifo_rd_en;
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wire [31:0] enc_fifo_dout_map;
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wire enc_fifo_empty;
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// tx bus
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wire clk_tx_data_src;
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wire [31:0] tx_data_src_count;
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wire [31:0] tx_data_src_tdata;
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wire tx_data_src_tready;
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wire tx_data_src_tvalid;
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// tx signal
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wire tx_test_flag;
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wire flag_mgc_done_pulse;
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// rx bus
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wire [31:0] rx_data_src_fifo_tdata;
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wire rx_data_src_fifo_tlast;
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wire rx_data_src_fifo_tready;
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wire rx_data_src_fifo_tvalid;
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// baseband signal
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wire [11:0] ad9361_rx_data_i;
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wire [11:0] ad9361_rx_data_q;
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wire ad9361_rx_frame_i;
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wire ad9361_rx_frame_q;
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wire [11:0] ad9361_tx_data_i;
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wire [11:0] ad9361_tx_data_q;
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wire [ 2:0] speed_mode;
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// mux
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wire bb_tx_iq_reverse;
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wire bb_rx_iq_reverse;
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wire [11:0] bb_tx_i;
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wire [11:0] bb_tx_q;
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wire [11:0] bb_rx_i;
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wire [11:0] bb_rx_q;
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// phy control signal
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wire phy_rst_vio;
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wire phy_rst;
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wire phy_tx_test_flag_vio;
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wire phy_tx_test_flag;
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wire phy_tx_iq_reverse;
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wire phy_rx_iq_reverse;
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wire tdma_flag_is_master;
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wire [31:0] tdma_slot_len;
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wire [31:0] tdma_tic_2_ps;
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wire [31:0] tdma_id_cfg;
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wire tdma_recv_cur_slot_id_valid;
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wire [ 7:0] tdma_recv_cur_slot_id;
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wire [31:0] tdma_frame_sync_tic;
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// tx signal
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wire frame_sync_pulse;
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wire rx_rst;
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wire tx_done;
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wire intr_2ps_vio;
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reg intr_2ps_vio_d1;
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wire intr_2ps_vio_pos;
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wire tx_start_vio;
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reg tx_start_vio_d1;
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wire tx_start_vio_pos;
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// rx
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wire rx_err_flag_pos;
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wire rf_io3_d1_12db;
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wire rf_io4_d2_6db;
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wire rf_io0_d3_18db;
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wire rf_io1_d4_12db;
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wire rf_io2_trx; // 1 for tx on, 0 for rx
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// vio
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wire rst_manual;
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wire rx_rst_vio;
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wire [ 7:0] node_id;
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wire intr_2ps;
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wire [ 7:0] max_slot_num;
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reg [15:0] cnt_pulse_wider_tx_start = 0;
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reg [15:0] cnt_pulse_wider_frame_sync = 0;
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// ******** Assingment ********
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assign ad9361_tx_clk = clk_1x;
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assign rst_sys = ~poweron_locked;
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// ad9361 control
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assign ad9361_enable = gpio_o[0]; // ad9361 enable state machine control
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assign ad9361_en_agc = gpio_o[1]; // ad9361 agc control
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assign ad9361_reset_b = gpio_o[2]; // ad9361 reset
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assign ad9361_txnrx = gpio_o[3]; // ad9361 txnrx
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assign ad9361_tx_data_i = phy_tx_iq_reverse ? bb_tx_q : bb_tx_i;
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assign ad9361_tx_data_q = phy_tx_iq_reverse ? bb_tx_i : bb_tx_q;
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assign bb_rx_i = phy_rx_iq_reverse ? ad9361_rx_data_q : ad9361_rx_data_i;
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assign bb_rx_q = phy_rx_iq_reverse ? ad9361_rx_data_i : ad9361_rx_data_q;
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// gpio rf control
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assign rf_gpio[0] = rf_io0_d3_18db;
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assign rf_gpio[1] = rf_io1_d4_12db;
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// assign rf_gpio[2] = rf_io2_trx;
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// assign rf_gpio[3] = rf_io3_d1_12db;
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assign rf_gpio[4] = rf_io4_d2_6db;
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assign rf_gpio[5] = 0;
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// temporary for test gpio
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assign rf_gpio[2] = (cnt_pulse_wider_tx_start != 0);
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assign rf_gpio[3] = (cnt_pulse_wider_frame_sync != 0);
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// ******** Logic Block ********
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always @(posedge clk_1x) begin
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if (tx_start) begin
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cnt_pulse_wider_tx_start <= 1;
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end
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else if (cnt_pulse_wider_tx_start > 0) begin
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cnt_pulse_wider_tx_start <= cnt_pulse_wider_tx_start + 1;
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end
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else begin
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cnt_pulse_wider_tx_start <= cnt_pulse_wider_tx_start;
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end
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end
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always @(posedge clk_2x) begin
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if (rx_data_src_fifo_tlast) begin
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cnt_pulse_wider_frame_sync <= 1;
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end
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else if (cnt_pulse_wider_frame_sync > 0) begin
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cnt_pulse_wider_frame_sync <= cnt_pulse_wider_frame_sync + 1;
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end
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else begin
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cnt_pulse_wider_frame_sync <= cnt_pulse_wider_frame_sync;
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end
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end
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// ******** Inst ********
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clk_wiz_poweron u_clk_wiz_poweron (
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// Clock out ports
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.clk_poweron(clk_poweron), // output clk_poweron
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// Status and control signals
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.locked (poweron_locked), // output locked
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// Clock in ports
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.clk_crystal(clk_crystal) // input clk_crystal
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);
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// clock domain - ad9361 rx & tx
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clk_wiz_baseband u_clk_wiz_baseband (
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// Clock out ports
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.clk_1x (clk_1x), // output clk_1x
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.clk_2x (clk_2x), // output clk_2x
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.clk_4x (clk_4x), // output clk_4x
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// Status and control signals
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.locked (locked), // output locked
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// Clock in ports
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.clk_src(ad9361_rx_clk) // input clk_src
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);
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MM7020_BD_wrapper u_MM7020_BD_wrapper (
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.ad9361_spi_clk (ad9361_spi_clk),
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.ad9361_spi_csn (ad9361_spi_csn),
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.ad9361_spi_miso (ad9361_spi_miso),
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.ad9361_spi_mosi (ad9361_spi_mosi),
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.clk_ps (clk_poweron),
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.rst_ps (rst_sys),
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// ddr
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.ddr_addr (ddr_addr),
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.ddr_ba (ddr_ba),
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.ddr_cas_n (ddr_cas_n),
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.ddr_ck_n (ddr_ck_n),
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.ddr_ck_p (ddr_ck_p),
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.ddr_cke (ddr_cke),
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.ddr_cs_n (ddr_cs_n),
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.ddr_dm (ddr_dm),
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.ddr_dq (ddr_dq),
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.ddr_dqs_n (ddr_dqs_n),
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.ddr_dqs_p (ddr_dqs_p),
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.ddr_odt (ddr_odt),
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.ddr_ras_n (ddr_ras_n),
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.ddr_reset_n (ddr_reset_n),
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.ddr_we_n (ddr_we_n),
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// fixed io
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.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
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.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
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.fixed_io_mio (fixed_io_mio),
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.fixed_io_ps_clk (fixed_io_ps_clk),
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.fixed_io_ps_porb (fixed_io_ps_porb),
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.fixed_io_ps_srstb (fixed_io_ps_srstb),
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// gpio ps
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.gpio_i (gpio_i),
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.gpio_o (gpio_o),
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.gpio_t (gpio_t),
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// intr pl to ps
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.pl_tx_intr (intr_2ps),
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.pl_rx_intr (rx_data_src_fifo_tlast),
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.pl_intr0 (rx_err_flag_pos),
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// tx fifo
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.tx_data_src_count (tx_data_src_count),
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.tx_data_src_tdata (tx_data_src_tdata),
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.tx_data_src_tready (tx_data_src_tready),
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.tx_data_src_tvalid (tx_data_src_tvalid),
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// rx fifo
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.clk_rx_data_src_fifo (clk_2x),
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.rst_rx_data_src_fifo (rx_rst),
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.rx_data_src_fifo_tdata (rx_data_src_fifo_tdata),
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.rx_data_src_fifo_tlast (rx_data_src_fifo_tlast),
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.rx_data_src_fifo_tready (rx_data_src_fifo_tready),
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.rx_data_src_fifo_tvalid (rx_data_src_fifo_tvalid),
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// phy clock and rst to ps
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.clk_phy (clk_1x),
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.rst_phy_n (~rst_sys),
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// phy control signal , under clk_1x domain
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.phy_rst (phy_rst),
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.phy_tx_test_flag (phy_tx_test_flag),
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.phy_tx_iq_reverse (phy_tx_iq_reverse),
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.phy_rx_iq_reverse (phy_rx_iq_reverse),
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.tdma_flag_is_master (tdma_flag_is_master),
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.tdma_slot_len (tdma_slot_len),
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.tdma_tic_2_ps (tdma_tic_2_ps),
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.tdma_id_cfg (tdma_id_cfg),
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.tdma_recv_cur_slot_id_valid(tdma_recv_cur_slot_id_valid),
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.tdma_recv_cur_slot_id (tdma_recv_cur_slot_id),
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.tdma_frame_sync_tic (tdma_frame_sync_tic),
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// uart
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.uart_rx (uart_rx),
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.uart_tx (uart_tx)
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);
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tdma u_tdma (
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.clk (clk_1x),
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.rst (rst_sys),
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.flag_frame_sync (frame_sync_pulse),
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.tdma_slot_len (tdma_slot_len[23:0]),
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.tdma_tic_2_ps (tdma_tic_2_ps[23:0]),
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.tdma_slot_num (tdma_id_cfg[15:8]),
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.tdma_frame_sync_tic (tdma_frame_sync_tic[23:0]),
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.local_id (tdma_id_cfg[7:0]),
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.recevied_cur_slot_id_valid(tdma_recv_cur_slot_id_valid),
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.recevied_cur_slot_id (tdma_recv_cur_slot_id),
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.intr_2ps (intr_2ps),
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.tx_start (tx_start),
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.rx_rst (rx_rst)
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);
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// ---- PHY layer logic start
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enc_control u_enc_control (
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.clk (clk_poweron),
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.rst (rst_sys | phy_rst),
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.s_axis_fifo_tvalid (tx_data_src_tvalid),
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.s_axis_fifo_tready (tx_data_src_tready),
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.s_axis_fifo_tdata (tx_data_src_tdata),
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.data_src_count (tx_data_src_count),
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.fifo_enc_out_rd_clk (clk_1x),
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.fifo_enc_out_rd_en (enc_fifo_rd_en),
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.fifo_enc_out_dout_map(enc_fifo_dout_map),
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.fifo_enc_out_empty (enc_fifo_empty)
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);
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Transmitter u_Transmitter (
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.clk (clk_1x),
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.rst (rst_sys | phy_rst),
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.speed_mode (2),
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.send_data_ready (send_data_ready),
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.send_start (tx_start),
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.send_over (tx_done),
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.clk_data_src (clk_data_src),
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.tx_data_src_tdata (enc_fifo_dout_map),
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.tx_data_src_tready(enc_fifo_rd_en),
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.tx_data_src_tvalid(~enc_fifo_empty),
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.hopping_freq (),
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.ad9361_tx_data_i (bb_tx_i),
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.ad9361_tx_data_q (bb_tx_q),
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.test (phy_tx_test_flag),
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.hop_wait (100)
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);
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RecvTop u_RecvTop (
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.clk (clk_1x),
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.clk_2x (clk_2x),
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.clk_4x (clk_4x),
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.rst (rst_sys | rx_rst | phy_rst),
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.rst2 (rst_sys | phy_rst),
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.dini (bb_rx_i),
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.dinq (bb_rx_q),
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.ad9361_ctrl_in (ad9361_ctrl_in),
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.flag_mgc_done_pulse (flag_mgc_done_pulse),
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.frame_sync_pulse (frame_sync_pulse),
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.vio_tsync_inter16 (1),
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.EQUenable_vio (1),
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.Zerozone_vio (8'd29),
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.vio_stopbit (7'd60),
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.flag_stop (flag_stop),
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.addr_stop (addr_stop),
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.recvNetData (recvNetData),
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.recvNetDataNd (recvNetDataNd),
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.rx_data_src_fifo_tdata (rx_data_src_fifo_tdata),
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.rx_data_src_fifo_tlast (rx_data_src_fifo_tlast),
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.rx_data_src_fifo_tready(rx_data_src_fifo_tready),
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.rx_data_src_fifo_tvalid(rx_data_src_fifo_tvalid),
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.err_flag_pos (rx_err_flag_pos)
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);
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// ---- PHY layer logic end
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// ad9361 digital port - 1R1T, Dual Port, DDR
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ad9361_dp_fdd_1r1t ad9361_dp_fdd_1r1t_inst (
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// Receive
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.rx_clk (ad9361_rx_clk),
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.rx_data (ad9361_rx_data),
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.rx_frame (ad9361_rx_frame),
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.rx_data_i (ad9361_rx_data_i),
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.rx_data_q (ad9361_rx_data_q),
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.rx_frame_i(ad9361_rx_frame_i),
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.rx_frame_q(ad9361_rx_frame_q),
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// Transmit
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.tx_clk (ad9361_tx_clk),
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.tx_data_i (ad9361_tx_data_i),
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.tx_data_q (ad9361_tx_data_q),
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.tx_data (ad9361_tx_data),
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.tx_frame (ad9361_tx_frame)
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);
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// ******** CDC ********
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// ******** Debug ********
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// ila_ad9361_rx u_ila_ad9361_rx (
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// .clk (ad9361_rx_clk),
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// .probe0(ad9361_rx_data_i),
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// .probe1(ad9361_rx_data_q),
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// .probe2(u_RecvTop.flag_mgc_done)
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// );
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// ila_ad9361_tx u_ila_ad9361_tx (
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// .clk (ad9361_tx_clk), // input wire clk
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// .probe0(ad9361_tx_data_i), // input wire [11:0] probe0
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// .probe1(ad9361_tx_data_q) // input wire [11:0] probe1
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// );
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// vio_rf u_vio_rf (
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// .clk (clk_poweron),
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// .probe_out0(rf_io2_trx),
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// .probe_out1(rf_io3_d1_12db),
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// .probe_out2(rf_io4_d2_6db),
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// .probe_out3(rf_io0_d3_18db),
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// .probe_out4(rf_io1_d4_12db)
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// );
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endmodule
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