134 lines
3.2 KiB
Verilog
134 lines
3.2 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2019/11/14 18:02:13
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// Design Name:
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// Module Name: ApproxAbs_12bit
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module ApproxAbs_18bit(
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input clk,
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input ND,
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input [17:0] Din_I,
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input [17:0] Din_Q,
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output reg [18:0] Dout,
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output reg Rdy
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);
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// 第一级延迟：把输入变负值：
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reg [17:0] Din_I_neg;
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always @ (posedge clk) begin
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if (Din_I[17:0]==18'b10_0000_0000_0000_0000)
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Din_I_neg[17:0] <= 18'b01_1111_1111_1111_1111;
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else
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Din_I_neg[17:0] <= -Din_I[17:0];
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end
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reg [17:0] Din_Q_neg;
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always @ (posedge clk) begin
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if (Din_Q[17:0]==18'b10_0000_0000_0000_0000)
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Din_Q_neg[17:0] <= 18'b01_1111_1111_1111_1111;
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else
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Din_Q_neg[17:0] <= -Din_Q[17:0];
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end
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// 第二级延迟：求绝对值：
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reg [17:0] Din_I_D1;
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reg [17:0] Din_Q_D1;
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always @ (posedge clk) begin
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Din_I_D1[17:0] <= Din_I[17:0];
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Din_Q_D1[17:0] <= Din_Q[17:0];
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end
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reg [17:0] Abs_Din_I;
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reg [17:0] Abs_Din_Q;
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always @ (posedge clk) begin
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if(Din_I_D1[17]==1'b1)
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Abs_Din_I[17:0] <= Din_I_neg[17:0];
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else
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Abs_Din_I[17:0] <= Din_I_D1[17:0];
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if(Din_Q_D1[17]==1'b1)
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Abs_Din_Q[17:0] <= Din_Q_neg[17:0];
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else
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Abs_Din_Q[17:0] <= Din_Q_D1[17:0];
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end
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// 第三级延迟：确定I/Q两路绝对值的大小关系：
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reg [17:0] AbsIQ_max;
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reg [17:0] AbsIQ_min;
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always @ (posedge clk) begin
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if (Abs_Din_I[17:0]>=Abs_Din_Q[17:0]) begin
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AbsIQ_max[17:0] <= Abs_Din_I[17:0];
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AbsIQ_min[17:0] <= Abs_Din_Q[17:0];
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end
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else begin
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AbsIQ_max[17:0] <= Abs_Din_Q[17:0];
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AbsIQ_min[17:0] <= Abs_Din_I[17:0];
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end
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end
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// 第四级延迟：MXQ选择的系数：7/8和1/2：
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reg [17:0] AbsIQ_max_7by8;
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reg [17:0] AbsIQ_min_1by2;
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always @ (posedge clk) begin
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AbsIQ_max_7by8[17:0] <= AbsIQ_max[17:0]-{3'b000,AbsIQ_max[17:3]};
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AbsIQ_min_1by2[17:0] <= {AbsIQ_min[17],AbsIQ_min[17:1]};
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end
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// 第五级延迟：1bit位扩展求和：
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// (MXQ)中间将最大延迟一个clk赋给 Dout_Temp2,使 Dout_Temp2与 Dout_Temp在同一个clk下进行比较。
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reg [18:0] Dout_Temp;
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reg [18:0] Dout_Temp1;
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reg [18:0] Dout_Temp2;
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always @ (posedge clk) begin
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Dout_Temp[18:0] <= {1'b0,AbsIQ_max_7by8[17:0]} + {1'b0,AbsIQ_min_1by2[17:0]};
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Dout_Temp1[18:0] <= {1'b0,AbsIQ_max[17:0]};
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Dout_Temp2[18:0] <= Dout_Temp1[18:0];
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end
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// (MXQ)第六级延迟：输出求和值与I/Q两路绝对值最大值比较之后的最大值：
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always @ (posedge clk) begin
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if(Dout_Temp[18:0]>=Dout_Temp2[17:0])
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Dout[18:0] <= Dout_Temp[18:0];
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else
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Dout[18:0] <= Dout_Temp2[18:0];
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end
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// 产生Rdy，与ND有六级延迟：
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reg Rdy_b5 = 1'b0;
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reg Rdy_b4 = 1'b0;
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reg Rdy_b3 = 1'b0;
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reg Rdy_b2 = 1'b0;
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reg Rdy_b1 = 1'b0;
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always@(posedge clk) begin//(MXQ)必须加 posedge clk ,否则仿真有问题，内存溢出
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Rdy_b5 <= ND;
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Rdy_b4 <= Rdy_b5;
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Rdy_b3 <= Rdy_b4;
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Rdy_b2 <= Rdy_b3;
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Rdy_b1 <= Rdy_b2;
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Rdy <= Rdy_b1;
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end
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endmodule
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