551 lines
18 KiB
Verilog
551 lines
18 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 17:42 11/14/2019
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// Design Name:
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// Module Name: RecvTop
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module RecvTop (
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input clk,
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input clk2,
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input clk_60M_mac,
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input rst,
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input rst2,
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input [11:0] dini,
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input [11:0] dinq,
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//视频数据存储，shx
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input [13:0] recv_addr_new_0,
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input [13:0] recv_addr_new_1,
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input [13:0] recv_addr_new_2,
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input [13:0] recv_addr_new_3,
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output [ 7:0] recv_data_new_0,
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output [ 7:0] recv_data_new_1,
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output [ 7:0] recv_data_new_2,
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output [ 7:0] recv_data_new_3,
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output [16:0] RAMaddra_write_0,
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output [16:0] RAMaddra_write_1,
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output [16:0] RAMaddra_write_2,
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output [16:0] RAMaddra_write_3,
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output [16:0] RAMaddra_new_0,
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output [16:0] RAMaddra_new_1,
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output [16:0] RAMaddra_new_2,
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output [16:0] RAMaddra_new_3,
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output flag_stop, //给shx，拉高8个clk表示当前时帧有效数据接收完毕
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output [16:0] addr_stop, //给shx，拉高8个clk,与flag_stop对齐，指示位置与最后1bit有效数据的位置对齐
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//vio
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// input DC_move_able, //为1的时候启用去直流，为0的时候不启用
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// input [1:0] vio_powertest_h, //DAGC
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// input [1:0] vio_powertest_l, //DAGC
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// input DAGC_enab, //为1的时候启用DAGC，为0的时候不启用DAGC
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// input vio_tsync_inter16, //为1的时候启用内插，从16倍过采样中挑一路
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// input EQUenable_vio, //为1时启用均衡
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// input [7:0] Zerozone_vio, //零域估计，默认值为8'd29
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input [6:0] vio_stopbit, //寻找停止位，默认值为7'd60
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//9361、射频增益控制
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output [7:0] data_9361,
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output [9:0] addr_9361,
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output enab_9361,
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output D1_12dB,
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output D2_6dB,
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output D3_18dB,
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output D4_12dB,
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//debug
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//trigger
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output rst_TimeSync,
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output rst_freq,
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output DAGC_rdy,
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output framesync, //帧同步峰
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output framesync_delay, //帧同步峰，与频率补偿输出对应
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output framesync_tsync, //帧同步标志，与TSync输出对应
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output IntpARdy, //TSync输出nd
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output nd_SC_FDE_dout, //SC_FDE输出nd
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output framerdy, //一帧译码结果存储完毕标志
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output reg flag_bercount = 1'd0,
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output reg flag_badframe = 1'd0,
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output reg flag_ber = 1'd0,
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//各模块输出，星座图
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output [11:0] dc_removal_dout_i, //MGC_adaptation、去直流输出
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output [11:0] dc_removal_dout_q,
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output [ 9:0] matchfilterout_i, //MF输出
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output [ 9:0] matchfilterout_q,
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output [ 9:0] DAGC_out_i, //DAGC输出
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output [ 9:0] DAGC_out_q,
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output [ 9:0] freqdataout_i, //频率补偿输出
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output [ 9:0] freqdataout_q,
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output [ 9:0] IntpOuti, //TSync输出
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output [ 9:0] IntpOutq,
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output [ 9:0] SC_FDE_douti, //SC_FDE输出
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output [ 9:0] SC_FDE_doutq,
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//MGC_adaptation
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output [24:0] mean_temp,
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output [12:0] acc_mean,
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output [ 4:0] state_mgc,
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output mgc1_rdy,
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output flag_state_mgc,
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output [ 2:0] state_rst,
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output flag_overflow,
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output flag_small,
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//DC
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output [11:0] dc_value_i,
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output [11:0] dc_value_q,
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output flag_dc,
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//DAGC
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output flag_agch,
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output flag_agcl,
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output flag_agc_power,
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output [12:0] agc_ref,
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output [12:0] agc_check,
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//power test
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output flag_powerabsh,
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output flag_powerabsl,
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output flag_abs_power,
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output [10:0] abs_ref,
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output [10:0] abs_check,
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//TSync
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output [ 3:0] flag_clk_4bit, //位同步选取通道结果
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//SC_FDE,溢出标志
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output flagoverflow_fftpilot_26to14, //第1个fft结果截位，即导频fft结果的截位，26截到14
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output flagoverflow_ChnZF_26to18, //第2个fft结果截位，即ZF信道估计结果的截位，26截到18
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output flagoverflow_comdiv_34to20i, //第1个除法器结果截位，即复数除法结果的截位，得到没有去噪的ZF估计，34截到18
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output flagoverflow_comdiv_34to20q, //第1个除法器结果截位，即复数除法结果的截位，得到没有去噪的ZF估计，34截到18
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output flagoverflow_ifftzero_29to17i, //第1个ifft结果截位，即ZF零域估计处，结果先除掉低8位，29-8=21截到17
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output flagoverflow_ifftzero_29to17q, //第1个ifft结果截位，即ZF零域估计处，结果先除掉低8位，29-8=21截到17
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output flagoverflow_MMSEdiv_divisor_31to28, //第2个除法器，即MMSE除法的分母截位，31截到28
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output flagoverflow_divmmse_34to11, //第2个除法器结果截位，即MMSE信道估计结果的截位，34截到11
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output flagoverflow_ifftindata_28to20i, //均衡完毕后（频域结果）的截位，即乘法器输出结果的截位，28截到20
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output flagoverflow_ifftindata_28to20q, //均衡完毕后（频域结果）的截位，即乘法器输出结果的截位，28截到20
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output flagoverflow_fftdata_26to16i, //数据段ow的fft输出截位，26截到16
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output flagoverflow_fftdata_26to16q, //数据段ow的fft输出截位，26截到16
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output flagoverflow_FDE_dataout_29to10i, //ifft结果截位，即均衡结果处，结果先除掉低8位，29-7=22截到10
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output flagoverflow_FDE_dataout_29to10q, //ifft结果截位，即均衡结果处，结果先除掉低8位，29-7=22截到10
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output reg flagoverflow = 1'd0, //总溢出标志
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output Pilot_rdy_hide1_d1,
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output [63:0] recvNetData,
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output recvNetDataNd,
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input debug_loss
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// input [ 7:0] MAC_idNum
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// input [ 7:0] video_id01,
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// input [ 7:0] video_id02,
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// input [ 7:0] video_id03
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);
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MGC_adaptation MGC_adaptation (
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.clk (clk),
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.rst (rst),
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.dini(dini),
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.dinq(dinq),
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.data_9361(data_9361),
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.addr_9361(addr_9361),
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.enab_9361(enab_9361),
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.D1_12dB (D1_12dB),
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.D2_6dB (D2_6dB),
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.D3_18dB (D3_18dB),
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.D4_12dB (D4_12dB),
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.mgc1_rdy(mgc1_rdy)
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);
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wire MF_rdy;
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wire MF_rst;
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MF_Top MF_Top (
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.clk(clk),
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.rst(rst),
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// .rst (rst),
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.dini (dini),
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.dinq (dinq),
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.start(mgc1_rdy),
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.matchfilterout_i(matchfilterout_i),
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.matchfilterout_q(matchfilterout_q),
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.MF_rdy (MF_rdy),
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.MF_rst (MF_rst)
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);
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//帧同步模块
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assign FrameSync_dini = (DAGC_enab) ? DAGC_out_i : matchfilterout_i;
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assign FrameSync_dinq = (DAGC_enab) ? DAGC_out_q : matchfilterout_q;
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// wire framesync;
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wire Sync_rdy;
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wire Pilot_rdy;
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wire [9:0] FrameSync_douti;
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wire [9:0] FrameSync_doutq;
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SCFDE_recv_FrameSync SCFDE_recv_FrameSync_inst (
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.clk (clk),
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.rst (MF_rst),
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.rst_ready (~MF_rdy),
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.datain_i (matchfilterout_i),
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.datain_q (matchfilterout_q),
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.Sync_i (FrameSync_douti),
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.Sync_q (FrameSync_doutq),
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.Sync_rdy (Sync_rdy), // 帧同步找到了过门限峰值
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.Pilot_rdy (Pilot_rdy),// 开始取导频的标志位 not used
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.flag_sync (framesync), // high level flag
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.Pilot_rdy_hide1_d1(Pilot_rdy_hide1_d1) // not used
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);
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//
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reg [20:0] cnt_lost;
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reg framelost;
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always @(posedge clk) begin
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if (Pilot_rdy_hide1_d1) begin
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cnt_lost <= 21'd0;
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framelost <= 1'b0;
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end else begin
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if (cnt_lost >= 21'd750000) begin
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;
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cnt_lost <= 21'd0;
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framelost <= 1'b1;
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end else begin
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cnt_lost <= 21'd1 + cnt_lost;
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framelost <= 1'b0;
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end
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end
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end
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// wire [9:0] DAGC_out_i;
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// wire [9:0] DAGC_out_q;
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// wire flag_agch;
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// wire flag_agcl;
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// wire flag_agc_power;
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// wire [12:0] agc_ref;
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// wire [12:0] agc_check;
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wire dagc_rdy;
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wire mgc_rdy;
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wire rst_dagc;
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DAGC_v2 DAGC_v2 (
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.clk (clk),
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.rst (~mgc1_rdy),
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.mgc1_rdy (MF_rdy),
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.framesync_d0 (framesync),
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.vio_powertest_h (2'b00),
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.vio_powertest_l (2'b00),
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.matchfilterout_i(FrameSync_douti), // input,
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.matchfilterout_q(FrameSync_doutq), // input
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.DAGC_out_i(DAGC_out_i), // output
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.DAGC_out_q(DAGC_out_q), // output
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.flag_agch (flag_agch),
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.flag_agcl (flag_agcl),
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.flag_agc_power(flag_agc_power),
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.agc_ref (agc_ref),
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.agc_check (agc_check),
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.dagc_rdy (dagc_rdy),
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.mgc_rdy (mgc_rdy),
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.rst_dagc (rst_dagc)
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);
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//载波频偏补偿
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// wire [9:0] freqdataout_i;
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// wire [9:0] freqdataout_q;
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// wire framesync_delay;
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wire data_save; //debug用，暂不需使用
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// wire rst_freq;
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freqestm freqestm (
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.clk (clk),
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.rst (MF_rst),
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.mgc_rdy (mgc_rdy),
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.framesync (dagc_rdy),
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.datain_i (DAGC_out_i),
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.datain_q (DAGC_out_q),
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.dataout_i (freqdataout_i),
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.dataout_q (freqdataout_q),
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.framesync_delay(framesync_delay),
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.data_save (data_save),
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.rst_freq (rst_freq)
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);
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//位同步
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wire [1:0] cnt_tsync;
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// wire framesync_tsync; //帧同步标志
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TimeSync_top TimeSync_top (
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.clk (clk),
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.rst (Pilot_rdy_hide1_d1),
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.dini (freqdataout_i),
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.dinq (freqdataout_q),
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.rdy (IntpARdy),
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.douti (IntpOuti),
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.doutq (IntpOutq),
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.vio_tsync_inter16(vio_tsync_inter16),
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.framesync (framesync_delay), //帧同步标志
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.framesync_tsync (framesync_tsync), //帧同步标志
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//debug
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.cnt_tsync (cnt_tsync),
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.flag_clk_4bit (flag_clk_4bit)
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);
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// SC-FDE
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SC_FDE_TOP SC_FDE_TOP_djy (
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.clk(clk),
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.rst(Pilot_rdy_hide1_d1),
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.EQUenable_vio(EQUenable_vio), //为1时启用均衡
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.Zerozone_vio (Zerozone_vio), //零域估计，默认值为8'd29
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.flag_ow_left (framesync_tsync), //在一帧内，与第一个数据段的pilot的ow第一个nd对齐
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.nd (IntpARdy),
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.dini (IntpOuti),
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.dinq (IntpOutq),
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.nd_SC_FDE_dout (nd_SC_FDE_dout),
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.SC_FDE_douti (SC_FDE_douti),
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.SC_FDE_doutq (SC_FDE_doutq),
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// debug,溢出标志
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.flagoverflow_fftpilot_26to14 (flagoverflow_fftpilot_26to14),
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.flagoverflow_ChnZF_26to18 (flagoverflow_ChnZF_26to18),
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.flagoverflow_comdiv_34to20i (flagoverflow_comdiv_34to20i),
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.flagoverflow_comdiv_34to20q (flagoverflow_comdiv_34to20q),
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.flagoverflow_ifftzero_29to17i (flagoverflow_ifftzero_29to17i),
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.flagoverflow_ifftzero_29to17q (flagoverflow_ifftzero_29to17q),
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.flagoverflow_MMSEdiv_divisor_31to28(flagoverflow_MMSEdiv_divisor_31to28),
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.flagoverflow_divmmse_34to11 (flagoverflow_divmmse_34to11),
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.flagoverflow_ifftindata_28to20i (flagoverflow_ifftindata_28to20i),
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.flagoverflow_ifftindata_28to20q (flagoverflow_ifftindata_28to20q),
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.flagoverflow_fftdata_26to16i (flagoverflow_fftdata_26to16i),
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.flagoverflow_fftdata_26to16q (flagoverflow_fftdata_26to16q),
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.flagoverflow_FDE_dataout_29to10i (flagoverflow_FDE_dataout_29to10i),
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.flagoverflow_FDE_dataout_29to10q (flagoverflow_FDE_dataout_29to10q)
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);
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wire phase_adjust_rdy;
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wire [9:0] phase_adjust_douti;
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wire [9:0] phase_adjust_doutq;
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phase_adjust phase_adjust (
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.clk (clk),
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.rst (Pilot_rdy_hide1_d1),
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.din_i (SC_FDE_douti),
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.din_q (SC_FDE_doutq),
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.nd (nd_SC_FDE_dout),
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.framesync(framesync_tsync),
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.rdy (phase_adjust_rdy),
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.dout_i (phase_adjust_douti),
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.dout_q (phase_adjust_doutq)
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);
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wire IQmergerdy;
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wire ldpcsyncin;
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wire [7:0] IQmergedout;
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IQmerge IQmerge (
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.clk (clk),
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.clk2 (clk2),
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.rst (rst2 || Pilot_rdy_hide1_d1),
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.nd (phase_adjust_rdy),
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.framesync (framesync_tsync),
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.dini (phase_adjust_douti),
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.dinq (phase_adjust_doutq),
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.rdy (IQmergerdy),
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.ldpcsyncin(ldpcsyncin),
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.dout (IQmergedout)
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);
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wire LDPC_SyncOut;
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wire LDPC_Rdy;
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wire LDPC_Dout;
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wire [8:0] good_frames;
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wire [8:0] bad_frames;
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wire [8:0] total_frames;
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CCSDS_LDPC_DEC_K1024_R12_TOPP LDPC_decode (
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.clk (clk2),
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.Rst (rst2 || Pilot_rdy_hide1_d1),
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.FrameSync (ldpcsyncin),
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.Nd (IQmergerdy),
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.Din (IQmergedout),
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.LDPC_SyncOut(LDPC_SyncOut),
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.Rdy (LDPC_Rdy),
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.LDPC_Dout (LDPC_Dout),
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.good_frames (good_frames),
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.bad_frames (bad_frames),
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.total_frames(total_frames)
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);
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wire flag_notbyte; //为1时说明得到的有效数据不以字节为单位
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wire [ 1:0] state_ram;
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wire berstart_1d;
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wire bercompare;
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wire [16:0] bercount;
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wire [16:0] bercount_max;
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wire [16:0] ROMaddra_d2;
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wire RAMdout_d1;
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wire validnd_new_new;
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wire [63:0] stop_temp_new;
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wire flag_stop_0; //给shx，拉高1个clk表示当前时帧有效数据接收完毕
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wire [16:0] addr_stop_0;
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wire [ 2:0] cnt_8;
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wire state_8;
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wire rdy_scramble;
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wire dout_scramble;
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wire [16:0] RAMaddra; //比较误码率
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wire [16:0] ROMaddra; //比较误码率
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wire nd_ber;
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FrameMerge FrameMerge (
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.clk (clk2),
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.rst (Pilot_rdy_hide1_d1),
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.rst2(rst2),
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.sync(LDPC_SyncOut),
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.nd (LDPC_Rdy),
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.din (LDPC_Dout),
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.vio_stopbit(vio_stopbit),
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.frameIDnd(Pilot_rdy_hide1_d1),
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.clk2 (clk_60M_mac),
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.framerdy (framerdy),
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.recv_addr_new_0 (recv_addr_new_0),
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.recv_addr_new_1 (recv_addr_new_1),
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.recv_addr_new_2 (recv_addr_new_2),
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.recv_addr_new_3 (recv_addr_new_3),
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.recv_data_new_0 (recv_data_new_0),
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.recv_data_new_1 (recv_data_new_1),
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.recv_data_new_2 (recv_data_new_2),
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.recv_data_new_3 (recv_data_new_3),
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.RAMaddra_write_0(RAMaddra_write_0),
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.RAMaddra_write_1(RAMaddra_write_1),
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.RAMaddra_write_2(RAMaddra_write_2),
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.RAMaddra_write_3(RAMaddra_write_3),
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.RAMaddra_new_0 (RAMaddra_new_0),
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.RAMaddra_new_1 (RAMaddra_new_1),
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.RAMaddra_new_2 (RAMaddra_new_2),
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.RAMaddra_new_3 (RAMaddra_new_3),
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|
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.flag_notbyte(flag_notbyte),
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.state_ram (state_ram),
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.flag_stop (flag_stop), //给shx，拉高8个clk表示当前时帧有效数据接收完毕
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.addr_stop (addr_stop), //给shx，拉高8个clk,与flag_stop对齐，指示位置与最后1bit有效数据的位置对齐
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//debug
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.berstart_1d (berstart_1d),
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.bercompare (bercompare),
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|
.bercount (bercount),
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|
.bercount_max(bercount_max),
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|
.ROMaddra_d2 (ROMaddra_d2),
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|
.RAMdout_d1 (RAMdout_d1),
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|
|
|
.validnd_new_new(validnd_new_new),
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|
|
|
.stop_temp_new(stop_temp_new),
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|
|
|
.flag_stop_0(flag_stop_0),
|
|
.addr_stop_0(addr_stop_0),
|
|
.cnt_8 (cnt_8),
|
|
.state_8 (state_8),
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|
|
|
.rdy_scramble (rdy_scramble),
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|
.dout_scramble(dout_scramble),
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|
|
|
.RAMaddra (RAMaddra),
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|
.ROMaddra (ROMaddra),
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|
.nd_ber (nd_ber),
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|
.recvNetData (recvNetData),
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|
.recvNetDataNd(recvNetDataNd)
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|
// .MAC_idNum (MAC_idNum)
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// .video_id01 (8'd0),
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// .video_id02 (8'd0),
|
|
// .video_id03 (8'd0)
|
|
);
|
|
|
|
|
|
|
|
|
|
/*ila_recvtop ila_recvtop(
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|
.clk(clk),
|
|
.probe0(framesync),
|
|
.probe1(framesync_delay),
|
|
.probe2(phase_adjust_rdy),
|
|
.probe3(nd_SC_FDE_dout),
|
|
.probe4(IQmergerdy),
|
|
.probe5(IQmergedout),
|
|
.probe6(LDPC_Rdy),
|
|
.probe7(LDPC_Dout),
|
|
.probe8(SC_FDE_douti),
|
|
.probe9(SC_FDE_doutq),
|
|
.probe10(total_frames),
|
|
.probe11(good_frames),
|
|
.probe12(dini),
|
|
.probe13(dinq),
|
|
.probe14(phase_adjust_douti),
|
|
.probe15(phase_adjust_doutq),
|
|
.probe16(D1_12dB),
|
|
.probe17(D2_6dB),
|
|
.probe18(D3_18dB),
|
|
.probe19(D4_12dB)
|
|
|
|
);*/
|
|
ila_recvtest ila_recvtest (
|
|
.clk (clk),
|
|
.probe0(framesync),
|
|
.probe1(framesync_delay),
|
|
.probe2(D1_12dB),
|
|
.probe3(D2_6dB),
|
|
.probe4(D3_18dB),
|
|
.probe5(D4_12dB),
|
|
.probe6(mgc1_rdy),
|
|
.probe7(rst),
|
|
.probe8(dini),
|
|
.probe9(dinq)
|
|
);
|
|
/*ila_decode ila_decode(
|
|
.clk(clk2),
|
|
.probe0(IQmergerdy),
|
|
.probe1(IQmergedout),
|
|
.probe2(LDPC_Dout),
|
|
.probe3(LDPC_Rdy),
|
|
.probe4(framerdy),
|
|
.probe5(total_frames),
|
|
.probe6(good_frames)
|
|
);*/
|
|
|
|
endmodule
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