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fix(hw config): swap ad9361 I/Q channel

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Gatsby Van
2024-11-05 23:55:24 +08:00
parent 92d3286d81
commit 5ef3ae13c3
2 changed files with 2 additions and 2 deletions
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src/dev_profile/ad9361_1_reg_profile.c
+1 -1
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@@ -100,7 +100,7 @@ uint32_t ad9361_1_reg_config(struct ad9361_reg_dev *dev){
//************************************************************
// Setup the Parallel Port (Digital Data Interface)
//************************************************************
status = ad9361_reg_write(dev, 0x0010, 0xC8); // I/O Config. Tx Swap IQ; Rx Swap IQ; Tx CH Swap, Rx CH Swap; Rx Frame Mode; 2R2T bit; Invert data bus; Invert DATA_CLK
status = ad9361_reg_write(dev, 0x0010, 0x08); // I/O Config. Tx Swap IQ; Rx Swap IQ; Tx CH Swap, Rx CH Swap; Rx Frame Mode; 2R2T bit; Invert data bus; Invert DATA_CLK
status = ad9361_reg_write(dev, 0x0011, 0x00); // I/O Config. Alt Word Order; -Rx1; -Rx2; -Tx1; -Tx2; Invert Rx Frame; Delay Rx Data
status = ad9361_reg_write(dev, 0x0012, 0x02); // I/O Config. Rx=2*Tx; Swap Ports; SDR; LVDS; Half Duplex; Single Port; Full Port; Swap Bits
status = ad9361_reg_write(dev, 0x0006, 0x00); // PPORT Rx Delay (adjusts Tco Dataclk->Data)
src/dev_profile/ad9361_2_reg_profile.c
+1 -1
View File
@@ -100,7 +100,7 @@ uint32_t ad9361_2_reg_config(struct ad9361_reg_dev *dev){
//************************************************************
// Setup the Parallel Port (Digital Data Interface)
//************************************************************
status = ad9361_reg_write(dev, 0x0010, 0xC8); // I/O Config. Tx Swap IQ; Rx Swap IQ; Tx CH Swap, Rx CH Swap; Rx Frame Mode; 2R2T bit; Invert data bus; Invert DATA_CLK
status = ad9361_reg_write(dev, 0x0010, 0x08); // I/O Config. Tx Swap IQ; Rx Swap IQ; Tx CH Swap, Rx CH Swap; Rx Frame Mode; 2R2T bit; Invert data bus; Invert DATA_CLK
status = ad9361_reg_write(dev, 0x0011, 0x00); // I/O Config. Alt Word Order; -Rx1; -Rx2; -Tx1; -Tx2; Invert Rx Frame; Delay Rx Data
status = ad9361_reg_write(dev, 0x0012, 0x02); // I/O Config. Rx=2*Tx; Swap Ports; SDR; LVDS; Half Duplex; Single Port; Full Port; Swap Bits
status = ad9361_reg_write(dev, 0x0006, 0x00); // PPORT Rx Delay (adjusts Tco Dataclk->Data)