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/******************************************************************************
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*
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* Copyright (C) 2002 - 2018 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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*
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* @file xintc_l.h
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* @addtogroup intc_v3_9
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* @{
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*
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* This header file contains identifiers and low-level driver functions (or
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* macros) that can be used to access the device. The user should refer to the
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* hardware device specification for more details of the device operation.
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*
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*
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* Note that users of the driver interface given in this file can register
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* an interrupt handler dynamically (at run-time) using the
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* XIntc_RegisterHandler() function.
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* User of the driver interface given in xintc.h should still use
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* XIntc_Connect(), as always.
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* Also see the discussion of the interrupt vector tables in xintc.h.
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*
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* There are currently two interrupt handlers specified in this interface.
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*
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* - XIntc_LowLevelInterruptHandler() is a handler without any arguments that
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* is used in cases where there is a single interrupt controller device in
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* the system and the handler cannot be passed an argument. This function is
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* provided mostly for backward compatibility.
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*
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* - XIntc_DeviceInterruptHandler() is a handler that takes a device ID as an
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* argument, indicating which interrupt controller device in the system is
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* causing the interrupt - thereby supporting multiple interrupt controllers.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- -------- -----------------------------------------------------
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* 1.00b jhl 04/24/02 First release
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* 1.00c rpm 10/17/03 New release. Support the static vector table created
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* in the xintc_g.c configuration table.
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* 1.10c mta 03/21/07 Updated to new coding style
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* 1.11a sv 11/21/07 Updated driver to support access through a DCR bridge
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* 2.00a ktn 10/20/09 Updated to use HAL Processor APIs. _m is removed from all
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* the macro definitions.
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* 2.04a bss 01/13/12 Updated for adding defines for IMR and IVAR for
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* the FAST Interrupt
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* 2.05a bss 08/18/12 Added XIntc_RegisterFastHandler API to register fast
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* interrupt handlers using base address.
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* 2.07a bss 10/18/13 Added XIN_ILR_OFFSET macro for nested interrupts.
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* 3.5 sk 11/10/15 Used UINTPTR instead of u32 for Baseaddress CR# 867425.
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* Changed the prototypes of XIntc_RegisterFastHandler,
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* XIntc_SetIntrSvcOption, XIntc_RegisterHandler APIs.
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*
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* </pre>
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*
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******************************************************************************/
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#ifndef XINTC_L_H /* prevent circular inclusions */
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#define XINTC_L_H /* by using protection macros */
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#ifdef __cplusplus
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extern "C" {
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#endif
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/***************************** Include Files *********************************/
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#include "xil_types.h"
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#include "xil_assert.h"
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#include "xparameters.h"
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#include "xil_io.h"
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/*
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* XPAR_XINTC_USE_DCR_BRIDGE has to be set to 1 if the Intc device will be
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* accessed through a DCR bus connected to a bridge.
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*/
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#define XPAR_XINTC_USE_DCR_BRIDGE 0
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#if ((XPAR_XINTC_USE_DCR != 0) || (XPAR_XINTC_USE_DCR_BRIDGE != 0))
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#include "xio_dcr.h"
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#endif
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/************************** Constant Definitions *****************************/
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/* define the offsets from the base address for all the registers of the
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* interrupt controller, some registers may be optional in the hardware device
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*/
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#if ((XPAR_XINTC_USE_DCR != 0) || (XPAR_XINTC_USE_DCR_BRIDGE != 0))
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#define XIN_ISR_OFFSET 0 /* Interrupt Status Register */
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#define XIN_IPR_OFFSET 1 /* Interrupt Pending Register */
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#define XIN_IER_OFFSET 2 /* Interrupt Enable Register */
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#define XIN_IAR_OFFSET 3 /* Interrupt Acknowledge Register */
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#define XIN_SIE_OFFSET 4 /* Set Interrupt Enable Register */
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#define XIN_CIE_OFFSET 5 /* Clear Interrupt Enable Register */
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#define XIN_IVR_OFFSET 6 /* Interrupt Vector Register */
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#define XIN_MER_OFFSET 7 /* Master Enable Register */
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#define XIN_IMR_OFFSET 8 /* Interrupt Mode Register , this is present
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* only for Fast Interrupt */
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#define XIN_IVAR_OFFSET 64 /* Interrupt Vector Address Register
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* Interrupt 0 Offest, this is present
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* only for Fast Interrupt */
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#else /* ((XPAR_XINTC_USE_DCR != 0) || (XPAR_XINTC_USE_DCR_BRIDGE != 0)) */
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#define XIN_ISR_OFFSET 0 /* Interrupt Status Register */
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#define XIN_IPR_OFFSET 4 /* Interrupt Pending Register */
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#define XIN_IER_OFFSET 8 /* Interrupt Enable Register */
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#define XIN_IAR_OFFSET 12 /* Interrupt Acknowledge Register */
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#define XIN_SIE_OFFSET 16 /* Set Interrupt Enable Register */
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#define XIN_CIE_OFFSET 20 /* Clear Interrupt Enable Register */
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#define XIN_IVR_OFFSET 24 /* Interrupt Vector Register */
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#define XIN_MER_OFFSET 28 /* Master Enable Register */
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#define XIN_IMR_OFFSET 32 /* Interrupt Mode Register , this is present
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* only for Fast Interrupt */
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#define XIN_ILR_OFFSET 36 /* Interrupt level register */
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#define XIN_IVAR_OFFSET 0x100 /* Interrupt Vector Address Register
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* Interrupt 0 Offest, this is present
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* only for Fast Interrupt */
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#define XIN_IVEAR_OFFSET 0x200 /* Interrupt Vector Extended Address
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Register */
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#endif /* ((XPAR_XINTC_USE_DCR != 0) || (XPAR_XINTC_USE_DCR_BRIDGE != 0)) */
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/* Bit definitions for the bits of the MER register */
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#define XIN_INT_MASTER_ENABLE_MASK 0x1UL
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#define XIN_INT_HARDWARE_ENABLE_MASK 0x2UL /* once set cannot be cleared */
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/**************************** Type Definitions *******************************/
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/* The following data type defines each entry in an interrupt vector table.
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* The callback reference is the base address of the interrupting device
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* for the driver interface given in this file and an instance pointer for the
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* driver interface given in xintc.h file.
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*/
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typedef struct {
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XInterruptHandler Handler;
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void *CallBackRef;
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} XIntc_VectorTableEntry;
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typedef void (*XFastInterruptHandler) (void);
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/***************** Macros (Inline Functions) Definitions *********************/
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/*
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* Define the appropriate I/O access method to memory mapped I/O or DCR.
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*/
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#if ((XPAR_XINTC_USE_DCR != 0) || (XPAR_XINTC_USE_DCR_BRIDGE != 0))
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#define XIntc_In32 XIo_DcrIn
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#define XIntc_Out32 XIo_DcrOut
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#else
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#define XIntc_In32 Xil_In32
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#define XIntc_Out32 Xil_Out32
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#define XIntc_Out64 Xil_Out64
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#endif
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/****************************************************************************/
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/**
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*
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* Enable all interrupts in the Master Enable register of the interrupt
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* controller. The interrupt controller defaults to all interrupts disabled
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* from reset such that this macro must be used to enable interrupts.
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*
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* @param BaseAddress is the base address of the device.
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*
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* @return None.
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*
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* @note C-style signature:
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* void XIntc_MasterEnable(u32 BaseAddress);
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*
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*****************************************************************************/
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#define XIntc_MasterEnable(BaseAddress) \
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XIntc_Out32((BaseAddress) + XIN_MER_OFFSET, \
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XIN_INT_MASTER_ENABLE_MASK | XIN_INT_HARDWARE_ENABLE_MASK)
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/****************************************************************************/
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/**
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*
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* Disable all interrupts in the Master Enable register of the interrupt
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* controller.
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*
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* @param BaseAddress is the base address of the device.
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*
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* @return None.
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*
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* @note C-style signature:
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* void XIntc_MasterDisable(u32 BaseAddress);
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*
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*****************************************************************************/
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#define XIntc_MasterDisable(BaseAddress) \
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XIntc_Out32((BaseAddress) + XIN_MER_OFFSET, 0)
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/****************************************************************************/
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/**
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*
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* Enable specific interrupt(s) in the interrupt controller.
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*
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* @param BaseAddress is the base address of the device
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* @param EnableMask is the 32-bit value to write to the enable register.
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* Each bit of the mask corresponds to an interrupt input signal
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* that is connected to the interrupt controller (INT0 = LSB).
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* Only the bits which are set in the mask will enable interrupts.
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*
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* @return None.
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*
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* @note C-style signature:
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* void XIntc_EnableIntr(u32 BaseAddress, u32 EnableMask);
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*
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*****************************************************************************/
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#define XIntc_EnableIntr(BaseAddress, EnableMask) \
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XIntc_Out32((BaseAddress) + XIN_IER_OFFSET, (EnableMask))
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/****************************************************************************/
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/**
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*
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* Disable specific interrupt(s) in the interrupt controller.
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*
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* @param BaseAddress is the base address of the device
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* @param DisableMask is the 32-bit value to write to the enable register.
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* Each bit of the mask corresponds to an interrupt input signal
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* that is connected to the interrupt controller (INT0 = LSB).
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* Only the bits which are set in the mask will disable interrupts.
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*
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* @return None.
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*
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* @note C-style signature:
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* void XIntc_DisableIntr(u32 BaseAddress, u32 DisableMask);
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*
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*****************************************************************************/
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#define XIntc_DisableIntr(BaseAddress, DisableMask) \
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XIntc_Out32((BaseAddress) + XIN_IER_OFFSET, ~(DisableMask))
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/****************************************************************************/
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/**
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*
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* Acknowledge specific interrupt(s) in the interrupt controller.
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*
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* @param BaseAddress is the base address of the device
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* @param AckMask is the 32-bit value to write to the acknowledge
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* register. Each bit of the mask corresponds to an interrupt input
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* signal that is connected to the interrupt controller (INT0 =
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* LSB). Only the bits which are set in the mask will acknowledge
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* interrupts.
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*
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* @return None.
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*
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* @note C-style signature:
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* void XIntc_AckIntr(u32 BaseAddress, u32 AckMask);
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*
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*****************************************************************************/
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#define XIntc_AckIntr(BaseAddress, AckMask) \
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XIntc_Out32((BaseAddress) + XIN_IAR_OFFSET, (AckMask))
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/****************************************************************************/
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/**
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*
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* Get the interrupt status from the interrupt controller which indicates
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* which interrupts are active and enabled.
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*
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* @param BaseAddress is the base address of the device
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*
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* @return The 32-bit contents of the interrupt status register. Each bit
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* corresponds to an interrupt input signal that is connected to
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* the interrupt controller (INT0 = LSB). Bits which are set
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* indicate an active interrupt which is also enabled.
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*
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* @note C-style signature:
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* u32 XIntc_GetIntrStatus(u32 BaseAddress);
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*
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*****************************************************************************/
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#define XIntc_GetIntrStatus(BaseAddress) \
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(XIntc_In32((BaseAddress) + XIN_ISR_OFFSET) & \
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XIntc_In32((BaseAddress) + XIN_IER_OFFSET))
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/************************** Function Prototypes ******************************/
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/*
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* Interrupt controller handlers, to be connected to processor exception
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* handling code.
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*/
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void XIntc_LowLevelInterruptHandler(void);
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void XIntc_DeviceInterruptHandler(void *DeviceId);
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/* Various configuration functions */
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void XIntc_SetIntrSvcOption(UINTPTR BaseAddress, int Option);
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void XIntc_RegisterHandler(UINTPTR BaseAddress, int InterruptId,
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XInterruptHandler Handler, void *CallBackRef);
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void XIntc_RegisterFastHandler(UINTPTR BaseAddress, u8 Id,
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XFastInterruptHandler FastHandler);
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/************************** Variable Definitions *****************************/
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#ifdef __cplusplus
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}
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#endif
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#endif /* end of protection macro */
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/** @} */
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