278 lines
7.9 KiB
C
278 lines
7.9 KiB
C
/*****************************************************************************/
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/**
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* Description: Physical layer register definitions
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*
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* Author: Fan Hao
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* Date: 2021-11-16 00:08
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* LastEditors: Fan Hao
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* LastEditTime: 2022-06-18 17:32
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* Revisions: Rev 0.0
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* History:
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* [2021-11-16]: Initial version.
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* [2022-06-18]: New branch for glink control purpose:
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* -Add poll modephysical layer will start Tx/Rx procedure
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* at specific time stamp.
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*
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* Copyright(c) 2021 Beijing Institute of Technology.
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* Lab of Communication and Networking
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*
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******************************************************************************/
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#ifndef PHY_REG_H_
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#define PHY_REG_H_
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/***************************** Include Files *********************************/
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#include "../util/util.h"
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/***************** Macros (Inline Functions) Definitions *********************/
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#define PhyRead(instPtr, addr) IO_In32(instPtr->phyCofig.baseAddr + addr)
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#define PhyWrite(instPtr, addr, value) IO_Out32(instPtr->phyCofig.baseAddr + addr, value)
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/************************** Constant Definitions *****************************/
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/**
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* Register: PHY_MAIN_CTRL
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*/
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#define PHY_MAIN_CTRL 0X00000000U
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#define PHY_MAIN_CTRL_EN_SHIFT 0
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#define PHY_MAIN_CTRL_EN_WIDTH 1
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#define PHY_MAIN_CTRL_EN_MASK 0x00000001U
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#define PHY_MAIN_CTRL_MODE_SHIFT 8
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#define PHY_MAIN_CTRL_MODE_WIDTH 8
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#define PHY_MAIN_CTRL_MODE_MASK 0x0000FF00U
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#define PHY_MAIN_CTRL_EN_EN 0x00000001U
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#define PHY_MAIN_CTRL_EN_DSBL 0x00000000U
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#define PHY_MAIN_CTRL_MODE_NONE 0x00000000U
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#define PHY_MAIN_CTRL_MODE_LISTEN 0x00000100U
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#define PHY_MAIN_CTRL_MODE_SCHEDULE 0x00000200U
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#define PHY_MAIN_CTRL_MODE_PULL 0x00000300U
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/**
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* Register: TXRX_CTRL
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*/
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#define PHY_MODE_CTRL 0x00000004U
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#define PHY_MODE_CTRL_TOR_SHIFT 0
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#define PHY_MODE_CTRL_TOR_WIDTH 8
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#define PHY_MODE_CTRL_TOR_MASK 0x000000FFU
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#define PHY_MODE_CTRL_FRAME_SHIFT 8
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#define PHY_MODE_CTRL_FRAME_WIDTH 8
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#define PHY_MODE_CTRL_FRAME_MASK 0x0000FF00U
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#define PHY_MODE_CTRL_CRC_SHIFT 8
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#define PHY_MODE_CTRL_CRC_WIDTH 16
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#define PHY_MODE_CTRL_CRC_MASK 0x00FF0000U
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#define PHY_MODE_CTRL_TOR_SUSPEND 0x00000000U
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#define PHY_MODE_CTRL_TOR_TX 0x00000001U
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#define PHY_MODE_CTRL_TOR_RX 0x00000002U
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#define PHY_MODE_CTRL_FRAME_NONE 0x00000000U
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#define PHY_MODE_CTRL_FRAME_2KBPS_20MS 0x00000100U
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#define PHY_MODE_CTRL_FRAME_2KBPS_100MS 0x00000200U
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#define PHY_MODE_CTRL_FRAME_10KBPS_10MS 0x00000300U // Initial Scan Frame
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#define PHY_MODE_CTRL_FRAME_10KBPS_20MS 0x00000400U // Benchmark Frame
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#define PHY_MODE_CTRL_FRAME_40KBPS_20MS 0x00000500U
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#define PHY_MODE_CTRL_FRAME_40KBPS_10MS 0x00000600U
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#define PHY_MODE_CTRL_FRAME_200KBPS_5MS 0x00000700U // 2-Way ACQ Frame, Management Frame, Service Frame
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#define PHY_MODE_CTRL_FRAME_1M2BPS_5MS 0x00000800U // Bistatic Synthetic Aperture Radar Frame
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#define PHY_MODE_CTRL_CRC_EN 0x00010000U
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#define PHY_MODE_CTRL_CRC_DSBL 0x00000000U
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/**
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* Register: POLLTIME_L
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*/
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#define POLLTIME_L 0x00000008U
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#define POLLTIME_L_SHIFT 0
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#define POLLTIME_L_WIDTH 32
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#define POLLTIME_L_MASK 0xFFFFFFFFU
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/**
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* Register: POLLTIME_H
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*/
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#define POLLTIME_H 0x0000000CU
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#define POLLTIME_H_SHIFT 0
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#define POLLTIME_H_WIDTH 32
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#define POLLTIME_H_MASK 0xFFFFFFFFU
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/**
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* Register: TIMEOUT_L
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*/
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#define LISTENTIMEOUT_L 0x00000010U
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#define LISTENTIMEOUT_L_SHIFT 0
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#define LISTENTIMEOUT_L_WIDTH 32
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#define LISTENTIMEOUT_L_MASK 0xFFFFFFFFU
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/**
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* Register: TIMEOUT_H
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*/
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#define LISTENTIMEOUT_H 0x00000014U
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#define LISTENTIMEOUT_H_SHIFT 0
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#define LISTENTIMEOUT_H_WIDTH 32
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#define LISTENTIMEOUT_H_MASK 0xFFFFFFFFU
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/**
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* Register: ANT_CTRL
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*/
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#define ANT_CONFIG 0x00000018U
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#define ANT_CONFIG_OFFSET_SHIFT 0
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#define ANT_CONFIG_OFFSET_WIDTH 16
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#define ANT_CONFIG_OFFSET_MASK 0x0000FFFFU
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#define ANT_CONFIG_LEN_SHIFT 16
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#define ANT_CONFIG_LEN_WIDTH 8
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#define ANT_CONFIG_LEN_MASK 0x00FF0000U
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#define ANT_CONFIG_NUM_SHIFT 24
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#define ANT_CONFIG_NUM_WIDTH 8
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#define ANT_CONFIG_NUM_MASK 0xFF000000U
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/**
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* Register: SEND_DATA_CMD
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*/
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#define SEND_DATA_CMD 0x0000001CU
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#define SEND_DATA_CMD_SHIFT 0
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#define SEND_DATA_CMD_WIDTH 32
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#define SEND_DATA_CMD_MASK 0xFFFFFFFFU
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#define SEND_DATA_CMD_LEN_SHIFT 0
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#define SEND_DATA_CMD_LEN_WIDTH 16
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#define SEND_DATA_CMD_LEN_MASK 0x0000FFFFU
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#define SEND_DATA_CMD_OFFSET_SHIFT 16
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#define SEND_DATA_CMD_OFFSET_WIDTH 16
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#define SEND_DATA_CMD_OFFSET_MASK 0xFFFF0000U
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/**
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* Register: SLOT_CONFIG_CMD
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*/
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#define SLOT_CMD 0x00000020U
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#define SLOT_CMD_SHIFT 0
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#define SLOT_CMD_WIDTH 32
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#define SLOT_CMD_MASK 0xFFFFFFFFU
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#define SLOT_CMD_KEY 0x434D442EU
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/**
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* Register: TXRX_STATE
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*/
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#define TXRX_STATE 0x00000024U
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#define TXRX_STATE_ACQ_SHIFT 0
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#define TXRX_STATE_ACQ_WIDTH 8
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#define TXRX_STATE_ACQ_MASK 0x000000FFU
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#define TXRX_STATE_ACQ_SUCCESS 0x00000001U
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#define TXRX_STATE_ACQ_FAIL 0x00000002U
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#define TXRX_STATE_FSYNC_SHIFT 8
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#define TXRX_STATE_FSYNC_WIDTH 8
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#define TXRX_STATE_FSYNC_MASK 0x0000FF00U
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#define TXRX_STATE_FSYNC_SUCCESS 0x00000100U
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#define TXRX_STATE_FSYNC_FAIL 0x00000200U
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#define TXRX_STATE_DECODE_SHIFT 16
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#define TXRX_STATE_DECODE_WIDTH 8
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#define TXRX_STATE_DECODE_MASK 0x00FF0000U
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#define TXRX_STATE_DECODE_SUCCESS 0x00010000U
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#define TXRX_STATE_DECODE_FAIL 0x00020000U
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#define TXRX_STATE_CRC_SHIFT 24
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#define TXRX_STATE_CRC_WIDTH 8
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#define TXRX_STATE_CRC_MASK 0xFF000000U
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#define TXRX_STATE_CRC_OK 0x01000000U
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#define TXRX_STATE_CRC_ERROR 0x02000000U
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/**
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* Register: RECVDATA_STATE
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*/
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#define RECVDATA_STATE 0x00000028U
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#define RECVDATA_STATE_LEN_SHIFT 0
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#define RECVDATA_STATE_LEN_WIDTH 16
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#define RECVDATA_STATE_LEN_MASK 0x0000FFFFU
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#define RECVDATA_STATE_OFFSET_SHIFT 16
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#define RECVDATA_STATE_OFFSET_WIDTH 16
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#define RECVDATA_STATE_OFFSET_MASK 0xFFFF0000U
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/**
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* Register: FSTIME_L
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*/
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#define FSTIME_L 0x0000002CU
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#define FSTIME_L_SHIFT 0
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#define FSTIME_L_WIDTH 32
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#define FSTIME_L_MASK 0xFFFFFFFFU
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/**
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* Register: FSTIME_INT1
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*/
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#define FSTIME_H 0x00000030U
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#define FSTIME_H_SHIFT 0
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#define FSTIME_H_WIDTH 32
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#define FSTIME_H_MASK 0xFFFFFFFFU
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/**
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* Register: TM_TARGET_L
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*/
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#define TM_TARGET_L 0x00000064U
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#define TM_TARGET_L_SHIFT 0
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#define TM_TARGET_L_WIDTH 32
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#define TM_TARGET_L_MASK 0xFFFFFFFFU
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/**
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* Register: TM_TARGET_H
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*/
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#define TM_TARGET_H 0x00000038U
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#define TM_TARGET_H_SHIFT 0
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#define TM_TARGET_H_WIDTH 32
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#define TM_TARGET_H_MASK 0xFFFFFFFFU
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/**
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* Register: COASEFREQEST
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*/
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#define COASE_FREQEST 0x0000003CU
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#define COASE_FREQEST_ACQ_SHIFT 0
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#define COASE_FREQEST_ACQ_WIDTH 8
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#define COASE_FREQEST_ACQ_MASK 0x000000FFU
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#define COASE_FREQEST_SYNC_SHIFT 8
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#define COASE_FREQEST_SYNC_WIDTH 8
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#define COASE_FREQEST_SYNC_MASK 0x0000FF00U
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#define COASE_TYPE_SHIFT 16
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#define COASE_TYPE_WIDTH 8
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#define COASE_TYPE_MASK 0x00FF0000U
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#define COASE_TYPE_2KBPS_20MS 0x00010000U
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#define COASE_TYPE_2KBPS_100MS 0x00020000U
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#define COASE_TYPE_10KBPS_10MS 0x00030000U
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#define COASE_TYPE_10KBPS_20MS 0x00040000U
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#define COASE_TYPE_40KBPS_20MS 0x00050000U
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#define COASE_TYPE_40KBPS_10MS 0x00060000U
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#define COASE_TYPE_200KBPS_5MS 0x00070000U
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#define COASE_TYPE_1M2BPS_5MS 0x00080000U
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/**
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* Register: FINE_FREQEST
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*/
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#define FINE_FREQEST 0x00000040U
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#define FINE_FREQEST_VAL_SHIFT 0
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#define FINE_FREQEST_VAL_WIDTH 24
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#define FINE_FREQEST_VAL_MASK 0x00FFFFFFU
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#define FINE_FREQEST_SIGN_SHIFT 24
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#define FINE_FREQEST_SIGN_WIDTH 8
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#define FINE_FREQEST_SIGN_MASK 0xFF000000U
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#define FINE_FREQEST_SIGN_POS 0x00000000U
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#define FINE_FREQEST_SIGN_NEG 0x01000000U
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/**
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* Register: BEAM_SELECT
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*/
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#define BEAM_SELECT_INDEX 0x00000044U
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#define BEAM_SELECT_INDEX_SHIFT 0
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#define BEAM_SELECT_INDEX_WIDTH 32
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#define BEAM_SELECT_INDEX_MASK 0xFFFFFFFFU
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/**
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* Register: BEAM_AXIS
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*/
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#define BEAM_AXIS 0x00000044U
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#define BEAM_AXIS_EL_SHIFT 0
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#define BEAM_AXIS_EL_WIDTH 16
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#define BEAM_AXIS_EL_MASK 0x0000FFFFU
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#define BEAM_AXIS_AZ_SHIFT 16
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#define BEAM_AXIS_AZ_WIDTH 16
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#define BEAM_AXIS_AZ_MASK 0xFFFF0000U
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// Reserved.
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#endif /* PHY_REG_H_ */
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