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add antenna bram control

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This commit is contained in:
Gatsby Van
2024-03-01 19:25:33 +08:00
parent 8be194a410
commit 0c270df599
4 changed files with 77 additions and 16 deletions
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df_datalink_sp/bsp/ps7_cortexa9_0/include/xparameters.h
+51 -16
View File
@@ -42,10 +42,28 @@
/******************************************************************/ /******************************************************************/
/* Definitions for driver BRAM */ /* Definitions for driver BRAM */
#define XPAR_XBRAM_NUM_INSTANCES 3U #define XPAR_XBRAM_NUM_INSTANCES 4U
/* Definitions for peripheral PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL */
#define XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_DEVICE_ID 0U
#define XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_DATA_WIDTH 32U
#define XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_ECC 0U
#define XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_FAULT_INJECT 0U
#define XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_CE_FAILING_REGISTERS 0U
#define XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_UE_FAILING_REGISTERS 0U
#define XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_ECC_STATUS_REGISTERS 0U
#define XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_CE_COUNTER_WIDTH 0U
#define XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_ECC_ONOFF_REGISTER 0U
#define XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_ECC_ONOFF_RESET_VALUE 0U
#define XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_WRITE_ACCESS 0U
#define XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_S_AXI_BASEADDR 0x42000000U
#define XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_S_AXI_HIGHADDR 0x42000FFFU
#define XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_S_AXI_CTRL_BASEADDR 0xFFFFFFFFU
#define XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_S_AXI_CTRL_HIGHADDR 0xFFFFFFFFU
/* Definitions for peripheral PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL */ /* Definitions for peripheral PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL */
#define XPAR_PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL_DEVICE_ID 0U #define XPAR_PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL_DEVICE_ID 1U
#define XPAR_PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL_DATA_WIDTH 32U #define XPAR_PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL_DATA_WIDTH 32U
#define XPAR_PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL_ECC 0U #define XPAR_PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL_ECC 0U
#define XPAR_PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL_FAULT_INJECT 0U #define XPAR_PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL_FAULT_INJECT 0U
@@ -63,7 +81,7 @@
/* Definitions for peripheral PHY_DATA_INTERFACE_RX_FRAME_BRAM_CTRL */ /* Definitions for peripheral PHY_DATA_INTERFACE_RX_FRAME_BRAM_CTRL */
#define XPAR_PHY_DATA_INTERFACE_RX_FRAME_BRAM_CTRL_DEVICE_ID 1U #define XPAR_PHY_DATA_INTERFACE_RX_FRAME_BRAM_CTRL_DEVICE_ID 2U
#define XPAR_PHY_DATA_INTERFACE_RX_FRAME_BRAM_CTRL_DATA_WIDTH 32U #define XPAR_PHY_DATA_INTERFACE_RX_FRAME_BRAM_CTRL_DATA_WIDTH 32U
#define XPAR_PHY_DATA_INTERFACE_RX_FRAME_BRAM_CTRL_ECC 0U #define XPAR_PHY_DATA_INTERFACE_RX_FRAME_BRAM_CTRL_ECC 0U
#define XPAR_PHY_DATA_INTERFACE_RX_FRAME_BRAM_CTRL_FAULT_INJECT 0U #define XPAR_PHY_DATA_INTERFACE_RX_FRAME_BRAM_CTRL_FAULT_INJECT 0U
@@ -81,7 +99,7 @@
/* Definitions for peripheral PHY_DATA_INTERFACE_TX_FRAME_BRAM_CTRL */ /* Definitions for peripheral PHY_DATA_INTERFACE_TX_FRAME_BRAM_CTRL */
#define XPAR_PHY_DATA_INTERFACE_TX_FRAME_BRAM_CTRL_DEVICE_ID 2U #define XPAR_PHY_DATA_INTERFACE_TX_FRAME_BRAM_CTRL_DEVICE_ID 3U
#define XPAR_PHY_DATA_INTERFACE_TX_FRAME_BRAM_CTRL_DATA_WIDTH 32U #define XPAR_PHY_DATA_INTERFACE_TX_FRAME_BRAM_CTRL_DATA_WIDTH 32U
#define XPAR_PHY_DATA_INTERFACE_TX_FRAME_BRAM_CTRL_ECC 0U #define XPAR_PHY_DATA_INTERFACE_TX_FRAME_BRAM_CTRL_ECC 0U
#define XPAR_PHY_DATA_INTERFACE_TX_FRAME_BRAM_CTRL_FAULT_INJECT 0U #define XPAR_PHY_DATA_INTERFACE_TX_FRAME_BRAM_CTRL_FAULT_INJECT 0U
@@ -100,8 +118,8 @@
/******************************************************************/ /******************************************************************/
/* Canonical definitions for peripheral PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL */ /* Canonical definitions for peripheral PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL */
#define XPAR_BRAM_0_DEVICE_ID XPAR_PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL_DEVICE_ID #define XPAR_BRAM_0_DEVICE_ID XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_DEVICE_ID
#define XPAR_BRAM_0_DATA_WIDTH 32U #define XPAR_BRAM_0_DATA_WIDTH 32U
#define XPAR_BRAM_0_ECC 0U #define XPAR_BRAM_0_ECC 0U
#define XPAR_BRAM_0_FAULT_INJECT 0U #define XPAR_BRAM_0_FAULT_INJECT 0U
@@ -112,13 +130,13 @@
#define XPAR_BRAM_0_ECC_ONOFF_REGISTER 0U #define XPAR_BRAM_0_ECC_ONOFF_REGISTER 0U
#define XPAR_BRAM_0_ECC_ONOFF_RESET_VALUE 0U #define XPAR_BRAM_0_ECC_ONOFF_RESET_VALUE 0U
#define XPAR_BRAM_0_WRITE_ACCESS 0U #define XPAR_BRAM_0_WRITE_ACCESS 0U
#define XPAR_BRAM_0_BASEADDR 0x40004000U #define XPAR_BRAM_0_BASEADDR 0x42000000U
#define XPAR_BRAM_0_HIGHADDR 0x40005FFFU #define XPAR_BRAM_0_HIGHADDR 0x42000FFFU
#define XPAR_BRAM_0_CTRL_BASEADDR 0xFFFFFFFFU #define XPAR_BRAM_0_CTRL_BASEADDR 0xFFFFFFFFU
#define XPAR_BRAM_0_CTRL_HIGHADDR 0xFFFFFFFEU #define XPAR_BRAM_0_CTRL_HIGHADDR 0xFFFFFFFEU
/* Canonical definitions for peripheral PHY_DATA_INTERFACE_RX_FRAME_BRAM_CTRL */ /* Canonical definitions for peripheral PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL */
#define XPAR_BRAM_1_DEVICE_ID XPAR_PHY_DATA_INTERFACE_RX_FRAME_BRAM_CTRL_DEVICE_ID #define XPAR_BRAM_1_DEVICE_ID XPAR_PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL_DEVICE_ID
#define XPAR_BRAM_1_DATA_WIDTH 32U #define XPAR_BRAM_1_DATA_WIDTH 32U
#define XPAR_BRAM_1_ECC 0U #define XPAR_BRAM_1_ECC 0U
#define XPAR_BRAM_1_FAULT_INJECT 0U #define XPAR_BRAM_1_FAULT_INJECT 0U
@@ -129,13 +147,13 @@
#define XPAR_BRAM_1_ECC_ONOFF_REGISTER 0U #define XPAR_BRAM_1_ECC_ONOFF_REGISTER 0U
#define XPAR_BRAM_1_ECC_ONOFF_RESET_VALUE 0U #define XPAR_BRAM_1_ECC_ONOFF_RESET_VALUE 0U
#define XPAR_BRAM_1_WRITE_ACCESS 0U #define XPAR_BRAM_1_WRITE_ACCESS 0U
#define XPAR_BRAM_1_BASEADDR 0x40000000U #define XPAR_BRAM_1_BASEADDR 0x40004000U
#define XPAR_BRAM_1_HIGHADDR 0x40001FFFU #define XPAR_BRAM_1_HIGHADDR 0x40005FFFU
#define XPAR_BRAM_1_CTRL_BASEADDR 0xFFFFFFFFU #define XPAR_BRAM_1_CTRL_BASEADDR 0xFFFFFFFFU
#define XPAR_BRAM_1_CTRL_HIGHADDR 0xFFFFFFFEU #define XPAR_BRAM_1_CTRL_HIGHADDR 0xFFFFFFFEU
/* Canonical definitions for peripheral PHY_DATA_INTERFACE_TX_FRAME_BRAM_CTRL */ /* Canonical definitions for peripheral PHY_DATA_INTERFACE_RX_FRAME_BRAM_CTRL */
#define XPAR_BRAM_2_DEVICE_ID XPAR_PHY_DATA_INTERFACE_TX_FRAME_BRAM_CTRL_DEVICE_ID #define XPAR_BRAM_2_DEVICE_ID XPAR_PHY_DATA_INTERFACE_RX_FRAME_BRAM_CTRL_DEVICE_ID
#define XPAR_BRAM_2_DATA_WIDTH 32U #define XPAR_BRAM_2_DATA_WIDTH 32U
#define XPAR_BRAM_2_ECC 0U #define XPAR_BRAM_2_ECC 0U
#define XPAR_BRAM_2_FAULT_INJECT 0U #define XPAR_BRAM_2_FAULT_INJECT 0U
@@ -146,11 +164,28 @@
#define XPAR_BRAM_2_ECC_ONOFF_REGISTER 0U #define XPAR_BRAM_2_ECC_ONOFF_REGISTER 0U
#define XPAR_BRAM_2_ECC_ONOFF_RESET_VALUE 0U #define XPAR_BRAM_2_ECC_ONOFF_RESET_VALUE 0U
#define XPAR_BRAM_2_WRITE_ACCESS 0U #define XPAR_BRAM_2_WRITE_ACCESS 0U
#define XPAR_BRAM_2_BASEADDR 0x40002000U #define XPAR_BRAM_2_BASEADDR 0x40000000U
#define XPAR_BRAM_2_HIGHADDR 0x40003FFFU #define XPAR_BRAM_2_HIGHADDR 0x40001FFFU
#define XPAR_BRAM_2_CTRL_BASEADDR 0xFFFFFFFFU #define XPAR_BRAM_2_CTRL_BASEADDR 0xFFFFFFFFU
#define XPAR_BRAM_2_CTRL_HIGHADDR 0xFFFFFFFEU #define XPAR_BRAM_2_CTRL_HIGHADDR 0xFFFFFFFEU
/* Canonical definitions for peripheral PHY_DATA_INTERFACE_TX_FRAME_BRAM_CTRL */
#define XPAR_BRAM_3_DEVICE_ID XPAR_PHY_DATA_INTERFACE_TX_FRAME_BRAM_CTRL_DEVICE_ID
#define XPAR_BRAM_3_DATA_WIDTH 32U
#define XPAR_BRAM_3_ECC 0U
#define XPAR_BRAM_3_FAULT_INJECT 0U
#define XPAR_BRAM_3_CE_FAILING_REGISTERS 0U
#define XPAR_BRAM_3_UE_FAILING_REGISTERS 0U
#define XPAR_BRAM_3_ECC_STATUS_REGISTERS 0U
#define XPAR_BRAM_3_CE_COUNTER_WIDTH 0U
#define XPAR_BRAM_3_ECC_ONOFF_REGISTER 0U
#define XPAR_BRAM_3_ECC_ONOFF_RESET_VALUE 0U
#define XPAR_BRAM_3_WRITE_ACCESS 0U
#define XPAR_BRAM_3_BASEADDR 0x40002000U
#define XPAR_BRAM_3_HIGHADDR 0x40003FFFU
#define XPAR_BRAM_3_CTRL_BASEADDR 0xFFFFFFFFU
#define XPAR_BRAM_3_CTRL_HIGHADDR 0xFFFFFFFEU
/******************************************************************/ /******************************************************************/
df_datalink_sp/bsp/ps7_cortexa9_0/libsrc/bram_v4_3/src/xbram_g.c
+19
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@@ -42,6 +42,25 @@
XBram_Config XBram_ConfigTable[] = XBram_Config XBram_ConfigTable[] =
{ {
{
XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_DEVICE_ID,
XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_DATA_WIDTH,
XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_ECC,
XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_FAULT_INJECT,
XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_CE_FAILING_REGISTERS,
0,
XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_UE_FAILING_REGISTERS,
0,
XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_ECC_STATUS_REGISTERS,
XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_CE_COUNTER_WIDTH,
XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_ECC_ONOFF_REGISTER,
XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_ECC_ONOFF_RESET_VALUE,
XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_WRITE_ACCESS,
XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_S_AXI_BASEADDR,
XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_S_AXI_HIGHADDR,
XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_S_AXI_CTRL_BASEADDR,
XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_S_AXI_CTRL_HIGHADDR
},
{ {
XPAR_PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL_DEVICE_ID, XPAR_PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL_DEVICE_ID,
XPAR_PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL_DATA_WIDTH, XPAR_PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL_DATA_WIDTH,
df_datalink_sp/bsp/system.mss
+6
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@@ -24,6 +24,12 @@ BEGIN DRIVER
PARAMETER HW_INSTANCE = axi_spi_engine_axi_spi_engine PARAMETER HW_INSTANCE = axi_spi_engine_axi_spi_engine
END END
BEGIN DRIVER
PARAMETER DRIVER_NAME = bram
PARAMETER DRIVER_VER = 4.3
PARAMETER HW_INSTANCE = phy_data_interface_ant_beam_bram_ctrl
END
BEGIN DRIVER BEGIN DRIVER
PARAMETER DRIVER_NAME = bram PARAMETER DRIVER_NAME = bram
PARAMETER DRIVER_VER = 4.3 PARAMETER DRIVER_VER = 4.3
df_datalink_sp/src/lscript.ld
+1
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@@ -26,6 +26,7 @@ MEMORY
phy_data_interface_rx_frame_bram_ctrl_Mem0 : ORIGIN = 0x40000000, LENGTH = 0x2000 phy_data_interface_rx_frame_bram_ctrl_Mem0 : ORIGIN = 0x40000000, LENGTH = 0x2000
phy_data_interface_tx_frame_bram_ctrl_Mem0 : ORIGIN = 0x40002000, LENGTH = 0x2000 phy_data_interface_tx_frame_bram_ctrl_Mem0 : ORIGIN = 0x40002000, LENGTH = 0x2000
phy_data_interface_ant_info_bram_ctrl_Mem0 : ORIGIN = 0x40004000, LENGTH = 0x2000 phy_data_interface_ant_info_bram_ctrl_Mem0 : ORIGIN = 0x40004000, LENGTH = 0x2000
phy_data_interface_ant_beam_bram_ctrl_Mem0 : ORIGIN = 0x42000000, LENGTH = 0x1000
ps7_ddr_0 : ORIGIN = 0x100000, LENGTH = 0x1FF00000 ps7_ddr_0 : ORIGIN = 0x100000, LENGTH = 0x1FF00000
ps7_qspi_linear_0 : ORIGIN = 0xFC000000, LENGTH = 0x1000000 ps7_qspi_linear_0 : ORIGIN = 0xFC000000, LENGTH = 0x1000000
ps7_ram_0 : ORIGIN = 0x0, LENGTH = 0x30000 ps7_ram_0 : ORIGIN = 0x0, LENGTH = 0x30000