add register status code

This commit is contained in:
Gatsby Van
2024-01-31 20:10:15 +08:00
parent 3a99da8b76
commit 223a772582
@@ -281,15 +281,22 @@
#define ANT_STATUS_CODE_SHIFT 0 #define ANT_STATUS_CODE_SHIFT 0
#define ANT_STATUS_CODE_WIDTH 8 #define ANT_STATUS_CODE_WIDTH 8
#define ANT_STATUS_CODE_MASK 0x000000FFU #define ANT_STATUS_CODE_MASK 0x000000FFU
#define ANT_STATUS_CODE_OK 0x00000001U
#define ANT_STATUS_NIL_VOLT_SHIFT 8 #define ANT_STATUS_NIL_VOLT_SHIFT 8
#define ANT_STATUS_NIL_VOLT_WIDTH 8 #define ANT_STATUS_NIL_VOLT_WIDTH 8
#define ANT_STATUS_NIL_VOLT_MASK 0x0000FF00U #define ANT_STATUS_NIL_VOLT_MASK 0x0000FF00U
#define ANT_STATUS_NIL_VOLT_OK 0x00000100U
#define ANT_STATUS_RF_VOLT_SHIFT 16 #define ANT_STATUS_RF_VOLT_SHIFT 16
#define ANT_STATUS_RF_VOLT_WIDTH 8 #define ANT_STATUS_RF_VOLT_WIDTH 8
#define ANT_STATUS_RF_VOLT_MASK 0x00FF0000U #define ANT_STATUS_RF_VOLT_MASK 0x00FF0000U
#define ANT_STATUS_RF_VOLT_OK 0x00010000U
#define ANT_STATUS_ANT_VOLT_SHIFT 24 #define ANT_STATUS_ANT_VOLT_SHIFT 24
#define ANT_STATUS_ANT_VOLT_WIDTH 8 #define ANT_STATUS_ANT_VOLT_WIDTH 8
#define ANT_STATUS_ANT_VOLT_MASK 0xFF000000U #define ANT_STATUS_ANT_VOLT_MASK 0xFF000000U
#define ANT_STATUS_ANT_VOLT_OK 0x01000000U
/** /**
* Register: ANT_FRAME_CNT * Register: ANT_FRAME_CNT
@@ -306,15 +313,21 @@
#define ANT_RF_STATUS_TEMP_SHIFT 0 #define ANT_RF_STATUS_TEMP_SHIFT 0
#define ANT_RF_STATUS_TEMP_WIDTH 8 #define ANT_RF_STATUS_TEMP_WIDTH 8
#define ANT_RF_STATUS_TEMP_MASK 0x000000FFU #define ANT_RF_STATUS_TEMP_MASK 0x000000FFU
#define ANT_RF_STATUS_BDLOCK_SHIFT 8
#define ANT_RF_STATUS_BDLOCK_WIDTH 8 #define ANT_RF_STATUS_BBLOCK_SHIFT 8
#define ANT_RF_STATUS_BDLOCK_MASK 0x0000FF00U #define ANT_RF_STATUS_BBLOCK_WIDTH 8
#define ANT_RF_STATUS_BBLOCK_MASK 0x0000FF00U
#define ANT_RF_STATUS_BBLOCK_OK 0x00000100U
#define ANT_RF_STATUS_PLLA_SHIFT 16 #define ANT_RF_STATUS_PLLA_SHIFT 16
#define ANT_RF_STATUS_PLLA_WIDTH 8 #define ANT_RF_STATUS_PLLA_WIDTH 8
#define ANT_RF_STATUS_PLLA_MASK 0x00FF0000U #define ANT_RF_STATUS_PLLA_MASK 0x00FF0000U
#define ANT_RF_STATUS_PLLA_OK 0x00010000U
#define ANT_RF_STATUS_PLLB_SHIFT 24 #define ANT_RF_STATUS_PLLB_SHIFT 24
#define ANT_RF_STATUS_PLLB_WIDTH 8 #define ANT_RF_STATUS_PLLB_WIDTH 8
#define ANT_RF_STATUS_PLLB_MASK 0xFF000000U #define ANT_RF_STATUS_PLLB_MASK 0xFF000000U
#define ANT_RF_STATUS_PLLB_OK 0x01000000U
/** /**
* Register: ANT_RF_MGC * Register: ANT_RF_MGC