add register status code
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@@ -281,15 +281,22 @@
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#define ANT_STATUS_CODE_SHIFT 0
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#define ANT_STATUS_CODE_SHIFT 0
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#define ANT_STATUS_CODE_WIDTH 8
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#define ANT_STATUS_CODE_WIDTH 8
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#define ANT_STATUS_CODE_MASK 0x000000FFU
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#define ANT_STATUS_CODE_MASK 0x000000FFU
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#define ANT_STATUS_CODE_OK 0x00000001U
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#define ANT_STATUS_NIL_VOLT_SHIFT 8
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#define ANT_STATUS_NIL_VOLT_SHIFT 8
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#define ANT_STATUS_NIL_VOLT_WIDTH 8
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#define ANT_STATUS_NIL_VOLT_WIDTH 8
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#define ANT_STATUS_NIL_VOLT_MASK 0x0000FF00U
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#define ANT_STATUS_NIL_VOLT_MASK 0x0000FF00U
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#define ANT_STATUS_NIL_VOLT_OK 0x00000100U
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#define ANT_STATUS_RF_VOLT_SHIFT 16
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#define ANT_STATUS_RF_VOLT_SHIFT 16
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#define ANT_STATUS_RF_VOLT_WIDTH 8
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#define ANT_STATUS_RF_VOLT_WIDTH 8
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#define ANT_STATUS_RF_VOLT_MASK 0x00FF0000U
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#define ANT_STATUS_RF_VOLT_MASK 0x00FF0000U
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#define ANT_STATUS_RF_VOLT_OK 0x00010000U
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#define ANT_STATUS_ANT_VOLT_SHIFT 24
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#define ANT_STATUS_ANT_VOLT_SHIFT 24
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#define ANT_STATUS_ANT_VOLT_WIDTH 8
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#define ANT_STATUS_ANT_VOLT_WIDTH 8
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#define ANT_STATUS_ANT_VOLT_MASK 0xFF000000U
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#define ANT_STATUS_ANT_VOLT_MASK 0xFF000000U
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#define ANT_STATUS_ANT_VOLT_OK 0x01000000U
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/**
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/**
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* Register: ANT_FRAME_CNT
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* Register: ANT_FRAME_CNT
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@@ -306,15 +313,21 @@
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#define ANT_RF_STATUS_TEMP_SHIFT 0
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#define ANT_RF_STATUS_TEMP_SHIFT 0
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#define ANT_RF_STATUS_TEMP_WIDTH 8
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#define ANT_RF_STATUS_TEMP_WIDTH 8
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#define ANT_RF_STATUS_TEMP_MASK 0x000000FFU
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#define ANT_RF_STATUS_TEMP_MASK 0x000000FFU
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#define ANT_RF_STATUS_BDLOCK_SHIFT 8
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#define ANT_RF_STATUS_BDLOCK_WIDTH 8
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#define ANT_RF_STATUS_BBLOCK_SHIFT 8
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#define ANT_RF_STATUS_BDLOCK_MASK 0x0000FF00U
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#define ANT_RF_STATUS_BBLOCK_WIDTH 8
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#define ANT_RF_STATUS_BBLOCK_MASK 0x0000FF00U
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#define ANT_RF_STATUS_BBLOCK_OK 0x00000100U
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#define ANT_RF_STATUS_PLLA_SHIFT 16
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#define ANT_RF_STATUS_PLLA_SHIFT 16
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#define ANT_RF_STATUS_PLLA_WIDTH 8
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#define ANT_RF_STATUS_PLLA_WIDTH 8
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#define ANT_RF_STATUS_PLLA_MASK 0x00FF0000U
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#define ANT_RF_STATUS_PLLA_MASK 0x00FF0000U
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#define ANT_RF_STATUS_PLLA_OK 0x00010000U
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#define ANT_RF_STATUS_PLLB_SHIFT 24
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#define ANT_RF_STATUS_PLLB_SHIFT 24
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#define ANT_RF_STATUS_PLLB_WIDTH 8
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#define ANT_RF_STATUS_PLLB_WIDTH 8
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#define ANT_RF_STATUS_PLLB_MASK 0xFF000000U
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#define ANT_RF_STATUS_PLLB_MASK 0xFF000000U
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#define ANT_RF_STATUS_PLLB_OK 0x01000000U
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/**
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/**
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* Register: ANT_RF_MGC
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* Register: ANT_RF_MGC
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