From 2700e7442ebe175010359cce6975305b1431e07d Mon Sep 17 00:00:00 2001 From: Gatsby Van Date: Wed, 31 Jan 2024 19:46:16 +0800 Subject: [PATCH] add new physical status registers --- .../src/networking/phy_layer/phy_reg.h | 203 +++++++++++++++--- 1 file changed, 168 insertions(+), 35 deletions(-) diff --git a/df_datalink_sp/src/networking/phy_layer/phy_reg.h b/df_datalink_sp/src/networking/phy_layer/phy_reg.h index 84e5e71..bca86ee 100644 --- a/df_datalink_sp/src/networking/phy_layer/phy_reg.h +++ b/df_datalink_sp/src/networking/phy_layer/phy_reg.h @@ -277,7 +277,7 @@ /** * Register: ANT_STATUS */ -#define ANT_STATUS 0x00000048U +#define ANT_STATUS 0x00000100U #define ANT_STATUS_CODE_SHIFT 0 #define ANT_STATUS_CODE_WIDTH 8 #define ANT_STATUS_CODE_MASK 0x000000FFU @@ -294,51 +294,184 @@ /** * Register: ANT_FRAME_CNT */ -#define ANT_FRAME_CNT 0x0000004CU +#define ANT_FRAME_CNT 0x00000104U #define ANT_FRAME_CNT_SHIFT 0 #define ANT_FRAME_CNT_WIDTH 32 #define ANT_FRAME_CNT_MASK 0xFFFFFFFFU /** - * Register: RF_STATUS + * Register: ANT_RF_STATUS */ -#define RF_STATUS 0x00000050U -#define RF_STATUS_TEMP_SHIFT 0 -#define RF_STATUS_TEMP_WIDTH 8 -#define RF_STATUS_TEMP_MASK 0x000000FFU -#define RF_STATUS_BDLOCK_SHIFT 8 -#define RF_STATUS_BDLOCK_WIDTH 8 -#define RF_STATUS_BDLOCK_MASK 0x0000FF00U -#define RF_STATUS_PLLA_SHIFT 16 -#define RF_STATUS_PLLA_WIDTH 8 -#define RF_STATUS_PLLA_MASK 0x00FF0000U -#define RF_STATUS_PLLB_SHIFT 24 -#define RF_STATUS_PLLB_WIDTH 8 -#define RF_STATUS_PLLB_MASK 0xFF000000U +#define ANT_RF_STATUS 0x00000108U +#define ANT_RF_STATUS_TEMP_SHIFT 0 +#define ANT_RF_STATUS_TEMP_WIDTH 8 +#define ANT_RF_STATUS_TEMP_MASK 0x000000FFU +#define ANT_RF_STATUS_BDLOCK_SHIFT 8 +#define ANT_RF_STATUS_BDLOCK_WIDTH 8 +#define ANT_RF_STATUS_BDLOCK_MASK 0x0000FF00U +#define ANT_RF_STATUS_PLLA_SHIFT 16 +#define ANT_RF_STATUS_PLLA_WIDTH 8 +#define ANT_RF_STATUS_PLLA_MASK 0x00FF0000U +#define ANT_RF_STATUS_PLLB_SHIFT 24 +#define ANT_RF_STATUS_PLLB_WIDTH 8 +#define ANT_RF_STATUS_PLLB_MASK 0xFF000000U /** - * Register: RF_MGC + * Register: ANT_RF_MGC */ -#define RF_MGC 0x00000054U -#define RF_MGC_CH1_SHIFT 0 -#define RF_MGC_CH1_WIDTH 4 -#define RF_MGC_CH1_MASK 0x0000000FU -#define RF_MGC_CH2_SHIFT 8 -#define RF_MGC_CH2_WIDTH 4 -#define RF_MGC_CH2_MASK 0x00000F00U -#define RF_MGC_CH3_SHIFT 16 -#define RF_MGC_CH3_WIDTH 4 -#define RF_MGC_CH3_MASK 0x000F0000U -#define RF_MGC_CH4_SHIFT 24 -#define RF_MGC_CH4_WIDTH 4 -#define RF_MGC_CH4_MASK 0x0F000000U +#define ANT_RF_MGC 0x0000010CU +#define ANT_RF_MGC_CH1_SHIFT 0 +#define ANT_RF_MGC_CH1_WIDTH 4 +#define ANT_RF_MGC_CH1_MASK 0x0000000FU +#define ANT_RF_MGC_CH2_SHIFT 8 +#define ANT_RF_MGC_CH2_WIDTH 4 +#define ANT_RF_MGC_CH2_MASK 0x00000F00U +#define ANT_RF_MGC_CH3_SHIFT 16 +#define ANT_RF_MGC_CH3_WIDTH 4 +#define ANT_RF_MGC_CH3_MASK 0x000F0000U +#define ANT_RF_MGC_CH4_SHIFT 24 +#define ANT_RF_MGC_CH4_WIDTH 4 +#define ANT_RF_MGC_CH4_MASK 0x0F000000U /** - * Register: RF_FRAME_CNT + * Register: ANT_RF_FRAME_CNT */ -#define RF_FRAME_CNT 0x00000058U -#define RF_FRAME_CNT_SHIFT 0 -#define RF_FRAME_CNT_WIDTH 32 -#define RF_FRAME_CNT_MASK 0xFFFFFFFFU +#define ANT_RF_FRAME_CNT 0x00000110U +#define ANT_RF_FRAME_CNT_SHIFT 0 +#define ANT_RF_FRAME_CNT_WIDTH 32 +#define ANT_RF_FRAME_CNT_MASK 0xFFFFFFFFU + +/** + * Register: PHY_ACQ_CNT + */ +#define PHY_ACQ_CNT 0x00000114U +#define PHY_ACQ_CNT_SHIFT 0 +#define PHY_ACQ_CNT_WIDTH 32 +#define PHY_ACQ_CNT_MASK 0xFFFFFFFFU + +/** + * Register: PHY_FRAME_SYNC_CNT + */ +#define PHY_FRAME_SYNC_CNT 0x00000118U +#define PHY_FRAME_SYNC_CNT_SHIFT 0 +#define PHY_FRAME_SYNC_CNT_WIDTH 32 +#define PHY_FRAME_SYNC_CNT_MASK 0xFFFFFFFFU + +/** + * Register: PHY_DECODE_CNT + */ +#define PHY_DECODE_CNT 0x0000011CU +#define PHY_DECODE_CNT_SHIFT 0 +#define PHY_DECODE_CNT_WIDTH 32 +#define PHY_DECODE_CNT_MASK 0xFFFFFFFFU + +/** + * Register: PHY_CRC_OK_CNT + */ +#define PHY_CRC_OK_CNT 0x00000120U +#define PHY_CRC_OK_CNT_SHIFT 0 +#define PHY_CRC_OK_CNT_WIDTH 32 +#define PHY_CRC_OK_CNT_MASK 0xFFFFFFFFU + +/** + * Register: PHY_ACQ_PEAK_H + */ +#define PHY_ACQ_PEAK_H 0x00000124U +#define PHY_ACQ_PEAK_H_SHIFT 0 +#define PHY_ACQ_PEAK_H_WIDTH 32 +#define PHY_ACQ_PEAK_H_MASK 0xFFFFFFFFU + +/** + * Register: PHY_ACQ_PEAK_L + */ +#define PHY_ACQ_PEAK_L 0x00000128U +#define PHY_ACQ_PEAK_L_SHIFT 0 +#define PHY_ACQ_PEAK_L_WIDTH 32 +#define PHY_ACQ_PEAK_L_MASK 0xFFFFFFFFU + + +/** + * Register: PHY_ACQ_MEAN_H + */ +#define PHY_ACQ_MEAN_H 0x0000012CU +#define PHY_ACQ_MEAN_H_SHIFT 0 +#define PHY_ACQ_MEAN_H_WIDTH 32 +#define PHY_ACQ_MEAN_H_MASK 0xFFFFFFFFU + +/** + * Register: PHY_ACQ_MEAN_L + */ +#define PHY_ACQ_MEAN_L 0x00000130U +#define PHY_ACQ_MEAN_L_SHIFT 0 +#define PHY_ACQ_MEAN_L_WIDTH 32 +#define PHY_ACQ_MEAN_L_MASK 0xFFFFFFFFU + +/** + * Register: PHY_ACQ_FREQEST + */ +#define PHY_ACQ_FREQEST 0x00000134U +#define PHY_ACQ_FREQEST_SHIFT 0 +#define PHY_ACQ_FREQEST_WIDTH 32 +#define PHY_ACQ_FREQEST_MASK 0xFFFFFFFFU + +#define PHY_ACQ_FREQEST_PHASE_SHIFT 0 +#define PHY_ACQ_FREQEST_PHASE_WIDTH 8 +#define PHY_ACQ_FREQEST_PHASE_MASK 0x000000FFU +#define PHY_ACQ_FREQEST_CHANNEL_SHIFT 8 +#define PHY_ACQ_FREQEST_CHANNEL_WIDTH 8 +#define PHY_ACQ_FREQEST_CHANNEL_MASK 0x0000FF00U + +/** + * Register: PHY_FRAME_SYNC_PEAK_H + */ +#define PHY_FRAME_SYNC_PEAK_H 0x00000138U +#define PHY_FRAME_SYNC_PEAK_H_SHIFT 0 +#define PHY_FRAME_SYNC_PEAK_H_WIDTH 32 +#define PHY_FRAME_SYNC_PEAK_H_MASK 0xFFFFFFFFU + +/** + * Register: PHY_FRAME_SYNC_PEAK_L + */ +#define PHY_FRAME_SYNC_PEAK_L 0x0000013CU +#define PHY_FRAME_SYNC_PEAK_L_SHIFT 0 +#define PHY_FRAME_SYNC_PEAK_L_WIDTH 32 +#define PHY_FRAME_SYNC_PEAK_L_MASK 0xFFFFFFFFU + + +/** + * Register: PHY_FRAME_SYNC_MEAN_H + */ +#define PHY_FRAME_SYNC_MEAN_H 0x00000140U +#define PHY_FRAME_SYNC_MEAN_H_SHIFT 0 +#define PHY_FRAME_SYNC_MEAN_H_WIDTH 32 +#define PHY_FRAME_SYNC_MEAN_H_MASK 0xFFFFFFFFU + +/** + * Register: PHY_FRAME_SYNC_MEAN_L + */ +#define PHY_FRAME_SYNC_MEAN_L 0x00000144U +#define PHY_FRAME_SYNC_MEAN_L_SHIFT 0 +#define PHY_FRAME_SYNC_MEAN_L_WIDTH 32 +#define PHY_FRAME_SYNC_MEAN_L_MASK 0xFFFFFFFFU + +/** + * Register: PHY_FRAME_SYNC_FREQEST + */ +#define PHY_FRAME_SYNC_FREQEST 0x00000148U +#define PHY_FRAME_SYNC_FREQEST_SHIFT 0 +#define PHY_FRAME_SYNC_FREQEST_WIDTH 32 +#define PHY_FRAME_SYNC_FREQEST_MASK 0xFFFFFFFFU + +#define PHY_FRAME_SYNC_FREQEST_CHANNEL_SHIFT 0 +#define PHY_FRAME_SYNC_FREQEST_CHANNEL_WIDTH 8 +#define PHY_FRAME_SYNC_FREQEST_CHANNEL_MASK 0x000000FFU + +/** + * Register: PHY_DEINTLV_AMPEST + */ +#define PHY_DEINTLV_AMPEST 0x00000148U +#define PHY_DEINTLV_AMPEST_SHIFT 0 +#define PHY_DEINTLV_AMPEST_WIDTH 16 +#define PHY_DEINTLV_AMPEST_MASK 0x0000FFFFU #endif /* PHY_REG_H_ */