From 884d9bcca945bbe7b363cc447bcab78842c7b06b Mon Sep 17 00:00:00 2001
From: bit-cyber-fh <3120225656@bit.edu.cn>
Date: Wed, 12 Jun 2024 10:28:38 +0800
Subject: [PATCH] update hardware validation constrain

---
 df_datalink_sp/src/hwconfig.c       | 11 ++++++++---
 df_datalink_sp/src/system_monitor.h | 12 ++++++------
 2 files changed, 14 insertions(+), 9 deletions(-)

diff --git a/df_datalink_sp/src/hwconfig.c b/df_datalink_sp/src/hwconfig.c
index 9de7043..b281039 100644
--- a/df_datalink_sp/src/hwconfig.c
+++ b/df_datalink_sp/src/hwconfig.c
@@ -401,12 +401,15 @@ int32_t Hardware_SwitchFreq(struct ad9361_reg_dev *dev, ad9361TxFreq freq)
 int8_t Hardware_GetAD9361Temp_1(void)
 {
 	int8_t scaleTemp;
+	double temp;
 
+	ad9361_reg_write(ad9361_1_reg_inst, 0x000B, -64);
 	ad9361_reg_write(ad9361_1_reg_inst, 0x001D, 0x01); // disable aux adc
 	ad9361_reg_read(ad9361_1_reg_inst, 0x000E, (uint8_t*)&scaleTemp);
 	ad9361_reg_write(ad9361_1_reg_inst, 0x001D, 0x00); // enable aux adc
 
-	return (int8_t) scaleTemp/1.16;
+	temp = ((double)scaleTemp + 64)/1.16;
+	return ((temp > INT8_MAX) ? INT8_MAX : (int8_t)temp);
 }
 
 // @ Get AD9361 - 2 temperature (Celsius Degree)
@@ -416,12 +419,14 @@ int8_t Hardware_GetAD9361Temp_1(void)
 int8_t Hardware_GetAD9361Temp_2(void)
 {
 	int8_t scaleTemp;
+	double temp;
 
+	ad9361_reg_write(ad9361_2_reg_inst, 0x000B, -64);
 	ad9361_reg_write(ad9361_2_reg_inst, 0x001D, 0x01); // disable aux adc
 	ad9361_reg_read(ad9361_2_reg_inst, 0x000E, (uint8_t*)&scaleTemp);
 	ad9361_reg_write(ad9361_2_reg_inst, 0x001D, 0x00); // enable aux adc
-
-	return (int8_t) scaleTemp/1.16;
+	temp = ((double)scaleTemp + 64)/1.16;
+	return ((temp > INT8_MAX) ? INT8_MAX : (int8_t)temp);
 }
 
 // @ Determine AD9361 lock state
diff --git a/df_datalink_sp/src/system_monitor.h b/df_datalink_sp/src/system_monitor.h
index 849dabc..f96abbc 100644
--- a/df_datalink_sp/src/system_monitor.h
+++ b/df_datalink_sp/src/system_monitor.h
@@ -54,12 +54,12 @@
 // #define IS_PL_VALID(x) (x <= 1.03 && x >= 0.97)
 // #define IS_PLAUX_VALID(x) (x <= 1.89 && x >= 1.71)
 // #define IS_BRAM_VALID(x) (x <= 1.03 && x >= 0.97)
-#define IS_PS_VALID(x) (x <= 1.05 && x >= 0.95)
-#define IS_PSAUX_VALID(x) (x <= 1.89 && x >= 1.71)
-#define IS_DDR_VALID(x) (x <= 1.89 && x >= 1.14)
-#define IS_PL_VALID(x) (x <= 1.03 && x >= 0.96)
-#define IS_PLAUX_VALID(x) (x <= 1.89 && x >= 1.71)
-#define IS_BRAM_VALID(x) (x <= 1.03 && x >= 0.96)
+#define IS_PS_VALID(x) (x <= 1.1 && x >= 0.9)
+#define IS_PSAUX_VALID(x) (x <= 2.0 && x >= 1.6)
+#define IS_DDR_VALID(x) (x <= 1.7 && x >= 1.3)
+#define IS_PL_VALID(x) (x <= 1.1 && x >= 0.9)
+#define IS_PLAUX_VALID(x) (x <= 2.0 && x >= 1.6)
+#define IS_BRAM_VALID(x) (x <= 1.1 && x >= 0.9)
 
 #define CLK_SP_PLL0_LOCK BIT(0)
 #define CLK_SP_PLL1_LOCK BIT(2)