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BSP update: trim unnecessary memory

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This commit is contained in:
Gatsby Van
2024-03-25 13:14:52 +08:00
parent e7b45ae1f5
commit 9b416114a1
5 changed files with 41 additions and 41 deletions
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df_datalink_sp/bsp/ps7_cortexa9_0/include/xparameters.h
+21 -21
View File
@@ -57,27 +57,27 @@
#define XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_ECC_ONOFF_RESET_VALUE 0U
#define XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_WRITE_ACCESS 0U
#define XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_S_AXI_BASEADDR 0x42000000U
#define XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_S_AXI_HIGHADDR 0x42001FFFU
#define XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_S_AXI_HIGHADDR 0x42000FFFU
#define XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_S_AXI_CTRL_BASEADDR 0xFFFFFFFFU
#define XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_S_AXI_CTRL_HIGHADDR 0xFFFFFFFFU
/* Definitions for peripheral PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL */
#define XPAR_PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL_DEVICE_ID 1U
#define XPAR_PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL_DATA_WIDTH 32U
#define XPAR_PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL_ECC 0U
#define XPAR_PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL_FAULT_INJECT 0U
#define XPAR_PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL_CE_FAILING_REGISTERS 0U
#define XPAR_PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL_UE_FAILING_REGISTERS 0U
#define XPAR_PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL_ECC_STATUS_REGISTERS 0U
#define XPAR_PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL_CE_COUNTER_WIDTH 0U
#define XPAR_PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL_ECC_ONOFF_REGISTER 0U
#define XPAR_PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL_ECC_ONOFF_RESET_VALUE 0U
#define XPAR_PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL_WRITE_ACCESS 0U
#define XPAR_PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL_S_AXI_BASEADDR 0x40004000U
#define XPAR_PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL_S_AXI_HIGHADDR 0x40004FFFU
#define XPAR_PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL_S_AXI_CTRL_BASEADDR 0xFFFFFFFFU
#define XPAR_PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL_S_AXI_CTRL_HIGHADDR 0xFFFFFFFFU
/* Definitions for peripheral PHY_DATA_INTERFACE_ANT_CONFIG_BRAM_CTRL */
#define XPAR_PHY_DATA_INTERFACE_ANT_CONFIG_BRAM_CTRL_DEVICE_ID 1U
#define XPAR_PHY_DATA_INTERFACE_ANT_CONFIG_BRAM_CTRL_DATA_WIDTH 32U
#define XPAR_PHY_DATA_INTERFACE_ANT_CONFIG_BRAM_CTRL_ECC 0U
#define XPAR_PHY_DATA_INTERFACE_ANT_CONFIG_BRAM_CTRL_FAULT_INJECT 0U
#define XPAR_PHY_DATA_INTERFACE_ANT_CONFIG_BRAM_CTRL_CE_FAILING_REGISTERS 0U
#define XPAR_PHY_DATA_INTERFACE_ANT_CONFIG_BRAM_CTRL_UE_FAILING_REGISTERS 0U
#define XPAR_PHY_DATA_INTERFACE_ANT_CONFIG_BRAM_CTRL_ECC_STATUS_REGISTERS 0U
#define XPAR_PHY_DATA_INTERFACE_ANT_CONFIG_BRAM_CTRL_CE_COUNTER_WIDTH 0U
#define XPAR_PHY_DATA_INTERFACE_ANT_CONFIG_BRAM_CTRL_ECC_ONOFF_REGISTER 0U
#define XPAR_PHY_DATA_INTERFACE_ANT_CONFIG_BRAM_CTRL_ECC_ONOFF_RESET_VALUE 0U
#define XPAR_PHY_DATA_INTERFACE_ANT_CONFIG_BRAM_CTRL_WRITE_ACCESS 0U
#define XPAR_PHY_DATA_INTERFACE_ANT_CONFIG_BRAM_CTRL_S_AXI_BASEADDR 0x40004000U
#define XPAR_PHY_DATA_INTERFACE_ANT_CONFIG_BRAM_CTRL_S_AXI_HIGHADDR 0x40005FFFU
#define XPAR_PHY_DATA_INTERFACE_ANT_CONFIG_BRAM_CTRL_S_AXI_CTRL_BASEADDR 0xFFFFFFFFU
#define XPAR_PHY_DATA_INTERFACE_ANT_CONFIG_BRAM_CTRL_S_AXI_CTRL_HIGHADDR 0xFFFFFFFFU
/* Definitions for peripheral PHY_DATA_INTERFACE_RX_FRAME_BRAM_CTRL */
@@ -131,12 +131,12 @@
#define XPAR_BRAM_0_ECC_ONOFF_RESET_VALUE 0U
#define XPAR_BRAM_0_WRITE_ACCESS 0U
#define XPAR_BRAM_0_BASEADDR 0x42000000U
#define XPAR_BRAM_0_HIGHADDR 0x42001FFFU
#define XPAR_BRAM_0_HIGHADDR 0x42000FFFU
#define XPAR_BRAM_0_CTRL_BASEADDR 0xFFFFFFFFU
#define XPAR_BRAM_0_CTRL_HIGHADDR 0xFFFFFFFEU
/* Canonical definitions for peripheral PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL */
#define XPAR_BRAM_1_DEVICE_ID XPAR_PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL_DEVICE_ID
/* Canonical definitions for peripheral PHY_DATA_INTERFACE_ANT_CONFIG_BRAM_CTRL */
#define XPAR_BRAM_1_DEVICE_ID XPAR_PHY_DATA_INTERFACE_ANT_CONFIG_BRAM_CTRL_DEVICE_ID
#define XPAR_BRAM_1_DATA_WIDTH 32U
#define XPAR_BRAM_1_ECC 0U
#define XPAR_BRAM_1_FAULT_INJECT 0U
@@ -148,7 +148,7 @@
#define XPAR_BRAM_1_ECC_ONOFF_RESET_VALUE 0U
#define XPAR_BRAM_1_WRITE_ACCESS 0U
#define XPAR_BRAM_1_BASEADDR 0x40004000U
#define XPAR_BRAM_1_HIGHADDR 0x40004FFFU
#define XPAR_BRAM_1_HIGHADDR 0x40005FFFU
#define XPAR_BRAM_1_CTRL_BASEADDR 0xFFFFFFFFU
#define XPAR_BRAM_1_CTRL_HIGHADDR 0xFFFFFFFEU
df_datalink_sp/bsp/ps7_cortexa9_0/libsrc/bram_v4_3/src/xbram_g.c
+15 -15
View File
@@ -62,23 +62,23 @@ XBram_Config XBram_ConfigTable[] =
XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_S_AXI_CTRL_HIGHADDR
},
{
XPAR_PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL_DEVICE_ID,
XPAR_PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL_DATA_WIDTH,
XPAR_PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL_ECC,
XPAR_PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL_FAULT_INJECT,
XPAR_PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL_CE_FAILING_REGISTERS,
XPAR_PHY_DATA_INTERFACE_ANT_CONFIG_BRAM_CTRL_DEVICE_ID,
XPAR_PHY_DATA_INTERFACE_ANT_CONFIG_BRAM_CTRL_DATA_WIDTH,
XPAR_PHY_DATA_INTERFACE_ANT_CONFIG_BRAM_CTRL_ECC,
XPAR_PHY_DATA_INTERFACE_ANT_CONFIG_BRAM_CTRL_FAULT_INJECT,
XPAR_PHY_DATA_INTERFACE_ANT_CONFIG_BRAM_CTRL_CE_FAILING_REGISTERS,
0,
XPAR_PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL_UE_FAILING_REGISTERS,
XPAR_PHY_DATA_INTERFACE_ANT_CONFIG_BRAM_CTRL_UE_FAILING_REGISTERS,
0,
XPAR_PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL_ECC_STATUS_REGISTERS,
XPAR_PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL_CE_COUNTER_WIDTH,
XPAR_PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL_ECC_ONOFF_REGISTER,
XPAR_PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL_ECC_ONOFF_RESET_VALUE,
XPAR_PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL_WRITE_ACCESS,
XPAR_PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL_S_AXI_BASEADDR,
XPAR_PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL_S_AXI_HIGHADDR,
XPAR_PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL_S_AXI_CTRL_BASEADDR,
XPAR_PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL_S_AXI_CTRL_HIGHADDR
XPAR_PHY_DATA_INTERFACE_ANT_CONFIG_BRAM_CTRL_ECC_STATUS_REGISTERS,
XPAR_PHY_DATA_INTERFACE_ANT_CONFIG_BRAM_CTRL_CE_COUNTER_WIDTH,
XPAR_PHY_DATA_INTERFACE_ANT_CONFIG_BRAM_CTRL_ECC_ONOFF_REGISTER,
XPAR_PHY_DATA_INTERFACE_ANT_CONFIG_BRAM_CTRL_ECC_ONOFF_RESET_VALUE,
XPAR_PHY_DATA_INTERFACE_ANT_CONFIG_BRAM_CTRL_WRITE_ACCESS,
XPAR_PHY_DATA_INTERFACE_ANT_CONFIG_BRAM_CTRL_S_AXI_BASEADDR,
XPAR_PHY_DATA_INTERFACE_ANT_CONFIG_BRAM_CTRL_S_AXI_HIGHADDR,
XPAR_PHY_DATA_INTERFACE_ANT_CONFIG_BRAM_CTRL_S_AXI_CTRL_BASEADDR,
XPAR_PHY_DATA_INTERFACE_ANT_CONFIG_BRAM_CTRL_S_AXI_CTRL_HIGHADDR
},
{
XPAR_PHY_DATA_INTERFACE_RX_FRAME_BRAM_CTRL_DEVICE_ID,
df_datalink_sp/bsp/system.mss
+1 -1
View File
@@ -33,7 +33,7 @@ END
BEGIN DRIVER
PARAMETER DRIVER_NAME = bram
PARAMETER DRIVER_VER = 4.3
PARAMETER HW_INSTANCE = phy_data_interface_ant_info_bram_ctrl
PARAMETER HW_INSTANCE = phy_data_interface_ant_config_bram_ctrl
END
BEGIN DRIVER
df_datalink_sp/src/config/app_config.h
+1 -1
View File
@@ -56,7 +56,7 @@
#define PHY_BASEADDR XPAR_PHYC_BASEADDR
#define PHY_BEAM_FORMING_ENABLE
// -- Antenna Bram Configs
#define PHY_ANTCONFIG_BRAM_DEVICE_ID XPAR_PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL_DEVICE_ID
#define PHY_ANTCONFIG_BRAM_DEVICE_ID XPAR_PHY_DATA_INTERFACE_ANT_CONFIG_BRAM_CTRL_DEVICE_ID
#define PHY_ANTINFO_BRAM_DEVICE_ID XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_DEVICE_ID
// -- Buffers
#define PHY_TXBUFF_BRAM_DEVICE_ID XPAR_PHY_DATA_INTERFACE_TX_FRAME_BRAM_CTRL_DEVICE_ID
df_datalink_sp/src/lscript.ld
+3 -3
View File
@@ -23,9 +23,9 @@ _UNDEF_STACK_SIZE = DEFINED(_UNDEF_STACK_SIZE) ? _UNDEF_STACK_SIZE : 1024;
MEMORY
{
phy_data_interface_rx_frame_bram_ctrl_Mem0 : ORIGIN = 0x40000000, LENGTH = 0x2000
phy_data_interface_tx_frame_bram_ctrl_Mem0 : ORIGIN = 0x40002000, LENGTH = 0x2000
phy_data_interface_ant_info_bram_ctrl_Mem0 : ORIGIN = 0x40004000, LENGTH = 0x2000
phy_data_interface_rx_frame_bram_ctrl_Mem0 : ORIGIN = 0x40000000, LENGTH = 0x1000
phy_data_interface_tx_frame_bram_ctrl_Mem0 : ORIGIN = 0x40002000, LENGTH = 0x1000
phy_data_interface_ant_config_bram_ctrl_Mem0 : ORIGIN = 0x40004000, LENGTH = 0x2000
phy_data_interface_ant_beam_bram_ctrl_Mem0 : ORIGIN = 0x42000000, LENGTH = 0x1000
ps7_ddr_0 : ORIGIN = 0x100000, LENGTH = 0x1FF00000
ps7_qspi_linear_0 : ORIGIN = 0xFC000000, LENGTH = 0x1000000