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adapted to new log content definition

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This commit is contained in:
Gatsby Van
2024-02-20 13:13:57 +08:00
parent 0701eb6f43
commit c27d6fc455
3 changed files with 148 additions and 101 deletions
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df_datalink_sp/src/systembus/systembus.c
+51 -34
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@@ -53,31 +53,30 @@
#define ST_RET_ERROR 0x55
#define ST_RET_INFO_LEN 13
// -- -- Signal processor PS voltage
#define WD_SP_PS_VOLT 0x03
#define WD_SP_FPGA_VOLT 0x03
// -- -- Signal processor PS AUX voltage
#define WD_SP_PSAUX_VOLT 0x04
#define WD_SP_CLK_STATE 0x04
// -- -- Signal processor DDR voltage
#define WD_SP_DDR_VOLT 0x05
#define WD_SP_AD_LOCK_STATE 0x05
// -- -- Signal processor PL voltage
#define WD_SP_PL_VOLT 0x06
#define WD_SP_AD_TEMP_0 0x06
// -- -- Signal processor PL AUX voltage
#define WD_SP_PLAUX_VOLT 0x07
#define WD_SP_AD_TEMP_1 0x07
// -- -- Signal processor Bram voltage
#define WD_SP_BRAM_VOLT 0x08
// -- -- Signal processor temperature
#define WD_SP_TEMP 0x09
#define WD_SP_FPGA_TEMP 0x08
// -- -- Signal processor antenna voltage status
#define WD_ANT_VOLT 0x0A
#define WD_ANT_VOLT 0x09
// -- -- Signal processor antenna RF temperature
#define WD_ANT_RF_TEMP 0x0B
#define WD_ANT_RF_TEMP 0x0A
// -- -- Signal processor antenna PLL lock status
#define WD_ANT_RF_PLL 0x0C
#define WD_ANT_RF_PLL 0x0B
// -- -- Signal processor antenna MGC
#define WD_ANT_MGC_0 0x0D
#define WD_ANT_MGC_1 0x0E
// -- -- Dummy must be 0x00
#define WD_ST_DUMMY 0x0F
#define WD_ANT_MGC_0 0x0C
#define WD_ANT_MGC_1 0x0D
// -- -- Reserved
#define WD_ANT_RESERVE 0x0E
// Data Send Test Command
#define CMD_DATA_TEST_A 0xE2
@@ -160,10 +159,12 @@
// -- Response
#define WD_FLJ_TIME_STAMP 0x02
#define WD_FLJ_TIME_STAMP_LEN 8
#define WD_FLJ_LINK_LOG 0x0A
#define WD_FLJ_SYSBUS_LOG 0x0A
#define WD_FLJ_SYSBUS_LOG_LEN 14
#define WD_FLJ_LINK_LOG 0x18
#define WD_FLJ_LINK_LOG_LEN 64
#define WD_FLJ_PHY_LOG 0x4A
#define WD_FLJ_PHY_LOG_LEN 71
#define WD_FLJ_PHY_LOG 0x58
#define WD_FLJ_PHY_LOG_LEN 57
#define WD_FLJ_HARDWARE_ST 0x91
#define WD_FLJ_HARDWARE_ST_LEN 13
@@ -177,10 +178,12 @@
// -- Response
#define WD_LJ_TIME_STAMP 0x02
#define WD_LJ_TIME_STAMP_LEN 8
#define WD_LJ_LINK_LOG 0x0A
#define WD_LJ_SYSBUS_LOG 0x0A
#define WD_LJ_SYSBUS_LOG_LEN 14
#define WD_LJ_LINK_LOG 0x18
#define WD_LJ_LINK_LOG_LEN 64
#define WD_LJ_PHY_LOG 0x4A
#define WD_LJ_PHY_LOG_LEN 71
#define WD_LJ_PHY_LOG 0x58
#define WD_LJ_PHY_LOG_LEN 57
#define WD_LJ_HARDWARE_ST 0x91
#define WD_LJ_HARDWARE_ST_LEN 13
@@ -247,7 +250,10 @@ int32_t SystemBus_Init(SYSBUS **instPtr, SYSBUS_CONFIG *config)
(*instPtr)->txQueue = NULL;
(*instPtr)->uartInst = NULL;
memcpy(&((*instPtr)->config), config, sizeof(SYSBUS_CONFIG));
memset(&((*instPtr)->sysLog), 0x00, sizeof(SYSLOG));
memset(&((*instPtr)->sysbusLog), 0x00, sizeof(SYSBUSLOG));
memset(&((*instPtr)->linkLog), 0x00, sizeof(LINKLOG));
memset(&((*instPtr)->phyLog), 0x00, sizeof(PHYLOG));
memset(&((*instPtr)->hwState), 0x00, sizeof(HWSTATE));
uartConfig.baseAddr = config->baseAddr;
Status = SysbusUart_Init(&((*instPtr)->uartInst), &uartConfig);
if (Status != SUCCESS)
@@ -304,11 +310,12 @@ int32_t SystemBus_HandleCmd(SYSBUS *instPtr)
DBG_WARNING("SystemBus::Production code mismatch!\n");
return EIGNORE;
}
switch (data[WD_CMD])
{
case CMD_SELF_TEST:
{
HWSTATE *hwStatsPtr = &(instPtr->sysLog.hwState);
HWSTATE *hwStatsPtr = &(instPtr->hwState);
sysbusRsp = malloc(sizeof(SYSBUS_UART_FRAME));
if (sysbusRsp == NULL) {
DBG_ERROR("Failed to allocate memory for SELF TEST Response!\n");
@@ -329,7 +336,7 @@ int32_t SystemBus_HandleCmd(SYSBUS *instPtr)
sysbusRsp->data[WD_ST_RET] = (hwStatsPtr->isSpOk && hwStatsPtr->isAntOk) ? ST_RET_OK : ST_RET_ERROR;
}
// apply status and omit 2 bytes of overhead.
memcpy(sysbusRsp->data + WD_SP_PS_VOLT, &(hwStatsPtr->spPsVolt), ST_RET_INFO_LEN);
memcpy(sysbusRsp->data + WD_SP_FPGA_VOLT, &(hwStatsPtr->spFpgaVolt), ST_RET_INFO_LEN);
if (CircQueuePush(instPtr->txQueue, (void *)sysbusRsp) == false)
{
@@ -449,6 +456,8 @@ int32_t SystemBus_HandleCmd(SYSBUS *instPtr)
}
Linklayer_Start(linkInstPtr);
instPtr->sysbusLog.lastConfig[0] = data[WD_MODE_CMD];
instPtr->sysbusLog.lastConfig[1] = data[WD_EN_CMD];
Status = SUCCESS;
break;
}
@@ -462,11 +471,13 @@ int32_t SystemBus_HandleCmd(SYSBUS *instPtr)
case CMD_FLJ_SEND:
{
SysMonitor_UpdateSendPayload(data + FLJ_DATA_OFFSET, PAYLOAD_LEN_FLJ_TX); // omit control info
instPtr->sysbusLog.svcCnt++;
break;
}
case CMD_LJ_SEND:
{
SysMonitor_UpdateSendPayload(data + LJ_DATA_OFFSET, PAYLOAD_LEN_LJ_TX); // omit control info
instPtr->sysbusLog.svcCnt++;
break;
}
case CMD_FLJ_POLL:
@@ -502,6 +513,7 @@ int32_t SystemBus_HandleCmd(SYSBUS *instPtr)
Status = EQUEUE;
break;
}
instPtr->sysbusLog.pollCnt++;
Status = SUCCESS;
break;
}
@@ -538,12 +550,12 @@ int32_t SystemBus_HandleCmd(SYSBUS *instPtr)
Status = EQUEUE;
break;
}
instPtr->sysbusLog.pollCnt++;
Status = SUCCESS;
break;
}
case CMD_FLJ_RM_TEST:
{
SYSLOG *sysLogPtr = &(instPtr->sysLog);
if (data[WD_FLJ_RM_TEST] != FLJ_RM_TEST_CODE)
{
DBG_WARNING("SystemBus::Invalid remote test code!\n");
@@ -567,10 +579,12 @@ int32_t SystemBus_HandleCmd(SYSBUS *instPtr)
TimeCtrl_GetCurrentTime(linkInstPtr->config.tmcInstPtr, &tmWord);
time = tmWord.int_part * TIME_FRAC_MAX + tmWord.frac_part;
memcpy(sysbusRsp->data + WD_FLJ_TIME_STAMP, &time, WD_FLJ_TIME_STAMP_LEN);
SysMonitor_GetSyslog(sysLogPtr);
memcpy(sysbusRsp->data + WD_FLJ_LINK_LOG, &(sysLogPtr->linkLog), WD_FLJ_LINK_LOG_LEN);
memcpy(sysbusRsp->data + WD_FLJ_PHY_LOG, &(sysLogPtr->phyLog), WD_FLJ_PHY_LOG_LEN);
memcpy(sysbusRsp->data + WD_FLJ_HARDWARE_ST, &(sysLogPtr->hwState.spPsVolt), WD_FLJ_HARDWARE_ST_LEN);
SysMonitor_GetLinklayerLog(&(instPtr->linkLog));
SysMonitor_GetPhysicalLayerLog(&(instPtr->phyLog));
SysMonitor_GetHardwareStatus(&(instPtr->hwState));
memcpy(sysbusRsp->data + WD_FLJ_LINK_LOG, &(instPtr->linkLog), WD_FLJ_LINK_LOG_LEN);
memcpy(sysbusRsp->data + WD_FLJ_PHY_LOG, &(instPtr->phyLog), WD_FLJ_PHY_LOG_LEN);
memcpy(sysbusRsp->data + WD_FLJ_HARDWARE_ST, &(instPtr->hwState.spFpgaVolt), WD_FLJ_HARDWARE_ST_LEN);
if (CircQueuePush(instPtr->txQueue, (void *)sysbusRsp) == false){
free(sysbusRsp);
@@ -578,12 +592,12 @@ int32_t SystemBus_HandleCmd(SYSBUS *instPtr)
Status = EQUEUE;
break;
}
instPtr->sysbusLog.remoteCnt++;
Status = SUCCESS;
break;
}
case CMD_LJ_RM_TEST:
{
SYSLOG *sysLogPtr = &(instPtr->sysLog);
if (data[WD_LJ_RM_TEST] != LJ_RM_TEST_CODE)
{
DBG_WARNING("SystemBus::Invalid remote test code!\n");
@@ -607,10 +621,12 @@ int32_t SystemBus_HandleCmd(SYSBUS *instPtr)
TimeCtrl_GetCurrentTime(linkInstPtr->config.tmcInstPtr, &tmWord);
time = tmWord.int_part * TIME_FRAC_MAX + tmWord.frac_part;
memcpy(sysbusRsp->data + WD_LJ_TIME_STAMP, &time, WD_LJ_TIME_STAMP_LEN);
SysMonitor_GetSyslog(sysLogPtr);
memcpy(sysbusRsp->data + WD_LJ_LINK_LOG, &(sysLogPtr->linkLog), WD_LJ_LINK_LOG_LEN);
memcpy(sysbusRsp->data + WD_LJ_PHY_LOG, &(sysLogPtr->phyLog), WD_LJ_PHY_LOG_LEN);
memcpy(sysbusRsp->data + WD_LJ_HARDWARE_ST, &(sysLogPtr->hwState.spPsVolt), WD_LJ_HARDWARE_ST_LEN);
SysMonitor_GetLinklayerLog(&(instPtr->linkLog));
SysMonitor_GetPhysicalLayerLog(&(instPtr->phyLog));
SysMonitor_GetHardwareStatus(&(instPtr->hwState));
memcpy(sysbusRsp->data + WD_LJ_LINK_LOG, &(instPtr->linkLog), WD_LJ_LINK_LOG_LEN);
memcpy(sysbusRsp->data + WD_LJ_PHY_LOG, &(instPtr->phyLog), WD_LJ_PHY_LOG_LEN);
memcpy(sysbusRsp->data + WD_LJ_HARDWARE_ST, &(instPtr->hwState.spFpgaVolt), WD_LJ_HARDWARE_ST_LEN);
if (CircQueuePush(instPtr->txQueue, (void *)sysbusRsp) == false){
free(sysbusRsp);
@@ -618,6 +634,7 @@ int32_t SystemBus_HandleCmd(SYSBUS *instPtr)
Status = EQUEUE;
break;
}
instPtr->sysbusLog.remoteCnt++;
Status = SUCCESS;
break;
}