From da1659a582fccecc1908d38d7977de85a77eba5d Mon Sep 17 00:00:00 2001 From: Gatsby Van Date: Tue, 2 Apr 2024 00:17:39 +0800 Subject: [PATCH] misc update --- df_datalink_sp/src/config/app_config.h | 193 +++++++++--------- .../src/networking/phy_layer/phy_antenna.c | 2 +- .../src/networking/phy_layer/phy_layer.c | 4 +- df_datalink_sp/src/system_monitor.h | 2 +- makecopy | 4 +- 5 files changed, 102 insertions(+), 103 deletions(-) diff --git a/df_datalink_sp/src/config/app_config.h b/df_datalink_sp/src/config/app_config.h index 2a3e398..f9d6463 100644 --- a/df_datalink_sp/src/config/app_config.h +++ b/df_datalink_sp/src/config/app_config.h @@ -23,11 +23,11 @@ #include "xparameters.h" /******** Software Version ********/ -#define _APP_VER 0x00010008 +#define _APP_VER 0x00010008 -#define _APP_VER_MAIN ((_APP_VER & 0xFF000000) >> 24) -#define _APP_VER_MINOR ((_APP_VER & 0x00FF0000) >> 16) -#define _APP_VER_PATCH (_APP_VER & 0x0000FFFF) +#define _APP_VER_MAIN ((_APP_VER & 0xFF000000) >> 24) +#define _APP_VER_MINOR ((_APP_VER & 0x00FF0000) >> 16) +#define _APP_VER_PATCH (_APP_VER & 0x0000FFFF) /*********** Debug Info Level ************/ // #define _DEBUG_LEVEL 1 @@ -38,13 +38,13 @@ #define DATALINK_ENABLE_AUTORECONNECT #define DATALINK_ENABLE_AUTOTIMESYNC -//#define DATALINK_ENABLE_BERTEST +// #define DATALINK_ENABLE_BERTEST /************ Hardware Configs ************/ -#define CPU_CLK_HZ XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ -#define GLOBAL_TIMER_CLK_HZ (CPU_CLK_HZ/2) -#define SCU_TIMER_CLK_HZ (CPU_CLK_HZ/2) -#define FCLK_CLK0_HZ 100000000 +#define CPU_CLK_HZ XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ +#define GLOBAL_TIMER_CLK_HZ (CPU_CLK_HZ / 2) +#define SCU_TIMER_CLK_HZ (CPU_CLK_HZ / 2) +#define FCLK_CLK0_HZ 100000000 /********* Zynq Platform Configs **********/ // SCU Timer (for logging) @@ -53,7 +53,7 @@ // Physical Layer Configs #define PHY_DEVICE_ID 0 -#define PHY_BASEADDR XPAR_PHYC_BASEADDR +#define PHY_BASEADDR XPAR_PHYC_BASEADDR #define PHY_BEAM_FORMING_ENABLE // -- Antenna Bram Configs #define PHY_ANTCONFIG_BRAM_DEVICE_ID XPAR_PHY_DATA_INTERFACE_ANT_CONFIG_BRAM_CTRL_DEVICE_ID @@ -71,88 +71,88 @@ #define TIME_CONTROLLER_BASEADDR XPAR_TMC_BASEADDR // System Bus Configs -#define SYSBUS_BASE_ADDR XPAR_SYSTEMBUS_BASEADDR -#define SYSBUS_TX_INTR_ID XPAR_FABRIC_SYSTEMBUS_TX_DONE_INTR -#define SYSBUS_RX_INTR_ID XPAR_FABRIC_SYSTEMBUS_RX_DONE_INTR +#define SYSBUS_BASE_ADDR XPAR_SYSTEMBUS_BASEADDR +#define SYSBUS_TX_INTR_ID XPAR_FABRIC_SYSTEMBUS_TX_DONE_INTR +#define SYSBUS_RX_INTR_ID XPAR_FABRIC_SYSTEMBUS_RX_DONE_INTR // Global Timer config -#define GLOBAL_TIMER_DEVICE_ID XPAR_GLOBAL_TMR_DEVICE_ID -#define GLOBAL_TIMER_BASEADDR XPAR_GLOBAL_TMR_BASEADDR -#define GLOBAL_TIMER_INTR_ID XPAR_GLOBAL_TMR_INTR +#define GLOBAL_TIMER_DEVICE_ID XPAR_GLOBAL_TMR_DEVICE_ID +#define GLOBAL_TIMER_BASEADDR XPAR_GLOBAL_TMR_BASEADDR +#define GLOBAL_TIMER_INTR_ID XPAR_GLOBAL_TMR_INTR // INTC configis #define INTC_DEVICE_ID XPAR_SCUGIC_0_DEVICE_ID // AD9361 Configuration #define SPI_INTERFACE_SPI_ENGINE -#define HAVE_SPLIT_GAIN_TABLE 1 /* only set to 0 in case split_gain_table_mode_enable = 0*/ -#define HAVE_TDD_SYNTH_TABLE 1 /* only set to 0 in case split_gain_table_mode_enable = 0*/ -#define AD9361_DEVICE 1 /* set it 1 if AD9361 device is used, 0 otherwise */ -#define AD9364_DEVICE 0 /* set it 1 if AD9364 device is used, 0 otherwise */ -#define AD9363A_DEVICE 0 /* set it 1 if AD9363A device is used, 0 otherwise */ -#define HAVE_VERBOSE_MESSAGES /* Recommended during development prints errors and warnings */ -//#define HAVE_DEBUG_MESSAGES /* For Debug purposes only */ -// -- AD9361 SPI Engine Configuration -#define AD9361_SPI_DEVICE_ID 0 -#define AD9361_SPI_ENGINE_REF_CLK FCLK_CLK0_HZ -#define AD9361_SPI_ENGINE_MAX_SPEED 5000000 -#define AD9361_SPI_ENGINE_BASEADDR XPAR_AXI_SPI_ENGINE_AXI_SPI_ENGINE_BASEADDR -#define AD9361_SPI_ENGINE_DATA_WIDTH 8 -#define AD9361_SPI_ENGINE_CS_DELAY 3 -#define AD9361_SPI_CS_AD9361_1 0x01 -#define AD9361_SPI_CS_AD9361_2 0x02 -#define AD9361_TIMEOUT_TH 2000 +#define HAVE_SPLIT_GAIN_TABLE 1 /* only set to 0 in case split_gain_table_mode_enable = 0*/ +#define HAVE_TDD_SYNTH_TABLE 1 /* only set to 0 in case split_gain_table_mode_enable = 0*/ +#define AD9361_DEVICE 1 /* set it 1 if AD9361 device is used, 0 otherwise */ +#define AD9364_DEVICE 0 /* set it 1 if AD9364 device is used, 0 otherwise */ +#define AD9363A_DEVICE 0 /* set it 1 if AD9363A device is used, 0 otherwise */ +#define HAVE_VERBOSE_MESSAGES /* Recommended during development prints errors and warnings */ +// #define HAVE_DEBUG_MESSAGES /* For Debug purposes only */ +// -- AD9361 SPI Engine Configuration +#define AD9361_SPI_DEVICE_ID 0 +#define AD9361_SPI_ENGINE_REF_CLK FCLK_CLK0_HZ +#define AD9361_SPI_ENGINE_MAX_SPEED 5000000 +#define AD9361_SPI_ENGINE_BASEADDR XPAR_AXI_SPI_ENGINE_AXI_SPI_ENGINE_BASEADDR +#define AD9361_SPI_ENGINE_DATA_WIDTH 8 +#define AD9361_SPI_ENGINE_CS_DELAY 3 +#define AD9361_SPI_CS_AD9361_1 0x01 +#define AD9361_SPI_CS_AD9361_2 0x02 +#define AD9361_TIMEOUT_TH 2000 // AD9361 GPIO Configurations -#define AD9361_GPIO_DEVICE_ID 0 -#define AD9361_GPIO_OFFSET 54 -#define AD9361_GPIO_INPUT 0 -#define AD9361_GPIO_OUTPUT 1 -#define AD9361_GPIO_DISABLE 0 -#define AD9361_GPIO_ENABLE 1 +#define AD9361_GPIO_DEVICE_ID 0 +#define AD9361_GPIO_OFFSET 54 +#define AD9361_GPIO_INPUT 0 +#define AD9361_GPIO_OUTPUT 1 +#define AD9361_GPIO_DISABLE 0 +#define AD9361_GPIO_ENABLE 1 // -- AD9361-1 -#define AD9361_1_TXNRX (AD9361_GPIO_OFFSET+6) -#define AD9361_1_ENABLE (AD9361_GPIO_OFFSET+7) -#define AD9361_1_EN_AGC (AD9361_GPIO_OFFSET+8) -#define AD9361_1_RESET_B (AD9361_GPIO_OFFSET+9) -#define AD9361_1_CTRL_OUT0 (AD9361_GPIO_OFFSET+10) -#define AD9361_1_CTRL_OUT1 (AD9361_GPIO_OFFSET+11) -#define AD9361_1_CTRL_OUT2 (AD9361_GPIO_OFFSET+12) -#define AD9361_1_CTRL_OUT3 (AD9361_GPIO_OFFSET+13) -#define AD9361_1_CTRL_OUT4 (AD9361_GPIO_OFFSET+14) -#define AD9361_1_CTRL_OUT5 (AD9361_GPIO_OFFSET+15) -#define AD9361_1_CTRL_OUT6 (AD9361_GPIO_OFFSET+16) -#define AD9361_1_CTRL_OUT7 (AD9361_GPIO_OFFSET+17) -#define AD9361_1_CTRL_IN0 (AD9361_GPIO_OFFSET+18) -#define AD9361_1_CTRL_IN1 (AD9361_GPIO_OFFSET+19) -#define AD9361_1_CTRL_IN2 (AD9361_GPIO_OFFSET+20) -#define AD9361_1_CTRL_IN3 (AD9361_GPIO_OFFSET+21) +#define AD9361_1_TXNRX (AD9361_GPIO_OFFSET + 6) +#define AD9361_1_ENABLE (AD9361_GPIO_OFFSET + 7) +#define AD9361_1_EN_AGC (AD9361_GPIO_OFFSET + 8) +#define AD9361_1_RESET_B (AD9361_GPIO_OFFSET + 9) +#define AD9361_1_CTRL_OUT0 (AD9361_GPIO_OFFSET + 10) +#define AD9361_1_CTRL_OUT1 (AD9361_GPIO_OFFSET + 11) +#define AD9361_1_CTRL_OUT2 (AD9361_GPIO_OFFSET + 12) +#define AD9361_1_CTRL_OUT3 (AD9361_GPIO_OFFSET + 13) +#define AD9361_1_CTRL_OUT4 (AD9361_GPIO_OFFSET + 14) +#define AD9361_1_CTRL_OUT5 (AD9361_GPIO_OFFSET + 15) +#define AD9361_1_CTRL_OUT6 (AD9361_GPIO_OFFSET + 16) +#define AD9361_1_CTRL_OUT7 (AD9361_GPIO_OFFSET + 17) +#define AD9361_1_CTRL_IN0 (AD9361_GPIO_OFFSET + 18) +#define AD9361_1_CTRL_IN1 (AD9361_GPIO_OFFSET + 19) +#define AD9361_1_CTRL_IN2 (AD9361_GPIO_OFFSET + 20) +#define AD9361_1_CTRL_IN3 (AD9361_GPIO_OFFSET + 21) // AD9361-2 -#define AD9361_2_TXNRX (AD9361_GPIO_OFFSET+22) -#define AD9361_2_ENABLE (AD9361_GPIO_OFFSET+23) -#define AD9361_2_EN_AGC (AD9361_GPIO_OFFSET+24) -#define AD9361_2_RESET_B (AD9361_GPIO_OFFSET+25) -#define AD9361_2_CTRL_OUT0 (AD9361_GPIO_OFFSET+26) -#define AD9361_2_CTRL_OUT1 (AD9361_GPIO_OFFSET+27) -#define AD9361_2_CTRL_OUT2 (AD9361_GPIO_OFFSET+28) -#define AD9361_2_CTRL_OUT3 (AD9361_GPIO_OFFSET+29) -#define AD9361_2_CTRL_OUT4 (AD9361_GPIO_OFFSET+30) -#define AD9361_2_CTRL_OUT5 (AD9361_GPIO_OFFSET+31) -#define AD9361_2_CTRL_OUT6 (AD9361_GPIO_OFFSET+32) -#define AD9361_2_CTRL_OUT7 (AD9361_GPIO_OFFSET+33) -#define AD9361_2_CTRL_IN0 (AD9361_GPIO_OFFSET+34) -#define AD9361_2_CTRL_IN1 (AD9361_GPIO_OFFSET+35) -#define AD9361_2_CTRL_IN2 (AD9361_GPIO_OFFSET+36) -#define AD9361_2_CTRL_IN3 (AD9361_GPIO_OFFSET+37) +#define AD9361_2_TXNRX (AD9361_GPIO_OFFSET + 22) +#define AD9361_2_ENABLE (AD9361_GPIO_OFFSET + 23) +#define AD9361_2_EN_AGC (AD9361_GPIO_OFFSET + 24) +#define AD9361_2_RESET_B (AD9361_GPIO_OFFSET + 25) +#define AD9361_2_CTRL_OUT0 (AD9361_GPIO_OFFSET + 26) +#define AD9361_2_CTRL_OUT1 (AD9361_GPIO_OFFSET + 27) +#define AD9361_2_CTRL_OUT2 (AD9361_GPIO_OFFSET + 28) +#define AD9361_2_CTRL_OUT3 (AD9361_GPIO_OFFSET + 29) +#define AD9361_2_CTRL_OUT4 (AD9361_GPIO_OFFSET + 30) +#define AD9361_2_CTRL_OUT5 (AD9361_GPIO_OFFSET + 31) +#define AD9361_2_CTRL_OUT6 (AD9361_GPIO_OFFSET + 32) +#define AD9361_2_CTRL_OUT7 (AD9361_GPIO_OFFSET + 33) +#define AD9361_2_CTRL_IN0 (AD9361_GPIO_OFFSET + 34) +#define AD9361_2_CTRL_IN1 (AD9361_GPIO_OFFSET + 35) +#define AD9361_2_CTRL_IN2 (AD9361_GPIO_OFFSET + 36) +#define AD9361_2_CTRL_IN3 (AD9361_GPIO_OFFSET + 37) // AD9361-Status Code -#define AD9361_SYNC (AD9361_GPIO_OFFSET+38) -#define AD9361_RX_FIFO_RST (AD9361_GPIO_OFFSET+39) -#define AD9361_1_CAL_START (AD9361_GPIO_OFFSET+40) -#define AD9361_2_CAL_START (AD9361_GPIO_OFFSET+41) -#define AD9361_RECAL (AD9361_GPIO_OFFSET+42) -#define AD9361_TX_SWITCH (AD9361_GPIO_OFFSET+43) -#define AD9361_1_CAL_DONE (AD9361_GPIO_OFFSET+44) -#define AD9361_2_CAL_DONE (AD9361_GPIO_OFFSET+45) -#define AD9361_CAL_RESULT (AD9361_GPIO_OFFSET+46) +#define AD9361_SYNC (AD9361_GPIO_OFFSET + 38) +#define AD9361_RX_FIFO_RST (AD9361_GPIO_OFFSET + 39) +#define AD9361_1_CAL_START (AD9361_GPIO_OFFSET + 40) +#define AD9361_2_CAL_START (AD9361_GPIO_OFFSET + 41) +#define AD9361_RECAL (AD9361_GPIO_OFFSET + 42) +#define AD9361_TX_SWITCH (AD9361_GPIO_OFFSET + 43) +#define AD9361_1_CAL_DONE (AD9361_GPIO_OFFSET + 44) +#define AD9361_2_CAL_DONE (AD9361_GPIO_OFFSET + 45) +#define AD9361_CAL_RESULT (AD9361_GPIO_OFFSET + 46) typedef enum { @@ -162,23 +162,22 @@ typedef enum } ad9361TxFreq; // HMC7044 Configurations -#define HMC7044_GPIO_DEVICE_ID 0 -#define HMC7044_GPIO_OFFSET 54 -#define HMC7044_RESET (HMC7044_GPIO_OFFSET+0) -#define HMC7044_SYNC (HMC7044_GPIO_OFFSET+1) -#define HMC7044_GPIO_0 (HMC7044_GPIO_OFFSET+2) -#define HMC7044_GPIO_1 (HMC7044_GPIO_OFFSET+3) -#define HMC7044_GPIO_2 (HMC7044_GPIO_OFFSET+4) -#define HMC7044_GPIO_3 (HMC7044_GPIO_OFFSET+5) +#define HMC7044_GPIO_DEVICE_ID 0 +#define HMC7044_GPIO_OFFSET 54 +#define HMC7044_RESET (HMC7044_GPIO_OFFSET + 0) +#define HMC7044_SYNC (HMC7044_GPIO_OFFSET + 1) +#define HMC7044_GPIO_0 (HMC7044_GPIO_OFFSET + 2) +#define HMC7044_GPIO_1 (HMC7044_GPIO_OFFSET + 3) +#define HMC7044_GPIO_2 (HMC7044_GPIO_OFFSET + 4) +#define HMC7044_GPIO_3 (HMC7044_GPIO_OFFSET + 5) // -- HMC7044 SPI Engine Configuration -#define HMC7044_SPI_DEVICE_ID 0 -#define HMC7044_SPI_ENGINE_REF_CLK FCLK_CLK0_HZ -#define HMC7044_SPI_ENGINE_MAX_SPEED 5000000 -#define HMC7044_SPI_ENGINE_BASEADDR XPAR_AXI_SPI_ENGINE_AXI_SPI_ENGINE_BASEADDR -#define HMC7044_SPI_ENGINE_DATA_WIDTH 8 -#define HMC7044_SPI_ENGINE_CS_DELAY 3 -#define HMC7044_SPI_CS_HMC7044 0x00 - +#define HMC7044_SPI_DEVICE_ID 0 +#define HMC7044_SPI_ENGINE_REF_CLK FCLK_CLK0_HZ +#define HMC7044_SPI_ENGINE_MAX_SPEED 5000000 +#define HMC7044_SPI_ENGINE_BASEADDR XPAR_AXI_SPI_ENGINE_AXI_SPI_ENGINE_BASEADDR +#define HMC7044_SPI_ENGINE_DATA_WIDTH 8 +#define HMC7044_SPI_ENGINE_CS_DELAY 3 +#define HMC7044_SPI_CS_HMC7044 0x00 // Configuration Check #if defined(PHY_BEAM_SET_PRESET) && !defined(PHY_BEAM_FORMING_ENABLE) @@ -188,7 +187,7 @@ typedef enum #if defined(DATALINK_ENABLE_BERTEST) #if !defined(DATALINK_ENABLE_AUTOTIMESYNC) - #warning To enbale bit error rate test, auto time-sync should be enabled... +#warning To enbale bit error rate test, auto time-sync should be enabled... #endif #endif diff --git a/df_datalink_sp/src/networking/phy_layer/phy_antenna.c b/df_datalink_sp/src/networking/phy_layer/phy_antenna.c index a8dbfad..f5ad869 100644 --- a/df_datalink_sp/src/networking/phy_layer/phy_antenna.c +++ b/df_datalink_sp/src/networking/phy_layer/phy_antenna.c @@ -80,7 +80,7 @@ const uint16_t freqTable[L1_FRAME_MAX_HOPS] = 1916, 1929, 1942, 1955, 1968, 1981, 1994, 2007, 2020, 2033, 2046, 2059, 2072, 2085, 2098, 2111, 2124 -} +}; const uint16_t antCalTable[L1_FRAME_MAX_HOPS][L1_ANT_NUM_CH] = //Antenna-JG01 diff --git a/df_datalink_sp/src/networking/phy_layer/phy_layer.c b/df_datalink_sp/src/networking/phy_layer/phy_layer.c index a15d199..ad97167 100644 --- a/df_datalink_sp/src/networking/phy_layer/phy_layer.c +++ b/df_datalink_sp/src/networking/phy_layer/phy_layer.c @@ -425,7 +425,7 @@ int32_t Phy_Init(PHY_INST **instPtr, PHY_CONFIG *phyConfig) memset(&((*instPtr))->tor, PHY_TOR_SUSPEND, sizeof(PHY_RCD)); memset(&((*instPtr)->frameType), L1_NONE_FRAME, sizeof(PHY_RCD)); - memset(&((*instPtr)->beamNo), (int32_t)L1_INIT_ANT_NO, sizeof(PHY_RCD)); + memset(&((*instPtr)->beamNo), (int32_t)L1_INIT_BEAM_NO, sizeof(PHY_RCD)); memset(&((*instPtr)->beamWd), (int32_t)L1_INIT_ANT_WD, sizeof(PHY_RCD)); memset(&((*instPtr)->hwSate), 0x00, sizeof(HWSTATE)); memset(&((*instPtr)->phyLog), 0x00, sizeof(PHYLOG)); @@ -1152,7 +1152,7 @@ void Phy_RefreshHwSate(PHY_INST *instPtr) instPtr->hwSate.isAntOk = (instPtr->hwSate.antVolt == (VOLT_ANT_PROC_OK | VOLT_ANT_RF_OK | VOLT_ANT_NIL_OK | ANT_STATE_OK)) && (instPtr->hwSate.antPll == (CLK_ANT_BBPLL_LOCK | CLK_ANT_RFPLL0_LOCK | CLK_ANT_RFPLL1_LOCK)); - instPtr->hwSate.phyId = instPtr.phyCofig.devId; + instPtr->hwSate.phyId = instPtr->phyCofig.devId; memset(instPtr->hwSate.reserve, 0x00, sizeof(instPtr->hwSate.reserve)); diff --git a/df_datalink_sp/src/system_monitor.h b/df_datalink_sp/src/system_monitor.h index 574355d..849dabc 100644 --- a/df_datalink_sp/src/system_monitor.h +++ b/df_datalink_sp/src/system_monitor.h @@ -204,7 +204,7 @@ typedef struct __attribute__((packed)) uint8_t antMgc0; ///< Antenna rf mgc0~1 indicator uint8_t antMgc1; ///< Antenna rf mgc2~3 indicator uint8_t phyId; - uint8_t reserve; + uint8_t reserve[1]; } HWSTATE; /** diff --git a/makecopy b/makecopy index 732bfd6..542de90 100755 --- a/makecopy +++ b/makecopy @@ -25,14 +25,14 @@ for key in ${!calMap[*]};do cd $DST_DIR/$projName # subtitite ID - sed -i'' "s/#define PHY_DEVICE_ID 0/#define PHY_DEVICE_ID $id/g" + sed -i'' "s/#define PHY_DEVICE_ID 0/#define PHY_DEVICE_ID 0x$id/g" ./config/app_config.h # subtitute table sed -i'' "/^const uint16_t antCalTable\[L1_FRAME_MAX_HOPS\]\[L1_ANT_NUM_CH\] =/{ :table N /\};/!b table - s/=.*\};/=\n\/\/Antenna-$key\n$calMap[$key]/ + s/=.*\};/=\n\/\/Antenna-$key\n${calMap[$key]}/ }" ./networking/phy_layer/phy_antenna.c cd $DST_DIR done \ No newline at end of file