diff --git a/df_datalink_sp/bsp/ps7_cortexa9_0/include/xparameters.h b/df_datalink_sp/bsp/ps7_cortexa9_0/include/xparameters.h
index ef591d0..485e44f 100644
--- a/df_datalink_sp/bsp/ps7_cortexa9_0/include/xparameters.h
+++ b/df_datalink_sp/bsp/ps7_cortexa9_0/include/xparameters.h
@@ -24,7 +24,7 @@
 
 /* Definitions for interface TMC */
 #define XPAR_TMC_BASEADDR 0x43C30000
-#define XPAR_TMC_HIGHADDR 0x43C3FFFF
+#define XPAR_TMC_HIGHADDR 0x43C30FFF
 
 #include "xparameters_ps.h"
 
@@ -57,7 +57,7 @@
 #define XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_ECC_ONOFF_RESET_VALUE 0U
 #define XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_WRITE_ACCESS 0U
 #define XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_S_AXI_BASEADDR 0x42000000U
-#define XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_S_AXI_HIGHADDR 0x42000FFFU
+#define XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_S_AXI_HIGHADDR 0x42001FFFU
 #define XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_S_AXI_CTRL_BASEADDR 0xFFFFFFFFU  
 #define XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_S_AXI_CTRL_HIGHADDR 0xFFFFFFFFU  
 
@@ -75,7 +75,7 @@
 #define XPAR_PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL_ECC_ONOFF_RESET_VALUE 0U
 #define XPAR_PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL_WRITE_ACCESS 0U
 #define XPAR_PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL_S_AXI_BASEADDR 0x40004000U
-#define XPAR_PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL_S_AXI_HIGHADDR 0x40005FFFU
+#define XPAR_PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL_S_AXI_HIGHADDR 0x40004FFFU
 #define XPAR_PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL_S_AXI_CTRL_BASEADDR 0xFFFFFFFFU  
 #define XPAR_PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL_S_AXI_CTRL_HIGHADDR 0xFFFFFFFFU  
 
@@ -93,7 +93,7 @@
 #define XPAR_PHY_DATA_INTERFACE_RX_FRAME_BRAM_CTRL_ECC_ONOFF_RESET_VALUE 0U
 #define XPAR_PHY_DATA_INTERFACE_RX_FRAME_BRAM_CTRL_WRITE_ACCESS 0U
 #define XPAR_PHY_DATA_INTERFACE_RX_FRAME_BRAM_CTRL_S_AXI_BASEADDR 0x40000000U
-#define XPAR_PHY_DATA_INTERFACE_RX_FRAME_BRAM_CTRL_S_AXI_HIGHADDR 0x40001FFFU
+#define XPAR_PHY_DATA_INTERFACE_RX_FRAME_BRAM_CTRL_S_AXI_HIGHADDR 0x40000FFFU
 #define XPAR_PHY_DATA_INTERFACE_RX_FRAME_BRAM_CTRL_S_AXI_CTRL_BASEADDR 0xFFFFFFFFU  
 #define XPAR_PHY_DATA_INTERFACE_RX_FRAME_BRAM_CTRL_S_AXI_CTRL_HIGHADDR 0xFFFFFFFFU  
 
@@ -111,7 +111,7 @@
 #define XPAR_PHY_DATA_INTERFACE_TX_FRAME_BRAM_CTRL_ECC_ONOFF_RESET_VALUE 0U
 #define XPAR_PHY_DATA_INTERFACE_TX_FRAME_BRAM_CTRL_WRITE_ACCESS 0U
 #define XPAR_PHY_DATA_INTERFACE_TX_FRAME_BRAM_CTRL_S_AXI_BASEADDR 0x40002000U
-#define XPAR_PHY_DATA_INTERFACE_TX_FRAME_BRAM_CTRL_S_AXI_HIGHADDR 0x40003FFFU
+#define XPAR_PHY_DATA_INTERFACE_TX_FRAME_BRAM_CTRL_S_AXI_HIGHADDR 0x40002FFFU
 #define XPAR_PHY_DATA_INTERFACE_TX_FRAME_BRAM_CTRL_S_AXI_CTRL_BASEADDR 0xFFFFFFFFU  
 #define XPAR_PHY_DATA_INTERFACE_TX_FRAME_BRAM_CTRL_S_AXI_CTRL_HIGHADDR 0xFFFFFFFFU  
 
@@ -131,7 +131,7 @@
 #define XPAR_BRAM_0_ECC_ONOFF_RESET_VALUE 0U
 #define XPAR_BRAM_0_WRITE_ACCESS 0U
 #define XPAR_BRAM_0_BASEADDR 0x42000000U
-#define XPAR_BRAM_0_HIGHADDR 0x42000FFFU
+#define XPAR_BRAM_0_HIGHADDR 0x42001FFFU
 #define XPAR_BRAM_0_CTRL_BASEADDR 0xFFFFFFFFU  
 #define XPAR_BRAM_0_CTRL_HIGHADDR 0xFFFFFFFEU  
 
@@ -148,7 +148,7 @@
 #define XPAR_BRAM_1_ECC_ONOFF_RESET_VALUE 0U
 #define XPAR_BRAM_1_WRITE_ACCESS 0U
 #define XPAR_BRAM_1_BASEADDR 0x40004000U
-#define XPAR_BRAM_1_HIGHADDR 0x40005FFFU
+#define XPAR_BRAM_1_HIGHADDR 0x40004FFFU
 #define XPAR_BRAM_1_CTRL_BASEADDR 0xFFFFFFFFU  
 #define XPAR_BRAM_1_CTRL_HIGHADDR 0xFFFFFFFEU  
 
@@ -165,7 +165,7 @@
 #define XPAR_BRAM_2_ECC_ONOFF_RESET_VALUE 0U
 #define XPAR_BRAM_2_WRITE_ACCESS 0U
 #define XPAR_BRAM_2_BASEADDR 0x40000000U
-#define XPAR_BRAM_2_HIGHADDR 0x40001FFFU
+#define XPAR_BRAM_2_HIGHADDR 0x40000FFFU
 #define XPAR_BRAM_2_CTRL_BASEADDR 0xFFFFFFFFU  
 #define XPAR_BRAM_2_CTRL_HIGHADDR 0xFFFFFFFEU  
 
@@ -182,7 +182,7 @@
 #define XPAR_BRAM_3_ECC_ONOFF_RESET_VALUE 0U
 #define XPAR_BRAM_3_WRITE_ACCESS 0U
 #define XPAR_BRAM_3_BASEADDR 0x40002000U
-#define XPAR_BRAM_3_HIGHADDR 0x40003FFFU
+#define XPAR_BRAM_3_HIGHADDR 0x40002FFFU
 #define XPAR_BRAM_3_CTRL_BASEADDR 0xFFFFFFFFU  
 #define XPAR_BRAM_3_CTRL_HIGHADDR 0xFFFFFFFEU  
 
@@ -346,7 +346,7 @@
 
 /* Definitions for peripheral SYSTEMBUS */
 #define XPAR_SYSTEMBUS_BASEADDR 0x43C10000
-#define XPAR_SYSTEMBUS_HIGHADDR 0x43C11FFF
+#define XPAR_SYSTEMBUS_HIGHADDR 0x43C10FFF
 
 
 /******************************************************************/