*bugfix: complete tmc configurations.

This commit is contained in:
Gatsby Van
2024-01-25 10:36:07 +08:00
parent 49a934e3d4
commit fea9795b5a
4 changed files with 8 additions and 2 deletions
+3
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@@ -67,6 +67,9 @@
#define PHY_INTR_ID XPAR_FABRIC_PHY_IRQ_INTR #define PHY_INTR_ID XPAR_FABRIC_PHY_IRQ_INTR
#define PERIODIC_5MS_INTR_ID XPAR_FABRIC_PHY_5MS_DELAY_2MS_INTR #define PERIODIC_5MS_INTR_ID XPAR_FABRIC_PHY_5MS_DELAY_2MS_INTR
// Time Controller Configs
#define TIME_CONTROLLER_BASEADDR XPAR_TMC_BASEADDR
// System Bus Configs // System Bus Configs
//#define SYSBUS_BASE_ADDR XPAR_SYSTEMBUS_BASEADDR //#define SYSBUS_BASE_ADDR XPAR_SYSTEMBUS_BASEADDR
//#define SYSBUS_TX_INTR_ID XPAR_FABRIC_SYSTEMBUS_TX_DONE_INTR //#define SYSBUS_TX_INTR_ID XPAR_FABRIC_SYSTEMBUS_TX_DONE_INTR
+1 -1
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@@ -108,7 +108,7 @@ static PHY_CONFIG phyConfig = {
}; };
TMC_CONFIG tmcConfig = { TMC_CONFIG tmcConfig = {
.baseAddr = 0, //TIME_CONTROLLER_BASEADDR, .baseAddr = TIME_CONTROLLER_BASEADDR,
.reset = 10 .reset = 10
}; };
+3
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@@ -67,6 +67,9 @@
#define PHY_INTR_ID XPAR_FABRIC_PHY_IRQ_INTR #define PHY_INTR_ID XPAR_FABRIC_PHY_IRQ_INTR
#define PERIODIC_5MS_INTR_ID XPAR_FABRIC_PHY_5MS_DELAY_2MS_INTR #define PERIODIC_5MS_INTR_ID XPAR_FABRIC_PHY_5MS_DELAY_2MS_INTR
// Time Controller Configs
#define TIME_CONTROLLER_BASEADDR XPAR_TMC_BASEADDR
// System Bus Configs // System Bus Configs
#define SYSBUS_BASE_ADDR XPAR_SYSTEMBUS_BASEADDR #define SYSBUS_BASE_ADDR XPAR_SYSTEMBUS_BASEADDR
#define SYSBUS_TX_INTR_ID XPAR_FABRIC_SYSTEMBUS_TX_DONE_INTR #define SYSBUS_TX_INTR_ID XPAR_FABRIC_SYSTEMBUS_TX_DONE_INTR
+1 -1
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@@ -104,7 +104,7 @@ static PHY_CONFIG phyConfig = {
}; };
TMC_CONFIG tmcConfig = { TMC_CONFIG tmcConfig = {
.baseAddr = 0, //TIME_CONTROLLER_BASEADDR, .baseAddr = TIME_CONTROLLER_BASEADDR,
.reset = 10 .reset = 10
}; };