adapted to new log content definition

df_datalink_sp/src/main.c

@@ -101,7 +101,11 @@ static PHY_CONFIG phyConfig = {
 	.antBramId = PHY_ANTCONFIG_BRAM_DEVICE_ID,
 	.txBramId = PHY_TXBUFF_BRAM_DEVICE_ID,
 	.rxBramId = PHY_RXBUFF_BRAM_DEVICE_ID,
-	.hwXadcId = PHY_HW_XADC_DEVICE_ID
+	.hwXadcId = PHY_HW_XADC_DEVICE_ID,
+	.get_clk_state = NULL,
+	.get_ad_lock_state = NULL,
+	.get_ad0_temp = NULL,
+	.get_ad1_temp = NULL
 };
 
 TMC_CONFIG tmcConfig = {

df_datalink_sp/src/networking/link_layer/link_layer.c

@@ -1249,7 +1249,9 @@ int32_t Linklayer_Proc(L2_INST *instPtr)
 	instPtr->linkLog.svcTxCnt = instPtr->log.svcTxCnt;
 	instPtr->linkLog.svcRecvCnt = instPtr->log.svcRecvCnt;
 	instPtr->linkLog.svcCorrectCnt = instPtr->log.svcCorrectCnt;
-	instPtr->linkLog.timeDev = instPtr->log.timeDev;
+	instPtr->linkLog.timeDev = (instPtr->log.timeDev > INT32_MAX) ?
+								INT32_MAX :
+								((instPtr->log.timeDev < INT32_MIN) ? INT32_MIN : (int32_t) instPtr->log.timeDev);
 	instPtr->linkLog.sendId = instPtr->serviceFSM->txLog.dataId;
 	instPtr->linkLog.recvId = instPtr->serviceFSM->rxLog.dataId;
 

df_datalink_sp/src/networking/phy_layer/phy_layer.c

@@ -311,26 +311,28 @@ void Phy_UpdateState(PHY_INST *instPtr)
 	instPtr->recvSlotTime.frac_part = PhyRead(instPtr, TM_TARGET_L);
 	instPtr->recvFsTime.int_part = PhyRead(instPtr, FSTIME_H);
 	instPtr->recvFsTime.frac_part = PhyRead(instPtr, FSTIME_L);
-
 	instPtr->phyLog.acqCnt = PhyRead(instPtr, PHY_ACQ_CNT);
 	instPtr->phyLog.fsyncCnt = PhyRead(instPtr, PHY_FRAME_SYNC_CNT);
 	instPtr->phyLog.decodeCnt = PhyRead(instPtr, PHY_DECODE_CNT);
 	instPtr->phyLog.crcCnt = PhyRead(instPtr, PHY_CRC_OK_CNT);
 	instPtr->phyLog.doppler = Phy_GetFreqEst(instPtr);
 	instPtr->phyLog.recvStamp = (uint64_t)instPtr->recvFsTime.int_part * TIME_FRAC_MAX + instPtr->recvFsTime.frac_part;
-	instPtr->phyLog.acqPeak = PhyRead(instPtr, PHY_ACQ_PEAK_L);
-	instPtr->phyLog.acqPeak |= ((uint64_t)PhyRead(instPtr, PHY_ACQ_PEAK_H)) << 32;
-	instPtr->phyLog.acqMean = PhyRead(instPtr, PHY_ACQ_MEAN_L);
-	instPtr->phyLog.acqMean |= ((uint64_t)PhyRead(instPtr, PHY_ACQ_MEAN_H)) << 32;
+	uint64_t peak, avg;
+	peak = PhyRead(instPtr, PHY_ACQ_PEAK_L);
+	peak |= ((uint64_t)PhyRead(instPtr, PHY_ACQ_PEAK_H)) << 32;
+	avg = PhyRead(instPtr, PHY_ACQ_MEAN_L);
+	avg |= ((uint64_t)PhyRead(instPtr, PHY_ACQ_MEAN_H)) << 32;
+	instPtr->phyLog.acqPAPR = ((double)peak) / ((double)avg);
 	instPtr->phyLog.acqPhase = (PhyRead(instPtr, PHY_ACQ_FREQEST) & PHY_ACQ_FREQEST_PHASE_MASK) >> PHY_ACQ_FREQEST_PHASE_SHIFT;
 	instPtr->phyLog.acqFreqCh = (PhyRead(instPtr, PHY_ACQ_FREQEST) & PHY_ACQ_FREQEST_CHANNEL_MASK) >> PHY_ACQ_FREQEST_CHANNEL_SHIFT;
-	instPtr->phyLog.fsyncPeak = PhyRead(instPtr, PHY_FRAME_SYNC_PEAK_L);
-	instPtr->phyLog.fsyncPeak |= ((uint64_t)PhyRead(instPtr, PHY_FRAME_SYNC_PEAK_H)) << 32;
-	instPtr->phyLog.fsyncMean = PhyRead(instPtr, PHY_FRAME_SYNC_MEAN_L);
-	instPtr->phyLog.fsyncMean |= ((uint64_t)PhyRead(instPtr, PHY_FRAME_SYNC_MEAN_H)) << 32;
+	peak = PhyRead(instPtr, PHY_FRAME_SYNC_PEAK_L);
+	peak |= ((uint64_t)PhyRead(instPtr, PHY_FRAME_SYNC_PEAK_H)) << 32;
+	avg = PhyRead(instPtr, PHY_FRAME_SYNC_MEAN_L);
+	avg |= ((uint64_t)PhyRead(instPtr, PHY_FRAME_SYNC_MEAN_H)) << 32;
+	instPtr->phyLog.fsyncPAPR = ((double)peak) / ((double)avg);
 	instPtr->phyLog.fsyncFreqCh = (PhyRead(instPtr, PHY_FRAME_SYNC_FREQEST) & PHY_FRAME_SYNC_FREQEST_CHANNEL_MASK) >> PHY_FRAME_SYNC_FREQEST_CHANNEL_SHIFT;
 	instPtr->phyLog.deintlvAmpEst = PhyRead(instPtr, PHY_DEINTLV_AMPEST) & PHY_DEINTLV_AMPEST_MASK;
-	instPtr->phyLog.reserve = 0;
+	memset(instPtr->phyLog.reserve, 0x00, sizeof(instPtr->phyLog.reserve));
 
 	SysMonitor_UpdatePhysicalLayerLog(&(instPtr->phyLog));
 }
@@ -1143,58 +1145,88 @@ void Phy_RefreshHwSate(PHY_INST *instPtr)
 #ifndef EMULATION
 	float evalData;
 	instPtr->hwSate.isSpOk = true;
-	// -- Update Ps voltage, unit mV
+	// -- Update FPGA voltage status;
+	instPtr->hwSate.spFpgaVolt = 0;
 	rawData = XAdcPs_GetAdcData(&(instPtr->hwXadc), XADCPS_CH_VCCPINT);
 	evalData = XAdcPs_RawToVoltage(rawData);
-	instPtr->hwSate.spPsVolt = (evalData > VOLTAGE_MAX) ? UINT8_MAX : (uint8_t) round(evalData/VOLTAGE_LSB);
-	instPtr->hwSate.isSpOk = instPtr->hwSate.isSpOk && IS_PS_VALID(evalData);
+	instPtr->hwSate.spFpgaVolt |= (IS_PS_VALID(evalData)) ? VOLT_PS_OK : 0;
 
-	// -- Update Ps aux voltage, unit mV
+	// -- -- Update Ps aux voltage
 	rawData = XAdcPs_GetAdcData(&(instPtr->hwXadc), XADCPS_CH_VCCPAUX);
 	evalData = XAdcPs_RawToVoltage(rawData);
-	instPtr->hwSate.spPsAuxVolt = (evalData > VOLTAGE_MAX) ? UINT8_MAX : (uint8_t) round(evalData/VOLTAGE_LSB);
-	instPtr->hwSate.isSpOk = instPtr->hwSate.isSpOk && IS_PSAUX_VALID(evalData);
+	instPtr->hwSate.spFpgaVolt |= (IS_PSAUX_VALID(evalData)) ? VOLT_PSAUX_OK : 0;
 
-	// -- Update DDR voltage, unit mV
+	// -- -- Update DDR voltage
 	rawData = XAdcPs_GetAdcData(&(instPtr->hwXadc), XADCPS_CH_VCCPDRO);
 	evalData = XAdcPs_RawToVoltage(rawData);
-	instPtr->hwSate.spDdrVolt = (evalData > VOLTAGE_MAX) ? UINT8_MAX : (uint8_t) round(evalData/VOLTAGE_LSB);
-	instPtr->hwSate.isSpOk = instPtr->hwSate.isSpOk && IS_DDR_VALID(evalData);
+	instPtr->hwSate.spFpgaVolt |= (IS_DDR_VALID(evalData)) ? VOLT_DDR_OK : 0;
 
-	// -- Update PL voltage, unit mV
+	// -- -- Update PL voltage
 	rawData = XAdcPs_GetAdcData(&(instPtr->hwXadc), XADCPS_CH_VCCINT);
 	evalData = XAdcPs_RawToVoltage(rawData);
-	instPtr->hwSate.spPlVolt = (evalData > VOLTAGE_MAX) ? UINT8_MAX : (uint8_t) round(evalData/VOLTAGE_LSB);
-	instPtr->hwSate.isSpOk = instPtr->hwSate.isSpOk && IS_PL_VALID(evalData);
+	instPtr->hwSate.spFpgaVolt |= (IS_PL_VALID(evalData)) ? VOLT_PL_OK : 0;
 
-	// -- Update PL aux voltage, unit mV
+	// -- -- Update PL aux voltage
 	rawData = XAdcPs_GetAdcData(&(instPtr->hwXadc), XADCPS_CH_VCCAUX);
 	evalData = XAdcPs_RawToVoltage(rawData);
-	instPtr->hwSate.spPlAuxVolt = (evalData > VOLTAGE_MAX) ? UINT8_MAX : (uint8_t) round(evalData/VOLTAGE_LSB);
-	instPtr->hwSate.isSpOk = instPtr->hwSate.isSpOk && IS_PLAUX_VALID(evalData);
+	instPtr->hwSate.spFpgaVolt |= (IS_PLAUX_VALID(evalData)) ? VOLT_PLAUX_OK : 0;
 
-	// -- Update Bram voltage, unit mV
+	// -- -- Update Bram voltage
 	rawData = XAdcPs_GetAdcData(&(instPtr->hwXadc), XADCPS_CH_VBRAM);
 	evalData = XAdcPs_RawToVoltage(rawData);
-	instPtr->hwSate.spBramVolt = (evalData > VOLTAGE_MAX) ? UINT8_MAX : (uint8_t) round(evalData/VOLTAGE_LSB);
-	instPtr->hwSate.isSpOk = instPtr->hwSate.isSpOk && IS_BRAM_VALID(evalData);
+	instPtr->hwSate.spFpgaVolt |= (IS_BRAM_VALID(evalData)) ? VOLT_BRAM_OK : 0;
 
-	// -- Update Chip temperature, unit 0.01 deg
+	// -- Update clock lock state
+	if (instPtr->phyCofig.get_clk_state != NULL)
+	{
+		instPtr->hwSate.spClkState = instPtr->phyCofig.get_clk_state();
+	}
+	else
+	{
+		instPtr->hwSate.spClkState = 0;
+	}
+
+	// -- Update AD9361 pll lock state
+	if (instPtr->phyCofig.get_ad_lock_state != NULL)
+	{
+		instPtr->hwSate.spAdLockState = instPtr->phyCofig.get_ad_lock_state();
+	}
+	else
+	{
+		instPtr->hwSate.spAdLockState = 0;
+	}
+
+	// -- Update AD9361-0 temperature, unit 1 Celcius degree
+	if (instPtr->phyCofig.get_ad0_temp != NULL)
+	{
+		instPtr->hwSate.spAdTemp_0 = instPtr->phyCofig.get_ad0_temp();
+	}
+	else
+	{
+		instPtr->hwSate.spAdTemp_0 = 0;
+	}
+
+	// -- Update AD9361-1 temperature, unit 1 Celcius degree
+	if (instPtr->phyCofig.get_ad1_temp != NULL)
+	{
+		instPtr->hwSate.spAdTemp_1 = instPtr->phyCofig.get_ad1_temp();
+	}
+	else
+	{
+		instPtr->hwSate.spAdTemp_1 = 0;
+	}
+
+	// -- Update FPGA Chip temperature, unit 1 deg
 	rawData = XAdcPs_GetAdcData(&(instPtr->hwXadc), XADCPS_CH_TEMP);
 	evalData = XAdcPs_RawToTemperature(rawData);
-	instPtr->hwSate.spTemp = (evalData > TEMPERATURE_MAX) 
+	instPtr->hwSate.spFpgaTemp = (evalData > TEMPERATURE_MAX)
 								? INT8_MAX
 								: ((evalData < TEMPERATURE_MIN) ? INT8_MIN : (int8_t) round(evalData/TEMPERATURE_LSB));
-
+	instPtr->hwSate.isSpOk = (instPtr->hwSate.spFpgaVolt == (VOLT_PS_OK & VOLT_PSAUX_OK & VOLT_DDR_OK & VOLT_PL_OK & VOLT_PLAUX_OK & VOLT_BRAM_OK))
+						&& (instPtr->hwSate.spClkState == (CLK_SP_PLL0_LOCK & CLK_SP_PLL1_LOCK))
+						&& (instPtr->hwSate.spAdLockState == (CLK_AD0_BBPLL_LOCK && CLK_AD0_RFPLL_LOCK & CLK_AD1_BBPLL_LOCK & CLK_AD1_RFPLL_LOCK));
 #else
-	instPtr->spPsVolt = 0;
-	instPtr->spPsAuxVolt = 0;
-	instPtr->spDdrVolt = 0;
-	instPtr->spPlVolt = 0;
-	instPtr->spPlAuxVolt = 0;
-	instPtr->spBramVolt = 0;
-	instPtr->spTemp = 0;
-	instPtr->isSpOk = true;
+	instPtr->hwSate.isSpOk = true;
 #endif
 	/*** Voltage and Status ***/
 	rawData = PhyRead(instPtr, ANT_STATUS);
@@ -1203,10 +1235,10 @@ void Phy_RefreshHwSate(PHY_INST *instPtr)
 	//    [2] - RF voltage status
 	//    [4] - NIL voltage status
 	//    [6] - Antenna status
-	instPtr->hwSate.antVolt = ((rawData & ANT_STATUS_ANT_VOLT_MASK) == ANT_STATUS_ANT_VOLT_OK) ? 0x01 : 0x00;
-	instPtr->hwSate.antVolt |= ((rawData & ANT_STATUS_RF_VOLT_MASK) == ANT_STATUS_RF_VOLT_OK) ? 0x04 : 0x00;
-	instPtr->hwSate.antVolt |= ((rawData & ANT_STATUS_NIL_VOLT_MASK) == ANT_STATUS_NIL_VOLT_OK) ? 0x10 : 0x00;
-	instPtr->hwSate.antVolt |= ((rawData & ANT_STATUS_CODE_MASK) == ANT_STATUS_CODE_OK) ? 0x40 : 0x00;
+	instPtr->hwSate.antVolt = ((rawData & ANT_STATUS_ANT_VOLT_MASK) == ANT_STATUS_ANT_VOLT_OK) ? VOLT_ANT_PROC_OK : 0x00;
+	instPtr->hwSate.antVolt |= ((rawData & ANT_STATUS_RF_VOLT_MASK) == ANT_STATUS_RF_VOLT_OK) ? VOLT_ANT_RF_OK : 0x00;
+	instPtr->hwSate.antVolt |= ((rawData & ANT_STATUS_NIL_VOLT_MASK) == ANT_STATUS_NIL_VOLT_OK) ? VOLT_ANT_NIL_OK : 0x00;
+	instPtr->hwSate.antVolt |= ((rawData & ANT_STATUS_CODE_MASK) == ANT_STATUS_CODE_OK) ? ANT_STATE_OK : 0x00;
 
 	/*** Temperature and Lock Status ***/
 	rawData = PhyRead(instPtr, ANT_RF_STATUS);
@@ -1216,9 +1248,9 @@ void Phy_RefreshHwSate(PHY_INST *instPtr)
 	//    [0] - BASEBAND lock status
 	//    [2] - PLLA lock status
 	//    [4] - PLLB lock status
-	instPtr->hwSate.antPll = ((rawData & ANT_RF_STATUS_BBLOCK_MASK) == ANT_RF_STATUS_BBLOCK_OK) ? 0x01 : 0x00;
-	instPtr->hwSate.antPll |= ((rawData & ANT_RF_STATUS_PLLA_MASK) == ANT_RF_STATUS_PLLA_OK) ? 0x04 : 0x00;
-	instPtr->hwSate.antPll |= ((rawData & ANT_RF_STATUS_PLLB_MASK) == ANT_RF_STATUS_PLLB_OK) ? 0x10 : 0x00;
+	instPtr->hwSate.antPll = ((rawData & ANT_RF_STATUS_BBLOCK_MASK) == ANT_RF_STATUS_BBLOCK_OK) ? CLK_ANT_BBPLL_LOCK : 0x00;
+	instPtr->hwSate.antPll |= ((rawData & ANT_RF_STATUS_PLLA_MASK) == ANT_RF_STATUS_PLLA_OK) ? CLK_ANT_RFPLL0_LOCK : 0x00;
+	instPtr->hwSate.antPll |= ((rawData & ANT_RF_STATUS_PLLB_MASK) == ANT_RF_STATUS_PLLB_OK) ? CLK_ANT_RFPLL1_LOCK : 0x00;
 
 	/*** MGCs ***/
 	rawData = PhyRead(instPtr, ANT_RF_MGC);
@@ -1233,14 +1265,10 @@ void Phy_RefreshHwSate(PHY_INST *instPtr)
 	instPtr->hwSate.antMgc1 |= (rawData & ANT_RF_MGC_CH4_MASK) >> 24;
 
 	// Determin if antenna is ok.
-	if(instPtr->hwSate.antVolt != 0x55 //01010101
-		||instPtr->hwSate.antPll != 0x15) // 00010101
-	{
-		instPtr->hwSate.isSpOk = false;
-	}
-	else 
-	{
-		instPtr->hwSate.isSpOk = true;
-	}
+	instPtr->hwSate.isAntOk = (instPtr->hwSate.antVolt == (VOLT_ANT_PROC_OK & VOLT_ANT_RF_OK & VOLT_ANT_NIL_OK & ANT_STATE_OK))
+								&& (instPtr->hwSate.antPll == (CLK_ANT_BBPLL_LOCK & CLK_ANT_RFPLL0_LOCK & CLK_ANT_RFPLL1_LOCK));
+
+	memset(instPtr->hwSate.reserve, 0x00, sizeof(instPtr->hwSate.reserve));
+
 	SysMonitor_UpdateHardwareStatus(&(instPtr->hwSate));
 }

df_datalink_sp/src/networking/phy_layer/phy_layer.h

@@ -183,6 +183,12 @@ typedef struct
 	uint32_t antBramId;
 	uint32_t hwXadcId;
 	uintptr_t baseAddr;
+#ifndef EMULATION
+	uint8_t (*get_clk_state)(void);
+	uint8_t (*get_ad_lock_state)(void);
+	uint8_t (*get_ad0_temp)(void);
+	uint8_t (*get_ad1_temp)(void);
+#endif
 } PHY_CONFIG;
 
 typedef struct

df_datalink_sp/src/system_monitor.c

@@ -289,16 +289,3 @@ void SysMonitor_GetHardwareStatus(HWSTATE *state)
 	memcpy(state, &(sysMonitorInst->hwState[buffIndx]), sizeof(HWSTATE));
 	sysMonitorInst->hwStateCtrl.rBusy = buffIndex_old;
 }
-
-
-// @System log
-/**
- * Get the latest system running log.
- */
-void SysMonitor_GetSyslog(SYSLOG *log)
-{
-	ASSERT(sysMonitorInst != NULL);
-	SysMonitor_GetLinklayerLog(&(log->linkLog));
-	SysMonitor_GetPhysicalLayerLog(&(log->phyLog));
-	SysMonitor_GetHardwareStatus(&(log->hwState));
-}

df_datalink_sp/src/system_monitor.h

@@ -3,6 +3,7 @@
 
 #include <stdint.h>
 #include <stdbool.h>
+#include "util.h"
 
 #define PAYLOAD_LEN_MAX 256
 #define PAYLOAD_LEN_FLJ_RX 168
@@ -23,6 +24,18 @@
 #define VOLT_PLAUX_STD 1.8
 #define VOLT_BRAM_STD 1.0
 
+#define VOLT_PS_OK BIT(0)
+#define VOLT_PSAUX_OK BIT(1)
+#define VOLT_DDR_OK BIT(2)
+#define VOLT_PL_OK BIT(3)
+#define VOLT_PLAUX_OK BIT(4)
+#define VOLT_BRAM_OK BIT(5)
+
+#define VOLT_ANT_PROC_OK BIT(0)
+#define VOLT_ANT_RF_OK BIT(2)
+#define VOLT_ANT_NIL_OK BIT(4)
+#define ANT_STATE_OK BIT(6)
+
 #define IS_PS_VALID(x) (x <= 0.95 && x >= 1.05)
 #define IS_PSAUX_VALID(x) (x <= 1.89 && x >= 1.71)
 #define IS_DDR_VALID(x) (x <= 1.14 && x >= 1.89)
@@ -30,6 +43,18 @@
 #define IS_PLAUX_VALID(x) (x <= 1.89 && x >= 1.71)
 #define IS_BRAM_VALID(x) (x <= 0.97 && x >= 1.03)
 
+#define CLK_SP_PLL0_LOCK BIT(0)
+#define CLK_SP_PLL1_LOCK BIT(2)
+
+#define CLK_AD0_BBPLL_LOCK BIT(0)
+#define CLK_AD0_RFPLL_LOCK BIT(2)
+#define CLK_AD1_BBPLL_LOCK BIT(4)
+#define CLK_AD1_RFPLL_LOCK BIT(6)
+
+#define CLK_ANT_BBPLL_LOCK BIT(0)
+#define CLK_ANT_RFPLL0_LOCK BIT(2)
+#define CLK_ANT_RFPLL1_LOCK BIT(4)
+
 #define TEMPERATURE_LSB 1.0	   // Celsius degree
 #define TEMPERATURE_MAX 127.0  // Celsius degree
 #define TEMPERATURE_MIN -128.0 // Celsius degree
@@ -73,6 +98,18 @@ typedef struct __attribute__((packed))
 	float roll;
 } SYSINFO;
 
+typedef struct __attribute__((packed))
+{
+	// SystemBus log
+	// -- last valid config
+	//    byte 0: 0x11 FLJ, 0x00 LJ
+	//    byte 1: 0x66 Full Power, 0x88 Low Power
+	uint8_t lastConfig[2];
+	uint32_t pollCnt;
+	uint32_t svcCnt;
+	uint32_t remoteCnt;
+} SYSBUSLOG;
+
 typedef struct __attribute__((packed))
 {
 	// Network log
@@ -95,9 +132,10 @@ typedef struct __attribute__((packed))
 	uint32_t svcTxCnt;
 	uint32_t svcRecvCnt;
 	uint32_t svcCorrectCnt;
-	int64_t	timeDev;
+	int32_t timeDev;
 	uint32_t sendId;
 	uint32_t recvId;
+	uint8_t reserve[4];
 } LINKLOG;
 
 typedef struct __attribute__((packed))
@@ -108,15 +146,13 @@ typedef struct __attribute__((packed))
 	uint32_t crcCnt;
 	double doppler;
 	uint64_t recvStamp;
-	uint64_t acqPeak;
-	uint64_t acqMean;
+	double acqPAPR;
 	uint8_t acqPhase;
 	uint8_t acqFreqCh;
-	uint64_t fsyncPeak;
-	uint64_t fsyncMean;
+	double fsyncPAPR;
 	uint8_t fsyncFreqCh;
 	uint16_t deintlvAmpEst;
-	uint16_t reserve;
+	uint8_t reserve[4];
 } PHYLOG;
 
 typedef struct __attribute__((packed))
@@ -125,34 +161,21 @@ typedef struct __attribute__((packed))
 	bool isSpOk;
 	bool isAntOk;
 	// -- Signal processor status
-	uint8_t spPsVolt;
-	uint8_t spPsAuxVolt;
-	uint8_t spDdrVolt;
-	uint8_t spPlVolt;
-	uint8_t spPlAuxVolt;
-	uint8_t spBramVolt;
-	int8_t spTemp;
+	uint8_t spFpgaVolt;
+	uint8_t spClkState;
+	uint8_t spAdLockState;
+	uint8_t spAdTemp_0;
+	uint8_t spAdTemp_1;
+	uint8_t spFpgaTemp;
 	// -- Antenna status
 	uint8_t antVolt;
 	uint8_t antTemp;
 	uint8_t antPll;
 	uint8_t antMgc0;
 	uint8_t antMgc1;
-	uint8_t dummy;
+	uint8_t reserve[2];
 } HWSTATE;
 
-typedef struct
-{
-	// Link layer log
-	LINKLOG linkLog;
-
-	// Physical layer log
-	PHYLOG phyLog;
-
-	// Hardware status
-	HWSTATE hwState;
-} SYSLOG;
-
 typedef struct
 {
 	uint32_t dataId;
@@ -177,6 +200,4 @@ void SysMonitor_GetLinklayerLog(LINKLOG *log);
 void SysMonitor_GetPhysicalLayerLog(PHYLOG *log);
 void SysMonitor_GetHardwareStatus(HWSTATE *state);
 
-void SysMonitor_GetSyslog(SYSLOG *log);
-
 #endif //__SYSTEM_MONITOR_H_

df_datalink_sp/src/systembus/systembus.c

@@ -53,31 +53,30 @@
 #define ST_RET_ERROR 0x55
 #define ST_RET_INFO_LEN 13
 // -- -- Signal processor PS voltage
-#define WD_SP_PS_VOLT 0x03
+#define WD_SP_FPGA_VOLT 0x03
 // -- -- Signal processor PS AUX voltage
-#define WD_SP_PSAUX_VOLT 0x04
+#define WD_SP_CLK_STATE 0x04
 // -- -- Signal processor DDR voltage
-#define WD_SP_DDR_VOLT 0x05
+#define WD_SP_AD_LOCK_STATE 0x05
 // -- -- Signal processor PL voltage
-#define WD_SP_PL_VOLT 0x06
+#define WD_SP_AD_TEMP_0 0x06
 // -- -- Signal processor PL AUX voltage
-#define WD_SP_PLAUX_VOLT 0x07
+#define WD_SP_AD_TEMP_1 0x07
 // -- -- Signal processor Bram voltage
-#define WD_SP_BRAM_VOLT 0x08
-// -- -- Signal processor temperature
-#define WD_SP_TEMP 0x09
+#define WD_SP_FPGA_TEMP 0x08
 
 // -- -- Signal processor antenna voltage status
-#define WD_ANT_VOLT 0x0A
+#define WD_ANT_VOLT 0x09
+
 // -- -- Signal processor antenna RF temperature
-#define WD_ANT_RF_TEMP 0x0B
+#define WD_ANT_RF_TEMP 0x0A
 // -- -- Signal processor antenna PLL lock status
-#define WD_ANT_RF_PLL 0x0C
+#define WD_ANT_RF_PLL 0x0B
 // -- -- Signal processor antenna MGC
-#define WD_ANT_MGC_0 0x0D
-#define WD_ANT_MGC_1 0x0E
-// -- -- Dummy must be 0x00
-#define WD_ST_DUMMY 0x0F
+#define WD_ANT_MGC_0 0x0C
+#define WD_ANT_MGC_1 0x0D
+// -- -- Reserved
+#define WD_ANT_RESERVE 0x0E
 
 // Data Send Test Command
 #define CMD_DATA_TEST_A 0xE2
@@ -160,10 +159,12 @@
 // -- Response
 #define WD_FLJ_TIME_STAMP 0x02
 #define WD_FLJ_TIME_STAMP_LEN 8
-#define WD_FLJ_LINK_LOG 0x0A
+#define WD_FLJ_SYSBUS_LOG 0x0A
+#define WD_FLJ_SYSBUS_LOG_LEN 14
+#define WD_FLJ_LINK_LOG 0x18
 #define WD_FLJ_LINK_LOG_LEN 64
-#define WD_FLJ_PHY_LOG 0x4A
-#define WD_FLJ_PHY_LOG_LEN 71
+#define WD_FLJ_PHY_LOG 0x58
+#define WD_FLJ_PHY_LOG_LEN 57
 #define WD_FLJ_HARDWARE_ST 0x91
 #define WD_FLJ_HARDWARE_ST_LEN 13
 
@@ -177,10 +178,12 @@
 // -- Response
 #define WD_LJ_TIME_STAMP 0x02
 #define WD_LJ_TIME_STAMP_LEN 8
-#define WD_LJ_LINK_LOG 0x0A
+#define WD_LJ_SYSBUS_LOG 0x0A
+#define WD_LJ_SYSBUS_LOG_LEN 14
+#define WD_LJ_LINK_LOG 0x18
 #define WD_LJ_LINK_LOG_LEN 64
-#define WD_LJ_PHY_LOG 0x4A
-#define WD_LJ_PHY_LOG_LEN 71
+#define WD_LJ_PHY_LOG 0x58
+#define WD_LJ_PHY_LOG_LEN 57
 #define WD_LJ_HARDWARE_ST 0x91
 #define WD_LJ_HARDWARE_ST_LEN 13
 
@@ -247,7 +250,10 @@ int32_t SystemBus_Init(SYSBUS **instPtr, SYSBUS_CONFIG *config)
 	(*instPtr)->txQueue = NULL;
 	(*instPtr)->uartInst = NULL;
 	memcpy(&((*instPtr)->config), config, sizeof(SYSBUS_CONFIG));
-	memset(&((*instPtr)->sysLog), 0x00, sizeof(SYSLOG));
+	memset(&((*instPtr)->sysbusLog), 0x00, sizeof(SYSBUSLOG));
+	memset(&((*instPtr)->linkLog), 0x00, sizeof(LINKLOG));
+	memset(&((*instPtr)->phyLog), 0x00, sizeof(PHYLOG));
+	memset(&((*instPtr)->hwState), 0x00, sizeof(HWSTATE));
 	uartConfig.baseAddr = config->baseAddr;
 	Status = SysbusUart_Init(&((*instPtr)->uartInst), &uartConfig);
 	if (Status != SUCCESS)
@@ -304,11 +310,12 @@ int32_t SystemBus_HandleCmd(SYSBUS *instPtr)
 		DBG_WARNING("SystemBus::Production code mismatch!\n");
 		return EIGNORE;
 	}
+
 	switch (data[WD_CMD])
 	{
 	case CMD_SELF_TEST:
 	{
-		HWSTATE *hwStatsPtr = &(instPtr->sysLog.hwState);
+		HWSTATE *hwStatsPtr = &(instPtr->hwState);
 		sysbusRsp = malloc(sizeof(SYSBUS_UART_FRAME));
 		if (sysbusRsp == NULL) {
 			DBG_ERROR("Failed to allocate memory for SELF TEST Response!\n");
@@ -329,7 +336,7 @@ int32_t SystemBus_HandleCmd(SYSBUS *instPtr)
 			sysbusRsp->data[WD_ST_RET] = (hwStatsPtr->isSpOk && hwStatsPtr->isAntOk) ? ST_RET_OK : ST_RET_ERROR;
 		}
 		// apply status and omit 2 bytes of overhead.
-		memcpy(sysbusRsp->data + WD_SP_PS_VOLT, &(hwStatsPtr->spPsVolt), ST_RET_INFO_LEN);
+		memcpy(sysbusRsp->data + WD_SP_FPGA_VOLT, &(hwStatsPtr->spFpgaVolt), ST_RET_INFO_LEN);
 
 		if (CircQueuePush(instPtr->txQueue, (void *)sysbusRsp) == false)
 		{
@@ -449,6 +456,8 @@ int32_t SystemBus_HandleCmd(SYSBUS *instPtr)
 		}
 
 		Linklayer_Start(linkInstPtr);
+		instPtr->sysbusLog.lastConfig[0] = data[WD_MODE_CMD];
+		instPtr->sysbusLog.lastConfig[1] = data[WD_EN_CMD];
 		Status = SUCCESS;
 		break;
 	}
@@ -462,11 +471,13 @@ int32_t SystemBus_HandleCmd(SYSBUS *instPtr)
 	case CMD_FLJ_SEND:
 	{
 		SysMonitor_UpdateSendPayload(data + FLJ_DATA_OFFSET, PAYLOAD_LEN_FLJ_TX); // omit control info
+		instPtr->sysbusLog.svcCnt++;
 		break;
 	}
 	case CMD_LJ_SEND:
 	{
 		SysMonitor_UpdateSendPayload(data + LJ_DATA_OFFSET, PAYLOAD_LEN_LJ_TX); // omit control info
+		instPtr->sysbusLog.svcCnt++;
 		break;
 	}
 	case CMD_FLJ_POLL:
@@ -502,6 +513,7 @@ int32_t SystemBus_HandleCmd(SYSBUS *instPtr)
 			Status = EQUEUE;
 			break;
 		}
+		instPtr->sysbusLog.pollCnt++;
 		Status = SUCCESS;
 		break;
 	}
@@ -538,12 +550,12 @@ int32_t SystemBus_HandleCmd(SYSBUS *instPtr)
 			Status = EQUEUE;
 			break;
 		}
+		instPtr->sysbusLog.pollCnt++;
 		Status = SUCCESS;
 		break;
 	}
 	case CMD_FLJ_RM_TEST:
 	{
-		SYSLOG *sysLogPtr = &(instPtr->sysLog);
 		if (data[WD_FLJ_RM_TEST] != FLJ_RM_TEST_CODE)
 		{
 			DBG_WARNING("SystemBus::Invalid remote test code!\n");
@@ -567,10 +579,12 @@ int32_t SystemBus_HandleCmd(SYSBUS *instPtr)
 		TimeCtrl_GetCurrentTime(linkInstPtr->config.tmcInstPtr, &tmWord);
 		time = tmWord.int_part * TIME_FRAC_MAX + tmWord.frac_part;
 		memcpy(sysbusRsp->data + WD_FLJ_TIME_STAMP, &time, WD_FLJ_TIME_STAMP_LEN);
-		SysMonitor_GetSyslog(sysLogPtr);
-		memcpy(sysbusRsp->data + WD_FLJ_LINK_LOG, &(sysLogPtr->linkLog), WD_FLJ_LINK_LOG_LEN);
-		memcpy(sysbusRsp->data + WD_FLJ_PHY_LOG, &(sysLogPtr->phyLog), WD_FLJ_PHY_LOG_LEN);
-		memcpy(sysbusRsp->data + WD_FLJ_HARDWARE_ST, &(sysLogPtr->hwState.spPsVolt), WD_FLJ_HARDWARE_ST_LEN);
+		SysMonitor_GetLinklayerLog(&(instPtr->linkLog));
+		SysMonitor_GetPhysicalLayerLog(&(instPtr->phyLog));
+		SysMonitor_GetHardwareStatus(&(instPtr->hwState));
+		memcpy(sysbusRsp->data + WD_FLJ_LINK_LOG, &(instPtr->linkLog), WD_FLJ_LINK_LOG_LEN);
+		memcpy(sysbusRsp->data + WD_FLJ_PHY_LOG, &(instPtr->phyLog), WD_FLJ_PHY_LOG_LEN);
+		memcpy(sysbusRsp->data + WD_FLJ_HARDWARE_ST, &(instPtr->hwState.spFpgaVolt), WD_FLJ_HARDWARE_ST_LEN);
 
 		if (CircQueuePush(instPtr->txQueue, (void *)sysbusRsp) == false){
 			free(sysbusRsp);
@@ -578,12 +592,12 @@ int32_t SystemBus_HandleCmd(SYSBUS *instPtr)
 			Status = EQUEUE;
 			break;
 		}
+		instPtr->sysbusLog.remoteCnt++;
 		Status = SUCCESS;
 		break;
 	}
 	case CMD_LJ_RM_TEST:
 	{
-		SYSLOG *sysLogPtr = &(instPtr->sysLog);
 		if (data[WD_LJ_RM_TEST] != LJ_RM_TEST_CODE)
 		{
 			DBG_WARNING("SystemBus::Invalid remote test code!\n");
@@ -607,10 +621,12 @@ int32_t SystemBus_HandleCmd(SYSBUS *instPtr)
 		TimeCtrl_GetCurrentTime(linkInstPtr->config.tmcInstPtr, &tmWord);
 		time = tmWord.int_part * TIME_FRAC_MAX + tmWord.frac_part;
 		memcpy(sysbusRsp->data + WD_LJ_TIME_STAMP, &time, WD_LJ_TIME_STAMP_LEN);
-		SysMonitor_GetSyslog(sysLogPtr);
-		memcpy(sysbusRsp->data + WD_LJ_LINK_LOG, &(sysLogPtr->linkLog), WD_LJ_LINK_LOG_LEN);
-		memcpy(sysbusRsp->data + WD_LJ_PHY_LOG, &(sysLogPtr->phyLog), WD_LJ_PHY_LOG_LEN);
-		memcpy(sysbusRsp->data + WD_LJ_HARDWARE_ST, &(sysLogPtr->hwState.spPsVolt), WD_LJ_HARDWARE_ST_LEN);
+		SysMonitor_GetLinklayerLog(&(instPtr->linkLog));
+		SysMonitor_GetPhysicalLayerLog(&(instPtr->phyLog));
+		SysMonitor_GetHardwareStatus(&(instPtr->hwState));
+		memcpy(sysbusRsp->data + WD_LJ_LINK_LOG, &(instPtr->linkLog), WD_LJ_LINK_LOG_LEN);
+		memcpy(sysbusRsp->data + WD_LJ_PHY_LOG, &(instPtr->phyLog), WD_LJ_PHY_LOG_LEN);
+		memcpy(sysbusRsp->data + WD_LJ_HARDWARE_ST, &(instPtr->hwState.spFpgaVolt), WD_LJ_HARDWARE_ST_LEN);
 
 		if (CircQueuePush(instPtr->txQueue, (void *)sysbusRsp) == false){
 			free(sysbusRsp);
@@ -618,6 +634,7 @@ int32_t SystemBus_HandleCmd(SYSBUS *instPtr)
 			Status = EQUEUE;
 			break;
 		}
+		instPtr->sysbusLog.remoteCnt++;
 		Status = SUCCESS;
 		break;
 	}

df_datalink_sp/src/systembus/systembus.h

@@ -36,7 +36,10 @@ typedef struct
 typedef struct
 {
     SYSBUS_CONFIG config;
-    SYSLOG sysLog;
+    SYSBUSLOG sysbusLog; // systembus log
+	LINKLOG linkLog; // Link layer log
+	PHYLOG phyLog; // Physical layer log
+	HWSTATE hwState; // Hardware status
     SYSBUS_UART *uartInst;
     CIRC_QUEUE *txQueue;
     CIRC_QUEUE *rxQueue;