/*****************************************************************************/ /** * Description: hwconfig.h * * Date: 2024-02-20 13:19 * Last Edit Time: [2024-02-20 13:19] * * Revisions: Rev 0.0 * History: * [2023-05-07]: Initial edition. * * Copyright(c) 2024 Beijing Institute of Technology. * ******************************************************************************/ /***************************** Include Files *********************************/ // Standard #include #include // Xilinx #include "xgpiops.h" #include "drivers/rf-transceiver/ad9361_reg/ad9361_reg.h" #include "drivers/rf-transceiver/ad9361/ad9361_api.h" #include "drivers/axi_core/spi_engine/spi_engine.h" // App #include "common.h" #include "error.h" #include "delay.h" #include "system_monitor.h" #include "hwconfig.h" #include "config/app_config.h" #include "dev_profile/dev_profile.h" /************************** Function Prototypes ******************************/ /*********************** Driver Instance Definitions **************************/ static struct hmc7044_dev *hmc7044_inst; static struct ad9361_reg_dev *ad9361_1_reg_inst; static struct ad9361_reg_dev *ad9361_2_reg_inst; // static struct ad9361_rf_phy *ad9361_phy; // static struct ad9361_rf_phy *ad9361_2_phy; /*****************************************************************************/ /** * @brief Hardware_Init * * @param none. * * @return None. * ******************************************************************************/ int32_t Hardware_Init(void) { int32_t Status; XGpioPs Gpio; XGpioPs_Config *ConfigPtr; ConfigPtr = XGpioPs_LookupConfig(AD9361_GPIO_DEVICE_ID); Status = XGpioPs_CfgInitialize(&Gpio, ConfigPtr, ConfigPtr->BaseAddr); if (Status != SUCCESS) { return FAILURE; } /**********************************************************/ /****************** HMC7044 Configuration *****************/ /**********************************************************/ Status = hmc7044_init(&hmc7044_inst, &hmc7044_default_init_param); if (Status != SUCCESS) { DBG_ERROR("hmc7044_init() error: %" PRId32 "\n", Status); return FAILURE; } /**********************************************************/ /***************** AD9361-1 Configuration *****************/ /**********************************************************/ XGpioPs_SetDirectionPin(&Gpio, AD9361_1_TXNRX, AD9361_GPIO_OUTPUT); XGpioPs_SetDirectionPin(&Gpio, AD9361_1_ENABLE, AD9361_GPIO_OUTPUT); XGpioPs_SetDirectionPin(&Gpio, AD9361_1_EN_AGC, AD9361_GPIO_OUTPUT); XGpioPs_SetDirectionPin(&Gpio, AD9361_1_RESET_B, AD9361_GPIO_OUTPUT); ad9361_reg_init(&ad9361_1_reg_inst, &ad9361_1_reg_default_init_param); XGpioPs_WritePin(&Gpio, AD9361_1_ENABLE, 0); ad9361_reg_config(ad9361_1_reg_inst); XGpioPs_WritePin(&Gpio, AD9361_1_ENABLE, 1); // Status = ad9361_init(&ad9361_phy, &ad9361_default_init_param); // if (Status != XST_SUCCESS){ // return XST_FAILURE; // }else{ // printf("Configurate AD9361 Completely!\n"); // } // ad9361_set_tx_fir_config(ad9361_phy, tx_fir_config); // ad9361_set_rx_fir_config(ad9361_phy, rx_fir_config); /**********************************************************/ /***************** AD9361-2 Configuration *****************/ /**********************************************************/ XGpioPs_SetDirectionPin(&Gpio, AD9361_2_TXNRX, AD9361_GPIO_OUTPUT); XGpioPs_SetDirectionPin(&Gpio, AD9361_2_ENABLE, AD9361_GPIO_OUTPUT); XGpioPs_SetDirectionPin(&Gpio, AD9361_2_EN_AGC, AD9361_GPIO_OUTPUT); XGpioPs_SetDirectionPin(&Gpio, AD9361_2_RESET_B, AD9361_GPIO_OUTPUT); ad9361_reg_init(&ad9361_2_reg_inst, &ad9361_2_reg_default_init_param); XGpioPs_WritePin(&Gpio, AD9361_2_ENABLE, 0); ad9361_reg_config(ad9361_2_reg_inst); XGpioPs_WritePin(&Gpio, AD9361_2_ENABLE, 1); // uint8_t rd_back; // Status = ad9361_reg_read(ad9361_1_reg_inst, 0x0002, &rd_back); // Status = ad9361_reg_read(ad9361_2_reg_inst, 0x0002, &rd_back); /**********************************************************/ /******* AD9361 Baseband Multichip Synchronization ********/ /**********************************************************/ XGpioPs_SetDirectionPin(&Gpio, AD9361_SYNC, AD9361_GPIO_OUTPUT); XGpioPs_SetDirectionPin(&Gpio, AD9361_RX_FIFO_RST, AD9361_GPIO_OUTPUT); // SYNC BBPLL and DIGITAL SAMPLING CLOCKS ad9361_reg_write(ad9361_1_reg_inst, 0x0001, 0x0D); // MCS RF Enable; MCS BBPLL Enable; MCS BB Enable ad9361_reg_write(ad9361_2_reg_inst, 0x0001, 0x0D); ad9361_reg_write(ad9361_1_reg_inst, 0x0047, 0x80); // MCS refclk Scale Enable ad9361_reg_write(ad9361_2_reg_inst, 0x0047, 0x80); XGpioPs_WritePin(&Gpio, AD9361_SYNC, 0); mdelay(20); XGpioPs_WritePin(&Gpio, AD9361_SYNC, 1); // Input a rising-edge pulse to the SYNC_IN pin mdelay(500); XGpioPs_WritePin(&Gpio, AD9361_SYNC, 0); mdelay(2000); ad9361_reg_write(ad9361_1_reg_inst, 0x0001, 0x0B); // MCS RF Enable; MCS Digital CLK Enable ; MCS BB Enable ad9361_reg_write(ad9361_2_reg_inst, 0x0001, 0x0B); XGpioPs_WritePin(&Gpio, AD9361_SYNC, 1); // Input another rising-edge pulse to the SYNC_IN pin mdelay(500); XGpioPs_WritePin(&Gpio, AD9361_SYNC, 0); ad9361_reg_write(ad9361_1_reg_inst, 0x0001, 0x08); // clear MCS bits ad9361_reg_write(ad9361_2_reg_inst, 0x0001, 0x08); XGpioPs_WritePin(&Gpio, AD9361_RX_FIFO_RST, 0); mdelay(20); XGpioPs_WritePin(&Gpio, AD9361_RX_FIFO_RST, 1); mdelay(20); XGpioPs_WritePin(&Gpio, AD9361_RX_FIFO_RST, 0); /**********************************************************/ /********* AD9361 Multichip Rx Phase Calibration **********/ /**********************************************************/ XGpioPs_SetDirectionPin(&Gpio, AD9361_TX_SWITCH, AD9361_GPIO_OUTPUT); XGpioPs_SetDirectionPin(&Gpio, AD9361_1_CAL_START, AD9361_GPIO_OUTPUT); XGpioPs_SetDirectionPin(&Gpio, AD9361_1_CAL_DONE, AD9361_GPIO_INPUT); XGpioPs_SetDirectionPin(&Gpio, AD9361_2_CAL_START, AD9361_GPIO_OUTPUT); XGpioPs_SetDirectionPin(&Gpio, AD9361_2_CAL_DONE, AD9361_GPIO_INPUT); // switch to lower frequency Status = Hardware_SwitchFreq(ad9361_1_reg_inst, TX_FREQ_126); XGpioPs_WritePin(&Gpio, AD9361_TX_SWITCH, 1); mdelay(20); // switch rx channel Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0004, 0x30); Status = ad9361_reg_write(ad9361_2_reg_inst, 0x0004, 0x30); // enable dual ad9361 tx channels Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0002, 0xE4); // Setup Tx Digital Filters/ Channels // switch ad9361 tx channel Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0004, 0x70); // Select Rx input pin(A,B,C)/ Tx out pin (A,B) mdelay(20); // begin to calibrate the 1st ad9361 XGpioPs_WritePin(&Gpio, AD9361_1_CAL_START, 0); XGpioPs_WritePin(&Gpio, AD9361_1_CAL_START, 1); mdelay(1); XGpioPs_WritePin(&Gpio, AD9361_1_CAL_START, 0); // read calibration status int32_t time_out_cnt = 0; do { mdelay(1); // Wait 1ms time_out_cnt++; } while (((XGpioPs_ReadPin(&Gpio, AD9361_1_CAL_DONE) == 0) && time_out_cnt <= AD9361_TIMEOUT_TH)); if (time_out_cnt == AD9361_TIMEOUT_TH) { return FAILURE; } // begin to calibrate the 2nd ad9361 XGpioPs_WritePin(&Gpio, AD9361_2_CAL_START, 1); mdelay(1); XGpioPs_WritePin(&Gpio, AD9361_2_CAL_START, 0); // read calibration status time_out_cnt = 0; do { mdelay(1); // Wait 1ms time_out_cnt++; } while (((XGpioPs_ReadPin(&Gpio, AD9361_2_CAL_DONE) == 0) && time_out_cnt <= AD9361_TIMEOUT_TH)); if (time_out_cnt == AD9361_TIMEOUT_TH) { return FAILURE; } // enable single ad9361 tx channels Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0002, 0xA4); // Setup Tx Digital Filters/ Channels // switch ad9361 tx & rx channel Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0004, 0x03); Status = ad9361_reg_write(ad9361_2_reg_inst, 0x0004, 0x03); // switch to higher frequency Status = Hardware_SwitchFreq(ad9361_1_reg_inst, TX_FREQ_4125); XGpioPs_WritePin(&Gpio, AD9361_TX_SWITCH, 0); DBG_PRINT("Done.\n"); return SUCCESS; } /*****************************************************************************/ /** * @brief Hardware_SwitchFreq * * @param devSysMonitor_UpdateHardwareStatus(newHwState); * @param freq * * @return None. * ******************************************************************************/ int32_t Hardware_SwitchFreq(struct ad9361_reg_dev *dev, ad9361TxFreq freq) { int32_t status = 0; uint8_t value = 0; int32_t time_out_cnt = 0; switch (freq) { case TX_FREQ_125: { //************************************************************ // Setup Tx Frequency-Dependent Syntheisizer Registers //************************************************************ status = ad9361_reg_write(dev, 0x027A, 0x4A); // Set VCO Output level[3:0] status = ad9361_reg_write(dev, 0x0279, 0xC1); // Set Init ALC Value[3:0] and VCO Varactor[3:0] status = ad9361_reg_write(dev, 0x0282, 0x0E); // Set VCO Bias Tcf[1:0] and VCO Bias Ref[2:0] status = ad9361_reg_write(dev, 0x0278, 0x78); // Set VCO Cal Offset[3:0] status = ad9361_reg_write(dev, 0x0285, 0x00); // Set VCO Cal Ref Tcf[2:0] status = ad9361_reg_write(dev, 0x0291, 0x0B); // Set VCO Varactor Reference[3:0] status = ad9361_reg_write(dev, 0x0290, 0x70); // Set VCO Varactor Ref Tcf[2:0] and VCO Varactor Offset[3:0] status = ad9361_reg_write(dev, 0x027B, 0x94); // Set Synth Loop Filter charge pump current (Icp) status = ad9361_reg_write(dev, 0x027E, 0xF4); // Set Synth Loop Filter C2 and C1 status = ad9361_reg_write(dev, 0x027F, 0xDF); // Set Synth Loop Filter R1 and C3 status = ad9361_reg_write(dev, 0x0280, 0x0A); // Set Synth Loop Filter R3 //************************************************************ // Write Tx Frequency Words //************************************************************ status = ad9361_reg_write(dev, 0x0273, 0x00); // Write Tx Synth Fractional Freq Word[7:0] status = ad9361_reg_write(dev, 0x0274, 0x00); // Write Tx Synth Fractional Freq Word[15:8] status = ad9361_reg_write(dev, 0x0275, 0x00); // Write Tx Synth Fractional Freq Word[22:16] status = ad9361_reg_write(dev, 0x0272, 0x00); // Write Tx Synth Integer Freq Word[10:8] status = ad9361_reg_write(dev, 0x0271, 0xA0); // Write Tx Synth Integer Freq Word[7:0] (starts VCO cal) status = ad9361_reg_write(dev, 0x0005, 0x57); // Set LO divider setting //************************************************************ // Tx Quadrature Calibration Settings //************************************************************ status = ad9361_reg_write(dev, 0x00A0, 0x75); // Set TxQuadcal NCO frequency status = ad9361_reg_write(dev, 0x00A3, 0xC0); // Set TxQuadcal NCO frequency (Only update bits [7:6]) status = ad9361_reg_write(dev, 0x00A1, 0x7B); // Tx Quad Cal Configuration, Phase and Gain Cal Enable status = ad9361_reg_write(dev, 0x00A9, 0xFF); // Set Tx Quad Cal Count status = ad9361_reg_write(dev, 0x00A2, 0x7F); // Set Tx Quad Cal Kexp status = ad9361_reg_write(dev, 0x00A5, 0x01); // Set Tx Quad Cal Magnitude Threshhold status = ad9361_reg_write(dev, 0x00A6, 0x01); // Set Tx Quad Cal Magnitude Threshhold status = ad9361_reg_write(dev, 0x00AA, 0x22); // Set Tx Quad Cal Gain Table index status = ad9361_reg_write(dev, 0x00A4, 0xF0); // Set Tx Quad Cal Settle Count status = ad9361_reg_write(dev, 0x00AE, 0x00); // Set Tx Quad Cal LPF Gain index incase Split table mode used status = ad9361_reg_write(dev, 0x0169, 0xC0); // Disable Rx Quadrature Calibration before Running Tx Quadrature Calibration status = ad9361_reg_write(dev, 0x0016, 0x10); // Start Tx Quad cal break; } case TX_FREQ_126: { //************************************************************ // Setup Tx Frequency-Dependent Syntheisizer Registers //************************************************************ status = ad9361_reg_write(dev, 0x027A, 0x4A); // Set VCO Output level[3:0] status = ad9361_reg_write(dev, 0x0279, 0xC1); // Set Init ALC Value[3:0] and VCO Varactor[3:0] status = ad9361_reg_write(dev, 0x0282, 0x0E); // Set VCO Bias Tcf[1:0] and VCO Bias Ref[2:0] status = ad9361_reg_write(dev, 0x0278, 0x78); // Set VCO Cal Offset[3:0] status = ad9361_reg_write(dev, 0x0285, 0x00); // Set VCO Cal Ref Tcf[2:0] status = ad9361_reg_write(dev, 0x0291, 0x0B); // Set VCO Varactor Reference[3:0] status = ad9361_reg_write(dev, 0x0290, 0x70); // Set VCO Varactor Ref Tcf[2:0] and VCO Varactor Offset[3:0] status = ad9361_reg_write(dev, 0x027B, 0x93); // Set Synth Loop Filter charge pump current (Icp) status = ad9361_reg_write(dev, 0x027E, 0xF4); // Set Synth Loop Filter C2 and C1 status = ad9361_reg_write(dev, 0x027F, 0xDF); // Set Synth Loop Filter R1 and C3 status = ad9361_reg_write(dev, 0x0280, 0x0A); // Set Synth Loop Filter R3 //************************************************************ // Write Tx Frequency Words //************************************************************ status = ad9361_reg_write(dev, 0x0273, 0x06); // Write Tx Synth Fractional Freq Word[7:0] status = ad9361_reg_write(dev, 0x0274, 0xD7); // Write Tx Synth Fractional Freq Word[15:8] status = ad9361_reg_write(dev, 0x0275, 0x23); // Write Tx Synth Fractional Freq Word[22:16] status = ad9361_reg_write(dev, 0x0272, 0x00); // Write Tx Synth Integer Freq Word[10:8] status = ad9361_reg_write(dev, 0x0271, 0xA1); // Write Tx Synth Integer Freq Word[7:0] (starts VCO cal) status = ad9361_reg_write(dev, 0x0005, 0x57); // Set LO divider setting //************************************************************ // Tx Quadrature Calibration Settings //************************************************************ status = ad9361_reg_write(dev, 0x00A0, 0x75); // Set TxQuadcal NCO frequency status = ad9361_reg_write(dev, 0x00A3, 0xC0); // Set TxQuadcal NCO frequency (Only update bits [7:6]) status = ad9361_reg_write(dev, 0x00A1, 0x7B); // Tx Quad Cal Configuration, Phase and Gain Cal Enable status = ad9361_reg_write(dev, 0x00A9, 0xFF); // Set Tx Quad Cal Count status = ad9361_reg_write(dev, 0x00A2, 0x7F); // Set Tx Quad Cal Kexp status = ad9361_reg_write(dev, 0x00A5, 0x01); // Set Tx Quad Cal Magnitude Threshhold status = ad9361_reg_write(dev, 0x00A6, 0x01); // Set Tx Quad Cal Magnitude Threshhold status = ad9361_reg_write(dev, 0x00AA, 0x22); // Set Tx Quad Cal Gain Table index status = ad9361_reg_write(dev, 0x00A4, 0xF0); // Set Tx Quad Cal Settle Count status = ad9361_reg_write(dev, 0x00AE, 0x00); // Set Tx Quad Cal LPF Gain index incase Split table mode used status = ad9361_reg_write(dev, 0x0169, 0xC0); // Disable Rx Quadrature Calibration before Running Tx Quadrature Calibration status = ad9361_reg_write(dev, 0x0016, 0x10); // Start Tx Quad cal break; } case TX_FREQ_4125: { //************************************************************ // Setup Tx Frequency-Dependent Syntheisizer Registers //************************************************************ status = ad9361_reg_write(dev, 0x027A, 0x4A); // Set VCO Output level[3:0] status = ad9361_reg_write(dev, 0x0279, 0xC1); // Set Init ALC Value[3:0] and VCO Varactor[3:0] status = ad9361_reg_write(dev, 0x0282, 0x0E); // Set VCO Bias Tcf[1:0] and VCO Bias Ref[2:0] status = ad9361_reg_write(dev, 0x0278, 0x78); // Set VCO Cal Offset[3:0] status = ad9361_reg_write(dev, 0x0285, 0x00); // Set VCO Cal Ref Tcf[2:0] status = ad9361_reg_write(dev, 0x0291, 0x0B); // Set VCO Varactor Reference[3:0] status = ad9361_reg_write(dev, 0x0290, 0x70); // Set VCO Varactor Ref Tcf[2:0] and VCO Varactor Offset[3:0] status = ad9361_reg_write(dev, 0x027B, 0x93); // Set Synth Loop Filter charge pump current (Icp) status = ad9361_reg_write(dev, 0x027E, 0xF4); // Set Synth Loop Filter C2 and C1 status = ad9361_reg_write(dev, 0x027F, 0xDF); // Set Synth Loop Filter R1 and C3 status = ad9361_reg_write(dev, 0x0280, 0x0A); // Set Synth Loop Filter R3 //************************************************************ // Write Rx Frequency Words //************************************************************ status = ad9361_reg_write(dev, 0x0273, 0x00); // Write Tx Synth Fractional Freq Word[7:0] status = ad9361_reg_write(dev, 0x0274, 0x00); // Write Tx Synth Fractional Freq Word[15:8] status = ad9361_reg_write(dev, 0x0275, 0x00); // Write Tx Synth Fractional Freq Word[22:16] status = ad9361_reg_write(dev, 0x0272, 0x00); // Write Tx Synth Integer Freq Word[10:8] status = ad9361_reg_write(dev, 0x0271, 0xA5); // Write Tx Synth Integer Freq Word[7:0] (starts VCO cal) status = ad9361_reg_write(dev, 0x0005, 0x07); // Set LO divider setting //************************************************************ // Tx Quadrature Calibration Settings //************************************************************ status = ad9361_reg_write(dev, 0x00A0, 0x75); // Set TxQuadcal NCO frequency status = ad9361_reg_write(dev, 0x00A3, 0xC0); // Set TxQuadcal NCO frequency (Only update bits [7:6]) status = ad9361_reg_write(dev, 0x00A1, 0x7B); // Tx Quad Cal Configuration, Phase and Gain Cal Enable status = ad9361_reg_write(dev, 0x00A9, 0xFF); // Set Tx Quad Cal Count status = ad9361_reg_write(dev, 0x00A2, 0x7F); // Set Tx Quad Cal Kexp status = ad9361_reg_write(dev, 0x00A5, 0x01); // Set Tx Quad Cal Magnitude Threshhold status = ad9361_reg_write(dev, 0x00A6, 0x01); // Set Tx Quad Cal Magnitude Threshhold status = ad9361_reg_write(dev, 0x00AA, 0x28); // Set Tx Quad Cal Gain Table index status = ad9361_reg_write(dev, 0x00A4, 0xF0); // Set Tx Quad Cal Settle Count status = ad9361_reg_write(dev, 0x00AE, 0x04); // Set Tx Quad Cal LPF Gain index incase Split table mode used status = ad9361_reg_write(dev, 0x0169, 0xC0); // Disable Rx Quadrature Calibration before Running Tx Quadrature Calibration status = ad9361_reg_write(dev, 0x0016, 0x10); // Start Tx Quad cal break; } // Wait for cal to complete (Done when 0x016[4]==0) time_out_cnt = 0; do { status |= ad9361_reg_read(dev, 0x0016, &value); mdelay(1); // Wait 1ms time_out_cnt++; } while ((value & 0x10) != 0x00 && time_out_cnt <= AD9361_TIMEOUT_TH); } return status; } // @ Get AD9361 - 1 temperature (Celsius Degree) /** * Read corresponding register to get AD9361 - 1 current temperature. */ int8_t Hardware_GetAD9361Temp_1(void) { int8_t scaleTemp; ad9361_reg_write(ad9361_1_reg_inst, 0x001D, 0x01); // disable aux adc ad9361_reg_read(ad9361_1_reg_inst, 0x000E, (uint8_t*)&scaleTemp); ad9361_reg_write(ad9361_1_reg_inst, 0x001D, 0x00); // enable aux adc return (int8_t) scaleTemp/1.16; } // @ Get AD9361 - 2 temperature (Celsius Degree) /** * Read corresponding register to get AD9361 - 2 current temperature. */ int8_t Hardware_GetAD9361Temp_2(void) { int8_t scaleTemp; ad9361_reg_write(ad9361_2_reg_inst, 0x001D, 0x01); // disable aux adc ad9361_reg_read(ad9361_2_reg_inst, 0x000E, (uint8_t*)&scaleTemp); ad9361_reg_write(ad9361_2_reg_inst, 0x001D, 0x00); // enable aux adc return (int8_t) scaleTemp/1.16; } // @ Determine AD9361 lock state /** * Read corresponding register to determine AD9361(both) lock state. */ uint8_t Hardware_GetAD9361LockStatus(void) { uint8_t ret = 0; uint8_t regVal; // bbpll ad9361_reg_read(ad9361_1_reg_inst, 0x005E, ®Val); // [D7] is lock indicator ret |= ((regVal & 0x80) == 0x80) ? CLK_AD0_BBPLL_LOCK : 0; ad9361_reg_read(ad9361_2_reg_inst, 0x005E, ®Val); // [D7] is lock indicator ret |= ((regVal & 0x80) == 0x80) ? CLK_AD1_BBPLL_LOCK : 0; // rfpll ad9361_reg_read(ad9361_1_reg_inst, 0x0287, ®Val); // [D1] is lock indicator ret |= ((regVal & 0x02) == 0x02) ? CLK_AD0_RFPLL_LOCK : 0; ad9361_reg_read(ad9361_2_reg_inst, 0x0287, ®Val); // [D1] is lock indicator ret |= ((regVal & 0x02) == 0x02) ? CLK_AD1_RFPLL_LOCK : 0; return ret; } // @ Determine HMC7044 lock state /** * Read corresponding register to determine clock lock state. */ uint8_t Hardware_GetHMC7044LockStatus(void) { uint8_t ret = 0; uint8_t regVal; // pll1 hmc7044_read(hmc7044_inst, 0x007C, ®Val); // [D5] is lock indicator ret |= ((regVal & 0xE0) != 0x00) ? CLK_SP_PLL0_LOCK : 0; // pll2 hmc7044_read(hmc7044_inst, 0x007D, ®Val); // [D0] is lock indicator ret |= ((regVal & 0x01) == 0x01) ? CLK_SP_PLL1_LOCK : 0; return ret; }