526 lines
14 KiB
C
526 lines
14 KiB
C
/*****************************************************************************/
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/**
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* Description: main.c
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*
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* Date: 2021-11-13 13:19
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* Last Editors: Fan Hao
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* Last Edit Time: [2022-03-28 20:32]
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*
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* Revisions: Rev 0.0
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* History:
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* [2021-11-13]: Initial edition.
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* [2022-03-28]: Add bit error test mode.
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*
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* Copyright(c) 2021 Beijing Institute of Technology.
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* Lab of Communication and Networking
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*
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******************************************************************************/
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/***************************** Include Files *********************************/
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// Standard
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#include <stdlib.h>
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#include <stdint.h>
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#include <stdbool.h>
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// Xilinx
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#include "sleep.h"
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#include "xil_cache.h"
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#include "xscugic.h"
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#include "xscutimer.h"
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#include "xgpiops.h"
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#include "drivers/platform/xilinx_irq.h"
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#include "drivers/platform/xilinx_timer.h"
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// App
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#include "common.h"
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#include "error.h"
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#include "timer.h"
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#include "config/app_config.h"
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#include "dev_profile/dev_profile.h"
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#include "mpc/mpc.h"
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#include "networking/phy_layer/phy_layer.h"
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#include "networking/link_layer/link_layer.h"
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// RF-Driver
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#include "hardware/headless.h"
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#include "hardware/platform_drivers.h"
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/************************** Function Prototypes ******************************/
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int32_t SetupInterruptSystem(struct irq_ctrl_desc *descPtr);
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void Phy_IntrHandler(void *context);
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void PeriodicPull_Handler(void *callBackRef);
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void ScuTimer_IntrHandler(void *context);
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void Mpc_RxIntrHandler(void *context);
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void Mpc_TxIntrHandler(void *context);
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/************************** Constant Definitions *****************************/
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struct callback_desc phy_callback_desc =
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{
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.callback = Phy_IntrHandler,
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.ctx = NULL
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};
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struct callback_desc periodicpull_callback_desc =
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{
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.callback = PeriodicPull_Handler,
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.ctx = NULL
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};
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struct callback_desc mpc_rx_callback_desc =
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{
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.callback = Mpc_RxIntrHandler,
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.ctx = NULL
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};
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struct callback_desc mpc_tx_callback_desc =
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{
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.callback = Mpc_TxIntrHandler,
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.ctx = NULL
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};
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struct callback_desc scutm_callback_desc =
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{
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.callback = ScuTimer_IntrHandler,
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.ctx = NULL
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};
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L2_CONFIG linkConfig =
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{
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.myType = L2_NODE_HEAD,
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.clustId = 1,
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.myId = 1,
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.headId = 1,
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.bkpHeadId = 0,
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.netScale = 2,
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.phyInstPtr = NULL, // physical layer reference
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.tmcInstPtr = NULL
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};
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// L2_CONFIG linkConfig = {
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// .myType = L2_NODE_MEMBER,
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// .clustId = 1,
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// .myId = 2,
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// .headId = 1,
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// .bkpHeadId = 0,
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// .netScale = 2,
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// .phyInstPtr = NULL, // physical layer reference
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// .tmcInstPtr = NULL
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// };
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static PHY_CONFIG phyConfig =
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{
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.devId = 0,
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.baseAddr = PHY_BASEADDR,
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.antBramId = PHY_ANTCONFIG_BRAM_DEVICE_ID,
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.antInfoBramId = -1,
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.txBramId = PHY_TXBUFF_BRAM_DEVICE_ID,
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.rxBramId = PHY_RXBUFF_BRAM_DEVICE_ID,
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.hwXadcId = PHY_HW_XADC_DEVICE_ID,
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.get_clk_state = NULL,
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.get_ad_lock_state = NULL,
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.get_ad0_temp = NULL,
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.get_ad1_temp = NULL
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};
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TMC_CONFIG tmcConfig =
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{
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.baseAddr = TIME_CONTROLLER_BASEADDR,
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.reset = 10
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};
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static MPC_CONFIG mpcConfig = {
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.bramId = MPC_BRAM_ID,
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.gpioId = MPC_GPIO_ID,
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.txQueueMax = 16,
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.rxQueueMax = 16
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};
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/************************** Function Prototypes ******************************/
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static struct irq_ctrl_desc *intcDescPtr; // General interrupt controller descriptor
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static struct timer_desc *logTmPtr;
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static MPC *mpcDescPtr;
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static PHY_INST *phyInstPtr;
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static TMC_INST *tmcInstPtr = NULL;
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L2_INST *linkInstPtr;
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/****************************************************************************/
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/**
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* This function is responsible for initializing the SCUGIC instance, looking
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* for the device configuration based on the unique device ID, initializing a
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* SCUGIC instance, and initialize the interrupt at IRQ_F2P[0:0]
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*
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* @param intcDesc A pointer to INTC descriptor
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*
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* @return SUCCESS if initialize successful.
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* FAILURE if initialization failed.
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*
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*****************************************************************************/
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int32_t SetupInterruptSystem(struct irq_ctrl_desc *descPtr)
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{
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int32_t Status;
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struct xil_irq_desc *xil_dev;
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Status = irq_ctrl_init(&descPtr, &intc_init_param);
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if (Status != SUCCESS)
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{
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DBG_ERROR("Intc Init FAILED, ErrorCode: %" PRId32 ".\n", Status);
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return Status;
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}
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xil_dev = (struct xil_irq_desc *)(descPtr->extra);
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// Clear any pending interrupt flags
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uint32_t intrState = XScuGic_CPUReadReg((XScuGic *)(xil_dev->instance), XSCUGIC_INT_ACK_OFFSET);
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XScuGic_CPUWriteReg((XScuGic *)(xil_dev->instance), XSCUGIC_EOI_OFFSET, intrState);
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/* Initialize physical layer interrupt. */
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Status = irq_trigger_level_set(descPtr, PHY_INTR_ID, IRQ_EDGE_RISING);
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if (Status != SUCCESS)
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{
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DBG_ERROR("PHY_INTR trigger level set FAILED, ErrorCode: %" PRId32 ".\n", Status);
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return Status;
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}
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// Set highest interrupt priority
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Status = irq_set_priority(descPtr, PHY_INTR_ID, 0x08);
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if (Status != SUCCESS)
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{
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DBG_ERROR("PHY_INTR priority level set FAILED, ErrorCode: %" PRId32 ".\n", Status);
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return Status;
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}
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// Connect the interrupt service routine isr1 to the interrupt controller
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Status = irq_register_callback(descPtr, PHY_INTR_ID, &phy_callback_desc);
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if (Status != SUCCESS)
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{
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DBG_ERROR("PHY_INTR register callback FAILED, ErrorCode: %" PRId32 ".\n", Status);
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return Status;
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}
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/* Initialize linklayer layer interrupt. */
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Status = irq_trigger_level_set(descPtr, PERIODIC_5MS_INTR_ID, IRQ_EDGE_RISING);
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if (Status != SUCCESS)
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{
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DBG_ERROR("PERIODIC_5MS_INTR_ID trigger level set FAILED, ErrorCode: %" PRId32 ".\n", Status);
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return Status;
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}
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// Set highest interrupt priority
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Status = irq_set_priority(descPtr, PERIODIC_5MS_INTR_ID, 0x00);
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if (Status != SUCCESS)
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{
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DBG_ERROR("PERIODIC_5MS_INTR_ID priority level set FAILED, ErrorCode: %" PRId32 ".\n", Status);
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return Status;
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}
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// Connect the interrupt service routine isr1 to the interrupt controller
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Status = irq_register_callback(descPtr, PERIODIC_5MS_INTR_ID, &periodicpull_callback_desc);
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if (Status != SUCCESS)
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{
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DBG_ERROR("PHY_INTR register callback FAILED, ErrorCode: %" PRId32 ".\n", Status);
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return Status;
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}
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/* Initialize system bus interrupt. */
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Status = irq_trigger_level_set(descPtr, MPC_TX_INTR_ID, IRQ_EDGE_RISING);
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if (Status != SUCCESS)
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{
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DBG_ERROR("PHY_INTR trigger level set FAILED, ErrorCode: %" PRId32 ".\n", Status);
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return Status;
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}
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// Set interrupt priority
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Status = irq_set_priority(descPtr, MPC_TX_INTR_ID, 0x10);
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if (Status != SUCCESS)
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{
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DBG_ERROR("PHY_INTR priority level set FAILED, ErrorCode: %" PRId32 ".\n", Status);
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return Status;
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}
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// Connect the interrupt service routine isr1 to the interrupt controller
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Status = irq_register_callback(descPtr, MPC_TX_INTR_ID, &mpc_tx_callback_desc);
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if (Status != SUCCESS)
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{
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DBG_ERROR("PHY_INTR register callback FAILED, ErrorCode: %" PRId32 ".\n", Status);
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return Status;
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}
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Status = irq_trigger_level_set(descPtr, MPC_RX_INTR_ID, IRQ_EDGE_RISING);
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if (Status != SUCCESS)
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{
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DBG_ERROR("PHY_INTR trigger level set FAILED, ErrorCode: %" PRId32 ".\n", Status);
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return Status;
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}
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// Set interrupt priority
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Status = irq_set_priority(descPtr, MPC_RX_INTR_ID, 0x18);
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if (Status != SUCCESS)
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{
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DBG_ERROR("PHY_INTR priority level set FAILED, ErrorCode: %" PRId32 ".\n", Status);
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return Status;
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}
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// Connect the interrupt service routine isr1 to the interrupt controller
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Status = irq_register_callback(descPtr, MPC_RX_INTR_ID, &mpc_rx_callback_desc);
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if (Status != SUCCESS)
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{
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DBG_ERROR("PHY_INTR register callback FAILED, ErrorCode: %" PRId32 ".\n", Status);
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return Status;
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}
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/* Initialize Scu timer interrupt. */
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// Connect the interrupt service routine isr1 to the interrupt controller
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Status = irq_register_callback(descPtr, SCUTIMER_INTR_ID, &scutm_callback_desc);
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if (Status != SUCCESS)
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{
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DBG_ERROR("PHY_INTR register callback FAILED, ErrorCode: %" PRId32 ".\n", Status);
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return Status;
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}
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// Enable interrupts
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irq_enable(descPtr, PHY_INTR_ID);
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irq_enable(descPtr, PERIODIC_5MS_INTR_ID);
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irq_enable(descPtr, MPC_RX_INTR_ID);
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irq_enable(descPtr, MPC_TX_INTR_ID);
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irq_enable(descPtr, SCUTIMER_INTR_ID);
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// Enable Exceptions
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Status = irq_global_enable(descPtr);
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if (Status != SUCCESS)
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{
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DBG_ERROR("IRQ global enable FAILED, ErrorCode: %" PRId32 ".\n", Status);
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return Status;
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}
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return SUCCESS;
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} // SetupInterruptSystem
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/****************************************************************************/
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/**
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* This function is a interrupt service routine for IRQ_F2P[1:1], IRQ_F2P[1:1]
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* tells CPU that the data in OCM is ready!
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*
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* @param context
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*
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* @return None.
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*
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*****************************************************************************/
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void Phy_IntrHandler(void *context)
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{
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Phy_UpdateState(phyInstPtr);
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} // PhyIntr_Handler
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/****************************************************************************/
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/**
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* Handler of periodic 5ms interrupt
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*
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* @param callBackRef is the linklayer instance pointer.
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*
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* @return None.
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*
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*****************************************************************************/
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void PeriodicPull_Handler(void *callBackRef)
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{
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int32_t Status;
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Status = Linklayer_Proc(linkInstPtr);
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if (Status != SUCCESS)
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{
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DBG_ERROR("Link layer runs failed, with error code: %" PRId32 "\n", Status);
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_nop_();
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}
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} // PeriodicPull_Handler
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/*****************************************************************************/
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/**
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* @brief Handler of System Bus RX done interrupt.
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*
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* @param context
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*
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* @return None.
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*
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******************************************************************************/
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void Mpc_RxIntrHandler(void *context)
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{
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int32_t Status;
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Status = Mpc_RxIrqHandler(mpcDescPtr);
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if (Status != SUCCESS)
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{
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DBG_ERROR("Mpc_RxIrqHandler exit with error code %" PRId32 ",\n", Status);
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}
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}
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/*****************************************************************************/
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/**
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* @brief Handler of System Bus TX done interrupt.
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*
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* @param context
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*
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* @return None.
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*
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******************************************************************************/
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void Mpc_TxIntrHandler(void *context)
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{
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int32_t Status;
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Status = Mpc_TxIrqHandler(mpcDescPtr);
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if (Status != SUCCESS)
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{
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DBG_ERROR("Mpc_TxIrqHandler exit with error code %" PRId32 ",\n", Status);
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}
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}
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/*****************************************************************************/
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/**
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* @brief Handler of ScuTimer interrupt.
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*
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* @param context
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*
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* @return None.
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*
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******************************************************************************/
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void ScuTimer_IntrHandler(void *context)
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{
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struct xil_timer_desc *xdesc;
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xdesc = (struct xil_timer_desc *)(logTmPtr->extra);
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if (XScuTimer_IsExpired((XScuTimer *)xdesc->instance))
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{
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// Refresh log
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Phy_RefreshHwSate(phyInstPtr);
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if (Mpc_IsEnable(mpcDescPtr))
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{
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if (Mpc_PendRemoteTest(mpcDescPtr) != SUCCESS)
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{
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DBG_ERROR("Failed to apply remote test.\n");
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}
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}
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XScuTimer_ClearInterruptStatus((XScuTimer *)xdesc->instance);
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}
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else
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{
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DBG_WARNING("UNEXPECTED CALL of ScuTimer_IntrHandler\n");
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}
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}
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/*****************************************************************************/
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/**
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* @brief Main function, initialize all the device needed, initialize
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* interrupt system, halt in while(1) wait for event interrupt.
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*
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* @param None.
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*
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* @return
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*
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******************************************************************************/
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int main(void)
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{
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int32_t Status;
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DBG_PRINT("Application Version: %2d.%2d.%4d.\n", _APP_VER_MAIN, _APP_VER_MINOR, _APP_VER_PATCH);
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/* System Monitor Initialize */
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Status = SysMonitor_Init();
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if (Status == SUCCESS)
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{
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DBG_PRINT("System monitor Init SUCCESS! \n");
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}
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else
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{
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DBG_PRINT("System monitor Init FAILED! \n");
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return Status;
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}
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Status = HARDWARE_initialize();
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if (Status == SUCCESS)
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{
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DBG_PRINT("Hardware Init SUCCESS! \n");
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}
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else
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{
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DBG_PRINT("Hardware Init FAILED! \n");
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return Status;
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}
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// Init time controller
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Status = TimeCtrl_Init(&tmcInstPtr, &tmcConfig);
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if (Status == SUCCESS)
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{
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DBG_PRINT("TmcCtrl Init SUCCESS! \n");
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}
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else
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{
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DBG_PRINT("TmcCtrl Init FAILED! \n");
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return Status;
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}
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/* Physical Layer Initialize */
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Status = Phy_InstInit(&phyInstPtr, &phyConfig);
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if (Status == SUCCESS)
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{
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DBG_PRINT("Physical layer Init SUCCESS! \n");
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}
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else
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{
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DBG_PRINT("Physical layer FAILED! \n");
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return Status;
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}
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/* Link Layer Initialize */
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linkConfig.phyInstPtr = phyInstPtr;
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linkConfig.tmcInstPtr = tmcInstPtr;
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Status = Linklayer_Init(&linkInstPtr, &linkConfig);
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if (Status == SUCCESS)
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{
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DBG_PRINT("LinkLayer Init SUCCESS! \n");
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}
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else
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{
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DBG_PRINT("Linklayer Init FAILED! \n");
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return Status;
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}
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/* System Bus Initialize */
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Status = Mpc_Init(&mpcDescPtr, &mpcConfig);
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if (Status != SUCCESS)
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{
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DBG_ERROR("MPC init FAILED, with error code: %" PRId32 "\n", Status);
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return Status;
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}
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/* System Monitor log timer Initialize */
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Status = timer_init(&logTmPtr, &scutimer_init_param);
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if (Status != SUCCESS)
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{
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DBG_ERROR("SCU Timer init FAILED, with error code: %" PRId32 "\n", Status);
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return Status;
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}
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/* interrupts Initialize */
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Status = SetupInterruptSystem(intcDescPtr);
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if (Status == SUCCESS)
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{
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DBG_INFO("Interrupt system setup SUCCESS!\n");
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}
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else
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{
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DBG_ERROR("Interrupt system setup FAILED, ErrorCode: %" PRId32 ".\n", Status);
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return Status;
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}
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// Start System Monitor logging.
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timer_start(logTmPtr);
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DBG_PRINT("Physical started...\n");
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Phy_Start(phyInstPtr);
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while (true)
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{
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// System bus handler
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if (Mpc_IsReqPending(mpcDescPtr))
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{
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Status = Mpc_HandleCmd(mpcDescPtr);
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if (Status != SUCCESS)
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{
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DBG_ERROR("Mpc_HandleCmd exit with ErrorCode: %" PRId32 ".\n", Status);
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}
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}
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if (Mpc_IsRsqPending(mpcDescPtr) && (!Mpc_IsTxBusy(mpcDescPtr)))
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{
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Status = Mpc_MakeResp(mpcDescPtr);
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if (Status != SUCCESS)
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{
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DBG_ERROR("Mpc_HandleCmd exit with ErrorCode: %" PRId32 ".\n", Status);
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}
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}
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}
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} // main
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