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feat: PL发端改为演示验证多符号速率QPSK,PS增加DEMO工程附带的CPP驱动程序

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josh
2024-11-02 12:08:58 +08:00
parent 986109c2f7
commit 16bac8585d
146 changed files with 961054 additions and 168083 deletions
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cx9261a_demo_cmos_20240513/CX9261A_ZC706.xsa
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cx9261a_demo_cmos_20240513/project_fix_dac.runs/impl_1/CX9261A_ZC706.bit
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cx9261a_demo_cmos_20240513/project_fix_dac.runs/impl_1/CX9261A_ZC706.ltx
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cx9261a_demo_cmos_20240513/project_fix_dac.runs/impl_1/debug_nets.ltx
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cx9261a_demo_cmos_20240513/project_fix_dac.srcs/constrs_1/new/cx9261a_zc706.xdc
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@@ -140,4 +140,4 @@ set_property LOC IDELAYCTRL_X0Y2 [get_cells u_mclk_delay/IDELAYCTRL_RX12]
set_property LOC IDELAYCTRL_X0Y4 [get_cells u_mclk_delay/IDELAYCTRL_RX3]
################################################################################################
set_clock_groups -asynchronous -group [get_clocks RXFB_MCLK_IN] -group [get_clocks RX1_MCLK_IN_N] -group [get_clocks RX2_MCLK_IN_P] -group [get_clocks clk_fpga_0]
set_clock_groups -asynchronous -group [get_clocks {system_top_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]}] -group [get_clocks RXFB_MCLK_IN] -group [get_clocks RX1_MCLK_IN_N] -group [get_clocks RX2_MCLK_IN_P]
cx9261a_demo_cmos_20240513/project_fix_dac.srcs/sources_1/imports/new/tx_qpsk_v1.v
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
// _ _ ____
// | | ___ ___| |__ / ___| __ _ ___
// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
// \___/ \___/|___/_| |_| \____|\__,_|\___/
//
// Create Date: 2022/03/23 20:17:56
// Last Modified Date: 2023/03/10 15:41
// Design Name:
// Module Name: tx_qpsk
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// 20230228-1541 - 修改不扫频、无基带频偏时 [baseband_i/q] 的数据输出，原来从
// 乘法器引出，会导致频率为 0 时输出数据错误，现在直接从基带数据引出。
// 20230310-1542 - 增加输入参数，发送数据更改为直接由参数输入，发送方波改为 8
// 倍过采样，发送双音信号中 1MHz 信号的频率控制字可以根据参数中的时钟频率计
// 算得出。
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module tx_qpsk_v1
#(
parameter DATA_WIDTH = 12, // need to be <= 16
parameter BIT_DATA = 128'b00000011000010100011110010001011001110101001111101000011100010010011011010110111101100011010010111011100110010101011111110000001, // inverse pseudorandom bit sequence, [0,flip(PRSB7)]
parameter BIT_DATA_LEN = 128,
parameter SQUARE_INTERP = 1,
parameter CLK_FREQ = 245760000 // in Hertz
)
(
input clk ,
input rst ,
output [DATA_WIDTH-1:0] tx_data_i ,
output [DATA_WIDTH-1:0] tx_data_q ,
// debug ports
input [ 1:0] waveform_sel ,
input sweep_on ,
input [31:0] freq_set ,
input [ 1:0] iq_sel ,
input [ 3:0] bb_rshift
);
localparam RCOS_INTERP = 1;
localparam INTERP = (RCOS_INTERP > SQUARE_INTERP) ? RCOS_INTERP : SQUARE_INTERP;
localparam FREQ_WORD_1M = 64'd2**64'd32*64'd1000000/CLK_FREQ;
////////////////////////////////////////////////////////////////////////////////
///////////////////////////////// Data Counter /////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// symbol & interpolation counter
reg [$clog2(INTERP*BIT_DATA_LEN)-1 : 0] cnt = 'b0;
always @(posedge clk) begin
if (rst) begin
cnt <= 'b0;
end
else begin
cnt <= (cnt == INTERP*BIT_DATA_LEN - 1) ? 'b0 : cnt + 16'b1;
end
end
////////////////////////////////////////////////////////////////////////////////
////////////////////// Root-Rasied Cosine Shaping Filter ///////////////////////
////////////////////////////////////////////////////////////////////////////////
// address
reg [$clog2(BIT_DATA_LEN)-1 : 0] hrc_data_addr_i = 'b0;
reg [$clog2(BIT_DATA_LEN)-1 : 0] hrc_data_addr_q = 'b1;
always @(posedge clk) begin
if (rst) begin
hrc_data_addr_i <= 'b0;
hrc_data_addr_q <= 'b1;
end
else begin
hrc_data_addr_i <= {cnt[$clog2(RCOS_INTERP) +: ($clog2(BIT_DATA_LEN)-1)],1'b0};
hrc_data_addr_q <= {cnt[$clog2(RCOS_INTERP) +: ($clog2(BIT_DATA_LEN)-1)],1'b1};
end
end
// bit data
reg hrc_data_i = 'b0;
reg hrc_data_q = 'b0;
always @(posedge clk) begin
if (rst) begin
hrc_data_i <= 'b0;
hrc_data_q <= 'b0;
end
else begin
hrc_data_i <= BIT_DATA[hrc_data_addr_i];
hrc_data_q <= BIT_DATA[hrc_data_addr_q];
end
end
// polarization
wire [ 7:0] hrc_data_polar_i;
wire [ 7:0] hrc_data_polar_q;
assign hrc_data_polar_i = {{7{hrc_data_i}},1'b1};
assign hrc_data_polar_q = {{7{hrc_data_q}},1'b1};
/* // root raised cosine shaping-filter
wire [23:0] hrc_wave_i;
wire [23:0] hrc_wave_q;
hrc_64_12_025 u_hrc_i (
.aclk (clk ), // input wire aclk
.s_axis_data_tvalid (~rst ), // input wire s_axis_data_tvalid
.s_axis_data_tready ( ), // output wire s_axis_data_tready
.s_axis_data_tdata (hrc_data_polar_i ), // input wire [7 : 0] s_axis_data_tdata
.m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid
.m_axis_data_tdata (hrc_wave_i ) // output wire [23 : 0] m_axis_data_tdata
);
hrc_64_12_025 u_hrc_q (
.aclk (clk ), // input wire aclk
.s_axis_data_tvalid (~rst ), // input wire s_axis_data_tvalid
.s_axis_data_tready ( ), // output wire s_axis_data_tready
.s_axis_data_tdata (hrc_data_polar_q ), // input wire [7 : 0] s_axis_data_tdata
.m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid
.m_axis_data_tdata (hrc_wave_q ) // output wire [23 : 0] m_axis_data_tdata
); */
wire [23:0] hrc_wave_i_48;
wire [23:0] hrc_wave_q_48;
hrc_4_12_03 i_hrc_4_12_03 (
.aclk (clk ), // input wire aclk
.s_axis_data_tvalid (~rst ), // input wire s_axis_data_tvalid
.s_axis_data_tready ( ), // output wire s_axis_data_tready
.s_axis_data_tdata (hrc_data_polar_i ), // input wire [7 : 0] s_axis_data_tdata
.m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid
.m_axis_data_tdata (hrc_wave_i_48 ) // output wire [23 : 0] m_axis_data_tdata
);
hrc_4_12_03 q_hrc_4_12_03 (
.aclk (clk ), // input wire aclk
.s_axis_data_tvalid (~rst ), // input wire s_axis_data_tvalid
.s_axis_data_tready ( ), // output wire s_axis_data_tready
.s_axis_data_tdata (hrc_data_polar_q ), // input wire [7 : 0] s_axis_data_tdata
.m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid
.m_axis_data_tdata (hrc_wave_q_48 ) // output wire [23 : 0] m_axis_data_tdata
);
wire [23:0] hrc_wave_i_12;
wire [23:0] hrc_wave_q_12;
hrc_16_12_03 i_hrc_16_12_03 (
.aclk (clk ), // input wire aclk
.s_axis_data_tvalid (~rst ), // input wire s_axis_data_tvalid
.s_axis_data_tready ( ), // output wire s_axis_data_tready
.s_axis_data_tdata (hrc_data_polar_i ), // input wire [7 : 0] s_axis_data_tdata
.m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid
.m_axis_data_tdata (hrc_wave_i_12 ) // output wire [23 : 0] m_axis_data_tdata
);
hrc_16_12_03 q_hrc_16_12_03 (
.aclk (clk ), // input wire aclk
.s_axis_data_tvalid (~rst ), // input wire s_axis_data_tvalid
.s_axis_data_tready ( ), // output wire s_axis_data_tready
.s_axis_data_tdata (hrc_data_polar_q ), // input wire [7 : 0] s_axis_data_tdata
.m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid
.m_axis_data_tdata (hrc_wave_q_12 ) // output wire [23 : 0] m_axis_data_tdata
);
wire [23:0] hrc_wave_i_1p5;
wire [23:0] hrc_wave_q_1p5;
hrc_128_12_03 i_hrc_128_12_03 (
.aclk (clk ), // input wire aclk
.s_axis_data_tvalid (~rst ), // input wire s_axis_data_tvalid
.s_axis_data_tready ( ), // output wire s_axis_data_tready
.s_axis_data_tdata (hrc_data_polar_i ), // input wire [7 : 0] s_axis_data_tdata
.m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid
.m_axis_data_tdata (hrc_wave_i_1p5 ) // output wire [23 : 0] m_axis_data_tdata
);
hrc_128_12_03 q_hrc_128_12_03 (
.aclk (clk ), // input wire aclk
.s_axis_data_tvalid (~rst ), // input wire s_axis_data_tvalid
.s_axis_data_tready ( ), // output wire s_axis_data_tready
.s_axis_data_tdata (hrc_data_polar_q ), // input wire [7 : 0] s_axis_data_tdata
.m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid
.m_axis_data_tdata (hrc_wave_q_1p5 ) // output wire [23 : 0] m_axis_data_tdata
);
////////////////////////////////////////////////////////////////////////////////
///////////////////// Waveform Selection & Hopping Control /////////////////////
////////////////////////////////////////////////////////////////////////////////
// baseband signal select
reg [17:0] baseband_sel_i = 'b0;
reg [17:0] baseband_sel_q = 'b0;
always @(posedge clk) begin
if (rst) begin
baseband_sel_i <= 'b0;
baseband_sel_q <= 'b0;
end
else begin
case (waveform_sel[1:0])
2'd0: begin
baseband_sel_i <= {hrc_wave_i_48[16:0],1'b0};
baseband_sel_q <= {hrc_wave_q_48[16:0],1'b0};
end
2'd1: begin
baseband_sel_i <= {hrc_wave_i_12[16:0],1'b0};
baseband_sel_q <= {hrc_wave_q_12[16:0],1'b0};
end
2'd2: begin
baseband_sel_i <= {hrc_wave_i_1p5[16:0],1'b0};
baseband_sel_q <= {hrc_wave_q_1p5[16:0],1'b0};
end
2'd3: begin
baseband_sel_i <= 18'b01_1111_1111_1111_1111;
baseband_sel_q <= 18'b0;
end
default: begin
baseband_sel_i <= {hrc_wave_i_48[16:0],1'b0};
baseband_sel_q <= {hrc_wave_q_48[16:0],1'b0};
end
endcase
end
end
// hopping control, 3750hop/s
reg [23:0] sweep_rom_addr = 'b0;
wire [31:0] freq_sweep;
always @(posedge clk) begin
if (rst) begin
sweep_rom_addr <= 'b0;
end
else if (sweep_on) begin
sweep_rom_addr <= sweep_rom_addr + 24'b1;
end
else begin
sweep_rom_addr <= 'b0;
end
end
hop_rom u_sweep_rom
(
.clka (clk ), // input wire clka
.addra (sweep_rom_addr[23:16] ), // input wire [7 : 0] addra
.douta (freq_sweep ) // output wire [31 : 0] douta
);
// choose the actual frequency word
reg [31:0] freq_word = 'b0;
always @(posedge clk) begin
if (rst) begin
freq_word <= 'b0;
end
else if (sweep_on) begin
// frequency sweep
freq_word <= freq_sweep;
end
else begin
// normal operation
freq_word <= freq_set;
end
end
// baseband frequency shift carrier generation
wire [ 7:0] cos_dds;
wire [ 7:0] sin_dds;
reg [ 7:0] cos = 'b0;
reg [ 7:0] sin = 'b0;
dds_32b_8b u_dds_bb_shift (
.aclk (clk ), // input wire aclk
.s_axis_config_tvalid (~rst ), // input wire s_axis_config_tvalid
.s_axis_config_tdata (freq_word ), // input wire [31 : 0] s_axis_config_tdata
.m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid
.m_axis_data_tdata ({sin_dds,cos_dds}) // output wire [31 : 0] m_axis_data_tdata
);
always @(posedge clk) begin
if (rst) begin
cos <= 'b0;
sin <= 'b0;
end
else if (freq_word == 'b0) begin
// to make sure the carriers stay at the right position when freq = 0
cos <= 8'b0111_1111;
sin <= 8'b0111_1111;
end
else begin
cos <= cos_dds;
sin <= sin_dds;
end
end
// baseband frequency shift modulation
wire [47:0] mod_cmpy_a;
wire [15:0] mod_cmpy_b;
wire [63:0] mod_cmpy_out;
wire [26:0] baseband_mult_i;
wire [26:0] baseband_mult_q;
assign mod_cmpy_a = {6'b0,baseband_sel_q,6'b0,baseband_sel_i};
assign mod_cmpy_b = {-sin,cos};
assign baseband_mult_i = mod_cmpy_out[58:32];
assign baseband_mult_q = mod_cmpy_out[26: 0];
cmpy_18x8 u_cmpy_18x8
(
.aclk (clk ), // input wire aclk
.s_axis_a_tvalid (1'b1 ), // input wire s_axis_a_tvalid
.s_axis_a_tdata (mod_cmpy_a ), // input wire [47 : 0] s_axis_a_tdata
.s_axis_b_tvalid (1'b1 ), // input wire s_axis_b_tvalid
.s_axis_b_tdata (mod_cmpy_b ), // input wire [15 : 0] s_axis_b_tdata
.m_axis_dout_tvalid ( ), // output wire m_axis_dout_tvalid
.m_axis_dout_tdata (mod_cmpy_out ) // output wire [63 : 0] m_axis_dout_tdata
);
// truncate to 16-bit
reg signed [15:0] baseband_i = 'b0;
reg signed [15:0] baseband_q = 'b0;
always @(posedge clk) begin
if (rst) begin
baseband_i <= 'b0;
baseband_q <= 'b0;
end
else begin
case (waveform_sel[1:0])
2'd0: begin
// scale rasied-cosine-shaped bpsk signal by 1.125 or 1.625
baseband_i <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_i[17 -: 16] : baseband_mult_i[25:10];
baseband_q <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_q[17 -: 16] : baseband_mult_q[25:10];
end
2'd1: begin
baseband_i <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_i[17 -: 16] : baseband_mult_i[25:10];
baseband_q <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_q[17 -: 16] : baseband_mult_q[25:10];
end
2'd2: begin
baseband_i <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_i[17 -: 16] : baseband_mult_i[25:10];
baseband_q <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_q[17 -: 16] : baseband_mult_q[25:10];
end
2'd3: begin
baseband_i <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_i[17 -: 16] : baseband_mult_i[24:9];
baseband_q <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_q[17 -: 16] : baseband_mult_q[24:9];
end
default: begin
// scale rasied-cosine-shaped bpsk signal by 1.125
baseband_i <= baseband_mult_i[25:10];
baseband_q <= baseband_mult_q[25:10];
end
endcase
end
end
// iq selection & baseband right shift
reg signed [15:0] baseband_data_i = 'b0;
reg signed [15:0] baseband_data_q = 'b0;
always @(posedge clk) begin
if (rst) begin
baseband_data_i <= 'b0;
baseband_data_q <= 'b0;
end
else begin
// inphase selection
if (iq_sel[1]) begin
baseband_data_i <= baseband_i >>> bb_rshift;
end
else begin
baseband_data_i <= 'b0;
end
// quadrature selection
if (iq_sel[0]) begin
baseband_data_q <= baseband_q >>> bb_rshift;
end
else begin
baseband_data_q <= 'b0;
end
end
end
// output data to ports
assign tx_data_i = baseband_data_i[15 -: DATA_WIDTH];
assign tx_data_q = baseband_data_q[15 -: DATA_WIDTH];
endmodule
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2020/12/08 12:43:46
// Design Name:
// Module Name: tb_tx_qpsk
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
// module tb_tx_qpsk;
// reg clk = 1'b0 ;
// reg rst = 1'b1 ;
// reg tx_on = 1'b1 ;
// reg [31:0] freq_set ;
// reg [ 1:0] waveform_sel = 2'b00;
// reg [ 1:0] iq_sel = 2'b11 ;
// wire [11:0] tx_data_i ;
// wire [11:0] tx_data_q ;
// reg [ 3:0] bb_rshift = 5'b0 ;
// tx_qpsk u_tx_qpsk
// (
// .clk (clk ),
// .rst (rst ),
// .tx_data_i (tx_data_i ),
// .tx_data_q (tx_data_q ),
// .waveform_sel (waveform_sel ),
// .sweep_on (1'b0 ),
// // .freq_set (32'd447392426 ),
// .freq_set (32'd0 ),
// .iq_sel (iq_sel ),
// .bb_rshift (bb_rshift )
// );
// initial begin
// #102
// rst = 1'b0;
// // freq_set = 32'd873813333;
// // waveform_sel = 2'b00;
// // bb_rshift = 5'd0;
// // #5000
// // bb_rshift = 5'd1;
// // #5000
// // bb_rshift = 5'd2;
// // #5000
// // bb_rshift = 5'd3;
// // #5000
// // bb_rshift = 5'd4;
// // #5000
// // bb_rshift = 5'd5;
// // #5000
// // bb_rshift = 5'd6;
// // #5000
// // bb_rshift = 5'd7;
// // #5000
// // bb_rshift = 5'd8;
// // #5000
// // bb_rshift = 5'd9;
// // #5000
// // bb_rshift = 5'd14;
// // #5000
// // bb_rshift = 5'd15;
// // #5000
// // bb_rshift = 5'd16;
// // freq_set = 32'd0;
// // func_sel = 3'b010;
// // #7777
// // freq_set = 32'd536870912;
// // func_sel = 3'b100;
// // #7777
// // freq_set = 32'd0;
// // func_sel = 3'b100;
// // #7777
// // freq_set = 32'd536870912;
// // func_sel = 3'b010;
// // #7777
// // freq_set = 32'd0;
// // func_sel = 3'b010;
// // freq_set = 32'd536870912;
// // iq_sel = 2'b00;
// // #7777
// // freq_set = 32'd536870912;
// // iq_sel = 2'b01;
// // #7777
// // freq_set = 32'd536870912;
// // iq_sel = 2'b10;
// // #7777
// // freq_set = 32'd536870912;
// // iq_sel = 2'b11;
// end
// always #5 clk = ~clk;
// // integer i;
// // integer w_file;
// // initial begin
// // w_file = $fopen("D:\\qpsk_josh.txt","w");
// // for (i = 0; i <= 35000; i = i + 1) begin
// // wait(clk);
// // #10;
// // $fdisplay(w_file,"%d %d",$signed(tx_data_i),
// // $signed(tx_data_q));
// // if (i == 35000) begin
// // $fclose(w_file);
// // $stop;
// // end
// // end
// // end
// endmodule
cx9261a_demo_cmos_20240513/project_fix_dac.srcs/sources_1/ip/coe/CreatePN40_LocalTemp_256points.m
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%% PN56
clc;clear;close all;
addpath(genpath(pwd));
%% 参数设置
load("PN40_reverse.mat");
% GMSK 调制的参数
BT = 0.3;
Rc = 1.5e6; % 码片速率 1.4Mcps
fs_clk = 48e6; % ADC 的采样速率
fs_acq = 4.8e6; % 捕获模块采样速率为3.2M, 与 Rc并不是整数倍关系
SampRate = fs_clk/Rc; % 对于码片的过采样率
% PN 码,帧结构参数
PNLen = 40; % 一组PN码的长度
% 捕获时参数
FFT_Len = 256;
Acq_Sample = fs_acq/Rc; %捕获时,采用的过采样率
FreSearchIdx = 0;
%% 发送端
frameSend = repmat(PN40,1,40);
[GMSKSendWave] = gmsk_base_modfpga_fuc(frameSend,BT,SampRate,4);
%变采样率,获取本地模板
% h = LPF_Fpass1p8_Fstop2p2_Fs48_40dB;
% hLen = floor(length(h)/2);
%
% GMSKSendWave2 = conv(GMSKSendWave,h);
% GMSKSendWave2 = GMSKSendWave2(hLen+1:end-hLen);
% 对抗混叠滤波后的数据,进行抽取
% Acq_Din = downsample(GMSKSendWave2,fs_clk/fs_acq);
Acq_Din = downsample(GMSKSendWave,fs_clk/fs_acq);
% 取本地模板
PNWave = Acq_Din(1:FFT_Len);
PNWaveLocalTemp = PNWave(1:FFT_Len);
PNWaveLocalTemp_Norm = PNWaveLocalTemp/max(PNWaveLocalTemp);
Acq_FFTLocalTemp = fft(PNWave,FFT_Len);
Acq_FFTLocalTemp_Norm = Acq_FFTLocalTemp/max(abs(Acq_FFTLocalTemp));
%save("GMSKSendWave.mat","GMSKSendWave");
%归一化并量化
q = quantizer([16, 15], 'fixed', 'convergent', 'saturate');
Acq_FFTLocalTemp_Norm = quantize(q,Acq_FFTLocalTemp_Norm);
% 转换为 16进制
Acq_FFTLocalTemp_I_FPGA = num2hex(q,real(Acq_FFTLocalTemp_Norm));
Acq_FFTLocalTemp_Q_FPGA = num2hex(q,imag(Acq_FFTLocalTemp_Norm));
Acq_FFTLocalTemp_FPGA = [Acq_FFTLocalTemp_Q_FPGA,Acq_FFTLocalTemp_I_FPGA];
%% 写入到 coe 文件中
data = Acq_FFTLocalTemp_FPGA;
fid = fopen("New_AcqPN40_FFTLocalTemp_256points.coe",'w');
fprintf(fid,'memory_initialization_radix=16;\n');
fprintf(fid,'memory_initialization_vector=\n');
for i = 1:length(data)
fprintf(fid,'%s\n',data(i,:));
end
fclose(fid);
% %% 保存Maltab 变量
% save("Acq_FFTLocalTemp.mat","Acq_FFTLocalTemp_Norm","Acq_FFTLocalTemp_FPGA");
%
save("New_AcqPN40_FFTLocalTemp_256points.mat","Acq_FFTLocalTemp_Norm","PNWaveLocalTemp_Norm");
%%
rmpath(genpath(pwd));
cx9261a_demo_cmos_20240513/project_fix_dac.srcs/sources_1/ip/coe/coe_gen.m
+90
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@@ -0,0 +1,90 @@
function coe_gen(data,file_name,varargin)%varargin : type radix [bit_width]
%coe_gen - Xilinx coe文件生成，根据官网语法说明编写
%
% coe_gen(data, file_nanme)
% coe_gen(data,file_name,type)
% coe_gen(data,file_name,type, 'd')
% coe_gen(data,file_name,type, radix, bit_width)
%
% data - integer double 需要写入的数据,整数或定点小数一维向量
% 为定点数时，只能使用十进制保存
% file_name - char 文件名或完成存放路径
% type - char coe文件类型 'memory' 'filter' 'correlator' 'interleaver'
% radix - char 数据保存进制 'b' 'd' 'h'
% 'b' 二进制
% 'd' 十进制
% 'h' 十六进制
% 二进制与十六进制时候需要指明位宽
% bit_width - integer 数据位宽
%
% Author: Fan Hao.
% References: https://www.xilinx.com/support/documentation/sw_manuals/xilinx11/cgn_r_coe_file_syntax.htm
% Copyright Beijing Institute of Technology.
radix_dic_str = ['b','o','d','h'];
radix_dic_num = [2 8 10 16];
narginchk(2,5);
%input check
if isempty(varargin) %default properties
radix = 10; type = 'memory';
else %type check
if length(varargin)>=1 &&ismember(varargin{1},{'memory','filter','correlator','interleaver'})
type = varargin{1};
else
error('ERROR: wrong coe file type!');
end%radix and bit_width check
if length(varargin)>=2 && ismember(varargin{2},['b','d','h'])
radix = radix_dic_num(radix_dic_str==varargin{2});
if varargin{2} ~= 'd'
if length(varargin)==3 && ~mod(varargin{3},1)
bit_width = varargin{3};
else
error('ERROR: bit width must be specified as a integer.');
end
else
if length(varargin)==3
error('ERROR: too many argument.');
end
end
else
if length(varargin)==1
radix = 10;
else
error("ERROR: radix must be 'b' or 'd' or 'h'.");
end
end
end
%create file
file_p = fopen(file_name, 'w+', 'n', 'UTF-8');
if type == 'memory'
fprintf(file_p,['MEMORY_INITIALIZATION_RADIX = ' num2str(radix) ';\n']);
else
fprintf(file_p,['RADIX = ' num2str(radix) ';\n']);
end
switch type
case 'memory'
fprintf(file_p,['MEMORY_INITIALIZATION_VECTOR = ' '\n']);
case 'filter'
fprintf(file_p,['COEFDATA = ' '\n']);
case 'correlator'
fprintf(file_p,['PATTERN = ' '\n']);
case 'interleaver'
fprintf(file_p,['BRANCH_LENGTH_VECTOR = ' '\n']);
end
for i = 1:length(data)
switch radix
case 2
temp = dec2bin(data(i),bit_width);
case 10
temp = num2str(data(i));
case 16
temp = dec2hex(data(i),ceil(bit_width/4));
end
if i == length(data)
fprintf(file_p,[temp ';\n']);
else
fprintf(file_p,[temp ',\n']);
end
end
fclose(file_p);
end
cx9261a_demo_cmos_20240513/project_fix_dac.srcs/sources_1/ip/coe/generate_baseband_coe.m
+29
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@@ -0,0 +1,29 @@
% clear all
% clc
% % pnSequence=comn.PNSequence('Polynomial','x^10+x^7+1','InitialConditions',[zeros(1,9),1],'SamplesPerFrame',2^10-1);
% % PRBS10=pnSequence();
% % PRB10_polar=1-2*[ PRBS10;0];
% % coe_gen(PRBS10,'prbs10.coe','memory');
% hrc=rcosdesign(0.35,6,8,'sqrt');
% %hrc=rcosdesign(0.25,12,64);
% hrc_16b=round(hrc/max(hrc)*(2^15-1));
% %coe_gen(hrc_16b,'hrc_64_12_025.coe','memory');
% coe_gen(hrc_16b,'hrc_8_6_035.coe','memory');
clear all
clc
fs = 64e6;
Rs = 48e6;
alpha = 0.3;
hrc_48 = rcosdesign(alpha,12,4,'sqrt');%span=6,sps=4
hrc_48_16b=round(hrc_48/max(hrc_48)*(2^15-1));
coe_gen(hrc_48_16b,'hrc_4_12_03.coe','memory');
hrc_12 = rcosdesign(alpha,12,16,'sqrt');
hrc_12_16b=round(hrc_12/max(hrc_12)*(2^15-1));
coe_gen(hrc_12_16b,'hrc_16_12_03.coe','memory');
hrc_1p5 = rcosdesign(alpha,12,128,'sqrt');
hrc_1p5_16b=round(hrc_1p5/max(hrc_1p5)*(2^15-1));
coe_gen(hrc_1p5_16b,'hrc_128_12_03.coe','memory');
cx9261a_demo_cmos_20240513/project_fix_dac.srcs/sources_1/ip/coe/hrc_128_12_03.coe
+1539
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File diff suppressed because it is too large Load Diff
cx9261a_demo_cmos_20240513/project_fix_dac.srcs/sources_1/ip/coe/hrc_16_12_03.coe
+195
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@@ -0,0 +1,195 @@
RADIX = 10;
COEFDATA =
-203,
-163,
-111,
-50,
17,
85,
152,
212,
261,
296,
315,
315,
295,
257,
203,
134,
55,
-29,
-113,
-191,
-258,
-309,
-340,
-348,
-331,
-290,
-226,
-142,
-43,
64,
172,
273,
360,
426,
462,
465,
432,
360,
252,
112,
-55,
-238,
-428,
-612,
-778,
-911,
-1000,
-1033,
-1003,
-903,
-732,
-492,
-190,
163,
553,
960,
1363,
1738,
2060,
2305,
2451,
2476,
2368,
2114,
1714,
1171,
497,
-288,
-1154,
-2067,
-2986,
-3864,
-4652,
-5298,
-5752,
-5968,
-5902,
-5521,
-4797,
-3715,
-2271,
-476,
1651,
4073,
6744,
9606,
12592,
15628,
18635,
21533,
24239,
26679,
28782,
30486,
31740,
32508,
32767,
32508,
31740,
30486,
28782,
26679,
24239,
21533,
18635,
15628,
12592,
9606,
6744,
4073,
1651,
-476,
-2271,
-3715,
-4797,
-5521,
-5902,
-5968,
-5752,
-5298,
-4652,
-3864,
-2986,
-2067,
-1154,
-288,
497,
1171,
1714,
2114,
2368,
2476,
2451,
2305,
2060,
1738,
1363,
960,
553,
163,
-190,
-492,
-732,
-903,
-1003,
-1033,
-1000,
-911,
-778,
-612,
-428,
-238,
-55,
112,
252,
360,
432,
465,
462,
426,
360,
273,
172,
64,
-43,
-142,
-226,
-290,
-331,
-348,
-340,
-309,
-258,
-191,
-113,
-29,
55,
134,
203,
257,
295,
315,
315,
296,
261,
212,
152,
85,
17,
-50,
-111,
-163,
-203;
cx9261a_demo_cmos_20240513/project_fix_dac.srcs/sources_1/ip/coe/hrc_4_12_03.coe
+51
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@@ -0,0 +1,51 @@
RADIX = 10;
COEFDATA =
-203,
17,
261,
295,
55,
-258,
-331,
-43,
360,
432,
-55,
-778,
-1003,
-190,
1363,
2451,
1714,
-1154,
-4652,
-5902,
-2271,
6744,
18635,
28782,
32767,
28782,
18635,
6744,
-2271,
-5902,
-4652,
-1154,
1714,
2451,
1363,
-190,
-1003,
-778,
-55,
432,
360,
-43,
-331,
-258,
55,
295,
261,
17,
-203;
cx9261a_demo_cmos_20240513/project_fix_dac.srcs/sources_1/ip/cx9261a_fifo/cx9261a_fifo.dcp
LFS
BIN
View File
Binary file not shown.
cx9261a_demo_cmos_20240513/project_fix_dac.srcs/sources_1/ip/cx9261a_fifo/cx9261a_fifo.veo
+72
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@@ -0,0 +1,72 @@
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of AMD and is protected under U.S. and international copyright
// and other intellectual property laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// AMD, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) AMD shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or AMD had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// AMD products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of AMD products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:fifo_generator:13.2
// IP Revision: 10
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
cx9261a_fifo your_instance_name (
.wr_clk(wr_clk), // input wire wr_clk
.rd_clk(rd_clk), // input wire rd_clk
.din(din), // input wire [31 : 0] din
.wr_en(wr_en), // input wire wr_en
.rd_en(rd_en), // input wire rd_en
.dout(dout), // output wire [31 : 0] dout
.full(full), // output wire full
.empty(empty) // output wire empty
);
// INST_TAG_END ------ End INSTANTIATION Template ---------
// You must compile the wrapper file cx9261a_fifo.v when simulating
// the core, cx9261a_fifo. When compiling the wrapper file, be sure to
// reference the Verilog simulation library.
cx9261a_demo_cmos_20240513/project_fix_dac.srcs/sources_1/ip/cx9261a_fifo/cx9261a_fifo.vho
+90
View File
@@ -0,0 +1,90 @@
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of AMD and is protected under U.S. and international copyright
-- and other intellectual property laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- AMD, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) AMD shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or AMD had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- AMD products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of AMD products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:13.2
-- IP Revision: 10
-- The following code must appear in the VHDL architecture header.
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
COMPONENT cx9261a_fifo
PORT (
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END COMPONENT;
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
-- The following code must appear in the VHDL architecture
-- body. Substitute your own instance name and net names.
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
your_instance_name : cx9261a_fifo
PORT MAP (
wr_clk => wr_clk,
rd_clk => rd_clk,
din => din,
wr_en => wr_en,
rd_en => rd_en,
dout => dout,
full => full,
empty => empty
);
-- INST_TAG_END ------ End INSTANTIATION Template ---------
-- You must compile the wrapper file cx9261a_fifo.vhd when simulating
-- the core, cx9261a_fifo. When compiling the wrapper file, be sure to
-- reference the VHDL simulation library.
cx9261a_demo_cmos_20240513/project_fix_dac.srcs/sources_1/ip/cx9261a_fifo/cx9261a_fifo.xci
+479
View File
@@ -0,0 +1,479 @@
{
"schema": "xilinx.com:schema:json_instance:1.0",
"ip_inst": {
"xci_name": "cx9261a_fifo",
"component_reference": "xilinx.com:ip:fifo_generator:13.2",
"ip_revision": "10",
"gen_directory": ".",
"parameters": {
"component_parameters": {
"Component_Name": [ { "value": "cx9261a_fifo", "resolve_type": "user", "usage": "all" } ],
"Fifo_Implementation": [ { "value": "Independent_Clocks_Distributed_RAM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"synchronization_stages": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
"synchronization_stages_axi": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
"INTERFACE_TYPE": [ { "value": "Native", "resolve_type": "user", "usage": "all" } ],
"Performance_Options": [ { "value": "Standard_FIFO", "resolve_type": "user", "usage": "all" } ],
"asymmetric_port_width": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Input_Data_Width": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Input_Depth": [ { "value": "64", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"Output_Data_Width": [ { "value": "32", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Output_Depth": [ { "value": "64", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"Enable_ECC": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Use_Embedded_Registers": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Reset_Pin": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Enable_Reset_Synchronization": [ { "value": "true", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Reset_Type": [ { "value": "Asynchronous_Reset", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Full_Flags_Reset_Value": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Use_Dout_Reset": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Dout_Reset_Value": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"dynamic_power_saving": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Almost_Full_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Almost_Empty_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Valid_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Valid_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Underflow_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Underflow_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Write_Acknowledge_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Write_Acknowledge_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Overflow_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Overflow_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Inject_Sbit_Error": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Inject_Dbit_Error": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"ecc_pipeline_reg": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Use_Extra_Logic": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Data_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Data_Count_Width": [ { "value": "6", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"Write_Data_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Write_Data_Count_Width": [ { "value": "6", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"Read_Data_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Read_Data_Count_Width": [ { "value": "6", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"Disable_Timing_Violations": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Read_Clock_Frequency": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"Write_Clock_Frequency": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"Programmable_Full_Type": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "usage": "all" } ],
"Full_Threshold_Assert_Value": [ { "value": "61", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"Full_Threshold_Negate_Value": [ { "value": "60", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"Programmable_Empty_Type": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "usage": "all" } ],
"Empty_Threshold_Assert_Value": [ { "value": "2", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"Empty_Threshold_Negate_Value": [ { "value": "3", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"PROTOCOL": [ { "value": "AXI4", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Clock_Type_AXI": [ { "value": "Common_Clock", "resolve_type": "user", "usage": "all" } ],
"HAS_ACLKEN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Clock_Enable_Type": [ { "value": "Slave_Interface_Clock_Enable", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "resolve_type": "user", "usage": "all" } ],
"ID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"ADDRESS_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
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cx9261a_demo_cmos_20240513/project_fix_dac.srcs/sources_1/ip/cx9261a_fifo/cx9261a_fifo.xdc
+64
View File
@@ -0,0 +1,64 @@
################################################################################
# (c) Copyright 2009 - 2013 Advanced Micro Devices, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Advanced Micro Devices, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# AMD, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) AMD shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or AMD had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# AMD products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of AMD products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#
################################################################################
#------------------------------------------------------------------------------#
# Native FIFO Constraints #
#------------------------------------------------------------------------------#
################################################################################
cx9261a_demo_cmos_20240513/project_fix_dac.srcs/sources_1/ip/cx9261a_fifo/cx9261a_fifo.xml
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cx9261a_demo_cmos_20240513/project_fix_dac.srcs/sources_1/ip/cx9261a_fifo/cx9261a_fifo_clocks.xdc
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################################################################################
# (c) Copyright 2009 - 2013 Advanced Micro Devices, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Advanced Micro Devices, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# AMD, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) AMD shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or AMD had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# AMD products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of AMD products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#
################################################################################
#------------------------------------------------------------------------------#
# Native FIFO Constraints #
#------------------------------------------------------------------------------#
#set wr_clock [get_clocks -of_objects [get_ports wr_clk]]
#set rd_clock [get_clocks -of_objects [get_ports rd_clk]]
#set wr_clk_period [get_property PERIOD $wr_clock]
#set rd_clk_period [get_property PERIOD $rd_clock]
#set skew_value [expr {(($wr_clk_period < $rd_clk_period) ? $wr_clk_period : $rd_clk_period)} ]
# Ignore paths from the write clock to the read data registers for Asynchronous Distributed RAM based FIFO
set_false_path -from [filter [all_fanout -from [get_ports wr_clk] -flat -endpoints_only] {IS_LEAF}] -to [get_cells -hierarchical -filter {NAME =~ *gdm.dm_gen.dm*/gpr1.dout_i_reg*}]
# Set max delay on cross clock domain path for Block/Distributed RAM based FIFO
## set_max_delay -from [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*rd_pntr_gc_reg[*]] -to [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*gsync_stage[1].wr_stg_inst/Q_reg_reg[*]] -datapath_only [get_property -min PERIOD $rd_clock]
## set_bus_skew -from [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*rd_pntr_gc_reg[*]] -to [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*gsync_stage[1].wr_stg_inst/Q_reg_reg[*]] $skew_value
## set_max_delay -from [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*wr_pntr_gc_reg[*]] -to [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*gsync_stage[1].rd_stg_inst/Q_reg_reg[*]] -datapath_only [get_property -min PERIOD $wr_clock]
## set_bus_skew -from [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*wr_pntr_gc_reg[*]] -to [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*gsync_stage[1].rd_stg_inst/Q_reg_reg[*]] $skew_value
################################################################################
cx9261a_demo_cmos_20240513/project_fix_dac.srcs/sources_1/ip/cx9261a_fifo/cx9261a_fifo_ooc.xdc
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# (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
# (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of AMD and is protected under U.S. and international copyright
# and other intellectual property laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# AMD, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) AMD shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or AMD had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# AMD products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of AMD products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#
# DO NOT MODIFY THIS FILE.
# #########################################################
#
# This XDC is used only in OOC mode for synthesis, implementation
#
# #########################################################
create_clock -period 10 -name wr_clk [get_ports wr_clk]
create_clock -period 10 -name rd_clk [get_ports rd_clk]
cx9261a_demo_cmos_20240513/project_fix_dac.srcs/sources_1/ip/cx9261a_fifo/cx9261a_fifo_sim_netlist.v
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// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
// Date : Sat Nov 2 11:18:01 2024
// Host : gatsby-dev running 64-bit Red Hat Enterprise Linux release 8.10 (Ootpa)
// Command : write_verilog -force -mode synth_stub
// /home/josh/Workspace/vivado/brd_cx2161a/cx9261a_demo_cmos_20240513/project_fix_dac.srcs/sources_1/ip/cx9261a_fifo/cx9261a_fifo_stub.v
// Design : cx9261a_fifo
// Purpose : Stub declaration of top-level module interface
// Device : xc7z045ffg900-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "fifo_generator_v13_2_10,Vivado 2024.1" *)
module cx9261a_fifo(wr_clk, rd_clk, din, wr_en, rd_en, dout, full, empty)
/* synthesis syn_black_box black_box_pad_pin="din[31:0],wr_en,rd_en,dout[31:0],full,empty" */
/* synthesis syn_force_seq_prim="wr_clk" */
/* synthesis syn_force_seq_prim="rd_clk" */;
input wr_clk /* synthesis syn_isclock = 1 */;
input rd_clk /* synthesis syn_isclock = 1 */;
input [31:0]din;
input wr_en;
input rd_en;
output [31:0]dout;
output full;
output empty;
endmodule
cx9261a_demo_cmos_20240513/project_fix_dac.srcs/sources_1/ip/cx9261a_fifo/cx9261a_fifo_stub.vhdl
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-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
-- Date : Sat Nov 2 11:18:01 2024
-- Host : gatsby-dev running 64-bit Red Hat Enterprise Linux release 8.10 (Ootpa)
-- Command : write_vhdl -force -mode synth_stub
-- /home/josh/Workspace/vivado/brd_cx2161a/cx9261a_demo_cmos_20240513/project_fix_dac.srcs/sources_1/ip/cx9261a_fifo/cx9261a_fifo_stub.vhdl
-- Design : cx9261a_fifo
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z045ffg900-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity cx9261a_fifo is
Port (
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 31 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC
);
end cx9261a_fifo;
architecture stub of cx9261a_fifo is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "wr_clk,rd_clk,din[31:0],wr_en,rd_en,dout[31:0],full,empty";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "fifo_generator_v13_2_10,Vivado 2024.1";
begin
end;
cx9261a_demo_cmos_20240513/project_fix_dac.srcs/sources_1/ip/cx9261a_fifo/doc/fifo_generator_v13_2_changelog.txt
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2024.1:
* Version 13.2 (Rev. 10)
* General: IP packaging adjustments to address warnings from IP Packager integrity check
* Revision change in one or more subcores
2023.2.2:
* Version 13.2 (Rev. 9)
* No changes
2023.2.1:
* Version 13.2 (Rev. 9)
* No changes
2023.2:
* Version 13.2 (Rev. 9)
* General: Rebrand to AMD copyright information
* Revision change in one or more subcores
2023.1.2:
* Version 13.2 (Rev. 8)
* No changes
2023.1.1:
* Version 13.2 (Rev. 8)
* No changes
2023.1:
* Version 13.2 (Rev. 8)
* Revision change in one or more subcores
2022.2.2:
* Version 13.2 (Rev. 7)
* No changes
2022.2.1:
* Version 13.2 (Rev. 7)
* No changes
2022.2:
* Version 13.2 (Rev. 7)
* No changes
2022.1.2:
* Version 13.2 (Rev. 7)
* No changes
2022.1.1:
* Version 13.2 (Rev. 7)
* No changes
2022.1:
* Version 13.2 (Rev. 7)
* General: Security key added. No functional changes
2021.2.2:
* Version 13.2 (Rev. 6)
* No changes
2021.2.1:
* Version 13.2 (Rev. 6)
* No changes
2021.2:
* Version 13.2 (Rev. 6)
* Revision change in one or more subcores
2021.1.1:
* Version 13.2 (Rev. 5)
* No changes
2021.1:
* Version 13.2 (Rev. 5)
* No changes
2020.3:
* Version 13.2 (Rev. 5)
* No changes
2020.2.2:
* Version 13.2 (Rev. 5)
* No changes
2020.2.1:
* Version 13.2 (Rev. 5)
* No changes
2020.2:
* Version 13.2 (Rev. 5)
* No changes
2020.1.1:
* Version 13.2 (Rev. 5)
* No changes
2020.1:
* Version 13.2 (Rev. 5)
* No changes
2019.2.2:
* Version 13.2 (Rev. 5)
* No changes
2019.2.1:
* Version 13.2 (Rev. 5)
* No changes
2019.2:
* Version 13.2 (Rev. 5)
* General: IP Waivers update in constraint files. No functional changes
* Revision change in one or more subcores
2019.1.3:
* Version 13.2 (Rev. 4)
* No changes
2019.1.2:
* Version 13.2 (Rev. 4)
* No changes
2019.1.1:
* Version 13.2 (Rev. 4)
* No changes
2019.1:
* Version 13.2 (Rev. 4)
* Bug Fix: Destination Clock not connected properly for some XPM_CDC instances when in common clock mode. Conditions added to connect the correct clock
* Other: IP Waivers added in constraint files. No functional changes
* Revision change in one or more subcores
2018.3.1:
* Version 13.2 (Rev. 3)
* No changes
2018.3:
* Version 13.2 (Rev. 3)
* Feature Enhancement: None
* Other: Reduced simulation warnings in Behavioral model. No functional changes
* Revision change in one or more subcores
2018.2:
* Version 13.2 (Rev. 2)
* No changes
2018.1:
* Version 13.2 (Rev. 2)
* Bug Fix: Enable Safety Circuit option was unintentionally made available for user selection when Enable Reset Synchronization is not selected. This unintentional enablement is corrected and Enable Safety Circuit is available for user selection only if Enable Reset Synchronization option is selected
* Bug Fix: REQP-1839 DRC warning removed from example test bench
* Bug Fix: Read Data Count in behavioral model is updated to start with a valid value when Enable Reset Synchronization option is not selected
* Other: As FIFO Generator core uses XPM_CDC module, user must ensure that the wr_rst and rd_rst overlap for at least C_SYNCHRONIZER_STAGE+1 slowest clock cycles if Enable Reset Synchronization option is disabled
2017.4:
* Version 13.2 (Rev. 1)
* Revision change in one or more subcores
2017.3:
* Version 13.2
* Feature Enhancement: Enable Safety Circuit option is made default for BRAM based FIFOs when Asynchronous Reset is selected
* Feature Enhancement: All outputs are made synchronous to respective clock domain when Enable Safety Circuit option is selected
* Feature Enhancement: All outputs are invalid for reset duration + 60 slowest clock cycles when Enable Safety Circuit option is selected
* Feature Enhancement: All outputs are invalid for reset duration + 30 slowest clock cycles when Enable Safety Circuit option is not selected
* Feature Enhancement: The outputs of FIFO Generator may be Xs for initial few clock cycles if the core is configured without reset. It is recommended to wait for 15 slowest clock cycles at the beginning of behavioral simulation (from time 0) before accessing the FIFO
2017.2:
* Version 13.1 (Rev. 4)
* No changes
2017.1:
* Version 13.1 (Rev. 4)
* Bug Fix: FIFO Generator core was constructing the buit-in FIFO sub-optimally for 2K-deep and 36-bit wide configuration. This is corrected to use the optimal FIFO structure
* Bug Fix: In order to enable the tool to perform the recovery check on the reset, set_false_path for reset is kept only from the input port to the first flop where it connects to
* Feature Enhancement: Updated the FIFO Generator's constraints to improve tool performance processing its XDC
* Other: Internal device family change, no functional changes
* Revision change in one or more subcores
2016.4:
* Version 13.1 (Rev. 3)
* Port Change: None
* Bug Fix: Supported features table in the first page of GUI updated to reflect the asymmetry support for common clock BRAM FIFO
* Feature Enhancement: None
* Revision change in one or more subcores
2016.3:
* Version 13.1 (Rev. 2)
* Port Change: wr_rst_busy and rd_rst_busy ports made available if safety circuit is enabled
* Bug Fix: Fixed issue which was causing the m_axis_tvalid to go high after the reset is released and no valid data written to the FIFO
* Feature Enhancement: Safety circuit is made independent of Output Register and Enable Reset Synchronization options
* Other: Added support for future devices
* Other: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user
* Revision change in one or more subcores
2016.2:
* Version 13.1 (Rev. 1)
* Revision change in one or more subcores
2016.1:
* Version 13.1
* Delivering only Verilog behavioral model.
* Constraint(s) for Independent Clocks Distributed RAM FIFO is changed, which may issue a CDC-1 warning that can be safely ignored.
* Output Register option is updated to offer either Embedded Register or Fabric Register or Both Embedded and Fabric Registers.
* Updated the FIFO Generator GUI to provide Embedded Register option for Built-in FIFO when ECC mode in selected.
* Programmable Full and Programmable Empty Threshold range has been reduced for UltraScale and UltraScale+ Built-in FIFO configurations. For more information on the exact threshold range change, refer the PG(057)
* Programmable Full and Programmable Empty Threshold values were reset to its default values when the previous version of the core is upgraded to the latest version. This has been corrected
* Revision change in one or more subcores
2015.4.2:
* Version 13.0 (Rev. 1)
* No changes
2015.4.1:
* Version 13.0 (Rev. 1)
* No changes
2015.4:
* Version 13.0 (Rev. 1)
* Fixed safety circuit related warnings in Behavioral model
* Revision change in one or more subcores
2015.3:
* Version 13.0
* Additional safety circuit option provided for asynchronous reset configurations.
* Delivering only VHDL behavioral model.
* Added asymmetric port width support for 7-series Common Clock Block RAM FIFO
* IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances
2015.2.1:
* Version 12.0 (Rev. 4)
* No changes
2015.2:
* Version 12.0 (Rev. 4)
* No changes
2015.1:
* Version 12.0 (Rev. 4)
* Delivering non encrypted behavioral models.
* Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock ports
* Enabling behavioral simulation for Built-in FIFO configurations changes the simulation file names and delivery structure.
* Supported devices and production status are now determined automatically, to simplify support for future devices
2014.4.1:
* Version 12.0 (Rev. 3)
* No changes
2014.4:
* Version 12.0 (Rev. 3)
* Reduced DRC warnings.
* Internal device family change, no functional changes
* Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
2014.3:
* Version 12.0 (Rev. 2)
* Added support for Asynchronous AXI Stream Packet FIFO for UltraScale devices.
* Added support for write data count and read data count for Asynchronous AXI Stream Packet FIFO for UltraScale devices.
* Added support for write data count and read data count for Common Clock Block RAM FIFO when Asymmetric Port Width option is enabled for UltraScale devices.
* Added support for Low Latency Built-in FIFO for UltraScale devices.
2014.2:
* Version 12.0 (Rev. 1)
* Repackaged to improve internal automation, no functional changes.
2014.1:
* Version 12.0
* Asynchronous reset port (rst) for Built-in FIFO configurations is removed for UltraScale Built-in FIFO configurations. When upgrading from previously released core, 'rst' port will be replaced by 'srst' port.
* Synchronous reset (srst) mechanism is changed now for UltraScale devices. FIFO Generator will now provide wr_rst_busy and rd_rst_busy output ports. When wr_rst_busy is active low, the core is ready for write operation and when rd_rst_busy is active low, the core is ready for read operation.
* Added asymmetric port width support for Common Clock Block RAM FIFO, Common Clock Built-in FIFO and Independent Clocks Built-in FIFO configurations for UltraScale Devices
* Added 'sleep' input port for Common Clock Built-in FIFO and Independent Clocks Built-in FIFO configurations only for UltraScale Devices
* Internal device family name change, no functional changes
2013.4:
* Version 11.0 (Rev. 1)
* Added support for Ultrascale devices
* Common Clock Builtin FIFO is set as default implementation type only for UltraScale devices
* Embedded Register option is always ON for Block RAM and Builtin FIFOs only for UltraScale devices
* Reset is sampled with respect to wr_clk/clk and then synchronized before the use in FIFO Generator only for UltraScale devices
2013.3:
* Version 11.0
* AXI ID Tags (s_axi_wid and m_axi_wid) are now determined by AXI protocol type (AXI4, AXI3). When upgrading from previously released core, these signals will be removed when AXI_Type = AXI4_Full.
* AXI Lock signals (s_axi_awlock, m_axi_awlock, s_axi_arlock and m_axi_arlock) are now determined by AXI Protocol type (AXI4, AXI3). When upgrading from previously released core, these signals width will reduce from 2-bits to 1-bit when AXI_Type=AXI4_Full
* Removed restriction on packet size in AXI4 Stream FIFO mode. Now, the packet size can be up to FIFO depth
* Enhanced support for IP Integrator
* Reduced warnings in synthesis and simulation
* Added support for Cadence IES and Synopsys VCS simulators
* Improved GUI speed and responsiveness, no functional changes
* Increased the maximum number of synchronization stages from 4 to 8. The minimum FIFO depth is limited to 32 when number of synchronization stages is > 4
2013.2:
* Version 10.0 (Rev. 1)
* Constraints processing order changed
2013.1:
* Version 10.0
* Native Vivado Release
* There have been no functional or interface changes to this IP. The version number has changed to support unique versioning in Vivado starting with 2013.1.
(c) Copyright 2002 - 2024 Advanced Micro Devices, Inc. All rights reserved.
This file contains confidential and proprietary information
of AMD and is protected under U.S. and international copyright
and other intellectual property laws.
DISCLAIMER
This disclaimer is not a license and does not grant any
rights to the materials distributed herewith. Except as
otherwise provided in a valid license issued to you by
AMD, and to the maximum extent permitted by applicable
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
(2) AMD shall not be liable (whether in contract or tort,
including negligence, or under any other theory of
liability) for any loss or damage of any kind or nature
related to, arising under or in connection with these
materials, including for any direct, or any indirect,
special, incidental, or consequential loss or damage
(including loss of data, profits, goodwill, or any type of
loss or damage suffered as a result of any action brought
by a third party) even if such damage or loss was
reasonably foreseeable or AMD had been advised of the
possibility of the same.
CRITICAL APPLICATIONS
AMD products are not designed or intended to be fail-
safe, or for use in any application requiring fail-safe
performance, such as life-support or safety devices or
systems, Class III medical devices, nuclear facilities,
applications related to the deployment of airbags, or any
other applications that could lead to death, personal
injury, or severe property or environmental damage
(individually and collectively, "Critical
Applications"). Customer assumes the sole risk and
liability of any use of AMD products in Critical
Applications, subject only to applicable laws and
regulations governing limitations on product liability.
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
PART OF THIS FILE AT ALL TIMES.
cx9261a_demo_cmos_20240513/project_fix_dac.srcs/sources_1/ip/cx9261a_fifo/hdl/blk_mem_gen_v8_4_vhsyn_rfs.vhd
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cx9261a_demo_cmos_20240513/project_fix_dac.srcs/sources_1/ip/cx9261a_fifo/hdl/fifo_generator_v13_2_rfs.v
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// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of AMD and is protected under U.S. and international copyright
// and other intellectual property laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// AMD, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) AMD shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or AMD had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// AMD products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of AMD products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:fifo_generator:13.2
// IP Revision: 10
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module cx9261a_fifo (
wr_clk,
rd_clk,
din,
wr_en,
rd_en,
dout,
full,
empty
);
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME write_clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 write_clk CLK" *)
input wire wr_clk;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME read_clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 read_clk CLK" *)
input wire rd_clk;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA" *)
input wire [31 : 0] din;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN" *)
input wire wr_en;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN" *)
input wire rd_en;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA" *)
output wire [31 : 0] dout;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL" *)
output wire full;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY" *)
output wire empty;
fifo_generator_v13_2_10 #(
.C_COMMON_CLOCK(0),
.C_SELECT_XPM(0),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(6),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(32),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(32),
.C_ENABLE_RLOCS(0),
.C_FAMILY("zynq"),
.C_FULL_FLAGS_RST_VAL(0),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_INT_CLK(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(0),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(2),
.C_INIT_WR_PNTR_VAL(0),
.C_MEMORY_TYPE(2),
.C_MIF_FILE_NAME("BlankString"),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(1),
.C_PRELOAD_REGS(0),
.C_PRIM_FIFO_TYPE("512x36"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(2),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(3),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(61),
.C_PROG_FULL_THRESH_NEGATE_VAL(60),
.C_PROG_FULL_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(6),
.C_RD_DEPTH(64),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(6),
.C_UNDERFLOW_LOW(0),
.C_USE_DOUT_RST(0),
.C_USE_ECC(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_PIPELINE_REG(0),
.C_POWER_SAVING_MODE(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(6),
.C_WR_DEPTH(64),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(6),
.C_WR_RESPONSE_LATENCY(1),
.C_MSGON_VAL(1),
.C_ENABLE_RST_SYNC(1),
.C_EN_SAFETY_CKT(0),
.C_ERROR_INJECTION_TYPE(0),
.C_SYNCHRONIZER_STAGE(2),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_HAS_AXI_WR_CHANNEL(1),
.C_HAS_AXI_RD_CHANNEL(1),
.C_HAS_SLAVE_CE(0),
.C_HAS_MASTER_CE(0),
.C_ADD_NGC_CONSTRAINT(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(64),
.C_AXI_LEN_WIDTH(8),
.C_AXI_LOCK_WIDTH(1),
.C_HAS_AXI_ID(0),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_RUSER(0),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_HAS_AXIS_TDATA(1),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TUSER(1),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TKEEP(0),
.C_AXIS_TDATA_WIDTH(8),
.C_AXIS_TID_WIDTH(1),
.C_AXIS_TDEST_WIDTH(1),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(1),
.C_AXIS_TKEEP_WIDTH(1),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WRCH_TYPE(0),
.C_RACH_TYPE(0),
.C_RDCH_TYPE(0),
.C_AXIS_TYPE(0),
.C_IMPLEMENTATION_TYPE_WACH(1),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(1),
.C_IMPLEMENTATION_TYPE_RACH(1),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_PRIM_FIFO_TYPE_WACH("512x36"),
.C_PRIM_FIFO_TYPE_WDCH("1kx36"),
.C_PRIM_FIFO_TYPE_WRCH("512x36"),
.C_PRIM_FIFO_TYPE_RACH("512x36"),
.C_PRIM_FIFO_TYPE_RDCH("1kx36"),
.C_PRIM_FIFO_TYPE_AXIS("1kx18"),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_AXIS(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_DIN_WIDTH_WACH(1),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_AXIS(1),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_AXIS(1024),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_PROG_FULL_TYPE_WACH(0),
.C_PROG_FULL_TYPE_WDCH(0),
.C_PROG_FULL_TYPE_WRCH(0),
.C_PROG_FULL_TYPE_RACH(0),
.C_PROG_FULL_TYPE_RDCH(0),
.C_PROG_FULL_TYPE_AXIS(0),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_EMPTY_TYPE_WACH(0),
.C_PROG_EMPTY_TYPE_WDCH(0),
.C_PROG_EMPTY_TYPE_WRCH(0),
.C_PROG_EMPTY_TYPE_RACH(0),
.C_PROG_EMPTY_TYPE_RDCH(0),
.C_PROG_EMPTY_TYPE_AXIS(0),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_AXIS(0)
) inst (
.backup(1'D0),
.backup_marker(1'D0),
.clk(1'D0),
.rst(1'D0),
.srst(1'D0),
.wr_clk(wr_clk),
.wr_rst(1'D0),
.rd_clk(rd_clk),
.rd_rst(1'D0),
.din(din),
.wr_en(wr_en),
.rd_en(rd_en),
.prog_empty_thresh(6'B0),
.prog_empty_thresh_assert(6'B0),
.prog_empty_thresh_negate(6'B0),
.prog_full_thresh(6'B0),
.prog_full_thresh_assert(6'B0),
.prog_full_thresh_negate(6'B0),
.int_clk(1'D0),
.injectdbiterr(1'D0),
.injectsbiterr(1'D0),
.sleep(1'D0),
.dout(dout),
.full(full),
.almost_full(),
.wr_ack(),
.overflow(),
.empty(empty),
.almost_empty(),
.valid(),
.underflow(),
.data_count(),
.rd_data_count(),
.wr_data_count(),
.prog_full(),
.prog_empty(),
.sbiterr(),
.dbiterr(),
.wr_rst_busy(),
.rd_rst_busy(),
.m_aclk(1'D0),
.s_aclk(1'D0),
.s_aresetn(1'D0),
.m_aclk_en(1'D0),
.s_aclk_en(1'D0),
.s_axi_awid(1'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awlock(1'B0),
.s_axi_awcache(4'B0),
.s_axi_awprot(3'B0),
.s_axi_awqos(4'B0),
.s_axi_awregion(4'B0),
.s_axi_awuser(1'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wid(1'B0),
.s_axi_wdata(64'B0),
.s_axi_wstrb(8'B0),
.s_axi_wlast(1'D0),
.s_axi_wuser(1'B0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_buser(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.m_axi_awid(),
.m_axi_awaddr(),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(),
.m_axi_awqos(),
.m_axi_awregion(),
.m_axi_awuser(),
.m_axi_awvalid(),
.m_axi_awready(1'D0),
.m_axi_wid(),
.m_axi_wdata(),
.m_axi_wstrb(),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(),
.m_axi_wready(1'D0),
.m_axi_bid(1'B0),
.m_axi_bresp(2'B0),
.m_axi_buser(1'B0),
.m_axi_bvalid(1'D0),
.m_axi_bready(),
.s_axi_arid(1'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arlock(1'B0),
.s_axi_arcache(4'B0),
.s_axi_arprot(3'B0),
.s_axi_arqos(4'B0),
.s_axi_arregion(4'B0),
.s_axi_aruser(1'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_ruser(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.m_axi_arid(),
.m_axi_araddr(),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(),
.m_axi_arqos(),
.m_axi_arregion(),
.m_axi_aruser(),
.m_axi_arvalid(),
.m_axi_arready(1'D0),
.m_axi_rid(1'B0),
.m_axi_rdata(64'B0),
.m_axi_rresp(2'B0),
.m_axi_rlast(1'D0),
.m_axi_ruser(1'B0),
.m_axi_rvalid(1'D0),
.m_axi_rready(),
.s_axis_tvalid(1'D0),
.s_axis_tready(),
.s_axis_tdata(8'B0),
.s_axis_tstrb(1'B0),
.s_axis_tkeep(1'B0),
.s_axis_tlast(1'D0),
.s_axis_tid(1'B0),
.s_axis_tdest(1'B0),
.s_axis_tuser(4'B0),
.m_axis_tvalid(),
.m_axis_tready(1'D0),
.m_axis_tdata(),
.m_axis_tstrb(),
.m_axis_tkeep(),
.m_axis_tlast(),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(),
.axi_aw_injectsbiterr(1'D0),
.axi_aw_injectdbiterr(1'D0),
.axi_aw_prog_full_thresh(4'B0),
.axi_aw_prog_empty_thresh(4'B0),
.axi_aw_data_count(),
.axi_aw_wr_data_count(),
.axi_aw_rd_data_count(),
.axi_aw_sbiterr(),
.axi_aw_dbiterr(),
.axi_aw_overflow(),
.axi_aw_underflow(),
.axi_aw_prog_full(),
.axi_aw_prog_empty(),
.axi_w_injectsbiterr(1'D0),
.axi_w_injectdbiterr(1'D0),
.axi_w_prog_full_thresh(10'B0),
.axi_w_prog_empty_thresh(10'B0),
.axi_w_data_count(),
.axi_w_wr_data_count(),
.axi_w_rd_data_count(),
.axi_w_sbiterr(),
.axi_w_dbiterr(),
.axi_w_overflow(),
.axi_w_underflow(),
.axi_w_prog_full(),
.axi_w_prog_empty(),
.axi_b_injectsbiterr(1'D0),
.axi_b_injectdbiterr(1'D0),
.axi_b_prog_full_thresh(4'B0),
.axi_b_prog_empty_thresh(4'B0),
.axi_b_data_count(),
.axi_b_wr_data_count(),
.axi_b_rd_data_count(),
.axi_b_sbiterr(),
.axi_b_dbiterr(),
.axi_b_overflow(),
.axi_b_underflow(),
.axi_b_prog_full(),
.axi_b_prog_empty(),
.axi_ar_injectsbiterr(1'D0),
.axi_ar_injectdbiterr(1'D0),
.axi_ar_prog_full_thresh(4'B0),
.axi_ar_prog_empty_thresh(4'B0),
.axi_ar_data_count(),
.axi_ar_wr_data_count(),
.axi_ar_rd_data_count(),
.axi_ar_sbiterr(),
.axi_ar_dbiterr(),
.axi_ar_overflow(),
.axi_ar_underflow(),
.axi_ar_prog_full(),
.axi_ar_prog_empty(),
.axi_r_injectsbiterr(1'D0),
.axi_r_injectdbiterr(1'D0),
.axi_r_prog_full_thresh(10'B0),
.axi_r_prog_empty_thresh(10'B0),
.axi_r_data_count(),
.axi_r_wr_data_count(),
.axi_r_rd_data_count(),
.axi_r_sbiterr(),
.axi_r_dbiterr(),
.axi_r_overflow(),
.axi_r_underflow(),
.axi_r_prog_full(),
.axi_r_prog_empty(),
.axis_injectsbiterr(1'D0),
.axis_injectdbiterr(1'D0),
.axis_prog_full_thresh(10'B0),
.axis_prog_empty_thresh(10'B0),
.axis_data_count(),
.axis_wr_data_count(),
.axis_rd_data_count(),
.axis_sbiterr(),
.axis_dbiterr(),
.axis_overflow(),
.axis_underflow(),
.axis_prog_full(),
.axis_prog_empty()
);
endmodule
cx9261a_demo_cmos_20240513/project_fix_dac.srcs/sources_1/ip/cx9261a_fifo/simulation/fifo_generator_vlog_beh.v
Executable
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cx9261a_demo_cmos_20240513/project_fix_dac.srcs/sources_1/ip/cx9261a_fifo/synth/cx9261a_fifo.vhd
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-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of AMD and is protected under U.S. and international copyright
-- and other intellectual property laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- AMD, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) AMD shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or AMD had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- AMD products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of AMD products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:13.2
-- IP Revision: 10
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v13_2_10;
USE fifo_generator_v13_2_10.fifo_generator_v13_2_10;
ENTITY cx9261a_fifo IS
PORT (
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END cx9261a_fifo;
ARCHITECTURE cx9261a_fifo_arch OF cx9261a_fifo IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF cx9261a_fifo_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v13_2_10 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_SELECT_XPM : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v13_2_10;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF cx9261a_fifo_arch: ARCHITECTURE IS "fifo_generator_v13_2_10,Vivado 2024.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF cx9261a_fifo_arch : ARCHITECTURE IS "cx9261a_fifo,fifo_generator_v13_2_10,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF cx9261a_fifo_arch: ARCHITECTURE IS "cx9261a_fifo,fifo_generator_v13_2_10,{x_ipProduct=Vivado 2024.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=13.2,x_ipCoreRevision=10,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=0,C_SELECT_XPM=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=6,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=32,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=32,C_ENABLE_RLOCS=0,C_FAMILY=zynq,C_FULL_FLAGS_RST_VAL=0,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_" &
"MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=0,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=2,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=2,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=1,C_PRELOAD_REGS=0,C_PRIM_FIFO_TYPE=512x36,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=61,C_PROG_FULL_TH" &
"RESH_NEGATE_VAL=60,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=6,C_RD_DEPTH=64,C_RD_FREQ=1,C_RD_PNTR_WIDTH=6,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=0,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=6,C_WR_DEPTH=64,C_WR_FREQ=1,C_WR_PNTR_WIDTH=6,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_EN_SAFETY_CKT=0,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=" &
"0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HA" &
"S_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1," &
"C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJE" &
"CTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=1,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNT" &
"R_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG" &
"_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RA" &
"CH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
ATTRIBUTE X_INTERFACE_PARAMETER OF rd_clk: SIGNAL IS "XIL_INTERFACENAME read_clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF rd_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 read_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
ATTRIBUTE X_INTERFACE_PARAMETER OF wr_clk: SIGNAL IS "XIL_INTERFACENAME write_clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF wr_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 write_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
BEGIN
U0 : fifo_generator_v13_2_10
GENERIC MAP (
C_COMMON_CLOCK => 0,
C_SELECT_XPM => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 6,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 32,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 32,
C_ENABLE_RLOCS => 0,
C_FAMILY => "zynq",
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 0,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 2,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 2,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 1,
C_PRELOAD_REGS => 0,
C_PRIM_FIFO_TYPE => "512x36",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 61,
C_PROG_FULL_THRESH_NEGATE_VAL => 60,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 6,
C_RD_DEPTH => 64,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 6,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 0,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 6,
C_WR_DEPTH => 64,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 6,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 0,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 1,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => '0',
rst => '0',
srst => '0',
wr_clk => wr_clk,
wr_rst => '0',
rd_clk => rd_clk,
rd_rst => '0',
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
empty => empty,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END cx9261a_fifo_arch;
cx9261a_demo_cmos_20240513/project_fix_dac.srcs/sources_1/ip/hrc_128_12_03/cmodel/fir_compiler_v7_2_bitacc_cmodel_lin64.zip
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cx9261a_demo_cmos_20240513/project_fix_dac.srcs/sources_1/ip/hrc_128_12_03/cmodel/fir_compiler_v7_2_bitacc_cmodel_nt64.zip
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//-----------------------------------------------------------------------------
// (c) Copyright 2014 2023 Advanced Micro Devices, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of AMD, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// AMD, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) AMD shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or AMD had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// AMD products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of AMD products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
// C testbench for the "hrc_128_12_03" instance
// o Basic C testbench based on the run_bitacc_cmodel.c smoke test program
// included in the C model zip files. Please refer run_bitacc_cmodel.c
// for further examples of how to use the FIR Compiler C model.
// o Unzip the appropriate platform specifc zip file and use the following example
// command line to compile and link this TB:
// gcc -x c++ -I. -L. -lIp_fir_compiler_v7_2_22_bitacc_cmodel -Wl,-rpath,. -o tb_hrc_128_12_03 tb_hrc_128_12_03.c
#include <stdio.h>
#include "fir_compiler_v7_2_bitacc_cmodel.h"
#include "hrc_128_12_03.h"
//---------------------------------------------------------------------------------------------------------------------
// Example message handler
static void msg_print(void* handle, int error, const char* msg)
{
printf("%s\n",msg);
}
//---------------------------------------------------------------------------------------------------------------------
//Print a xip_array_real
void print_array_real(const xip_array_real* x)
{
putchar('[');
if (x && x->data && x->data_size)
{
const xip_real* p=x->data;
const xip_real* q=x->data;
const xip_real* r=x->data+x->data_size;
while (q!=r)
{
if (q!=p) putchar(' ');
printf("%g",*q);
q++;
}
}
putchar(']');
putchar('\n');
}
//----------------------------------------------------------------------------------------------------------------------
// Fill data array with a scaled impulse. Assumes 3-D array.
int create_impulse(xip_array_real* x) {
int path;
int chan;
int i;
for (path = 0; path < x->dim[0];path++) {
for (chan = 0; chan < x->dim[1];chan++) {
xip_fir_v7_2_xip_array_real_set_chan(x,(double)((path+1)*(chan+1)),path,chan,0,P_BASIC);
for (i = 1; i < x->dim[2];i++) {
xip_fir_v7_2_xip_array_real_set_chan(x,0,path,chan,i,P_BASIC);
}
}
}
return 0;
}
//----------------------------------------------------------------------------------------------------------------------
// String arrays used by the print_config funtion
const char *filt_desc[5] = { "SINGLE RATE", "INTERPOLATION", "DECIMATION", "HILBERT", "INTERPOLATED" };
const char *seq_desc[2] = { "Basic" , "Advanced" };
//----------------------------------------------------------------------------------------------------------------------
// Print a summary of a filter configuration
int print_config(const xip_fir_v7_2_config* cfg) {
printf("Configuration of %s:\n",cfg->name);
printf("\tFilter : ");
if ( cfg->filter_type == XIP_FIR_SINGLE_RATE || cfg->filter_type == XIP_FIR_HILBERT ) {
printf("%s\n",filt_desc[cfg->filter_type]);
} else if ( cfg->filter_type == XIP_FIR_INTERPOLATED ) {
printf("%s by %d\n",filt_desc[cfg->filter_type],cfg->zero_pack_factor);
} else {
printf("%s up by %d down by %d\n",filt_desc[cfg->filter_type],cfg->interp_rate,cfg->decim_rate);
}
printf("\tCoefficients : %d ",cfg->coeff_sets);
if ( cfg->is_halfband ) {
printf("Halfband ");
}
if (cfg->reloadable) {
printf("Reloadable ");
}
printf("coefficient set(s) of %d taps\n",cfg->num_coeffs);
printf("\tData : %d path(s) of %d %s channel(s)\n",cfg->num_paths,cfg->num_channels,seq_desc[cfg->chan_seq]);
return 0;
}
//----------------------------------------------------------------------------------------------------------------------
int main () {
const char* ver_str = xip_fir_v7_2_get_version();
printf("FIR Compiler C Model version: %s\n",ver_str);
print_config(&hrc_128_12_03_config);
//Create filter instances
xip_fir_v7_2* hrc_128_12_03_inst = xip_fir_v7_2_create(&hrc_128_12_03_config,&msg_print,0);
if (!hrc_128_12_03_inst) {
printf("Error creating instance\n",hrc_128_12_03_config.name);
return -1;
} else {
printf("Created instance\n",hrc_128_12_03_config.name);
}
// Create input data packet
xip_array_real* din = xip_array_real_create();
xip_array_real_reserve_dim(din,3);
din->dim_size = 3; // 3D array
din->dim[0] = hrc_128_12_03_config.num_paths;
din->dim[1] = hrc_128_12_03_config.num_channels;
din->dim[2] = hrc_128_12_03_config.num_coeffs; // vectors in a single packet
din->data_size = din->dim[0] * din->dim[1] * din->dim[2];
if (xip_array_real_reserve_data(din,din->data_size) == XIP_STATUS_OK) {
printf("Reserved data\n");
} else {
printf("Unable to reserve data!\n");
return -1;
}
// Create output data packet
// - Automatically sized using xip_fir_v7_2_calc_size
xip_array_real* dout = xip_array_real_create();
xip_array_real_reserve_dim(dout,3);
dout->dim_size = 3; // 3D array
if(xip_fir_v7_2_calc_size(hrc_128_12_03_inst,din,dout,0)== XIP_STATUS_OK) {
printf("Calculated output data size\n");
if (xip_array_real_reserve_data(dout,dout->data_size) == XIP_STATUS_OK) {
printf("Reserved data\n");
} else {
printf("Unable to reserve data!\n");
return -1;
}
} else {
printf("Unable to calculate output date size\n");
return -1;
}
// Populate data in with an impulse
printf("Create impulse\n");
create_impulse(din);
// Send input data and filter
if ( xip_fir_v7_2_data_send(hrc_128_12_03_inst,din)== XIP_STATUS_OK) {
printf("Sent data : ");
print_array_real(din);
} else {
printf("Error sending data\n");
return -1;
}
// Retrieve filtered data
if ( xip_fir_v7_2_data_get(hrc_128_12_03_inst,dout,0)== XIP_STATUS_OK) {
printf("Fetched result: ");
print_array_real(dout);
} else {
printf("Error getting data\n");
return -1;
}
}
cx9261a_demo_cmos_20240513/project_fix_dac.srcs/sources_1/ip/hrc_128_12_03/constraints/fir_compiler_v7_2.xdc
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# (c) Copyright 2023 Advanced Micro Devices, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of AMD and is protected under U.S. and international copyright
# and other intellectual property laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# AMD, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) AMD shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or AMD had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# AMD products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of AMD products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
############################################################
set_property -quiet SIM_COLLISION_CHECK GENERATE_X_ONLY [get_cells -quiet -hierarchical -filter {IS_PRIMITIVE && (TYPE=="Block Memory" || TYPE=="Block Ram" || TYPE=="BLOCKRAM")}]
cx9261a_demo_cmos_20240513/project_fix_dac.srcs/sources_1/ip/hrc_128_12_03/demo_tb/tb_hrc_128_12_03.vhd
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--------------------------------------------------------------------------------
-- (c) Copyright 2011 - 2013 2023 Advanced Micro Devices, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of AMD, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- AMD, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) AMD shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or AMD had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- AMD products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of AMD products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Description:
-- This is an example testbench for the FIR Compiler IP core.
-- The testbench has been generated by Vivado to accompany the IP core
-- instance you have generated.
--
-- This testbench is for demonstration purposes only. See note below for
-- instructions on how to use it with your core.
--
-- See the FIR Compiler product guide for further information
-- about this core.
--
--------------------------------------------------------------------------------
-- Using this testbench
--
-- This testbench instantiates your generated FIR Compiler core
-- instance named "hrc_128_12_03".
--
-- Use Vivado's Run Simulation flow to run this testbench. See the Vivado
-- documentation for details.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_hrc_128_12_03 is
end tb_hrc_128_12_03;
architecture tb of tb_hrc_128_12_03 is
-----------------------------------------------------------------------
-- Timing constants
-----------------------------------------------------------------------
constant CLOCK_PERIOD : time := 100 ns;
constant T_HOLD : time := 10 ns;
constant T_STROBE : time := CLOCK_PERIOD - (1 ns);
-----------------------------------------------------------------------
-- DUT signals
-----------------------------------------------------------------------
-- General signals
signal aclk : std_logic := '0'; -- the master clock
-- Data slave channel signals
signal s_axis_data_tvalid : std_logic := '0'; -- payload is valid
signal s_axis_data_tready : std_logic := '1'; -- slave is ready
signal s_axis_data_tdata : std_logic_vector(7 downto 0) := (others => '0'); -- data payload
-- Data master channel signals
signal m_axis_data_tvalid : std_logic := '0'; -- payload is valid
signal m_axis_data_tdata : std_logic_vector(23 downto 0) := (others => '0'); -- data payload
-----------------------------------------------------------------------
-- Aliases for AXI channel TDATA and TUSER fields
-- These are a convenience for viewing data in a simulator waveform viewer.
-- If using ModelSim or Questa, add "-voptargs=+acc=n" to the vsim command
-- to prevent the simulator optimizing away these signals.
-----------------------------------------------------------------------
-- Data slave channel alias signals
signal s_axis_data_tdata_data : std_logic_vector(1 downto 0) := (others => '0');
-- Data master channel alias signals
signal m_axis_data_tdata_data : std_logic_vector(17 downto 0) := (others => '0');
begin
-----------------------------------------------------------------------
-- Instantiate the DUT
-----------------------------------------------------------------------
dut : entity work.hrc_128_12_03
port map (
aclk => aclk,
s_axis_data_tvalid => s_axis_data_tvalid,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tdata => s_axis_data_tdata,
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tdata => m_axis_data_tdata
);
-----------------------------------------------------------------------
-- Generate clock
-----------------------------------------------------------------------
clock_gen : process
begin
aclk <= '0';
wait for CLOCK_PERIOD;
loop
aclk <= '0';
wait for CLOCK_PERIOD/2;
aclk <= '1';
wait for CLOCK_PERIOD/2;
end loop;
end process clock_gen;
-----------------------------------------------------------------------
-- Generate inputs
-----------------------------------------------------------------------
stimuli : process
-- Procedure to drive a number of input samples with specific data
-- data is the data value to drive on the tdata signal
-- samples is the number of zero-data input samples to drive
procedure drive_data ( data : std_logic_vector(7 downto 0);
samples : natural := 1 ) is
variable ip_count : integer := 0;
begin
ip_count := 0;
loop
s_axis_data_tvalid <= '1';
s_axis_data_tdata <= data;
loop
wait until rising_edge(aclk);
exit when s_axis_data_tready = '1';
end loop;
ip_count := ip_count + 1;
wait for T_HOLD;
-- Input rate is 1 input each 42 clock cycles: drive valid inputs at this rate
s_axis_data_tvalid <= '0';
wait for CLOCK_PERIOD * 41;
exit when ip_count >= samples;
end loop;
end procedure drive_data;
-- Procedure to drive a number of zero-data input samples
-- samples is the number of zero-data input samples to drive
procedure drive_zeros ( samples : natural := 1 ) is
begin
drive_data((others => '0'), samples);
end procedure drive_zeros;
-- Procedure to drive an impulse and let the impulse response emerge on the data master channel
-- samples is the number of input samples to drive; default is enough for impulse response output to emerge
procedure drive_impulse ( samples : natural := 1669 ) is
variable impulse : std_logic_vector(7 downto 0);
begin
impulse := (others => '0'); -- initialize unused bits to zero
impulse(1 downto 0) := "01";
drive_data(impulse);
if samples > 1 then
drive_zeros(samples-1);
end if;
end procedure drive_impulse;
begin
-- Drive inputs T_HOLD time after rising edge of clock
wait until rising_edge(aclk);
wait for T_HOLD;
-- Drive a single impulse and let the impulse response emerge
drive_impulse;
-- Drive another impulse, during which demonstrate use and effect of AXI handshaking signals
drive_impulse(2); -- start of impulse; data is now zero
s_axis_data_tvalid <= '0';
wait for CLOCK_PERIOD * 210; -- provide no data for 5 input samples worth
drive_zeros(2); -- 2 normal input samples
s_axis_data_tvalid <= '1';
wait for CLOCK_PERIOD * 210; -- provide data as fast as the core can accept it for 5 input samples worth
drive_zeros(1660); -- back to normal operation
-- End of test
report "Not a real failure. Simulation finished successfully. Test completed successfully" severity failure;
wait;
end process stimuli;
-----------------------------------------------------------------------
-- Check outputs
-----------------------------------------------------------------------
check_outputs : process
variable check_ok : boolean := true;
begin
-- Check outputs T_STROBE time after rising edge of clock
wait until rising_edge(aclk);
wait for T_STROBE;
-- Do not check the output payload values, as this requires the behavioral model
-- which would make this demonstration testbench unwieldy.
-- Instead, check the protocol of the master DATA channel:
-- check that the payload is valid (not X) when TVALID is high
if m_axis_data_tvalid = '1' then
if is_x(m_axis_data_tdata) then
report "ERROR: m_axis_data_tdata is invalid when m_axis_data_tvalid is high" severity error;
check_ok := false;
end if;
end if;
assert check_ok
report "ERROR: terminating test with failures." severity failure;
end process check_outputs;
-----------------------------------------------------------------------
-- Assign TDATA / TUSER fields to aliases, for easy simulator waveform viewing
-----------------------------------------------------------------------
-- Data slave channel alias signals
s_axis_data_tdata_data <= s_axis_data_tdata(1 downto 0);
-- Data master channel alias signals: update these only when they are valid
m_axis_data_tdata_data <= m_axis_data_tdata(17 downto 0) when m_axis_data_tvalid = '1';
end tb;
cx9261a_demo_cmos_20240513/project_fix_dac.srcs/sources_1/ip/hrc_128_12_03/doc/fir_compiler_v7_2_changelog.txt
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2024.1:
* Version 7.2 (Rev. 22)
* Bug Fix: Added Synplicity key
* Other: IP packaging adjustments to address warnings from IP Packager integrity check
* Revision change in one or more subcores
2023.2.2:
* Version 7.2 (Rev. 21)
* Revision change in one or more subcores
2023.2.1:
* Version 7.2 (Rev. 20)
* No changes
2023.2:
* Version 7.2 (Rev. 20)
* Bug Fix: Minor GUI fix to update Output Width range following a change in Coefficient Structure
* Bug Fix: Update half-band interpolation "power of 2" center tap optimization to support symmetric rounding
* Other: Rebrand to AMD copyright information
* Revision change in one or more subcores
2023.1.2:
* Version 7.2 (Rev. 19)
* No changes
2023.1.1:
* Version 7.2 (Rev. 19)
* No changes
2023.1:
* Version 7.2 (Rev. 19)
* General: Device support changes. No change to functionality or performance
2022.2.2:
* Version 7.2 (Rev. 18)
* No changes
2022.2.1:
* Version 7.2 (Rev. 18)
* No changes
2022.2:
* Version 7.2 (Rev. 18)
* No changes
2022.1.2:
* Version 7.2 (Rev. 18)
* No changes
2022.1.1:
* Version 7.2 (Rev. 18)
* No changes
2022.1:
* Version 7.2 (Rev. 18)
* Feature Enhancement: C model MEX wrapper updates to support Octave
2021.2.2:
* Version 7.2 (Rev. 17)
* No changes
2021.2.1:
* Version 7.2 (Rev. 17)
* No changes
2021.2:
* Version 7.2 (Rev. 17)
* Bug Fix: Fixed convergent rounding bug for symmetric polyphase decimators
2021.1.1:
* Version 7.2 (Rev. 16)
* No changes
2021.1:
* Version 7.2 (Rev. 16)
* Bug Fix: Fixed width mismatch issue with SSR single rate extended multiply reload configs
* Other: testbench and constraints updates
2020.3:
* Version 7.2 (Rev. 15)
* No changes
2020.2.2:
* Version 7.2 (Rev. 15)
* No changes
2020.2.1:
* Version 7.2 (Rev. 15)
* No changes
2020.2:
* Version 7.2 (Rev. 15)
* Bug Fix: Fixed incorrect application of symmetry when Interpolation_Rate > clk_freq/samp_freq > 1
* Feature Enhancement: Improved GUI error reporting for designs that don't fit within selected device.
* Other: Windows C model compilation now uses Visual Studio 2017
2020.1.1:
* Version 7.2 (Rev. 14)
* No changes
2020.1:
* Version 7.2 (Rev. 14)
* Bug Fix: Fixed bug with coefficient reload file.
* Bug Fix: Improved error trapping behaviour in the GUI.
* Bug Fix: Fixed simulator specific bug
* Feature Enhancement: Extended Symmetric Coefficient Structures for Interpolation and Decimation Filters with Super Sample Rate.
* Feature Enhancement: Improved the GUI for selecting optimizations.
2019.2.2:
* Version 7.2 (Rev. 13)
* No changes
2019.2.1:
* Version 7.2 (Rev. 13)
* No changes
2019.2:
* Version 7.2 (Rev. 13)
* General: Improved efficiency to C model output. No change to functionality.
2019.1.3:
* Version 7.2 (Rev. 12)
* No changes
2019.1.2:
* Version 7.2 (Rev. 12)
* No changes
2019.1.1:
* Version 7.2 (Rev. 12)
* No changes
2019.1:
* Version 7.2 (Rev. 12)
* Bug Fix: Addressing memory leak in MEX wrapper.
* Bug Fix: Fixed coefficient width range minimum for coefficient file input.
* Bug Fix: Fixed upper bound of Sample Frequency when Advanced Channel Sequence is selected.
* Bug Fix: Fixed C model crash when multiple DSP IP C models are run together: AR 71876
* Other: Support for new devices. No change to exisiting functionality, resource use or performance.
* Revision change in one or more subcores
2018.3.1:
* Version 7.2 (Rev. 11)
* No changes
2018.3:
* Version 7.2 (Rev. 11)
* No changes
2018.2:
* Version 7.2 (Rev. 11)
* No changes
2018.1:
* Version 7.2 (Rev. 11)
* Revision change in one or more subcores
2017.4:
* Version 7.2 (Rev. 10)
* Feature Enhancement: Add option to remove shift register inference attributes; SHREG_EXTRACT and SRL_STYLE
2017.3:
* Version 7.2 (Rev. 9)
* Feature Enhancement: Increase the maximum number of parallel inputs from 64 to 256
* Revision change in one or more subcores
2017.2:
* Version 7.2 (Rev. 8)
* No changes
2017.1:
* Version 7.2 (Rev. 8)
* Bug Fix: Output Rounding Mode parameter validation corrected to produce an error during design validation (IP Integrator/System Generator) rather than silently updating to a legal value.
* Bug Fix: Correction to Convergent Rounding when multiple DSP slices are required to implement the filter multiply operations.
2016.4:
* Version 7.2 (Rev. 7)
* No changes
2016.3:
* Version 7.2 (Rev. 7)
* General: Support for Spartan7 devices
* Revision change in one or more subcores
2016.2:
* Version 7.2 (Rev. 6)
* No changes
2016.1:
* Version 7.2 (Rev. 6)
* Fix for error in Sysgen parameter propagation.
* Enabled DSP48 ADREG/DREG but gate CEAD/CED to address power DRC.
* Fix in common c model utilities package for handling of arrays of real types in Matlab
* Revision change in one or more subcores
2015.4.2:
* Version 7.2 (Rev. 5)
* No changes
2015.4.1:
* Version 7.2 (Rev. 5)
* No changes
2015.4:
* Version 7.2 (Rev. 5)
* Correction to GUI reported Calculated Coefficients for Transpose Interpolation filters.
* Revision change in one or more subcores
2015.3:
* Version 7.2 (Rev. 4)
* Add constraints file to suppress expected memory collision warnings during post-synthesis simulation.
* IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances
* Correction to GUI reported latency estimate for polyphase interpolation configurations.
* Revision change in one or more subcores
2015.2.1:
* Version 7.2 (Rev. 3)
* No changes
2015.2:
* Version 7.2 (Rev. 3)
* Correction to the GUI reported startup latency for polyphase interpolation configurations.
* Correction for Halfband Decimation with Symmetric rounding on Ultrascale parts.
* Correction for Polyphase Interpolation with Convergent rounding where multiple DSP columns are required to support the data and/or coefficient width.
2015.1:
* Version 7.2 (Rev. 2)
* Warning reduction.
* Correction to single rate half-band control for data vector reset, an oversample rate of 2, utilizing a single multiply add unit.
* Added the SRL_STYLE attribute to the delay component to ensure an efficient implementation.
* Fix to Sample Period propagation to avoid false Column Configuration errors.
* GUI filter coefficient processing speed up for bit widths greater than DSP48 input width.
* Addition of Beta support for future devices
* Correction to fractional interpolation configurations utilizing Maximium Possible hardware oversampling specification in System Generator.
* Update to C model to match GUI behaviour. Add support for quantization/truncation of integer only coefficients when XIP_FIR_QUANTIZED_ONLY has been specified.
* Supported devices and production status are now determined automatically, to simplify support for future devices
* C models are no longer provided for 32-bit operating systems as Vivado has deprecated 32-bit OS support
2014.4.1:
* Version 7.2 (Rev. 1)
* No changes
2014.4:
* Version 7.2 (Rev. 1)
* Fix for UltraScale Halfband Interpolation optimization with Convergent Rounding and multiple parallel paths.
* C Model maximum data and coefficient widths updated for UltraScale.
* Correction to GUI latency calculation.
* Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
* Add 1 x fs Advanced Channel Sequence to sequence length 24.
* Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interface aclk_intf
2014.3:
* Version 7.2
* Optimized Halfband filter support for UltraScale devices.
* Super sample rate support.
* Enhanced Hardware Oversampling specification methods. Now supports input and output sample period specification.
* CONFIG channel behavior has been updated for the Packet Synchronization method (On Packet) following power up or reset.
2014.2:
* Version 7.1 (Rev. 4)
* Removed component statement for DSP48E2, no functional changes
2014.1:
* Version 7.1 (Rev. 3)
* C models for Windows are compiled using Microsoft Visual Studio 2012
* Internal device family name change, no functional changes
* Netlists created by write_verilog and write_vhdl are IEEE P1735 encrypted, with keys for supported simulators so that netlist simulation can still be done
* Enable third party synthesis tools to read encrypted netlists (but not source HDL)
* Fixed AR58946, COE file coefficient specification now working correctly in IP Integrator.
* Support for Virtex Ultrascale devices at Pre-Production Status
2013.4:
* Version 7.1 (Rev. 2)
* Added workaround to the GUI for AR57785
* Support for Kintex Ultrascale devices at Pre-Production Status
2013.3:
* Version 7.1 (Rev. 1)
* Behavioral VHDL model replaced by Encrypted RTL. For more information on this change please refer to the Migrating and Upgrading section in the Product Guide
* Internal standardization in source file delivery, does not change behavior
* Support for Automotive Artix-7, Automotive Zynq, Defense Grade Artix-7, Defense Grade Zynq and Lower Power Artix-7 devices at Production Status
* Added default constraints for out of context flow
* Optimized support for UltraScale devices
* Added support for Cadence IES and Synopsys VCS simulators
* Removed C model dependency on stlport (STL Portability) library; C model now uses STL built into the compiler
* Windows C model DLLs are statically linked to the Windows C run-time (CRT) library, to remove the runtime dependency on MSVCRT90.dll, which can cause problems when using the C model in a Windows compiler other than Visual Studio 2008
* C model updated to use third-party library MPIR version 2.6.0 (previously was version 2.2.1); the Windows MPIR DLLs are also statically linked to the Windows CRT library, to remove the dependency on MSVCRT90.dll
2013.2:
* Version 7.1
* Support for Series 7 devices at Production status
* Beta support for future devices
* Enhanced Optimization specification including optional use of Block RAM READ-FIRST mode
* Maximum interleaved channels increased to 1024
* Bug Fixes
2013.1:
* Version 7.0
* Native Vivado Release
* There have been no functional or interface changes to this IP. The version number has changed to support unique versioning in Vivado starting with 2013.1.
(c) Copyright 2002 - 2024 Advanced Micro Devices, Inc. All rights reserved.
This file contains confidential and proprietary information
of AMD and is protected under U.S. and international copyright
and other intellectual property laws.
DISCLAIMER
This disclaimer is not a license and does not grant any
rights to the materials distributed herewith. Except as
otherwise provided in a valid license issued to you by
AMD, and to the maximum extent permitted by applicable
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
(2) AMD shall not be liable (whether in contract or tort,
including negligence, or under any other theory of
liability) for any loss or damage of any kind or nature
related to, arising under or in connection with these
materials, including for any direct, or any indirect,
special, incidental, or consequential loss or damage
(including loss of data, profits, goodwill, or any type of
loss or damage suffered as a result of any action brought
by a third party) even if such damage or loss was
reasonably foreseeable or AMD had been advised of the
possibility of the same.
CRITICAL APPLICATIONS
AMD products are not designed or intended to be fail-
safe, or for use in any application requiring fail-safe
performance, such as life-support or safety devices or
systems, Class III medical devices, nuclear facilities,
applications related to the deployment of airbags, or any
other applications that could lead to death, personal
injury, or severe property or environmental damage
(individually and collectively, "Critical
Applications"). Customer assumes the sole risk and
liability of any use of AMD products in Critical
Applications, subject only to applicable laws and
regulations governing limitations on product liability.
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
PART OF THIS FILE AT ALL TIMES.
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// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of AMD and is protected under U.S. and international copyright
// and other intellectual property laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// AMD, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) AMD shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or AMD had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// AMD products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of AMD products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:fir_compiler:7.2
// IP Revision: 22
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
hrc_128_12_03 your_instance_name (
.aclk(aclk), // input wire aclk
.s_axis_data_tvalid(s_axis_data_tvalid), // input wire s_axis_data_tvalid
.s_axis_data_tready(s_axis_data_tready), // output wire s_axis_data_tready
.s_axis_data_tdata(s_axis_data_tdata), // input wire [7 : 0] s_axis_data_tdata
.m_axis_data_tvalid(m_axis_data_tvalid), // output wire m_axis_data_tvalid
.m_axis_data_tdata(m_axis_data_tdata) // output wire [23 : 0] m_axis_data_tdata
);
// INST_TAG_END ------ End INSTANTIATION Template ---------
// You must compile the wrapper file hrc_128_12_03.v when simulating
// the core, hrc_128_12_03. When compiling the wrapper file, be sure to
// reference the Verilog simulation library.
cx9261a_demo_cmos_20240513/project_fix_dac.srcs/sources_1/ip/hrc_128_12_03/hrc_128_12_03.vho
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-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of AMD and is protected under U.S. and international copyright
-- and other intellectual property laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- AMD, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) AMD shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or AMD had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- AMD products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of AMD products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fir_compiler:7.2
-- IP Revision: 22
-- The following code must appear in the VHDL architecture header.
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
COMPONENT hrc_128_12_03
PORT (
aclk : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END COMPONENT;
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
-- The following code must appear in the VHDL architecture
-- body. Substitute your own instance name and net names.
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
your_instance_name : hrc_128_12_03
PORT MAP (
aclk => aclk,
s_axis_data_tvalid => s_axis_data_tvalid,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tdata => s_axis_data_tdata,
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tdata => m_axis_data_tdata
);
-- INST_TAG_END ------ End INSTANTIATION Template ---------
-- You must compile the wrapper file hrc_128_12_03.vhd when simulating
-- the core, hrc_128_12_03. When compiling the wrapper file, be sure to
-- reference the VHDL simulation library.
cx9261a_demo_cmos_20240513/project_fix_dac.srcs/sources_1/ip/hrc_128_12_03/hrc_128_12_03.xci
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{
"schema": "xilinx.com:schema:json_instance:1.0",
"ip_inst": {
"xci_name": "hrc_128_12_03",
"component_reference": "xilinx.com:ip:fir_compiler:7.2",
"ip_revision": "22",
"gen_directory": ".",
"parameters": {
"component_parameters": {
"Component_Name": [ { "value": "hrc_128_12_03", "resolve_type": "user", "usage": "all" } ],
"GUI_Behaviour": [ { "value": "Coregen", "resolve_type": "user", "usage": "all" } ],
"CoefficientSource": [ { "value": "COE_File", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"CoefficientVector": [ { "value": "6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6", "resolve_type": "user", "usage": "all" } ],
"Coefficient_File": [ { "value": "../coe/hrc_128_12_03.coe", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"Coefficient_Sets": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Coefficient_Reload": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Filter_Type": [ { "value": "Interpolation", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"Rate_Change_Type": [ { "value": "Fixed_Fractional", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"Interpolation_Rate": [ { "value": "128", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Decimation_Rate": [ { "value": "3", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Zero_Pack_Factor": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Channel_Sequence": [ { "value": "Basic", "resolve_type": "user", "usage": "all" } ],
"Number_Channels": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Select_Pattern": [ { "value": "All", "resolve_type": "user", "usage": "all" } ],
"Pattern_List": [ { "value": "P4-0,P4-1,P4-2,P4-3,P4-4", "resolve_type": "user", "usage": "all" } ],
"Number_Paths": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"RateSpecification": [ { "value": "Frequency_Specification", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"HardwareOversamplingRate": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"SamplePeriod": [ { "value": "1", "resolve_type": "user", "format": "float", "usage": "all" } ],
"Sample_Frequency": [ { "value": "1.5", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"Clock_Frequency": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"Coefficient_Sign": [ { "value": "Signed", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"Quantization": [ { "value": "Integer_Coefficients", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"Coefficient_Width": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"BestPrecision": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Coefficient_Fractional_Bits": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Coefficient_Structure": [ { "value": "Non_Symmetric", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"Data_Sign": [ { "value": "Signed", "resolve_type": "user", "usage": "all" } ],
"Data_Width": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Data_Fractional_Bits": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Output_Rounding_Mode": [ { "value": "Full_Precision", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"Output_Width": [ { "value": "18", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Filter_Architecture": [ { "value": "Systolic_Multiply_Accumulate", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"Optimization_Goal": [ { "value": "Area", "resolve_type": "user", "usage": "all" } ],
"Optimization_Selection": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
"Data_Path_Fanout": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Pre_Adder_Pipeline": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Coefficient_Fanout": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Control_Path_Fanout": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Control_Column_Fanout": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Control_Broadcast_Fanout": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Control_LUT_Pipeline": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"No_BRAM_Read_First_Mode": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Optimal_Column_Lengths": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Data_Path_Broadcast": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Disable_Half_Band_Centre_Tap": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"No_SRL_Attributes": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Other": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Optimization_List": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
"Data_Buffer_Type": [ { "value": "Automatic", "resolve_type": "user", "usage": "all" } ],
"Coefficient_Buffer_Type": [ { "value": "Automatic", "resolve_type": "user", "usage": "all" } ],
"Input_Buffer_Type": [ { "value": "Automatic", "resolve_type": "user", "usage": "all" } ],
"Output_Buffer_Type": [ { "value": "Automatic", "resolve_type": "user", "usage": "all" } ],
"Preference_For_Other_Storage": [ { "value": "Automatic", "resolve_type": "user", "usage": "all" } ],
"Multi_Column_Support": [ { "value": "Automatic", "resolve_type": "user", "usage": "all" } ],
"Inter_Column_Pipe_Length": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
"ColumnConfig": [ { "value": "13", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"DATA_Has_TLAST": [ { "value": "Not_Required", "resolve_type": "user", "usage": "all" } ],
"M_DATA_Has_TREADY": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"S_DATA_Has_FIFO": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"S_DATA_Has_TUSER": [ { "value": "Not_Required", "resolve_type": "user", "usage": "all" } ],
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cx9261a_demo_cmos_20240513/project_fix_dac.srcs/sources_1/ip/hrc_128_12_03/hrc_128_12_03_ooc.xdc
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# (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
# (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of AMD and is protected under U.S. and international copyright
# and other intellectual property laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# AMD, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) AMD shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or AMD had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# AMD products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of AMD products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#
# DO NOT MODIFY THIS FILE.
# #########################################################
#
# This XDC is used only in OOC mode for synthesis, implementation
#
# #########################################################
create_clock -period 10 -name aclk [get_ports aclk]
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// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
// Date : Fri Nov 1 13:04:12 2024
// Host : gatsby-dev running 64-bit Red Hat Enterprise Linux release 8.10 (Ootpa)
// Command : write_verilog -force -mode synth_stub
// /home/josh/Workspace/vivado/brd_cx2161a/zc706_cx9261a_demo/zc706_cx9261a_demo.gen/sources_1/ip/hrc_128_12_03/hrc_128_12_03_stub.v
// Design : hrc_128_12_03
// Purpose : Stub declaration of top-level module interface
// Device : xc7z045ffg900-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "fir_compiler_v7_2_22,Vivado 2024.1" *)
module hrc_128_12_03(aclk, s_axis_data_tvalid, s_axis_data_tready,
s_axis_data_tdata, m_axis_data_tvalid, m_axis_data_tdata)
/* synthesis syn_black_box black_box_pad_pin="s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[7:0],m_axis_data_tvalid,m_axis_data_tdata[23:0]" */
/* synthesis syn_force_seq_prim="aclk" */;
input aclk /* synthesis syn_isclock = 1 */;
input s_axis_data_tvalid;
output s_axis_data_tready;
input [7:0]s_axis_data_tdata;
output m_axis_data_tvalid;
output [23:0]m_axis_data_tdata;
endmodule
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-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
-- Date : Fri Nov 1 13:04:12 2024
-- Host : gatsby-dev running 64-bit Red Hat Enterprise Linux release 8.10 (Ootpa)
-- Command : write_vhdl -force -mode synth_stub
-- /home/josh/Workspace/vivado/brd_cx2161a/zc706_cx9261a_demo/zc706_cx9261a_demo.gen/sources_1/ip/hrc_128_12_03/hrc_128_12_03_stub.vhdl
-- Design : hrc_128_12_03
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z045ffg900-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity hrc_128_12_03 is
Port (
aclk : in STD_LOGIC;
s_axis_data_tvalid : in STD_LOGIC;
s_axis_data_tready : out STD_LOGIC;
s_axis_data_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_data_tvalid : out STD_LOGIC;
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
end hrc_128_12_03;
architecture stub of hrc_128_12_03 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[7:0],m_axis_data_tvalid,m_axis_data_tdata[23:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "fir_compiler_v7_2_22,Vivado 2024.1";
begin
end;
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-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of AMD and is protected under U.S. and international copyright
-- and other intellectual property laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- AMD, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) AMD shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or AMD had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- AMD products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of AMD products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fir_compiler:7.2
-- IP Revision: 22
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fir_compiler_v7_2_22;
USE fir_compiler_v7_2_22.fir_compiler_v7_2_22;
ENTITY hrc_128_12_03 IS
PORT (
aclk : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END hrc_128_12_03;
ARCHITECTURE hrc_128_12_03_arch OF hrc_128_12_03 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF hrc_128_12_03_arch: ARCHITECTURE IS "yes";
COMPONENT fir_compiler_v7_2_22 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_COMPONENT_NAME : STRING;
C_COEF_FILE : STRING;
C_COEF_FILE_LINES : INTEGER;
C_FILTER_TYPE : INTEGER;
C_INTERP_RATE : INTEGER;
C_DECIM_RATE : INTEGER;
C_ZERO_PACKING_FACTOR : INTEGER;
C_SYMMETRY : INTEGER;
C_NUM_FILTS : INTEGER;
C_NUM_TAPS : INTEGER;
C_NUM_CHANNELS : INTEGER;
C_CHANNEL_PATTERN : STRING;
C_ROUND_MODE : INTEGER;
C_COEF_RELOAD : INTEGER;
C_NUM_RELOAD_SLOTS : INTEGER;
C_COL_MODE : INTEGER;
C_COL_PIPE_LEN : INTEGER;
C_COL_CONFIG : STRING;
C_OPTIMIZATION : INTEGER;
C_DATA_PATH_WIDTHS : STRING;
C_DATA_IP_PATH_WIDTHS : STRING;
C_DATA_PX_PATH_WIDTHS : STRING;
C_DATA_WIDTH : INTEGER;
C_COEF_PATH_WIDTHS : STRING;
C_COEF_WIDTH : INTEGER;
C_DATA_PATH_SRC : STRING;
C_COEF_PATH_SRC : STRING;
C_PX_PATH_SRC : STRING;
C_DATA_PATH_SIGN : STRING;
C_COEF_PATH_SIGN : STRING;
C_ACCUM_PATH_WIDTHS : STRING;
C_OUTPUT_WIDTH : INTEGER;
C_OUTPUT_PATH_WIDTHS : STRING;
C_ACCUM_OP_PATH_WIDTHS : STRING;
C_EXT_MULT_CNFG : STRING;
C_DATA_PATH_PSAMP_SRC : STRING;
C_OP_PATH_PSAMP_SRC : STRING;
C_NUM_MADDS : INTEGER;
C_OPT_MADDS : STRING;
C_OVERSAMPLING_RATE : INTEGER;
C_INPUT_RATE : INTEGER;
C_OUTPUT_RATE : INTEGER;
C_DATA_MEMTYPE : INTEGER;
C_COEF_MEMTYPE : INTEGER;
C_IPBUFF_MEMTYPE : INTEGER;
C_OPBUFF_MEMTYPE : INTEGER;
C_DATAPATH_MEMTYPE : INTEGER;
C_MEM_ARRANGEMENT : INTEGER;
C_DATA_MEM_PACKING : INTEGER;
C_COEF_MEM_PACKING : INTEGER;
C_FILTS_PACKED : INTEGER;
C_LATENCY : INTEGER;
C_HAS_ARESETn : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_DATA_HAS_TLAST : INTEGER;
C_S_DATA_HAS_FIFO : INTEGER;
C_S_DATA_HAS_TUSER : INTEGER;
C_S_DATA_TDATA_WIDTH : INTEGER;
C_S_DATA_TUSER_WIDTH : INTEGER;
C_M_DATA_HAS_TREADY : INTEGER;
C_M_DATA_HAS_TUSER : INTEGER;
C_M_DATA_TDATA_WIDTH : INTEGER;
C_M_DATA_TUSER_WIDTH : INTEGER;
C_HAS_CONFIG_CHANNEL : INTEGER;
C_CONFIG_SYNC_MODE : INTEGER;
C_CONFIG_PACKET_SIZE : INTEGER;
C_CONFIG_TDATA_WIDTH : INTEGER;
C_RELOAD_TDATA_WIDTH : INTEGER
);
PORT (
aresetn : IN STD_LOGIC;
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tlast : IN STD_LOGIC;
s_axis_data_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_data_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_config_tvalid : IN STD_LOGIC;
s_axis_config_tready : OUT STD_LOGIC;
s_axis_config_tlast : IN STD_LOGIC;
s_axis_config_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_reload_tvalid : IN STD_LOGIC;
s_axis_reload_tready : OUT STD_LOGIC;
s_axis_reload_tlast : IN STD_LOGIC;
s_axis_reload_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tready : IN STD_LOGIC;
m_axis_data_tlast : OUT STD_LOGIC;
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
event_s_data_tlast_missing : OUT STD_LOGIC;
event_s_data_tlast_unexpected : OUT STD_LOGIC;
event_s_data_chanid_incorrect : OUT STD_LOGIC;
event_s_config_tlast_missing : OUT STD_LOGIC;
event_s_config_tlast_unexpected : OUT STD_LOGIC;
event_s_reload_tlast_missing : OUT STD_LOGIC;
event_s_reload_tlast_unexpected : OUT STD_LOGIC
);
END COMPONENT fir_compiler_v7_2_22;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF aclk: SIGNAL IS "XIL_INTERFACENAME aclk_intf, ASSOCIATED_BUSIF S_AXIS_CONFIG:M_AXIS_DATA:S_AXIS_DATA:S_AXIS_RELOAD, ASSOCIATED_RESET aresetn, ASSOCIATED_CLKEN aclken, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axis_data_tvalid: SIGNAL IS "XIL_INTERFACENAME M_AXIS_DATA, TDATA_NUM_BYTES 3, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TREADY";
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_data_tvalid: SIGNAL IS "XIL_INTERFACENAME S_AXIS_DATA, TDATA_NUM_BYTES 1, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TVALID";
BEGIN
U0 : fir_compiler_v7_2_22
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_COMPONENT_NAME => "hrc_128_12_03",
C_COEF_FILE => "hrc_128_12_03.mif",
C_COEF_FILE_LINES => 1664,
C_FILTER_TYPE => 2,
C_INTERP_RATE => 128,
C_DECIM_RATE => 3,
C_ZERO_PACKING_FACTOR => 1,
C_SYMMETRY => 0,
C_NUM_FILTS => 1,
C_NUM_TAPS => 1537,
C_NUM_CHANNELS => 1,
C_CHANNEL_PATTERN => "fixed",
C_ROUND_MODE => 0,
C_COEF_RELOAD => 0,
C_NUM_RELOAD_SLOTS => 1,
C_COL_MODE => 1,
C_COL_PIPE_LEN => 4,
C_COL_CONFIG => "13",
C_OPTIMIZATION => 0,
C_DATA_PATH_WIDTHS => "2",
C_DATA_IP_PATH_WIDTHS => "2",
C_DATA_PX_PATH_WIDTHS => "2",
C_DATA_WIDTH => 2,
C_COEF_PATH_WIDTHS => "16",
C_COEF_WIDTH => 16,
C_DATA_PATH_SRC => "0",
C_COEF_PATH_SRC => "0",
C_PX_PATH_SRC => "0",
C_DATA_PATH_SIGN => "0",
C_COEF_PATH_SIGN => "0",
C_ACCUM_PATH_WIDTHS => "18",
C_OUTPUT_WIDTH => 18,
C_OUTPUT_PATH_WIDTHS => "18",
C_ACCUM_OP_PATH_WIDTHS => "18",
C_EXT_MULT_CNFG => "none",
C_DATA_PATH_PSAMP_SRC => "0",
C_OP_PATH_PSAMP_SRC => "0",
C_NUM_MADDS => 13,
C_OPT_MADDS => "none",
C_OVERSAMPLING_RATE => 1,
C_INPUT_RATE => 42,
C_OUTPUT_RATE => 1,
C_DATA_MEMTYPE => 0,
C_COEF_MEMTYPE => 2,
C_IPBUFF_MEMTYPE => 0,
C_OPBUFF_MEMTYPE => 0,
C_DATAPATH_MEMTYPE => 0,
C_MEM_ARRANGEMENT => 2,
C_DATA_MEM_PACKING => 0,
C_COEF_MEM_PACKING => 0,
C_FILTS_PACKED => 0,
C_LATENCY => 19,
C_HAS_ARESETn => 0,
C_HAS_ACLKEN => 0,
C_DATA_HAS_TLAST => 0,
C_S_DATA_HAS_FIFO => 1,
C_S_DATA_HAS_TUSER => 0,
C_S_DATA_TDATA_WIDTH => 8,
C_S_DATA_TUSER_WIDTH => 1,
C_M_DATA_HAS_TREADY => 0,
C_M_DATA_HAS_TUSER => 0,
C_M_DATA_TDATA_WIDTH => 24,
C_M_DATA_TUSER_WIDTH => 1,
C_HAS_CONFIG_CHANNEL => 0,
C_CONFIG_SYNC_MODE => 0,
C_CONFIG_PACKET_SIZE => 0,
C_CONFIG_TDATA_WIDTH => 1,
C_RELOAD_TDATA_WIDTH => 1
)
PORT MAP (
aresetn => '1',
aclk => aclk,
aclken => '1',
s_axis_data_tvalid => s_axis_data_tvalid,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tlast => '0',
s_axis_data_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_data_tdata => s_axis_data_tdata,
s_axis_config_tvalid => '0',
s_axis_config_tlast => '0',
s_axis_config_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_reload_tvalid => '0',
s_axis_reload_tlast => '0',
s_axis_reload_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tready => '1',
m_axis_data_tdata => m_axis_data_tdata
);
END hrc_128_12_03_arch;
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-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of AMD and is protected under U.S. and international copyright
-- and other intellectual property laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- AMD, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) AMD shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or AMD had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- AMD products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of AMD products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fir_compiler:7.2
-- IP Revision: 22
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fir_compiler_v7_2_22;
USE fir_compiler_v7_2_22.fir_compiler_v7_2_22;
ENTITY hrc_128_12_03 IS
PORT (
aclk : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END hrc_128_12_03;
ARCHITECTURE hrc_128_12_03_arch OF hrc_128_12_03 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF hrc_128_12_03_arch: ARCHITECTURE IS "yes";
COMPONENT fir_compiler_v7_2_22 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_COMPONENT_NAME : STRING;
C_COEF_FILE : STRING;
C_COEF_FILE_LINES : INTEGER;
C_FILTER_TYPE : INTEGER;
C_INTERP_RATE : INTEGER;
C_DECIM_RATE : INTEGER;
C_ZERO_PACKING_FACTOR : INTEGER;
C_SYMMETRY : INTEGER;
C_NUM_FILTS : INTEGER;
C_NUM_TAPS : INTEGER;
C_NUM_CHANNELS : INTEGER;
C_CHANNEL_PATTERN : STRING;
C_ROUND_MODE : INTEGER;
C_COEF_RELOAD : INTEGER;
C_NUM_RELOAD_SLOTS : INTEGER;
C_COL_MODE : INTEGER;
C_COL_PIPE_LEN : INTEGER;
C_COL_CONFIG : STRING;
C_OPTIMIZATION : INTEGER;
C_DATA_PATH_WIDTHS : STRING;
C_DATA_IP_PATH_WIDTHS : STRING;
C_DATA_PX_PATH_WIDTHS : STRING;
C_DATA_WIDTH : INTEGER;
C_COEF_PATH_WIDTHS : STRING;
C_COEF_WIDTH : INTEGER;
C_DATA_PATH_SRC : STRING;
C_COEF_PATH_SRC : STRING;
C_PX_PATH_SRC : STRING;
C_DATA_PATH_SIGN : STRING;
C_COEF_PATH_SIGN : STRING;
C_ACCUM_PATH_WIDTHS : STRING;
C_OUTPUT_WIDTH : INTEGER;
C_OUTPUT_PATH_WIDTHS : STRING;
C_ACCUM_OP_PATH_WIDTHS : STRING;
C_EXT_MULT_CNFG : STRING;
C_DATA_PATH_PSAMP_SRC : STRING;
C_OP_PATH_PSAMP_SRC : STRING;
C_NUM_MADDS : INTEGER;
C_OPT_MADDS : STRING;
C_OVERSAMPLING_RATE : INTEGER;
C_INPUT_RATE : INTEGER;
C_OUTPUT_RATE : INTEGER;
C_DATA_MEMTYPE : INTEGER;
C_COEF_MEMTYPE : INTEGER;
C_IPBUFF_MEMTYPE : INTEGER;
C_OPBUFF_MEMTYPE : INTEGER;
C_DATAPATH_MEMTYPE : INTEGER;
C_MEM_ARRANGEMENT : INTEGER;
C_DATA_MEM_PACKING : INTEGER;
C_COEF_MEM_PACKING : INTEGER;
C_FILTS_PACKED : INTEGER;
C_LATENCY : INTEGER;
C_HAS_ARESETn : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_DATA_HAS_TLAST : INTEGER;
C_S_DATA_HAS_FIFO : INTEGER;
C_S_DATA_HAS_TUSER : INTEGER;
C_S_DATA_TDATA_WIDTH : INTEGER;
C_S_DATA_TUSER_WIDTH : INTEGER;
C_M_DATA_HAS_TREADY : INTEGER;
C_M_DATA_HAS_TUSER : INTEGER;
C_M_DATA_TDATA_WIDTH : INTEGER;
C_M_DATA_TUSER_WIDTH : INTEGER;
C_HAS_CONFIG_CHANNEL : INTEGER;
C_CONFIG_SYNC_MODE : INTEGER;
C_CONFIG_PACKET_SIZE : INTEGER;
C_CONFIG_TDATA_WIDTH : INTEGER;
C_RELOAD_TDATA_WIDTH : INTEGER
);
PORT (
aresetn : IN STD_LOGIC;
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tlast : IN STD_LOGIC;
s_axis_data_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_data_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_config_tvalid : IN STD_LOGIC;
s_axis_config_tready : OUT STD_LOGIC;
s_axis_config_tlast : IN STD_LOGIC;
s_axis_config_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_reload_tvalid : IN STD_LOGIC;
s_axis_reload_tready : OUT STD_LOGIC;
s_axis_reload_tlast : IN STD_LOGIC;
s_axis_reload_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tready : IN STD_LOGIC;
m_axis_data_tlast : OUT STD_LOGIC;
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
event_s_data_tlast_missing : OUT STD_LOGIC;
event_s_data_tlast_unexpected : OUT STD_LOGIC;
event_s_data_chanid_incorrect : OUT STD_LOGIC;
event_s_config_tlast_missing : OUT STD_LOGIC;
event_s_config_tlast_unexpected : OUT STD_LOGIC;
event_s_reload_tlast_missing : OUT STD_LOGIC;
event_s_reload_tlast_unexpected : OUT STD_LOGIC
);
END COMPONENT fir_compiler_v7_2_22;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF hrc_128_12_03_arch: ARCHITECTURE IS "fir_compiler_v7_2_22,Vivado 2024.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF hrc_128_12_03_arch : ARCHITECTURE IS "hrc_128_12_03,fir_compiler_v7_2_22,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF hrc_128_12_03_arch: ARCHITECTURE IS "hrc_128_12_03,fir_compiler_v7_2_22,{x_ipProduct=Vivado 2024.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fir_compiler,x_ipVersion=7.2,x_ipCoreRevision=22,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_COMPONENT_NAME=hrc_128_12_03,C_COEF_FILE=hrc_128_12_03.mif,C_COEF_FILE_LINES=1664,C_FILTER_TYPE=2,C_INTERP_RATE=128,C_DECIM_RATE=3,C_ZERO_PACKING_FACTOR=1,C_SYMMETRY=0,C_NUM_FILTS=1,C_NUM_TAPS=1537,C_NUM_CHANNELS=1,C_CHANNEL_PATTERN=fixed,C_ROUND_MODE=0,C_" &
"COEF_RELOAD=0,C_NUM_RELOAD_SLOTS=1,C_COL_MODE=1,C_COL_PIPE_LEN=4,C_COL_CONFIG=13,C_OPTIMIZATION=0,C_DATA_PATH_WIDTHS=2,C_DATA_IP_PATH_WIDTHS=2,C_DATA_PX_PATH_WIDTHS=2,C_DATA_WIDTH=2,C_COEF_PATH_WIDTHS=16,C_COEF_WIDTH=16,C_DATA_PATH_SRC=0,C_COEF_PATH_SRC=0,C_PX_PATH_SRC=0,C_DATA_PATH_SIGN=0,C_COEF_PATH_SIGN=0,C_ACCUM_PATH_WIDTHS=18,C_OUTPUT_WIDTH=18,C_OUTPUT_PATH_WIDTHS=18,C_ACCUM_OP_PATH_WIDTHS=18,C_EXT_MULT_CNFG=none,C_DATA_PATH_PSAMP_SRC=0,C_OP_PATH_PSAMP_SRC=0,C_NUM_MADDS=13,C_OPT_MADDS=none," &
"C_OVERSAMPLING_RATE=1,C_INPUT_RATE=42,C_OUTPUT_RATE=1,C_DATA_MEMTYPE=0,C_COEF_MEMTYPE=2,C_IPBUFF_MEMTYPE=0,C_OPBUFF_MEMTYPE=0,C_DATAPATH_MEMTYPE=0,C_MEM_ARRANGEMENT=2,C_DATA_MEM_PACKING=0,C_COEF_MEM_PACKING=0,C_FILTS_PACKED=0,C_LATENCY=19,C_HAS_ARESETn=0,C_HAS_ACLKEN=0,C_DATA_HAS_TLAST=0,C_S_DATA_HAS_FIFO=1,C_S_DATA_HAS_TUSER=0,C_S_DATA_TDATA_WIDTH=8,C_S_DATA_TUSER_WIDTH=1,C_M_DATA_HAS_TREADY=0,C_M_DATA_HAS_TUSER=0,C_M_DATA_TDATA_WIDTH=24,C_M_DATA_TUSER_WIDTH=1,C_HAS_CONFIG_CHANNEL=0,C_CONFIG_SY" &
"NC_MODE=0,C_CONFIG_PACKET_SIZE=0,C_CONFIG_TDATA_WIDTH=1,C_RELOAD_TDATA_WIDTH=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF aclk: SIGNAL IS "XIL_INTERFACENAME aclk_intf, ASSOCIATED_BUSIF S_AXIS_CONFIG:M_AXIS_DATA:S_AXIS_DATA:S_AXIS_RELOAD, ASSOCIATED_RESET aresetn, ASSOCIATED_CLKEN aclken, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axis_data_tvalid: SIGNAL IS "XIL_INTERFACENAME M_AXIS_DATA, TDATA_NUM_BYTES 3, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TREADY";
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_data_tvalid: SIGNAL IS "XIL_INTERFACENAME S_AXIS_DATA, TDATA_NUM_BYTES 1, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TVALID";
BEGIN
U0 : fir_compiler_v7_2_22
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_COMPONENT_NAME => "hrc_128_12_03",
C_COEF_FILE => "hrc_128_12_03.mif",
C_COEF_FILE_LINES => 1664,
C_FILTER_TYPE => 2,
C_INTERP_RATE => 128,
C_DECIM_RATE => 3,
C_ZERO_PACKING_FACTOR => 1,
C_SYMMETRY => 0,
C_NUM_FILTS => 1,
C_NUM_TAPS => 1537,
C_NUM_CHANNELS => 1,
C_CHANNEL_PATTERN => "fixed",
C_ROUND_MODE => 0,
C_COEF_RELOAD => 0,
C_NUM_RELOAD_SLOTS => 1,
C_COL_MODE => 1,
C_COL_PIPE_LEN => 4,
C_COL_CONFIG => "13",
C_OPTIMIZATION => 0,
C_DATA_PATH_WIDTHS => "2",
C_DATA_IP_PATH_WIDTHS => "2",
C_DATA_PX_PATH_WIDTHS => "2",
C_DATA_WIDTH => 2,
C_COEF_PATH_WIDTHS => "16",
C_COEF_WIDTH => 16,
C_DATA_PATH_SRC => "0",
C_COEF_PATH_SRC => "0",
C_PX_PATH_SRC => "0",
C_DATA_PATH_SIGN => "0",
C_COEF_PATH_SIGN => "0",
C_ACCUM_PATH_WIDTHS => "18",
C_OUTPUT_WIDTH => 18,
C_OUTPUT_PATH_WIDTHS => "18",
C_ACCUM_OP_PATH_WIDTHS => "18",
C_EXT_MULT_CNFG => "none",
C_DATA_PATH_PSAMP_SRC => "0",
C_OP_PATH_PSAMP_SRC => "0",
C_NUM_MADDS => 13,
C_OPT_MADDS => "none",
C_OVERSAMPLING_RATE => 1,
C_INPUT_RATE => 42,
C_OUTPUT_RATE => 1,
C_DATA_MEMTYPE => 0,
C_COEF_MEMTYPE => 2,
C_IPBUFF_MEMTYPE => 0,
C_OPBUFF_MEMTYPE => 0,
C_DATAPATH_MEMTYPE => 0,
C_MEM_ARRANGEMENT => 2,
C_DATA_MEM_PACKING => 0,
C_COEF_MEM_PACKING => 0,
C_FILTS_PACKED => 0,
C_LATENCY => 19,
C_HAS_ARESETn => 0,
C_HAS_ACLKEN => 0,
C_DATA_HAS_TLAST => 0,
C_S_DATA_HAS_FIFO => 1,
C_S_DATA_HAS_TUSER => 0,
C_S_DATA_TDATA_WIDTH => 8,
C_S_DATA_TUSER_WIDTH => 1,
C_M_DATA_HAS_TREADY => 0,
C_M_DATA_HAS_TUSER => 0,
C_M_DATA_TDATA_WIDTH => 24,
C_M_DATA_TUSER_WIDTH => 1,
C_HAS_CONFIG_CHANNEL => 0,
C_CONFIG_SYNC_MODE => 0,
C_CONFIG_PACKET_SIZE => 0,
C_CONFIG_TDATA_WIDTH => 1,
C_RELOAD_TDATA_WIDTH => 1
)
PORT MAP (
aresetn => '1',
aclk => aclk,
aclken => '1',
s_axis_data_tvalid => s_axis_data_tvalid,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tlast => '0',
s_axis_data_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_data_tdata => s_axis_data_tdata,
s_axis_config_tvalid => '0',
s_axis_config_tlast => '0',
s_axis_config_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_reload_tvalid => '0',
s_axis_reload_tlast => '0',
s_axis_reload_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tready => '1',
m_axis_data_tdata => m_axis_data_tdata
);
END hrc_128_12_03_arch;
cx9261a_demo_cmos_20240513/project_fix_dac.srcs/sources_1/ip/hrc_16_12_03/cmodel/fir_compiler_v7_2_bitacc_cmodel_lin64.zip
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//------------------------------------------------------------------------------
// (c) Copyright 2023 Advanced Micro Devices. All rights reserved.
//
// This file contains confidential and proprietary information
// of AMD, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// AMD, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) AMD shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or AMD had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// AMD products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of AMD products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//------------------------------------------------------------------------------
//
// C Model configuration for the "hrc_16_12_03" instance.
//
//------------------------------------------------------------------------------
//
// coefficients: -203,-163,-111,-50,17,85,152,212,261,296,315,315,295,257,203,134,55,-29,-113,-191,-258,-309,-340,-348,-331,-290,-226,-142,-43,64,172,273,360,426,462,465,432,360,252,112,-55,-238,-428,-612,-778,-911,-1000,-1033,-1003,-903,-732,-492,-190,163,553,960,1363,1738,2060,2305,2451,2476,2368,2114,1714,1171,497,-288,-1154,-2067,-2986,-3864,-4652,-5298,-5752,-5968,-5902,-5521,-4797,-3715,-2271,-476,1651,4073,6744,9606,12592,15628,18635,21533,24239,26679,28782,30486,31740,32508,32767,32508,31740,30486,28782,26679,24239,21533,18635,15628,12592,9606,6744,4073,1651,-476,-2271,-3715,-4797,-5521,-5902,-5968,-5752,-5298,-4652,-3864,-2986,-2067,-1154,-288,497,1171,1714,2114,2368,2476,2451,2305,2060,1738,1363,960,553,163,-190,-492,-732,-903,-1003,-1033,-1000,-911,-778,-612,-428,-238,-55,112,252,360,432,465,462,426,360,273,172,64,-43,-142,-226,-290,-331,-348,-340,-309,-258,-191,-113,-29,55,134,203,257,295,315,315,296,261,212,152,85,17,-50,-111,-163,-203
// chanpats: 173
// name: hrc_16_12_03
// filter_type: 1
// rate_change: 1
// interp_rate: 16
// decim_rate: 3
// zero_pack_factor: 1
// coeff_padding: 0
// num_coeffs: 193
// coeff_sets: 1
// reloadable: 0
// is_halfband: 0
// quantization: 0
// coeff_width: 16
// coeff_fract_width: 0
// chan_seq: 0
// num_channels: 1
// num_paths: 1
// data_width: 2
// data_fract_width: 0
// output_rounding_mode: 0
// output_width: 18
// output_fract_width: 0
// config_method: 0
const double hrc_16_12_03_coefficients[193] = {-203,-163,-111,-50,17,85,152,212,261,296,315,315,295,257,203,134,55,-29,-113,-191,-258,-309,-340,-348,-331,-290,-226,-142,-43,64,172,273,360,426,462,465,432,360,252,112,-55,-238,-428,-612,-778,-911,-1000,-1033,-1003,-903,-732,-492,-190,163,553,960,1363,1738,2060,2305,2451,2476,2368,2114,1714,1171,497,-288,-1154,-2067,-2986,-3864,-4652,-5298,-5752,-5968,-5902,-5521,-4797,-3715,-2271,-476,1651,4073,6744,9606,12592,15628,18635,21533,24239,26679,28782,30486,31740,32508,32767,32508,31740,30486,28782,26679,24239,21533,18635,15628,12592,9606,6744,4073,1651,-476,-2271,-3715,-4797,-5521,-5902,-5968,-5752,-5298,-4652,-3864,-2986,-2067,-1154,-288,497,1171,1714,2114,2368,2476,2451,2305,2060,1738,1363,960,553,163,-190,-492,-732,-903,-1003,-1033,-1000,-911,-778,-612,-428,-238,-55,112,252,360,432,465,462,426,360,273,172,64,-43,-142,-226,-290,-331,-348,-340,-309,-258,-191,-113,-29,55,134,203,257,295,315,315,296,261,212,152,85,17,-50,-111,-163,-203};
const xip_fir_v7_2_pattern hrc_16_12_03_chanpats[1] = {P_BASIC};
static xip_fir_v7_2_config gen_hrc_16_12_03_config() {
xip_fir_v7_2_config config;
config.name = "hrc_16_12_03";
config.filter_type = 1;
config.rate_change = XIP_FIR_FRACTIONAL_RATE;
config.interp_rate = 16;
config.decim_rate = 3;
config.zero_pack_factor = 1;
config.coeff = &hrc_16_12_03_coefficients[0];
config.coeff_padding = 0;
config.num_coeffs = 193;
config.coeff_sets = 1;
config.reloadable = 0;
config.is_halfband = 0;
config.quantization = XIP_FIR_INTEGER_COEFF;
config.coeff_width = 16;
config.coeff_fract_width = 0;
config.chan_seq = XIP_FIR_BASIC_CHAN_SEQ;
config.num_channels = 1;
config.init_pattern = hrc_16_12_03_chanpats[0];
config.num_paths = 1;
config.data_width = 2;
config.data_fract_width = 0;
config.output_rounding_mode= XIP_FIR_FULL_PRECISION;
config.output_width = 18;
config.output_fract_width = 0,
config.config_method = XIP_FIR_CONFIG_SINGLE;
return config;
}
const xip_fir_v7_2_config hrc_16_12_03_config = gen_hrc_16_12_03_config();
cx9261a_demo_cmos_20240513/project_fix_dac.srcs/sources_1/ip/hrc_16_12_03/cmodel/tb_hrc_16_12_03.c
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//-----------------------------------------------------------------------------
// (c) Copyright 2014 2023 Advanced Micro Devices, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of AMD, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// AMD, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) AMD shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or AMD had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// AMD products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of AMD products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
// C testbench for the "hrc_16_12_03" instance
// o Basic C testbench based on the run_bitacc_cmodel.c smoke test program
// included in the C model zip files. Please refer run_bitacc_cmodel.c
// for further examples of how to use the FIR Compiler C model.
// o Unzip the appropriate platform specifc zip file and use the following example
// command line to compile and link this TB:
// gcc -x c++ -I. -L. -lIp_fir_compiler_v7_2_22_bitacc_cmodel -Wl,-rpath,. -o tb_hrc_16_12_03 tb_hrc_16_12_03.c
#include <stdio.h>
#include "fir_compiler_v7_2_bitacc_cmodel.h"
#include "hrc_16_12_03.h"
//---------------------------------------------------------------------------------------------------------------------
// Example message handler
static void msg_print(void* handle, int error, const char* msg)
{
printf("%s\n",msg);
}
//---------------------------------------------------------------------------------------------------------------------
//Print a xip_array_real
void print_array_real(const xip_array_real* x)
{
putchar('[');
if (x && x->data && x->data_size)
{
const xip_real* p=x->data;
const xip_real* q=x->data;
const xip_real* r=x->data+x->data_size;
while (q!=r)
{
if (q!=p) putchar(' ');
printf("%g",*q);
q++;
}
}
putchar(']');
putchar('\n');
}
//----------------------------------------------------------------------------------------------------------------------
// Fill data array with a scaled impulse. Assumes 3-D array.
int create_impulse(xip_array_real* x) {
int path;
int chan;
int i;
for (path = 0; path < x->dim[0];path++) {
for (chan = 0; chan < x->dim[1];chan++) {
xip_fir_v7_2_xip_array_real_set_chan(x,(double)((path+1)*(chan+1)),path,chan,0,P_BASIC);
for (i = 1; i < x->dim[2];i++) {
xip_fir_v7_2_xip_array_real_set_chan(x,0,path,chan,i,P_BASIC);
}
}
}
return 0;
}
//----------------------------------------------------------------------------------------------------------------------
// String arrays used by the print_config funtion
const char *filt_desc[5] = { "SINGLE RATE", "INTERPOLATION", "DECIMATION", "HILBERT", "INTERPOLATED" };
const char *seq_desc[2] = { "Basic" , "Advanced" };
//----------------------------------------------------------------------------------------------------------------------
// Print a summary of a filter configuration
int print_config(const xip_fir_v7_2_config* cfg) {
printf("Configuration of %s:\n",cfg->name);
printf("\tFilter : ");
if ( cfg->filter_type == XIP_FIR_SINGLE_RATE || cfg->filter_type == XIP_FIR_HILBERT ) {
printf("%s\n",filt_desc[cfg->filter_type]);
} else if ( cfg->filter_type == XIP_FIR_INTERPOLATED ) {
printf("%s by %d\n",filt_desc[cfg->filter_type],cfg->zero_pack_factor);
} else {
printf("%s up by %d down by %d\n",filt_desc[cfg->filter_type],cfg->interp_rate,cfg->decim_rate);
}
printf("\tCoefficients : %d ",cfg->coeff_sets);
if ( cfg->is_halfband ) {
printf("Halfband ");
}
if (cfg->reloadable) {
printf("Reloadable ");
}
printf("coefficient set(s) of %d taps\n",cfg->num_coeffs);
printf("\tData : %d path(s) of %d %s channel(s)\n",cfg->num_paths,cfg->num_channels,seq_desc[cfg->chan_seq]);
return 0;
}
//----------------------------------------------------------------------------------------------------------------------
int main () {
const char* ver_str = xip_fir_v7_2_get_version();
printf("FIR Compiler C Model version: %s\n",ver_str);
print_config(&hrc_16_12_03_config);
//Create filter instances
xip_fir_v7_2* hrc_16_12_03_inst = xip_fir_v7_2_create(&hrc_16_12_03_config,&msg_print,0);
if (!hrc_16_12_03_inst) {
printf("Error creating instance\n",hrc_16_12_03_config.name);
return -1;
} else {
printf("Created instance\n",hrc_16_12_03_config.name);
}
// Create input data packet
xip_array_real* din = xip_array_real_create();
xip_array_real_reserve_dim(din,3);
din->dim_size = 3; // 3D array
din->dim[0] = hrc_16_12_03_config.num_paths;
din->dim[1] = hrc_16_12_03_config.num_channels;
din->dim[2] = hrc_16_12_03_config.num_coeffs; // vectors in a single packet
din->data_size = din->dim[0] * din->dim[1] * din->dim[2];
if (xip_array_real_reserve_data(din,din->data_size) == XIP_STATUS_OK) {
printf("Reserved data\n");
} else {
printf("Unable to reserve data!\n");
return -1;
}
// Create output data packet
// - Automatically sized using xip_fir_v7_2_calc_size
xip_array_real* dout = xip_array_real_create();
xip_array_real_reserve_dim(dout,3);
dout->dim_size = 3; // 3D array
if(xip_fir_v7_2_calc_size(hrc_16_12_03_inst,din,dout,0)== XIP_STATUS_OK) {
printf("Calculated output data size\n");
if (xip_array_real_reserve_data(dout,dout->data_size) == XIP_STATUS_OK) {
printf("Reserved data\n");
} else {
printf("Unable to reserve data!\n");
return -1;
}
} else {
printf("Unable to calculate output date size\n");
return -1;
}
// Populate data in with an impulse
printf("Create impulse\n");
create_impulse(din);
// Send input data and filter
if ( xip_fir_v7_2_data_send(hrc_16_12_03_inst,din)== XIP_STATUS_OK) {
printf("Sent data : ");
print_array_real(din);
} else {
printf("Error sending data\n");
return -1;
}
// Retrieve filtered data
if ( xip_fir_v7_2_data_get(hrc_16_12_03_inst,dout,0)== XIP_STATUS_OK) {
printf("Fetched result: ");
print_array_real(dout);
} else {
printf("Error getting data\n");
return -1;
}
}
cx9261a_demo_cmos_20240513/project_fix_dac.srcs/sources_1/ip/hrc_16_12_03/constraints/fir_compiler_v7_2.xdc
+46
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# (c) Copyright 2023 Advanced Micro Devices, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of AMD and is protected under U.S. and international copyright
# and other intellectual property laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# AMD, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) AMD shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or AMD had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# AMD products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of AMD products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
############################################################
set_property -quiet SIM_COLLISION_CHECK GENERATE_X_ONLY [get_cells -quiet -hierarchical -filter {IS_PRIMITIVE && (TYPE=="Block Memory" || TYPE=="Block Ram" || TYPE=="BLOCKRAM")}]
cx9261a_demo_cmos_20240513/project_fix_dac.srcs/sources_1/ip/hrc_16_12_03/demo_tb/tb_hrc_16_12_03.vhd
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--------------------------------------------------------------------------------
-- (c) Copyright 2011 - 2013 2023 Advanced Micro Devices, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of AMD, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- AMD, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) AMD shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or AMD had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- AMD products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of AMD products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Description:
-- This is an example testbench for the FIR Compiler IP core.
-- The testbench has been generated by Vivado to accompany the IP core
-- instance you have generated.
--
-- This testbench is for demonstration purposes only. See note below for
-- instructions on how to use it with your core.
--
-- See the FIR Compiler product guide for further information
-- about this core.
--
--------------------------------------------------------------------------------
-- Using this testbench
--
-- This testbench instantiates your generated FIR Compiler core
-- instance named "hrc_16_12_03".
--
-- Use Vivado's Run Simulation flow to run this testbench. See the Vivado
-- documentation for details.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_hrc_16_12_03 is
end tb_hrc_16_12_03;
architecture tb of tb_hrc_16_12_03 is
-----------------------------------------------------------------------
-- Timing constants
-----------------------------------------------------------------------
constant CLOCK_PERIOD : time := 100 ns;
constant T_HOLD : time := 10 ns;
constant T_STROBE : time := CLOCK_PERIOD - (1 ns);
-----------------------------------------------------------------------
-- DUT signals
-----------------------------------------------------------------------
-- General signals
signal aclk : std_logic := '0'; -- the master clock
-- Data slave channel signals
signal s_axis_data_tvalid : std_logic := '0'; -- payload is valid
signal s_axis_data_tready : std_logic := '1'; -- slave is ready
signal s_axis_data_tdata : std_logic_vector(7 downto 0) := (others => '0'); -- data payload
-- Data master channel signals
signal m_axis_data_tvalid : std_logic := '0'; -- payload is valid
signal m_axis_data_tdata : std_logic_vector(23 downto 0) := (others => '0'); -- data payload
-----------------------------------------------------------------------
-- Aliases for AXI channel TDATA and TUSER fields
-- These are a convenience for viewing data in a simulator waveform viewer.
-- If using ModelSim or Questa, add "-voptargs=+acc=n" to the vsim command
-- to prevent the simulator optimizing away these signals.
-----------------------------------------------------------------------
-- Data slave channel alias signals
signal s_axis_data_tdata_data : std_logic_vector(1 downto 0) := (others => '0');
-- Data master channel alias signals
signal m_axis_data_tdata_data : std_logic_vector(17 downto 0) := (others => '0');
begin
-----------------------------------------------------------------------
-- Instantiate the DUT
-----------------------------------------------------------------------
dut : entity work.hrc_16_12_03
port map (
aclk => aclk,
s_axis_data_tvalid => s_axis_data_tvalid,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tdata => s_axis_data_tdata,
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tdata => m_axis_data_tdata
);
-----------------------------------------------------------------------
-- Generate clock
-----------------------------------------------------------------------
clock_gen : process
begin
aclk <= '0';
wait for CLOCK_PERIOD;
loop
aclk <= '0';
wait for CLOCK_PERIOD/2;
aclk <= '1';
wait for CLOCK_PERIOD/2;
end loop;
end process clock_gen;
-----------------------------------------------------------------------
-- Generate inputs
-----------------------------------------------------------------------
stimuli : process
-- Procedure to drive a number of input samples with specific data
-- data is the data value to drive on the tdata signal
-- samples is the number of zero-data input samples to drive
procedure drive_data ( data : std_logic_vector(7 downto 0);
samples : natural := 1 ) is
variable ip_count : integer := 0;
begin
ip_count := 0;
loop
s_axis_data_tvalid <= '1';
s_axis_data_tdata <= data;
loop
wait until rising_edge(aclk);
exit when s_axis_data_tready = '1';
end loop;
ip_count := ip_count + 1;
wait for T_HOLD;
-- Input rate is 1 input each 5 clock cycles: drive valid inputs at this rate
s_axis_data_tvalid <= '0';
wait for CLOCK_PERIOD * 4;
exit when ip_count >= samples;
end loop;
end procedure drive_data;
-- Procedure to drive a number of zero-data input samples
-- samples is the number of zero-data input samples to drive
procedure drive_zeros ( samples : natural := 1 ) is
begin
drive_data((others => '0'), samples);
end procedure drive_zeros;
-- Procedure to drive an impulse and let the impulse response emerge on the data master channel
-- samples is the number of input samples to drive; default is enough for impulse response output to emerge
procedure drive_impulse ( samples : natural := 216 ) is
variable impulse : std_logic_vector(7 downto 0);
begin
impulse := (others => '0'); -- initialize unused bits to zero
impulse(1 downto 0) := "01";
drive_data(impulse);
if samples > 1 then
drive_zeros(samples-1);
end if;
end procedure drive_impulse;
begin
-- Drive inputs T_HOLD time after rising edge of clock
wait until rising_edge(aclk);
wait for T_HOLD;
-- Drive a single impulse and let the impulse response emerge
drive_impulse;
-- Drive another impulse, during which demonstrate use and effect of AXI handshaking signals
drive_impulse(2); -- start of impulse; data is now zero
s_axis_data_tvalid <= '0';
wait for CLOCK_PERIOD * 25; -- provide no data for 5 input samples worth
drive_zeros(2); -- 2 normal input samples
s_axis_data_tvalid <= '1';
wait for CLOCK_PERIOD * 25; -- provide data as fast as the core can accept it for 5 input samples worth
drive_zeros(207); -- back to normal operation
-- End of test
report "Not a real failure. Simulation finished successfully. Test completed successfully" severity failure;
wait;
end process stimuli;
-----------------------------------------------------------------------
-- Check outputs
-----------------------------------------------------------------------
check_outputs : process
variable check_ok : boolean := true;
begin
-- Check outputs T_STROBE time after rising edge of clock
wait until rising_edge(aclk);
wait for T_STROBE;
-- Do not check the output payload values, as this requires the behavioral model
-- which would make this demonstration testbench unwieldy.
-- Instead, check the protocol of the master DATA channel:
-- check that the payload is valid (not X) when TVALID is high
if m_axis_data_tvalid = '1' then
if is_x(m_axis_data_tdata) then
report "ERROR: m_axis_data_tdata is invalid when m_axis_data_tvalid is high" severity error;
check_ok := false;
end if;
end if;
assert check_ok
report "ERROR: terminating test with failures." severity failure;
end process check_outputs;
-----------------------------------------------------------------------
-- Assign TDATA / TUSER fields to aliases, for easy simulator waveform viewing
-----------------------------------------------------------------------
-- Data slave channel alias signals
s_axis_data_tdata_data <= s_axis_data_tdata(1 downto 0);
-- Data master channel alias signals: update these only when they are valid
m_axis_data_tdata_data <= m_axis_data_tdata(17 downto 0) when m_axis_data_tvalid = '1';
end tb;
cx9261a_demo_cmos_20240513/project_fix_dac.srcs/sources_1/ip/hrc_16_12_03/doc/fir_compiler_v7_2_changelog.txt
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2024.1:
* Version 7.2 (Rev. 22)
* Bug Fix: Added Synplicity key
* Other: IP packaging adjustments to address warnings from IP Packager integrity check
* Revision change in one or more subcores
2023.2.2:
* Version 7.2 (Rev. 21)
* Revision change in one or more subcores
2023.2.1:
* Version 7.2 (Rev. 20)
* No changes
2023.2:
* Version 7.2 (Rev. 20)
* Bug Fix: Minor GUI fix to update Output Width range following a change in Coefficient Structure
* Bug Fix: Update half-band interpolation "power of 2" center tap optimization to support symmetric rounding
* Other: Rebrand to AMD copyright information
* Revision change in one or more subcores
2023.1.2:
* Version 7.2 (Rev. 19)
* No changes
2023.1.1:
* Version 7.2 (Rev. 19)
* No changes
2023.1:
* Version 7.2 (Rev. 19)
* General: Device support changes. No change to functionality or performance
2022.2.2:
* Version 7.2 (Rev. 18)
* No changes
2022.2.1:
* Version 7.2 (Rev. 18)
* No changes
2022.2:
* Version 7.2 (Rev. 18)
* No changes
2022.1.2:
* Version 7.2 (Rev. 18)
* No changes
2022.1.1:
* Version 7.2 (Rev. 18)
* No changes
2022.1:
* Version 7.2 (Rev. 18)
* Feature Enhancement: C model MEX wrapper updates to support Octave
2021.2.2:
* Version 7.2 (Rev. 17)
* No changes
2021.2.1:
* Version 7.2 (Rev. 17)
* No changes
2021.2:
* Version 7.2 (Rev. 17)
* Bug Fix: Fixed convergent rounding bug for symmetric polyphase decimators
2021.1.1:
* Version 7.2 (Rev. 16)
* No changes
2021.1:
* Version 7.2 (Rev. 16)
* Bug Fix: Fixed width mismatch issue with SSR single rate extended multiply reload configs
* Other: testbench and constraints updates
2020.3:
* Version 7.2 (Rev. 15)
* No changes
2020.2.2:
* Version 7.2 (Rev. 15)
* No changes
2020.2.1:
* Version 7.2 (Rev. 15)
* No changes
2020.2:
* Version 7.2 (Rev. 15)
* Bug Fix: Fixed incorrect application of symmetry when Interpolation_Rate > clk_freq/samp_freq > 1
* Feature Enhancement: Improved GUI error reporting for designs that don't fit within selected device.
* Other: Windows C model compilation now uses Visual Studio 2017
2020.1.1:
* Version 7.2 (Rev. 14)
* No changes
2020.1:
* Version 7.2 (Rev. 14)
* Bug Fix: Fixed bug with coefficient reload file.
* Bug Fix: Improved error trapping behaviour in the GUI.
* Bug Fix: Fixed simulator specific bug
* Feature Enhancement: Extended Symmetric Coefficient Structures for Interpolation and Decimation Filters with Super Sample Rate.
* Feature Enhancement: Improved the GUI for selecting optimizations.
2019.2.2:
* Version 7.2 (Rev. 13)
* No changes
2019.2.1:
* Version 7.2 (Rev. 13)
* No changes
2019.2:
* Version 7.2 (Rev. 13)
* General: Improved efficiency to C model output. No change to functionality.
2019.1.3:
* Version 7.2 (Rev. 12)
* No changes
2019.1.2:
* Version 7.2 (Rev. 12)
* No changes
2019.1.1:
* Version 7.2 (Rev. 12)
* No changes
2019.1:
* Version 7.2 (Rev. 12)
* Bug Fix: Addressing memory leak in MEX wrapper.
* Bug Fix: Fixed coefficient width range minimum for coefficient file input.
* Bug Fix: Fixed upper bound of Sample Frequency when Advanced Channel Sequence is selected.
* Bug Fix: Fixed C model crash when multiple DSP IP C models are run together: AR 71876
* Other: Support for new devices. No change to exisiting functionality, resource use or performance.
* Revision change in one or more subcores
2018.3.1:
* Version 7.2 (Rev. 11)
* No changes
2018.3:
* Version 7.2 (Rev. 11)
* No changes
2018.2:
* Version 7.2 (Rev. 11)
* No changes
2018.1:
* Version 7.2 (Rev. 11)
* Revision change in one or more subcores
2017.4:
* Version 7.2 (Rev. 10)
* Feature Enhancement: Add option to remove shift register inference attributes; SHREG_EXTRACT and SRL_STYLE
2017.3:
* Version 7.2 (Rev. 9)
* Feature Enhancement: Increase the maximum number of parallel inputs from 64 to 256
* Revision change in one or more subcores
2017.2:
* Version 7.2 (Rev. 8)
* No changes
2017.1:
* Version 7.2 (Rev. 8)
* Bug Fix: Output Rounding Mode parameter validation corrected to produce an error during design validation (IP Integrator/System Generator) rather than silently updating to a legal value.
* Bug Fix: Correction to Convergent Rounding when multiple DSP slices are required to implement the filter multiply operations.
2016.4:
* Version 7.2 (Rev. 7)
* No changes
2016.3:
* Version 7.2 (Rev. 7)
* General: Support for Spartan7 devices
* Revision change in one or more subcores
2016.2:
* Version 7.2 (Rev. 6)
* No changes
2016.1:
* Version 7.2 (Rev. 6)
* Fix for error in Sysgen parameter propagation.
* Enabled DSP48 ADREG/DREG but gate CEAD/CED to address power DRC.
* Fix in common c model utilities package for handling of arrays of real types in Matlab
* Revision change in one or more subcores
2015.4.2:
* Version 7.2 (Rev. 5)
* No changes
2015.4.1:
* Version 7.2 (Rev. 5)
* No changes
2015.4:
* Version 7.2 (Rev. 5)
* Correction to GUI reported Calculated Coefficients for Transpose Interpolation filters.
* Revision change in one or more subcores
2015.3:
* Version 7.2 (Rev. 4)
* Add constraints file to suppress expected memory collision warnings during post-synthesis simulation.
* IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances
* Correction to GUI reported latency estimate for polyphase interpolation configurations.
* Revision change in one or more subcores
2015.2.1:
* Version 7.2 (Rev. 3)
* No changes
2015.2:
* Version 7.2 (Rev. 3)
* Correction to the GUI reported startup latency for polyphase interpolation configurations.
* Correction for Halfband Decimation with Symmetric rounding on Ultrascale parts.
* Correction for Polyphase Interpolation with Convergent rounding where multiple DSP columns are required to support the data and/or coefficient width.
2015.1:
* Version 7.2 (Rev. 2)
* Warning reduction.
* Correction to single rate half-band control for data vector reset, an oversample rate of 2, utilizing a single multiply add unit.
* Added the SRL_STYLE attribute to the delay component to ensure an efficient implementation.
* Fix to Sample Period propagation to avoid false Column Configuration errors.
* GUI filter coefficient processing speed up for bit widths greater than DSP48 input width.
* Addition of Beta support for future devices
* Correction to fractional interpolation configurations utilizing Maximium Possible hardware oversampling specification in System Generator.
* Update to C model to match GUI behaviour. Add support for quantization/truncation of integer only coefficients when XIP_FIR_QUANTIZED_ONLY has been specified.
* Supported devices and production status are now determined automatically, to simplify support for future devices
* C models are no longer provided for 32-bit operating systems as Vivado has deprecated 32-bit OS support
2014.4.1:
* Version 7.2 (Rev. 1)
* No changes
2014.4:
* Version 7.2 (Rev. 1)
* Fix for UltraScale Halfband Interpolation optimization with Convergent Rounding and multiple parallel paths.
* C Model maximum data and coefficient widths updated for UltraScale.
* Correction to GUI latency calculation.
* Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
* Add 1 x fs Advanced Channel Sequence to sequence length 24.
* Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interface aclk_intf
2014.3:
* Version 7.2
* Optimized Halfband filter support for UltraScale devices.
* Super sample rate support.
* Enhanced Hardware Oversampling specification methods. Now supports input and output sample period specification.
* CONFIG channel behavior has been updated for the Packet Synchronization method (On Packet) following power up or reset.
2014.2:
* Version 7.1 (Rev. 4)
* Removed component statement for DSP48E2, no functional changes
2014.1:
* Version 7.1 (Rev. 3)
* C models for Windows are compiled using Microsoft Visual Studio 2012
* Internal device family name change, no functional changes
* Netlists created by write_verilog and write_vhdl are IEEE P1735 encrypted, with keys for supported simulators so that netlist simulation can still be done
* Enable third party synthesis tools to read encrypted netlists (but not source HDL)
* Fixed AR58946, COE file coefficient specification now working correctly in IP Integrator.
* Support for Virtex Ultrascale devices at Pre-Production Status
2013.4:
* Version 7.1 (Rev. 2)
* Added workaround to the GUI for AR57785
* Support for Kintex Ultrascale devices at Pre-Production Status
2013.3:
* Version 7.1 (Rev. 1)
* Behavioral VHDL model replaced by Encrypted RTL. For more information on this change please refer to the Migrating and Upgrading section in the Product Guide
* Internal standardization in source file delivery, does not change behavior
* Support for Automotive Artix-7, Automotive Zynq, Defense Grade Artix-7, Defense Grade Zynq and Lower Power Artix-7 devices at Production Status
* Added default constraints for out of context flow
* Optimized support for UltraScale devices
* Added support for Cadence IES and Synopsys VCS simulators
* Removed C model dependency on stlport (STL Portability) library; C model now uses STL built into the compiler
* Windows C model DLLs are statically linked to the Windows C run-time (CRT) library, to remove the runtime dependency on MSVCRT90.dll, which can cause problems when using the C model in a Windows compiler other than Visual Studio 2008
* C model updated to use third-party library MPIR version 2.6.0 (previously was version 2.2.1); the Windows MPIR DLLs are also statically linked to the Windows CRT library, to remove the dependency on MSVCRT90.dll
2013.2:
* Version 7.1
* Support for Series 7 devices at Production status
* Beta support for future devices
* Enhanced Optimization specification including optional use of Block RAM READ-FIRST mode
* Maximum interleaved channels increased to 1024
* Bug Fixes
2013.1:
* Version 7.0
* Native Vivado Release
* There have been no functional or interface changes to this IP. The version number has changed to support unique versioning in Vivado starting with 2013.1.
(c) Copyright 2002 - 2024 Advanced Micro Devices, Inc. All rights reserved.
This file contains confidential and proprietary information
of AMD and is protected under U.S. and international copyright
and other intellectual property laws.
DISCLAIMER
This disclaimer is not a license and does not grant any
rights to the materials distributed herewith. Except as
otherwise provided in a valid license issued to you by
AMD, and to the maximum extent permitted by applicable
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
(2) AMD shall not be liable (whether in contract or tort,
including negligence, or under any other theory of
liability) for any loss or damage of any kind or nature
related to, arising under or in connection with these
materials, including for any direct, or any indirect,
special, incidental, or consequential loss or damage
(including loss of data, profits, goodwill, or any type of
loss or damage suffered as a result of any action brought
by a third party) even if such damage or loss was
reasonably foreseeable or AMD had been advised of the
possibility of the same.
CRITICAL APPLICATIONS
AMD products are not designed or intended to be fail-
safe, or for use in any application requiring fail-safe
performance, such as life-support or safety devices or
systems, Class III medical devices, nuclear facilities,
applications related to the deployment of airbags, or any
other applications that could lead to death, personal
injury, or severe property or environmental damage
(individually and collectively, "Critical
Applications"). Customer assumes the sole risk and
liability of any use of AMD products in Critical
Applications, subject only to applicable laws and
regulations governing limitations on product liability.
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
PART OF THIS FILE AT ALL TIMES.
cx9261a_demo_cmos_20240513/project_fix_dac.srcs/sources_1/ip/hrc_16_12_03/hdl/axi_utils_v2_0_vh_rfs.vhd
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cx9261a_demo_cmos_20240513/project_fix_dac.srcs/sources_1/ip/hrc_16_12_03/hrc_16_12_03.dcp
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cx9261a_demo_cmos_20240513/project_fix_dac.srcs/sources_1/ip/hrc_16_12_03/hrc_16_12_03.veo
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// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of AMD and is protected under U.S. and international copyright
// and other intellectual property laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// AMD, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) AMD shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or AMD had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// AMD products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of AMD products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:fir_compiler:7.2
// IP Revision: 22
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
hrc_16_12_03 your_instance_name (
.aclk(aclk), // input wire aclk
.s_axis_data_tvalid(s_axis_data_tvalid), // input wire s_axis_data_tvalid
.s_axis_data_tready(s_axis_data_tready), // output wire s_axis_data_tready
.s_axis_data_tdata(s_axis_data_tdata), // input wire [7 : 0] s_axis_data_tdata
.m_axis_data_tvalid(m_axis_data_tvalid), // output wire m_axis_data_tvalid
.m_axis_data_tdata(m_axis_data_tdata) // output wire [23 : 0] m_axis_data_tdata
);
// INST_TAG_END ------ End INSTANTIATION Template ---------
// You must compile the wrapper file hrc_16_12_03.v when simulating
// the core, hrc_16_12_03. When compiling the wrapper file, be sure to
// reference the Verilog simulation library.
cx9261a_demo_cmos_20240513/project_fix_dac.srcs/sources_1/ip/hrc_16_12_03/hrc_16_12_03.vho
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-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of AMD and is protected under U.S. and international copyright
-- and other intellectual property laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- AMD, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) AMD shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or AMD had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- AMD products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of AMD products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fir_compiler:7.2
-- IP Revision: 22
-- The following code must appear in the VHDL architecture header.
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
COMPONENT hrc_16_12_03
PORT (
aclk : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END COMPONENT;
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
-- The following code must appear in the VHDL architecture
-- body. Substitute your own instance name and net names.
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
your_instance_name : hrc_16_12_03
PORT MAP (
aclk => aclk,
s_axis_data_tvalid => s_axis_data_tvalid,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tdata => s_axis_data_tdata,
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tdata => m_axis_data_tdata
);
-- INST_TAG_END ------ End INSTANTIATION Template ---------
-- You must compile the wrapper file hrc_16_12_03.vhd when simulating
-- the core, hrc_16_12_03. When compiling the wrapper file, be sure to
-- reference the VHDL simulation library.
cx9261a_demo_cmos_20240513/project_fix_dac.srcs/sources_1/ip/hrc_16_12_03/hrc_16_12_03.xci
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{
"schema": "xilinx.com:schema:json_instance:1.0",
"ip_inst": {
"xci_name": "hrc_16_12_03",
"component_reference": "xilinx.com:ip:fir_compiler:7.2",
"ip_revision": "22",
"gen_directory": ".",
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"Coefficient_Sets": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Coefficient_Reload": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Filter_Type": [ { "value": "Interpolation", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
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"Select_Pattern": [ { "value": "All", "resolve_type": "user", "usage": "all" } ],
"Pattern_List": [ { "value": "P4-0,P4-1,P4-2,P4-3,P4-4", "resolve_type": "user", "usage": "all" } ],
"Number_Paths": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"RateSpecification": [ { "value": "Frequency_Specification", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"HardwareOversamplingRate": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"Sample_Frequency": [ { "value": "12", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"Clock_Frequency": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"Coefficient_Sign": [ { "value": "Signed", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"Quantization": [ { "value": "Integer_Coefficients", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"Coefficient_Width": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"Data_Sign": [ { "value": "Signed", "resolve_type": "user", "usage": "all" } ],
"Data_Width": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Data_Fractional_Bits": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Output_Rounding_Mode": [ { "value": "Full_Precision", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"Output_Width": [ { "value": "18", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"Optimization_Goal": [ { "value": "Area", "resolve_type": "user", "usage": "all" } ],
"Optimization_Selection": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
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"Coefficient_Fanout": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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"Control_Column_Fanout": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Control_Broadcast_Fanout": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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"Data_Buffer_Type": [ { "value": "Automatic", "resolve_type": "user", "usage": "all" } ],
"Coefficient_Buffer_Type": [ { "value": "Automatic", "resolve_type": "user", "usage": "all" } ],
"Input_Buffer_Type": [ { "value": "Automatic", "resolve_type": "user", "usage": "all" } ],
"Output_Buffer_Type": [ { "value": "Automatic", "resolve_type": "user", "usage": "all" } ],
"Preference_For_Other_Storage": [ { "value": "Automatic", "resolve_type": "user", "usage": "all" } ],
"Multi_Column_Support": [ { "value": "Automatic", "resolve_type": "user", "usage": "all" } ],
"Inter_Column_Pipe_Length": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
"ColumnConfig": [ { "value": "13", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
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"M_DATA_Has_TREADY": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"S_DATA_Has_FIFO": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"S_DATA_Has_TUSER": [ { "value": "Not_Required", "resolve_type": "user", "usage": "all" } ],
"M_DATA_Has_TUSER": [ { "value": "Not_Required", "resolve_type": "user", "usage": "all" } ],
"DATA_TUSER_Width": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"S_CONFIG_Sync_Mode": [ { "value": "On_Vector", "resolve_type": "user", "usage": "all" } ],
"S_CONFIG_Method": [ { "value": "Single", "resolve_type": "user", "usage": "all" } ],
"Num_Reload_Slots": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Has_ACLKEN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Has_ARESETn": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Reset_Data_Vector": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Blank_Output": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Gen_MIF_from_Spec": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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"Reload_File": [ { "value": "no_coe_file_loaded", "resolve_type": "user", "usage": "all" } ],
"Gen_MIF_Files": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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},
"model_parameters": {
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cx9261a_demo_cmos_20240513/project_fix_dac.srcs/sources_1/ip/hrc_16_12_03/hrc_16_12_03.xml
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# (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
# (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of AMD and is protected under U.S. and international copyright
# and other intellectual property laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# AMD, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) AMD shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or AMD had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# AMD products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of AMD products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#
# DO NOT MODIFY THIS FILE.
# #########################################################
#
# This XDC is used only in OOC mode for synthesis, implementation
#
# #########################################################
create_clock -period 10 -name aclk [get_ports aclk]
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// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
// Date : Fri Nov 1 13:03:30 2024
// Host : gatsby-dev running 64-bit Red Hat Enterprise Linux release 8.10 (Ootpa)
// Command : write_verilog -force -mode synth_stub
// /home/josh/Workspace/vivado/brd_cx2161a/zc706_cx9261a_demo/zc706_cx9261a_demo.gen/sources_1/ip/hrc_16_12_03/hrc_16_12_03_stub.v
// Design : hrc_16_12_03
// Purpose : Stub declaration of top-level module interface
// Device : xc7z045ffg900-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "fir_compiler_v7_2_22,Vivado 2024.1" *)
module hrc_16_12_03(aclk, s_axis_data_tvalid, s_axis_data_tready,
s_axis_data_tdata, m_axis_data_tvalid, m_axis_data_tdata)
/* synthesis syn_black_box black_box_pad_pin="s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[7:0],m_axis_data_tvalid,m_axis_data_tdata[23:0]" */
/* synthesis syn_force_seq_prim="aclk" */;
input aclk /* synthesis syn_isclock = 1 */;
input s_axis_data_tvalid;
output s_axis_data_tready;
input [7:0]s_axis_data_tdata;
output m_axis_data_tvalid;
output [23:0]m_axis_data_tdata;
endmodule
cx9261a_demo_cmos_20240513/project_fix_dac.srcs/sources_1/ip/hrc_16_12_03/hrc_16_12_03_stub.vhdl
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-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
-- Date : Fri Nov 1 13:03:30 2024
-- Host : gatsby-dev running 64-bit Red Hat Enterprise Linux release 8.10 (Ootpa)
-- Command : write_vhdl -force -mode synth_stub
-- /home/josh/Workspace/vivado/brd_cx2161a/zc706_cx9261a_demo/zc706_cx9261a_demo.gen/sources_1/ip/hrc_16_12_03/hrc_16_12_03_stub.vhdl
-- Design : hrc_16_12_03
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z045ffg900-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity hrc_16_12_03 is
Port (
aclk : in STD_LOGIC;
s_axis_data_tvalid : in STD_LOGIC;
s_axis_data_tready : out STD_LOGIC;
s_axis_data_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_data_tvalid : out STD_LOGIC;
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
end hrc_16_12_03;
architecture stub of hrc_16_12_03 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[7:0],m_axis_data_tvalid,m_axis_data_tdata[23:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "fir_compiler_v7_2_22,Vivado 2024.1";
begin
end;
cx9261a_demo_cmos_20240513/project_fix_dac.srcs/sources_1/ip/hrc_16_12_03/sim/hrc_16_12_03.vhd
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-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of AMD and is protected under U.S. and international copyright
-- and other intellectual property laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- AMD, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) AMD shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or AMD had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- AMD products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of AMD products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fir_compiler:7.2
-- IP Revision: 22
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fir_compiler_v7_2_22;
USE fir_compiler_v7_2_22.fir_compiler_v7_2_22;
ENTITY hrc_16_12_03 IS
PORT (
aclk : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END hrc_16_12_03;
ARCHITECTURE hrc_16_12_03_arch OF hrc_16_12_03 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF hrc_16_12_03_arch: ARCHITECTURE IS "yes";
COMPONENT fir_compiler_v7_2_22 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_COMPONENT_NAME : STRING;
C_COEF_FILE : STRING;
C_COEF_FILE_LINES : INTEGER;
C_FILTER_TYPE : INTEGER;
C_INTERP_RATE : INTEGER;
C_DECIM_RATE : INTEGER;
C_ZERO_PACKING_FACTOR : INTEGER;
C_SYMMETRY : INTEGER;
C_NUM_FILTS : INTEGER;
C_NUM_TAPS : INTEGER;
C_NUM_CHANNELS : INTEGER;
C_CHANNEL_PATTERN : STRING;
C_ROUND_MODE : INTEGER;
C_COEF_RELOAD : INTEGER;
C_NUM_RELOAD_SLOTS : INTEGER;
C_COL_MODE : INTEGER;
C_COL_PIPE_LEN : INTEGER;
C_COL_CONFIG : STRING;
C_OPTIMIZATION : INTEGER;
C_DATA_PATH_WIDTHS : STRING;
C_DATA_IP_PATH_WIDTHS : STRING;
C_DATA_PX_PATH_WIDTHS : STRING;
C_DATA_WIDTH : INTEGER;
C_COEF_PATH_WIDTHS : STRING;
C_COEF_WIDTH : INTEGER;
C_DATA_PATH_SRC : STRING;
C_COEF_PATH_SRC : STRING;
C_PX_PATH_SRC : STRING;
C_DATA_PATH_SIGN : STRING;
C_COEF_PATH_SIGN : STRING;
C_ACCUM_PATH_WIDTHS : STRING;
C_OUTPUT_WIDTH : INTEGER;
C_OUTPUT_PATH_WIDTHS : STRING;
C_ACCUM_OP_PATH_WIDTHS : STRING;
C_EXT_MULT_CNFG : STRING;
C_DATA_PATH_PSAMP_SRC : STRING;
C_OP_PATH_PSAMP_SRC : STRING;
C_NUM_MADDS : INTEGER;
C_OPT_MADDS : STRING;
C_OVERSAMPLING_RATE : INTEGER;
C_INPUT_RATE : INTEGER;
C_OUTPUT_RATE : INTEGER;
C_DATA_MEMTYPE : INTEGER;
C_COEF_MEMTYPE : INTEGER;
C_IPBUFF_MEMTYPE : INTEGER;
C_OPBUFF_MEMTYPE : INTEGER;
C_DATAPATH_MEMTYPE : INTEGER;
C_MEM_ARRANGEMENT : INTEGER;
C_DATA_MEM_PACKING : INTEGER;
C_COEF_MEM_PACKING : INTEGER;
C_FILTS_PACKED : INTEGER;
C_LATENCY : INTEGER;
C_HAS_ARESETn : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_DATA_HAS_TLAST : INTEGER;
C_S_DATA_HAS_FIFO : INTEGER;
C_S_DATA_HAS_TUSER : INTEGER;
C_S_DATA_TDATA_WIDTH : INTEGER;
C_S_DATA_TUSER_WIDTH : INTEGER;
C_M_DATA_HAS_TREADY : INTEGER;
C_M_DATA_HAS_TUSER : INTEGER;
C_M_DATA_TDATA_WIDTH : INTEGER;
C_M_DATA_TUSER_WIDTH : INTEGER;
C_HAS_CONFIG_CHANNEL : INTEGER;
C_CONFIG_SYNC_MODE : INTEGER;
C_CONFIG_PACKET_SIZE : INTEGER;
C_CONFIG_TDATA_WIDTH : INTEGER;
C_RELOAD_TDATA_WIDTH : INTEGER
);
PORT (
aresetn : IN STD_LOGIC;
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tlast : IN STD_LOGIC;
s_axis_data_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_data_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_config_tvalid : IN STD_LOGIC;
s_axis_config_tready : OUT STD_LOGIC;
s_axis_config_tlast : IN STD_LOGIC;
s_axis_config_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_reload_tvalid : IN STD_LOGIC;
s_axis_reload_tready : OUT STD_LOGIC;
s_axis_reload_tlast : IN STD_LOGIC;
s_axis_reload_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tready : IN STD_LOGIC;
m_axis_data_tlast : OUT STD_LOGIC;
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
event_s_data_tlast_missing : OUT STD_LOGIC;
event_s_data_tlast_unexpected : OUT STD_LOGIC;
event_s_data_chanid_incorrect : OUT STD_LOGIC;
event_s_config_tlast_missing : OUT STD_LOGIC;
event_s_config_tlast_unexpected : OUT STD_LOGIC;
event_s_reload_tlast_missing : OUT STD_LOGIC;
event_s_reload_tlast_unexpected : OUT STD_LOGIC
);
END COMPONENT fir_compiler_v7_2_22;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF aclk: SIGNAL IS "XIL_INTERFACENAME aclk_intf, ASSOCIATED_BUSIF S_AXIS_CONFIG:M_AXIS_DATA:S_AXIS_DATA:S_AXIS_RELOAD, ASSOCIATED_RESET aresetn, ASSOCIATED_CLKEN aclken, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axis_data_tvalid: SIGNAL IS "XIL_INTERFACENAME M_AXIS_DATA, TDATA_NUM_BYTES 3, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TREADY";
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_data_tvalid: SIGNAL IS "XIL_INTERFACENAME S_AXIS_DATA, TDATA_NUM_BYTES 1, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TVALID";
BEGIN
U0 : fir_compiler_v7_2_22
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_COMPONENT_NAME => "hrc_16_12_03",
C_COEF_FILE => "hrc_16_12_03.mif",
C_COEF_FILE_LINES => 208,
C_FILTER_TYPE => 2,
C_INTERP_RATE => 16,
C_DECIM_RATE => 3,
C_ZERO_PACKING_FACTOR => 1,
C_SYMMETRY => 0,
C_NUM_FILTS => 1,
C_NUM_TAPS => 193,
C_NUM_CHANNELS => 1,
C_CHANNEL_PATTERN => "fixed",
C_ROUND_MODE => 0,
C_COEF_RELOAD => 0,
C_NUM_RELOAD_SLOTS => 1,
C_COL_MODE => 1,
C_COL_PIPE_LEN => 4,
C_COL_CONFIG => "13",
C_OPTIMIZATION => 0,
C_DATA_PATH_WIDTHS => "2",
C_DATA_IP_PATH_WIDTHS => "2",
C_DATA_PX_PATH_WIDTHS => "2",
C_DATA_WIDTH => 2,
C_COEF_PATH_WIDTHS => "16",
C_COEF_WIDTH => 16,
C_DATA_PATH_SRC => "0",
C_COEF_PATH_SRC => "0",
C_PX_PATH_SRC => "0",
C_DATA_PATH_SIGN => "0",
C_COEF_PATH_SIGN => "0",
C_ACCUM_PATH_WIDTHS => "18",
C_OUTPUT_WIDTH => 18,
C_OUTPUT_PATH_WIDTHS => "18",
C_ACCUM_OP_PATH_WIDTHS => "18",
C_EXT_MULT_CNFG => "none",
C_DATA_PATH_PSAMP_SRC => "0",
C_OP_PATH_PSAMP_SRC => "0",
C_NUM_MADDS => 13,
C_OPT_MADDS => "none",
C_OVERSAMPLING_RATE => 1,
C_INPUT_RATE => 5,
C_OUTPUT_RATE => 1,
C_DATA_MEMTYPE => 0,
C_COEF_MEMTYPE => 2,
C_IPBUFF_MEMTYPE => 0,
C_OPBUFF_MEMTYPE => 0,
C_DATAPATH_MEMTYPE => 0,
C_MEM_ARRANGEMENT => 2,
C_DATA_MEM_PACKING => 0,
C_COEF_MEM_PACKING => 0,
C_FILTS_PACKED => 0,
C_LATENCY => 19,
C_HAS_ARESETn => 0,
C_HAS_ACLKEN => 0,
C_DATA_HAS_TLAST => 0,
C_S_DATA_HAS_FIFO => 1,
C_S_DATA_HAS_TUSER => 0,
C_S_DATA_TDATA_WIDTH => 8,
C_S_DATA_TUSER_WIDTH => 1,
C_M_DATA_HAS_TREADY => 0,
C_M_DATA_HAS_TUSER => 0,
C_M_DATA_TDATA_WIDTH => 24,
C_M_DATA_TUSER_WIDTH => 1,
C_HAS_CONFIG_CHANNEL => 0,
C_CONFIG_SYNC_MODE => 0,
C_CONFIG_PACKET_SIZE => 0,
C_CONFIG_TDATA_WIDTH => 1,
C_RELOAD_TDATA_WIDTH => 1
)
PORT MAP (
aresetn => '1',
aclk => aclk,
aclken => '1',
s_axis_data_tvalid => s_axis_data_tvalid,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tlast => '0',
s_axis_data_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_data_tdata => s_axis_data_tdata,
s_axis_config_tvalid => '0',
s_axis_config_tlast => '0',
s_axis_config_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_reload_tvalid => '0',
s_axis_reload_tlast => '0',
s_axis_reload_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tready => '1',
m_axis_data_tdata => m_axis_data_tdata
);
END hrc_16_12_03_arch;
cx9261a_demo_cmos_20240513/project_fix_dac.srcs/sources_1/ip/hrc_16_12_03/synth/hrc_16_12_03.vhd
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-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of AMD and is protected under U.S. and international copyright
-- and other intellectual property laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- AMD, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) AMD shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or AMD had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- AMD products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of AMD products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fir_compiler:7.2
-- IP Revision: 22
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fir_compiler_v7_2_22;
USE fir_compiler_v7_2_22.fir_compiler_v7_2_22;
ENTITY hrc_16_12_03 IS
PORT (
aclk : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END hrc_16_12_03;
ARCHITECTURE hrc_16_12_03_arch OF hrc_16_12_03 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF hrc_16_12_03_arch: ARCHITECTURE IS "yes";
COMPONENT fir_compiler_v7_2_22 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_COMPONENT_NAME : STRING;
C_COEF_FILE : STRING;
C_COEF_FILE_LINES : INTEGER;
C_FILTER_TYPE : INTEGER;
C_INTERP_RATE : INTEGER;
C_DECIM_RATE : INTEGER;
C_ZERO_PACKING_FACTOR : INTEGER;
C_SYMMETRY : INTEGER;
C_NUM_FILTS : INTEGER;
C_NUM_TAPS : INTEGER;
C_NUM_CHANNELS : INTEGER;
C_CHANNEL_PATTERN : STRING;
C_ROUND_MODE : INTEGER;
C_COEF_RELOAD : INTEGER;
C_NUM_RELOAD_SLOTS : INTEGER;
C_COL_MODE : INTEGER;
C_COL_PIPE_LEN : INTEGER;
C_COL_CONFIG : STRING;
C_OPTIMIZATION : INTEGER;
C_DATA_PATH_WIDTHS : STRING;
C_DATA_IP_PATH_WIDTHS : STRING;
C_DATA_PX_PATH_WIDTHS : STRING;
C_DATA_WIDTH : INTEGER;
C_COEF_PATH_WIDTHS : STRING;
C_COEF_WIDTH : INTEGER;
C_DATA_PATH_SRC : STRING;
C_COEF_PATH_SRC : STRING;
C_PX_PATH_SRC : STRING;
C_DATA_PATH_SIGN : STRING;
C_COEF_PATH_SIGN : STRING;
C_ACCUM_PATH_WIDTHS : STRING;
C_OUTPUT_WIDTH : INTEGER;
C_OUTPUT_PATH_WIDTHS : STRING;
C_ACCUM_OP_PATH_WIDTHS : STRING;
C_EXT_MULT_CNFG : STRING;
C_DATA_PATH_PSAMP_SRC : STRING;
C_OP_PATH_PSAMP_SRC : STRING;
C_NUM_MADDS : INTEGER;
C_OPT_MADDS : STRING;
C_OVERSAMPLING_RATE : INTEGER;
C_INPUT_RATE : INTEGER;
C_OUTPUT_RATE : INTEGER;
C_DATA_MEMTYPE : INTEGER;
C_COEF_MEMTYPE : INTEGER;
C_IPBUFF_MEMTYPE : INTEGER;
C_OPBUFF_MEMTYPE : INTEGER;
C_DATAPATH_MEMTYPE : INTEGER;
C_MEM_ARRANGEMENT : INTEGER;
C_DATA_MEM_PACKING : INTEGER;
C_COEF_MEM_PACKING : INTEGER;
C_FILTS_PACKED : INTEGER;
C_LATENCY : INTEGER;
C_HAS_ARESETn : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_DATA_HAS_TLAST : INTEGER;
C_S_DATA_HAS_FIFO : INTEGER;
C_S_DATA_HAS_TUSER : INTEGER;
C_S_DATA_TDATA_WIDTH : INTEGER;
C_S_DATA_TUSER_WIDTH : INTEGER;
C_M_DATA_HAS_TREADY : INTEGER;
C_M_DATA_HAS_TUSER : INTEGER;
C_M_DATA_TDATA_WIDTH : INTEGER;
C_M_DATA_TUSER_WIDTH : INTEGER;
C_HAS_CONFIG_CHANNEL : INTEGER;
C_CONFIG_SYNC_MODE : INTEGER;
C_CONFIG_PACKET_SIZE : INTEGER;
C_CONFIG_TDATA_WIDTH : INTEGER;
C_RELOAD_TDATA_WIDTH : INTEGER
);
PORT (
aresetn : IN STD_LOGIC;
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tlast : IN STD_LOGIC;
s_axis_data_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_data_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_config_tvalid : IN STD_LOGIC;
s_axis_config_tready : OUT STD_LOGIC;
s_axis_config_tlast : IN STD_LOGIC;
s_axis_config_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_reload_tvalid : IN STD_LOGIC;
s_axis_reload_tready : OUT STD_LOGIC;
s_axis_reload_tlast : IN STD_LOGIC;
s_axis_reload_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tready : IN STD_LOGIC;
m_axis_data_tlast : OUT STD_LOGIC;
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
event_s_data_tlast_missing : OUT STD_LOGIC;
event_s_data_tlast_unexpected : OUT STD_LOGIC;
event_s_data_chanid_incorrect : OUT STD_LOGIC;
event_s_config_tlast_missing : OUT STD_LOGIC;
event_s_config_tlast_unexpected : OUT STD_LOGIC;
event_s_reload_tlast_missing : OUT STD_LOGIC;
event_s_reload_tlast_unexpected : OUT STD_LOGIC
);
END COMPONENT fir_compiler_v7_2_22;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF hrc_16_12_03_arch: ARCHITECTURE IS "fir_compiler_v7_2_22,Vivado 2024.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF hrc_16_12_03_arch : ARCHITECTURE IS "hrc_16_12_03,fir_compiler_v7_2_22,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF hrc_16_12_03_arch: ARCHITECTURE IS "hrc_16_12_03,fir_compiler_v7_2_22,{x_ipProduct=Vivado 2024.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fir_compiler,x_ipVersion=7.2,x_ipCoreRevision=22,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_COMPONENT_NAME=hrc_16_12_03,C_COEF_FILE=hrc_16_12_03.mif,C_COEF_FILE_LINES=208,C_FILTER_TYPE=2,C_INTERP_RATE=16,C_DECIM_RATE=3,C_ZERO_PACKING_FACTOR=1,C_SYMMETRY=0,C_NUM_FILTS=1,C_NUM_TAPS=193,C_NUM_CHANNELS=1,C_CHANNEL_PATTERN=fixed,C_ROUND_MODE=0,C_COEF_R" &
"ELOAD=0,C_NUM_RELOAD_SLOTS=1,C_COL_MODE=1,C_COL_PIPE_LEN=4,C_COL_CONFIG=13,C_OPTIMIZATION=0,C_DATA_PATH_WIDTHS=2,C_DATA_IP_PATH_WIDTHS=2,C_DATA_PX_PATH_WIDTHS=2,C_DATA_WIDTH=2,C_COEF_PATH_WIDTHS=16,C_COEF_WIDTH=16,C_DATA_PATH_SRC=0,C_COEF_PATH_SRC=0,C_PX_PATH_SRC=0,C_DATA_PATH_SIGN=0,C_COEF_PATH_SIGN=0,C_ACCUM_PATH_WIDTHS=18,C_OUTPUT_WIDTH=18,C_OUTPUT_PATH_WIDTHS=18,C_ACCUM_OP_PATH_WIDTHS=18,C_EXT_MULT_CNFG=none,C_DATA_PATH_PSAMP_SRC=0,C_OP_PATH_PSAMP_SRC=0,C_NUM_MADDS=13,C_OPT_MADDS=none,C_OVER" &
"SAMPLING_RATE=1,C_INPUT_RATE=5,C_OUTPUT_RATE=1,C_DATA_MEMTYPE=0,C_COEF_MEMTYPE=2,C_IPBUFF_MEMTYPE=0,C_OPBUFF_MEMTYPE=0,C_DATAPATH_MEMTYPE=0,C_MEM_ARRANGEMENT=2,C_DATA_MEM_PACKING=0,C_COEF_MEM_PACKING=0,C_FILTS_PACKED=0,C_LATENCY=19,C_HAS_ARESETn=0,C_HAS_ACLKEN=0,C_DATA_HAS_TLAST=0,C_S_DATA_HAS_FIFO=1,C_S_DATA_HAS_TUSER=0,C_S_DATA_TDATA_WIDTH=8,C_S_DATA_TUSER_WIDTH=1,C_M_DATA_HAS_TREADY=0,C_M_DATA_HAS_TUSER=0,C_M_DATA_TDATA_WIDTH=24,C_M_DATA_TUSER_WIDTH=1,C_HAS_CONFIG_CHANNEL=0,C_CONFIG_SYNC_MODE" &
"=0,C_CONFIG_PACKET_SIZE=0,C_CONFIG_TDATA_WIDTH=1,C_RELOAD_TDATA_WIDTH=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF aclk: SIGNAL IS "XIL_INTERFACENAME aclk_intf, ASSOCIATED_BUSIF S_AXIS_CONFIG:M_AXIS_DATA:S_AXIS_DATA:S_AXIS_RELOAD, ASSOCIATED_RESET aresetn, ASSOCIATED_CLKEN aclken, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axis_data_tvalid: SIGNAL IS "XIL_INTERFACENAME M_AXIS_DATA, TDATA_NUM_BYTES 3, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TREADY";
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_data_tvalid: SIGNAL IS "XIL_INTERFACENAME S_AXIS_DATA, TDATA_NUM_BYTES 1, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TVALID";
BEGIN
U0 : fir_compiler_v7_2_22
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_COMPONENT_NAME => "hrc_16_12_03",
C_COEF_FILE => "hrc_16_12_03.mif",
C_COEF_FILE_LINES => 208,
C_FILTER_TYPE => 2,
C_INTERP_RATE => 16,
C_DECIM_RATE => 3,
C_ZERO_PACKING_FACTOR => 1,
C_SYMMETRY => 0,
C_NUM_FILTS => 1,
C_NUM_TAPS => 193,
C_NUM_CHANNELS => 1,
C_CHANNEL_PATTERN => "fixed",
C_ROUND_MODE => 0,
C_COEF_RELOAD => 0,
C_NUM_RELOAD_SLOTS => 1,
C_COL_MODE => 1,
C_COL_PIPE_LEN => 4,
C_COL_CONFIG => "13",
C_OPTIMIZATION => 0,
C_DATA_PATH_WIDTHS => "2",
C_DATA_IP_PATH_WIDTHS => "2",
C_DATA_PX_PATH_WIDTHS => "2",
C_DATA_WIDTH => 2,
C_COEF_PATH_WIDTHS => "16",
C_COEF_WIDTH => 16,
C_DATA_PATH_SRC => "0",
C_COEF_PATH_SRC => "0",
C_PX_PATH_SRC => "0",
C_DATA_PATH_SIGN => "0",
C_COEF_PATH_SIGN => "0",
C_ACCUM_PATH_WIDTHS => "18",
C_OUTPUT_WIDTH => 18,
C_OUTPUT_PATH_WIDTHS => "18",
C_ACCUM_OP_PATH_WIDTHS => "18",
C_EXT_MULT_CNFG => "none",
C_DATA_PATH_PSAMP_SRC => "0",
C_OP_PATH_PSAMP_SRC => "0",
C_NUM_MADDS => 13,
C_OPT_MADDS => "none",
C_OVERSAMPLING_RATE => 1,
C_INPUT_RATE => 5,
C_OUTPUT_RATE => 1,
C_DATA_MEMTYPE => 0,
C_COEF_MEMTYPE => 2,
C_IPBUFF_MEMTYPE => 0,
C_OPBUFF_MEMTYPE => 0,
C_DATAPATH_MEMTYPE => 0,
C_MEM_ARRANGEMENT => 2,
C_DATA_MEM_PACKING => 0,
C_COEF_MEM_PACKING => 0,
C_FILTS_PACKED => 0,
C_LATENCY => 19,
C_HAS_ARESETn => 0,
C_HAS_ACLKEN => 0,
C_DATA_HAS_TLAST => 0,
C_S_DATA_HAS_FIFO => 1,
C_S_DATA_HAS_TUSER => 0,
C_S_DATA_TDATA_WIDTH => 8,
C_S_DATA_TUSER_WIDTH => 1,
C_M_DATA_HAS_TREADY => 0,
C_M_DATA_HAS_TUSER => 0,
C_M_DATA_TDATA_WIDTH => 24,
C_M_DATA_TUSER_WIDTH => 1,
C_HAS_CONFIG_CHANNEL => 0,
C_CONFIG_SYNC_MODE => 0,
C_CONFIG_PACKET_SIZE => 0,
C_CONFIG_TDATA_WIDTH => 1,
C_RELOAD_TDATA_WIDTH => 1
)
PORT MAP (
aresetn => '1',
aclk => aclk,
aclken => '1',
s_axis_data_tvalid => s_axis_data_tvalid,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tlast => '0',
s_axis_data_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_data_tdata => s_axis_data_tdata,
s_axis_config_tvalid => '0',
s_axis_config_tlast => '0',
s_axis_config_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_reload_tvalid => '0',
s_axis_reload_tlast => '0',
s_axis_reload_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tready => '1',
m_axis_data_tdata => m_axis_data_tdata
);
END hrc_16_12_03_arch;
cx9261a_demo_cmos_20240513/project_fix_dac.srcs/sources_1/ip/hrc_4_12_03/cmodel/fir_compiler_v7_2_bitacc_cmodel_lin64.zip
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//------------------------------------------------------------------------------
// (c) Copyright 2023 Advanced Micro Devices. All rights reserved.
//
// This file contains confidential and proprietary information
// of AMD, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// AMD, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) AMD shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or AMD had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// AMD products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of AMD products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//------------------------------------------------------------------------------
//
// C Model configuration for the "hrc_4_12_03" instance.
//
//------------------------------------------------------------------------------
//
// coefficients: -203,17,261,295,55,-258,-331,-43,360,432,-55,-778,-1003,-190,1363,2451,1714,-1154,-4652,-5902,-2271,6744,18635,28782,32767,28782,18635,6744,-2271,-5902,-4652,-1154,1714,2451,1363,-190,-1003,-778,-55,432,360,-43,-331,-258,55,295,261,17,-203
// chanpats: 173
// name: hrc_4_12_03
// filter_type: 1
// rate_change: 1
// interp_rate: 4
// decim_rate: 3
// zero_pack_factor: 1
// coeff_padding: 0
// num_coeffs: 49
// coeff_sets: 1
// reloadable: 0
// is_halfband: 0
// quantization: 0
// coeff_width: 16
// coeff_fract_width: 0
// chan_seq: 0
// num_channels: 1
// num_paths: 1
// data_width: 2
// data_fract_width: 0
// output_rounding_mode: 0
// output_width: 18
// output_fract_width: 0
// config_method: 0
const double hrc_4_12_03_coefficients[49] = {-203,17,261,295,55,-258,-331,-43,360,432,-55,-778,-1003,-190,1363,2451,1714,-1154,-4652,-5902,-2271,6744,18635,28782,32767,28782,18635,6744,-2271,-5902,-4652,-1154,1714,2451,1363,-190,-1003,-778,-55,432,360,-43,-331,-258,55,295,261,17,-203};
const xip_fir_v7_2_pattern hrc_4_12_03_chanpats[1] = {P_BASIC};
static xip_fir_v7_2_config gen_hrc_4_12_03_config() {
xip_fir_v7_2_config config;
config.name = "hrc_4_12_03";
config.filter_type = 1;
config.rate_change = XIP_FIR_FRACTIONAL_RATE;
config.interp_rate = 4;
config.decim_rate = 3;
config.zero_pack_factor = 1;
config.coeff = &hrc_4_12_03_coefficients[0];
config.coeff_padding = 0;
config.num_coeffs = 49;
config.coeff_sets = 1;
config.reloadable = 0;
config.is_halfband = 0;
config.quantization = XIP_FIR_INTEGER_COEFF;
config.coeff_width = 16;
config.coeff_fract_width = 0;
config.chan_seq = XIP_FIR_BASIC_CHAN_SEQ;
config.num_channels = 1;
config.init_pattern = hrc_4_12_03_chanpats[0];
config.num_paths = 1;
config.data_width = 2;
config.data_fract_width = 0;
config.output_rounding_mode= XIP_FIR_FULL_PRECISION;
config.output_width = 18;
config.output_fract_width = 0,
config.config_method = XIP_FIR_CONFIG_SINGLE;
return config;
}
const xip_fir_v7_2_config hrc_4_12_03_config = gen_hrc_4_12_03_config();
cx9261a_demo_cmos_20240513/project_fix_dac.srcs/sources_1/ip/hrc_4_12_03/cmodel/tb_hrc_4_12_03.c
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//-----------------------------------------------------------------------------
// (c) Copyright 2014 2023 Advanced Micro Devices, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of AMD, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// AMD, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) AMD shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or AMD had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// AMD products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of AMD products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
// C testbench for the "hrc_4_12_03" instance
// o Basic C testbench based on the run_bitacc_cmodel.c smoke test program
// included in the C model zip files. Please refer run_bitacc_cmodel.c
// for further examples of how to use the FIR Compiler C model.
// o Unzip the appropriate platform specifc zip file and use the following example
// command line to compile and link this TB:
// gcc -x c++ -I. -L. -lIp_fir_compiler_v7_2_22_bitacc_cmodel -Wl,-rpath,. -o tb_hrc_4_12_03 tb_hrc_4_12_03.c
#include <stdio.h>
#include "fir_compiler_v7_2_bitacc_cmodel.h"
#include "hrc_4_12_03.h"
//---------------------------------------------------------------------------------------------------------------------
// Example message handler
static void msg_print(void* handle, int error, const char* msg)
{
printf("%s\n",msg);
}
//---------------------------------------------------------------------------------------------------------------------
//Print a xip_array_real
void print_array_real(const xip_array_real* x)
{
putchar('[');
if (x && x->data && x->data_size)
{
const xip_real* p=x->data;
const xip_real* q=x->data;
const xip_real* r=x->data+x->data_size;
while (q!=r)
{
if (q!=p) putchar(' ');
printf("%g",*q);
q++;
}
}
putchar(']');
putchar('\n');
}
//----------------------------------------------------------------------------------------------------------------------
// Fill data array with a scaled impulse. Assumes 3-D array.
int create_impulse(xip_array_real* x) {
int path;
int chan;
int i;
for (path = 0; path < x->dim[0];path++) {
for (chan = 0; chan < x->dim[1];chan++) {
xip_fir_v7_2_xip_array_real_set_chan(x,(double)((path+1)*(chan+1)),path,chan,0,P_BASIC);
for (i = 1; i < x->dim[2];i++) {
xip_fir_v7_2_xip_array_real_set_chan(x,0,path,chan,i,P_BASIC);
}
}
}
return 0;
}
//----------------------------------------------------------------------------------------------------------------------
// String arrays used by the print_config funtion
const char *filt_desc[5] = { "SINGLE RATE", "INTERPOLATION", "DECIMATION", "HILBERT", "INTERPOLATED" };
const char *seq_desc[2] = { "Basic" , "Advanced" };
//----------------------------------------------------------------------------------------------------------------------
// Print a summary of a filter configuration
int print_config(const xip_fir_v7_2_config* cfg) {
printf("Configuration of %s:\n",cfg->name);
printf("\tFilter : ");
if ( cfg->filter_type == XIP_FIR_SINGLE_RATE || cfg->filter_type == XIP_FIR_HILBERT ) {
printf("%s\n",filt_desc[cfg->filter_type]);
} else if ( cfg->filter_type == XIP_FIR_INTERPOLATED ) {
printf("%s by %d\n",filt_desc[cfg->filter_type],cfg->zero_pack_factor);
} else {
printf("%s up by %d down by %d\n",filt_desc[cfg->filter_type],cfg->interp_rate,cfg->decim_rate);
}
printf("\tCoefficients : %d ",cfg->coeff_sets);
if ( cfg->is_halfband ) {
printf("Halfband ");
}
if (cfg->reloadable) {
printf("Reloadable ");
}
printf("coefficient set(s) of %d taps\n",cfg->num_coeffs);
printf("\tData : %d path(s) of %d %s channel(s)\n",cfg->num_paths,cfg->num_channels,seq_desc[cfg->chan_seq]);
return 0;
}
//----------------------------------------------------------------------------------------------------------------------
int main () {
const char* ver_str = xip_fir_v7_2_get_version();
printf("FIR Compiler C Model version: %s\n",ver_str);
print_config(&hrc_4_12_03_config);
//Create filter instances
xip_fir_v7_2* hrc_4_12_03_inst = xip_fir_v7_2_create(&hrc_4_12_03_config,&msg_print,0);
if (!hrc_4_12_03_inst) {
printf("Error creating instance\n",hrc_4_12_03_config.name);
return -1;
} else {
printf("Created instance\n",hrc_4_12_03_config.name);
}
// Create input data packet
xip_array_real* din = xip_array_real_create();
xip_array_real_reserve_dim(din,3);
din->dim_size = 3; // 3D array
din->dim[0] = hrc_4_12_03_config.num_paths;
din->dim[1] = hrc_4_12_03_config.num_channels;
din->dim[2] = hrc_4_12_03_config.num_coeffs; // vectors in a single packet
din->data_size = din->dim[0] * din->dim[1] * din->dim[2];
if (xip_array_real_reserve_data(din,din->data_size) == XIP_STATUS_OK) {
printf("Reserved data\n");
} else {
printf("Unable to reserve data!\n");
return -1;
}
// Create output data packet
// - Automatically sized using xip_fir_v7_2_calc_size
xip_array_real* dout = xip_array_real_create();
xip_array_real_reserve_dim(dout,3);
dout->dim_size = 3; // 3D array
if(xip_fir_v7_2_calc_size(hrc_4_12_03_inst,din,dout,0)== XIP_STATUS_OK) {
printf("Calculated output data size\n");
if (xip_array_real_reserve_data(dout,dout->data_size) == XIP_STATUS_OK) {
printf("Reserved data\n");
} else {
printf("Unable to reserve data!\n");
return -1;
}
} else {
printf("Unable to calculate output date size\n");
return -1;
}
// Populate data in with an impulse
printf("Create impulse\n");
create_impulse(din);
// Send input data and filter
if ( xip_fir_v7_2_data_send(hrc_4_12_03_inst,din)== XIP_STATUS_OK) {
printf("Sent data : ");
print_array_real(din);
} else {
printf("Error sending data\n");
return -1;
}
// Retrieve filtered data
if ( xip_fir_v7_2_data_get(hrc_4_12_03_inst,dout,0)== XIP_STATUS_OK) {
printf("Fetched result: ");
print_array_real(dout);
} else {
printf("Error getting data\n");
return -1;
}
}
cx9261a_demo_cmos_20240513/project_fix_dac.srcs/sources_1/ip/hrc_4_12_03/constraints/fir_compiler_v7_2.xdc
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# (c) Copyright 2023 Advanced Micro Devices, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of AMD and is protected under U.S. and international copyright
# and other intellectual property laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# AMD, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) AMD shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or AMD had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# AMD products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of AMD products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
############################################################
set_property -quiet SIM_COLLISION_CHECK GENERATE_X_ONLY [get_cells -quiet -hierarchical -filter {IS_PRIMITIVE && (TYPE=="Block Memory" || TYPE=="Block Ram" || TYPE=="BLOCKRAM")}]
cx9261a_demo_cmos_20240513/project_fix_dac.srcs/sources_1/ip/hrc_4_12_03/demo_tb/tb_hrc_4_12_03.vhd
+255
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@@ -0,0 +1,255 @@
--------------------------------------------------------------------------------
-- (c) Copyright 2011 - 2013 2023 Advanced Micro Devices, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of AMD, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- AMD, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) AMD shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or AMD had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- AMD products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of AMD products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Description:
-- This is an example testbench for the FIR Compiler IP core.
-- The testbench has been generated by Vivado to accompany the IP core
-- instance you have generated.
--
-- This testbench is for demonstration purposes only. See note below for
-- instructions on how to use it with your core.
--
-- See the FIR Compiler product guide for further information
-- about this core.
--
--------------------------------------------------------------------------------
-- Using this testbench
--
-- This testbench instantiates your generated FIR Compiler core
-- instance named "hrc_4_12_03".
--
-- Use Vivado's Run Simulation flow to run this testbench. See the Vivado
-- documentation for details.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_hrc_4_12_03 is
end tb_hrc_4_12_03;
architecture tb of tb_hrc_4_12_03 is
-----------------------------------------------------------------------
-- Timing constants
-----------------------------------------------------------------------
constant CLOCK_PERIOD : time := 100 ns;
constant T_HOLD : time := 10 ns;
constant T_STROBE : time := CLOCK_PERIOD - (1 ns);
-----------------------------------------------------------------------
-- DUT signals
-----------------------------------------------------------------------
-- General signals
signal aclk : std_logic := '0'; -- the master clock
-- Data slave channel signals
signal s_axis_data_tvalid : std_logic := '0'; -- payload is valid
signal s_axis_data_tready : std_logic := '1'; -- slave is ready
signal s_axis_data_tdata : std_logic_vector(7 downto 0) := (others => '0'); -- data payload
-- Data master channel signals
signal m_axis_data_tvalid : std_logic := '0'; -- payload is valid
signal m_axis_data_tdata : std_logic_vector(23 downto 0) := (others => '0'); -- data payload
-----------------------------------------------------------------------
-- Aliases for AXI channel TDATA and TUSER fields
-- These are a convenience for viewing data in a simulator waveform viewer.
-- If using ModelSim or Questa, add "-voptargs=+acc=n" to the vsim command
-- to prevent the simulator optimizing away these signals.
-----------------------------------------------------------------------
-- Data slave channel alias signals
signal s_axis_data_tdata_data : std_logic_vector(1 downto 0) := (others => '0');
-- Data master channel alias signals
signal m_axis_data_tdata_data : std_logic_vector(17 downto 0) := (others => '0');
begin
-----------------------------------------------------------------------
-- Instantiate the DUT
-----------------------------------------------------------------------
dut : entity work.hrc_4_12_03
port map (
aclk => aclk,
s_axis_data_tvalid => s_axis_data_tvalid,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tdata => s_axis_data_tdata,
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tdata => m_axis_data_tdata
);
-----------------------------------------------------------------------
-- Generate clock
-----------------------------------------------------------------------
clock_gen : process
begin
aclk <= '0';
wait for CLOCK_PERIOD;
loop
aclk <= '0';
wait for CLOCK_PERIOD/2;
aclk <= '1';
wait for CLOCK_PERIOD/2;
end loop;
end process clock_gen;
-----------------------------------------------------------------------
-- Generate inputs
-----------------------------------------------------------------------
stimuli : process
-- Procedure to drive a number of input samples with specific data
-- data is the data value to drive on the tdata signal
-- samples is the number of zero-data input samples to drive
procedure drive_data ( data : std_logic_vector(7 downto 0);
samples : natural := 1 ) is
variable ip_count : integer := 0;
begin
ip_count := 0;
loop
s_axis_data_tvalid <= '1';
s_axis_data_tdata <= data;
loop
wait until rising_edge(aclk);
exit when s_axis_data_tready = '1';
end loop;
ip_count := ip_count + 1;
wait for T_HOLD;
exit when ip_count >= samples;
end loop;
end procedure drive_data;
-- Procedure to drive a number of zero-data input samples
-- samples is the number of zero-data input samples to drive
procedure drive_zeros ( samples : natural := 1 ) is
begin
drive_data((others => '0'), samples);
end procedure drive_zeros;
-- Procedure to drive an impulse and let the impulse response emerge on the data master channel
-- samples is the number of input samples to drive; default is enough for impulse response output to emerge
procedure drive_impulse ( samples : natural := 76 ) is
variable impulse : std_logic_vector(7 downto 0);
begin
impulse := (others => '0'); -- initialize unused bits to zero
impulse(1 downto 0) := "01";
drive_data(impulse);
if samples > 1 then
drive_zeros(samples-1);
end if;
end procedure drive_impulse;
begin
-- Drive inputs T_HOLD time after rising edge of clock
wait until rising_edge(aclk);
wait for T_HOLD;
-- Drive a single impulse and let the impulse response emerge
drive_impulse;
-- Drive another impulse, during which demonstrate use and effect of AXI handshaking signals
drive_impulse(2); -- start of impulse; data is now zero
s_axis_data_tvalid <= '0';
wait for CLOCK_PERIOD * 5; -- provide no data for 5 input samples worth
drive_zeros(74); -- back to normal operation
-- End of test
report "Not a real failure. Simulation finished successfully. Test completed successfully" severity failure;
wait;
end process stimuli;
-----------------------------------------------------------------------
-- Check outputs
-----------------------------------------------------------------------
check_outputs : process
variable check_ok : boolean := true;
begin
-- Check outputs T_STROBE time after rising edge of clock
wait until rising_edge(aclk);
wait for T_STROBE;
-- Do not check the output payload values, as this requires the behavioral model
-- which would make this demonstration testbench unwieldy.
-- Instead, check the protocol of the master DATA channel:
-- check that the payload is valid (not X) when TVALID is high
if m_axis_data_tvalid = '1' then
if is_x(m_axis_data_tdata) then
report "ERROR: m_axis_data_tdata is invalid when m_axis_data_tvalid is high" severity error;
check_ok := false;
end if;
end if;
assert check_ok
report "ERROR: terminating test with failures." severity failure;
end process check_outputs;
-----------------------------------------------------------------------
-- Assign TDATA / TUSER fields to aliases, for easy simulator waveform viewing
-----------------------------------------------------------------------
-- Data slave channel alias signals
s_axis_data_tdata_data <= s_axis_data_tdata(1 downto 0);
-- Data master channel alias signals: update these only when they are valid
m_axis_data_tdata_data <= m_axis_data_tdata(17 downto 0) when m_axis_data_tvalid = '1';
end tb;
cx9261a_demo_cmos_20240513/project_fix_dac.srcs/sources_1/ip/hrc_4_12_03/doc/fir_compiler_v7_2_changelog.txt
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2024.1:
* Version 7.2 (Rev. 22)
* Bug Fix: Added Synplicity key
* Other: IP packaging adjustments to address warnings from IP Packager integrity check
* Revision change in one or more subcores
2023.2.2:
* Version 7.2 (Rev. 21)
* Revision change in one or more subcores
2023.2.1:
* Version 7.2 (Rev. 20)
* No changes
2023.2:
* Version 7.2 (Rev. 20)
* Bug Fix: Minor GUI fix to update Output Width range following a change in Coefficient Structure
* Bug Fix: Update half-band interpolation "power of 2" center tap optimization to support symmetric rounding
* Other: Rebrand to AMD copyright information
* Revision change in one or more subcores
2023.1.2:
* Version 7.2 (Rev. 19)
* No changes
2023.1.1:
* Version 7.2 (Rev. 19)
* No changes
2023.1:
* Version 7.2 (Rev. 19)
* General: Device support changes. No change to functionality or performance
2022.2.2:
* Version 7.2 (Rev. 18)
* No changes
2022.2.1:
* Version 7.2 (Rev. 18)
* No changes
2022.2:
* Version 7.2 (Rev. 18)
* No changes
2022.1.2:
* Version 7.2 (Rev. 18)
* No changes
2022.1.1:
* Version 7.2 (Rev. 18)
* No changes
2022.1:
* Version 7.2 (Rev. 18)
* Feature Enhancement: C model MEX wrapper updates to support Octave
2021.2.2:
* Version 7.2 (Rev. 17)
* No changes
2021.2.1:
* Version 7.2 (Rev. 17)
* No changes
2021.2:
* Version 7.2 (Rev. 17)
* Bug Fix: Fixed convergent rounding bug for symmetric polyphase decimators
2021.1.1:
* Version 7.2 (Rev. 16)
* No changes
2021.1:
* Version 7.2 (Rev. 16)
* Bug Fix: Fixed width mismatch issue with SSR single rate extended multiply reload configs
* Other: testbench and constraints updates
2020.3:
* Version 7.2 (Rev. 15)
* No changes
2020.2.2:
* Version 7.2 (Rev. 15)
* No changes
2020.2.1:
* Version 7.2 (Rev. 15)
* No changes
2020.2:
* Version 7.2 (Rev. 15)
* Bug Fix: Fixed incorrect application of symmetry when Interpolation_Rate > clk_freq/samp_freq > 1
* Feature Enhancement: Improved GUI error reporting for designs that don't fit within selected device.
* Other: Windows C model compilation now uses Visual Studio 2017
2020.1.1:
* Version 7.2 (Rev. 14)
* No changes
2020.1:
* Version 7.2 (Rev. 14)
* Bug Fix: Fixed bug with coefficient reload file.
* Bug Fix: Improved error trapping behaviour in the GUI.
* Bug Fix: Fixed simulator specific bug
* Feature Enhancement: Extended Symmetric Coefficient Structures for Interpolation and Decimation Filters with Super Sample Rate.
* Feature Enhancement: Improved the GUI for selecting optimizations.
2019.2.2:
* Version 7.2 (Rev. 13)
* No changes
2019.2.1:
* Version 7.2 (Rev. 13)
* No changes
2019.2:
* Version 7.2 (Rev. 13)
* General: Improved efficiency to C model output. No change to functionality.
2019.1.3:
* Version 7.2 (Rev. 12)
* No changes
2019.1.2:
* Version 7.2 (Rev. 12)
* No changes
2019.1.1:
* Version 7.2 (Rev. 12)
* No changes
2019.1:
* Version 7.2 (Rev. 12)
* Bug Fix: Addressing memory leak in MEX wrapper.
* Bug Fix: Fixed coefficient width range minimum for coefficient file input.
* Bug Fix: Fixed upper bound of Sample Frequency when Advanced Channel Sequence is selected.
* Bug Fix: Fixed C model crash when multiple DSP IP C models are run together: AR 71876
* Other: Support for new devices. No change to exisiting functionality, resource use or performance.
* Revision change in one or more subcores
2018.3.1:
* Version 7.2 (Rev. 11)
* No changes
2018.3:
* Version 7.2 (Rev. 11)
* No changes
2018.2:
* Version 7.2 (Rev. 11)
* No changes
2018.1:
* Version 7.2 (Rev. 11)
* Revision change in one or more subcores
2017.4:
* Version 7.2 (Rev. 10)
* Feature Enhancement: Add option to remove shift register inference attributes; SHREG_EXTRACT and SRL_STYLE
2017.3:
* Version 7.2 (Rev. 9)
* Feature Enhancement: Increase the maximum number of parallel inputs from 64 to 256
* Revision change in one or more subcores
2017.2:
* Version 7.2 (Rev. 8)
* No changes
2017.1:
* Version 7.2 (Rev. 8)
* Bug Fix: Output Rounding Mode parameter validation corrected to produce an error during design validation (IP Integrator/System Generator) rather than silently updating to a legal value.
* Bug Fix: Correction to Convergent Rounding when multiple DSP slices are required to implement the filter multiply operations.
2016.4:
* Version 7.2 (Rev. 7)
* No changes
2016.3:
* Version 7.2 (Rev. 7)
* General: Support for Spartan7 devices
* Revision change in one or more subcores
2016.2:
* Version 7.2 (Rev. 6)
* No changes
2016.1:
* Version 7.2 (Rev. 6)
* Fix for error in Sysgen parameter propagation.
* Enabled DSP48 ADREG/DREG but gate CEAD/CED to address power DRC.
* Fix in common c model utilities package for handling of arrays of real types in Matlab
* Revision change in one or more subcores
2015.4.2:
* Version 7.2 (Rev. 5)
* No changes
2015.4.1:
* Version 7.2 (Rev. 5)
* No changes
2015.4:
* Version 7.2 (Rev. 5)
* Correction to GUI reported Calculated Coefficients for Transpose Interpolation filters.
* Revision change in one or more subcores
2015.3:
* Version 7.2 (Rev. 4)
* Add constraints file to suppress expected memory collision warnings during post-synthesis simulation.
* IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances
* Correction to GUI reported latency estimate for polyphase interpolation configurations.
* Revision change in one or more subcores
2015.2.1:
* Version 7.2 (Rev. 3)
* No changes
2015.2:
* Version 7.2 (Rev. 3)
* Correction to the GUI reported startup latency for polyphase interpolation configurations.
* Correction for Halfband Decimation with Symmetric rounding on Ultrascale parts.
* Correction for Polyphase Interpolation with Convergent rounding where multiple DSP columns are required to support the data and/or coefficient width.
2015.1:
* Version 7.2 (Rev. 2)
* Warning reduction.
* Correction to single rate half-band control for data vector reset, an oversample rate of 2, utilizing a single multiply add unit.
* Added the SRL_STYLE attribute to the delay component to ensure an efficient implementation.
* Fix to Sample Period propagation to avoid false Column Configuration errors.
* GUI filter coefficient processing speed up for bit widths greater than DSP48 input width.
* Addition of Beta support for future devices
* Correction to fractional interpolation configurations utilizing Maximium Possible hardware oversampling specification in System Generator.
* Update to C model to match GUI behaviour. Add support for quantization/truncation of integer only coefficients when XIP_FIR_QUANTIZED_ONLY has been specified.
* Supported devices and production status are now determined automatically, to simplify support for future devices
* C models are no longer provided for 32-bit operating systems as Vivado has deprecated 32-bit OS support
2014.4.1:
* Version 7.2 (Rev. 1)
* No changes
2014.4:
* Version 7.2 (Rev. 1)
* Fix for UltraScale Halfband Interpolation optimization with Convergent Rounding and multiple parallel paths.
* C Model maximum data and coefficient widths updated for UltraScale.
* Correction to GUI latency calculation.
* Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
* Add 1 x fs Advanced Channel Sequence to sequence length 24.
* Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interface aclk_intf
2014.3:
* Version 7.2
* Optimized Halfband filter support for UltraScale devices.
* Super sample rate support.
* Enhanced Hardware Oversampling specification methods. Now supports input and output sample period specification.
* CONFIG channel behavior has been updated for the Packet Synchronization method (On Packet) following power up or reset.
2014.2:
* Version 7.1 (Rev. 4)
* Removed component statement for DSP48E2, no functional changes
2014.1:
* Version 7.1 (Rev. 3)
* C models for Windows are compiled using Microsoft Visual Studio 2012
* Internal device family name change, no functional changes
* Netlists created by write_verilog and write_vhdl are IEEE P1735 encrypted, with keys for supported simulators so that netlist simulation can still be done
* Enable third party synthesis tools to read encrypted netlists (but not source HDL)
* Fixed AR58946, COE file coefficient specification now working correctly in IP Integrator.
* Support for Virtex Ultrascale devices at Pre-Production Status
2013.4:
* Version 7.1 (Rev. 2)
* Added workaround to the GUI for AR57785
* Support for Kintex Ultrascale devices at Pre-Production Status
2013.3:
* Version 7.1 (Rev. 1)
* Behavioral VHDL model replaced by Encrypted RTL. For more information on this change please refer to the Migrating and Upgrading section in the Product Guide
* Internal standardization in source file delivery, does not change behavior
* Support for Automotive Artix-7, Automotive Zynq, Defense Grade Artix-7, Defense Grade Zynq and Lower Power Artix-7 devices at Production Status
* Added default constraints for out of context flow
* Optimized support for UltraScale devices
* Added support for Cadence IES and Synopsys VCS simulators
* Removed C model dependency on stlport (STL Portability) library; C model now uses STL built into the compiler
* Windows C model DLLs are statically linked to the Windows C run-time (CRT) library, to remove the runtime dependency on MSVCRT90.dll, which can cause problems when using the C model in a Windows compiler other than Visual Studio 2008
* C model updated to use third-party library MPIR version 2.6.0 (previously was version 2.2.1); the Windows MPIR DLLs are also statically linked to the Windows CRT library, to remove the dependency on MSVCRT90.dll
2013.2:
* Version 7.1
* Support for Series 7 devices at Production status
* Beta support for future devices
* Enhanced Optimization specification including optional use of Block RAM READ-FIRST mode
* Maximum interleaved channels increased to 1024
* Bug Fixes
2013.1:
* Version 7.0
* Native Vivado Release
* There have been no functional or interface changes to this IP. The version number has changed to support unique versioning in Vivado starting with 2013.1.
(c) Copyright 2002 - 2024 Advanced Micro Devices, Inc. All rights reserved.
This file contains confidential and proprietary information
of AMD and is protected under U.S. and international copyright
and other intellectual property laws.
DISCLAIMER
This disclaimer is not a license and does not grant any
rights to the materials distributed herewith. Except as
otherwise provided in a valid license issued to you by
AMD, and to the maximum extent permitted by applicable
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
(2) AMD shall not be liable (whether in contract or tort,
including negligence, or under any other theory of
liability) for any loss or damage of any kind or nature
related to, arising under or in connection with these
materials, including for any direct, or any indirect,
special, incidental, or consequential loss or damage
(including loss of data, profits, goodwill, or any type of
loss or damage suffered as a result of any action brought
by a third party) even if such damage or loss was
reasonably foreseeable or AMD had been advised of the
possibility of the same.
CRITICAL APPLICATIONS
AMD products are not designed or intended to be fail-
safe, or for use in any application requiring fail-safe
performance, such as life-support or safety devices or
systems, Class III medical devices, nuclear facilities,
applications related to the deployment of airbags, or any
other applications that could lead to death, personal
injury, or severe property or environmental damage
(individually and collectively, "Critical
Applications"). Customer assumes the sole risk and
liability of any use of AMD products in Critical
Applications, subject only to applicable laws and
regulations governing limitations on product liability.
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
PART OF THIS FILE AT ALL TIMES.
cx9261a_demo_cmos_20240513/project_fix_dac.srcs/sources_1/ip/hrc_4_12_03/hdl/axi_utils_v2_0_vh_rfs.vhd
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cx9261a_demo_cmos_20240513/project_fix_dac.srcs/sources_1/ip/hrc_4_12_03/hrc_4_12_03.mif
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ffffff35 0 0 0 0 0 0
00000127 0 0 0 0 3 0
00000105 0 0 0 0 2 0
00000011 0 0 0 0 1 0
00000037 0 1 0 0 4 0
ffffffd5 0 1 0 0 7 0
fffffeb5 0 1 0 0 6 0
fffffefe 0 1 0 0 5 0
00000168 0 2 0 0 8 0
fffffcf6 0 2 0 0 11 0
ffffffc9 0 2 0 0 10 0
000001b0 0 2 0 0 9 0
fffffc15 0 3 0 0 12 0
00000993 0 3 0 0 15 0
00000553 0 3 0 0 14 0
ffffff42 0 3 0 0 13 0
000006b2 0 4 0 0 16 0
ffffe8f2 0 4 0 0 19 0
ffffedd4 0 4 0 0 18 0
fffffb7e 0 4 0 0 17 0
fffff721 0 5 0 0 20 0
0000706e 0 5 0 0 23 0
000048cb 0 5 0 0 22 0
00001a58 0 5 0 0 21 0
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00001a58 0 6 0 0 27 0
000048cb 0 6 0 0 26 0
0000706e 0 6 0 0 25 0
fffff721 0 7 0 0 28 0
fffffb7e 0 7 0 0 31 0
ffffedd4 0 7 0 0 30 0
ffffe8f2 0 7 0 0 29 0
000006b2 0 8 0 0 32 0
ffffff42 0 8 0 0 35 0
00000553 0 8 0 0 34 0
00000993 0 8 0 0 33 0
fffffc15 0 9 0 0 36 0
000001b0 0 9 0 0 39 0
ffffffc9 0 9 0 0 38 0
fffffcf6 0 9 0 0 37 0
00000168 0 10 0 0 40 0
fffffefe 0 10 0 0 43 0
fffffeb5 0 10 0 0 42 0
ffffffd5 0 10 0 0 41 0
00000037 0 11 0 0 44 0
00000011 0 11 0 0 47 0
00000105 0 11 0 0 46 0
00000127 0 11 0 0 45 0
ffffff35 0 12 0 0 48 0
00000000 0 12 0 0 51 0
00000000 0 12 0 0 50 0
00000000 0 12 0 0 49 0
cx9261a_demo_cmos_20240513/project_fix_dac.srcs/sources_1/ip/hrc_4_12_03/hrc_4_12_03.veo
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// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of AMD and is protected under U.S. and international copyright
// and other intellectual property laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// AMD, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) AMD shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or AMD had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// AMD products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of AMD products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:fir_compiler:7.2
// IP Revision: 22
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
hrc_4_12_03 your_instance_name (
.aclk(aclk), // input wire aclk
.s_axis_data_tvalid(s_axis_data_tvalid), // input wire s_axis_data_tvalid
.s_axis_data_tready(s_axis_data_tready), // output wire s_axis_data_tready
.s_axis_data_tdata(s_axis_data_tdata), // input wire [7 : 0] s_axis_data_tdata
.m_axis_data_tvalid(m_axis_data_tvalid), // output wire m_axis_data_tvalid
.m_axis_data_tdata(m_axis_data_tdata) // output wire [23 : 0] m_axis_data_tdata
);
// INST_TAG_END ------ End INSTANTIATION Template ---------
// You must compile the wrapper file hrc_4_12_03.v when simulating
// the core, hrc_4_12_03. When compiling the wrapper file, be sure to
// reference the Verilog simulation library.
cx9261a_demo_cmos_20240513/project_fix_dac.srcs/sources_1/ip/hrc_4_12_03/hrc_4_12_03.vho
+86
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@@ -0,0 +1,86 @@
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of AMD and is protected under U.S. and international copyright
-- and other intellectual property laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- AMD, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) AMD shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or AMD had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- AMD products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of AMD products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fir_compiler:7.2
-- IP Revision: 22
-- The following code must appear in the VHDL architecture header.
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
COMPONENT hrc_4_12_03
PORT (
aclk : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END COMPONENT;
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
-- The following code must appear in the VHDL architecture
-- body. Substitute your own instance name and net names.
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
your_instance_name : hrc_4_12_03
PORT MAP (
aclk => aclk,
s_axis_data_tvalid => s_axis_data_tvalid,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tdata => s_axis_data_tdata,
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tdata => m_axis_data_tdata
);
-- INST_TAG_END ------ End INSTANTIATION Template ---------
-- You must compile the wrapper file hrc_4_12_03.vhd when simulating
-- the core, hrc_4_12_03. When compiling the wrapper file, be sure to
-- reference the VHDL simulation library.
cx9261a_demo_cmos_20240513/project_fix_dac.srcs/sources_1/ip/hrc_4_12_03/hrc_4_12_03.xci
+350
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@@ -0,0 +1,350 @@
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"s_axis_data_tdata": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
"m_axis_data_tvalid": [ { "direction": "out", "driver_value": "0x0" } ],
"m_axis_data_tdata": [ { "direction": "out", "size_left": "23", "size_right": "0", "driver_value": "0" } ]
},
"interfaces": {
"event_s_data_tlast_missing_intf": {
"vlnv": "xilinx.com:signal:interrupt:1.0",
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
"mode": "master",
"parameters": {
"SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
"PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
}
},
"event_s_data_tlast_unexpected_intf": {
"vlnv": "xilinx.com:signal:interrupt:1.0",
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
"mode": "master",
"parameters": {
"SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
"PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
}
},
"event_s_data_chanid_incorrect_intf": {
"vlnv": "xilinx.com:signal:interrupt:1.0",
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
"mode": "master",
"parameters": {
"SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
"PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
}
},
"event_s_config_tlast_missing_intf": {
"vlnv": "xilinx.com:signal:interrupt:1.0",
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
"mode": "master",
"parameters": {
"SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
"PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
}
},
"event_s_config_tlast_unexpected_intf": {
"vlnv": "xilinx.com:signal:interrupt:1.0",
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
"mode": "master",
"parameters": {
"SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
"PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
}
},
"event_s_reload_tlast_missing_intf": {
"vlnv": "xilinx.com:signal:interrupt:1.0",
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
"mode": "master",
"parameters": {
"SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
"PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
}
},
"event_s_reload_tlast_unexpected_intf": {
"vlnv": "xilinx.com:signal:interrupt:1.0",
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
"mode": "master",
"parameters": {
"SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
"PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
}
},
"aclk_intf": {
"vlnv": "xilinx.com:signal:clock:1.0",
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
"mode": "slave",
"parameters": {
"ASSOCIATED_BUSIF": [ { "value": "S_AXIS_CONFIG:M_AXIS_DATA:S_AXIS_DATA:S_AXIS_RELOAD", "value_src": "constant", "usage": "all" } ],
"ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "usage": "all" } ],
"ASSOCIATED_CLKEN": [ { "value": "aclken", "value_src": "constant", "usage": "all" } ],
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"CLK": [ { "physical_name": "aclk" } ]
}
},
"aresetn_intf": {
"vlnv": "xilinx.com:signal:reset:1.0",
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
"mode": "slave",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
}
},
"aclken_intf": {
"vlnv": "xilinx.com:signal:clockenable:1.0",
"abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0",
"mode": "slave",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ]
}
},
"S_AXIS_DATA": {
"vlnv": "xilinx.com:interface:axis:1.0",
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
"mode": "slave",
"parameters": {
"TDATA_NUM_BYTES": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"TDATA": [ { "physical_name": "s_axis_data_tdata" } ],
"TREADY": [ { "physical_name": "s_axis_data_tready" } ],
"TVALID": [ { "physical_name": "s_axis_data_tvalid" } ]
}
},
"M_AXIS_DATA": {
"vlnv": "xilinx.com:interface:axis:1.0",
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
"mode": "master",
"parameters": {
"TDATA_NUM_BYTES": [ { "value": "3", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"TDATA": [ { "physical_name": "m_axis_data_tdata" } ],
"TVALID": [ { "physical_name": "m_axis_data_tvalid" } ]
}
}
}
}
}
}
cx9261a_demo_cmos_20240513/project_fix_dac.srcs/sources_1/ip/hrc_4_12_03/hrc_4_12_03.xml
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# (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
# (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of AMD and is protected under U.S. and international copyright
# and other intellectual property laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# AMD, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) AMD shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or AMD had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# AMD products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of AMD products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#
# DO NOT MODIFY THIS FILE.
# #########################################################
#
# This XDC is used only in OOC mode for synthesis, implementation
#
# #########################################################
create_clock -period 10 -name aclk [get_ports aclk]
cx9261a_demo_cmos_20240513/project_fix_dac.srcs/sources_1/ip/hrc_4_12_03/hrc_4_12_03_sim_netlist.v
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// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
// Date : Fri Nov 1 13:02:46 2024
// Host : gatsby-dev running 64-bit Red Hat Enterprise Linux release 8.10 (Ootpa)
// Command : write_verilog -force -mode synth_stub
// /home/josh/Workspace/vivado/brd_cx2161a/zc706_cx9261a_demo/zc706_cx9261a_demo.gen/sources_1/ip/hrc_4_12_03/hrc_4_12_03_stub.v
// Design : hrc_4_12_03
// Purpose : Stub declaration of top-level module interface
// Device : xc7z045ffg900-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "fir_compiler_v7_2_22,Vivado 2024.1" *)
module hrc_4_12_03(aclk, s_axis_data_tvalid, s_axis_data_tready,
s_axis_data_tdata, m_axis_data_tvalid, m_axis_data_tdata)
/* synthesis syn_black_box black_box_pad_pin="s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[7:0],m_axis_data_tvalid,m_axis_data_tdata[23:0]" */
/* synthesis syn_force_seq_prim="aclk" */;
input aclk /* synthesis syn_isclock = 1 */;
input s_axis_data_tvalid;
output s_axis_data_tready;
input [7:0]s_axis_data_tdata;
output m_axis_data_tvalid;
output [23:0]m_axis_data_tdata;
endmodule
cx9261a_demo_cmos_20240513/project_fix_dac.srcs/sources_1/ip/hrc_4_12_03/hrc_4_12_03_stub.vhdl
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-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
-- Date : Fri Nov 1 13:02:47 2024
-- Host : gatsby-dev running 64-bit Red Hat Enterprise Linux release 8.10 (Ootpa)
-- Command : write_vhdl -force -mode synth_stub
-- /home/josh/Workspace/vivado/brd_cx2161a/zc706_cx9261a_demo/zc706_cx9261a_demo.gen/sources_1/ip/hrc_4_12_03/hrc_4_12_03_stub.vhdl
-- Design : hrc_4_12_03
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z045ffg900-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity hrc_4_12_03 is
Port (
aclk : in STD_LOGIC;
s_axis_data_tvalid : in STD_LOGIC;
s_axis_data_tready : out STD_LOGIC;
s_axis_data_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_data_tvalid : out STD_LOGIC;
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
end hrc_4_12_03;
architecture stub of hrc_4_12_03 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[7:0],m_axis_data_tvalid,m_axis_data_tdata[23:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "fir_compiler_v7_2_22,Vivado 2024.1";
begin
end;
cx9261a_demo_cmos_20240513/project_fix_dac.srcs/sources_1/ip/hrc_4_12_03/sim/hrc_4_12_03.vhd
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-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of AMD and is protected under U.S. and international copyright
-- and other intellectual property laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- AMD, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) AMD shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or AMD had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- AMD products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of AMD products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fir_compiler:7.2
-- IP Revision: 22
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fir_compiler_v7_2_22;
USE fir_compiler_v7_2_22.fir_compiler_v7_2_22;
ENTITY hrc_4_12_03 IS
PORT (
aclk : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END hrc_4_12_03;
ARCHITECTURE hrc_4_12_03_arch OF hrc_4_12_03 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF hrc_4_12_03_arch: ARCHITECTURE IS "yes";
COMPONENT fir_compiler_v7_2_22 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_COMPONENT_NAME : STRING;
C_COEF_FILE : STRING;
C_COEF_FILE_LINES : INTEGER;
C_FILTER_TYPE : INTEGER;
C_INTERP_RATE : INTEGER;
C_DECIM_RATE : INTEGER;
C_ZERO_PACKING_FACTOR : INTEGER;
C_SYMMETRY : INTEGER;
C_NUM_FILTS : INTEGER;
C_NUM_TAPS : INTEGER;
C_NUM_CHANNELS : INTEGER;
C_CHANNEL_PATTERN : STRING;
C_ROUND_MODE : INTEGER;
C_COEF_RELOAD : INTEGER;
C_NUM_RELOAD_SLOTS : INTEGER;
C_COL_MODE : INTEGER;
C_COL_PIPE_LEN : INTEGER;
C_COL_CONFIG : STRING;
C_OPTIMIZATION : INTEGER;
C_DATA_PATH_WIDTHS : STRING;
C_DATA_IP_PATH_WIDTHS : STRING;
C_DATA_PX_PATH_WIDTHS : STRING;
C_DATA_WIDTH : INTEGER;
C_COEF_PATH_WIDTHS : STRING;
C_COEF_WIDTH : INTEGER;
C_DATA_PATH_SRC : STRING;
C_COEF_PATH_SRC : STRING;
C_PX_PATH_SRC : STRING;
C_DATA_PATH_SIGN : STRING;
C_COEF_PATH_SIGN : STRING;
C_ACCUM_PATH_WIDTHS : STRING;
C_OUTPUT_WIDTH : INTEGER;
C_OUTPUT_PATH_WIDTHS : STRING;
C_ACCUM_OP_PATH_WIDTHS : STRING;
C_EXT_MULT_CNFG : STRING;
C_DATA_PATH_PSAMP_SRC : STRING;
C_OP_PATH_PSAMP_SRC : STRING;
C_NUM_MADDS : INTEGER;
C_OPT_MADDS : STRING;
C_OVERSAMPLING_RATE : INTEGER;
C_INPUT_RATE : INTEGER;
C_OUTPUT_RATE : INTEGER;
C_DATA_MEMTYPE : INTEGER;
C_COEF_MEMTYPE : INTEGER;
C_IPBUFF_MEMTYPE : INTEGER;
C_OPBUFF_MEMTYPE : INTEGER;
C_DATAPATH_MEMTYPE : INTEGER;
C_MEM_ARRANGEMENT : INTEGER;
C_DATA_MEM_PACKING : INTEGER;
C_COEF_MEM_PACKING : INTEGER;
C_FILTS_PACKED : INTEGER;
C_LATENCY : INTEGER;
C_HAS_ARESETn : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_DATA_HAS_TLAST : INTEGER;
C_S_DATA_HAS_FIFO : INTEGER;
C_S_DATA_HAS_TUSER : INTEGER;
C_S_DATA_TDATA_WIDTH : INTEGER;
C_S_DATA_TUSER_WIDTH : INTEGER;
C_M_DATA_HAS_TREADY : INTEGER;
C_M_DATA_HAS_TUSER : INTEGER;
C_M_DATA_TDATA_WIDTH : INTEGER;
C_M_DATA_TUSER_WIDTH : INTEGER;
C_HAS_CONFIG_CHANNEL : INTEGER;
C_CONFIG_SYNC_MODE : INTEGER;
C_CONFIG_PACKET_SIZE : INTEGER;
C_CONFIG_TDATA_WIDTH : INTEGER;
C_RELOAD_TDATA_WIDTH : INTEGER
);
PORT (
aresetn : IN STD_LOGIC;
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tlast : IN STD_LOGIC;
s_axis_data_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_data_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_config_tvalid : IN STD_LOGIC;
s_axis_config_tready : OUT STD_LOGIC;
s_axis_config_tlast : IN STD_LOGIC;
s_axis_config_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_reload_tvalid : IN STD_LOGIC;
s_axis_reload_tready : OUT STD_LOGIC;
s_axis_reload_tlast : IN STD_LOGIC;
s_axis_reload_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tready : IN STD_LOGIC;
m_axis_data_tlast : OUT STD_LOGIC;
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
event_s_data_tlast_missing : OUT STD_LOGIC;
event_s_data_tlast_unexpected : OUT STD_LOGIC;
event_s_data_chanid_incorrect : OUT STD_LOGIC;
event_s_config_tlast_missing : OUT STD_LOGIC;
event_s_config_tlast_unexpected : OUT STD_LOGIC;
event_s_reload_tlast_missing : OUT STD_LOGIC;
event_s_reload_tlast_unexpected : OUT STD_LOGIC
);
END COMPONENT fir_compiler_v7_2_22;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF aclk: SIGNAL IS "XIL_INTERFACENAME aclk_intf, ASSOCIATED_BUSIF S_AXIS_CONFIG:M_AXIS_DATA:S_AXIS_DATA:S_AXIS_RELOAD, ASSOCIATED_RESET aresetn, ASSOCIATED_CLKEN aclken, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axis_data_tvalid: SIGNAL IS "XIL_INTERFACENAME M_AXIS_DATA, TDATA_NUM_BYTES 3, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TREADY";
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_data_tvalid: SIGNAL IS "XIL_INTERFACENAME S_AXIS_DATA, TDATA_NUM_BYTES 1, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TVALID";
BEGIN
U0 : fir_compiler_v7_2_22
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_COMPONENT_NAME => "hrc_4_12_03",
C_COEF_FILE => "hrc_4_12_03.mif",
C_COEF_FILE_LINES => 52,
C_FILTER_TYPE => 2,
C_INTERP_RATE => 4,
C_DECIM_RATE => 3,
C_ZERO_PACKING_FACTOR => 1,
C_SYMMETRY => 0,
C_NUM_FILTS => 1,
C_NUM_TAPS => 49,
C_NUM_CHANNELS => 1,
C_CHANNEL_PATTERN => "fixed",
C_ROUND_MODE => 0,
C_COEF_RELOAD => 0,
C_NUM_RELOAD_SLOTS => 1,
C_COL_MODE => 1,
C_COL_PIPE_LEN => 4,
C_COL_CONFIG => "13",
C_OPTIMIZATION => 0,
C_DATA_PATH_WIDTHS => "2",
C_DATA_IP_PATH_WIDTHS => "2",
C_DATA_PX_PATH_WIDTHS => "2",
C_DATA_WIDTH => 2,
C_COEF_PATH_WIDTHS => "16",
C_COEF_WIDTH => 16,
C_DATA_PATH_SRC => "0",
C_COEF_PATH_SRC => "0",
C_PX_PATH_SRC => "0",
C_DATA_PATH_SIGN => "0",
C_COEF_PATH_SIGN => "0",
C_ACCUM_PATH_WIDTHS => "18",
C_OUTPUT_WIDTH => 18,
C_OUTPUT_PATH_WIDTHS => "18",
C_ACCUM_OP_PATH_WIDTHS => "18",
C_EXT_MULT_CNFG => "none",
C_DATA_PATH_PSAMP_SRC => "0",
C_OP_PATH_PSAMP_SRC => "0",
C_NUM_MADDS => 13,
C_OPT_MADDS => "none",
C_OVERSAMPLING_RATE => 1,
C_INPUT_RATE => 1,
C_OUTPUT_RATE => 1,
C_DATA_MEMTYPE => 0,
C_COEF_MEMTYPE => 2,
C_IPBUFF_MEMTYPE => 0,
C_OPBUFF_MEMTYPE => 0,
C_DATAPATH_MEMTYPE => 0,
C_MEM_ARRANGEMENT => 2,
C_DATA_MEM_PACKING => 0,
C_COEF_MEM_PACKING => 0,
C_FILTS_PACKED => 0,
C_LATENCY => 19,
C_HAS_ARESETn => 0,
C_HAS_ACLKEN => 0,
C_DATA_HAS_TLAST => 0,
C_S_DATA_HAS_FIFO => 1,
C_S_DATA_HAS_TUSER => 0,
C_S_DATA_TDATA_WIDTH => 8,
C_S_DATA_TUSER_WIDTH => 1,
C_M_DATA_HAS_TREADY => 0,
C_M_DATA_HAS_TUSER => 0,
C_M_DATA_TDATA_WIDTH => 24,
C_M_DATA_TUSER_WIDTH => 1,
C_HAS_CONFIG_CHANNEL => 0,
C_CONFIG_SYNC_MODE => 0,
C_CONFIG_PACKET_SIZE => 0,
C_CONFIG_TDATA_WIDTH => 1,
C_RELOAD_TDATA_WIDTH => 1
)
PORT MAP (
aresetn => '1',
aclk => aclk,
aclken => '1',
s_axis_data_tvalid => s_axis_data_tvalid,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tlast => '0',
s_axis_data_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_data_tdata => s_axis_data_tdata,
s_axis_config_tvalid => '0',
s_axis_config_tlast => '0',
s_axis_config_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_reload_tvalid => '0',
s_axis_reload_tlast => '0',
s_axis_reload_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tready => '1',
m_axis_data_tdata => m_axis_data_tdata
);
END hrc_4_12_03_arch;

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