feat: 新增工程,由20241025技术支持包中的coms工程upgrade得到,发端修改为演示验证QPSK
This commit is contained in:
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################ 1 #CX9261A Interface PACKAGE_PIN and IOStandard constraints####################
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############CX9261A SPI and Control pin Interface##############
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set_property PACKAGE_PIN V28 [get_ports SCLK ]
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set_property PACKAGE_PIN V29 [get_ports CSB ]
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set_property PACKAGE_PIN T28 [get_ports SDO ]
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set_property PACKAGE_PIN R28 [get_ports SDIO ]
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set_property PACKAGE_PIN N27 [get_ports NRST ]
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set_property PACKAGE_PIN U26 [get_ports OSC_OUT ]
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set_property PACKAGE_PIN P26 [get_ports ENABLE_TRX2]
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set_property PACKAGE_PIN P25 [get_ports ENABLE_TRX1]
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set_property PACKAGE_PIN N26 [get_ports ENABLE_RXFB]
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set_property PACKAGE_PIN P29 [get_ports TXNRX_TRX1 ]
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set_property PACKAGE_PIN N29 [get_ports TXNRX_TRX2 ]
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set_property PACKAGE_PIN U27 [get_ports TXNRX_RXFB ]
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set_property IOSTANDARD LVCMOS25 [get_ports SCLK ]
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set_property IOSTANDARD LVCMOS25 [get_ports CSB ]
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set_property IOSTANDARD LVCMOS25 [get_ports SDO ]
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set_property IOSTANDARD LVCMOS25 [get_ports SDIO ]
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set_property IOSTANDARD LVCMOS25 [get_ports NRST ]
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set_property IOSTANDARD LVCMOS25 [get_ports OSC_OUT ]
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set_property IOSTANDARD LVCMOS25 [get_ports ENABLE_TRX1]
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set_property IOSTANDARD LVCMOS25 [get_ports ENABLE_TRX2]
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set_property IOSTANDARD LVCMOS25 [get_ports ENABLE_RXFB]
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set_property IOSTANDARD LVCMOS25 [get_ports TXNRX_TRX1 ]
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set_property IOSTANDARD LVCMOS25 [get_ports TXNRX_TRX2 ]
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set_property IOSTANDARD LVCMOS25 [get_ports TXNRX_RXFB ]
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###############################################################
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####################CX9261A data Interface#####################
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set_property PACKAGE_PIN W25 [get_ports RXFB_MCLK_IN ]
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set_property PACKAGE_PIN W26 [get_ports RXFB_FRAME_IN ]
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set_property PACKAGE_PIN AF22 [get_ports RX1_MCLK_IN_N ]
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set_property PACKAGE_PIN AE22 [get_ports RX2_MCLK_IN_P ]
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set_property PACKAGE_PIN AH24 [get_ports RX1_FRAME_IN_N ]
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set_property PACKAGE_PIN AH23 [get_ports RX2_FRAME_IN_P ]
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set_property PACKAGE_PIN R26 [get_ports TX1_FCLK_OUT_N ]
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set_property PACKAGE_PIN R25 [get_ports TX2_FCLK_OUT_P ]
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set_property PACKAGE_PIN T25 [get_ports TX1_FRAME_OUT_N ]
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set_property PACKAGE_PIN T24 [get_ports TX2_FRAME_OUT_P ]
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set_property PACKAGE_PIN P30 [get_ports {RXFB_RX_DATA[7]}]
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set_property PACKAGE_PIN R30 [get_ports {RXFB_RX_DATA[6]}]
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set_property PACKAGE_PIN P23 [get_ports {RXFB_RX_DATA[5]}]
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set_property PACKAGE_PIN P24 [get_ports {RXFB_RX_DATA[4]}]
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set_property PACKAGE_PIN P21 [get_ports {RXFB_RX_DATA[3]}]
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set_property PACKAGE_PIN R21 [get_ports {RXFB_RX_DATA[2]}]
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set_property PACKAGE_PIN W29 [get_ports {RXFB_RX_DATA[1]}]
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set_property PACKAGE_PIN W30 [get_ports {RXFB_RX_DATA[0]}]
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set_property PACKAGE_PIN U25 [get_ports {RXFB_TX_DATA[7]}]
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set_property PACKAGE_PIN V26 [get_ports {RXFB_TX_DATA[6]}]
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set_property PACKAGE_PIN V27 [get_ports {RXFB_TX_DATA[5]}]
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set_property PACKAGE_PIN W28 [get_ports {RXFB_TX_DATA[4]}]
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set_property PACKAGE_PIN T29 [get_ports {RXFB_TX_DATA[3]}]
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set_property PACKAGE_PIN U29 [get_ports {RXFB_TX_DATA[2]}]
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set_property PACKAGE_PIN T30 [get_ports {RXFB_TX_DATA[1]}]
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set_property PACKAGE_PIN U30 [get_ports {RXFB_TX_DATA[0]}]
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set_property PACKAGE_PIN AH19 [get_ports {RX1_FDD_DATA[7]}]
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set_property PACKAGE_PIN AJ19 [get_ports {RX1_FDD_DATA[6]}]
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set_property PACKAGE_PIN AF19 [get_ports {RX1_FDD_DATA[5]}]
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set_property PACKAGE_PIN AG19 [get_ports {RX1_FDD_DATA[4]}]
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set_property PACKAGE_PIN AF23 [get_ports {RX1_FDD_DATA[3]}]
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set_property PACKAGE_PIN AF24 [get_ports {RX1_FDD_DATA[2]}]
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set_property PACKAGE_PIN AA24 [get_ports {RX1_FDD_DATA[1]}]
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set_property PACKAGE_PIN AB24 [get_ports {RX1_FDD_DATA[0]}]
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set_property PACKAGE_PIN Y22 [get_ports {RX2_FDD_DATA[7]}]
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set_property PACKAGE_PIN Y23 [get_ports {RX2_FDD_DATA[6]}]
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set_property PACKAGE_PIN AC24 [get_ports {RX2_FDD_DATA[5]}]
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set_property PACKAGE_PIN AD24 [get_ports {RX2_FDD_DATA[4]}]
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set_property PACKAGE_PIN AG24 [get_ports {RX2_FDD_DATA[3]}]
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set_property PACKAGE_PIN AG25 [get_ports {RX2_FDD_DATA[2]}]
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set_property PACKAGE_PIN AF20 [get_ports {RX2_FDD_DATA[1]}]
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set_property PACKAGE_PIN AG20 [get_ports {RX2_FDD_DATA[0]}]
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set_property PACKAGE_PIN AG22 [get_ports {TX1_FDD_DATA[7]}]
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set_property PACKAGE_PIN AH22 [get_ports {TX1_FDD_DATA[6]}]
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set_property PACKAGE_PIN AA22 [get_ports {TX1_FDD_DATA[5]}]
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set_property PACKAGE_PIN AA23 [get_ports {TX1_FDD_DATA[4]}]
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set_property PACKAGE_PIN AG21 [get_ports {TX1_FDD_DATA[3]}]
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set_property PACKAGE_PIN AH21 [get_ports {TX1_FDD_DATA[2]}]
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set_property PACKAGE_PIN AD21 [get_ports {TX1_FDD_DATA[1]}]
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set_property PACKAGE_PIN AE21 [get_ports {TX1_FDD_DATA[0]}]
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set_property PACKAGE_PIN AK17 [get_ports {TX2_FDD_DATA[7]}]
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set_property PACKAGE_PIN AK18 [get_ports {TX2_FDD_DATA[6]}]
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set_property PACKAGE_PIN AJ20 [get_ports {TX2_FDD_DATA[5]}]
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set_property PACKAGE_PIN AK20 [get_ports {TX2_FDD_DATA[4]}]
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set_property PACKAGE_PIN AJ23 [get_ports {TX2_FDD_DATA[3]}]
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set_property PACKAGE_PIN AJ24 [get_ports {TX2_FDD_DATA[2]}]
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set_property PACKAGE_PIN AD23 [get_ports {TX2_FDD_DATA[1]}]
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set_property PACKAGE_PIN AE23 [get_ports {TX2_FDD_DATA[0]}]
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set_property IOSTANDARD LVCMOS25 [get_ports RXFB_MCLK_IN ]
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set_property IOSTANDARD LVCMOS25 [get_ports RXFB_FRAME_IN ]
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set_property IOSTANDARD LVCMOS25 [get_ports RX1_MCLK_IN_N ]
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set_property IOSTANDARD LVCMOS25 [get_ports RX2_MCLK_IN_P ]
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set_property IOSTANDARD LVCMOS25 [get_ports RX1_FRAME_IN_N ]
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set_property IOSTANDARD LVCMOS25 [get_ports RX2_FRAME_IN_P ]
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set_property IOSTANDARD LVCMOS25 [get_ports TX1_FCLK_OUT_N ]
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set_property IOSTANDARD LVCMOS25 [get_ports TX2_FCLK_OUT_P ]
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set_property IOSTANDARD LVCMOS25 [get_ports TX1_FRAME_OUT_N ]
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set_property IOSTANDARD LVCMOS25 [get_ports TX2_FRAME_OUT_P ]
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set_property IOSTANDARD LVCMOS25 [get_ports {RXFB_RX_DATA[*]}]
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set_property IOSTANDARD LVCMOS25 [get_ports {RXFB_TX_DATA[*]}]
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set_property IOSTANDARD LVCMOS25 [get_ports {RX1_FDD_DATA[*]}]
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set_property IOSTANDARD LVCMOS25 [get_ports {RX2_FDD_DATA[*]}]
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set_property IOSTANDARD LVCMOS25 [get_ports {TX1_FDD_DATA[*]}]
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set_property IOSTANDARD LVCMOS25 [get_ports {TX2_FDD_DATA[*]}]
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###############################################################
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################################################################################################
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########### 2 #CX3E04 and Debug Interface PACKAGE_PIN and IOStandard constraints################
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######################CX3E04 Interface#########################
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set_property PACKAGE_PIN W23 [get_ports CX3E04_NRST ]
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set_property PACKAGE_PIN AJ25 [get_ports CX3E04_CSB ]
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set_property PACKAGE_PIN AK25 [get_ports CX3E04_SDIO ]
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set_property PACKAGE_PIN AK22 [get_ports CX3E04_SCLK ]
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set_property IOSTANDARD LVCMOS25 [get_ports CX3E04_NRST ]
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set_property IOSTANDARD LVCMOS25 [get_ports CX3E04_CSB ]
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set_property IOSTANDARD LVCMOS25 [get_ports CX3E04_SDIO ]
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set_property IOSTANDARD LVCMOS25 [get_ports CX3E04_SCLK ]
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set_property PACKAGE_PIN AE28 [get_ports CX3E04_CLK_P ]
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set_property PACKAGE_PIN AF28 [get_ports CX3E04_CLK_N ]
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set_property PACKAGE_PIN AC29 [get_ports CX3E04_SYNC_P]
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set_property PACKAGE_PIN AD29 [get_ports CX3E04_SYNC_N]
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set_property IOSTANDARD LVDS_25 [get_ports CX3E04_CLK_P ]
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set_property IOSTANDARD LVDS_25 [get_ports CX3E04_CLK_N ]
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set_property IOSTANDARD LVDS_25 [get_ports CX3E04_SYNC_P]
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set_property IOSTANDARD LVDS_25 [get_ports CX3E04_SYNC_N]
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###############################################################
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######################Debug Interface##########################
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#set_property PACKAGE_PIN AD18 [get_ports power_on_trigger]
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#set_property IOSTANDARD LVCMOS25 [get_ports power_on_trigger]
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###############################################################
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################################################################################################
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################# 3 #clock Period/Route and hardcore Position constraints#######################
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create_clock -period 6.25 -name RX1_MCLK_IN_N -waveform {0.000 3.125} [get_ports RX1_MCLK_IN_N]
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create_clock -period 6.25 -name RX2_MCLK_IN_P -waveform {0.000 3.125} [get_ports RX2_MCLK_IN_P]
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create_clock -period 6.25 -name RXFB_MCLK_IN -waveform {0.000 3.125} [get_ports RXFB_MCLK_IN ]
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets u_mclk_delay/MCLK1]
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets u_mclk_delay/MCLK2]
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets u_mclk_delay/MCLK3]
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set_property LOC IDELAYCTRL_X0Y2 [get_cells u_mclk_delay/IDELAYCTRL_RX12]
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set_property LOC IDELAYCTRL_X0Y4 [get_cells u_mclk_delay/IDELAYCTRL_RX3]
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################################################################################################
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##################################### 1 #set false path########################################
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set_false_path -from [get_pins {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[7].ram.r/SAFETY_CKT_GEN.RSTB_SHFT_REG_reg[3]_srl3/CLK}] -to [get_pins {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[7].ram.r/SAFETY_CKT_GEN.RSTB_SHFT_REG_reg[4]/D}]
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set_false_path -from [get_pins {system_top_i/fifo_generator_0/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/SAFETY_CKT_GEN.RSTA_SHFT_REG_reg[3]_srl3/CLK}] -to [get_pins {system_top_i/fifo_generator_0/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/SAFETY_CKT_GEN.RSTA_SHFT_REG_reg[4]/D}]
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set_false_path -from [get_clocks RX1_MCLK_IN_N] -to [get_clocks -of_objects [get_pins system_top_i/mig_7series_0/u_system_top_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKFBOUT]]
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set_false_path -from [get_clocks RX2_MCLK_IN_P] -to [get_clocks -of_objects [get_pins system_top_i/mig_7series_0/u_system_top_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKFBOUT]]
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set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks RX2_MCLK_IN_P]
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################################################################################################
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#################################### 2 #CX9261A data ila########################################
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create_debug_core u_ila_0 ila
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set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
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set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0]
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set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0]
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set_property C_DATA_DEPTH 16384 [get_debug_cores u_ila_0]
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set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0]
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set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
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set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
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set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
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set_property port_width 1 [get_debug_ports u_ila_0/clk]
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connect_debug_port u_ila_0/clk [get_nets [list system_top_i/processing_system7_0/inst/FCLK_CLK0]]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
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set_property port_width 24 [get_debug_ports u_ila_0/probe0]
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connect_debug_port u_ila_0/probe0 [get_nets [list {hop_intr/r_hop_cnt[0]} {hop_intr/r_hop_cnt[1]} {hop_intr/r_hop_cnt[2]} {hop_intr/r_hop_cnt[3]} {hop_intr/r_hop_cnt[4]} {hop_intr/r_hop_cnt[5]} {hop_intr/r_hop_cnt[6]} {hop_intr/r_hop_cnt[7]} {hop_intr/r_hop_cnt[8]} {hop_intr/r_hop_cnt[9]} {hop_intr/r_hop_cnt[10]} {hop_intr/r_hop_cnt[11]} {hop_intr/r_hop_cnt[12]} {hop_intr/r_hop_cnt[13]} {hop_intr/r_hop_cnt[14]} {hop_intr/r_hop_cnt[15]} {hop_intr/r_hop_cnt[16]} {hop_intr/r_hop_cnt[17]} {hop_intr/r_hop_cnt[18]} {hop_intr/r_hop_cnt[19]} {hop_intr/r_hop_cnt[20]} {hop_intr/r_hop_cnt[21]} {hop_intr/r_hop_cnt[22]} {hop_intr/r_hop_cnt[23]}]]
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create_debug_port u_ila_0 probe
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
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set_property port_width 1 [get_debug_ports u_ila_0/probe1]
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connect_debug_port u_ila_0/probe1 [get_nets [list hop_intr/hop_flag]]
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create_debug_port u_ila_0 probe
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
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set_property port_width 1 [get_debug_ports u_ila_0/probe2]
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connect_debug_port u_ila_0/probe2 [get_nets [list hop_intr/r_SPI_0_0_ss_o]]
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create_debug_port u_ila_0 probe
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
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set_property port_width 1 [get_debug_ports u_ila_0/probe3]
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connect_debug_port u_ila_0/probe3 [get_nets [list hop_intr/spi_pose_flag]]
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create_debug_port u_ila_0 probe
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
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set_property port_width 1 [get_debug_ports u_ila_0/probe4]
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connect_debug_port u_ila_0/probe4 [get_nets [list hop_intr/r_hop_cnt_flag]]
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create_debug_port u_ila_0 probe
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
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set_property port_width 1 [get_debug_ports u_ila_0/probe5]
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connect_debug_port u_ila_0/probe5 [get_nets [list hop_intr/hop_neg_flag]]
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create_debug_port u_ila_0 probe
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
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set_property port_width 1 [get_debug_ports u_ila_0/probe6]
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connect_debug_port u_ila_0/probe6 [get_nets [list hop_intr/hop_signal]]
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create_debug_core u_ila_1 ila
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set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_1]
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set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_1]
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set_property C_ADV_TRIGGER true [get_debug_cores u_ila_1]
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set_property C_DATA_DEPTH 16384 [get_debug_cores u_ila_1]
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set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_1]
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set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_1]
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set_property C_TRIGIN_EN false [get_debug_cores u_ila_1]
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set_property C_TRIGOUT_EN false [get_debug_cores u_ila_1]
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set_property port_width 1 [get_debug_ports u_ila_1/clk]
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connect_debug_port u_ila_1/clk [get_nets [list cx9261a_if_cmos/u_cx9261a_if_cmos_port/mclk_g1]]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe0]
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set_property port_width 16 [get_debug_ports u_ila_1/probe0]
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connect_debug_port u_ila_1/probe0 [get_nets [list {rx1_i_data[0]} {rx1_i_data[1]} {rx1_i_data[2]} {rx1_i_data[3]} {rx1_i_data[4]} {rx1_i_data[5]} {rx1_i_data[6]} {rx1_i_data[7]} {rx1_i_data[8]} {rx1_i_data[9]} {rx1_i_data[10]} {rx1_i_data[11]} {rx1_i_data[12]} {rx1_i_data[13]} {rx1_i_data[14]} {rx1_i_data[15]}]]
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create_debug_port u_ila_1 probe
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe1]
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set_property port_width 16 [get_debug_ports u_ila_1/probe1]
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connect_debug_port u_ila_1/probe1 [get_nets [list {rx2_q_data[0]} {rx2_q_data[1]} {rx2_q_data[2]} {rx2_q_data[3]} {rx2_q_data[4]} {rx2_q_data[5]} {rx2_q_data[6]} {rx2_q_data[7]} {rx2_q_data[8]} {rx2_q_data[9]} {rx2_q_data[10]} {rx2_q_data[11]} {rx2_q_data[12]} {rx2_q_data[13]} {rx2_q_data[14]} {rx2_q_data[15]}]]
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create_debug_port u_ila_1 probe
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe2]
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set_property port_width 16 [get_debug_ports u_ila_1/probe2]
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connect_debug_port u_ila_1/probe2 [get_nets [list {tx1_i_data[0]} {tx1_i_data[1]} {tx1_i_data[2]} {tx1_i_data[3]} {tx1_i_data[4]} {tx1_i_data[5]} {tx1_i_data[6]} {tx1_i_data[7]} {tx1_i_data[8]} {tx1_i_data[9]} {tx1_i_data[10]} {tx1_i_data[11]} {tx1_i_data[12]} {tx1_i_data[13]} {tx1_i_data[14]} {tx1_i_data[15]}]]
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create_debug_port u_ila_1 probe
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe3]
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set_property port_width 16 [get_debug_ports u_ila_1/probe3]
|
||||
connect_debug_port u_ila_1/probe3 [get_nets [list {tx2_q_data[0]} {tx2_q_data[1]} {tx2_q_data[2]} {tx2_q_data[3]} {tx2_q_data[4]} {tx2_q_data[5]} {tx2_q_data[6]} {tx2_q_data[7]} {tx2_q_data[8]} {tx2_q_data[9]} {tx2_q_data[10]} {tx2_q_data[11]} {tx2_q_data[12]} {tx2_q_data[13]} {tx2_q_data[14]} {tx2_q_data[15]}]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe4]
|
||||
set_property port_width 16 [get_debug_ports u_ila_1/probe4]
|
||||
connect_debug_port u_ila_1/probe4 [get_nets [list {rx2_i_data[0]} {rx2_i_data[1]} {rx2_i_data[2]} {rx2_i_data[3]} {rx2_i_data[4]} {rx2_i_data[5]} {rx2_i_data[6]} {rx2_i_data[7]} {rx2_i_data[8]} {rx2_i_data[9]} {rx2_i_data[10]} {rx2_i_data[11]} {rx2_i_data[12]} {rx2_i_data[13]} {rx2_i_data[14]} {rx2_i_data[15]}]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe5]
|
||||
set_property port_width 16 [get_debug_ports u_ila_1/probe5]
|
||||
connect_debug_port u_ila_1/probe5 [get_nets [list {rx1_q_data[0]} {rx1_q_data[1]} {rx1_q_data[2]} {rx1_q_data[3]} {rx1_q_data[4]} {rx1_q_data[5]} {rx1_q_data[6]} {rx1_q_data[7]} {rx1_q_data[8]} {rx1_q_data[9]} {rx1_q_data[10]} {rx1_q_data[11]} {rx1_q_data[12]} {rx1_q_data[13]} {rx1_q_data[14]} {rx1_q_data[15]}]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe6]
|
||||
set_property port_width 16 [get_debug_ports u_ila_1/probe6]
|
||||
connect_debug_port u_ila_1/probe6 [get_nets [list {rx3_q_data[0]} {rx3_q_data[1]} {rx3_q_data[2]} {rx3_q_data[3]} {rx3_q_data[4]} {rx3_q_data[5]} {rx3_q_data[6]} {rx3_q_data[7]} {rx3_q_data[8]} {rx3_q_data[9]} {rx3_q_data[10]} {rx3_q_data[11]} {rx3_q_data[12]} {rx3_q_data[13]} {rx3_q_data[14]} {rx3_q_data[15]}]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe7]
|
||||
set_property port_width 16 [get_debug_ports u_ila_1/probe7]
|
||||
connect_debug_port u_ila_1/probe7 [get_nets [list {rx3_i_data[0]} {rx3_i_data[1]} {rx3_i_data[2]} {rx3_i_data[3]} {rx3_i_data[4]} {rx3_i_data[5]} {rx3_i_data[6]} {rx3_i_data[7]} {rx3_i_data[8]} {rx3_i_data[9]} {rx3_i_data[10]} {rx3_i_data[11]} {rx3_i_data[12]} {rx3_i_data[13]} {rx3_i_data[14]} {rx3_i_data[15]}]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe8]
|
||||
set_property port_width 16 [get_debug_ports u_ila_1/probe8]
|
||||
connect_debug_port u_ila_1/probe8 [get_nets [list {tx2_i_data[0]} {tx2_i_data[1]} {tx2_i_data[2]} {tx2_i_data[3]} {tx2_i_data[4]} {tx2_i_data[5]} {tx2_i_data[6]} {tx2_i_data[7]} {tx2_i_data[8]} {tx2_i_data[9]} {tx2_i_data[10]} {tx2_i_data[11]} {tx2_i_data[12]} {tx2_i_data[13]} {tx2_i_data[14]} {tx2_i_data[15]}]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe9]
|
||||
set_property port_width 16 [get_debug_ports u_ila_1/probe9]
|
||||
connect_debug_port u_ila_1/probe9 [get_nets [list {tx1_q_data[0]} {tx1_q_data[1]} {tx1_q_data[2]} {tx1_q_data[3]} {tx1_q_data[4]} {tx1_q_data[5]} {tx1_q_data[6]} {tx1_q_data[7]} {tx1_q_data[8]} {tx1_q_data[9]} {tx1_q_data[10]} {tx1_q_data[11]} {tx1_q_data[12]} {tx1_q_data[13]} {tx1_q_data[14]} {tx1_q_data[15]}]]
|
||||
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
|
||||
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
|
||||
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
|
||||
connect_debug_port dbg_hub/clk [get_nets MCLK2]
|
||||
################################################################################################
|
||||
@@ -0,0 +1,163 @@
|
||||
set_false_path -from [get_pins {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[7].ram.r/SAFETY_CKT_GEN.RSTB_SHFT_REG_reg[3]_srl3/CLK}] -to [get_pins {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[7].ram.r/SAFETY_CKT_GEN.RSTB_SHFT_REG_reg[4]/D}]
|
||||
set_false_path -from [get_pins {system_top_i/fifo_generator_0/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/SAFETY_CKT_GEN.RSTA_SHFT_REG_reg[3]_srl3/CLK}] -to [get_pins {system_top_i/fifo_generator_0/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/SAFETY_CKT_GEN.RSTA_SHFT_REG_reg[4]/D}]
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
create_debug_core u_ila_0 ila
|
||||
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
|
||||
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
|
||||
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
|
||||
set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
|
||||
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
|
||||
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
|
||||
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
|
||||
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/clk]
|
||||
connect_debug_port u_ila_0/clk [get_nets [list cx9261a_if_cmos/u_cx9261a_if_cmos_port/mclk_g1]]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
|
||||
set_property port_width 8 [get_debug_ports u_ila_0/probe0]
|
||||
connect_debug_port u_ila_0/probe0 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA[7]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
|
||||
set_property port_width 8 [get_debug_ports u_ila_0/probe1]
|
||||
connect_debug_port u_ila_0/probe1 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA[7]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
|
||||
set_property port_width 8 [get_debug_ports u_ila_0/probe2]
|
||||
connect_debug_port u_ila_0/probe2 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA_pos_o[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA_pos_o[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA_pos_o[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA_pos_o[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA_pos_o[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA_pos_o[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA_pos_o[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA_pos_o[7]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
|
||||
set_property port_width 8 [get_debug_ports u_ila_0/probe3]
|
||||
connect_debug_port u_ila_0/probe3 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA_neg_o[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA_neg_o[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA_neg_o[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA_neg_o[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA_neg_o[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA_neg_o[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA_neg_o[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA_neg_o[7]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
|
||||
set_property port_width 8 [get_debug_ports u_ila_0/probe4]
|
||||
connect_debug_port u_ila_0/probe4 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA_pos_o[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA_pos_o[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA_pos_o[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA_pos_o[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA_pos_o[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA_pos_o[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA_pos_o[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA_pos_o[7]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
|
||||
set_property port_width 8 [get_debug_ports u_ila_0/probe5]
|
||||
connect_debug_port u_ila_0/probe5 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA_neg_o[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA_neg_o[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA_neg_o[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA_neg_o[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA_neg_o[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA_neg_o[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA_neg_o[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA_neg_o[7]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
|
||||
set_property port_width 16 [get_debug_ports u_ila_0/probe6]
|
||||
connect_debug_port u_ila_0/probe6 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_i_data[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_i_data[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_i_data[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_i_data[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_i_data[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_i_data[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_i_data[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_i_data[7]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_i_data[8]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_i_data[9]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_i_data[10]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_i_data[11]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_i_data[12]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_i_data[13]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_i_data[14]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_i_data[15]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
|
||||
set_property port_width 16 [get_debug_ports u_ila_0/probe7]
|
||||
connect_debug_port u_ila_0/probe7 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_q_data[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_q_data[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_q_data[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_q_data[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_q_data[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_q_data[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_q_data[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_q_data[7]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_q_data[8]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_q_data[9]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_q_data[10]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_q_data[11]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_q_data[12]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_q_data[13]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_q_data[14]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_q_data[15]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
|
||||
set_property port_width 16 [get_debug_ports u_ila_0/probe8]
|
||||
connect_debug_port u_ila_0/probe8 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_i_data[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_i_data[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_i_data[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_i_data[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_i_data[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_i_data[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_i_data[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_i_data[7]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_i_data[8]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_i_data[9]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_i_data[10]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_i_data[11]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_i_data[12]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_i_data[13]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_i_data[14]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_i_data[15]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
|
||||
set_property port_width 16 [get_debug_ports u_ila_0/probe9]
|
||||
connect_debug_port u_ila_0/probe9 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_q_data[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_q_data[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_q_data[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_q_data[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_q_data[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_q_data[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_q_data[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_q_data[7]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_q_data[8]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_q_data[9]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_q_data[10]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_q_data[11]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_q_data[12]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_q_data[13]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_q_data[14]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_q_data[15]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe10]
|
||||
connect_debug_port u_ila_0/probe10 [get_nets [list cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_data_valid]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe11]
|
||||
connect_debug_port u_ila_0/probe11 [get_nets [list cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_data_ready]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe12]
|
||||
connect_debug_port u_ila_0/probe12 [get_nets [list cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_frame_neg]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe13]
|
||||
connect_debug_port u_ila_0/probe13 [get_nets [list cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_frame_pos]]
|
||||
create_debug_core u_ila_1 ila
|
||||
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_1]
|
||||
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_1]
|
||||
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_1]
|
||||
set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_1]
|
||||
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_1]
|
||||
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_1]
|
||||
set_property C_TRIGIN_EN false [get_debug_cores u_ila_1]
|
||||
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_1]
|
||||
set_property port_width 1 [get_debug_ports u_ila_1/clk]
|
||||
connect_debug_port u_ila_1/clk [get_nets [list cx9261a_if_cmos/u_cx9261a_if_cmos_port/data_clk2]]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe0]
|
||||
set_property port_width 2 [get_debug_ports u_ila_1/probe0]
|
||||
connect_debug_port u_ila_1/probe0 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX_FRAME_N[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX_FRAME_N[1]}]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe1]
|
||||
set_property port_width 8 [get_debug_ports u_ila_1/probe1]
|
||||
connect_debug_port u_ila_1/probe1 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA_neg_o[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA_neg_o[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA_neg_o[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA_neg_o[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA_neg_o[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA_neg_o[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA_neg_o[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA_neg_o[7]}]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe2]
|
||||
set_property port_width 8 [get_debug_ports u_ila_1/probe2]
|
||||
connect_debug_port u_ila_1/probe2 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA[7]}]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe3]
|
||||
set_property port_width 8 [get_debug_ports u_ila_1/probe3]
|
||||
connect_debug_port u_ila_1/probe3 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA_neg_o[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA_neg_o[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA_neg_o[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA_neg_o[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA_neg_o[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA_neg_o[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA_neg_o[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA_neg_o[7]}]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe4]
|
||||
set_property port_width 8 [get_debug_ports u_ila_1/probe4]
|
||||
connect_debug_port u_ila_1/probe4 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA_pos_o[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA_pos_o[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA_pos_o[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA_pos_o[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA_pos_o[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA_pos_o[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA_pos_o[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA_pos_o[7]}]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe5]
|
||||
set_property port_width 8 [get_debug_ports u_ila_1/probe5]
|
||||
connect_debug_port u_ila_1/probe5 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA_pos_o[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA_pos_o[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA_pos_o[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA_pos_o[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA_pos_o[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA_pos_o[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA_pos_o[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA_pos_o[7]}]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe6]
|
||||
set_property port_width 8 [get_debug_ports u_ila_1/probe6]
|
||||
connect_debug_port u_ila_1/probe6 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA[7]}]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe7]
|
||||
set_property port_width 16 [get_debug_ports u_ila_1/probe7]
|
||||
connect_debug_port u_ila_1/probe7 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_q_data[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_q_data[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_q_data[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_q_data[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_q_data[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_q_data[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_q_data[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_q_data[7]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_q_data[8]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_q_data[9]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_q_data[10]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_q_data[11]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_q_data[12]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_q_data[13]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_q_data[14]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_q_data[15]}]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe8]
|
||||
set_property port_width 16 [get_debug_ports u_ila_1/probe8]
|
||||
connect_debug_port u_ila_1/probe8 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_i_data[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_i_data[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_i_data[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_i_data[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_i_data[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_i_data[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_i_data[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_i_data[7]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_i_data[8]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_i_data[9]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_i_data[10]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_i_data[11]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_i_data[12]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_i_data[13]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_i_data[14]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_i_data[15]}]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe9]
|
||||
set_property port_width 16 [get_debug_ports u_ila_1/probe9]
|
||||
connect_debug_port u_ila_1/probe9 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_i_data[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_i_data[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_i_data[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_i_data[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_i_data[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_i_data[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_i_data[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_i_data[7]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_i_data[8]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_i_data[9]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_i_data[10]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_i_data[11]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_i_data[12]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_i_data[13]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_i_data[14]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_i_data[15]}]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe10]
|
||||
set_property port_width 16 [get_debug_ports u_ila_1/probe10]
|
||||
connect_debug_port u_ila_1/probe10 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_q_data[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_q_data[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_q_data[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_q_data[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_q_data[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_q_data[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_q_data[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_q_data[7]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_q_data[8]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_q_data[9]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_q_data[10]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_q_data[11]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_q_data[12]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_q_data[13]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_q_data[14]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_q_data[15]}]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe11]
|
||||
set_property port_width 1 [get_debug_ports u_ila_1/probe11]
|
||||
connect_debug_port u_ila_1/probe11 [get_nets [list cx9261a_if_cmos/u_cx9261a_if_cmos_port/r1t1_r2t2_sel]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe12]
|
||||
set_property port_width 1 [get_debug_ports u_ila_1/probe12]
|
||||
connect_debug_port u_ila_1/probe12 [get_nets [list cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_data_valid]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe13]
|
||||
set_property port_width 1 [get_debug_ports u_ila_1/probe13]
|
||||
connect_debug_port u_ila_1/probe13 [get_nets [list cx9261a_if_cmos/u_cx9261a_if_cmos_port/sp_dp_sel]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe14]
|
||||
set_property port_width 1 [get_debug_ports u_ila_1/probe14]
|
||||
connect_debug_port u_ila_1/probe14 [get_nets [list cx9261a_if_cmos/u_cx9261a_if_cmos_port/tdd_fdd_sel]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe15]
|
||||
set_property port_width 1 [get_debug_ports u_ila_1/probe15]
|
||||
connect_debug_port u_ila_1/probe15 [get_nets [list cx9261a_if_cmos/u_cx9261a_if_cmos_port/tr_sel]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe16]
|
||||
set_property port_width 1 [get_debug_ports u_ila_1/probe16]
|
||||
connect_debug_port u_ila_1/probe16 [get_nets [list cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_data_ready]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe17]
|
||||
set_property port_width 1 [get_debug_ports u_ila_1/probe17]
|
||||
connect_debug_port u_ila_1/probe17 [get_nets [list cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_frame_neg]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe18]
|
||||
set_property port_width 1 [get_debug_ports u_ila_1/probe18]
|
||||
connect_debug_port u_ila_1/probe18 [get_nets [list cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_frame_pos]]
|
||||
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
|
||||
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
|
||||
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
|
||||
connect_debug_port dbg_hub/clk [get_nets data_clk2]
|
||||
@@ -0,0 +1,763 @@
|
||||
set_property MARK_DEBUG true [get_nets {data_i[10]}]
|
||||
set_property MARK_DEBUG true [get_nets {data_i[1]}]
|
||||
set_property MARK_DEBUG true [get_nets {data_i[4]}]
|
||||
set_property MARK_DEBUG true [get_nets {data_i[6]}]
|
||||
set_property MARK_DEBUG true [get_nets {data_i[13]}]
|
||||
set_property MARK_DEBUG true [get_nets {data_q[2]}]
|
||||
set_property MARK_DEBUG true [get_nets {data_q[6]}]
|
||||
set_property MARK_DEBUG true [get_nets {data_q[10]}]
|
||||
set_property MARK_DEBUG true [get_nets {data_q[15]}]
|
||||
set_property MARK_DEBUG true [get_nets {data_i[0]}]
|
||||
set_property MARK_DEBUG true [get_nets {data_i[5]}]
|
||||
set_property MARK_DEBUG true [get_nets {data_i[8]}]
|
||||
set_property MARK_DEBUG true [get_nets {data_i[15]}]
|
||||
set_property MARK_DEBUG true [get_nets {data_q[1]}]
|
||||
set_property MARK_DEBUG true [get_nets {data_q[5]}]
|
||||
set_property MARK_DEBUG true [get_nets {data_q[8]}]
|
||||
set_property MARK_DEBUG true [get_nets {data_q[12]}]
|
||||
set_property MARK_DEBUG true [get_nets {data_i[3]}]
|
||||
set_property MARK_DEBUG true [get_nets {data_i[7]}]
|
||||
set_property MARK_DEBUG true [get_nets {data_i[12]}]
|
||||
set_property MARK_DEBUG true [get_nets {data_q[0]}]
|
||||
set_property MARK_DEBUG true [get_nets {data_q[4]}]
|
||||
set_property MARK_DEBUG true [get_nets {data_q[7]}]
|
||||
set_property MARK_DEBUG true [get_nets {data_q[13]}]
|
||||
set_property MARK_DEBUG true [get_nets {data_i[2]}]
|
||||
set_property MARK_DEBUG true [get_nets {data_i[9]}]
|
||||
set_property MARK_DEBUG true [get_nets {data_i[11]}]
|
||||
set_property MARK_DEBUG true [get_nets {data_i[14]}]
|
||||
set_property MARK_DEBUG true [get_nets {data_q[3]}]
|
||||
set_property MARK_DEBUG true [get_nets {data_q[9]}]
|
||||
set_property MARK_DEBUG true [get_nets {data_q[11]}]
|
||||
set_property MARK_DEBUG true [get_nets {data_q[14]}]
|
||||
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_1_Q[0]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_1_Q[2]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_1_Q[4]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_1_Q[6]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_1_Q[7]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_1_Q[10]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_1_Q[12]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_1_Q[14]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_1_Q[1]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_1_Q[3]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_1_Q[5]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_1_Q[8]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_1_Q[9]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_1_Q[11]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_1_Q[13]}]
|
||||
|
||||
set_property MARK_DEBUG true [get_nets system_top_i/CE]
|
||||
set_property MARK_DEBUG true [get_nets NRST_OBUF]
|
||||
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[13]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[29]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[54]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[12]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[42]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[17]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[34]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[37]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[35]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[41]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[61]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[24]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[39]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[45]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[23]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[56]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[21]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[35]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[54]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[56]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[42]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[10]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[53]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[63]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[1]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[6]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[58]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[9]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[21]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[23]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[38]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[14]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[12]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[50]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[55]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[57]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[61]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[5]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[50]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[31]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[43]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[55]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[10]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[12]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[39]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[32]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[16]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[63]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[49]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[40]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[58]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[4]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[27]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[13]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[22]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[44]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[15]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[58]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[4]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[7]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[49]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[5]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[59]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[19]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[28]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[3]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[27]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[30]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[9]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[26]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[1]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[6]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[27]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[46]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[3]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[53]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[56]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[8]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[25]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[26]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[47]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[59]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[11]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[29]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[52]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[18]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[24]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[7]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[50]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[33]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[41]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[61]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[1]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[15]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[18]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[0]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[16]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[19]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[51]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[55]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[2]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[20]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[31]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[13]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[49]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[3]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[51]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[7]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[14]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[15]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[32]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[53]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[17]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[23]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[4]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[14]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[45]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[24]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[22]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[59]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[62]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[11]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[22]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[37]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[45]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[60]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[18]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[28]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[0]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[17]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[36]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[39]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[43]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[63]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[2]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[30]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[42]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[60]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[52]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[54]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[26]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[9]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[20]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[33]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[44]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[48]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[60]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[21]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[41]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[48]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[38]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[47]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[29]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[36]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[38]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[44]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[51]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[43]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[48]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[11]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[16]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[35]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[10]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[34]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[40]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[46]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[62]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[0]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[25]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[32]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[8]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[19]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[37]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[57]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[62]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[6]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[52]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[8]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[31]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[20]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[25]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[34]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[40]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[46]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[2]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[57]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[5]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[28]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[47]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[33]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[36]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[30]}]
|
||||
set_property MARK_DEBUG true [get_nets system_top_i/SPI_0_0_io0_t]
|
||||
set_property MARK_DEBUG true [get_nets system_top_i/SPI_0_0_io1_t]
|
||||
set_property MARK_DEBUG true [get_nets system_top_i/SPI_0_0_sck_o]
|
||||
set_property MARK_DEBUG true [get_nets system_top_i/SPI_0_0_ss_i]
|
||||
set_property MARK_DEBUG true [get_nets system_top_i/SPI_0_0_io0_i]
|
||||
set_property MARK_DEBUG true [get_nets system_top_i/SPI_0_0_sck_i]
|
||||
set_property MARK_DEBUG true [get_nets system_top_i/SPI_0_0_sck_t]
|
||||
set_property MARK_DEBUG true [get_nets system_top_i/SPI_0_0_ss1_o]
|
||||
set_property MARK_DEBUG true [get_nets system_top_i/SPI_0_0_ss2_o]
|
||||
set_property MARK_DEBUG true [get_nets system_top_i/SPI_0_0_io0_o]
|
||||
set_property MARK_DEBUG true [get_nets system_top_i/SPI_0_0_io1_i]
|
||||
set_property MARK_DEBUG true [get_nets system_top_i/SPI_0_0_io1_o]
|
||||
set_property MARK_DEBUG true [get_nets system_top_i/SPI_0_0_ss_o]
|
||||
set_property MARK_DEBUG true [get_nets system_top_i/SPI_0_0_ss_t]
|
||||
|
||||
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/addrb[3]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/addrb[5]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/addrb[7]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/addrb[10]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/addrb[11]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/addrb[12]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/addrb[14]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/addrb[2]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/addrb[4]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/addrb[6]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/addrb[8]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/addrb[9]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/addrb[13]}]
|
||||
set_property MARK_DEBUG true [get_nets system_top_i/blk_mem_gen_0/U0/rstb_busy]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[1]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[3]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[6]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[10]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[4]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[0]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[2]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[5]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[8]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[12]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[9]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[11]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[7]}]
|
||||
|
||||
set_property MARK_DEBUG true [get_nets system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/capture_cdc]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[3]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[8]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[24]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[25]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[9]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[0]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[2]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[5]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[18]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[19]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[20]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[21]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[6]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[10]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[17]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[22]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[23]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[12]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[16]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[1]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[4]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[7]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[11]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[13]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[14]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[15]}]
|
||||
#connect_debug_port dbg_hub/clk [get_nets data_clk]
|
||||
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_neg[3]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_neg[0]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_neg[1]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_neg[2]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_neg[4]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_neg[5]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_neg[6]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_neg[7]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_pos[0]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_pos[1]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_pos[2]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_pos[3]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_pos[4]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_pos[5]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_pos[6]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_pos[7]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_neg[4]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_neg[5]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_neg[7]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_neg[2]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_neg[3]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_neg[6]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_neg[0]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_neg[1]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_pos[0]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_pos[1]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_pos[2]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_pos[3]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_pos[4]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_pos[5]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_pos[6]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_pos[7]}]
|
||||
set_property MARK_DEBUG true [get_nets cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FRAME_neg]
|
||||
set_property MARK_DEBUG true [get_nets cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FRAME_pos]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_neg[2]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_pos[0]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_pos[6]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_neg[1]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_neg[5]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_pos[0]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_pos[4]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_pos[2]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_neg[3]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_neg[7]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_pos[1]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_neg[2]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_neg[6]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_pos[1]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_pos[7]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_pos[3]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_neg[0]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_neg[4]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_pos[4]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_pos[7]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_neg[3]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_pos[2]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_pos[5]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_neg[6]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_neg[1]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_neg[5]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_pos[5]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_neg[0]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_neg[4]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_neg[7]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_pos[3]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_pos[6]}]
|
||||
set_property MARK_DEBUG true [get_nets cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FRAME_neg]
|
||||
set_property MARK_DEBUG true [get_nets cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FRAME_pos]
|
||||
|
||||
set_property MARK_DEBUG true [get_nets {rx1_q_data[1]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx1_i_data[1]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx1_i_data[8]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx1_q_data[8]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx2_i_data[8]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx2_i_data[1]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx2_q_data[1]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx2_q_data[8]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx1_i_data[4]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx1_i_data[12]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx1_q_data[4]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx2_i_data[12]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx1_q_data[12]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx2_i_data[4]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx2_q_data[4]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx2_q_data[12]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx1_q_data[11]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx1_i_data[3]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx1_i_data[11]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx1_q_data[3]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx2_i_data[3]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx2_i_data[11]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx2_q_data[3]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx2_q_data[11]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx1_i_data[9]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx1_i_data[14]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx1_q_data[6]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx1_q_data[14]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx2_i_data[6]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx2_i_data[14]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx2_q_data[6]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx2_q_data[14]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx1_i_data[5]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx1_i_data[13]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx1_q_data[5]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx1_q_data[13]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx2_i_data[5]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx2_i_data[13]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx2_q_data[5]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx2_q_data[13]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx1_q_data[7]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx1_q_data[0]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx1_i_data[6]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx1_i_data[0]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx2_i_data[7]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx2_i_data[0]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx2_q_data[0]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx2_q_data[7]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx1_i_data[7]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx1_i_data[15]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx1_q_data[9]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx1_q_data[15]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx2_i_data[15]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx2_i_data[9]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx2_q_data[9]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx2_q_data[15]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx1_q_data[2]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx1_i_data[2]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx1_i_data[10]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx1_q_data[10]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx2_i_data[2]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx2_i_data[10]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx2_q_data[2]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx2_q_data[10]}]
|
||||
|
||||
set_property MARK_DEBUG true [get_nets {tx1_i_data[4]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx1_i_data[12]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx1_q_data[4]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx1_q_data[12]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx2_i_data[12]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx2_i_data[4]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx2_q_data[4]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx2_q_data[12]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx1_q_data[1]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx1_i_data[1]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx1_i_data[8]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx1_q_data[8]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx2_i_data[1]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx2_i_data[8]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx2_q_data[1]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx2_q_data[8]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx1_i_data[2]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx1_i_data[10]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx1_q_data[2]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx1_q_data[10]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx2_i_data[2]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx2_i_data[10]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx2_q_data[2]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx2_q_data[10]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx1_i_data[15]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx1_i_data[9]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx1_q_data[9]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx1_q_data[15]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx2_i_data[9]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx2_i_data[15]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx2_q_data[9]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx2_q_data[15]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx1_q_data[7]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx1_i_data[7]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx1_q_data[0]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx1_i_data[0]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx2_i_data[0]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx2_i_data[7]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx2_q_data[0]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx2_q_data[7]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx1_i_data[5]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx1_i_data[13]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx1_q_data[5]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx1_q_data[13]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx2_i_data[13]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx2_i_data[5]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx2_q_data[5]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx2_q_data[13]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx1_i_data[14]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx1_i_data[6]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx1_q_data[6]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx1_q_data[14]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx2_i_data[6]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx2_i_data[14]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx2_q_data[6]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx2_q_data[14]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx1_i_data[3]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx1_i_data[11]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx1_q_data[3]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx1_q_data[11]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx2_i_data[11]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx2_i_data[3]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx2_q_data[3]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx2_q_data[11]}]
|
||||
|
||||
set_property MARK_DEBUG true [get_nets system_top_i/CE_1]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[1]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[4]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[15]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[16]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[17]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[19]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[24]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[31]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[3]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[5]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[6]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[7]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[10]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[18]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[22]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[2]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[0]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[8]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[29]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[9]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[12]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[30]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[13]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[20]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[21]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[27]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[11]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[14]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[23]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[25]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[26]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[28]}]
|
||||
create_debug_core u_ila_0 ila
|
||||
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
|
||||
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
|
||||
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
|
||||
set_property C_DATA_DEPTH 8192 [get_debug_cores u_ila_0]
|
||||
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
|
||||
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
|
||||
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
|
||||
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/clk]
|
||||
connect_debug_port u_ila_0/clk [get_nets [list system_top_i/mig_7series_0/u_system_top_mig_7series_0_0_mig/u_ddr3_infrastructure/CLK]]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
|
||||
set_property port_width 26 [get_debug_ports u_ila_0/probe0]
|
||||
connect_debug_port u_ila_0/probe0 [get_nets [list {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[0]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[1]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[2]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[3]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[4]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[5]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[6]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[7]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[8]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[9]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[10]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[11]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[12]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[13]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[14]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[15]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[16]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[17]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[18]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[19]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[20]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[21]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[22]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[23]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[24]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[25]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
|
||||
set_property port_width 64 [get_debug_ports u_ila_0/probe1]
|
||||
connect_debug_port u_ila_0/probe1 [get_nets [list {system_top_i/GPIO_0_0_tri_o[0]} {system_top_i/GPIO_0_0_tri_o[1]} {system_top_i/GPIO_0_0_tri_o[2]} {system_top_i/GPIO_0_0_tri_o[3]} {system_top_i/GPIO_0_0_tri_o[4]} {system_top_i/GPIO_0_0_tri_o[5]} {system_top_i/GPIO_0_0_tri_o[6]} {system_top_i/GPIO_0_0_tri_o[7]} {system_top_i/GPIO_0_0_tri_o[8]} {system_top_i/GPIO_0_0_tri_o[9]} {system_top_i/GPIO_0_0_tri_o[10]} {system_top_i/GPIO_0_0_tri_o[11]} {system_top_i/GPIO_0_0_tri_o[12]} {system_top_i/GPIO_0_0_tri_o[13]} {system_top_i/GPIO_0_0_tri_o[14]} {system_top_i/GPIO_0_0_tri_o[15]} {system_top_i/GPIO_0_0_tri_o[16]} {system_top_i/GPIO_0_0_tri_o[17]} {system_top_i/GPIO_0_0_tri_o[18]} {system_top_i/GPIO_0_0_tri_o[19]} {system_top_i/GPIO_0_0_tri_o[20]} {system_top_i/GPIO_0_0_tri_o[21]} {system_top_i/GPIO_0_0_tri_o[22]} {system_top_i/GPIO_0_0_tri_o[23]} {system_top_i/GPIO_0_0_tri_o[24]} {system_top_i/GPIO_0_0_tri_o[25]} {system_top_i/GPIO_0_0_tri_o[26]} {system_top_i/GPIO_0_0_tri_o[27]} {system_top_i/GPIO_0_0_tri_o[28]} {system_top_i/GPIO_0_0_tri_o[29]} {system_top_i/GPIO_0_0_tri_o[30]} {system_top_i/GPIO_0_0_tri_o[31]} {system_top_i/GPIO_0_0_tri_o[32]} {system_top_i/GPIO_0_0_tri_o[33]} {system_top_i/GPIO_0_0_tri_o[34]} {system_top_i/GPIO_0_0_tri_o[35]} {system_top_i/GPIO_0_0_tri_o[36]} {system_top_i/GPIO_0_0_tri_o[37]} {system_top_i/GPIO_0_0_tri_o[38]} {system_top_i/GPIO_0_0_tri_o[39]} {system_top_i/GPIO_0_0_tri_o[40]} {system_top_i/GPIO_0_0_tri_o[41]} {system_top_i/GPIO_0_0_tri_o[42]} {system_top_i/GPIO_0_0_tri_o[43]} {system_top_i/GPIO_0_0_tri_o[44]} {system_top_i/GPIO_0_0_tri_o[45]} {system_top_i/GPIO_0_0_tri_o[46]} {system_top_i/GPIO_0_0_tri_o[47]} {system_top_i/GPIO_0_0_tri_o[48]} {system_top_i/GPIO_0_0_tri_o[49]} {system_top_i/GPIO_0_0_tri_o[50]} {system_top_i/GPIO_0_0_tri_o[51]} {system_top_i/GPIO_0_0_tri_o[52]} {system_top_i/GPIO_0_0_tri_o[53]} {system_top_i/GPIO_0_0_tri_o[54]} {system_top_i/GPIO_0_0_tri_o[55]} {system_top_i/GPIO_0_0_tri_o[56]} {system_top_i/GPIO_0_0_tri_o[57]} {system_top_i/GPIO_0_0_tri_o[58]} {system_top_i/GPIO_0_0_tri_o[59]} {system_top_i/GPIO_0_0_tri_o[60]} {system_top_i/GPIO_0_0_tri_o[61]} {system_top_i/GPIO_0_0_tri_o[62]} {system_top_i/GPIO_0_0_tri_o[63]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
|
||||
set_property port_width 64 [get_debug_ports u_ila_0/probe2]
|
||||
connect_debug_port u_ila_0/probe2 [get_nets [list {system_top_i/GPIO_0_0_tri_t[0]} {system_top_i/GPIO_0_0_tri_t[1]} {system_top_i/GPIO_0_0_tri_t[2]} {system_top_i/GPIO_0_0_tri_t[3]} {system_top_i/GPIO_0_0_tri_t[4]} {system_top_i/GPIO_0_0_tri_t[5]} {system_top_i/GPIO_0_0_tri_t[6]} {system_top_i/GPIO_0_0_tri_t[7]} {system_top_i/GPIO_0_0_tri_t[8]} {system_top_i/GPIO_0_0_tri_t[9]} {system_top_i/GPIO_0_0_tri_t[10]} {system_top_i/GPIO_0_0_tri_t[11]} {system_top_i/GPIO_0_0_tri_t[12]} {system_top_i/GPIO_0_0_tri_t[13]} {system_top_i/GPIO_0_0_tri_t[14]} {system_top_i/GPIO_0_0_tri_t[15]} {system_top_i/GPIO_0_0_tri_t[16]} {system_top_i/GPIO_0_0_tri_t[17]} {system_top_i/GPIO_0_0_tri_t[18]} {system_top_i/GPIO_0_0_tri_t[19]} {system_top_i/GPIO_0_0_tri_t[20]} {system_top_i/GPIO_0_0_tri_t[21]} {system_top_i/GPIO_0_0_tri_t[22]} {system_top_i/GPIO_0_0_tri_t[23]} {system_top_i/GPIO_0_0_tri_t[24]} {system_top_i/GPIO_0_0_tri_t[25]} {system_top_i/GPIO_0_0_tri_t[26]} {system_top_i/GPIO_0_0_tri_t[27]} {system_top_i/GPIO_0_0_tri_t[28]} {system_top_i/GPIO_0_0_tri_t[29]} {system_top_i/GPIO_0_0_tri_t[30]} {system_top_i/GPIO_0_0_tri_t[31]} {system_top_i/GPIO_0_0_tri_t[32]} {system_top_i/GPIO_0_0_tri_t[33]} {system_top_i/GPIO_0_0_tri_t[34]} {system_top_i/GPIO_0_0_tri_t[35]} {system_top_i/GPIO_0_0_tri_t[36]} {system_top_i/GPIO_0_0_tri_t[37]} {system_top_i/GPIO_0_0_tri_t[38]} {system_top_i/GPIO_0_0_tri_t[39]} {system_top_i/GPIO_0_0_tri_t[40]} {system_top_i/GPIO_0_0_tri_t[41]} {system_top_i/GPIO_0_0_tri_t[42]} {system_top_i/GPIO_0_0_tri_t[43]} {system_top_i/GPIO_0_0_tri_t[44]} {system_top_i/GPIO_0_0_tri_t[45]} {system_top_i/GPIO_0_0_tri_t[46]} {system_top_i/GPIO_0_0_tri_t[47]} {system_top_i/GPIO_0_0_tri_t[48]} {system_top_i/GPIO_0_0_tri_t[49]} {system_top_i/GPIO_0_0_tri_t[50]} {system_top_i/GPIO_0_0_tri_t[51]} {system_top_i/GPIO_0_0_tri_t[52]} {system_top_i/GPIO_0_0_tri_t[53]} {system_top_i/GPIO_0_0_tri_t[54]} {system_top_i/GPIO_0_0_tri_t[55]} {system_top_i/GPIO_0_0_tri_t[56]} {system_top_i/GPIO_0_0_tri_t[57]} {system_top_i/GPIO_0_0_tri_t[58]} {system_top_i/GPIO_0_0_tri_t[59]} {system_top_i/GPIO_0_0_tri_t[60]} {system_top_i/GPIO_0_0_tri_t[61]} {system_top_i/GPIO_0_0_tri_t[62]} {system_top_i/GPIO_0_0_tri_t[63]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
|
||||
set_property port_width 13 [get_debug_ports u_ila_0/probe3]
|
||||
connect_debug_port u_ila_0/probe3 [get_nets [list {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[0]} {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[1]} {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[2]} {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[3]} {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[4]} {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[5]} {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[6]} {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[7]} {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[8]} {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[9]} {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[10]} {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[11]} {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[12]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe4]
|
||||
connect_debug_port u_ila_0/probe4 [get_nets [list system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/capture_cdc]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe5]
|
||||
connect_debug_port u_ila_0/probe5 [get_nets [list NRST_OBUF]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe6]
|
||||
connect_debug_port u_ila_0/probe6 [get_nets [list system_top_i/blk_mem_gen_0/U0/rstb_busy]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe7]
|
||||
connect_debug_port u_ila_0/probe7 [get_nets [list system_top_i/SPI_0_0_io0_i]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe8]
|
||||
connect_debug_port u_ila_0/probe8 [get_nets [list system_top_i/SPI_0_0_io0_o]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe9]
|
||||
connect_debug_port u_ila_0/probe9 [get_nets [list system_top_i/SPI_0_0_io0_t]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe10]
|
||||
connect_debug_port u_ila_0/probe10 [get_nets [list system_top_i/SPI_0_0_io1_i]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe11]
|
||||
connect_debug_port u_ila_0/probe11 [get_nets [list system_top_i/SPI_0_0_io1_o]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe12]
|
||||
connect_debug_port u_ila_0/probe12 [get_nets [list system_top_i/SPI_0_0_io1_t]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe13]
|
||||
connect_debug_port u_ila_0/probe13 [get_nets [list system_top_i/SPI_0_0_sck_i]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe14]
|
||||
connect_debug_port u_ila_0/probe14 [get_nets [list system_top_i/SPI_0_0_sck_o]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe15]
|
||||
connect_debug_port u_ila_0/probe15 [get_nets [list system_top_i/SPI_0_0_sck_t]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe16]
|
||||
connect_debug_port u_ila_0/probe16 [get_nets [list system_top_i/SPI_0_0_ss1_o]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe17]
|
||||
connect_debug_port u_ila_0/probe17 [get_nets [list system_top_i/SPI_0_0_ss2_o]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe18]
|
||||
connect_debug_port u_ila_0/probe18 [get_nets [list system_top_i/SPI_0_0_ss_i]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe19]
|
||||
connect_debug_port u_ila_0/probe19 [get_nets [list system_top_i/SPI_0_0_ss_o]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe20]
|
||||
connect_debug_port u_ila_0/probe20 [get_nets [list system_top_i/SPI_0_0_ss_t]]
|
||||
create_debug_core u_ila_1 ila
|
||||
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_1]
|
||||
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_1]
|
||||
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_1]
|
||||
set_property C_DATA_DEPTH 8192 [get_debug_cores u_ila_1]
|
||||
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_1]
|
||||
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_1]
|
||||
set_property C_TRIGIN_EN false [get_debug_cores u_ila_1]
|
||||
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_1]
|
||||
set_property port_width 1 [get_debug_ports u_ila_1/clk]
|
||||
connect_debug_port u_ila_1/clk [get_nets [list cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/CLK]]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe0]
|
||||
set_property port_width 8 [get_debug_ports u_ila_1/probe0]
|
||||
connect_debug_port u_ila_1/probe0 [get_nets [list {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_neg[0]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_neg[1]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_neg[2]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_neg[3]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_neg[4]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_neg[5]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_neg[6]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_neg[7]}]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe1]
|
||||
set_property port_width 16 [get_debug_ports u_ila_1/probe1]
|
||||
connect_debug_port u_ila_1/probe1 [get_nets [list {rx1_i_data[0]} {rx1_i_data[1]} {rx1_i_data[2]} {rx1_i_data[3]} {rx1_i_data[4]} {rx1_i_data[5]} {rx1_i_data[6]} {rx1_i_data[7]} {rx1_i_data[8]} {rx1_i_data[9]} {rx1_i_data[10]} {rx1_i_data[11]} {rx1_i_data[12]} {rx1_i_data[13]} {rx1_i_data[14]} {rx1_i_data[15]}]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe2]
|
||||
set_property port_width 8 [get_debug_ports u_ila_1/probe2]
|
||||
connect_debug_port u_ila_1/probe2 [get_nets [list {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_pos[0]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_pos[1]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_pos[2]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_pos[3]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_pos[4]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_pos[5]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_pos[6]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_pos[7]}]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe3]
|
||||
set_property port_width 8 [get_debug_ports u_ila_1/probe3]
|
||||
connect_debug_port u_ila_1/probe3 [get_nets [list {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_pos[0]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_pos[1]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_pos[2]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_pos[3]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_pos[4]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_pos[5]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_pos[6]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_pos[7]}]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe4]
|
||||
set_property port_width 16 [get_debug_ports u_ila_1/probe4]
|
||||
connect_debug_port u_ila_1/probe4 [get_nets [list {tx1_i_data[0]} {tx1_i_data[1]} {tx1_i_data[2]} {tx1_i_data[3]} {tx1_i_data[4]} {tx1_i_data[5]} {tx1_i_data[6]} {tx1_i_data[7]} {tx1_i_data[8]} {tx1_i_data[9]} {tx1_i_data[10]} {tx1_i_data[11]} {tx1_i_data[12]} {tx1_i_data[13]} {tx1_i_data[14]} {tx1_i_data[15]}]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe5]
|
||||
set_property port_width 16 [get_debug_ports u_ila_1/probe5]
|
||||
connect_debug_port u_ila_1/probe5 [get_nets [list {tx1_q_data[0]} {tx1_q_data[1]} {tx1_q_data[2]} {tx1_q_data[3]} {tx1_q_data[4]} {tx1_q_data[5]} {tx1_q_data[6]} {tx1_q_data[7]} {tx1_q_data[8]} {tx1_q_data[9]} {tx1_q_data[10]} {tx1_q_data[11]} {tx1_q_data[12]} {tx1_q_data[13]} {tx1_q_data[14]} {tx1_q_data[15]}]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe6]
|
||||
set_property port_width 16 [get_debug_ports u_ila_1/probe6]
|
||||
connect_debug_port u_ila_1/probe6 [get_nets [list {rx1_q_data[0]} {rx1_q_data[1]} {rx1_q_data[2]} {rx1_q_data[3]} {rx1_q_data[4]} {rx1_q_data[5]} {rx1_q_data[6]} {rx1_q_data[7]} {rx1_q_data[8]} {rx1_q_data[9]} {rx1_q_data[10]} {rx1_q_data[11]} {rx1_q_data[12]} {rx1_q_data[13]} {rx1_q_data[14]} {rx1_q_data[15]}]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe7]
|
||||
set_property port_width 8 [get_debug_ports u_ila_1/probe7]
|
||||
connect_debug_port u_ila_1/probe7 [get_nets [list {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_neg[0]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_neg[1]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_neg[2]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_neg[3]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_neg[4]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_neg[5]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_neg[6]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_neg[7]}]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe8]
|
||||
set_property port_width 32 [get_debug_ports u_ila_1/probe8]
|
||||
connect_debug_port u_ila_1/probe8 [get_nets [list {system_top_i/c_counter_binary_1_Q[0]} {system_top_i/c_counter_binary_1_Q[1]} {system_top_i/c_counter_binary_1_Q[2]} {system_top_i/c_counter_binary_1_Q[3]} {system_top_i/c_counter_binary_1_Q[4]} {system_top_i/c_counter_binary_1_Q[5]} {system_top_i/c_counter_binary_1_Q[6]} {system_top_i/c_counter_binary_1_Q[7]} {system_top_i/c_counter_binary_1_Q[8]} {system_top_i/c_counter_binary_1_Q[9]} {system_top_i/c_counter_binary_1_Q[10]} {system_top_i/c_counter_binary_1_Q[11]} {system_top_i/c_counter_binary_1_Q[12]} {system_top_i/c_counter_binary_1_Q[13]} {system_top_i/c_counter_binary_1_Q[14]} {system_top_i/c_counter_binary_1_Q[15]} {system_top_i/c_counter_binary_1_Q[16]} {system_top_i/c_counter_binary_1_Q[17]} {system_top_i/c_counter_binary_1_Q[18]} {system_top_i/c_counter_binary_1_Q[19]} {system_top_i/c_counter_binary_1_Q[20]} {system_top_i/c_counter_binary_1_Q[21]} {system_top_i/c_counter_binary_1_Q[22]} {system_top_i/c_counter_binary_1_Q[23]} {system_top_i/c_counter_binary_1_Q[24]} {system_top_i/c_counter_binary_1_Q[25]} {system_top_i/c_counter_binary_1_Q[26]} {system_top_i/c_counter_binary_1_Q[27]} {system_top_i/c_counter_binary_1_Q[28]} {system_top_i/c_counter_binary_1_Q[29]} {system_top_i/c_counter_binary_1_Q[30]} {system_top_i/c_counter_binary_1_Q[31]}]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe9]
|
||||
set_property port_width 1 [get_debug_ports u_ila_1/probe9]
|
||||
connect_debug_port u_ila_1/probe9 [get_nets [list system_top_i/CE]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe10]
|
||||
set_property port_width 1 [get_debug_ports u_ila_1/probe10]
|
||||
connect_debug_port u_ila_1/probe10 [get_nets [list cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FRAME_neg]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe11]
|
||||
set_property port_width 1 [get_debug_ports u_ila_1/probe11]
|
||||
connect_debug_port u_ila_1/probe11 [get_nets [list cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FRAME_pos]]
|
||||
create_debug_core u_ila_2 ila
|
||||
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_2]
|
||||
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_2]
|
||||
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_2]
|
||||
set_property C_DATA_DEPTH 8192 [get_debug_cores u_ila_2]
|
||||
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_2]
|
||||
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_2]
|
||||
set_property C_TRIGIN_EN false [get_debug_cores u_ila_2]
|
||||
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_2]
|
||||
set_property port_width 1 [get_debug_ports u_ila_2/clk]
|
||||
connect_debug_port u_ila_2/clk [get_nets [list cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/CLK]]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe0]
|
||||
set_property port_width 16 [get_debug_ports u_ila_2/probe0]
|
||||
connect_debug_port u_ila_2/probe0 [get_nets [list {rx2_i_data[0]} {rx2_i_data[1]} {rx2_i_data[2]} {rx2_i_data[3]} {rx2_i_data[4]} {rx2_i_data[5]} {rx2_i_data[6]} {rx2_i_data[7]} {rx2_i_data[8]} {rx2_i_data[9]} {rx2_i_data[10]} {rx2_i_data[11]} {rx2_i_data[12]} {rx2_i_data[13]} {rx2_i_data[14]} {rx2_i_data[15]}]]
|
||||
create_debug_port u_ila_2 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe1]
|
||||
set_property port_width 8 [get_debug_ports u_ila_2/probe1]
|
||||
connect_debug_port u_ila_2/probe1 [get_nets [list {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_neg[0]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_neg[1]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_neg[2]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_neg[3]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_neg[4]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_neg[5]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_neg[6]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_neg[7]}]]
|
||||
create_debug_port u_ila_2 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe2]
|
||||
set_property port_width 8 [get_debug_ports u_ila_2/probe2]
|
||||
connect_debug_port u_ila_2/probe2 [get_nets [list {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_neg[0]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_neg[1]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_neg[2]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_neg[3]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_neg[4]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_neg[5]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_neg[6]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_neg[7]}]]
|
||||
create_debug_port u_ila_2 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe3]
|
||||
set_property port_width 16 [get_debug_ports u_ila_2/probe3]
|
||||
connect_debug_port u_ila_2/probe3 [get_nets [list {tx2_i_data[0]} {tx2_i_data[1]} {tx2_i_data[2]} {tx2_i_data[3]} {tx2_i_data[4]} {tx2_i_data[5]} {tx2_i_data[6]} {tx2_i_data[7]} {tx2_i_data[8]} {tx2_i_data[9]} {tx2_i_data[10]} {tx2_i_data[11]} {tx2_i_data[12]} {tx2_i_data[13]} {tx2_i_data[14]} {tx2_i_data[15]}]]
|
||||
create_debug_port u_ila_2 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe4]
|
||||
set_property port_width 32 [get_debug_ports u_ila_2/probe4]
|
||||
connect_debug_port u_ila_2/probe4 [get_nets [list {system_top_i/c_counter_binary_2_Q[0]} {system_top_i/c_counter_binary_2_Q[1]} {system_top_i/c_counter_binary_2_Q[2]} {system_top_i/c_counter_binary_2_Q[3]} {system_top_i/c_counter_binary_2_Q[4]} {system_top_i/c_counter_binary_2_Q[5]} {system_top_i/c_counter_binary_2_Q[6]} {system_top_i/c_counter_binary_2_Q[7]} {system_top_i/c_counter_binary_2_Q[8]} {system_top_i/c_counter_binary_2_Q[9]} {system_top_i/c_counter_binary_2_Q[10]} {system_top_i/c_counter_binary_2_Q[11]} {system_top_i/c_counter_binary_2_Q[12]} {system_top_i/c_counter_binary_2_Q[13]} {system_top_i/c_counter_binary_2_Q[14]} {system_top_i/c_counter_binary_2_Q[15]} {system_top_i/c_counter_binary_2_Q[16]} {system_top_i/c_counter_binary_2_Q[17]} {system_top_i/c_counter_binary_2_Q[18]} {system_top_i/c_counter_binary_2_Q[19]} {system_top_i/c_counter_binary_2_Q[20]} {system_top_i/c_counter_binary_2_Q[21]} {system_top_i/c_counter_binary_2_Q[22]} {system_top_i/c_counter_binary_2_Q[23]} {system_top_i/c_counter_binary_2_Q[24]} {system_top_i/c_counter_binary_2_Q[25]} {system_top_i/c_counter_binary_2_Q[26]} {system_top_i/c_counter_binary_2_Q[27]} {system_top_i/c_counter_binary_2_Q[28]} {system_top_i/c_counter_binary_2_Q[29]} {system_top_i/c_counter_binary_2_Q[30]} {system_top_i/c_counter_binary_2_Q[31]}]]
|
||||
create_debug_port u_ila_2 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe5]
|
||||
set_property port_width 16 [get_debug_ports u_ila_2/probe5]
|
||||
connect_debug_port u_ila_2/probe5 [get_nets [list {tx2_q_data[0]} {tx2_q_data[1]} {tx2_q_data[2]} {tx2_q_data[3]} {tx2_q_data[4]} {tx2_q_data[5]} {tx2_q_data[6]} {tx2_q_data[7]} {tx2_q_data[8]} {tx2_q_data[9]} {tx2_q_data[10]} {tx2_q_data[11]} {tx2_q_data[12]} {tx2_q_data[13]} {tx2_q_data[14]} {tx2_q_data[15]}]]
|
||||
create_debug_port u_ila_2 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe6]
|
||||
set_property port_width 16 [get_debug_ports u_ila_2/probe6]
|
||||
connect_debug_port u_ila_2/probe6 [get_nets [list {rx2_q_data[0]} {rx2_q_data[1]} {rx2_q_data[2]} {rx2_q_data[3]} {rx2_q_data[4]} {rx2_q_data[5]} {rx2_q_data[6]} {rx2_q_data[7]} {rx2_q_data[8]} {rx2_q_data[9]} {rx2_q_data[10]} {rx2_q_data[11]} {rx2_q_data[12]} {rx2_q_data[13]} {rx2_q_data[14]} {rx2_q_data[15]}]]
|
||||
create_debug_port u_ila_2 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe7]
|
||||
set_property port_width 8 [get_debug_ports u_ila_2/probe7]
|
||||
connect_debug_port u_ila_2/probe7 [get_nets [list {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_pos[0]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_pos[1]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_pos[2]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_pos[3]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_pos[4]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_pos[5]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_pos[6]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_pos[7]}]]
|
||||
create_debug_port u_ila_2 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe8]
|
||||
set_property port_width 8 [get_debug_ports u_ila_2/probe8]
|
||||
connect_debug_port u_ila_2/probe8 [get_nets [list {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_pos[0]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_pos[1]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_pos[2]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_pos[3]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_pos[4]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_pos[5]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_pos[6]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_pos[7]}]]
|
||||
create_debug_port u_ila_2 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe9]
|
||||
set_property port_width 1 [get_debug_ports u_ila_2/probe9]
|
||||
connect_debug_port u_ila_2/probe9 [get_nets [list system_top_i/CE_1]]
|
||||
create_debug_port u_ila_2 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe10]
|
||||
set_property port_width 1 [get_debug_ports u_ila_2/probe10]
|
||||
connect_debug_port u_ila_2/probe10 [get_nets [list cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FRAME_neg]]
|
||||
create_debug_port u_ila_2 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe11]
|
||||
set_property port_width 1 [get_debug_ports u_ila_2/probe11]
|
||||
connect_debug_port u_ila_2/probe11 [get_nets [list cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FRAME_pos]]
|
||||
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
|
||||
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
|
||||
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
|
||||
connect_debug_port dbg_hub/clk [get_nets ui_clk]
|
||||
@@ -0,0 +1,86 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2022/05/19 13:23:50
|
||||
// Design Name:
|
||||
// Module Name: tb
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module tb(
|
||||
|
||||
);
|
||||
reg aclk,S_AXI_ACLK;
|
||||
|
||||
reg[31:0] slv_reg0,slv_reg1;
|
||||
|
||||
|
||||
initial begin
|
||||
aclk = 0;
|
||||
S_AXI_ACLK = 0;
|
||||
#100 slv_reg0 = 0;
|
||||
#100 slv_reg1 = 8192;
|
||||
#100 slv_reg0 = 1;
|
||||
end
|
||||
|
||||
always #2 aclk=~aclk;
|
||||
always #1 S_AXI_ACLK=~S_AXI_ACLK;
|
||||
|
||||
|
||||
wire capture_cdc;
|
||||
wire [25:0] length_cdc;
|
||||
|
||||
xpm_cdc_array_single #(
|
||||
.DEST_SYNC_FF(4), // DECIMAL; range: 2-10
|
||||
.INIT_SYNC_FF(0), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values
|
||||
.SIM_ASSERT_CHK(0), // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
|
||||
.SRC_INPUT_REG(1), // DECIMAL; 0=do not register input, 1=register input
|
||||
.WIDTH(1) // DECIMAL; range: 1-1024
|
||||
)
|
||||
xpm_cdc_array_single_inst0 (
|
||||
.dest_out(capture_cdc), // WIDTH-bit output: src_in synchronized to the destination clock domain. This
|
||||
// output is registered.
|
||||
|
||||
.dest_clk(aclk), // 1-bit input: Clock signal for the destination clock domain.
|
||||
.src_clk(S_AXI_ACLK), // 1-bit input: optional; required when SRC_INPUT_REG = 1
|
||||
.src_in(slv_reg0[0]) // WIDTH-bit input: Input single-bit array to be synchronized to destination clock
|
||||
// domain. It is assumed that each bit of the array is unrelated to the others. This
|
||||
// is reflected in the constraints applied to this macro. To transfer a binary value
|
||||
// losslessly across the two clock domains, use the XPM_CDC_GRAY macro instead.
|
||||
|
||||
);
|
||||
|
||||
xpm_cdc_array_single #(
|
||||
.DEST_SYNC_FF(4), // DECIMAL; range: 2-10
|
||||
.INIT_SYNC_FF(0), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values
|
||||
.SIM_ASSERT_CHK(0), // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
|
||||
.SRC_INPUT_REG(1), // DECIMAL; 0=do not register input, 1=register input
|
||||
.WIDTH(26) // DECIMAL; range: 1-1024
|
||||
)
|
||||
xpm_cdc_array_single_inst1 (
|
||||
.dest_out(length_cdc), // WIDTH-bit output: src_in synchronized to the destination clock domain. This
|
||||
// output is registered.
|
||||
|
||||
.dest_clk(aclk), // 1-bit input: Clock signal for the destination clock domain.
|
||||
.src_clk(S_AXI_ACLK), // 1-bit input: optional; required when SRC_INPUT_REG = 1
|
||||
.src_in(slv_reg1[25:0]) // WIDTH-bit input: Input single-bit array to be synchronized to destination clock
|
||||
// domain. It is assumed that each bit of the array is unrelated to the others. This
|
||||
// is reflected in the constraints applied to this macro. To transfer a binary value
|
||||
// losslessly across the two clock domains, use the XPM_CDC_GRAY macro instead.
|
||||
|
||||
);
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,11 @@
|
||||
{
|
||||
"design": {
|
||||
"design_info": {
|
||||
"boundary_crc": "0x0",
|
||||
"name": "bin_rom",
|
||||
"synth_flow_mode": "Hierarchical",
|
||||
"tool_version": "2018.3"
|
||||
},
|
||||
"design_tree": {}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,11 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<Root MajorVersion="0" MinorVersion="36">
|
||||
<CompositeFile CompositeFileTopName="bin_rom" CanBeSetAsTop="false" CanDisplayChildGraph="true">
|
||||
<Description>Composite Fileset</Description>
|
||||
<Generation Name="SYNTHESIS" State="STALE" Timestamp="1700708194"/>
|
||||
<Generation Name="IMPLEMENTATION" State="STALE" Timestamp="1700708194"/>
|
||||
<Generation Name="SIMULATION" State="STALE" Timestamp="1700708194"/>
|
||||
<Generation Name="HW_HANDOFF" State="STALE" Timestamp="1700708194"/>
|
||||
<FileCollection Name="SOURCES" Type="SOURCES"/>
|
||||
</CompositeFile>
|
||||
</Root>
|
||||
+269
@@ -0,0 +1,269 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "system_top_Axis_adc_data_packer_0_0",
|
||||
"cell_name": "Axis_adc_data_packer_0",
|
||||
"component_reference": "labnet.com:user:Axis_adc_data_packer:1.0",
|
||||
"ip_revision": "9",
|
||||
"gen_directory": "../../../../../../project_fix_dac.gen/sources_1/bd/system_top/ip/system_top_Axis_adc_data_packer_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"C_S00_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_S00_AXI_ADDR_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_S00_AXI_BASEADDR": [ { "value": "0xFFFFFFFF", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||
"C_S00_AXI_HIGHADDR": [ { "value": "0x00000000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "system_top_Axis_adc_data_packer_0_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_S00_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S00_AXI_ADDR_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "xilinx.com:zc706:part0:1.4" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z045" } ],
|
||||
"NEXTGEN_VERSAL": [ { "value": "0" } ],
|
||||
"PACKAGE": [ { "value": "ffg900" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "9" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../project_fix_dac.gen/sources_1/bd/system_top/ip/system_top_Axis_adc_data_packer_0_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2024.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"aclk": [ { "direction": "in" } ],
|
||||
"aresetn": [ { "direction": "in" } ],
|
||||
"axis_tvalid": [ { "direction": "in" } ],
|
||||
"axis_tlast": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"axis_ready": [ { "direction": "out" } ],
|
||||
"axis_tdata": [ { "direction": "in", "size_left": "63", "size_right": "0", "driver_value": "0" } ],
|
||||
"m_axis_tvalid": [ { "direction": "out" } ],
|
||||
"m_axis_tlast": [ { "direction": "out" } ],
|
||||
"m_axis_ready": [ { "direction": "in" } ],
|
||||
"m_axis_tdata": [ { "direction": "out", "size_left": "63", "size_right": "0" } ],
|
||||
"s00_axi_awaddr": [ { "direction": "in", "size_left": "3", "size_right": "0" } ],
|
||||
"s00_axi_awprot": [ { "direction": "in", "size_left": "2", "size_right": "0" } ],
|
||||
"s00_axi_awvalid": [ { "direction": "in" } ],
|
||||
"s00_axi_awready": [ { "direction": "out" } ],
|
||||
"s00_axi_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
|
||||
"s00_axi_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0" } ],
|
||||
"s00_axi_wvalid": [ { "direction": "in" } ],
|
||||
"s00_axi_wready": [ { "direction": "out" } ],
|
||||
"s00_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s00_axi_bvalid": [ { "direction": "out" } ],
|
||||
"s00_axi_bready": [ { "direction": "in" } ],
|
||||
"s00_axi_araddr": [ { "direction": "in", "size_left": "3", "size_right": "0" } ],
|
||||
"s00_axi_arprot": [ { "direction": "in", "size_left": "2", "size_right": "0" } ],
|
||||
"s00_axi_arvalid": [ { "direction": "in" } ],
|
||||
"s00_axi_arready": [ { "direction": "out" } ],
|
||||
"s00_axi_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"s00_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s00_axi_rvalid": [ { "direction": "out" } ],
|
||||
"s00_axi_rready": [ { "direction": "in" } ],
|
||||
"s00_axi_aclk": [ { "direction": "in" } ],
|
||||
"s00_axi_aresetn": [ { "direction": "in" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"S00_AXI": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"memory_map_ref": "S00_AXI",
|
||||
"parameters": {
|
||||
"WIZ_DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
|
||||
"WIZ_NUM_REG": [ { "value": "4", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "4", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"AWADDR": [ { "physical_name": "s00_axi_awaddr" } ],
|
||||
"AWPROT": [ { "physical_name": "s00_axi_awprot" } ],
|
||||
"AWVALID": [ { "physical_name": "s00_axi_awvalid" } ],
|
||||
"AWREADY": [ { "physical_name": "s00_axi_awready" } ],
|
||||
"WDATA": [ { "physical_name": "s00_axi_wdata" } ],
|
||||
"WSTRB": [ { "physical_name": "s00_axi_wstrb" } ],
|
||||
"WVALID": [ { "physical_name": "s00_axi_wvalid" } ],
|
||||
"WREADY": [ { "physical_name": "s00_axi_wready" } ],
|
||||
"BRESP": [ { "physical_name": "s00_axi_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "s00_axi_bvalid" } ],
|
||||
"BREADY": [ { "physical_name": "s00_axi_bready" } ],
|
||||
"ARADDR": [ { "physical_name": "s00_axi_araddr" } ],
|
||||
"ARPROT": [ { "physical_name": "s00_axi_arprot" } ],
|
||||
"ARVALID": [ { "physical_name": "s00_axi_arvalid" } ],
|
||||
"ARREADY": [ { "physical_name": "s00_axi_arready" } ],
|
||||
"RDATA": [ { "physical_name": "s00_axi_rdata" } ],
|
||||
"RRESP": [ { "physical_name": "s00_axi_rresp" } ],
|
||||
"RVALID": [ { "physical_name": "s00_axi_rvalid" } ],
|
||||
"RREADY": [ { "physical_name": "s00_axi_rready" } ]
|
||||
}
|
||||
},
|
||||
"S00_AXI_RST": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "s00_axi_aresetn" } ]
|
||||
}
|
||||
},
|
||||
"S00_AXI_CLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S00_AXI", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "s00_axi_aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "s00_axi_aclk" } ]
|
||||
}
|
||||
},
|
||||
"m_axis": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "8", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_data_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "m_axis_tdata" } ],
|
||||
"TLAST": [ { "physical_name": "m_axis_tlast" } ],
|
||||
"TVALID": [ { "physical_name": "m_axis_tvalid" } ],
|
||||
"TREADY": [ { "physical_name": "m_axis_ready" } ]
|
||||
}
|
||||
},
|
||||
"aclk": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "axis:m_axis", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_data_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "aclk" } ]
|
||||
}
|
||||
},
|
||||
"aresetn": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "aresetn" } ]
|
||||
}
|
||||
},
|
||||
"axis": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "8", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_data_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "axis_tdata" } ],
|
||||
"TLAST": [ { "physical_name": "axis_tlast" } ],
|
||||
"TVALID": [ { "physical_name": "axis_tvalid" } ],
|
||||
"TREADY": [ { "physical_name": "axis_ready" } ]
|
||||
}
|
||||
}
|
||||
},
|
||||
"memory_maps": {
|
||||
"S00_AXI": {
|
||||
"address_blocks": {
|
||||
"S00_AXI_reg": {
|
||||
"base_address": "0",
|
||||
"range": "4096",
|
||||
"usage": "register",
|
||||
"parameters": {
|
||||
"OFFSET_BASE_PARAM": [ { "value": "C_S00_AXI_BASEADDR" } ],
|
||||
"OFFSET_HIGH_PARAM": [ { "value": "C_S00_AXI_HIGHADDR" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+269
@@ -0,0 +1,269 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "system_top_Axis_adc_data_packer_1_0",
|
||||
"cell_name": "Axis_adc_data_packer_1",
|
||||
"component_reference": "labnet.com:user:Axis_adc_data_packer:1.0",
|
||||
"ip_revision": "9",
|
||||
"gen_directory": "../../../../../../project_fix_dac.gen/sources_1/bd/system_top/ip/system_top_Axis_adc_data_packer_1_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"C_S00_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_S00_AXI_ADDR_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_S00_AXI_BASEADDR": [ { "value": "0xFFFFFFFF", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||
"C_S00_AXI_HIGHADDR": [ { "value": "0x00000000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "system_top_Axis_adc_data_packer_1_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_S00_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S00_AXI_ADDR_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "xilinx.com:zc706:part0:1.4" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z045" } ],
|
||||
"NEXTGEN_VERSAL": [ { "value": "0" } ],
|
||||
"PACKAGE": [ { "value": "ffg900" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "9" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../project_fix_dac.gen/sources_1/bd/system_top/ip/system_top_Axis_adc_data_packer_1_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2024.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"aclk": [ { "direction": "in" } ],
|
||||
"aresetn": [ { "direction": "in" } ],
|
||||
"axis_tvalid": [ { "direction": "in" } ],
|
||||
"axis_tlast": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"axis_ready": [ { "direction": "out" } ],
|
||||
"axis_tdata": [ { "direction": "in", "size_left": "63", "size_right": "0", "driver_value": "0" } ],
|
||||
"m_axis_tvalid": [ { "direction": "out" } ],
|
||||
"m_axis_tlast": [ { "direction": "out" } ],
|
||||
"m_axis_ready": [ { "direction": "in" } ],
|
||||
"m_axis_tdata": [ { "direction": "out", "size_left": "63", "size_right": "0" } ],
|
||||
"s00_axi_awaddr": [ { "direction": "in", "size_left": "3", "size_right": "0" } ],
|
||||
"s00_axi_awprot": [ { "direction": "in", "size_left": "2", "size_right": "0" } ],
|
||||
"s00_axi_awvalid": [ { "direction": "in" } ],
|
||||
"s00_axi_awready": [ { "direction": "out" } ],
|
||||
"s00_axi_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
|
||||
"s00_axi_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0" } ],
|
||||
"s00_axi_wvalid": [ { "direction": "in" } ],
|
||||
"s00_axi_wready": [ { "direction": "out" } ],
|
||||
"s00_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s00_axi_bvalid": [ { "direction": "out" } ],
|
||||
"s00_axi_bready": [ { "direction": "in" } ],
|
||||
"s00_axi_araddr": [ { "direction": "in", "size_left": "3", "size_right": "0" } ],
|
||||
"s00_axi_arprot": [ { "direction": "in", "size_left": "2", "size_right": "0" } ],
|
||||
"s00_axi_arvalid": [ { "direction": "in" } ],
|
||||
"s00_axi_arready": [ { "direction": "out" } ],
|
||||
"s00_axi_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"s00_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s00_axi_rvalid": [ { "direction": "out" } ],
|
||||
"s00_axi_rready": [ { "direction": "in" } ],
|
||||
"s00_axi_aclk": [ { "direction": "in" } ],
|
||||
"s00_axi_aresetn": [ { "direction": "in" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"S00_AXI": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"memory_map_ref": "S00_AXI",
|
||||
"parameters": {
|
||||
"WIZ_DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
|
||||
"WIZ_NUM_REG": [ { "value": "4", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "4", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"AWADDR": [ { "physical_name": "s00_axi_awaddr" } ],
|
||||
"AWPROT": [ { "physical_name": "s00_axi_awprot" } ],
|
||||
"AWVALID": [ { "physical_name": "s00_axi_awvalid" } ],
|
||||
"AWREADY": [ { "physical_name": "s00_axi_awready" } ],
|
||||
"WDATA": [ { "physical_name": "s00_axi_wdata" } ],
|
||||
"WSTRB": [ { "physical_name": "s00_axi_wstrb" } ],
|
||||
"WVALID": [ { "physical_name": "s00_axi_wvalid" } ],
|
||||
"WREADY": [ { "physical_name": "s00_axi_wready" } ],
|
||||
"BRESP": [ { "physical_name": "s00_axi_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "s00_axi_bvalid" } ],
|
||||
"BREADY": [ { "physical_name": "s00_axi_bready" } ],
|
||||
"ARADDR": [ { "physical_name": "s00_axi_araddr" } ],
|
||||
"ARPROT": [ { "physical_name": "s00_axi_arprot" } ],
|
||||
"ARVALID": [ { "physical_name": "s00_axi_arvalid" } ],
|
||||
"ARREADY": [ { "physical_name": "s00_axi_arready" } ],
|
||||
"RDATA": [ { "physical_name": "s00_axi_rdata" } ],
|
||||
"RRESP": [ { "physical_name": "s00_axi_rresp" } ],
|
||||
"RVALID": [ { "physical_name": "s00_axi_rvalid" } ],
|
||||
"RREADY": [ { "physical_name": "s00_axi_rready" } ]
|
||||
}
|
||||
},
|
||||
"S00_AXI_RST": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "s00_axi_aresetn" } ]
|
||||
}
|
||||
},
|
||||
"S00_AXI_CLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S00_AXI", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "s00_axi_aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "s00_axi_aclk" } ]
|
||||
}
|
||||
},
|
||||
"m_axis": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "8", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_data_clk_1", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "m_axis_tdata" } ],
|
||||
"TLAST": [ { "physical_name": "m_axis_tlast" } ],
|
||||
"TVALID": [ { "physical_name": "m_axis_tvalid" } ],
|
||||
"TREADY": [ { "physical_name": "m_axis_ready" } ]
|
||||
}
|
||||
},
|
||||
"aclk": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "axis:m_axis", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_data_clk_1", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "aclk" } ]
|
||||
}
|
||||
},
|
||||
"aresetn": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "aresetn" } ]
|
||||
}
|
||||
},
|
||||
"axis": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "8", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_data_clk_1", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "axis_tdata" } ],
|
||||
"TLAST": [ { "physical_name": "axis_tlast" } ],
|
||||
"TVALID": [ { "physical_name": "axis_tvalid" } ],
|
||||
"TREADY": [ { "physical_name": "axis_ready" } ]
|
||||
}
|
||||
}
|
||||
},
|
||||
"memory_maps": {
|
||||
"S00_AXI": {
|
||||
"address_blocks": {
|
||||
"S00_AXI_reg": {
|
||||
"base_address": "0",
|
||||
"range": "4096",
|
||||
"usage": "register",
|
||||
"parameters": {
|
||||
"OFFSET_BASE_PARAM": [ { "value": "C_S00_AXI_BASEADDR" } ],
|
||||
"OFFSET_HIGH_PARAM": [ { "value": "C_S00_AXI_HIGHADDR" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+269
@@ -0,0 +1,269 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "system_top_Axis_adc_data_packer_2_0",
|
||||
"cell_name": "Axis_adc_data_packer_2",
|
||||
"component_reference": "labnet.com:user:Axis_adc_data_packer:1.0",
|
||||
"ip_revision": "9",
|
||||
"gen_directory": "../../../../../../project_fix_dac.gen/sources_1/bd/system_top/ip/system_top_Axis_adc_data_packer_2_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"C_S00_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_S00_AXI_ADDR_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_S00_AXI_BASEADDR": [ { "value": "0xFFFFFFFF", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||
"C_S00_AXI_HIGHADDR": [ { "value": "0x00000000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "system_top_Axis_adc_data_packer_2_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_S00_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S00_AXI_ADDR_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "xilinx.com:zc706:part0:1.4" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z045" } ],
|
||||
"NEXTGEN_VERSAL": [ { "value": "0" } ],
|
||||
"PACKAGE": [ { "value": "ffg900" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "9" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../project_fix_dac.gen/sources_1/bd/system_top/ip/system_top_Axis_adc_data_packer_2_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2024.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"aclk": [ { "direction": "in" } ],
|
||||
"aresetn": [ { "direction": "in" } ],
|
||||
"axis_tvalid": [ { "direction": "in" } ],
|
||||
"axis_tlast": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"axis_ready": [ { "direction": "out" } ],
|
||||
"axis_tdata": [ { "direction": "in", "size_left": "63", "size_right": "0", "driver_value": "0" } ],
|
||||
"m_axis_tvalid": [ { "direction": "out" } ],
|
||||
"m_axis_tlast": [ { "direction": "out" } ],
|
||||
"m_axis_ready": [ { "direction": "in" } ],
|
||||
"m_axis_tdata": [ { "direction": "out", "size_left": "63", "size_right": "0" } ],
|
||||
"s00_axi_awaddr": [ { "direction": "in", "size_left": "3", "size_right": "0" } ],
|
||||
"s00_axi_awprot": [ { "direction": "in", "size_left": "2", "size_right": "0" } ],
|
||||
"s00_axi_awvalid": [ { "direction": "in" } ],
|
||||
"s00_axi_awready": [ { "direction": "out" } ],
|
||||
"s00_axi_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
|
||||
"s00_axi_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0" } ],
|
||||
"s00_axi_wvalid": [ { "direction": "in" } ],
|
||||
"s00_axi_wready": [ { "direction": "out" } ],
|
||||
"s00_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s00_axi_bvalid": [ { "direction": "out" } ],
|
||||
"s00_axi_bready": [ { "direction": "in" } ],
|
||||
"s00_axi_araddr": [ { "direction": "in", "size_left": "3", "size_right": "0" } ],
|
||||
"s00_axi_arprot": [ { "direction": "in", "size_left": "2", "size_right": "0" } ],
|
||||
"s00_axi_arvalid": [ { "direction": "in" } ],
|
||||
"s00_axi_arready": [ { "direction": "out" } ],
|
||||
"s00_axi_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"s00_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s00_axi_rvalid": [ { "direction": "out" } ],
|
||||
"s00_axi_rready": [ { "direction": "in" } ],
|
||||
"s00_axi_aclk": [ { "direction": "in" } ],
|
||||
"s00_axi_aresetn": [ { "direction": "in" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"S00_AXI": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"memory_map_ref": "S00_AXI",
|
||||
"parameters": {
|
||||
"WIZ_DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
|
||||
"WIZ_NUM_REG": [ { "value": "4", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "4", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"AWADDR": [ { "physical_name": "s00_axi_awaddr" } ],
|
||||
"AWPROT": [ { "physical_name": "s00_axi_awprot" } ],
|
||||
"AWVALID": [ { "physical_name": "s00_axi_awvalid" } ],
|
||||
"AWREADY": [ { "physical_name": "s00_axi_awready" } ],
|
||||
"WDATA": [ { "physical_name": "s00_axi_wdata" } ],
|
||||
"WSTRB": [ { "physical_name": "s00_axi_wstrb" } ],
|
||||
"WVALID": [ { "physical_name": "s00_axi_wvalid" } ],
|
||||
"WREADY": [ { "physical_name": "s00_axi_wready" } ],
|
||||
"BRESP": [ { "physical_name": "s00_axi_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "s00_axi_bvalid" } ],
|
||||
"BREADY": [ { "physical_name": "s00_axi_bready" } ],
|
||||
"ARADDR": [ { "physical_name": "s00_axi_araddr" } ],
|
||||
"ARPROT": [ { "physical_name": "s00_axi_arprot" } ],
|
||||
"ARVALID": [ { "physical_name": "s00_axi_arvalid" } ],
|
||||
"ARREADY": [ { "physical_name": "s00_axi_arready" } ],
|
||||
"RDATA": [ { "physical_name": "s00_axi_rdata" } ],
|
||||
"RRESP": [ { "physical_name": "s00_axi_rresp" } ],
|
||||
"RVALID": [ { "physical_name": "s00_axi_rvalid" } ],
|
||||
"RREADY": [ { "physical_name": "s00_axi_rready" } ]
|
||||
}
|
||||
},
|
||||
"S00_AXI_RST": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "s00_axi_aresetn" } ]
|
||||
}
|
||||
},
|
||||
"S00_AXI_CLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S00_AXI", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "s00_axi_aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "s00_axi_aclk" } ]
|
||||
}
|
||||
},
|
||||
"m_axis": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "8", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_data_clk_2", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "m_axis_tdata" } ],
|
||||
"TLAST": [ { "physical_name": "m_axis_tlast" } ],
|
||||
"TVALID": [ { "physical_name": "m_axis_tvalid" } ],
|
||||
"TREADY": [ { "physical_name": "m_axis_ready" } ]
|
||||
}
|
||||
},
|
||||
"aclk": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "axis:m_axis", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_data_clk_2", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "aclk" } ]
|
||||
}
|
||||
},
|
||||
"aresetn": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "aresetn" } ]
|
||||
}
|
||||
},
|
||||
"axis": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "8", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_data_clk_2", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "axis_tdata" } ],
|
||||
"TLAST": [ { "physical_name": "axis_tlast" } ],
|
||||
"TVALID": [ { "physical_name": "axis_tvalid" } ],
|
||||
"TREADY": [ { "physical_name": "axis_ready" } ]
|
||||
}
|
||||
}
|
||||
},
|
||||
"memory_maps": {
|
||||
"S00_AXI": {
|
||||
"address_blocks": {
|
||||
"S00_AXI_reg": {
|
||||
"base_address": "0",
|
||||
"range": "4096",
|
||||
"usage": "register",
|
||||
"parameters": {
|
||||
"OFFSET_BASE_PARAM": [ { "value": "C_S00_AXI_BASEADDR" } ],
|
||||
"OFFSET_HIGH_PARAM": [ { "value": "C_S00_AXI_HIGHADDR" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+184
@@ -0,0 +1,184 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "system_top_axi4_lite_spi_0_0",
|
||||
"cell_name": "axi4_lite_spi_0",
|
||||
"component_reference": "cxkj.com:user:axi4_lite_spi:1.0",
|
||||
"ip_revision": "2",
|
||||
"gen_directory": "../../../../../../project_fix_dac.gen/sources_1/bd/system_top/ip/system_top_axi4_lite_spi_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"C_S_AXI_ADDR_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"REGS_SIZE": [ { "value": "24", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SPI_CONFIG": [ { "value": "\"1011101\"", "value_src": "user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||
"BAUD_RATE": [ { "value": "0x0002", "value_src": "user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||
"REG_WIDTH": [ { "value": "8", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CHIP_ADDR_WIDTH": [ { "value": "12", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FOUR_WIRE_SPI": [ { "value": "false", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "system_top_axi4_lite_spi_0_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_S_AXI_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"REGS_SIZE": [ { "value": "24", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"SPI_CONFIG": [ { "value": "\"1011101\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"BAUD_RATE": [ { "value": "0x0002", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"REG_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"CHIP_ADDR_WIDTH": [ { "value": "12", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"FOUR_WIRE_SPI": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "xilinx.com:zc706:part0:1.4" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z045" } ],
|
||||
"NEXTGEN_VERSAL": [ { "value": "0" } ],
|
||||
"PACKAGE": [ { "value": "ffg900" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "2" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../project_fix_dac.gen/sources_1/bd/system_top/ip/system_top_axi4_lite_spi_0_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2024.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"s_axi_aclk": [ { "direction": "in" } ],
|
||||
"s_axi_aresetn": [ { "direction": "in" } ],
|
||||
"s_axi_awaddr": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_awvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_awready": [ { "direction": "out" } ],
|
||||
"s_axi_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "1" } ],
|
||||
"s_axi_wvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_wready": [ { "direction": "out" } ],
|
||||
"s_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s_axi_bvalid": [ { "direction": "out" } ],
|
||||
"s_axi_bready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_araddr": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_arvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_arready": [ { "direction": "out" } ],
|
||||
"s_axi_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"s_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s_axi_rvalid": [ { "direction": "out" } ],
|
||||
"s_axi_rready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"sclk_o": [ { "direction": "out" } ],
|
||||
"ssn_o": [ { "direction": "out" } ],
|
||||
"miso_i": [ { "direction": "in" } ],
|
||||
"mosi_o": [ { "direction": "out" } ],
|
||||
"sdio": [ { "direction": "inout" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"s_axi": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"memory_map_ref": "s_axi",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"AWADDR": [ { "physical_name": "s_axi_awaddr" } ],
|
||||
"AWVALID": [ { "physical_name": "s_axi_awvalid" } ],
|
||||
"AWREADY": [ { "physical_name": "s_axi_awready" } ],
|
||||
"WDATA": [ { "physical_name": "s_axi_wdata" } ],
|
||||
"WSTRB": [ { "physical_name": "s_axi_wstrb" } ],
|
||||
"WVALID": [ { "physical_name": "s_axi_wvalid" } ],
|
||||
"WREADY": [ { "physical_name": "s_axi_wready" } ],
|
||||
"BRESP": [ { "physical_name": "s_axi_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "s_axi_bvalid" } ],
|
||||
"BREADY": [ { "physical_name": "s_axi_bready" } ],
|
||||
"ARADDR": [ { "physical_name": "s_axi_araddr" } ],
|
||||
"ARVALID": [ { "physical_name": "s_axi_arvalid" } ],
|
||||
"ARREADY": [ { "physical_name": "s_axi_arready" } ],
|
||||
"RDATA": [ { "physical_name": "s_axi_rdata" } ],
|
||||
"RRESP": [ { "physical_name": "s_axi_rresp" } ],
|
||||
"RVALID": [ { "physical_name": "s_axi_rvalid" } ],
|
||||
"RREADY": [ { "physical_name": "s_axi_rready" } ]
|
||||
}
|
||||
},
|
||||
"s_axi_aresetn": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "s_axi_aresetn" } ]
|
||||
}
|
||||
},
|
||||
"s_axi_aclk": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "s_axi", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "s_axi_aresetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "s_axi_aclk" } ]
|
||||
}
|
||||
}
|
||||
},
|
||||
"memory_maps": {
|
||||
"s_axi": {
|
||||
"address_blocks": {
|
||||
"reg0": {
|
||||
"base_address": "0",
|
||||
"range": "4294967296",
|
||||
"usage": "register"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+184
@@ -0,0 +1,184 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "system_top_axi4_lite_spi_0_1",
|
||||
"cell_name": "axi4_lite_spi_1",
|
||||
"component_reference": "cxkj.com:user:axi4_lite_spi:1.0",
|
||||
"ip_revision": "2",
|
||||
"gen_directory": "../../../../../../project_fix_dac.gen/sources_1/bd/system_top/ip/system_top_axi4_lite_spi_0_1",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"C_S_AXI_ADDR_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"REGS_SIZE": [ { "value": "24", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SPI_CONFIG": [ { "value": "\"1011101\"", "value_src": "user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||
"BAUD_RATE": [ { "value": "0x0002", "value_src": "user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||
"REG_WIDTH": [ { "value": "8", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CHIP_ADDR_WIDTH": [ { "value": "13", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FOUR_WIRE_SPI": [ { "value": "true", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "system_top_axi4_lite_spi_0_1", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_S_AXI_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"REGS_SIZE": [ { "value": "24", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"SPI_CONFIG": [ { "value": "\"1011101\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"BAUD_RATE": [ { "value": "0x0002", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"REG_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"CHIP_ADDR_WIDTH": [ { "value": "13", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"FOUR_WIRE_SPI": [ { "value": "true", "resolve_type": "generated", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "xilinx.com:zc706:part0:1.4" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z045" } ],
|
||||
"NEXTGEN_VERSAL": [ { "value": "0" } ],
|
||||
"PACKAGE": [ { "value": "ffg900" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "2" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../project_fix_dac.gen/sources_1/bd/system_top/ip/system_top_axi4_lite_spi_0_1" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2024.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"s_axi_aclk": [ { "direction": "in" } ],
|
||||
"s_axi_aresetn": [ { "direction": "in" } ],
|
||||
"s_axi_awaddr": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_awvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_awready": [ { "direction": "out" } ],
|
||||
"s_axi_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "1" } ],
|
||||
"s_axi_wvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_wready": [ { "direction": "out" } ],
|
||||
"s_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s_axi_bvalid": [ { "direction": "out" } ],
|
||||
"s_axi_bready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_araddr": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_arvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_arready": [ { "direction": "out" } ],
|
||||
"s_axi_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"s_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s_axi_rvalid": [ { "direction": "out" } ],
|
||||
"s_axi_rready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"sclk_o": [ { "direction": "out" } ],
|
||||
"ssn_o": [ { "direction": "out" } ],
|
||||
"miso_i": [ { "direction": "in" } ],
|
||||
"mosi_o": [ { "direction": "out" } ],
|
||||
"sdio": [ { "direction": "inout" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"s_axi": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"memory_map_ref": "s_axi",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"AWADDR": [ { "physical_name": "s_axi_awaddr" } ],
|
||||
"AWVALID": [ { "physical_name": "s_axi_awvalid" } ],
|
||||
"AWREADY": [ { "physical_name": "s_axi_awready" } ],
|
||||
"WDATA": [ { "physical_name": "s_axi_wdata" } ],
|
||||
"WSTRB": [ { "physical_name": "s_axi_wstrb" } ],
|
||||
"WVALID": [ { "physical_name": "s_axi_wvalid" } ],
|
||||
"WREADY": [ { "physical_name": "s_axi_wready" } ],
|
||||
"BRESP": [ { "physical_name": "s_axi_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "s_axi_bvalid" } ],
|
||||
"BREADY": [ { "physical_name": "s_axi_bready" } ],
|
||||
"ARADDR": [ { "physical_name": "s_axi_araddr" } ],
|
||||
"ARVALID": [ { "physical_name": "s_axi_arvalid" } ],
|
||||
"ARREADY": [ { "physical_name": "s_axi_arready" } ],
|
||||
"RDATA": [ { "physical_name": "s_axi_rdata" } ],
|
||||
"RRESP": [ { "physical_name": "s_axi_rresp" } ],
|
||||
"RVALID": [ { "physical_name": "s_axi_rvalid" } ],
|
||||
"RREADY": [ { "physical_name": "s_axi_rready" } ]
|
||||
}
|
||||
},
|
||||
"s_axi_aresetn": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "s_axi_aresetn" } ]
|
||||
}
|
||||
},
|
||||
"s_axi_aclk": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "s_axi", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "s_axi_aresetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "s_axi_aclk" } ]
|
||||
}
|
||||
}
|
||||
},
|
||||
"memory_maps": {
|
||||
"s_axi": {
|
||||
"address_blocks": {
|
||||
"reg0": {
|
||||
"base_address": "0",
|
||||
"range": "4294967296",
|
||||
"usage": "register"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+259
@@ -0,0 +1,259 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "system_top_axi_bram_ctrl_0_0",
|
||||
"cell_name": "axi_bram_ctrl_0",
|
||||
"component_reference": "xilinx.com:ip:axi_bram_ctrl:4.1",
|
||||
"ip_revision": "10",
|
||||
"gen_directory": "../../../../../../project_fix_dac.gen/sources_1/bd/system_top/ip/system_top_axi_bram_ctrl_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PROTOCOL": [ { "value": "AXI4", "resolve_type": "user", "usage": "all" } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SINGLE_PORT_BRAM": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ECC_TYPE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"USE_ECC": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FAULT_INJECT": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"ECC_ONOFF_RESET_VALUE": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "system_top_axi_bram_ctrl_0_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"BMG_INSTANCE": [ { "value": "EXTERNAL", "value_permission": "bd", "resolve_type": "user", "usage": "all" } ],
|
||||
"MEM_DEPTH": [ { "value": "8192", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"READ_LATENCY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"RD_CMD_OPTIMIZATION": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_BRAM_INST_MODE": [ { "value": "EXTERNAL", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MEMORY_DEPTH": [ { "value": "8192", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_BRAM_ADDR_WIDTH": [ { "value": "13", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_ADDR_WIDTH": [ { "value": "15", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_ID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_PROTOCOL": [ { "value": "AXI4", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_S_AXI_SUPPORTS_NARROW_BURST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SINGLE_PORT_BRAM": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_FAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_READ_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_RD_CMD_OPTIMIZATION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_CTRL_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_CTRL_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ECC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ECC_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_FAULT_INJECT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ECC_ONOFF_RESET_VALUE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "xilinx.com:zc706:part0:1.4" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z045" } ],
|
||||
"NEXTGEN_VERSAL": [ { "value": "0" } ],
|
||||
"PACKAGE": [ { "value": "ffg900" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "10" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../project_fix_dac.gen/sources_1/bd/system_top/ip/system_top_axi_bram_ctrl_0_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2024.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"s_axi_aclk": [ { "direction": "in" } ],
|
||||
"s_axi_aresetn": [ { "direction": "in" } ],
|
||||
"s_axi_awaddr": [ { "direction": "in", "size_left": "14", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_awlen": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_awsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_awburst": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_awlock": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_awcache": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_awprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_awvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_awready": [ { "direction": "out" } ],
|
||||
"s_axi_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_wlast": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_wvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_wready": [ { "direction": "out" } ],
|
||||
"s_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s_axi_bvalid": [ { "direction": "out" } ],
|
||||
"s_axi_bready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_araddr": [ { "direction": "in", "size_left": "14", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_arlen": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_arsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_arburst": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_arlock": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_arcache": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_arprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_arvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_arready": [ { "direction": "out" } ],
|
||||
"s_axi_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"s_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s_axi_rlast": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"s_axi_rvalid": [ { "direction": "out" } ],
|
||||
"s_axi_rready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"bram_rst_a": [ { "direction": "out" } ],
|
||||
"bram_clk_a": [ { "direction": "out" } ],
|
||||
"bram_en_a": [ { "direction": "out" } ],
|
||||
"bram_we_a": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||
"bram_addr_a": [ { "direction": "out", "size_left": "14", "size_right": "0" } ],
|
||||
"bram_wrdata_a": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"bram_rddata_a": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"S_AXI": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"memory_map_ref": "S_AXI",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "15", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "16", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"ARADDR": [ { "physical_name": "s_axi_araddr" } ],
|
||||
"ARBURST": [ { "physical_name": "s_axi_arburst" } ],
|
||||
"ARCACHE": [ { "physical_name": "s_axi_arcache" } ],
|
||||
"ARLEN": [ { "physical_name": "s_axi_arlen" } ],
|
||||
"ARLOCK": [ { "physical_name": "s_axi_arlock" } ],
|
||||
"ARPROT": [ { "physical_name": "s_axi_arprot" } ],
|
||||
"ARREADY": [ { "physical_name": "s_axi_arready" } ],
|
||||
"ARSIZE": [ { "physical_name": "s_axi_arsize" } ],
|
||||
"ARVALID": [ { "physical_name": "s_axi_arvalid" } ],
|
||||
"AWADDR": [ { "physical_name": "s_axi_awaddr" } ],
|
||||
"AWBURST": [ { "physical_name": "s_axi_awburst" } ],
|
||||
"AWCACHE": [ { "physical_name": "s_axi_awcache" } ],
|
||||
"AWLEN": [ { "physical_name": "s_axi_awlen" } ],
|
||||
"AWLOCK": [ { "physical_name": "s_axi_awlock" } ],
|
||||
"AWPROT": [ { "physical_name": "s_axi_awprot" } ],
|
||||
"AWREADY": [ { "physical_name": "s_axi_awready" } ],
|
||||
"AWSIZE": [ { "physical_name": "s_axi_awsize" } ],
|
||||
"AWVALID": [ { "physical_name": "s_axi_awvalid" } ],
|
||||
"BREADY": [ { "physical_name": "s_axi_bready" } ],
|
||||
"BRESP": [ { "physical_name": "s_axi_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "s_axi_bvalid" } ],
|
||||
"RDATA": [ { "physical_name": "s_axi_rdata" } ],
|
||||
"RLAST": [ { "physical_name": "s_axi_rlast" } ],
|
||||
"RREADY": [ { "physical_name": "s_axi_rready" } ],
|
||||
"RRESP": [ { "physical_name": "s_axi_rresp" } ],
|
||||
"RVALID": [ { "physical_name": "s_axi_rvalid" } ],
|
||||
"WDATA": [ { "physical_name": "s_axi_wdata" } ],
|
||||
"WLAST": [ { "physical_name": "s_axi_wlast" } ],
|
||||
"WREADY": [ { "physical_name": "s_axi_wready" } ],
|
||||
"WSTRB": [ { "physical_name": "s_axi_wstrb" } ],
|
||||
"WVALID": [ { "physical_name": "s_axi_wvalid" } ]
|
||||
}
|
||||
},
|
||||
"BRAM_PORTA": {
|
||||
"vlnv": "xilinx.com:interface:bram:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:bram_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"MASTER_TYPE": [ { "value": "BRAM_CTRL", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"MEM_SIZE": [ { "value": "32768", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MEM_WIDTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MEM_ECC": [ { "value": "NONE", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_LATENCY": [ { "value": "1", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MEM_ADDRESS_MODE": [ { "value": "", "value_src": "weak", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"ADDR": [ { "physical_name": "bram_addr_a" } ],
|
||||
"CLK": [ { "physical_name": "bram_clk_a" } ],
|
||||
"DIN": [ { "physical_name": "bram_wrdata_a" } ],
|
||||
"DOUT": [ { "physical_name": "bram_rddata_a" } ],
|
||||
"EN": [ { "physical_name": "bram_en_a" } ],
|
||||
"RST": [ { "physical_name": "bram_rst_a" } ],
|
||||
"WE": [ { "physical_name": "bram_we_a" } ]
|
||||
}
|
||||
},
|
||||
"RSTIF": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "s_axi_aresetn" } ]
|
||||
}
|
||||
},
|
||||
"CLKIF": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S_AXI:S_AXI_CTRL", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "s_axi_aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "s_axi_aclk" } ]
|
||||
}
|
||||
}
|
||||
},
|
||||
"memory_maps": {
|
||||
"S_AXI": {
|
||||
"display_name": "S_AXI_MEM",
|
||||
"description": "Memory Map for S_AXI",
|
||||
"address_blocks": {
|
||||
"Mem0": {
|
||||
"base_address": "0",
|
||||
"range": "4096",
|
||||
"display_name": "Mem0",
|
||||
"description": "Register Block",
|
||||
"usage": "memory",
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+259
@@ -0,0 +1,259 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "system_top_axi_bram_ctrl_1_0",
|
||||
"cell_name": "axi_bram_ctrl_1",
|
||||
"component_reference": "xilinx.com:ip:axi_bram_ctrl:4.1",
|
||||
"ip_revision": "10",
|
||||
"gen_directory": "../../../../../../project_fix_dac.gen/sources_1/bd/system_top/ip/system_top_axi_bram_ctrl_1_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PROTOCOL": [ { "value": "AXI4", "resolve_type": "user", "usage": "all" } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SINGLE_PORT_BRAM": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ECC_TYPE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"USE_ECC": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FAULT_INJECT": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"ECC_ONOFF_RESET_VALUE": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "system_top_axi_bram_ctrl_1_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"BMG_INSTANCE": [ { "value": "EXTERNAL", "value_permission": "bd", "resolve_type": "user", "usage": "all" } ],
|
||||
"MEM_DEPTH": [ { "value": "8192", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"READ_LATENCY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"RD_CMD_OPTIMIZATION": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_BRAM_INST_MODE": [ { "value": "EXTERNAL", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MEMORY_DEPTH": [ { "value": "8192", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_BRAM_ADDR_WIDTH": [ { "value": "13", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_ADDR_WIDTH": [ { "value": "15", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_ID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_PROTOCOL": [ { "value": "AXI4", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_S_AXI_SUPPORTS_NARROW_BURST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SINGLE_PORT_BRAM": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_FAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_READ_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_RD_CMD_OPTIMIZATION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_CTRL_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_CTRL_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ECC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ECC_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_FAULT_INJECT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ECC_ONOFF_RESET_VALUE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "xilinx.com:zc706:part0:1.4" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z045" } ],
|
||||
"NEXTGEN_VERSAL": [ { "value": "0" } ],
|
||||
"PACKAGE": [ { "value": "ffg900" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "10" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../project_fix_dac.gen/sources_1/bd/system_top/ip/system_top_axi_bram_ctrl_1_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2024.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"s_axi_aclk": [ { "direction": "in" } ],
|
||||
"s_axi_aresetn": [ { "direction": "in" } ],
|
||||
"s_axi_awaddr": [ { "direction": "in", "size_left": "14", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_awlen": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_awsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_awburst": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_awlock": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_awcache": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_awprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_awvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_awready": [ { "direction": "out" } ],
|
||||
"s_axi_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_wlast": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_wvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_wready": [ { "direction": "out" } ],
|
||||
"s_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s_axi_bvalid": [ { "direction": "out" } ],
|
||||
"s_axi_bready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_araddr": [ { "direction": "in", "size_left": "14", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_arlen": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_arsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_arburst": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_arlock": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_arcache": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_arprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_arvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_arready": [ { "direction": "out" } ],
|
||||
"s_axi_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"s_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s_axi_rlast": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"s_axi_rvalid": [ { "direction": "out" } ],
|
||||
"s_axi_rready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"bram_rst_a": [ { "direction": "out" } ],
|
||||
"bram_clk_a": [ { "direction": "out" } ],
|
||||
"bram_en_a": [ { "direction": "out" } ],
|
||||
"bram_we_a": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||
"bram_addr_a": [ { "direction": "out", "size_left": "14", "size_right": "0" } ],
|
||||
"bram_wrdata_a": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"bram_rddata_a": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"S_AXI": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"memory_map_ref": "S_AXI",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "15", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "16", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"ARADDR": [ { "physical_name": "s_axi_araddr" } ],
|
||||
"ARBURST": [ { "physical_name": "s_axi_arburst" } ],
|
||||
"ARCACHE": [ { "physical_name": "s_axi_arcache" } ],
|
||||
"ARLEN": [ { "physical_name": "s_axi_arlen" } ],
|
||||
"ARLOCK": [ { "physical_name": "s_axi_arlock" } ],
|
||||
"ARPROT": [ { "physical_name": "s_axi_arprot" } ],
|
||||
"ARREADY": [ { "physical_name": "s_axi_arready" } ],
|
||||
"ARSIZE": [ { "physical_name": "s_axi_arsize" } ],
|
||||
"ARVALID": [ { "physical_name": "s_axi_arvalid" } ],
|
||||
"AWADDR": [ { "physical_name": "s_axi_awaddr" } ],
|
||||
"AWBURST": [ { "physical_name": "s_axi_awburst" } ],
|
||||
"AWCACHE": [ { "physical_name": "s_axi_awcache" } ],
|
||||
"AWLEN": [ { "physical_name": "s_axi_awlen" } ],
|
||||
"AWLOCK": [ { "physical_name": "s_axi_awlock" } ],
|
||||
"AWPROT": [ { "physical_name": "s_axi_awprot" } ],
|
||||
"AWREADY": [ { "physical_name": "s_axi_awready" } ],
|
||||
"AWSIZE": [ { "physical_name": "s_axi_awsize" } ],
|
||||
"AWVALID": [ { "physical_name": "s_axi_awvalid" } ],
|
||||
"BREADY": [ { "physical_name": "s_axi_bready" } ],
|
||||
"BRESP": [ { "physical_name": "s_axi_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "s_axi_bvalid" } ],
|
||||
"RDATA": [ { "physical_name": "s_axi_rdata" } ],
|
||||
"RLAST": [ { "physical_name": "s_axi_rlast" } ],
|
||||
"RREADY": [ { "physical_name": "s_axi_rready" } ],
|
||||
"RRESP": [ { "physical_name": "s_axi_rresp" } ],
|
||||
"RVALID": [ { "physical_name": "s_axi_rvalid" } ],
|
||||
"WDATA": [ { "physical_name": "s_axi_wdata" } ],
|
||||
"WLAST": [ { "physical_name": "s_axi_wlast" } ],
|
||||
"WREADY": [ { "physical_name": "s_axi_wready" } ],
|
||||
"WSTRB": [ { "physical_name": "s_axi_wstrb" } ],
|
||||
"WVALID": [ { "physical_name": "s_axi_wvalid" } ]
|
||||
}
|
||||
},
|
||||
"BRAM_PORTA": {
|
||||
"vlnv": "xilinx.com:interface:bram:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:bram_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"MASTER_TYPE": [ { "value": "BRAM_CTRL", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"MEM_SIZE": [ { "value": "32768", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MEM_WIDTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MEM_ECC": [ { "value": "NONE", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_LATENCY": [ { "value": "1", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MEM_ADDRESS_MODE": [ { "value": "", "value_src": "weak", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"ADDR": [ { "physical_name": "bram_addr_a" } ],
|
||||
"CLK": [ { "physical_name": "bram_clk_a" } ],
|
||||
"DIN": [ { "physical_name": "bram_wrdata_a" } ],
|
||||
"DOUT": [ { "physical_name": "bram_rddata_a" } ],
|
||||
"EN": [ { "physical_name": "bram_en_a" } ],
|
||||
"RST": [ { "physical_name": "bram_rst_a" } ],
|
||||
"WE": [ { "physical_name": "bram_we_a" } ]
|
||||
}
|
||||
},
|
||||
"RSTIF": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "s_axi_aresetn" } ]
|
||||
}
|
||||
},
|
||||
"CLKIF": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S_AXI:S_AXI_CTRL", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "s_axi_aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "s_axi_aclk" } ]
|
||||
}
|
||||
}
|
||||
},
|
||||
"memory_maps": {
|
||||
"S_AXI": {
|
||||
"display_name": "S_AXI_MEM",
|
||||
"description": "Memory Map for S_AXI",
|
||||
"address_blocks": {
|
||||
"Mem0": {
|
||||
"base_address": "0",
|
||||
"range": "4096",
|
||||
"display_name": "Mem0",
|
||||
"description": "Register Block",
|
||||
"usage": "memory",
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+976
@@ -0,0 +1,976 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "system_top_axi_dma_0_0",
|
||||
"cell_name": "axi_dma_0",
|
||||
"component_reference": "xilinx.com:ip:axi_dma:7.1",
|
||||
"ip_revision": "32",
|
||||
"gen_directory": "../../../../../../project_fix_dac.gen/sources_1/bd/system_top/ip/system_top_axi_dma_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "system_top_axi_dma_0_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"c_include_sg": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_enable_multi_channel": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"c_num_mm2s_channels": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"c_num_s2mm_channels": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"c_sg_length_width": [ { "value": "26", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_dlytmr_resolution": [ { "value": "125", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_prmry_is_aclk_async": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_sg_include_stscntrl_strm": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
},
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
},
|
||||
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|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
},
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
}
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"s2mm_prmry_reset_out_n": [ { "direction": "out" } ],
|
||||
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|
||||
"s_axis_s2mm_tkeep": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0xFF" } ],
|
||||
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|
||||
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|
||||
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|
||||
"s2mm_introut": [ { "direction": "out" } ],
|
||||
"axi_dma_tstvec": [ { "direction": "out", "size_left": "31", "size_right": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"S_AXI_LITE": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "slave",
|
||||
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|
||||
"parameters": {
|
||||
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|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "10", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
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|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
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|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"ARADDR": [ { "physical_name": "s_axi_lite_araddr" } ],
|
||||
"ARREADY": [ { "physical_name": "s_axi_lite_arready" } ],
|
||||
"ARVALID": [ { "physical_name": "s_axi_lite_arvalid" } ],
|
||||
"AWADDR": [ { "physical_name": "s_axi_lite_awaddr" } ],
|
||||
"AWREADY": [ { "physical_name": "s_axi_lite_awready" } ],
|
||||
"AWVALID": [ { "physical_name": "s_axi_lite_awvalid" } ],
|
||||
"BREADY": [ { "physical_name": "s_axi_lite_bready" } ],
|
||||
"BRESP": [ { "physical_name": "s_axi_lite_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "s_axi_lite_bvalid" } ],
|
||||
"RDATA": [ { "physical_name": "s_axi_lite_rdata" } ],
|
||||
"RREADY": [ { "physical_name": "s_axi_lite_rready" } ],
|
||||
"RRESP": [ { "physical_name": "s_axi_lite_rresp" } ],
|
||||
"RVALID": [ { "physical_name": "s_axi_lite_rvalid" } ],
|
||||
"WDATA": [ { "physical_name": "s_axi_lite_wdata" } ],
|
||||
"WREADY": [ { "physical_name": "s_axi_lite_wready" } ],
|
||||
"WVALID": [ { "physical_name": "s_axi_lite_wvalid" } ]
|
||||
}
|
||||
},
|
||||
"M_AXI_S2MM": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "master",
|
||||
"address_space_ref": "Data_S2MM",
|
||||
"parameters": {
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
|
||||
"DATA_WIDTH": [ { "value": "64", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "200000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "40", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "WRITE_ONLY", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "16", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_mig_7series_0_0_ui_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"AWADDR": [ { "physical_name": "m_axi_s2mm_awaddr" } ],
|
||||
"AWBURST": [ { "physical_name": "m_axi_s2mm_awburst" } ],
|
||||
"AWCACHE": [ { "physical_name": "m_axi_s2mm_awcache" } ],
|
||||
"AWLEN": [ { "physical_name": "m_axi_s2mm_awlen" } ],
|
||||
"AWPROT": [ { "physical_name": "m_axi_s2mm_awprot" } ],
|
||||
"AWREADY": [ { "physical_name": "m_axi_s2mm_awready" } ],
|
||||
"AWSIZE": [ { "physical_name": "m_axi_s2mm_awsize" } ],
|
||||
"AWVALID": [ { "physical_name": "m_axi_s2mm_awvalid" } ],
|
||||
"BREADY": [ { "physical_name": "m_axi_s2mm_bready" } ],
|
||||
"BRESP": [ { "physical_name": "m_axi_s2mm_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "m_axi_s2mm_bvalid" } ],
|
||||
"WDATA": [ { "physical_name": "m_axi_s2mm_wdata" } ],
|
||||
"WLAST": [ { "physical_name": "m_axi_s2mm_wlast" } ],
|
||||
"WREADY": [ { "physical_name": "m_axi_s2mm_wready" } ],
|
||||
"WSTRB": [ { "physical_name": "m_axi_s2mm_wstrb" } ],
|
||||
"WVALID": [ { "physical_name": "m_axi_s2mm_wvalid" } ]
|
||||
}
|
||||
},
|
||||
"S_AXIS_S2MM": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "8", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "200000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_mig_7series_0_0_ui_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "s_axis_s2mm_tdata" } ],
|
||||
"TKEEP": [ { "physical_name": "s_axis_s2mm_tkeep" } ],
|
||||
"TLAST": [ { "physical_name": "s_axis_s2mm_tlast" } ],
|
||||
"TREADY": [ { "physical_name": "s_axis_s2mm_tready" } ],
|
||||
"TVALID": [ { "physical_name": "s_axis_s2mm_tvalid" } ]
|
||||
}
|
||||
},
|
||||
"AXI_RESETN": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "axi_resetn" } ]
|
||||
}
|
||||
},
|
||||
"MM2S_INTROUT": {
|
||||
"vlnv": "xilinx.com:signal:interrupt:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"SENSITIVITY": [ { "value": "LEVEL_HIGH", "value_src": "constant", "usage": "all" } ],
|
||||
"PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"S2MM_INTROUT": {
|
||||
"vlnv": "xilinx.com:signal:interrupt:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"SENSITIVITY": [ { "value": "LEVEL_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"PortWidth": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"INTERRUPT": [ { "physical_name": "s2mm_introut" } ]
|
||||
}
|
||||
},
|
||||
"M_AXI_SG_CLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "M_AXI_SG", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"M_AXI_MM2S_CLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "M_AXI_MM2S:M_AXIS_MM2S:M_AXIS_CNTRL", "value_src": "constant", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "mm2s_prmry_reset_out_n:mm2s_cntrl_reset_out_n", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"M_AXI_S2MM_CLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "M_AXI_S2MM:S_AXIS_S2MM:S_AXIS_STS", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "s2mm_prmry_reset_out_n:s2mm_sts_reset_out_n", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "200000000", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_mig_7series_0_0_ui_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "m_axi_s2mm_aclk" } ]
|
||||
}
|
||||
},
|
||||
"S_AXI_LITE_ACLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S_AXI_LITE:M_AXI", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "axi_resetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "s_axi_lite_aclk" } ]
|
||||
}
|
||||
},
|
||||
"MM2S_PRMRY_RESET_OUT_N": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"S2MM_PRMRY_RESET_OUT_N": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "s2mm_prmry_reset_out_n" } ]
|
||||
}
|
||||
},
|
||||
"MM2S_CNTRL_RESET_OUT_N": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"S2MM_STS_RESET_OUT_N": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
}
|
||||
},
|
||||
"address_spaces": {
|
||||
"Data_S2MM": {
|
||||
"range": "1099511627776",
|
||||
"width": "40"
|
||||
}
|
||||
},
|
||||
"memory_maps": {
|
||||
"S_AXI_LITE": {
|
||||
"display_name": "S_AXI_MEM",
|
||||
"description": "Memory Map for S_AXI_LITE",
|
||||
"address_blocks": {
|
||||
"Reg": {
|
||||
"base_address": "0",
|
||||
"range": "4096",
|
||||
"display_name": "Reg",
|
||||
"description": "Register Block",
|
||||
"usage": "register",
|
||||
"access": "read-write",
|
||||
"registers": {
|
||||
"MM2S_DMACR": {
|
||||
"address_offset": "0x0",
|
||||
"size": 32,
|
||||
"display_name": "MM2S DMA Control Register",
|
||||
"description": "MM2S DMA Control Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x10002",
|
||||
"fields": {
|
||||
"RS": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 1,
|
||||
"display_name": "Run/Stop Control",
|
||||
"description": "Run / Stop control for controlling running and stopping of the DMA channel.\n 0 - Stop, DMA stops when current (if any) DMA operations are complete. For Scatter / Gather Mode pending commands/transfers are flushed or completed. \n AXI4-Stream outs are potentially terminated early. Descriptors in the update queue are allowed to finish updating to remote memory before engine halt.\n For Direct Register mode pending commands/transfers are flushed or completed. AXI4-Stream outs are potentially terminated.\n The halted bit in the DMA Status register asserts to 1 when the DMA engine is halted. This bit is cleared by AXI DMA hardware when an error occurs. The CPU can also choose to clear this bit to stop DMA operations.\n 1 - Run, Start DMA operations. The halted bit in the DMA Status register deasserts to 0 when the DMA engine begins operations.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Reset": {
|
||||
"bit_offset": 2,
|
||||
"bit_width": 1,
|
||||
"display_name": "Soft Reset",
|
||||
"description": "Soft reset for resetting the AXI DMA core. Setting this bit to a 1 causes the AXI DMA to be reset. Reset is accomplished gracefully. Pending commands/transfers are flushed or completed.\nAXI4-Stream outs are potentially terminated early. Setting either MM2S_DMACR. Reset = 1 or S2MM_DMACR.Reset = 1 resets the entire AXI DMA engine. After completion of a soft reset, all registers and bits are in the Reset State. 0 - Normal operation. 1 - Reset in progress.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Keyhole": {
|
||||
"bit_offset": 3,
|
||||
"bit_width": 1,
|
||||
"display_name": "Keyhole Read",
|
||||
"description": "Keyhole Read. Setting this bit to 1 causes AXI DMA to initiate MM2S reads (AXI4read) in non-incrementing address mode (Fixed Address Burst transfer on AXI4). This bit can be updated when AXI DMA is in idle. When using keyhole operation the Max Burst Length should not exceed 16. This bit should not be set when DRE is enabled.\nThis bit is non functional when the multichannel feature is enabled or in Direct Register mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Cyclic_BD_Enable": {
|
||||
"bit_offset": 4,
|
||||
"bit_width": 1,
|
||||
"display_name": "Cyclic BD Enable",
|
||||
"description": "When set to 1, the DMA operates in Cyclic Buffer Descriptor (BD) mode without any user intervention. In this mode, the Scatter Gather module ignores the Completed bit of the BD. With this bit set, you can use the same BDs in cyclic manner without worrying about any stale descriptor errors.\nThis bit should be set/unset only when the DMA is idle or when not running. Updating this bit while the DMA is running can result in unexpected behavior.\nThis bit is non functional when DMA operates in multichannel mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"IOC_IrqEn": {
|
||||
"bit_offset": 12,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Complete (IOC) Interrupt Enable",
|
||||
"description": "Interrupt on Complete (IOC) Interrupt Enable. When set to 1, allows DMASR.IOC_Irq to generate an interrupt out for descriptors with the IOC bit set. 0 - IOC Interrupt disabled 1 - IOC Interrupt enabled\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Dly_IrqEn": {
|
||||
"bit_offset": 13,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Delay Timer Interrupt Enable",
|
||||
"description": "Interrupt on Delay Timer Interrupt Enable. When set to 1, allows DMASR.Dly_Irq to generate an interrupt out. 0 - Delay Interrupt disabled 1 - Delay Interrupt enabled Note: This field is ignored when AXI DMA is configured for Direct Register Mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Err_IrqEn": {
|
||||
"bit_offset": 14,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Error Interrupt Enable",
|
||||
"description": "Interrupt on Error Interrupt Enable.\n 0 - Error Interrupt disabled\n 1 - Error Interrupt enabled\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"IRQThreshold": {
|
||||
"bit_offset": 16,
|
||||
"bit_width": 8,
|
||||
"display_name": "Interrupt Threshold",
|
||||
"description": "Interrupt Threshold. This value is used for setting the interrupt threshold. When IOC interrupt events occur, an internal counter counts down from the Interrupt Threshold setting. When the count reaches zero, an interrupt out is generated by the DMA engine. Note: The minimum setting for the threshold is 0x01. A write of 0x00 to this register has no effect. Note: This field is ignored when AXI DMA is configured for Direct Register Mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"IRQDelay": {
|
||||
"bit_offset": 24,
|
||||
"bit_width": 8,
|
||||
"display_name": "Interrupt Delay Time Out",
|
||||
"description": "Interrupt Delay Time Out. This value is used for setting the interrupt timeout value. The interrupt timeout mechanism causes the DMA engine to generate an interrupt after the delay time period has expired. Timer begins counting at the end of a packet and resets with receipt of a new packet or a timeout event occurs.\nNote: Setting this value to zero disables the delay timer interrupt.\nNote: This field is ignored when AXI DMA is configured for Direct Register Mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"MM2S_DMASR": {
|
||||
"address_offset": "0x04",
|
||||
"size": 32,
|
||||
"display_name": "MM2S DMA Status Register",
|
||||
"description": "MM2S DMA Status Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x10000",
|
||||
"fields": {
|
||||
"Halted": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Channel Halted",
|
||||
"description": "DMA Channel Halted. Indicates the run/stop state of the DMA channel. 0 - DMA channel running. 1 - DMA channel halted. For Scatter / Gather Mode this bit gets set when DMACR.RS = 0 and DMA and SG operations have halted. For Direct Register mode (C_INCLUDE_SG = 0) this bit gets set when DMACR.RS = 0 and DMA operations have halted. There can be a lag of time between when DMACR.RS = 0 and when DMASR.Halted = 1 Note: When halted (RS= 0 and Halted = 1), writing to CURDESC_PTR or TAILDESC_PTR pointer registers has no effect on DMA operations when in Scatter Gather Mode. For Direct Register Mode, writing to the LENGTH register has no effect on DMA operations.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"Idle": {
|
||||
"bit_offset": 1,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Channel Idle",
|
||||
"description": "DMA Channel Idle. Indicates the state of AXI DMA operations.\nFor Scatter / Gather Mode when IDLE indicates the SG Engine has reached the tail pointer for the associated channel and all queued descriptors have been processed. Writing to the tail pointer register automatically restarts DMA operations.\nFor Direct Register Mode when IDLE indicates the current transfer has completed. 0 - Not Idle. For Scatter / Gather Mode, SG has not reached tail descriptor pointer and/or DMA operations in progress. For Direct Register Mode, transfer is not complete. 1 - Idle. For Scatter / Gather Mode, SG has reached tail descriptor pointer and DMA operation paused. for Direct Register Mode, DMA transfer has completed and controller is paused. Note: This bit is 0 when channel is halted (DMASR.Halted=1). This bit is also 0 prior to initial transfer when AXI DMA configured for Direct Register Mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"SGIncld": {
|
||||
"bit_offset": 3,
|
||||
"bit_width": 1,
|
||||
"display_name": "SGIncld",
|
||||
"description": "1 - Scatter Gather Enabled\n0 - Scatter Gather not enabled\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"DMAIntErr": {
|
||||
"bit_offset": 4,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Internal Error",
|
||||
"description": "DMA Internal Error. Internal error occurs if the buffer length specified in the fetched descriptor is set to 0. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Internal Errors 1 - DMA Internal Error detected. DMA Engine halts\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"DMASlvErr": {
|
||||
"bit_offset": 5,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Slave Error",
|
||||
"description": "DMA Slave Error. This error occurs if the slave read from the Memory Map interface issues a Slave Error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Slave Errors. 1 - DMA Slave Error detected. DMA Engine halts\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"DMADecErr": {
|
||||
"bit_offset": 6,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Decode Error",
|
||||
"description": "DMA Decode Error. This error occurs if the address request points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Decode Errors. 1 - DMA Decode Error detected. DMA Engine halts.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"SGIntErr": {
|
||||
"bit_offset": 8,
|
||||
"bit_width": 1,
|
||||
"display_name": "Scatter Gather Internal Error",
|
||||
"description": "Scatter Gather Internal Error. This error occurs if a descriptor with the \"Complete bit\" already set is fetched. Refer to the Scatter Gather Descriptor section for more information.This indicates to the SG Engine that the descriptor is a stale descriptor. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Internal Errors. 1 - SG Internal Error detected. DMA Engine halts. Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"SGSlvErr": {
|
||||
"bit_offset": 9,
|
||||
"bit_width": 1,
|
||||
"display_name": "Scatter Gather Slave Error",
|
||||
"description": "Scatter Gather Slave Error. This error occurs if the slave read from on the Memory Map interface issues a Slave error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Slave Errors. 1 - SG Slave Error detected. DMA Engine halts. Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode. \n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"SGDecErr": {
|
||||
"bit_offset": 10,
|
||||
"bit_width": 1,
|
||||
"display_name": "Scatter Gather Decode Error",
|
||||
"description": "Scatter Gather Decode Error. This error occurs if CURDESC_PTR and/or NXTDESC_PTR points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Decode Errors. 1 - SG Decode Error detected. DMA Engine halts. Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode. \n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"IOC_Irq": {
|
||||
"bit_offset": 12,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Complete",
|
||||
"description": "Interrupt on Complete. When set to 1 for Scatter/Gather Mode, indicates an interrupt event was generated on completion of a descriptor. This occurs for descriptors with the End of Frame (EOF) bit set. When set to 1 for Direct Register Mode, indicates an interrupt event was generated on completion of a transfer. If the corresponding bit is enabled in the MM2S_DMACR (IOC_IrqEn = 1) and if the interrupt threshold has been met, causes an interrupt out to be generated from the AXI DMA. 0 - No IOC Interrupt. 1 - IOC Interrupt detected. Writing a 1 to this bit will clear it.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Dly_Irq": {
|
||||
"bit_offset": 13,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Delay",
|
||||
"description": "Interrupt on Delay. When set to 1, indicates an interrupt event was generated on delay timer time out. If the corresponding bit is enabled in the MM2S_DMACR (Dly_IrqEn = 1), an interrupt out is generated from the AXI DMA. 0 - No Delay Interrupt. 1 - Delay Interrupt detected. Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode. \n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Err_Irq": {
|
||||
"bit_offset": 14,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Error",
|
||||
"description": "Interrupt on Error. When set to 1, indicates an interrupt event was generated on error. If the corresponding bit is enabled in the MM2S_DMACR (Err_IrqEn = 1), an interrupt out is generated from the AXI DMA.\nWriting a 1 to this bit will clear it. \n0 - No error Interrupt. \n1 - Error interrupt detected.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"IRQThresholdSts": {
|
||||
"bit_offset": 16,
|
||||
"bit_width": 8,
|
||||
"display_name": "Interrupt Threshold Status",
|
||||
"description": "Interrupt Threshold Status. Indicates current interrupt threshold value.\nNote: Applicable only when Scatter Gather is enabled.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"IRQDelaySts": {
|
||||
"bit_offset": 24,
|
||||
"bit_width": 8,
|
||||
"display_name": "Interrupt Delay Time Status",
|
||||
"description": "Interrupt Delay Time Status. Indicates current interrupt delay time value.\nNote: Applicable only when Scatter Gather is enabled.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
}
|
||||
}
|
||||
},
|
||||
"MM2S_SA": {
|
||||
"address_offset": "0x18",
|
||||
"size": 32,
|
||||
"display_name": "MM2S Source Address Register",
|
||||
"description": "MM2S Source Address Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"Source_Address": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 32,
|
||||
"display_name": "Source Address",
|
||||
"description": "Indicates the source address AXI DMA reads from to transfer data to AXI4-Stream on the MM2S Channel.\nNote: If Data Realignment Engine is included, the Source Address can be at any byte offset. If Data Realignment Engine is not included, the Source Address must be MM2S Memory Map data width aligned.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"MM2S_SA_MSB": {
|
||||
"address_offset": "0x1C",
|
||||
"size": 32,
|
||||
"display_name": "MM2S Source Address Register",
|
||||
"description": "MM2S Source Address Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"Source_Address": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 32,
|
||||
"display_name": "Source Address",
|
||||
"description": "Indicates the MSB 32 bits of the source address AXI DMA reads from to transfer data to AXI4-Stream on the MM2S Channel.\nNote: If Data Realignment Engine is included, the Source Address can be at any byte offset. If Data Realignment Engine is not included, the Source Address must be MM2S Memory Map data width aligned.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"MM2S_LENGTH": {
|
||||
"address_offset": "0x28",
|
||||
"size": 32,
|
||||
"display_name": "MM2S DMA Transfer Length Register",
|
||||
"description": "MM2S DMA Transfer Length Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"Length": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 26,
|
||||
"display_name": "Length",
|
||||
"description": "Indicates the number of bytes to transfer for the MM2S channel. Writing a non-zero value to this register starts the MM2S transfer.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"S2MM_DMACR": {
|
||||
"address_offset": "0x30",
|
||||
"size": 32,
|
||||
"display_name": "S2MM DMA Control Register",
|
||||
"description": "S2MM DMA Control Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x10002",
|
||||
"fields": {
|
||||
"RS": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 1,
|
||||
"display_name": "Run/Stop Control",
|
||||
"description": "Run / Stop control for controlling running and stopping of the DMA channel.\n 0 - Stop, DMA stops when current (if any) DMA operations are complete. For Scatter / Gather Mode pending commands/transfers are flushed or completed. \n AXI4-Stream outs are potentially terminated early. Descriptors in the update queue are allowed to finish updating to remote memory before engine halt.\n For Direct Register mode pending commands/transfers are flushed or completed. AXI4-Stream outs are potentially terminated. Data integrity on S2MM AXI4 cannot be guaranteed.\n The halted bit in the DMA Status register asserts to 1 when the DMA engine is halted. This bit is cleared by AXI DMA hardware when an error occurs. The CPU can also choose to clear this bit to stop DMA operations.\n 1 - Run, Start DMA operations. The halted bit in the DMA Status register deasserts to 0 when the DMA engine begins operations.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Reset": {
|
||||
"bit_offset": 2,
|
||||
"bit_width": 1,
|
||||
"display_name": "Soft Reset",
|
||||
"description": "Soft reset for resetting the AXI DMA core. Setting this bit to a 1 causes the AXI DMA to be reset. Reset is accomplished gracefully. Pending commands/transfers are flushed or completed.\nAXI4-Stream outs are terminated early, if necessary with associated TLAST. Setting either MM2S_DMACR.Reset = 1 or S2MM_DMACR.Reset = 1 resets the entire AXI DMA engine. After completion of a soft reset, all registers and bits are in the Reset State. 0 - Reset not in progress. Normal operation. 1 - Reset in progress\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Keyhole": {
|
||||
"bit_offset": 3,
|
||||
"bit_width": 1,
|
||||
"display_name": "Keyhole Write",
|
||||
"description": "Keyhole Write. Setting this bit to 1 causes AXI DMA to initiate S2MM writes (AXI4 Writes) in non-incrementing address mode (Fixed Address Burst transfer on AXI4). This bit can be modified when AXI DMA is in idle. When enabling Key hole operation the maximum burst length cannot be more than 16. This bit should not be set when DRE is enabled.\nThis bit is non functional when DMA is used in multichannel mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Cyclic_BD_Enable": {
|
||||
"bit_offset": 4,
|
||||
"bit_width": 1,
|
||||
"display_name": "Cyclic BD Enable",
|
||||
"description": "When set to 1, the DMA operates in Cyclic Buffer Descriptor (BD) mode without any user intervention. In this mode, the Scatter Gather module ignores the Completed bit of the BD. With this bit set, you can use the same BDs in cyclic manner without worrying about any stale descriptor errors.\nThis bit is non functional when DMA operates in Multichannel mode. or in Direct Register Mode\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"IOC_IrqEn": {
|
||||
"bit_offset": 12,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Complete (IOC) Interrupt Enable",
|
||||
"description": "Interrupt on Complete (IOC) Interrupt Enable. When set to 1, allows Interrupt On Complete events to generate an interrupt out for descriptors with the Complete bit set. 0 - IOC Interrupt disabled 1 - IOC Interrupt enabled\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Dly_IrqEn": {
|
||||
"bit_offset": 13,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Delay Timer Interrupt Enable",
|
||||
"description": "Interrupt on Delay Timer Interrupt Enable. When set to 1, allows error events to generate an interrupt out. 0 - Delay Interrupt disabled 1 - Delay Interrupt enabled Note: Applicable only when Scatter Gather is enabled.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Err_IrqEn": {
|
||||
"bit_offset": 14,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Error Interrupt Enable",
|
||||
"description": "Interrupt on Error Interrupt Enable. When set to 1, allows error events to generate an interrupt out. 0 - Error Interrupt disabled 1 - Error Interrupt enabled\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"IRQThreshold": {
|
||||
"bit_offset": 16,
|
||||
"bit_width": 8,
|
||||
"display_name": "Interrupt Threshold",
|
||||
"description": "Interrupt Threshold. This value is used for setting the interrupt threshold. When IOC interrupt events occur, an internal counter counts down from the Interrupt Threshold setting. When the count reaches zero, an interrupt out is generated by the DMA engine.\nNote: The minimum setting for the threshold is 0x01. A write of 0x00 to this register has no effect.\nNote: Applicable only when Scatter Gather is enabled.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"IRQDelay": {
|
||||
"bit_offset": 24,
|
||||
"bit_width": 8,
|
||||
"display_name": "Interrupt Delay Time Out",
|
||||
"description": "Interrupt Delay Time Out. This value is used for setting the interrupt timeout value. The interrupt timeout mechanism causes the DMA engine to generate an interrupt after the delay time period has expired. Timer begins counting at the end of a packet and resets with receipt of a new packet or a timeout event occurs.\nNote: Setting this value to zero disables the delay timer interrupt.\nNote: Applicable only when Scatter Gather is enabled.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"S2MM_DMASR": {
|
||||
"address_offset": "0x34",
|
||||
"size": 32,
|
||||
"display_name": "S2MM DMA Status Register",
|
||||
"description": "S2MM DMA Status Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x10000",
|
||||
"fields": {
|
||||
"Halted": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Channel Halted",
|
||||
"description": "DMA Channel Halted. Indicates the run/stop state of the DMA channel. 0 - DMA channel running. 1 - DMA channel halted. For Scatter/Gather Mode this bit gets set when DMACR.RS = 0 and DMA and SG operations have halted. For Direct Register Mode this bit gets set when DMACR.RS = 0 and DMA operations have halted. There can be a lag of time between when DMACR.RS = 0 and when DMASR.Halted = 1 \nNote: When halted (RS= 0 and Halted = 1), writing to CURDESC_PTR or TAILDESC_PTR pointer registers has no effect on DMA operations when in Scatter Gather Mode. For Direct Register Mode, writing to the LENGTH register has no effect on DMA operations.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"Idle": {
|
||||
"bit_offset": 1,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Channel Idle",
|
||||
"description": "DMA Channel Idle. Indicates the state of AXI DMA operations.\nFor Scatter / Gather Mode when IDLE indicates the SG Engine has reached the tail pointer for the associated channel and all queued descriptors have been processed. Writing to the tail pointer register automatically restarts DMA operations.\nFor Direct Register Mode when IDLE indicates the current transfer has completed. 0 - Not Idle. 1 - Idle. Note: This bit is 0 when channel is halted (DMASR.Halted=1). This bit is also 0 prior to initial transfer when AXI DMA configured for Direct Register Mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"SGIncld": {
|
||||
"bit_offset": 3,
|
||||
"bit_width": 1,
|
||||
"display_name": "SGIncld",
|
||||
"description": "Scatter Gather Engine Included. DMASR.SGIncld = 1 indicates the Scatter Gather engine is included and the AXI DMA is configured for Scatter Gather mode. DMASR.SGIncld = 0 indicates the Scatter Gather engine is excluded and the AXI DMA is configured for Direct Register Mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"DMAIntErr": {
|
||||
"bit_offset": 4,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Internal Error",
|
||||
"description": "DMA Internal Error. This error occurs if the buffer length specified in the fetched descriptor is set to 0. Also, when in Scatter Gather Mode and using the status app length field, this error occurs when the Status AXI4-Stream packet RxLength field does not match the S2MM packet being received by the S_AXIS_S2MM interface. When Scatter Gather is disabled, this error is flagged if any error occurs during Memory write or if the incoming packet is bigger than what is specified in the DMA length register.\nThis error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Internal Errors 1 - DMA Internal Error detected.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"DMASlvErr": {
|
||||
"bit_offset": 5,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Slave Error",
|
||||
"description": "DMA Slave Error. This error occurs if the slave read from the Memory Map interface issues a Slave Error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Slave Errors. 1 - DMA Slave Error detected.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"DMADecErr": {
|
||||
"bit_offset": 6,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Decode Error",
|
||||
"description": "DMA Decode Error. This error occurs if the address request points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Decode Errors. 1 - DMA Decode Error detected.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"SGIntErr": {
|
||||
"bit_offset": 8,
|
||||
"bit_width": 1,
|
||||
"display_name": "Scatter Gather Internal Error",
|
||||
"description": "Scatter Gather Internal Error. This error occurs if a descriptor with the \"Complete bit\" already set is fetched. This indicates to the SG Engine that the descriptor is a tail descriptor. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Internal Errors. 1 - SG Internal Error detected. Note: Applicable only when Scatter Gather is enabled. \n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"SGSlvErr": {
|
||||
"bit_offset": 9,
|
||||
"bit_width": 1,
|
||||
"display_name": "Scatter Gather Slave Error",
|
||||
"description": "Scatter Gather Slave Error. This error occurs if the slave read from on the Memory Map interface issues a Slave error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Slave Errors. 1 - SG Slave Error detected. DMA Engine halts. Note: Applicable only when Scatter Gather is enabled. \n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"SGDecErr": {
|
||||
"bit_offset": 10,
|
||||
"bit_width": 1,
|
||||
"display_name": "Scatter Gather Decode Error",
|
||||
"description": "Scatter Gather Decode Error. This error occurs if CURDESC_PTR and/or NXTDESC_PTR points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Decode Errors. 1 - SG Decode Error detected. DMA Engine halts. Note: Applicable only when Scatter Gather is enabled. \n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"IOC_Irq": {
|
||||
"bit_offset": 12,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Complete",
|
||||
"description": "Interrupt on Complete. When set to 1 for Scatter/Gather Mode, indicates an interrupt event was generated on completion of a descriptor. This occurs for descriptors with the End of Frame (EOF) bit set. When set to 1 for Direct Register Mode, indicates an interrupt event was generated on completion of a transfer. If the corresponding bit in S2MM_DMACR is enabled (IOC_IrqEn = 1) and if the interrupt threshold has been met, causes an interrupt out to be generated from the AXI DMA. 0 - No IOC Interrupt. 1 - IOC Interrupt detected. Writing a 1 to this bit will clear it.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Dly_Irq": {
|
||||
"bit_offset": 13,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Delay",
|
||||
"description": "Interrupt on Delay. When set to 1, indicates an interrupt event was generated on delay timer time out. If the corresponding bit is enabled in the S2MM_DMACR (Dly_IrqEn = 1), an interrupt out is generated from the AXI DMA. 0 - No Delay Interrupt. 1 - Delay Interrupt detected.1 = IOC Interrupt detected. Writing a 1 to this bit will clear it. Note: Applicable only when Scatter Gather is enabled. \n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Err_Irq": {
|
||||
"bit_offset": 14,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Error",
|
||||
"description": "Interrupt on Error. When set to 1, indicates an interrupt event was generated on error. If the corresponding bit is enabled in the S2MM_DMACR (Err_IrqEn = 1), an interrupt out is generated from the AXI DMA.\nWriting a 1 to this bit will clear it. 0 - No error Interrupt. 1 - Error interrupt detected.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"IRQThresholdSts": {
|
||||
"bit_offset": 16,
|
||||
"bit_width": 8,
|
||||
"display_name": "Interrupt Threshold Status",
|
||||
"description": "Interrupt Threshold Status. Indicates current interrupt threshold value.\nNote: Applicable only when Scatter Gather is enabled.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"IRQDelaySts": {
|
||||
"bit_offset": 24,
|
||||
"bit_width": 8,
|
||||
"display_name": "Interrupt Delay Time Status",
|
||||
"description": "Interrupt Delay Time Status. Indicates current interrupt delay time value.\nNote: Applicable only when Scatter Gather is enabled.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
}
|
||||
}
|
||||
},
|
||||
"S2MM_DA": {
|
||||
"address_offset": "0x48",
|
||||
"size": 32,
|
||||
"display_name": "S2MM DMA Destination Address Register",
|
||||
"description": "S2MM DMA Destination Address Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"Destination_Address": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 32,
|
||||
"display_name": "Destination Address",
|
||||
"description": "Indicates the destination address the AXI DMA writes to transfer data from AXI4-Stream on S2MM Channel.\nNote: If Data Realignment Engine is included, the Destination Address can be at any byte offset. If Data Realignment Engine is not included, the Destination Address must be S2MM Memory Map data width aligned.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"S2MM_DA_MSB": {
|
||||
"address_offset": "0x4C",
|
||||
"size": 32,
|
||||
"display_name": "S2MM Destination Address Register",
|
||||
"description": "S2MM Destination Address Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"Destination_Address": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 32,
|
||||
"display_name": "Destination Address",
|
||||
"description": "Indicates the MSB 32 bits of the Destination address AXI DMA writes to transfer data from AXI4-Stream on the S2MM Channel.\nNote: If Data Realignment Engine is included, the Destination Address can be at any byte offset. If Data Realignment Engine is not included, the Dstination Address must be S2MM Memory Map data width aligned.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"S2MM_LENGTH": {
|
||||
"address_offset": "0x58",
|
||||
"size": 32,
|
||||
"display_name": "S2MM DMA Transfer Length Register",
|
||||
"description": "S2MM DMA Transfer Length Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"Length": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 26,
|
||||
"display_name": "Length",
|
||||
"description": "Indicates the length in bytes of the S2MM buffer available to write receive data from the S2MM channel. Writing a non-zero value to this register enables S2MM channel to receive packet data.\nAt the completion of the S2MM transfer, the number of actual bytes written on the S2MM AXI4 interface is updated to the S2MM_LENGTH register.\nNote: This value must be greater than or equal to the largest expected packet to be received on S2MM AXI4-Stream. Values smaller than the received packet result in undefined behavior. \n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+976
@@ -0,0 +1,976 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "system_top_axi_dma_1_0",
|
||||
"cell_name": "axi_dma_1",
|
||||
"component_reference": "xilinx.com:ip:axi_dma:7.1",
|
||||
"ip_revision": "32",
|
||||
"gen_directory": "../../../../../../project_fix_dac.gen/sources_1/bd/system_top/ip/system_top_axi_dma_1_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "system_top_axi_dma_1_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"c_include_sg": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_enable_multi_channel": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"c_num_mm2s_channels": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"c_num_s2mm_channels": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"c_sg_length_width": [ { "value": "26", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_dlytmr_resolution": [ { "value": "125", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_prmry_is_aclk_async": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_sg_include_stscntrl_strm": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"c_micro_dma": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_include_mm2s": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_m_axi_mm2s_data_width": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"c_m_axis_mm2s_tdata_width": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"c_include_mm2s_dre": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"c_include_mm2s_sf": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_mm2s_burst_size": [ { "value": "16", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"c_include_s2mm": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_sg_use_stsapp_length": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"c_m_axi_s2mm_data_width": [ { "value": "64", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_s_axis_s2mm_tdata_width": [ { "value": "64", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_include_s2mm_dre": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_include_s2mm_sf": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_s2mm_burst_size": [ { "value": "16", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_addr_width": [ { "value": "40", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_single_interface": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"c_increase_throughput": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_S_AXI_LITE_ADDR_WIDTH": [ { "value": "10", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_LITE_DATA_WIDTH": [ { "value": "32", "format": "long", "usage": "all" } ],
|
||||
"C_DLYTMR_RESOLUTION": [ { "value": "125", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PRMRY_IS_ACLK_ASYNC": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ENABLE_MULTI_CHANNEL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_MM2S_CHANNELS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_S2MM_CHANNELS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INCLUDE_SG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"axi_dma_tstvec": [ { "direction": "out", "size_left": "31", "size_right": "0" } ]
|
||||
},
|
||||
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|
||||
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|
||||
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|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"ARADDR": [ { "physical_name": "s_axi_lite_araddr" } ],
|
||||
"ARREADY": [ { "physical_name": "s_axi_lite_arready" } ],
|
||||
"ARVALID": [ { "physical_name": "s_axi_lite_arvalid" } ],
|
||||
"AWADDR": [ { "physical_name": "s_axi_lite_awaddr" } ],
|
||||
"AWREADY": [ { "physical_name": "s_axi_lite_awready" } ],
|
||||
"AWVALID": [ { "physical_name": "s_axi_lite_awvalid" } ],
|
||||
"BREADY": [ { "physical_name": "s_axi_lite_bready" } ],
|
||||
"BRESP": [ { "physical_name": "s_axi_lite_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "s_axi_lite_bvalid" } ],
|
||||
"RDATA": [ { "physical_name": "s_axi_lite_rdata" } ],
|
||||
"RREADY": [ { "physical_name": "s_axi_lite_rready" } ],
|
||||
"RRESP": [ { "physical_name": "s_axi_lite_rresp" } ],
|
||||
"RVALID": [ { "physical_name": "s_axi_lite_rvalid" } ],
|
||||
"WDATA": [ { "physical_name": "s_axi_lite_wdata" } ],
|
||||
"WREADY": [ { "physical_name": "s_axi_lite_wready" } ],
|
||||
"WVALID": [ { "physical_name": "s_axi_lite_wvalid" } ]
|
||||
}
|
||||
},
|
||||
"M_AXI_S2MM": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "master",
|
||||
"address_space_ref": "Data_S2MM",
|
||||
"parameters": {
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
|
||||
"DATA_WIDTH": [ { "value": "64", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "200000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "40", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "WRITE_ONLY", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "16", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_mig_7series_0_0_ui_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"AWADDR": [ { "physical_name": "m_axi_s2mm_awaddr" } ],
|
||||
"AWBURST": [ { "physical_name": "m_axi_s2mm_awburst" } ],
|
||||
"AWCACHE": [ { "physical_name": "m_axi_s2mm_awcache" } ],
|
||||
"AWLEN": [ { "physical_name": "m_axi_s2mm_awlen" } ],
|
||||
"AWPROT": [ { "physical_name": "m_axi_s2mm_awprot" } ],
|
||||
"AWREADY": [ { "physical_name": "m_axi_s2mm_awready" } ],
|
||||
"AWSIZE": [ { "physical_name": "m_axi_s2mm_awsize" } ],
|
||||
"AWVALID": [ { "physical_name": "m_axi_s2mm_awvalid" } ],
|
||||
"BREADY": [ { "physical_name": "m_axi_s2mm_bready" } ],
|
||||
"BRESP": [ { "physical_name": "m_axi_s2mm_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "m_axi_s2mm_bvalid" } ],
|
||||
"WDATA": [ { "physical_name": "m_axi_s2mm_wdata" } ],
|
||||
"WLAST": [ { "physical_name": "m_axi_s2mm_wlast" } ],
|
||||
"WREADY": [ { "physical_name": "m_axi_s2mm_wready" } ],
|
||||
"WSTRB": [ { "physical_name": "m_axi_s2mm_wstrb" } ],
|
||||
"WVALID": [ { "physical_name": "m_axi_s2mm_wvalid" } ]
|
||||
}
|
||||
},
|
||||
"S_AXIS_S2MM": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "8", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "200000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_mig_7series_0_0_ui_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "s_axis_s2mm_tdata" } ],
|
||||
"TKEEP": [ { "physical_name": "s_axis_s2mm_tkeep" } ],
|
||||
"TLAST": [ { "physical_name": "s_axis_s2mm_tlast" } ],
|
||||
"TREADY": [ { "physical_name": "s_axis_s2mm_tready" } ],
|
||||
"TVALID": [ { "physical_name": "s_axis_s2mm_tvalid" } ]
|
||||
}
|
||||
},
|
||||
"AXI_RESETN": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "axi_resetn" } ]
|
||||
}
|
||||
},
|
||||
"MM2S_INTROUT": {
|
||||
"vlnv": "xilinx.com:signal:interrupt:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"SENSITIVITY": [ { "value": "LEVEL_HIGH", "value_src": "constant", "usage": "all" } ],
|
||||
"PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"S2MM_INTROUT": {
|
||||
"vlnv": "xilinx.com:signal:interrupt:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"SENSITIVITY": [ { "value": "LEVEL_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"PortWidth": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"INTERRUPT": [ { "physical_name": "s2mm_introut" } ]
|
||||
}
|
||||
},
|
||||
"M_AXI_SG_CLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "M_AXI_SG", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"M_AXI_MM2S_CLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "M_AXI_MM2S:M_AXIS_MM2S:M_AXIS_CNTRL", "value_src": "constant", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "mm2s_prmry_reset_out_n:mm2s_cntrl_reset_out_n", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"M_AXI_S2MM_CLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "M_AXI_S2MM:S_AXIS_S2MM:S_AXIS_STS", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "s2mm_prmry_reset_out_n:s2mm_sts_reset_out_n", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "200000000", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_mig_7series_0_0_ui_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "m_axi_s2mm_aclk" } ]
|
||||
}
|
||||
},
|
||||
"S_AXI_LITE_ACLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S_AXI_LITE:M_AXI", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "axi_resetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "s_axi_lite_aclk" } ]
|
||||
}
|
||||
},
|
||||
"MM2S_PRMRY_RESET_OUT_N": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"S2MM_PRMRY_RESET_OUT_N": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "s2mm_prmry_reset_out_n" } ]
|
||||
}
|
||||
},
|
||||
"MM2S_CNTRL_RESET_OUT_N": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"S2MM_STS_RESET_OUT_N": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
}
|
||||
},
|
||||
"address_spaces": {
|
||||
"Data_S2MM": {
|
||||
"range": "1099511627776",
|
||||
"width": "40"
|
||||
}
|
||||
},
|
||||
"memory_maps": {
|
||||
"S_AXI_LITE": {
|
||||
"display_name": "S_AXI_MEM",
|
||||
"description": "Memory Map for S_AXI_LITE",
|
||||
"address_blocks": {
|
||||
"Reg": {
|
||||
"base_address": "0",
|
||||
"range": "4096",
|
||||
"display_name": "Reg",
|
||||
"description": "Register Block",
|
||||
"usage": "register",
|
||||
"access": "read-write",
|
||||
"registers": {
|
||||
"MM2S_DMACR": {
|
||||
"address_offset": "0x0",
|
||||
"size": 32,
|
||||
"display_name": "MM2S DMA Control Register",
|
||||
"description": "MM2S DMA Control Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x10002",
|
||||
"fields": {
|
||||
"RS": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 1,
|
||||
"display_name": "Run/Stop Control",
|
||||
"description": "Run / Stop control for controlling running and stopping of the DMA channel.\n 0 - Stop, DMA stops when current (if any) DMA operations are complete. For Scatter / Gather Mode pending commands/transfers are flushed or completed. \n AXI4-Stream outs are potentially terminated early. Descriptors in the update queue are allowed to finish updating to remote memory before engine halt.\n For Direct Register mode pending commands/transfers are flushed or completed. AXI4-Stream outs are potentially terminated.\n The halted bit in the DMA Status register asserts to 1 when the DMA engine is halted. This bit is cleared by AXI DMA hardware when an error occurs. The CPU can also choose to clear this bit to stop DMA operations.\n 1 - Run, Start DMA operations. The halted bit in the DMA Status register deasserts to 0 when the DMA engine begins operations.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Reset": {
|
||||
"bit_offset": 2,
|
||||
"bit_width": 1,
|
||||
"display_name": "Soft Reset",
|
||||
"description": "Soft reset for resetting the AXI DMA core. Setting this bit to a 1 causes the AXI DMA to be reset. Reset is accomplished gracefully. Pending commands/transfers are flushed or completed.\nAXI4-Stream outs are potentially terminated early. Setting either MM2S_DMACR. Reset = 1 or S2MM_DMACR.Reset = 1 resets the entire AXI DMA engine. After completion of a soft reset, all registers and bits are in the Reset State. 0 - Normal operation. 1 - Reset in progress.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Keyhole": {
|
||||
"bit_offset": 3,
|
||||
"bit_width": 1,
|
||||
"display_name": "Keyhole Read",
|
||||
"description": "Keyhole Read. Setting this bit to 1 causes AXI DMA to initiate MM2S reads (AXI4read) in non-incrementing address mode (Fixed Address Burst transfer on AXI4). This bit can be updated when AXI DMA is in idle. When using keyhole operation the Max Burst Length should not exceed 16. This bit should not be set when DRE is enabled.\nThis bit is non functional when the multichannel feature is enabled or in Direct Register mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Cyclic_BD_Enable": {
|
||||
"bit_offset": 4,
|
||||
"bit_width": 1,
|
||||
"display_name": "Cyclic BD Enable",
|
||||
"description": "When set to 1, the DMA operates in Cyclic Buffer Descriptor (BD) mode without any user intervention. In this mode, the Scatter Gather module ignores the Completed bit of the BD. With this bit set, you can use the same BDs in cyclic manner without worrying about any stale descriptor errors.\nThis bit should be set/unset only when the DMA is idle or when not running. Updating this bit while the DMA is running can result in unexpected behavior.\nThis bit is non functional when DMA operates in multichannel mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"IOC_IrqEn": {
|
||||
"bit_offset": 12,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Complete (IOC) Interrupt Enable",
|
||||
"description": "Interrupt on Complete (IOC) Interrupt Enable. When set to 1, allows DMASR.IOC_Irq to generate an interrupt out for descriptors with the IOC bit set. 0 - IOC Interrupt disabled 1 - IOC Interrupt enabled\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Dly_IrqEn": {
|
||||
"bit_offset": 13,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Delay Timer Interrupt Enable",
|
||||
"description": "Interrupt on Delay Timer Interrupt Enable. When set to 1, allows DMASR.Dly_Irq to generate an interrupt out. 0 - Delay Interrupt disabled 1 - Delay Interrupt enabled Note: This field is ignored when AXI DMA is configured for Direct Register Mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Err_IrqEn": {
|
||||
"bit_offset": 14,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Error Interrupt Enable",
|
||||
"description": "Interrupt on Error Interrupt Enable.\n 0 - Error Interrupt disabled\n 1 - Error Interrupt enabled\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"IRQThreshold": {
|
||||
"bit_offset": 16,
|
||||
"bit_width": 8,
|
||||
"display_name": "Interrupt Threshold",
|
||||
"description": "Interrupt Threshold. This value is used for setting the interrupt threshold. When IOC interrupt events occur, an internal counter counts down from the Interrupt Threshold setting. When the count reaches zero, an interrupt out is generated by the DMA engine. Note: The minimum setting for the threshold is 0x01. A write of 0x00 to this register has no effect. Note: This field is ignored when AXI DMA is configured for Direct Register Mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"IRQDelay": {
|
||||
"bit_offset": 24,
|
||||
"bit_width": 8,
|
||||
"display_name": "Interrupt Delay Time Out",
|
||||
"description": "Interrupt Delay Time Out. This value is used for setting the interrupt timeout value. The interrupt timeout mechanism causes the DMA engine to generate an interrupt after the delay time period has expired. Timer begins counting at the end of a packet and resets with receipt of a new packet or a timeout event occurs.\nNote: Setting this value to zero disables the delay timer interrupt.\nNote: This field is ignored when AXI DMA is configured for Direct Register Mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"MM2S_DMASR": {
|
||||
"address_offset": "0x04",
|
||||
"size": 32,
|
||||
"display_name": "MM2S DMA Status Register",
|
||||
"description": "MM2S DMA Status Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x10000",
|
||||
"fields": {
|
||||
"Halted": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Channel Halted",
|
||||
"description": "DMA Channel Halted. Indicates the run/stop state of the DMA channel. 0 - DMA channel running. 1 - DMA channel halted. For Scatter / Gather Mode this bit gets set when DMACR.RS = 0 and DMA and SG operations have halted. For Direct Register mode (C_INCLUDE_SG = 0) this bit gets set when DMACR.RS = 0 and DMA operations have halted. There can be a lag of time between when DMACR.RS = 0 and when DMASR.Halted = 1 Note: When halted (RS= 0 and Halted = 1), writing to CURDESC_PTR or TAILDESC_PTR pointer registers has no effect on DMA operations when in Scatter Gather Mode. For Direct Register Mode, writing to the LENGTH register has no effect on DMA operations.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"Idle": {
|
||||
"bit_offset": 1,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Channel Idle",
|
||||
"description": "DMA Channel Idle. Indicates the state of AXI DMA operations.\nFor Scatter / Gather Mode when IDLE indicates the SG Engine has reached the tail pointer for the associated channel and all queued descriptors have been processed. Writing to the tail pointer register automatically restarts DMA operations.\nFor Direct Register Mode when IDLE indicates the current transfer has completed. 0 - Not Idle. For Scatter / Gather Mode, SG has not reached tail descriptor pointer and/or DMA operations in progress. For Direct Register Mode, transfer is not complete. 1 - Idle. For Scatter / Gather Mode, SG has reached tail descriptor pointer and DMA operation paused. for Direct Register Mode, DMA transfer has completed and controller is paused. Note: This bit is 0 when channel is halted (DMASR.Halted=1). This bit is also 0 prior to initial transfer when AXI DMA configured for Direct Register Mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"SGIncld": {
|
||||
"bit_offset": 3,
|
||||
"bit_width": 1,
|
||||
"display_name": "SGIncld",
|
||||
"description": "1 - Scatter Gather Enabled\n0 - Scatter Gather not enabled\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"DMAIntErr": {
|
||||
"bit_offset": 4,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Internal Error",
|
||||
"description": "DMA Internal Error. Internal error occurs if the buffer length specified in the fetched descriptor is set to 0. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Internal Errors 1 - DMA Internal Error detected. DMA Engine halts\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"DMASlvErr": {
|
||||
"bit_offset": 5,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Slave Error",
|
||||
"description": "DMA Slave Error. This error occurs if the slave read from the Memory Map interface issues a Slave Error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Slave Errors. 1 - DMA Slave Error detected. DMA Engine halts\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"DMADecErr": {
|
||||
"bit_offset": 6,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Decode Error",
|
||||
"description": "DMA Decode Error. This error occurs if the address request points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Decode Errors. 1 - DMA Decode Error detected. DMA Engine halts.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"SGIntErr": {
|
||||
"bit_offset": 8,
|
||||
"bit_width": 1,
|
||||
"display_name": "Scatter Gather Internal Error",
|
||||
"description": "Scatter Gather Internal Error. This error occurs if a descriptor with the \"Complete bit\" already set is fetched. Refer to the Scatter Gather Descriptor section for more information.This indicates to the SG Engine that the descriptor is a stale descriptor. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Internal Errors. 1 - SG Internal Error detected. DMA Engine halts. Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"SGSlvErr": {
|
||||
"bit_offset": 9,
|
||||
"bit_width": 1,
|
||||
"display_name": "Scatter Gather Slave Error",
|
||||
"description": "Scatter Gather Slave Error. This error occurs if the slave read from on the Memory Map interface issues a Slave error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Slave Errors. 1 - SG Slave Error detected. DMA Engine halts. Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode. \n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"SGDecErr": {
|
||||
"bit_offset": 10,
|
||||
"bit_width": 1,
|
||||
"display_name": "Scatter Gather Decode Error",
|
||||
"description": "Scatter Gather Decode Error. This error occurs if CURDESC_PTR and/or NXTDESC_PTR points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Decode Errors. 1 - SG Decode Error detected. DMA Engine halts. Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode. \n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"IOC_Irq": {
|
||||
"bit_offset": 12,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Complete",
|
||||
"description": "Interrupt on Complete. When set to 1 for Scatter/Gather Mode, indicates an interrupt event was generated on completion of a descriptor. This occurs for descriptors with the End of Frame (EOF) bit set. When set to 1 for Direct Register Mode, indicates an interrupt event was generated on completion of a transfer. If the corresponding bit is enabled in the MM2S_DMACR (IOC_IrqEn = 1) and if the interrupt threshold has been met, causes an interrupt out to be generated from the AXI DMA. 0 - No IOC Interrupt. 1 - IOC Interrupt detected. Writing a 1 to this bit will clear it.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Dly_Irq": {
|
||||
"bit_offset": 13,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Delay",
|
||||
"description": "Interrupt on Delay. When set to 1, indicates an interrupt event was generated on delay timer time out. If the corresponding bit is enabled in the MM2S_DMACR (Dly_IrqEn = 1), an interrupt out is generated from the AXI DMA. 0 - No Delay Interrupt. 1 - Delay Interrupt detected. Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode. \n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Err_Irq": {
|
||||
"bit_offset": 14,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Error",
|
||||
"description": "Interrupt on Error. When set to 1, indicates an interrupt event was generated on error. If the corresponding bit is enabled in the MM2S_DMACR (Err_IrqEn = 1), an interrupt out is generated from the AXI DMA.\nWriting a 1 to this bit will clear it. \n0 - No error Interrupt. \n1 - Error interrupt detected.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"IRQThresholdSts": {
|
||||
"bit_offset": 16,
|
||||
"bit_width": 8,
|
||||
"display_name": "Interrupt Threshold Status",
|
||||
"description": "Interrupt Threshold Status. Indicates current interrupt threshold value.\nNote: Applicable only when Scatter Gather is enabled.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"IRQDelaySts": {
|
||||
"bit_offset": 24,
|
||||
"bit_width": 8,
|
||||
"display_name": "Interrupt Delay Time Status",
|
||||
"description": "Interrupt Delay Time Status. Indicates current interrupt delay time value.\nNote: Applicable only when Scatter Gather is enabled.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
}
|
||||
}
|
||||
},
|
||||
"MM2S_SA": {
|
||||
"address_offset": "0x18",
|
||||
"size": 32,
|
||||
"display_name": "MM2S Source Address Register",
|
||||
"description": "MM2S Source Address Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"Source_Address": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 32,
|
||||
"display_name": "Source Address",
|
||||
"description": "Indicates the source address AXI DMA reads from to transfer data to AXI4-Stream on the MM2S Channel.\nNote: If Data Realignment Engine is included, the Source Address can be at any byte offset. If Data Realignment Engine is not included, the Source Address must be MM2S Memory Map data width aligned.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"MM2S_SA_MSB": {
|
||||
"address_offset": "0x1C",
|
||||
"size": 32,
|
||||
"display_name": "MM2S Source Address Register",
|
||||
"description": "MM2S Source Address Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"Source_Address": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 32,
|
||||
"display_name": "Source Address",
|
||||
"description": "Indicates the MSB 32 bits of the source address AXI DMA reads from to transfer data to AXI4-Stream on the MM2S Channel.\nNote: If Data Realignment Engine is included, the Source Address can be at any byte offset. If Data Realignment Engine is not included, the Source Address must be MM2S Memory Map data width aligned.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"MM2S_LENGTH": {
|
||||
"address_offset": "0x28",
|
||||
"size": 32,
|
||||
"display_name": "MM2S DMA Transfer Length Register",
|
||||
"description": "MM2S DMA Transfer Length Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"Length": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 26,
|
||||
"display_name": "Length",
|
||||
"description": "Indicates the number of bytes to transfer for the MM2S channel. Writing a non-zero value to this register starts the MM2S transfer.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"S2MM_DMACR": {
|
||||
"address_offset": "0x30",
|
||||
"size": 32,
|
||||
"display_name": "S2MM DMA Control Register",
|
||||
"description": "S2MM DMA Control Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x10002",
|
||||
"fields": {
|
||||
"RS": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 1,
|
||||
"display_name": "Run/Stop Control",
|
||||
"description": "Run / Stop control for controlling running and stopping of the DMA channel.\n 0 - Stop, DMA stops when current (if any) DMA operations are complete. For Scatter / Gather Mode pending commands/transfers are flushed or completed. \n AXI4-Stream outs are potentially terminated early. Descriptors in the update queue are allowed to finish updating to remote memory before engine halt.\n For Direct Register mode pending commands/transfers are flushed or completed. AXI4-Stream outs are potentially terminated. Data integrity on S2MM AXI4 cannot be guaranteed.\n The halted bit in the DMA Status register asserts to 1 when the DMA engine is halted. This bit is cleared by AXI DMA hardware when an error occurs. The CPU can also choose to clear this bit to stop DMA operations.\n 1 - Run, Start DMA operations. The halted bit in the DMA Status register deasserts to 0 when the DMA engine begins operations.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Reset": {
|
||||
"bit_offset": 2,
|
||||
"bit_width": 1,
|
||||
"display_name": "Soft Reset",
|
||||
"description": "Soft reset for resetting the AXI DMA core. Setting this bit to a 1 causes the AXI DMA to be reset. Reset is accomplished gracefully. Pending commands/transfers are flushed or completed.\nAXI4-Stream outs are terminated early, if necessary with associated TLAST. Setting either MM2S_DMACR.Reset = 1 or S2MM_DMACR.Reset = 1 resets the entire AXI DMA engine. After completion of a soft reset, all registers and bits are in the Reset State. 0 - Reset not in progress. Normal operation. 1 - Reset in progress\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Keyhole": {
|
||||
"bit_offset": 3,
|
||||
"bit_width": 1,
|
||||
"display_name": "Keyhole Write",
|
||||
"description": "Keyhole Write. Setting this bit to 1 causes AXI DMA to initiate S2MM writes (AXI4 Writes) in non-incrementing address mode (Fixed Address Burst transfer on AXI4). This bit can be modified when AXI DMA is in idle. When enabling Key hole operation the maximum burst length cannot be more than 16. This bit should not be set when DRE is enabled.\nThis bit is non functional when DMA is used in multichannel mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Cyclic_BD_Enable": {
|
||||
"bit_offset": 4,
|
||||
"bit_width": 1,
|
||||
"display_name": "Cyclic BD Enable",
|
||||
"description": "When set to 1, the DMA operates in Cyclic Buffer Descriptor (BD) mode without any user intervention. In this mode, the Scatter Gather module ignores the Completed bit of the BD. With this bit set, you can use the same BDs in cyclic manner without worrying about any stale descriptor errors.\nThis bit is non functional when DMA operates in Multichannel mode. or in Direct Register Mode\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"IOC_IrqEn": {
|
||||
"bit_offset": 12,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Complete (IOC) Interrupt Enable",
|
||||
"description": "Interrupt on Complete (IOC) Interrupt Enable. When set to 1, allows Interrupt On Complete events to generate an interrupt out for descriptors with the Complete bit set. 0 - IOC Interrupt disabled 1 - IOC Interrupt enabled\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Dly_IrqEn": {
|
||||
"bit_offset": 13,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Delay Timer Interrupt Enable",
|
||||
"description": "Interrupt on Delay Timer Interrupt Enable. When set to 1, allows error events to generate an interrupt out. 0 - Delay Interrupt disabled 1 - Delay Interrupt enabled Note: Applicable only when Scatter Gather is enabled.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Err_IrqEn": {
|
||||
"bit_offset": 14,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Error Interrupt Enable",
|
||||
"description": "Interrupt on Error Interrupt Enable. When set to 1, allows error events to generate an interrupt out. 0 - Error Interrupt disabled 1 - Error Interrupt enabled\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"IRQThreshold": {
|
||||
"bit_offset": 16,
|
||||
"bit_width": 8,
|
||||
"display_name": "Interrupt Threshold",
|
||||
"description": "Interrupt Threshold. This value is used for setting the interrupt threshold. When IOC interrupt events occur, an internal counter counts down from the Interrupt Threshold setting. When the count reaches zero, an interrupt out is generated by the DMA engine.\nNote: The minimum setting for the threshold is 0x01. A write of 0x00 to this register has no effect.\nNote: Applicable only when Scatter Gather is enabled.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"IRQDelay": {
|
||||
"bit_offset": 24,
|
||||
"bit_width": 8,
|
||||
"display_name": "Interrupt Delay Time Out",
|
||||
"description": "Interrupt Delay Time Out. This value is used for setting the interrupt timeout value. The interrupt timeout mechanism causes the DMA engine to generate an interrupt after the delay time period has expired. Timer begins counting at the end of a packet and resets with receipt of a new packet or a timeout event occurs.\nNote: Setting this value to zero disables the delay timer interrupt.\nNote: Applicable only when Scatter Gather is enabled.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"S2MM_DMASR": {
|
||||
"address_offset": "0x34",
|
||||
"size": 32,
|
||||
"display_name": "S2MM DMA Status Register",
|
||||
"description": "S2MM DMA Status Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x10000",
|
||||
"fields": {
|
||||
"Halted": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Channel Halted",
|
||||
"description": "DMA Channel Halted. Indicates the run/stop state of the DMA channel. 0 - DMA channel running. 1 - DMA channel halted. For Scatter/Gather Mode this bit gets set when DMACR.RS = 0 and DMA and SG operations have halted. For Direct Register Mode this bit gets set when DMACR.RS = 0 and DMA operations have halted. There can be a lag of time between when DMACR.RS = 0 and when DMASR.Halted = 1 \nNote: When halted (RS= 0 and Halted = 1), writing to CURDESC_PTR or TAILDESC_PTR pointer registers has no effect on DMA operations when in Scatter Gather Mode. For Direct Register Mode, writing to the LENGTH register has no effect on DMA operations.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"Idle": {
|
||||
"bit_offset": 1,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Channel Idle",
|
||||
"description": "DMA Channel Idle. Indicates the state of AXI DMA operations.\nFor Scatter / Gather Mode when IDLE indicates the SG Engine has reached the tail pointer for the associated channel and all queued descriptors have been processed. Writing to the tail pointer register automatically restarts DMA operations.\nFor Direct Register Mode when IDLE indicates the current transfer has completed. 0 - Not Idle. 1 - Idle. Note: This bit is 0 when channel is halted (DMASR.Halted=1). This bit is also 0 prior to initial transfer when AXI DMA configured for Direct Register Mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"SGIncld": {
|
||||
"bit_offset": 3,
|
||||
"bit_width": 1,
|
||||
"display_name": "SGIncld",
|
||||
"description": "Scatter Gather Engine Included. DMASR.SGIncld = 1 indicates the Scatter Gather engine is included and the AXI DMA is configured for Scatter Gather mode. DMASR.SGIncld = 0 indicates the Scatter Gather engine is excluded and the AXI DMA is configured for Direct Register Mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"DMAIntErr": {
|
||||
"bit_offset": 4,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Internal Error",
|
||||
"description": "DMA Internal Error. This error occurs if the buffer length specified in the fetched descriptor is set to 0. Also, when in Scatter Gather Mode and using the status app length field, this error occurs when the Status AXI4-Stream packet RxLength field does not match the S2MM packet being received by the S_AXIS_S2MM interface. When Scatter Gather is disabled, this error is flagged if any error occurs during Memory write or if the incoming packet is bigger than what is specified in the DMA length register.\nThis error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Internal Errors 1 - DMA Internal Error detected.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"DMASlvErr": {
|
||||
"bit_offset": 5,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Slave Error",
|
||||
"description": "DMA Slave Error. This error occurs if the slave read from the Memory Map interface issues a Slave Error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Slave Errors. 1 - DMA Slave Error detected.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"DMADecErr": {
|
||||
"bit_offset": 6,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Decode Error",
|
||||
"description": "DMA Decode Error. This error occurs if the address request points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Decode Errors. 1 - DMA Decode Error detected.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"SGIntErr": {
|
||||
"bit_offset": 8,
|
||||
"bit_width": 1,
|
||||
"display_name": "Scatter Gather Internal Error",
|
||||
"description": "Scatter Gather Internal Error. This error occurs if a descriptor with the \"Complete bit\" already set is fetched. This indicates to the SG Engine that the descriptor is a tail descriptor. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Internal Errors. 1 - SG Internal Error detected. Note: Applicable only when Scatter Gather is enabled. \n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"SGSlvErr": {
|
||||
"bit_offset": 9,
|
||||
"bit_width": 1,
|
||||
"display_name": "Scatter Gather Slave Error",
|
||||
"description": "Scatter Gather Slave Error. This error occurs if the slave read from on the Memory Map interface issues a Slave error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Slave Errors. 1 - SG Slave Error detected. DMA Engine halts. Note: Applicable only when Scatter Gather is enabled. \n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"SGDecErr": {
|
||||
"bit_offset": 10,
|
||||
"bit_width": 1,
|
||||
"display_name": "Scatter Gather Decode Error",
|
||||
"description": "Scatter Gather Decode Error. This error occurs if CURDESC_PTR and/or NXTDESC_PTR points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Decode Errors. 1 - SG Decode Error detected. DMA Engine halts. Note: Applicable only when Scatter Gather is enabled. \n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"IOC_Irq": {
|
||||
"bit_offset": 12,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Complete",
|
||||
"description": "Interrupt on Complete. When set to 1 for Scatter/Gather Mode, indicates an interrupt event was generated on completion of a descriptor. This occurs for descriptors with the End of Frame (EOF) bit set. When set to 1 for Direct Register Mode, indicates an interrupt event was generated on completion of a transfer. If the corresponding bit in S2MM_DMACR is enabled (IOC_IrqEn = 1) and if the interrupt threshold has been met, causes an interrupt out to be generated from the AXI DMA. 0 - No IOC Interrupt. 1 - IOC Interrupt detected. Writing a 1 to this bit will clear it.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Dly_Irq": {
|
||||
"bit_offset": 13,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Delay",
|
||||
"description": "Interrupt on Delay. When set to 1, indicates an interrupt event was generated on delay timer time out. If the corresponding bit is enabled in the S2MM_DMACR (Dly_IrqEn = 1), an interrupt out is generated from the AXI DMA. 0 - No Delay Interrupt. 1 - Delay Interrupt detected.1 = IOC Interrupt detected. Writing a 1 to this bit will clear it. Note: Applicable only when Scatter Gather is enabled. \n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Err_Irq": {
|
||||
"bit_offset": 14,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Error",
|
||||
"description": "Interrupt on Error. When set to 1, indicates an interrupt event was generated on error. If the corresponding bit is enabled in the S2MM_DMACR (Err_IrqEn = 1), an interrupt out is generated from the AXI DMA.\nWriting a 1 to this bit will clear it. 0 - No error Interrupt. 1 - Error interrupt detected.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"IRQThresholdSts": {
|
||||
"bit_offset": 16,
|
||||
"bit_width": 8,
|
||||
"display_name": "Interrupt Threshold Status",
|
||||
"description": "Interrupt Threshold Status. Indicates current interrupt threshold value.\nNote: Applicable only when Scatter Gather is enabled.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"IRQDelaySts": {
|
||||
"bit_offset": 24,
|
||||
"bit_width": 8,
|
||||
"display_name": "Interrupt Delay Time Status",
|
||||
"description": "Interrupt Delay Time Status. Indicates current interrupt delay time value.\nNote: Applicable only when Scatter Gather is enabled.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
}
|
||||
}
|
||||
},
|
||||
"S2MM_DA": {
|
||||
"address_offset": "0x48",
|
||||
"size": 32,
|
||||
"display_name": "S2MM DMA Destination Address Register",
|
||||
"description": "S2MM DMA Destination Address Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"Destination_Address": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 32,
|
||||
"display_name": "Destination Address",
|
||||
"description": "Indicates the destination address the AXI DMA writes to transfer data from AXI4-Stream on S2MM Channel.\nNote: If Data Realignment Engine is included, the Destination Address can be at any byte offset. If Data Realignment Engine is not included, the Destination Address must be S2MM Memory Map data width aligned.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"S2MM_DA_MSB": {
|
||||
"address_offset": "0x4C",
|
||||
"size": 32,
|
||||
"display_name": "S2MM Destination Address Register",
|
||||
"description": "S2MM Destination Address Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"Destination_Address": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 32,
|
||||
"display_name": "Destination Address",
|
||||
"description": "Indicates the MSB 32 bits of the Destination address AXI DMA writes to transfer data from AXI4-Stream on the S2MM Channel.\nNote: If Data Realignment Engine is included, the Destination Address can be at any byte offset. If Data Realignment Engine is not included, the Dstination Address must be S2MM Memory Map data width aligned.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"S2MM_LENGTH": {
|
||||
"address_offset": "0x58",
|
||||
"size": 32,
|
||||
"display_name": "S2MM DMA Transfer Length Register",
|
||||
"description": "S2MM DMA Transfer Length Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"Length": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 26,
|
||||
"display_name": "Length",
|
||||
"description": "Indicates the length in bytes of the S2MM buffer available to write receive data from the S2MM channel. Writing a non-zero value to this register enables S2MM channel to receive packet data.\nAt the completion of the S2MM transfer, the number of actual bytes written on the S2MM AXI4 interface is updated to the S2MM_LENGTH register.\nNote: This value must be greater than or equal to the largest expected packet to be received on S2MM AXI4-Stream. Values smaller than the received packet result in undefined behavior. \n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+976
@@ -0,0 +1,976 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "system_top_axi_dma_2_0",
|
||||
"cell_name": "axi_dma_2",
|
||||
"component_reference": "xilinx.com:ip:axi_dma:7.1",
|
||||
"ip_revision": "32",
|
||||
"gen_directory": "../../../../../../project_fix_dac.gen/sources_1/bd/system_top/ip/system_top_axi_dma_2_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "system_top_axi_dma_2_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"c_include_sg": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_enable_multi_channel": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"c_num_mm2s_channels": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"c_num_s2mm_channels": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"c_sg_length_width": [ { "value": "26", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_dlytmr_resolution": [ { "value": "125", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_prmry_is_aclk_async": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_sg_include_stscntrl_strm": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"c_micro_dma": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_include_mm2s": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_m_axi_mm2s_data_width": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"c_m_axis_mm2s_tdata_width": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"c_include_mm2s_dre": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"c_include_mm2s_sf": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_mm2s_burst_size": [ { "value": "16", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"c_include_s2mm": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_sg_use_stsapp_length": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"c_m_axi_s2mm_data_width": [ { "value": "64", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_s_axis_s2mm_tdata_width": [ { "value": "64", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_include_s2mm_dre": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_include_s2mm_sf": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_s2mm_burst_size": [ { "value": "16", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_addr_width": [ { "value": "40", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_single_interface": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"c_increase_throughput": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_S_AXI_LITE_ADDR_WIDTH": [ { "value": "10", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_LITE_DATA_WIDTH": [ { "value": "32", "format": "long", "usage": "all" } ],
|
||||
"C_DLYTMR_RESOLUTION": [ { "value": "125", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PRMRY_IS_ACLK_ASYNC": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ENABLE_MULTI_CHANNEL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_MM2S_CHANNELS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_S2MM_CHANNELS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INCLUDE_SG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SG_INCLUDE_STSCNTRL_STRM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SG_USE_STSAPP_LENGTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SG_LENGTH_WIDTH": [ { "value": "26", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_AXI_SG_ADDR_WIDTH": [ { "value": "40", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_AXI_SG_DATA_WIDTH": [ { "value": "32", "format": "long", "usage": "all" } ],
|
||||
"C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_S_AXIS_S2MM_STS_TDATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_MICRO_DMA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INCLUDE_MM2S": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INCLUDE_MM2S_SF": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_MM2S_BURST_SIZE": [ { "value": "16", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_M_AXI_MM2S_ADDR_WIDTH": [ { "value": "40", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_M_AXI_MM2S_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_M_AXIS_MM2S_TDATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_INCLUDE_MM2S_DRE": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_INCLUDE_S2MM": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INCLUDE_S2MM_SF": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S2MM_BURST_SIZE": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_AXI_S2MM_ADDR_WIDTH": [ { "value": "40", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_AXI_S2MM_DATA_WIDTH": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXIS_S2MM_TDATA_WIDTH": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INCLUDE_S2MM_DRE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INCREASE_THROUGHPUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_FAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "xilinx.com:zc706:part0:1.4" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z045" } ],
|
||||
"NEXTGEN_VERSAL": [ { "value": "0" } ],
|
||||
"PACKAGE": [ { "value": "ffg900" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "32" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../project_fix_dac.gen/sources_1/bd/system_top/ip/system_top_axi_dma_2_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2024.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"s_axi_lite_aclk": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"m_axi_s2mm_aclk": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"axi_resetn": [ { "direction": "in", "driver_value": "1" } ],
|
||||
"s_axi_lite_awvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_lite_awready": [ { "direction": "out" } ],
|
||||
"s_axi_lite_awaddr": [ { "direction": "in", "size_left": "9", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_lite_wvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_lite_wready": [ { "direction": "out" } ],
|
||||
"s_axi_lite_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_lite_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s_axi_lite_bvalid": [ { "direction": "out" } ],
|
||||
"s_axi_lite_bready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_lite_arvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_lite_arready": [ { "direction": "out" } ],
|
||||
"s_axi_lite_araddr": [ { "direction": "in", "size_left": "9", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_lite_rvalid": [ { "direction": "out" } ],
|
||||
"s_axi_lite_rready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_lite_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"s_axi_lite_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"m_axi_s2mm_awaddr": [ { "direction": "out", "size_left": "39", "size_right": "0" } ],
|
||||
"m_axi_s2mm_awlen": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
|
||||
"m_axi_s2mm_awsize": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||
"m_axi_s2mm_awburst": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"m_axi_s2mm_awprot": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||
"m_axi_s2mm_awcache": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||
"m_axi_s2mm_awvalid": [ { "direction": "out" } ],
|
||||
"m_axi_s2mm_awready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"m_axi_s2mm_wdata": [ { "direction": "out", "size_left": "63", "size_right": "0" } ],
|
||||
"m_axi_s2mm_wstrb": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
|
||||
"m_axi_s2mm_wlast": [ { "direction": "out" } ],
|
||||
"m_axi_s2mm_wvalid": [ { "direction": "out" } ],
|
||||
"m_axi_s2mm_wready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"m_axi_s2mm_bresp": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"m_axi_s2mm_bvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"m_axi_s2mm_bready": [ { "direction": "out" } ],
|
||||
"s2mm_prmry_reset_out_n": [ { "direction": "out" } ],
|
||||
"s_axis_s2mm_tdata": [ { "direction": "in", "size_left": "63", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axis_s2mm_tkeep": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0xFF" } ],
|
||||
"s_axis_s2mm_tvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axis_s2mm_tready": [ { "direction": "out" } ],
|
||||
"s_axis_s2mm_tlast": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s2mm_introut": [ { "direction": "out" } ],
|
||||
"axi_dma_tstvec": [ { "direction": "out", "size_left": "31", "size_right": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"S_AXI_LITE": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"memory_map_ref": "S_AXI_LITE",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "10", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"ARADDR": [ { "physical_name": "s_axi_lite_araddr" } ],
|
||||
"ARREADY": [ { "physical_name": "s_axi_lite_arready" } ],
|
||||
"ARVALID": [ { "physical_name": "s_axi_lite_arvalid" } ],
|
||||
"AWADDR": [ { "physical_name": "s_axi_lite_awaddr" } ],
|
||||
"AWREADY": [ { "physical_name": "s_axi_lite_awready" } ],
|
||||
"AWVALID": [ { "physical_name": "s_axi_lite_awvalid" } ],
|
||||
"BREADY": [ { "physical_name": "s_axi_lite_bready" } ],
|
||||
"BRESP": [ { "physical_name": "s_axi_lite_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "s_axi_lite_bvalid" } ],
|
||||
"RDATA": [ { "physical_name": "s_axi_lite_rdata" } ],
|
||||
"RREADY": [ { "physical_name": "s_axi_lite_rready" } ],
|
||||
"RRESP": [ { "physical_name": "s_axi_lite_rresp" } ],
|
||||
"RVALID": [ { "physical_name": "s_axi_lite_rvalid" } ],
|
||||
"WDATA": [ { "physical_name": "s_axi_lite_wdata" } ],
|
||||
"WREADY": [ { "physical_name": "s_axi_lite_wready" } ],
|
||||
"WVALID": [ { "physical_name": "s_axi_lite_wvalid" } ]
|
||||
}
|
||||
},
|
||||
"M_AXI_S2MM": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "master",
|
||||
"address_space_ref": "Data_S2MM",
|
||||
"parameters": {
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
|
||||
"DATA_WIDTH": [ { "value": "64", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "200000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "40", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "WRITE_ONLY", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "16", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_mig_7series_0_0_ui_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"AWADDR": [ { "physical_name": "m_axi_s2mm_awaddr" } ],
|
||||
"AWBURST": [ { "physical_name": "m_axi_s2mm_awburst" } ],
|
||||
"AWCACHE": [ { "physical_name": "m_axi_s2mm_awcache" } ],
|
||||
"AWLEN": [ { "physical_name": "m_axi_s2mm_awlen" } ],
|
||||
"AWPROT": [ { "physical_name": "m_axi_s2mm_awprot" } ],
|
||||
"AWREADY": [ { "physical_name": "m_axi_s2mm_awready" } ],
|
||||
"AWSIZE": [ { "physical_name": "m_axi_s2mm_awsize" } ],
|
||||
"AWVALID": [ { "physical_name": "m_axi_s2mm_awvalid" } ],
|
||||
"BREADY": [ { "physical_name": "m_axi_s2mm_bready" } ],
|
||||
"BRESP": [ { "physical_name": "m_axi_s2mm_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "m_axi_s2mm_bvalid" } ],
|
||||
"WDATA": [ { "physical_name": "m_axi_s2mm_wdata" } ],
|
||||
"WLAST": [ { "physical_name": "m_axi_s2mm_wlast" } ],
|
||||
"WREADY": [ { "physical_name": "m_axi_s2mm_wready" } ],
|
||||
"WSTRB": [ { "physical_name": "m_axi_s2mm_wstrb" } ],
|
||||
"WVALID": [ { "physical_name": "m_axi_s2mm_wvalid" } ]
|
||||
}
|
||||
},
|
||||
"S_AXIS_S2MM": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "8", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "200000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_mig_7series_0_0_ui_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "s_axis_s2mm_tdata" } ],
|
||||
"TKEEP": [ { "physical_name": "s_axis_s2mm_tkeep" } ],
|
||||
"TLAST": [ { "physical_name": "s_axis_s2mm_tlast" } ],
|
||||
"TREADY": [ { "physical_name": "s_axis_s2mm_tready" } ],
|
||||
"TVALID": [ { "physical_name": "s_axis_s2mm_tvalid" } ]
|
||||
}
|
||||
},
|
||||
"AXI_RESETN": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "axi_resetn" } ]
|
||||
}
|
||||
},
|
||||
"MM2S_INTROUT": {
|
||||
"vlnv": "xilinx.com:signal:interrupt:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"SENSITIVITY": [ { "value": "LEVEL_HIGH", "value_src": "constant", "usage": "all" } ],
|
||||
"PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"S2MM_INTROUT": {
|
||||
"vlnv": "xilinx.com:signal:interrupt:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"SENSITIVITY": [ { "value": "LEVEL_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"PortWidth": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"INTERRUPT": [ { "physical_name": "s2mm_introut" } ]
|
||||
}
|
||||
},
|
||||
"M_AXI_SG_CLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "M_AXI_SG", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"M_AXI_MM2S_CLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "M_AXI_MM2S:M_AXIS_MM2S:M_AXIS_CNTRL", "value_src": "constant", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "mm2s_prmry_reset_out_n:mm2s_cntrl_reset_out_n", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"M_AXI_S2MM_CLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "M_AXI_S2MM:S_AXIS_S2MM:S_AXIS_STS", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "s2mm_prmry_reset_out_n:s2mm_sts_reset_out_n", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "200000000", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_mig_7series_0_0_ui_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "m_axi_s2mm_aclk" } ]
|
||||
}
|
||||
},
|
||||
"S_AXI_LITE_ACLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S_AXI_LITE:M_AXI", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "axi_resetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "s_axi_lite_aclk" } ]
|
||||
}
|
||||
},
|
||||
"MM2S_PRMRY_RESET_OUT_N": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"S2MM_PRMRY_RESET_OUT_N": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "s2mm_prmry_reset_out_n" } ]
|
||||
}
|
||||
},
|
||||
"MM2S_CNTRL_RESET_OUT_N": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"S2MM_STS_RESET_OUT_N": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
}
|
||||
},
|
||||
"address_spaces": {
|
||||
"Data_S2MM": {
|
||||
"range": "1099511627776",
|
||||
"width": "40"
|
||||
}
|
||||
},
|
||||
"memory_maps": {
|
||||
"S_AXI_LITE": {
|
||||
"display_name": "S_AXI_MEM",
|
||||
"description": "Memory Map for S_AXI_LITE",
|
||||
"address_blocks": {
|
||||
"Reg": {
|
||||
"base_address": "0",
|
||||
"range": "4096",
|
||||
"display_name": "Reg",
|
||||
"description": "Register Block",
|
||||
"usage": "register",
|
||||
"access": "read-write",
|
||||
"registers": {
|
||||
"MM2S_DMACR": {
|
||||
"address_offset": "0x0",
|
||||
"size": 32,
|
||||
"display_name": "MM2S DMA Control Register",
|
||||
"description": "MM2S DMA Control Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x10002",
|
||||
"fields": {
|
||||
"RS": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 1,
|
||||
"display_name": "Run/Stop Control",
|
||||
"description": "Run / Stop control for controlling running and stopping of the DMA channel.\n 0 - Stop, DMA stops when current (if any) DMA operations are complete. For Scatter / Gather Mode pending commands/transfers are flushed or completed. \n AXI4-Stream outs are potentially terminated early. Descriptors in the update queue are allowed to finish updating to remote memory before engine halt.\n For Direct Register mode pending commands/transfers are flushed or completed. AXI4-Stream outs are potentially terminated.\n The halted bit in the DMA Status register asserts to 1 when the DMA engine is halted. This bit is cleared by AXI DMA hardware when an error occurs. The CPU can also choose to clear this bit to stop DMA operations.\n 1 - Run, Start DMA operations. The halted bit in the DMA Status register deasserts to 0 when the DMA engine begins operations.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Reset": {
|
||||
"bit_offset": 2,
|
||||
"bit_width": 1,
|
||||
"display_name": "Soft Reset",
|
||||
"description": "Soft reset for resetting the AXI DMA core. Setting this bit to a 1 causes the AXI DMA to be reset. Reset is accomplished gracefully. Pending commands/transfers are flushed or completed.\nAXI4-Stream outs are potentially terminated early. Setting either MM2S_DMACR. Reset = 1 or S2MM_DMACR.Reset = 1 resets the entire AXI DMA engine. After completion of a soft reset, all registers and bits are in the Reset State. 0 - Normal operation. 1 - Reset in progress.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Keyhole": {
|
||||
"bit_offset": 3,
|
||||
"bit_width": 1,
|
||||
"display_name": "Keyhole Read",
|
||||
"description": "Keyhole Read. Setting this bit to 1 causes AXI DMA to initiate MM2S reads (AXI4read) in non-incrementing address mode (Fixed Address Burst transfer on AXI4). This bit can be updated when AXI DMA is in idle. When using keyhole operation the Max Burst Length should not exceed 16. This bit should not be set when DRE is enabled.\nThis bit is non functional when the multichannel feature is enabled or in Direct Register mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Cyclic_BD_Enable": {
|
||||
"bit_offset": 4,
|
||||
"bit_width": 1,
|
||||
"display_name": "Cyclic BD Enable",
|
||||
"description": "When set to 1, the DMA operates in Cyclic Buffer Descriptor (BD) mode without any user intervention. In this mode, the Scatter Gather module ignores the Completed bit of the BD. With this bit set, you can use the same BDs in cyclic manner without worrying about any stale descriptor errors.\nThis bit should be set/unset only when the DMA is idle or when not running. Updating this bit while the DMA is running can result in unexpected behavior.\nThis bit is non functional when DMA operates in multichannel mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"IOC_IrqEn": {
|
||||
"bit_offset": 12,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Complete (IOC) Interrupt Enable",
|
||||
"description": "Interrupt on Complete (IOC) Interrupt Enable. When set to 1, allows DMASR.IOC_Irq to generate an interrupt out for descriptors with the IOC bit set. 0 - IOC Interrupt disabled 1 - IOC Interrupt enabled\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Dly_IrqEn": {
|
||||
"bit_offset": 13,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Delay Timer Interrupt Enable",
|
||||
"description": "Interrupt on Delay Timer Interrupt Enable. When set to 1, allows DMASR.Dly_Irq to generate an interrupt out. 0 - Delay Interrupt disabled 1 - Delay Interrupt enabled Note: This field is ignored when AXI DMA is configured for Direct Register Mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Err_IrqEn": {
|
||||
"bit_offset": 14,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Error Interrupt Enable",
|
||||
"description": "Interrupt on Error Interrupt Enable.\n 0 - Error Interrupt disabled\n 1 - Error Interrupt enabled\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"IRQThreshold": {
|
||||
"bit_offset": 16,
|
||||
"bit_width": 8,
|
||||
"display_name": "Interrupt Threshold",
|
||||
"description": "Interrupt Threshold. This value is used for setting the interrupt threshold. When IOC interrupt events occur, an internal counter counts down from the Interrupt Threshold setting. When the count reaches zero, an interrupt out is generated by the DMA engine. Note: The minimum setting for the threshold is 0x01. A write of 0x00 to this register has no effect. Note: This field is ignored when AXI DMA is configured for Direct Register Mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"IRQDelay": {
|
||||
"bit_offset": 24,
|
||||
"bit_width": 8,
|
||||
"display_name": "Interrupt Delay Time Out",
|
||||
"description": "Interrupt Delay Time Out. This value is used for setting the interrupt timeout value. The interrupt timeout mechanism causes the DMA engine to generate an interrupt after the delay time period has expired. Timer begins counting at the end of a packet and resets with receipt of a new packet or a timeout event occurs.\nNote: Setting this value to zero disables the delay timer interrupt.\nNote: This field is ignored when AXI DMA is configured for Direct Register Mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"MM2S_DMASR": {
|
||||
"address_offset": "0x04",
|
||||
"size": 32,
|
||||
"display_name": "MM2S DMA Status Register",
|
||||
"description": "MM2S DMA Status Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x10000",
|
||||
"fields": {
|
||||
"Halted": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Channel Halted",
|
||||
"description": "DMA Channel Halted. Indicates the run/stop state of the DMA channel. 0 - DMA channel running. 1 - DMA channel halted. For Scatter / Gather Mode this bit gets set when DMACR.RS = 0 and DMA and SG operations have halted. For Direct Register mode (C_INCLUDE_SG = 0) this bit gets set when DMACR.RS = 0 and DMA operations have halted. There can be a lag of time between when DMACR.RS = 0 and when DMASR.Halted = 1 Note: When halted (RS= 0 and Halted = 1), writing to CURDESC_PTR or TAILDESC_PTR pointer registers has no effect on DMA operations when in Scatter Gather Mode. For Direct Register Mode, writing to the LENGTH register has no effect on DMA operations.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"Idle": {
|
||||
"bit_offset": 1,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Channel Idle",
|
||||
"description": "DMA Channel Idle. Indicates the state of AXI DMA operations.\nFor Scatter / Gather Mode when IDLE indicates the SG Engine has reached the tail pointer for the associated channel and all queued descriptors have been processed. Writing to the tail pointer register automatically restarts DMA operations.\nFor Direct Register Mode when IDLE indicates the current transfer has completed. 0 - Not Idle. For Scatter / Gather Mode, SG has not reached tail descriptor pointer and/or DMA operations in progress. For Direct Register Mode, transfer is not complete. 1 - Idle. For Scatter / Gather Mode, SG has reached tail descriptor pointer and DMA operation paused. for Direct Register Mode, DMA transfer has completed and controller is paused. Note: This bit is 0 when channel is halted (DMASR.Halted=1). This bit is also 0 prior to initial transfer when AXI DMA configured for Direct Register Mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"SGIncld": {
|
||||
"bit_offset": 3,
|
||||
"bit_width": 1,
|
||||
"display_name": "SGIncld",
|
||||
"description": "1 - Scatter Gather Enabled\n0 - Scatter Gather not enabled\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"DMAIntErr": {
|
||||
"bit_offset": 4,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Internal Error",
|
||||
"description": "DMA Internal Error. Internal error occurs if the buffer length specified in the fetched descriptor is set to 0. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Internal Errors 1 - DMA Internal Error detected. DMA Engine halts\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"DMASlvErr": {
|
||||
"bit_offset": 5,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Slave Error",
|
||||
"description": "DMA Slave Error. This error occurs if the slave read from the Memory Map interface issues a Slave Error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Slave Errors. 1 - DMA Slave Error detected. DMA Engine halts\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"DMADecErr": {
|
||||
"bit_offset": 6,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Decode Error",
|
||||
"description": "DMA Decode Error. This error occurs if the address request points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Decode Errors. 1 - DMA Decode Error detected. DMA Engine halts.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"SGIntErr": {
|
||||
"bit_offset": 8,
|
||||
"bit_width": 1,
|
||||
"display_name": "Scatter Gather Internal Error",
|
||||
"description": "Scatter Gather Internal Error. This error occurs if a descriptor with the \"Complete bit\" already set is fetched. Refer to the Scatter Gather Descriptor section for more information.This indicates to the SG Engine that the descriptor is a stale descriptor. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Internal Errors. 1 - SG Internal Error detected. DMA Engine halts. Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"SGSlvErr": {
|
||||
"bit_offset": 9,
|
||||
"bit_width": 1,
|
||||
"display_name": "Scatter Gather Slave Error",
|
||||
"description": "Scatter Gather Slave Error. This error occurs if the slave read from on the Memory Map interface issues a Slave error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Slave Errors. 1 - SG Slave Error detected. DMA Engine halts. Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode. \n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"SGDecErr": {
|
||||
"bit_offset": 10,
|
||||
"bit_width": 1,
|
||||
"display_name": "Scatter Gather Decode Error",
|
||||
"description": "Scatter Gather Decode Error. This error occurs if CURDESC_PTR and/or NXTDESC_PTR points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Decode Errors. 1 - SG Decode Error detected. DMA Engine halts. Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode. \n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"IOC_Irq": {
|
||||
"bit_offset": 12,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Complete",
|
||||
"description": "Interrupt on Complete. When set to 1 for Scatter/Gather Mode, indicates an interrupt event was generated on completion of a descriptor. This occurs for descriptors with the End of Frame (EOF) bit set. When set to 1 for Direct Register Mode, indicates an interrupt event was generated on completion of a transfer. If the corresponding bit is enabled in the MM2S_DMACR (IOC_IrqEn = 1) and if the interrupt threshold has been met, causes an interrupt out to be generated from the AXI DMA. 0 - No IOC Interrupt. 1 - IOC Interrupt detected. Writing a 1 to this bit will clear it.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Dly_Irq": {
|
||||
"bit_offset": 13,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Delay",
|
||||
"description": "Interrupt on Delay. When set to 1, indicates an interrupt event was generated on delay timer time out. If the corresponding bit is enabled in the MM2S_DMACR (Dly_IrqEn = 1), an interrupt out is generated from the AXI DMA. 0 - No Delay Interrupt. 1 - Delay Interrupt detected. Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode. \n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Err_Irq": {
|
||||
"bit_offset": 14,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Error",
|
||||
"description": "Interrupt on Error. When set to 1, indicates an interrupt event was generated on error. If the corresponding bit is enabled in the MM2S_DMACR (Err_IrqEn = 1), an interrupt out is generated from the AXI DMA.\nWriting a 1 to this bit will clear it. \n0 - No error Interrupt. \n1 - Error interrupt detected.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"IRQThresholdSts": {
|
||||
"bit_offset": 16,
|
||||
"bit_width": 8,
|
||||
"display_name": "Interrupt Threshold Status",
|
||||
"description": "Interrupt Threshold Status. Indicates current interrupt threshold value.\nNote: Applicable only when Scatter Gather is enabled.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"IRQDelaySts": {
|
||||
"bit_offset": 24,
|
||||
"bit_width": 8,
|
||||
"display_name": "Interrupt Delay Time Status",
|
||||
"description": "Interrupt Delay Time Status. Indicates current interrupt delay time value.\nNote: Applicable only when Scatter Gather is enabled.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
}
|
||||
}
|
||||
},
|
||||
"MM2S_SA": {
|
||||
"address_offset": "0x18",
|
||||
"size": 32,
|
||||
"display_name": "MM2S Source Address Register",
|
||||
"description": "MM2S Source Address Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"Source_Address": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 32,
|
||||
"display_name": "Source Address",
|
||||
"description": "Indicates the source address AXI DMA reads from to transfer data to AXI4-Stream on the MM2S Channel.\nNote: If Data Realignment Engine is included, the Source Address can be at any byte offset. If Data Realignment Engine is not included, the Source Address must be MM2S Memory Map data width aligned.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"MM2S_SA_MSB": {
|
||||
"address_offset": "0x1C",
|
||||
"size": 32,
|
||||
"display_name": "MM2S Source Address Register",
|
||||
"description": "MM2S Source Address Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"Source_Address": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 32,
|
||||
"display_name": "Source Address",
|
||||
"description": "Indicates the MSB 32 bits of the source address AXI DMA reads from to transfer data to AXI4-Stream on the MM2S Channel.\nNote: If Data Realignment Engine is included, the Source Address can be at any byte offset. If Data Realignment Engine is not included, the Source Address must be MM2S Memory Map data width aligned.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"MM2S_LENGTH": {
|
||||
"address_offset": "0x28",
|
||||
"size": 32,
|
||||
"display_name": "MM2S DMA Transfer Length Register",
|
||||
"description": "MM2S DMA Transfer Length Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"Length": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 26,
|
||||
"display_name": "Length",
|
||||
"description": "Indicates the number of bytes to transfer for the MM2S channel. Writing a non-zero value to this register starts the MM2S transfer.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"S2MM_DMACR": {
|
||||
"address_offset": "0x30",
|
||||
"size": 32,
|
||||
"display_name": "S2MM DMA Control Register",
|
||||
"description": "S2MM DMA Control Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x10002",
|
||||
"fields": {
|
||||
"RS": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 1,
|
||||
"display_name": "Run/Stop Control",
|
||||
"description": "Run / Stop control for controlling running and stopping of the DMA channel.\n 0 - Stop, DMA stops when current (if any) DMA operations are complete. For Scatter / Gather Mode pending commands/transfers are flushed or completed. \n AXI4-Stream outs are potentially terminated early. Descriptors in the update queue are allowed to finish updating to remote memory before engine halt.\n For Direct Register mode pending commands/transfers are flushed or completed. AXI4-Stream outs are potentially terminated. Data integrity on S2MM AXI4 cannot be guaranteed.\n The halted bit in the DMA Status register asserts to 1 when the DMA engine is halted. This bit is cleared by AXI DMA hardware when an error occurs. The CPU can also choose to clear this bit to stop DMA operations.\n 1 - Run, Start DMA operations. The halted bit in the DMA Status register deasserts to 0 when the DMA engine begins operations.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Reset": {
|
||||
"bit_offset": 2,
|
||||
"bit_width": 1,
|
||||
"display_name": "Soft Reset",
|
||||
"description": "Soft reset for resetting the AXI DMA core. Setting this bit to a 1 causes the AXI DMA to be reset. Reset is accomplished gracefully. Pending commands/transfers are flushed or completed.\nAXI4-Stream outs are terminated early, if necessary with associated TLAST. Setting either MM2S_DMACR.Reset = 1 or S2MM_DMACR.Reset = 1 resets the entire AXI DMA engine. After completion of a soft reset, all registers and bits are in the Reset State. 0 - Reset not in progress. Normal operation. 1 - Reset in progress\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Keyhole": {
|
||||
"bit_offset": 3,
|
||||
"bit_width": 1,
|
||||
"display_name": "Keyhole Write",
|
||||
"description": "Keyhole Write. Setting this bit to 1 causes AXI DMA to initiate S2MM writes (AXI4 Writes) in non-incrementing address mode (Fixed Address Burst transfer on AXI4). This bit can be modified when AXI DMA is in idle. When enabling Key hole operation the maximum burst length cannot be more than 16. This bit should not be set when DRE is enabled.\nThis bit is non functional when DMA is used in multichannel mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Cyclic_BD_Enable": {
|
||||
"bit_offset": 4,
|
||||
"bit_width": 1,
|
||||
"display_name": "Cyclic BD Enable",
|
||||
"description": "When set to 1, the DMA operates in Cyclic Buffer Descriptor (BD) mode without any user intervention. In this mode, the Scatter Gather module ignores the Completed bit of the BD. With this bit set, you can use the same BDs in cyclic manner without worrying about any stale descriptor errors.\nThis bit is non functional when DMA operates in Multichannel mode. or in Direct Register Mode\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"IOC_IrqEn": {
|
||||
"bit_offset": 12,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Complete (IOC) Interrupt Enable",
|
||||
"description": "Interrupt on Complete (IOC) Interrupt Enable. When set to 1, allows Interrupt On Complete events to generate an interrupt out for descriptors with the Complete bit set. 0 - IOC Interrupt disabled 1 - IOC Interrupt enabled\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Dly_IrqEn": {
|
||||
"bit_offset": 13,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Delay Timer Interrupt Enable",
|
||||
"description": "Interrupt on Delay Timer Interrupt Enable. When set to 1, allows error events to generate an interrupt out. 0 - Delay Interrupt disabled 1 - Delay Interrupt enabled Note: Applicable only when Scatter Gather is enabled.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Err_IrqEn": {
|
||||
"bit_offset": 14,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Error Interrupt Enable",
|
||||
"description": "Interrupt on Error Interrupt Enable. When set to 1, allows error events to generate an interrupt out. 0 - Error Interrupt disabled 1 - Error Interrupt enabled\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"IRQThreshold": {
|
||||
"bit_offset": 16,
|
||||
"bit_width": 8,
|
||||
"display_name": "Interrupt Threshold",
|
||||
"description": "Interrupt Threshold. This value is used for setting the interrupt threshold. When IOC interrupt events occur, an internal counter counts down from the Interrupt Threshold setting. When the count reaches zero, an interrupt out is generated by the DMA engine.\nNote: The minimum setting for the threshold is 0x01. A write of 0x00 to this register has no effect.\nNote: Applicable only when Scatter Gather is enabled.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"IRQDelay": {
|
||||
"bit_offset": 24,
|
||||
"bit_width": 8,
|
||||
"display_name": "Interrupt Delay Time Out",
|
||||
"description": "Interrupt Delay Time Out. This value is used for setting the interrupt timeout value. The interrupt timeout mechanism causes the DMA engine to generate an interrupt after the delay time period has expired. Timer begins counting at the end of a packet and resets with receipt of a new packet or a timeout event occurs.\nNote: Setting this value to zero disables the delay timer interrupt.\nNote: Applicable only when Scatter Gather is enabled.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"S2MM_DMASR": {
|
||||
"address_offset": "0x34",
|
||||
"size": 32,
|
||||
"display_name": "S2MM DMA Status Register",
|
||||
"description": "S2MM DMA Status Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x10000",
|
||||
"fields": {
|
||||
"Halted": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Channel Halted",
|
||||
"description": "DMA Channel Halted. Indicates the run/stop state of the DMA channel. 0 - DMA channel running. 1 - DMA channel halted. For Scatter/Gather Mode this bit gets set when DMACR.RS = 0 and DMA and SG operations have halted. For Direct Register Mode this bit gets set when DMACR.RS = 0 and DMA operations have halted. There can be a lag of time between when DMACR.RS = 0 and when DMASR.Halted = 1 \nNote: When halted (RS= 0 and Halted = 1), writing to CURDESC_PTR or TAILDESC_PTR pointer registers has no effect on DMA operations when in Scatter Gather Mode. For Direct Register Mode, writing to the LENGTH register has no effect on DMA operations.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"Idle": {
|
||||
"bit_offset": 1,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Channel Idle",
|
||||
"description": "DMA Channel Idle. Indicates the state of AXI DMA operations.\nFor Scatter / Gather Mode when IDLE indicates the SG Engine has reached the tail pointer for the associated channel and all queued descriptors have been processed. Writing to the tail pointer register automatically restarts DMA operations.\nFor Direct Register Mode when IDLE indicates the current transfer has completed. 0 - Not Idle. 1 - Idle. Note: This bit is 0 when channel is halted (DMASR.Halted=1). This bit is also 0 prior to initial transfer when AXI DMA configured for Direct Register Mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"SGIncld": {
|
||||
"bit_offset": 3,
|
||||
"bit_width": 1,
|
||||
"display_name": "SGIncld",
|
||||
"description": "Scatter Gather Engine Included. DMASR.SGIncld = 1 indicates the Scatter Gather engine is included and the AXI DMA is configured for Scatter Gather mode. DMASR.SGIncld = 0 indicates the Scatter Gather engine is excluded and the AXI DMA is configured for Direct Register Mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"DMAIntErr": {
|
||||
"bit_offset": 4,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Internal Error",
|
||||
"description": "DMA Internal Error. This error occurs if the buffer length specified in the fetched descriptor is set to 0. Also, when in Scatter Gather Mode and using the status app length field, this error occurs when the Status AXI4-Stream packet RxLength field does not match the S2MM packet being received by the S_AXIS_S2MM interface. When Scatter Gather is disabled, this error is flagged if any error occurs during Memory write or if the incoming packet is bigger than what is specified in the DMA length register.\nThis error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Internal Errors 1 - DMA Internal Error detected.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"DMASlvErr": {
|
||||
"bit_offset": 5,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Slave Error",
|
||||
"description": "DMA Slave Error. This error occurs if the slave read from the Memory Map interface issues a Slave Error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Slave Errors. 1 - DMA Slave Error detected.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"DMADecErr": {
|
||||
"bit_offset": 6,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Decode Error",
|
||||
"description": "DMA Decode Error. This error occurs if the address request points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Decode Errors. 1 - DMA Decode Error detected.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"SGIntErr": {
|
||||
"bit_offset": 8,
|
||||
"bit_width": 1,
|
||||
"display_name": "Scatter Gather Internal Error",
|
||||
"description": "Scatter Gather Internal Error. This error occurs if a descriptor with the \"Complete bit\" already set is fetched. This indicates to the SG Engine that the descriptor is a tail descriptor. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Internal Errors. 1 - SG Internal Error detected. Note: Applicable only when Scatter Gather is enabled. \n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"SGSlvErr": {
|
||||
"bit_offset": 9,
|
||||
"bit_width": 1,
|
||||
"display_name": "Scatter Gather Slave Error",
|
||||
"description": "Scatter Gather Slave Error. This error occurs if the slave read from on the Memory Map interface issues a Slave error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Slave Errors. 1 - SG Slave Error detected. DMA Engine halts. Note: Applicable only when Scatter Gather is enabled. \n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"SGDecErr": {
|
||||
"bit_offset": 10,
|
||||
"bit_width": 1,
|
||||
"display_name": "Scatter Gather Decode Error",
|
||||
"description": "Scatter Gather Decode Error. This error occurs if CURDESC_PTR and/or NXTDESC_PTR points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Decode Errors. 1 - SG Decode Error detected. DMA Engine halts. Note: Applicable only when Scatter Gather is enabled. \n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"IOC_Irq": {
|
||||
"bit_offset": 12,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Complete",
|
||||
"description": "Interrupt on Complete. When set to 1 for Scatter/Gather Mode, indicates an interrupt event was generated on completion of a descriptor. This occurs for descriptors with the End of Frame (EOF) bit set. When set to 1 for Direct Register Mode, indicates an interrupt event was generated on completion of a transfer. If the corresponding bit in S2MM_DMACR is enabled (IOC_IrqEn = 1) and if the interrupt threshold has been met, causes an interrupt out to be generated from the AXI DMA. 0 - No IOC Interrupt. 1 - IOC Interrupt detected. Writing a 1 to this bit will clear it.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Dly_Irq": {
|
||||
"bit_offset": 13,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Delay",
|
||||
"description": "Interrupt on Delay. When set to 1, indicates an interrupt event was generated on delay timer time out. If the corresponding bit is enabled in the S2MM_DMACR (Dly_IrqEn = 1), an interrupt out is generated from the AXI DMA. 0 - No Delay Interrupt. 1 - Delay Interrupt detected.1 = IOC Interrupt detected. Writing a 1 to this bit will clear it. Note: Applicable only when Scatter Gather is enabled. \n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Err_Irq": {
|
||||
"bit_offset": 14,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Error",
|
||||
"description": "Interrupt on Error. When set to 1, indicates an interrupt event was generated on error. If the corresponding bit is enabled in the S2MM_DMACR (Err_IrqEn = 1), an interrupt out is generated from the AXI DMA.\nWriting a 1 to this bit will clear it. 0 - No error Interrupt. 1 - Error interrupt detected.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"IRQThresholdSts": {
|
||||
"bit_offset": 16,
|
||||
"bit_width": 8,
|
||||
"display_name": "Interrupt Threshold Status",
|
||||
"description": "Interrupt Threshold Status. Indicates current interrupt threshold value.\nNote: Applicable only when Scatter Gather is enabled.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"IRQDelaySts": {
|
||||
"bit_offset": 24,
|
||||
"bit_width": 8,
|
||||
"display_name": "Interrupt Delay Time Status",
|
||||
"description": "Interrupt Delay Time Status. Indicates current interrupt delay time value.\nNote: Applicable only when Scatter Gather is enabled.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
}
|
||||
}
|
||||
},
|
||||
"S2MM_DA": {
|
||||
"address_offset": "0x48",
|
||||
"size": 32,
|
||||
"display_name": "S2MM DMA Destination Address Register",
|
||||
"description": "S2MM DMA Destination Address Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"Destination_Address": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 32,
|
||||
"display_name": "Destination Address",
|
||||
"description": "Indicates the destination address the AXI DMA writes to transfer data from AXI4-Stream on S2MM Channel.\nNote: If Data Realignment Engine is included, the Destination Address can be at any byte offset. If Data Realignment Engine is not included, the Destination Address must be S2MM Memory Map data width aligned.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"S2MM_DA_MSB": {
|
||||
"address_offset": "0x4C",
|
||||
"size": 32,
|
||||
"display_name": "S2MM Destination Address Register",
|
||||
"description": "S2MM Destination Address Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"Destination_Address": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 32,
|
||||
"display_name": "Destination Address",
|
||||
"description": "Indicates the MSB 32 bits of the Destination address AXI DMA writes to transfer data from AXI4-Stream on the S2MM Channel.\nNote: If Data Realignment Engine is included, the Destination Address can be at any byte offset. If Data Realignment Engine is not included, the Dstination Address must be S2MM Memory Map data width aligned.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"S2MM_LENGTH": {
|
||||
"address_offset": "0x58",
|
||||
"size": 32,
|
||||
"display_name": "S2MM DMA Transfer Length Register",
|
||||
"description": "S2MM DMA Transfer Length Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"Length": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 26,
|
||||
"display_name": "Length",
|
||||
"description": "Indicates the length in bytes of the S2MM buffer available to write receive data from the S2MM channel. Writing a non-zero value to this register enables S2MM channel to receive packet data.\nAt the completion of the S2MM transfer, the number of actual bytes written on the S2MM AXI4 interface is updated to the S2MM_LENGTH register.\nNote: This value must be greater than or equal to the largest expected packet to be received on S2MM AXI4-Stream. Values smaller than the received packet result in undefined behavior. \n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+380
@@ -0,0 +1,380 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "system_top_axi_gpio_0_0",
|
||||
"cell_name": "axi_gpio_0",
|
||||
"component_reference": "xilinx.com:ip:axi_gpio:2.0",
|
||||
"ip_revision": "33",
|
||||
"gen_directory": "../../../../../../project_fix_dac.gen/sources_1/bd/system_top/ip/system_top_axi_gpio_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"C_TRI_DEFAULT": [ { "value": "0xFFFFFFFF", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||
"C_GPIO_WIDTH": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_GPIO2_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_IS_DUAL": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_ALL_INPUTS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_TRI_DEFAULT_2": [ { "value": "0xFFFFFFFF", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||
"C_DOUT_DEFAULT_2": [ { "value": "0x00000000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||
"C_DOUT_DEFAULT": [ { "value": "0x00000000", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||
"C_ALL_INPUTS_2": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_INTERRUPT_PRESENT": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "system_top_axi_gpio_0_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"USE_BOARD_FLOW": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"GPIO_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
|
||||
"GPIO2_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
|
||||
"C_ALL_OUTPUTS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_ALL_OUTPUTS_2": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_FAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_S_AXI_ADDR_WIDTH": [ { "value": "9", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_DATA_WIDTH": [ { "value": "32", "format": "long", "usage": "all" } ],
|
||||
"C_GPIO_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_GPIO2_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ALL_INPUTS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ALL_INPUTS_2": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ALL_OUTPUTS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ALL_OUTPUTS_2": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INTERRUPT_PRESENT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DOUT_DEFAULT": [ { "value": "0x00000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_TRI_DEFAULT": [ { "value": "0xFFFFFFFF", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_IS_DUAL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DOUT_DEFAULT_2": [ { "value": "0x00000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_TRI_DEFAULT_2": [ { "value": "0xFFFFFFFF", "resolve_type": "generated", "format": "bitString", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "xilinx.com:zc706:part0:1.4" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z045" } ],
|
||||
"NEXTGEN_VERSAL": [ { "value": "0" } ],
|
||||
"PACKAGE": [ { "value": "ffg900" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "33" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../project_fix_dac.gen/sources_1/bd/system_top/ip/system_top_axi_gpio_0_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2024.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"s_axi_aclk": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_aresetn": [ { "direction": "in", "driver_value": "1" } ],
|
||||
"s_axi_awaddr": [ { "direction": "in", "size_left": "8", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_awvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_awready": [ { "direction": "out" } ],
|
||||
"s_axi_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_wvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_wready": [ { "direction": "out" } ],
|
||||
"s_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s_axi_bvalid": [ { "direction": "out" } ],
|
||||
"s_axi_bready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_araddr": [ { "direction": "in", "size_left": "8", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_arvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_arready": [ { "direction": "out" } ],
|
||||
"s_axi_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"s_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s_axi_rvalid": [ { "direction": "out" } ],
|
||||
"s_axi_rready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"ip2intc_irpt": [ { "direction": "out" } ],
|
||||
"gpio_io_i": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"gpio_io_o": [ { "direction": "out", "size_left": "0", "size_right": "0" } ],
|
||||
"gpio_io_t": [ { "direction": "out", "size_left": "0", "size_right": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"S_AXI": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"memory_map_ref": "S_AXI",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "9", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"ARADDR": [ { "physical_name": "s_axi_araddr" } ],
|
||||
"ARREADY": [ { "physical_name": "s_axi_arready" } ],
|
||||
"ARVALID": [ { "physical_name": "s_axi_arvalid" } ],
|
||||
"AWADDR": [ { "physical_name": "s_axi_awaddr" } ],
|
||||
"AWREADY": [ { "physical_name": "s_axi_awready" } ],
|
||||
"AWVALID": [ { "physical_name": "s_axi_awvalid" } ],
|
||||
"BREADY": [ { "physical_name": "s_axi_bready" } ],
|
||||
"BRESP": [ { "physical_name": "s_axi_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "s_axi_bvalid" } ],
|
||||
"RDATA": [ { "physical_name": "s_axi_rdata" } ],
|
||||
"RREADY": [ { "physical_name": "s_axi_rready" } ],
|
||||
"RRESP": [ { "physical_name": "s_axi_rresp" } ],
|
||||
"RVALID": [ { "physical_name": "s_axi_rvalid" } ],
|
||||
"WDATA": [ { "physical_name": "s_axi_wdata" } ],
|
||||
"WREADY": [ { "physical_name": "s_axi_wready" } ],
|
||||
"WSTRB": [ { "physical_name": "s_axi_wstrb" } ],
|
||||
"WVALID": [ { "physical_name": "s_axi_wvalid" } ]
|
||||
}
|
||||
},
|
||||
"S_AXI_ACLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S_AXI", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "s_axi_aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "s_axi_aclk" } ]
|
||||
}
|
||||
},
|
||||
"S_AXI_ARESETN": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "s_axi_aresetn" } ]
|
||||
}
|
||||
},
|
||||
"IP2INTC_IRQ": {
|
||||
"vlnv": "xilinx.com:signal:interrupt:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"SENSITIVITY": [ { "value": "LEVEL_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"PortWidth": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"INTERRUPT": [ { "physical_name": "ip2intc_irpt" } ]
|
||||
}
|
||||
},
|
||||
"GPIO": {
|
||||
"vlnv": "xilinx.com:interface:gpio:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:gpio_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"BOARD.ASSOCIATED_PARAM": [ { "value": "GPIO_BOARD_INTERFACE", "value_src": "constant", "value_permission": "bd", "usage": "all" } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TRI_I": [ { "physical_name": "gpio_io_i" } ],
|
||||
"TRI_O": [ { "physical_name": "gpio_io_o" } ],
|
||||
"TRI_T": [ { "physical_name": "gpio_io_t" } ]
|
||||
}
|
||||
}
|
||||
},
|
||||
"memory_maps": {
|
||||
"S_AXI": {
|
||||
"display_name": "S_AXI_MEM",
|
||||
"description": "Memory Map for S_AXI",
|
||||
"address_blocks": {
|
||||
"Reg": {
|
||||
"base_address": "0",
|
||||
"range": "4096",
|
||||
"display_name": "Reg",
|
||||
"description": "Register Block",
|
||||
"usage": "register",
|
||||
"access": "read-write",
|
||||
"registers": {
|
||||
"GPIO_DATA": {
|
||||
"address_offset": "0x0",
|
||||
"size": 1,
|
||||
"display_name": "Channel_1_GPIO_DATA",
|
||||
"description": "Channel-1 AXI GPIO Data register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"CH1_DATA": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 1,
|
||||
"display_name": "Channel_1_GPIO_DATA",
|
||||
"description": "AXI GPIO Data Register.\nFor each I/O bit programmed as input\n R - Reads value on the input pin.\n W - No effect.\nFor each I/O bit programmed as output\n R - Reads value on GPIO_O pins\n W - Writes value to the corresponding AXI GPIO \n data register bit and output pin\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"GPIO_TRI": {
|
||||
"address_offset": "0x4",
|
||||
"size": 1,
|
||||
"display_name": "Channel_1_GPIO_TRI",
|
||||
"description": "Channel-1 AXI GPIO 3-State Control register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"CH1_TRI": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 1,
|
||||
"display_name": "Channel_1_GPIO_DATA",
|
||||
"description": "AXI GPIO 3-State Control Register\nEach I/O pin of the AXI GPIO is individually programmable as an input or output For each of the bits 0 - I/O pin configured as output 1 - I/O pin configured as input\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"GPIO2_DATA": {
|
||||
"address_offset": "0x8",
|
||||
"size": 32,
|
||||
"display_name": "Channel_2_GPIO_DATA",
|
||||
"description": "Channel-2 AXI GPIO Data register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"CH2_DATA": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 32,
|
||||
"display_name": "Channel_2_GPIO_DATA",
|
||||
"description": "AXI GPIO Data Register.\nFor each I/O bit programmed as input\n R - Reads value on the input pin.\n W - No effect.\nFor each I/O bit programmed as output\n R - Reads value on GPIO_O pins\n W - Writes value to the corresponding AXI GPIO \n data register bit and output pin\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"GPIO2_TRI": {
|
||||
"address_offset": "0xC",
|
||||
"size": 32,
|
||||
"display_name": "Channel_2_GPIO_TRI",
|
||||
"description": "Channel-2 AXI GPIO 3-State Control register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"CH2_TRI": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 32,
|
||||
"display_name": "Channel_2_GPIO_DATA",
|
||||
"description": "AXI GPIO 3-State Control Register\nEach I/O pin of the AXI GPIO is individually programmable as an input or output For each of the bits 0 - I/O pin configured as output 1 - I/O pin configured as input\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"GIER": {
|
||||
"address_offset": "0x11C",
|
||||
"size": 32,
|
||||
"display_name": "Global_Interrupt_Enable register",
|
||||
"description": "Global_Interrupt_Enable register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"INT_EN": {
|
||||
"bit_offset": 31,
|
||||
"bit_width": 1,
|
||||
"display_name": "Global_Interrupt_Enable",
|
||||
"description": "Master enable for the device interrupt output\n 0 - Disabled\n 1 - Enabled\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"IP_IER": {
|
||||
"address_offset": "0x128",
|
||||
"size": 32,
|
||||
"display_name": "IP Interrupt Enable register",
|
||||
"description": "IP Interrupt Enable register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"CH1_INT_EN": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 1,
|
||||
"display_name": "Channel_1_Interrupt_Enable",
|
||||
"description": "Enable Channel 1 Interrupt\n 0 - Disabled (masked)\n 1 - Enabled\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"CH2_INT_EN": {
|
||||
"bit_offset": 1,
|
||||
"bit_width": 1,
|
||||
"display_name": "Channel_2_Interrupt_Enable",
|
||||
"description": "Enable Channel 2 Interrupt\n 0 - Disabled (masked)\n 1 - Enabled\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"IP_ISR": {
|
||||
"address_offset": "0x120",
|
||||
"size": 32,
|
||||
"display_name": "IP Interrupt Status register",
|
||||
"description": "IP Interrupt Status register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"CH1_INT_S": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 1,
|
||||
"display_name": "Channel_1_Interrupt_Status",
|
||||
"description": "Channel 1 Interrupt Status\n 0 - No Channel 1 input interrupt\n 1 - Channel 1 input interrupt\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"CH2_INT_S": {
|
||||
"bit_offset": 1,
|
||||
"bit_width": 1,
|
||||
"display_name": "Channel_2_Interrupt_Status",
|
||||
"description": "Channel 2 Interrupt Status\n 0 - No Channel 2 input interrupt\n 1 - Channel 2 input interrupt\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+537
@@ -0,0 +1,537 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "system_top_axi_smc1_0",
|
||||
"cell_name": "axi_smc1",
|
||||
"component_reference": "xilinx.com:ip:smartconnect:1.0",
|
||||
"ip_revision": "23",
|
||||
"gen_directory": "../../../../../../project_fix_dac.gen/sources_1/bd/system_top/ip/system_top_axi_smc1_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "system_top_axi_smc1_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"NUM_MI": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"NUM_SI": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"NUM_CLKS": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_ARESETN": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ADVANCED_PROPERTIES": [ { "value": "0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"TLM_COMPONENT_NAME": [ { "value": "system_top_axi_smc1_0", "resolve_type": "generated", "usage": "simulation.tlm" } ],
|
||||
"HAS_RESET": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "xilinx.com:zc706:part0:1.4" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z045" } ],
|
||||
"NEXTGEN_VERSAL": [ { "value": "0" } ],
|
||||
"PACKAGE": [ { "value": "ffg900" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "23" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../project_fix_dac.gen/sources_1/bd/system_top/ip/system_top_axi_smc1_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2024.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"aclk": [ { "direction": "in" } ],
|
||||
"aresetn": [ { "direction": "in", "driver_value": "1" } ],
|
||||
"S00_AXI_awid": [ { "direction": "in", "size_left": "11", "size_right": "0", "driver_value": "0" } ],
|
||||
"S00_AXI_awaddr": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"S00_AXI_awlen": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||
"S00_AXI_awsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "010" } ],
|
||||
"S00_AXI_awburst": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "1" } ],
|
||||
"S00_AXI_awlock": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"S00_AXI_awcache": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "3" } ],
|
||||
"S00_AXI_awprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"S00_AXI_awqos": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||
"S00_AXI_awvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"S00_AXI_awready": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"S00_AXI_wid": [ { "direction": "in", "size_left": "11", "size_right": "0", "driver_value": "0" } ],
|
||||
"S00_AXI_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"S00_AXI_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "1" } ],
|
||||
"S00_AXI_wlast": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"S00_AXI_wvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"S00_AXI_wready": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"S00_AXI_bid": [ { "direction": "out", "size_left": "11", "size_right": "0", "driver_value": "0" } ],
|
||||
"S00_AXI_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"S00_AXI_bvalid": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"S00_AXI_bready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"S00_AXI_arid": [ { "direction": "in", "size_left": "11", "size_right": "0", "driver_value": "0" } ],
|
||||
"S00_AXI_araddr": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"S00_AXI_arlen": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||
"S00_AXI_arsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "010" } ],
|
||||
"S00_AXI_arburst": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "1" } ],
|
||||
"S00_AXI_arlock": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"S00_AXI_arcache": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "3" } ],
|
||||
"S00_AXI_arprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"S00_AXI_arqos": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||
"S00_AXI_arvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"S00_AXI_arready": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"S00_AXI_rid": [ { "direction": "out", "size_left": "11", "size_right": "0", "driver_value": "0" } ],
|
||||
"S00_AXI_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"S00_AXI_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"S00_AXI_rlast": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"S00_AXI_rvalid": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"S00_AXI_rready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"S01_AXI_awaddr": [ { "direction": "in", "size_left": "39", "size_right": "0", "driver_value": "0" } ],
|
||||
"S01_AXI_awlen": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
|
||||
"S01_AXI_awsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "011" } ],
|
||||
"S01_AXI_awburst": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "1" } ],
|
||||
"S01_AXI_awlock": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"S01_AXI_awcache": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "3" } ],
|
||||
"S01_AXI_awprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"S01_AXI_awqos": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||
"S01_AXI_awvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"S01_AXI_awready": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"S01_AXI_wdata": [ { "direction": "in", "size_left": "63", "size_right": "0", "driver_value": "0" } ],
|
||||
"S01_AXI_wstrb": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "1" } ],
|
||||
"S01_AXI_wlast": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"S01_AXI_wvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"S01_AXI_wready": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"S01_AXI_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"S01_AXI_bvalid": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"S01_AXI_bready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"S02_AXI_awaddr": [ { "direction": "in", "size_left": "39", "size_right": "0", "driver_value": "0" } ],
|
||||
"S02_AXI_awlen": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
|
||||
"S02_AXI_awsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "011" } ],
|
||||
"S02_AXI_awburst": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "1" } ],
|
||||
"S02_AXI_awlock": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"S02_AXI_awcache": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "3" } ],
|
||||
"S02_AXI_awprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"S02_AXI_awqos": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||
"S02_AXI_awvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"S02_AXI_awready": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"S02_AXI_wdata": [ { "direction": "in", "size_left": "63", "size_right": "0", "driver_value": "0" } ],
|
||||
"S02_AXI_wstrb": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "1" } ],
|
||||
"S02_AXI_wlast": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"S02_AXI_wvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"S02_AXI_wready": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"S02_AXI_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"S02_AXI_bvalid": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"S02_AXI_bready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"S03_AXI_awaddr": [ { "direction": "in", "size_left": "39", "size_right": "0", "driver_value": "0" } ],
|
||||
"S03_AXI_awlen": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
|
||||
"S03_AXI_awsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "011" } ],
|
||||
"S03_AXI_awburst": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "1" } ],
|
||||
"S03_AXI_awlock": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"S03_AXI_awcache": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "3" } ],
|
||||
"S03_AXI_awprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"S03_AXI_awqos": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||
"S03_AXI_awvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"S03_AXI_awready": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"S03_AXI_wdata": [ { "direction": "in", "size_left": "63", "size_right": "0", "driver_value": "0" } ],
|
||||
"S03_AXI_wstrb": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "1" } ],
|
||||
"S03_AXI_wlast": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"S03_AXI_wvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"S03_AXI_wready": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"S03_AXI_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"S03_AXI_bvalid": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"S03_AXI_bready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"M00_AXI_awaddr": [ { "direction": "out", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"M00_AXI_awlen": [ { "direction": "out", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
|
||||
"M00_AXI_awsize": [ { "direction": "out", "size_left": "2", "size_right": "0", "driver_value": "110" } ],
|
||||
"M00_AXI_awburst": [ { "direction": "out", "size_left": "1", "size_right": "0", "driver_value": "1" } ],
|
||||
"M00_AXI_awlock": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"M00_AXI_awcache": [ { "direction": "out", "size_left": "3", "size_right": "0", "driver_value": "3" } ],
|
||||
"M00_AXI_awprot": [ { "direction": "out", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"M00_AXI_awqos": [ { "direction": "out", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||
"M00_AXI_awvalid": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"M00_AXI_awready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"M00_AXI_wdata": [ { "direction": "out", "size_left": "511", "size_right": "0", "driver_value": "0" } ],
|
||||
"M00_AXI_wstrb": [ { "direction": "out", "size_left": "63", "size_right": "0", "driver_value": "1" } ],
|
||||
"M00_AXI_wlast": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"M00_AXI_wvalid": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"M00_AXI_wready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"M00_AXI_bresp": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"M00_AXI_bvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"M00_AXI_bready": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"M00_AXI_araddr": [ { "direction": "out", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"M00_AXI_arlen": [ { "direction": "out", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
|
||||
"M00_AXI_arsize": [ { "direction": "out", "size_left": "2", "size_right": "0", "driver_value": "110" } ],
|
||||
"M00_AXI_arburst": [ { "direction": "out", "size_left": "1", "size_right": "0", "driver_value": "1" } ],
|
||||
"M00_AXI_arlock": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"M00_AXI_arcache": [ { "direction": "out", "size_left": "3", "size_right": "0", "driver_value": "3" } ],
|
||||
"M00_AXI_arprot": [ { "direction": "out", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"M00_AXI_arqos": [ { "direction": "out", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||
"M00_AXI_arvalid": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"M00_AXI_arready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"M00_AXI_rdata": [ { "direction": "in", "size_left": "511", "size_right": "0", "driver_value": "0" } ],
|
||||
"M00_AXI_rresp": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"M00_AXI_rlast": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"M00_AXI_rvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"M00_AXI_rready": [ { "direction": "out", "driver_value": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"CLK.aclk": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "200000000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_mig_7series_0_0_ui_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "M00_AXI:S00_AXI:S01_AXI:S02_AXI:S03_AXI", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ],
|
||||
"ASSOCIATED_CLKEN": [ { "value": "m_sc_aclken", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "aclk" } ]
|
||||
}
|
||||
},
|
||||
"RST.aresetn": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "aresetn" } ]
|
||||
}
|
||||
},
|
||||
"S00_AXI": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI3", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "200000000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "12", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "16", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_mig_7series_0_0_ui_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "4", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "4", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"AWID": [ { "physical_name": "S00_AXI_awid" } ],
|
||||
"AWADDR": [ { "physical_name": "S00_AXI_awaddr" } ],
|
||||
"AWLEN": [ { "physical_name": "S00_AXI_awlen" } ],
|
||||
"AWSIZE": [ { "physical_name": "S00_AXI_awsize" } ],
|
||||
"AWBURST": [ { "physical_name": "S00_AXI_awburst" } ],
|
||||
"AWLOCK": [ { "physical_name": "S00_AXI_awlock" } ],
|
||||
"AWCACHE": [ { "physical_name": "S00_AXI_awcache" } ],
|
||||
"AWPROT": [ { "physical_name": "S00_AXI_awprot" } ],
|
||||
"AWQOS": [ { "physical_name": "S00_AXI_awqos" } ],
|
||||
"AWVALID": [ { "physical_name": "S00_AXI_awvalid" } ],
|
||||
"AWREADY": [ { "physical_name": "S00_AXI_awready" } ],
|
||||
"WID": [ { "physical_name": "S00_AXI_wid" } ],
|
||||
"WDATA": [ { "physical_name": "S00_AXI_wdata" } ],
|
||||
"WSTRB": [ { "physical_name": "S00_AXI_wstrb" } ],
|
||||
"WLAST": [ { "physical_name": "S00_AXI_wlast" } ],
|
||||
"WVALID": [ { "physical_name": "S00_AXI_wvalid" } ],
|
||||
"WREADY": [ { "physical_name": "S00_AXI_wready" } ],
|
||||
"BID": [ { "physical_name": "S00_AXI_bid" } ],
|
||||
"BRESP": [ { "physical_name": "S00_AXI_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "S00_AXI_bvalid" } ],
|
||||
"BREADY": [ { "physical_name": "S00_AXI_bready" } ],
|
||||
"ARID": [ { "physical_name": "S00_AXI_arid" } ],
|
||||
"ARADDR": [ { "physical_name": "S00_AXI_araddr" } ],
|
||||
"ARLEN": [ { "physical_name": "S00_AXI_arlen" } ],
|
||||
"ARSIZE": [ { "physical_name": "S00_AXI_arsize" } ],
|
||||
"ARBURST": [ { "physical_name": "S00_AXI_arburst" } ],
|
||||
"ARLOCK": [ { "physical_name": "S00_AXI_arlock" } ],
|
||||
"ARCACHE": [ { "physical_name": "S00_AXI_arcache" } ],
|
||||
"ARPROT": [ { "physical_name": "S00_AXI_arprot" } ],
|
||||
"ARQOS": [ { "physical_name": "S00_AXI_arqos" } ],
|
||||
"ARVALID": [ { "physical_name": "S00_AXI_arvalid" } ],
|
||||
"ARREADY": [ { "physical_name": "S00_AXI_arready" } ],
|
||||
"RID": [ { "physical_name": "S00_AXI_rid" } ],
|
||||
"RDATA": [ { "physical_name": "S00_AXI_rdata" } ],
|
||||
"RRESP": [ { "physical_name": "S00_AXI_rresp" } ],
|
||||
"RLAST": [ { "physical_name": "S00_AXI_rlast" } ],
|
||||
"RVALID": [ { "physical_name": "S00_AXI_rvalid" } ],
|
||||
"RREADY": [ { "physical_name": "S00_AXI_rready" } ]
|
||||
}
|
||||
},
|
||||
"S01_AXI": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "64", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "200000000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "40", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "WRITE_ONLY", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "16", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_mig_7series_0_0_ui_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"AWADDR": [ { "physical_name": "S01_AXI_awaddr" } ],
|
||||
"AWLEN": [ { "physical_name": "S01_AXI_awlen" } ],
|
||||
"AWSIZE": [ { "physical_name": "S01_AXI_awsize" } ],
|
||||
"AWBURST": [ { "physical_name": "S01_AXI_awburst" } ],
|
||||
"AWLOCK": [ { "physical_name": "S01_AXI_awlock" } ],
|
||||
"AWCACHE": [ { "physical_name": "S01_AXI_awcache" } ],
|
||||
"AWPROT": [ { "physical_name": "S01_AXI_awprot" } ],
|
||||
"AWQOS": [ { "physical_name": "S01_AXI_awqos" } ],
|
||||
"AWVALID": [ { "physical_name": "S01_AXI_awvalid" } ],
|
||||
"AWREADY": [ { "physical_name": "S01_AXI_awready" } ],
|
||||
"WDATA": [ { "physical_name": "S01_AXI_wdata" } ],
|
||||
"WSTRB": [ { "physical_name": "S01_AXI_wstrb" } ],
|
||||
"WLAST": [ { "physical_name": "S01_AXI_wlast" } ],
|
||||
"WVALID": [ { "physical_name": "S01_AXI_wvalid" } ],
|
||||
"WREADY": [ { "physical_name": "S01_AXI_wready" } ],
|
||||
"BRESP": [ { "physical_name": "S01_AXI_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "S01_AXI_bvalid" } ],
|
||||
"BREADY": [ { "physical_name": "S01_AXI_bready" } ]
|
||||
}
|
||||
},
|
||||
"S02_AXI": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "64", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "200000000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "40", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "WRITE_ONLY", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "16", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_mig_7series_0_0_ui_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"AWADDR": [ { "physical_name": "S02_AXI_awaddr" } ],
|
||||
"AWLEN": [ { "physical_name": "S02_AXI_awlen" } ],
|
||||
"AWSIZE": [ { "physical_name": "S02_AXI_awsize" } ],
|
||||
"AWBURST": [ { "physical_name": "S02_AXI_awburst" } ],
|
||||
"AWLOCK": [ { "physical_name": "S02_AXI_awlock" } ],
|
||||
"AWCACHE": [ { "physical_name": "S02_AXI_awcache" } ],
|
||||
"AWPROT": [ { "physical_name": "S02_AXI_awprot" } ],
|
||||
"AWQOS": [ { "physical_name": "S02_AXI_awqos" } ],
|
||||
"AWVALID": [ { "physical_name": "S02_AXI_awvalid" } ],
|
||||
"AWREADY": [ { "physical_name": "S02_AXI_awready" } ],
|
||||
"WDATA": [ { "physical_name": "S02_AXI_wdata" } ],
|
||||
"WSTRB": [ { "physical_name": "S02_AXI_wstrb" } ],
|
||||
"WLAST": [ { "physical_name": "S02_AXI_wlast" } ],
|
||||
"WVALID": [ { "physical_name": "S02_AXI_wvalid" } ],
|
||||
"WREADY": [ { "physical_name": "S02_AXI_wready" } ],
|
||||
"BRESP": [ { "physical_name": "S02_AXI_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "S02_AXI_bvalid" } ],
|
||||
"BREADY": [ { "physical_name": "S02_AXI_bready" } ]
|
||||
}
|
||||
},
|
||||
"S03_AXI": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "64", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "200000000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "40", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "WRITE_ONLY", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "16", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_mig_7series_0_0_ui_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"AWADDR": [ { "physical_name": "S03_AXI_awaddr" } ],
|
||||
"AWLEN": [ { "physical_name": "S03_AXI_awlen" } ],
|
||||
"AWSIZE": [ { "physical_name": "S03_AXI_awsize" } ],
|
||||
"AWBURST": [ { "physical_name": "S03_AXI_awburst" } ],
|
||||
"AWLOCK": [ { "physical_name": "S03_AXI_awlock" } ],
|
||||
"AWCACHE": [ { "physical_name": "S03_AXI_awcache" } ],
|
||||
"AWPROT": [ { "physical_name": "S03_AXI_awprot" } ],
|
||||
"AWQOS": [ { "physical_name": "S03_AXI_awqos" } ],
|
||||
"AWVALID": [ { "physical_name": "S03_AXI_awvalid" } ],
|
||||
"AWREADY": [ { "physical_name": "S03_AXI_awready" } ],
|
||||
"WDATA": [ { "physical_name": "S03_AXI_wdata" } ],
|
||||
"WSTRB": [ { "physical_name": "S03_AXI_wstrb" } ],
|
||||
"WLAST": [ { "physical_name": "S03_AXI_wlast" } ],
|
||||
"WVALID": [ { "physical_name": "S03_AXI_wvalid" } ],
|
||||
"WREADY": [ { "physical_name": "S03_AXI_wready" } ],
|
||||
"BRESP": [ { "physical_name": "S03_AXI_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "S03_AXI_bvalid" } ],
|
||||
"BREADY": [ { "physical_name": "S03_AXI_bready" } ]
|
||||
}
|
||||
},
|
||||
"M00_AXI": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "512", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "200000000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "2", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_mig_7series_0_0_ui_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"AWADDR": [ { "physical_name": "M00_AXI_awaddr" } ],
|
||||
"AWLEN": [ { "physical_name": "M00_AXI_awlen" } ],
|
||||
"AWSIZE": [ { "physical_name": "M00_AXI_awsize" } ],
|
||||
"AWBURST": [ { "physical_name": "M00_AXI_awburst" } ],
|
||||
"AWLOCK": [ { "physical_name": "M00_AXI_awlock" } ],
|
||||
"AWCACHE": [ { "physical_name": "M00_AXI_awcache" } ],
|
||||
"AWPROT": [ { "physical_name": "M00_AXI_awprot" } ],
|
||||
"AWQOS": [ { "physical_name": "M00_AXI_awqos" } ],
|
||||
"AWVALID": [ { "physical_name": "M00_AXI_awvalid" } ],
|
||||
"AWREADY": [ { "physical_name": "M00_AXI_awready" } ],
|
||||
"WDATA": [ { "physical_name": "M00_AXI_wdata" } ],
|
||||
"WSTRB": [ { "physical_name": "M00_AXI_wstrb" } ],
|
||||
"WLAST": [ { "physical_name": "M00_AXI_wlast" } ],
|
||||
"WVALID": [ { "physical_name": "M00_AXI_wvalid" } ],
|
||||
"WREADY": [ { "physical_name": "M00_AXI_wready" } ],
|
||||
"BRESP": [ { "physical_name": "M00_AXI_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "M00_AXI_bvalid" } ],
|
||||
"BREADY": [ { "physical_name": "M00_AXI_bready" } ],
|
||||
"ARADDR": [ { "physical_name": "M00_AXI_araddr" } ],
|
||||
"ARLEN": [ { "physical_name": "M00_AXI_arlen" } ],
|
||||
"ARSIZE": [ { "physical_name": "M00_AXI_arsize" } ],
|
||||
"ARBURST": [ { "physical_name": "M00_AXI_arburst" } ],
|
||||
"ARLOCK": [ { "physical_name": "M00_AXI_arlock" } ],
|
||||
"ARCACHE": [ { "physical_name": "M00_AXI_arcache" } ],
|
||||
"ARPROT": [ { "physical_name": "M00_AXI_arprot" } ],
|
||||
"ARQOS": [ { "physical_name": "M00_AXI_arqos" } ],
|
||||
"ARVALID": [ { "physical_name": "M00_AXI_arvalid" } ],
|
||||
"ARREADY": [ { "physical_name": "M00_AXI_arready" } ],
|
||||
"RDATA": [ { "physical_name": "M00_AXI_rdata" } ],
|
||||
"RRESP": [ { "physical_name": "M00_AXI_rresp" } ],
|
||||
"RLAST": [ { "physical_name": "M00_AXI_rlast" } ],
|
||||
"RVALID": [ { "physical_name": "M00_AXI_rvalid" } ],
|
||||
"RREADY": [ { "physical_name": "M00_AXI_rready" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+1195
File diff suppressed because it is too large
Load Diff
+295
@@ -0,0 +1,295 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "system_top_blk_mem_gen_0_0",
|
||||
"cell_name": "blk_mem_gen_0",
|
||||
"component_reference": "xilinx.com:ip:blk_mem_gen:8.4",
|
||||
"ip_revision": "8",
|
||||
"gen_directory": "../../../../../../project_fix_dac.gen/sources_1/bd/system_top/ip/system_top_blk_mem_gen_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "system_top_blk_mem_gen_0_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Interface_Type": [ { "value": "Native", "resolve_type": "user", "usage": "all" } ],
|
||||
"AXI_Type": [ { "value": "AXI4_Full", "resolve_type": "user", "usage": "all" } ],
|
||||
"AXI_Slave_Type": [ { "value": "Memory_Slave", "resolve_type": "user", "usage": "all" } ],
|
||||
"Use_AXI_ID": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"AXI_ID_Width": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Memory_Type": [ { "value": "True_Dual_Port_RAM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PRIM_type_to_Implement": [ { "value": "BRAM", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_32bit_Address": [ { "value": "true", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ecctype": [ { "value": "No_ECC", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"ECC": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"EN_SLEEP_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"EN_DEEPSLEEP_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"EN_SHUTDOWN_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"EN_ECC_PIPE": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"RD_ADDR_CHNG_A": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"RD_ADDR_CHNG_B": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Use_Error_Injection_Pins": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Error_Injection_Type": [ { "value": "Single_Bit_Error_Injection", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Use_Byte_Write_Enable": [ { "value": "true", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Byte_Size": [ { "value": "8", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Algorithm": [ { "value": "Minimum_Area", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Primitive": [ { "value": "8kx2", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Assume_Synchronous_Clk": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Write_Width_A": [ { "value": "32", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Write_Depth_A": [ { "value": "8192", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Read_Width_A": [ { "value": "32", "value_src": "propagated", "resolve_type": "user", "usage": "all" } ],
|
||||
"Operating_Mode_A": [ { "value": "WRITE_FIRST", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_A": [ { "value": "Use_ENA_Pin", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Write_Width_B": [ { "value": "32", "value_src": "propagated", "resolve_type": "user", "usage": "all" } ],
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
},
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
},
|
||||
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|
||||
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|
||||
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|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../project_fix_dac.gen/sources_1/bd/system_top/ip/system_top_blk_mem_gen_0_0" } ],
|
||||
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|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"rstb_busy": [ { "direction": "out" } ]
|
||||
},
|
||||
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|
||||
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|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
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|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"BRAM_PORTA": {
|
||||
"vlnv": "xilinx.com:interface:bram:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:bram_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"MEM_ADDRESS_MODE": [ { "value": "BYTE_ADDRESS", "value_permission": "bd", "resolve_type": "user", "usage": "all" } ],
|
||||
"MEM_SIZE": [ { "value": "32768", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MEM_WIDTH": [ { "value": "32", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MEM_ECC": [ { "value": "NONE", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MASTER_TYPE": [ { "value": "BRAM_CTRL", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_LATENCY": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"ADDR": [ { "physical_name": "addra" } ],
|
||||
"CLK": [ { "physical_name": "clka" } ],
|
||||
"DIN": [ { "physical_name": "dina" } ],
|
||||
"DOUT": [ { "physical_name": "douta" } ],
|
||||
"EN": [ { "physical_name": "ena" } ],
|
||||
"RST": [ { "physical_name": "rsta" } ],
|
||||
"WE": [ { "physical_name": "wea" } ]
|
||||
}
|
||||
},
|
||||
"BRAM_PORTB": {
|
||||
"vlnv": "xilinx.com:interface:bram:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:bram_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"MEM_ADDRESS_MODE": [ { "value": "BYTE_ADDRESS", "value_permission": "bd", "resolve_type": "user", "usage": "all" } ],
|
||||
"MEM_SIZE": [ { "value": "8192", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MEM_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MEM_ECC": [ { "value": "NONE", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MASTER_TYPE": [ { "value": "BRAM_CTRL", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_LATENCY": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"ADDR": [ { "physical_name": "addrb" } ],
|
||||
"CLK": [ { "physical_name": "clkb" } ],
|
||||
"DIN": [ { "physical_name": "dinb" } ],
|
||||
"DOUT": [ { "physical_name": "doutb" } ],
|
||||
"EN": [ { "physical_name": "enb" } ],
|
||||
"RST": [ { "physical_name": "rstb" } ],
|
||||
"WE": [ { "physical_name": "web" } ]
|
||||
}
|
||||
}
|
||||
},
|
||||
"memory_maps": {
|
||||
"S_1": {
|
||||
"address_blocks": {
|
||||
"Mem0": {
|
||||
"base_address": "0",
|
||||
"range": "4096",
|
||||
"usage": "memory",
|
||||
"access": "read-write",
|
||||
"parameters": {
|
||||
"OFFSET_BASE_PARAM": [ { "value": "C_BASEADDR" } ],
|
||||
"OFFSET_HIGH_PARAM": [ { "value": "C_HIGHADDR" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+295
@@ -0,0 +1,295 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "system_top_blk_mem_gen_1_0",
|
||||
"cell_name": "blk_mem_gen_1",
|
||||
"component_reference": "xilinx.com:ip:blk_mem_gen:8.4",
|
||||
"ip_revision": "8",
|
||||
"gen_directory": "../../../../../../project_fix_dac.gen/sources_1/bd/system_top/ip/system_top_blk_mem_gen_1_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "system_top_blk_mem_gen_1_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Interface_Type": [ { "value": "Native", "resolve_type": "user", "usage": "all" } ],
|
||||
"AXI_Type": [ { "value": "AXI4_Full", "resolve_type": "user", "usage": "all" } ],
|
||||
"AXI_Slave_Type": [ { "value": "Memory_Slave", "resolve_type": "user", "usage": "all" } ],
|
||||
"Use_AXI_ID": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"AXI_ID_Width": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Memory_Type": [ { "value": "True_Dual_Port_RAM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PRIM_type_to_Implement": [ { "value": "BRAM", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_32bit_Address": [ { "value": "true", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ecctype": [ { "value": "No_ECC", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"ECC": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"EN_SLEEP_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"EN_DEEPSLEEP_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"EN_SHUTDOWN_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"EN_ECC_PIPE": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"RD_ADDR_CHNG_A": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"RD_ADDR_CHNG_B": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Use_Error_Injection_Pins": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Error_Injection_Type": [ { "value": "Single_Bit_Error_Injection", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Use_Byte_Write_Enable": [ { "value": "true", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Byte_Size": [ { "value": "8", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Algorithm": [ { "value": "Minimum_Area", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Primitive": [ { "value": "8kx2", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Assume_Synchronous_Clk": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Write_Width_A": [ { "value": "32", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Write_Depth_A": [ { "value": "8192", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Read_Width_A": [ { "value": "32", "value_src": "propagated", "resolve_type": "user", "usage": "all" } ],
|
||||
"Operating_Mode_A": [ { "value": "WRITE_FIRST", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_A": [ { "value": "Use_ENA_Pin", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Write_Width_B": [ { "value": "32", "value_src": "propagated", "resolve_type": "user", "usage": "all" } ],
|
||||
"Read_Width_B": [ { "value": "32", "value_src": "propagated", "resolve_type": "user", "usage": "all" } ],
|
||||
"Operating_Mode_B": [ { "value": "WRITE_FIRST", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_B": [ { "value": "Use_ENB_Pin", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Register_PortA_Output_of_Memory_Primitives": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Register_PortA_Output_of_Memory_Core": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Use_REGCEA_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Register_PortB_Output_of_Memory_Primitives": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Register_PortB_Output_of_Memory_Core": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Use_REGCEB_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"register_porta_input_of_softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"register_portb_output_of_softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Pipeline_Stages": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Load_Init_File": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Coe_File": [ { "value": "no_coe_file_loaded", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Fill_Remaining_Memory_Locations": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Remaining_Memory_Locations": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Use_RSTA_Pin": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Reset_Memory_Latch_A": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Reset_Priority_A": [ { "value": "CE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Output_Reset_Value_A": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Use_RSTB_Pin": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Reset_Memory_Latch_B": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Reset_Priority_B": [ { "value": "CE", "resolve_type": "user", "usage": "all" } ],
|
||||
"Output_Reset_Value_B": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Reset_Type": [ { "value": "SYNC", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Additional_Inputs_for_Power_Estimation": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Port_A_Clock": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Port_A_Write_Rate": [ { "value": "50", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Port_B_Clock": [ { "value": "100", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Port_B_Write_Rate": [ { "value": "50", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Port_A_Enable_Rate": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Port_B_Enable_Rate": [ { "value": "100", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Collision_Warnings": [ { "value": "ALL", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Disable_Collision_Warnings": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Disable_Out_of_Range_Warnings": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"use_bram_block": [ { "value": "BRAM_Controller", "resolve_type": "user", "usage": "all" } ],
|
||||
"MEM_FILE": [ { "value": "NONE", "value_src": "ip_propagated", "resolve_type": "user", "usage": "all" } ],
|
||||
"CTRL_ECC_ALGO": [ { "value": "NONE", "value_src": "propagated", "resolve_type": "user", "usage": "all" } ],
|
||||
"EN_SAFETY_CKT": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"READ_LATENCY_A": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"READ_LATENCY_B": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_FAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_XDEVICEFAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_ELABORATION_DIR": [ { "value": "./", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_INTERFACE_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_SLAVE_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_BRAM_BLOCK": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ENABLE_32BIT_ADDRESS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CTRL_ECC_ALGO": [ { "value": "NONE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_HAS_AXI_ID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_ID_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MEM_TYPE": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_BYTE_SIZE": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ALGORITHM": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PRIM_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_LOAD_INIT_FILE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INIT_FILE_NAME": [ { "value": "no_coe_file_loaded", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_INIT_FILE": [ { "value": "NONE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_USE_DEFAULT_DATA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DEFAULT_DATA": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_HAS_RSTA": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_RST_PRIORITY_A": [ { "value": "CE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_RSTRAM_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INITA_VAL": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_HAS_ENA": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_REGCEA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_BYTE_WEA": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WEA_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WRITE_MODE_A": [ { "value": "WRITE_FIRST", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_WRITE_WIDTH_A": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_READ_WIDTH_A": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WRITE_DEPTH_A": [ { "value": "8192", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_READ_DEPTH_A": [ { "value": "8192", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ADDRA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_RSTB": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_RST_PRIORITY_B": [ { "value": "CE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_RSTRAM_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INITB_VAL": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_HAS_ENB": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_REGCEB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_BYTE_WEB": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WEB_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WRITE_MODE_B": [ { "value": "WRITE_FIRST", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_WRITE_WIDTH_B": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_READ_WIDTH_B": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WRITE_DEPTH_B": [ { "value": "8192", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_READ_DEPTH_B": [ { "value": "8192", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ADDRB_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_MEM_OUTPUT_REGS_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_MEM_OUTPUT_REGS_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_MUX_OUTPUT_REGS_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_MUX_OUTPUT_REGS_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MUX_PIPELINE_STAGES": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_SOFTECC_INPUT_REGS_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_SOFTECC_OUTPUT_REGS_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_SOFTECC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_ECC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_EN_ECC_PIPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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|
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
}
|
||||
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|
||||
}
|
||||
+192
@@ -0,0 +1,192 @@
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
||||
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|
||||
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||||
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|
||||
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||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"CLK": [ { "physical_name": "CLK" } ]
|
||||
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|
||||
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|
||||
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|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0",
|
||||
"mode": "slave",
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"CE": [ { "physical_name": "CE" } ]
|
||||
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|
||||
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|
||||
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|
||||
"vlnv": "xilinx.com:signal:data:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:data_rtl:1.0",
|
||||
"mode": "slave",
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"vlnv": "xilinx.com:signal:data:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:data_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
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|
||||
"load_intf": {
|
||||
"vlnv": "xilinx.com:signal:data:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:data_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"l_intf": {
|
||||
"vlnv": "xilinx.com:signal:data:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:data_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"thresh0_intf": {
|
||||
"vlnv": "xilinx.com:signal:data:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:data_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
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|
||||
"q_intf": {
|
||||
"vlnv": "xilinx.com:signal:data:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:data_rtl:1.0",
|
||||
"mode": "master",
|
||||
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|
||||
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|
||||
},
|
||||
"port_maps": {
|
||||
"DATA": [ { "physical_name": "Q" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+192
@@ -0,0 +1,192 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
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|
||||
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|
||||
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|
||||
"component_reference": "xilinx.com:ip:c_counter_binary:12.0",
|
||||
"ip_revision": "19",
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"SWVERSION": [ { "value": "2024.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
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|
||||
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|
||||
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|
||||
"CE": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"Q": [ { "direction": "out", "size_left": "31", "size_right": "0" } ]
|
||||
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|
||||
"interfaces": {
|
||||
"sset_intf": {
|
||||
"vlnv": "xilinx.com:signal:data:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:data_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"clk_intf": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_data_clk_1", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "CLK" } ]
|
||||
}
|
||||
},
|
||||
"sclr_intf": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"ce_intf": {
|
||||
"vlnv": "xilinx.com:signal:clockenable:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CE": [ { "physical_name": "CE" } ]
|
||||
}
|
||||
},
|
||||
"sinit_intf": {
|
||||
"vlnv": "xilinx.com:signal:data:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:data_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"up_intf": {
|
||||
"vlnv": "xilinx.com:signal:data:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:data_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"load_intf": {
|
||||
"vlnv": "xilinx.com:signal:data:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:data_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"l_intf": {
|
||||
"vlnv": "xilinx.com:signal:data:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:data_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"thresh0_intf": {
|
||||
"vlnv": "xilinx.com:signal:data:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:data_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"q_intf": {
|
||||
"vlnv": "xilinx.com:signal:data:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:data_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"LAYERED_METADATA": [ { "value": "xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value data} bitwidth {attribs {resolve_type generated dependency bitwidth format long minimum {} maximum {}} value 32} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} integer {signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value false}}}} DATA_WIDTH 32}", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"DATA": [ { "physical_name": "Q" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+533
@@ -0,0 +1,533 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "system_top_fifo_generator_0_0",
|
||||
"cell_name": "fifo_generator_0",
|
||||
"component_reference": "xilinx.com:ip:fifo_generator:13.2",
|
||||
"ip_revision": "10",
|
||||
"gen_directory": "../../../../../../project_fix_dac.gen/sources_1/bd/system_top/ip/system_top_fifo_generator_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "system_top_fifo_generator_0_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Fifo_Implementation": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"synchronization_stages": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"synchronization_stages_axi": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"INTERFACE_TYPE": [ { "value": "AXI_STREAM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Performance_Options": [ { "value": "Standard_FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"asymmetric_port_width": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Data_Width": [ { "value": "18", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Input_Depth": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
|
||||
"Output_Data_Width": [ { "value": "18", "resolve_type": "user", "usage": "all" } ],
|
||||
"Output_Depth": [ { "value": "1024", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Use_Embedded_Registers": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Reset_Pin": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Enable_Reset_Synchronization": [ { "value": "true", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Reset_Type": [ { "value": "Asynchronous_Reset", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Flags_Reset_Value": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Use_Dout_Reset": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Dout_Reset_Value": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"dynamic_power_saving": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Almost_Full_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Almost_Empty_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Valid_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Valid_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Underflow_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Underflow_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Write_Acknowledge_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Write_Acknowledge_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Overflow_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Overflow_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"ecc_pipeline_reg": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Use_Extra_Logic": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Data_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Data_Count_Width": [ { "value": "10", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Write_Data_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Write_Data_Count_Width": [ { "value": "10", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Read_Data_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Read_Data_Count_Width": [ { "value": "10", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Disable_Timing_Violations": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Read_Clock_Frequency": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Write_Clock_Frequency": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Negate_Value": [ { "value": "1021", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value": [ { "value": "2", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Negate_Value": [ { "value": "3", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PROTOCOL": [ { "value": "AXI4", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Clock_Type_AXI": [ { "value": "Independent_Clock", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"HAS_ACLKEN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Clock_Enable_Type": [ { "value": "Slave_Interface_Clock_Enable", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "resolve_type": "user", "usage": "all" } ],
|
||||
"ID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"ADDRESS_WIDTH": [ { "value": "32", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"DATA_WIDTH": [ { "value": "64", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"AWUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"WUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"BUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"ARUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"RUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"TDATA_NUM_BYTES": [ { "value": "8", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TUSER_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Enable_TREADY": [ { "value": "true", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Enable_TLAST": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"HAS_TSTRB": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"TSTRB_WIDTH": [ { "value": "8", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_TKEEP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"TKEEP_WIDTH": [ { "value": "8", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"wach_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_wach": [ { "value": "Independent_Clocks_Distributed_RAM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_wach": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_wach": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_wach": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_wach": [ { "value": "15", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_wach": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_wach": [ { "value": "13", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"wdch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_wdch": [ { "value": "Independent_Clocks_Block_RAM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_wdch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_wdch": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_wdch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_wdch": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_wdch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_wdch": [ { "value": "1021", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"wrch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_wrch": [ { "value": "Independent_Clocks_Distributed_RAM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_wrch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_wrch": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_wrch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_wrch": [ { "value": "15", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_wrch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_wrch": [ { "value": "13", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"rach_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_rach": [ { "value": "Independent_Clocks_Distributed_RAM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_rach": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_rach": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_rach": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_rach": [ { "value": "15", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_rach": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_rach": [ { "value": "13", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"rdch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_rdch": [ { "value": "Independent_Clocks_Block_RAM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_rdch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_rdch": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_rdch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_rdch": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_rdch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_rdch": [ { "value": "1021", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"axis_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_axis": [ { "value": "Independent_Clocks_Block_RAM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_axis": [ { "value": "Data_FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_ECC_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Inject_Sbit_Error_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_axis": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Programmable_Full_Type_axis": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_axis": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_axis": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_axis": [ { "value": "1021", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Register_Slice_Mode_wach": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Register_Slice_Mode_wdch": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Register_Slice_Mode_wrch": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Register_Slice_Mode_rach": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Register_Slice_Mode_rdch": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
}
|
||||
},
|
||||
"slave_aresetn": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "s_aresetn" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+533
@@ -0,0 +1,533 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "system_top_fifo_generator_1_0",
|
||||
"cell_name": "fifo_generator_1",
|
||||
"component_reference": "xilinx.com:ip:fifo_generator:13.2",
|
||||
"ip_revision": "10",
|
||||
"gen_directory": "../../../../../../project_fix_dac.gen/sources_1/bd/system_top/ip/system_top_fifo_generator_1_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "system_top_fifo_generator_1_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Fifo_Implementation": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"synchronization_stages": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"synchronization_stages_axi": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"INTERFACE_TYPE": [ { "value": "AXI_STREAM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Performance_Options": [ { "value": "Standard_FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"asymmetric_port_width": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Data_Width": [ { "value": "18", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Input_Depth": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
|
||||
"Output_Data_Width": [ { "value": "18", "resolve_type": "user", "usage": "all" } ],
|
||||
"Output_Depth": [ { "value": "1024", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Use_Embedded_Registers": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Reset_Pin": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Enable_Reset_Synchronization": [ { "value": "true", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Reset_Type": [ { "value": "Asynchronous_Reset", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Flags_Reset_Value": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Use_Dout_Reset": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Dout_Reset_Value": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"dynamic_power_saving": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Almost_Full_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Almost_Empty_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Valid_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Valid_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Underflow_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Underflow_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Write_Acknowledge_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Write_Acknowledge_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Overflow_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Overflow_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"ecc_pipeline_reg": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Use_Extra_Logic": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Data_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Data_Count_Width": [ { "value": "10", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Write_Data_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Write_Data_Count_Width": [ { "value": "10", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Read_Data_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Read_Data_Count_Width": [ { "value": "10", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Disable_Timing_Violations": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Read_Clock_Frequency": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Write_Clock_Frequency": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Negate_Value": [ { "value": "1021", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value": [ { "value": "2", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Negate_Value": [ { "value": "3", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PROTOCOL": [ { "value": "AXI4", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Clock_Type_AXI": [ { "value": "Independent_Clock", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"HAS_ACLKEN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Clock_Enable_Type": [ { "value": "Slave_Interface_Clock_Enable", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "resolve_type": "user", "usage": "all" } ],
|
||||
"ID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"ADDRESS_WIDTH": [ { "value": "32", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"DATA_WIDTH": [ { "value": "64", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"AWUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"WUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"BUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"ARUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"RUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"TDATA_NUM_BYTES": [ { "value": "8", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TUSER_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Enable_TREADY": [ { "value": "true", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Enable_TLAST": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"HAS_TSTRB": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"TSTRB_WIDTH": [ { "value": "8", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_TKEEP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"TKEEP_WIDTH": [ { "value": "8", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"wach_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_wach": [ { "value": "Independent_Clocks_Distributed_RAM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_wach": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_wach": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_wach": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_wach": [ { "value": "15", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_wach": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_wach": [ { "value": "13", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"wdch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_wdch": [ { "value": "Independent_Clocks_Block_RAM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_wdch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_wdch": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_wdch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_wdch": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_wdch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_wdch": [ { "value": "1021", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"wrch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_wrch": [ { "value": "Independent_Clocks_Distributed_RAM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_wrch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_wrch": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_wrch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_wrch": [ { "value": "15", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_wrch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_wrch": [ { "value": "13", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"rach_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_rach": [ { "value": "Independent_Clocks_Distributed_RAM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_rach": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_rach": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_rach": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_rach": [ { "value": "15", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_rach": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_rach": [ { "value": "13", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"rdch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_rdch": [ { "value": "Independent_Clocks_Block_RAM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_rdch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_rdch": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_rdch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_rdch": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_rdch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_rdch": [ { "value": "1021", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"axis_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_axis": [ { "value": "Independent_Clocks_Block_RAM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_axis": [ { "value": "Data_FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_ECC_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Inject_Sbit_Error_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_axis": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Programmable_Full_Type_axis": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_axis": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_axis": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_axis": [ { "value": "1021", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Register_Slice_Mode_wach": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Register_Slice_Mode_wdch": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Register_Slice_Mode_wrch": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Register_Slice_Mode_rach": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
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||||
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||||
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},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "s_aclk" } ]
|
||||
}
|
||||
},
|
||||
"slave_aresetn": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "s_aresetn" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+533
@@ -0,0 +1,533 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "system_top_fifo_generator_2_0",
|
||||
"cell_name": "fifo_generator_2",
|
||||
"component_reference": "xilinx.com:ip:fifo_generator:13.2",
|
||||
"ip_revision": "10",
|
||||
"gen_directory": "../../../../../../project_fix_dac.gen/sources_1/bd/system_top/ip/system_top_fifo_generator_2_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "system_top_fifo_generator_2_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Fifo_Implementation": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"synchronization_stages": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"synchronization_stages_axi": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"INTERFACE_TYPE": [ { "value": "AXI_STREAM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Performance_Options": [ { "value": "Standard_FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"asymmetric_port_width": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Data_Width": [ { "value": "18", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Input_Depth": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
|
||||
"Output_Data_Width": [ { "value": "18", "resolve_type": "user", "usage": "all" } ],
|
||||
"Output_Depth": [ { "value": "1024", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Use_Embedded_Registers": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Reset_Pin": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Enable_Reset_Synchronization": [ { "value": "true", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Reset_Type": [ { "value": "Asynchronous_Reset", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Flags_Reset_Value": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Use_Dout_Reset": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Dout_Reset_Value": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"dynamic_power_saving": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Almost_Full_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Almost_Empty_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Valid_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Valid_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Underflow_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Underflow_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Write_Acknowledge_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Write_Acknowledge_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Overflow_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Overflow_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"ecc_pipeline_reg": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Use_Extra_Logic": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Data_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Data_Count_Width": [ { "value": "10", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Write_Data_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Write_Data_Count_Width": [ { "value": "10", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Read_Data_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Read_Data_Count_Width": [ { "value": "10", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Disable_Timing_Violations": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Read_Clock_Frequency": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Write_Clock_Frequency": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Negate_Value": [ { "value": "1021", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value": [ { "value": "2", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Negate_Value": [ { "value": "3", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PROTOCOL": [ { "value": "AXI4", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Clock_Type_AXI": [ { "value": "Independent_Clock", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"HAS_ACLKEN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Clock_Enable_Type": [ { "value": "Slave_Interface_Clock_Enable", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "resolve_type": "user", "usage": "all" } ],
|
||||
"ID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"ADDRESS_WIDTH": [ { "value": "32", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"DATA_WIDTH": [ { "value": "64", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"AWUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"WUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"BUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"ARUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"RUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"TDATA_NUM_BYTES": [ { "value": "8", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TUSER_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Enable_TREADY": [ { "value": "true", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Enable_TLAST": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"HAS_TSTRB": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"TSTRB_WIDTH": [ { "value": "8", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_TKEEP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"TKEEP_WIDTH": [ { "value": "8", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"wach_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_wach": [ { "value": "Independent_Clocks_Distributed_RAM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_wach": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_wach": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_wach": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_wach": [ { "value": "15", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_wach": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_wach": [ { "value": "13", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"wdch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_wdch": [ { "value": "Independent_Clocks_Block_RAM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_wdch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_wdch": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_wdch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_wdch": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_wdch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_wdch": [ { "value": "1021", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"wrch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_wrch": [ { "value": "Independent_Clocks_Distributed_RAM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_wrch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_wrch": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_wrch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_wrch": [ { "value": "15", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_wrch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_wrch": [ { "value": "13", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"rach_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_rach": [ { "value": "Independent_Clocks_Distributed_RAM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_rach": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_rach": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_rach": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_rach": [ { "value": "15", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_rach": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_rach": [ { "value": "13", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"rdch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_rdch": [ { "value": "Independent_Clocks_Block_RAM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_rdch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_rdch": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_rdch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_rdch": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_rdch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_rdch": [ { "value": "1021", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"axis_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_axis": [ { "value": "Independent_Clocks_Block_RAM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_axis": [ { "value": "Data_FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_ECC_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Inject_Sbit_Error_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_axis": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Programmable_Full_Type_axis": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_axis": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_axis": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_axis": [ { "value": "1021", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Register_Slice_Mode_wach": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Register_Slice_Mode_wdch": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Register_Slice_Mode_wrch": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
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||||
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|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "s_aclk" } ]
|
||||
}
|
||||
},
|
||||
"slave_aresetn": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "s_aresetn" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+203
@@ -0,0 +1,203 @@
|
||||
<?xml version='1.0' encoding='UTF-8'?>
|
||||
<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->
|
||||
<Project NoOfControllers="1" >
|
||||
<ModuleName>design_1_mig_7series_1_0</ModuleName>
|
||||
<dci_inouts_inputs>1</dci_inouts_inputs>
|
||||
<dci_inputs>1</dci_inputs>
|
||||
<Debug_En>OFF</Debug_En>
|
||||
<DataDepth_En>1024</DataDepth_En>
|
||||
<LowPower_En>ON</LowPower_En>
|
||||
<XADC_En>Enabled</XADC_En>
|
||||
<TargetFPGA>xc7z045-ffg900/-2</TargetFPGA>
|
||||
<Version>1.9</Version>
|
||||
<SystemClock>Differential</SystemClock>
|
||||
<ReferenceClock>Use System Clock</ReferenceClock>
|
||||
<SysResetPolarity>ACTIVE HIGH</SysResetPolarity>
|
||||
<BankSelectionFlag>FALSE</BankSelectionFlag>
|
||||
<InternalVref>0</InternalVref>
|
||||
<dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs>
|
||||
<dci_cascade>1</dci_cascade>
|
||||
<Controller number="0" >
|
||||
<MemoryDevice>DDR3_SDRAM/SODIMMs/MT8JTF12864HZ-1G6</MemoryDevice>
|
||||
<TimePeriod>1250</TimePeriod>
|
||||
<VccAuxIO>1.8V</VccAuxIO>
|
||||
<PHYRatio>4:1</PHYRatio>
|
||||
<InputClkFreq>200</InputClkFreq>
|
||||
<UIExtraClocks>1</UIExtraClocks>
|
||||
<MMCMClkOut0> 8.000</MMCMClkOut0>
|
||||
<MMCMClkOut1>1</MMCMClkOut1>
|
||||
<MMCMClkOut2>1</MMCMClkOut2>
|
||||
<MMCMClkOut3>1</MMCMClkOut3>
|
||||
<MMCMClkOut4>1</MMCMClkOut4>
|
||||
<DataWidth>64</DataWidth>
|
||||
<DeepMemory>1</DeepMemory>
|
||||
<DataMask>1</DataMask>
|
||||
<ECC>Disabled</ECC>
|
||||
<Ordering>Normal</Ordering>
|
||||
<CustomPart>FALSE</CustomPart>
|
||||
<NewPartName></NewPartName>
|
||||
<RowAddress>14</RowAddress>
|
||||
<ColAddress>10</ColAddress>
|
||||
<BankAddress>3</BankAddress>
|
||||
<MemoryVoltage>1.5V</MemoryVoltage>
|
||||
<UserMemoryAddressMap>BANK_ROW_COLUMN</UserMemoryAddressMap>
|
||||
<PinSelection>
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="E10" SLEW="FAST" name="ddr3_addr[0]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="D6" SLEW="FAST" name="ddr3_addr[10]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="B7" SLEW="FAST" name="ddr3_addr[11]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="H12" SLEW="FAST" name="ddr3_addr[12]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="A10" SLEW="FAST" name="ddr3_addr[13]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="B9" SLEW="FAST" name="ddr3_addr[1]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="E11" SLEW="FAST" name="ddr3_addr[2]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="A9" SLEW="FAST" name="ddr3_addr[3]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="D11" SLEW="FAST" name="ddr3_addr[4]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="B6" SLEW="FAST" name="ddr3_addr[5]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="F9" SLEW="FAST" name="ddr3_addr[6]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="E8" SLEW="FAST" name="ddr3_addr[7]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="B10" SLEW="FAST" name="ddr3_addr[8]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="J8" SLEW="FAST" name="ddr3_addr[9]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="F8" SLEW="FAST" name="ddr3_ba[0]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="H7" SLEW="FAST" name="ddr3_ba[1]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="A7" SLEW="FAST" name="ddr3_ba[2]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="E7" SLEW="FAST" name="ddr3_cas_n" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15" PADName="F10" SLEW="FAST" name="ddr3_ck_n[0]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15" PADName="G10" SLEW="FAST" name="ddr3_ck_p[0]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="D10" SLEW="FAST" name="ddr3_cke[0]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="J11" SLEW="FAST" name="ddr3_cs_n[0]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="J3" SLEW="FAST" name="ddr3_dm[0]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="F2" SLEW="FAST" name="ddr3_dm[1]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="E1" SLEW="FAST" name="ddr3_dm[2]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="C2" SLEW="FAST" name="ddr3_dm[3]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="L12" SLEW="FAST" name="ddr3_dm[4]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="G14" SLEW="FAST" name="ddr3_dm[5]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="C16" SLEW="FAST" name="ddr3_dm[6]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="C11" SLEW="FAST" name="ddr3_dm[7]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="L1" SLEW="FAST" name="ddr3_dq[0]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="H6" SLEW="FAST" name="ddr3_dq[10]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="H3" SLEW="FAST" name="ddr3_dq[11]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="G1" SLEW="FAST" name="ddr3_dq[12]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="H2" SLEW="FAST" name="ddr3_dq[13]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="G5" SLEW="FAST" name="ddr3_dq[14]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="G4" SLEW="FAST" name="ddr3_dq[15]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="E2" SLEW="FAST" name="ddr3_dq[16]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="E3" SLEW="FAST" name="ddr3_dq[17]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="D4" SLEW="FAST" name="ddr3_dq[18]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="E5" SLEW="FAST" name="ddr3_dq[19]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="L2" SLEW="FAST" name="ddr3_dq[1]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="F4" SLEW="FAST" name="ddr3_dq[20]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="F3" SLEW="FAST" name="ddr3_dq[21]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="D1" SLEW="FAST" name="ddr3_dq[22]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="D3" SLEW="FAST" name="ddr3_dq[23]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="A2" SLEW="FAST" name="ddr3_dq[24]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="B2" SLEW="FAST" name="ddr3_dq[25]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="B4" SLEW="FAST" name="ddr3_dq[26]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="B5" SLEW="FAST" name="ddr3_dq[27]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="A3" SLEW="FAST" name="ddr3_dq[28]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="B1" SLEW="FAST" name="ddr3_dq[29]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="K5" SLEW="FAST" name="ddr3_dq[2]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="C1" SLEW="FAST" name="ddr3_dq[30]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="C4" SLEW="FAST" name="ddr3_dq[31]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="K10" SLEW="FAST" name="ddr3_dq[32]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="L9" SLEW="FAST" name="ddr3_dq[33]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="K12" SLEW="FAST" name="ddr3_dq[34]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="J9" SLEW="FAST" name="ddr3_dq[35]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="K11" SLEW="FAST" name="ddr3_dq[36]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="L10" SLEW="FAST" name="ddr3_dq[37]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="J10" SLEW="FAST" name="ddr3_dq[38]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="L7" SLEW="FAST" name="ddr3_dq[39]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="J4" SLEW="FAST" name="ddr3_dq[3]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="F14" SLEW="FAST" name="ddr3_dq[40]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="F15" SLEW="FAST" name="ddr3_dq[41]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="F13" SLEW="FAST" name="ddr3_dq[42]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="G16" SLEW="FAST" name="ddr3_dq[43]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="G15" SLEW="FAST" name="ddr3_dq[44]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="E12" SLEW="FAST" name="ddr3_dq[45]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="D13" SLEW="FAST" name="ddr3_dq[46]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="E13" SLEW="FAST" name="ddr3_dq[47]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="D15" SLEW="FAST" name="ddr3_dq[48]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="E15" SLEW="FAST" name="ddr3_dq[49]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="K1" SLEW="FAST" name="ddr3_dq[4]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="D16" SLEW="FAST" name="ddr3_dq[50]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="E16" SLEW="FAST" name="ddr3_dq[51]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="C17" SLEW="FAST" name="ddr3_dq[52]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="B16" SLEW="FAST" name="ddr3_dq[53]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="D14" SLEW="FAST" name="ddr3_dq[54]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="B17" SLEW="FAST" name="ddr3_dq[55]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="B12" SLEW="FAST" name="ddr3_dq[56]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="C12" SLEW="FAST" name="ddr3_dq[57]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="A12" SLEW="FAST" name="ddr3_dq[58]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="A14" SLEW="FAST" name="ddr3_dq[59]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="L3" SLEW="FAST" name="ddr3_dq[5]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="A13" SLEW="FAST" name="ddr3_dq[60]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="B11" SLEW="FAST" name="ddr3_dq[61]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="C14" SLEW="FAST" name="ddr3_dq[62]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="B14" SLEW="FAST" name="ddr3_dq[63]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="J5" SLEW="FAST" name="ddr3_dq[6]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="K6" SLEW="FAST" name="ddr3_dq[7]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="G6" SLEW="FAST" name="ddr3_dq[8]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="H4" SLEW="FAST" name="ddr3_dq[9]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="K2" SLEW="FAST" name="ddr3_dqs_n[0]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="H1" SLEW="FAST" name="ddr3_dqs_n[1]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="D5" SLEW="FAST" name="ddr3_dqs_n[2]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="A4" SLEW="FAST" name="ddr3_dqs_n[3]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="K8" SLEW="FAST" name="ddr3_dqs_n[4]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="F12" SLEW="FAST" name="ddr3_dqs_n[5]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="E17" SLEW="FAST" name="ddr3_dqs_n[6]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="A15" SLEW="FAST" name="ddr3_dqs_n[7]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="K3" SLEW="FAST" name="ddr3_dqs_p[0]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="J1" SLEW="FAST" name="ddr3_dqs_p[1]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="E6" SLEW="FAST" name="ddr3_dqs_p[2]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="A5" SLEW="FAST" name="ddr3_dqs_p[3]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="L8" SLEW="FAST" name="ddr3_dqs_p[4]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="G12" SLEW="FAST" name="ddr3_dqs_p[5]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="F17" SLEW="FAST" name="ddr3_dqs_p[6]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="B15" SLEW="FAST" name="ddr3_dqs_p[7]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="G7" SLEW="FAST" name="ddr3_odt[0]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="H11" SLEW="FAST" name="ddr3_ras_n" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="LVCMOS15" PADName="G17" SLEW="FAST" name="ddr3_reset_n" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="F7" SLEW="FAST" name="ddr3_we_n" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="DONTCARE" IOSTANDARD="DIFF_SSTL15" PADName="G9" SLEW="" name="sys_clk_n" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="DONTCARE" IOSTANDARD="DIFF_SSTL15" PADName="H9" SLEW="" name="sys_clk_p" IN_TERM="" />
|
||||
</PinSelection>
|
||||
<System_Clock>
|
||||
<Pin PADName="H9/G9(CC_P/N)" Bank="34" name="sys_clk_p/n" />
|
||||
</System_Clock>
|
||||
<System_Control>
|
||||
<Pin PADName="No connect" Bank="Select Bank" name="sys_rst" />
|
||||
<Pin PADName="No connect" Bank="Select Bank" name="init_calib_complete" />
|
||||
<Pin PADName="No connect" Bank="Select Bank" name="tg_compare_error" />
|
||||
</System_Control>
|
||||
<TimingParameters>
|
||||
<Parameters twtr="7.5" trrd="6" trefi="7.8" tfaw="30" trtp="7.5" tcke="5" trfc="110" trp="13.125" tras="35" trcd="13.125" />
|
||||
</TimingParameters>
|
||||
<mrBurstLength name="Burst Length" >8 - Fixed</mrBurstLength>
|
||||
<mrBurstType name="Read Burst Type and Length" >Sequential</mrBurstType>
|
||||
<mrCasLatency name="CAS Latency" >6</mrCasLatency>
|
||||
<mrMode name="Mode" >Normal</mrMode>
|
||||
<mrDllReset name="DLL Reset" >No</mrDllReset>
|
||||
<mrPdMode name="DLL control for precharge PD" >Slow Exit</mrPdMode>
|
||||
<emrDllEnable name="DLL Enable" >Enable</emrDllEnable>
|
||||
<emrOutputDriveStrength name="Output Driver Impedance Control" >RZQ/7</emrOutputDriveStrength>
|
||||
<emrMirrorSelection name="Address Mirroring" >Disable</emrMirrorSelection>
|
||||
<emrCSSelection name="Controller Chip Select Pin" >Enable</emrCSSelection>
|
||||
<emrRTT name="RTT (nominal) - On Die Termination (ODT)" >RZQ/6</emrRTT>
|
||||
<emrPosted name="Additive Latency (AL)" >0</emrPosted>
|
||||
<emrOCD name="Write Leveling Enable" >Disabled</emrOCD>
|
||||
<emrDQS name="TDQS enable" >Enabled</emrDQS>
|
||||
<emrRDQS name="Qoff" >Output Buffer Enabled</emrRDQS>
|
||||
<mr2PartialArraySelfRefresh name="Partial-Array Self Refresh" >Full Array</mr2PartialArraySelfRefresh>
|
||||
<mr2CasWriteLatency name="CAS write latency" >5</mr2CasWriteLatency>
|
||||
<mr2AutoSelfRefresh name="Auto Self Refresh" >Enabled</mr2AutoSelfRefresh>
|
||||
<mr2SelfRefreshTempRange name="High Temparature Self Refresh Rate" >Normal</mr2SelfRefreshTempRange>
|
||||
<mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)" >Dynamic ODT off</mr2RTTWR>
|
||||
<PortInterface>AXI</PortInterface>
|
||||
<AXIParameters>
|
||||
<C0_C_RD_WR_ARB_ALGORITHM>RD_PRI_REG</C0_C_RD_WR_ARB_ALGORITHM>
|
||||
<C0_S_AXI_ADDR_WIDTH>32</C0_S_AXI_ADDR_WIDTH>
|
||||
<C0_S_AXI_DATA_WIDTH>512</C0_S_AXI_DATA_WIDTH>
|
||||
<C0_S_AXI_ID_WIDTH>2</C0_S_AXI_ID_WIDTH>
|
||||
<C0_S_AXI_SUPPORTS_NARROW_BURST>0</C0_S_AXI_SUPPORTS_NARROW_BURST>
|
||||
</AXIParameters>
|
||||
</Controller>
|
||||
|
||||
</Project>
|
||||
BIN
Binary file not shown.
+160
@@ -0,0 +1,160 @@
|
||||
//*****************************************************************************␍␍
|
||||
// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.␍␍
|
||||
//␍␍
|
||||
// This file contains confidential and proprietary information␍␍
|
||||
// of Xilinx, Inc. and is protected under U.S. and␍␍
|
||||
// international copyright and other intellectual property␍␍
|
||||
// laws.␍␍
|
||||
//␍␍
|
||||
// DISCLAIMER␍␍
|
||||
// This disclaimer is not a license and does not grant any␍␍
|
||||
// rights to the materials distributed herewith. Except as␍␍
|
||||
// otherwise provided in a valid license issued to you by␍␍
|
||||
// Xilinx, and to the maximum extent permitted by applicable␍␍
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND␍␍
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES␍␍
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING␍␍
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-␍␍
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and␍␍
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,␍␍
|
||||
// including negligence, or under any other theory of␍␍
|
||||
// liability) for any loss or damage of any kind or nature␍␍
|
||||
// related to, arising under or in connection with these␍␍
|
||||
// materials, including for any direct, or any indirect,␍␍
|
||||
// special, incidental, or consequential loss or damage␍␍
|
||||
// (including loss of data, profits, goodwill, or any type of␍␍
|
||||
// loss or damage suffered as a result of any action brought␍␍
|
||||
// by a third party) even if such damage or loss was␍␍
|
||||
// reasonably foreseeable or Xilinx had been advised of the␍␍
|
||||
// possibility of the same.␍␍
|
||||
//␍␍
|
||||
// CRITICAL APPLICATIONS␍␍
|
||||
// Xilinx products are not designed or intended to be fail-␍␍
|
||||
// safe, or for use in any application requiring fail-safe␍␍
|
||||
// performance, such as life-support or safety devices or␍␍
|
||||
// systems, Class III medical devices, nuclear facilities,␍␍
|
||||
// applications related to the deployment of airbags, or any␍␍
|
||||
// other applications that could lead to death, personal␍␍
|
||||
// injury, or severe property or environmental damage␍␍
|
||||
// (individually and collectively, "Critical␍␍
|
||||
// Applications"). Customer assumes the sole risk and␍␍
|
||||
// liability of any use of Xilinx products in Critical␍␍
|
||||
// Applications, subject only to applicable laws and␍␍
|
||||
// regulations governing limitations on product liability.␍␍
|
||||
//␍␍
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS␍␍
|
||||
// PART OF THIS FILE AT ALL TIMES.␍␍
|
||||
//␍␍
|
||||
//*****************************************************************************␍␍
|
||||
// ____ ____␍␍
|
||||
// / /\/ /␍␍
|
||||
// /___/ \ / Vendor : Xilinx␍␍
|
||||
// \ \ \/ Version : 4.2␍␍
|
||||
// \ \ Application : MIG␍␍
|
||||
// / / Filename : system_top_mig_7series_0_0.veo␍␍
|
||||
// /___/ /\ Date Last Modified : $Date: 2011/06/02 08:34:47 $␍␍
|
||||
// \ \ / \ Date Created : Tue Sept 21 2010␍␍
|
||||
// \___\/\___\␍␍
|
||||
//␍␍
|
||||
// Device : 7 Series␍␍
|
||||
// Design Name : DDR3 SDRAM␍␍
|
||||
// Purpose : Template file containing code that can be used as a model␍␍
|
||||
// for instantiating a CORE Generator module in a HDL design.␍␍
|
||||
// Revision History :␍␍
|
||||
//*****************************************************************************␍␍
|
||||
␍␍
|
||||
// The following must be inserted into your Verilog file for this␍␍
|
||||
// core to be instantiated. Change the instance name and port connections␍␍
|
||||
// (in parentheses) to your own signal names.␍␍
|
||||
␍␍
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG␍␍
|
||||
␍␍
|
||||
system_top_mig_7series_0_0 u_system_top_mig_7series_0_0 (␍␍
|
||||
␍␍
|
||||
// Memory interface ports␍␍
|
||||
.ddr3_addr (ddr3_addr), // output [13:0] ddr3_addr␍␍
|
||||
.ddr3_ba (ddr3_ba), // output [2:0] ddr3_ba␍␍
|
||||
.ddr3_cas_n (ddr3_cas_n), // output ddr3_cas_n␍␍
|
||||
.ddr3_ck_n (ddr3_ck_n), // output [0:0] ddr3_ck_n␍␍
|
||||
.ddr3_ck_p (ddr3_ck_p), // output [0:0] ddr3_ck_p␍␍
|
||||
.ddr3_cke (ddr3_cke), // output [0:0] ddr3_cke␍␍
|
||||
.ddr3_ras_n (ddr3_ras_n), // output ddr3_ras_n␍␍
|
||||
.ddr3_reset_n (ddr3_reset_n), // output ddr3_reset_n␍␍
|
||||
.ddr3_we_n (ddr3_we_n), // output ddr3_we_n␍␍
|
||||
.ddr3_dq (ddr3_dq), // inout [63:0] ddr3_dq␍␍
|
||||
.ddr3_dqs_n (ddr3_dqs_n), // inout [7:0] ddr3_dqs_n␍␍
|
||||
.ddr3_dqs_p (ddr3_dqs_p), // inout [7:0] ddr3_dqs_p␍␍
|
||||
.init_calib_complete (init_calib_complete), // output init_calib_complete␍␍
|
||||
␍␍
|
||||
.ddr3_cs_n (ddr3_cs_n), // output [0:0] ddr3_cs_n␍␍
|
||||
.ddr3_dm (ddr3_dm), // output [7:0] ddr3_dm␍␍
|
||||
.ddr3_odt (ddr3_odt), // output [0:0] ddr3_odt␍␍
|
||||
// Application interface ports␍␍
|
||||
.ui_clk (ui_clk), // output ui_clk␍␍
|
||||
.ui_clk_sync_rst (ui_clk_sync_rst), // output ui_clk_sync_rst␍␍
|
||||
.ui_addn_clk_0 (ui_addn_clk_0), // output ui_addn_clk_0␍␍
|
||||
.ui_addn_clk_1 (ui_addn_clk_1), // output ui_addn_clk_1␍␍
|
||||
.ui_addn_clk_2 (ui_addn_clk_2), // output ui_addn_clk_2␍␍
|
||||
.ui_addn_clk_3 (ui_addn_clk_3), // output ui_addn_clk_3␍␍
|
||||
.ui_addn_clk_4 (ui_addn_clk_4), // output ui_addn_clk_4␍␍
|
||||
.mmcm_locked (mmcm_locked), // output mmcm_locked␍␍
|
||||
.aresetn (aresetn), // input aresetn␍␍
|
||||
.app_sr_active (app_sr_active), // output app_sr_active␍␍
|
||||
.app_ref_ack (app_ref_ack), // output app_ref_ack␍␍
|
||||
.app_zq_ack (app_zq_ack), // output app_zq_ack␍␍
|
||||
// Slave Interface Write Address Ports␍␍
|
||||
.s_axi_awid (s_axi_awid), // input [1:0] s_axi_awid␍␍
|
||||
.s_axi_awaddr (s_axi_awaddr), // input [31:0] s_axi_awaddr␍␍
|
||||
.s_axi_awlen (s_axi_awlen), // input [7:0] s_axi_awlen␍␍
|
||||
.s_axi_awsize (s_axi_awsize), // input [2:0] s_axi_awsize␍␍
|
||||
.s_axi_awburst (s_axi_awburst), // input [1:0] s_axi_awburst␍␍
|
||||
.s_axi_awlock (s_axi_awlock), // input [0:0] s_axi_awlock␍␍
|
||||
.s_axi_awcache (s_axi_awcache), // input [3:0] s_axi_awcache␍␍
|
||||
.s_axi_awprot (s_axi_awprot), // input [2:0] s_axi_awprot␍␍
|
||||
.s_axi_awqos (s_axi_awqos), // input [3:0] s_axi_awqos␍␍
|
||||
.s_axi_awvalid (s_axi_awvalid), // input s_axi_awvalid␍␍
|
||||
.s_axi_awready (s_axi_awready), // output s_axi_awready␍␍
|
||||
// Slave Interface Write Data Ports␍␍
|
||||
.s_axi_wdata (s_axi_wdata), // input [511:0] s_axi_wdata␍␍
|
||||
.s_axi_wstrb (s_axi_wstrb), // input [63:0] s_axi_wstrb␍␍
|
||||
.s_axi_wlast (s_axi_wlast), // input s_axi_wlast␍␍
|
||||
.s_axi_wvalid (s_axi_wvalid), // input s_axi_wvalid␍␍
|
||||
.s_axi_wready (s_axi_wready), // output s_axi_wready␍␍
|
||||
// Slave Interface Write Response Ports␍␍
|
||||
.s_axi_bid (s_axi_bid), // output [1:0] s_axi_bid␍␍
|
||||
.s_axi_bresp (s_axi_bresp), // output [1:0] s_axi_bresp␍␍
|
||||
.s_axi_bvalid (s_axi_bvalid), // output s_axi_bvalid␍␍
|
||||
.s_axi_bready (s_axi_bready), // input s_axi_bready␍␍
|
||||
// Slave Interface Read Address Ports␍␍
|
||||
.s_axi_arid (s_axi_arid), // input [1:0] s_axi_arid␍␍
|
||||
.s_axi_araddr (s_axi_araddr), // input [31:0] s_axi_araddr␍␍
|
||||
.s_axi_arlen (s_axi_arlen), // input [7:0] s_axi_arlen␍␍
|
||||
.s_axi_arsize (s_axi_arsize), // input [2:0] s_axi_arsize␍␍
|
||||
.s_axi_arburst (s_axi_arburst), // input [1:0] s_axi_arburst␍␍
|
||||
.s_axi_arlock (s_axi_arlock), // input [0:0] s_axi_arlock␍␍
|
||||
.s_axi_arcache (s_axi_arcache), // input [3:0] s_axi_arcache␍␍
|
||||
.s_axi_arprot (s_axi_arprot), // input [2:0] s_axi_arprot␍␍
|
||||
.s_axi_arqos (s_axi_arqos), // input [3:0] s_axi_arqos␍␍
|
||||
.s_axi_arvalid (s_axi_arvalid), // input s_axi_arvalid␍␍
|
||||
.s_axi_arready (s_axi_arready), // output s_axi_arready␍␍
|
||||
// Slave Interface Read Data Ports␍␍
|
||||
.s_axi_rid (s_axi_rid), // output [1:0] s_axi_rid␍␍
|
||||
.s_axi_rdata (s_axi_rdata), // output [511:0] s_axi_rdata␍␍
|
||||
.s_axi_rresp (s_axi_rresp), // output [1:0] s_axi_rresp␍␍
|
||||
.s_axi_rlast (s_axi_rlast), // output s_axi_rlast␍␍
|
||||
.s_axi_rvalid (s_axi_rvalid), // output s_axi_rvalid␍␍
|
||||
.s_axi_rready (s_axi_rready), // input s_axi_rready␍␍
|
||||
// System Clock Ports␍␍
|
||||
.sys_clk_p (sys_clk_p), // input sys_clk_p␍␍
|
||||
.sys_clk_n (sys_clk_n), // input sys_clk_n␍␍
|
||||
.sys_rst (sys_rst) // input sys_rst␍␍
|
||||
);␍␍
|
||||
␍␍
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------␍␍
|
||||
␍␍
|
||||
// You must compile the wrapper file system_top_mig_7series_0_0.v when simulating␍␍
|
||||
// the core, system_top_mig_7series_0_0. When compiling the wrapper file, be sure to␍␍
|
||||
// reference the XilinxCoreLib Verilog simulation library. For detailed␍␍
|
||||
// instructions, please refer to the "CORE Generator Help".␍␍
|
||||
␍␍
|
||||
␍
|
||||
+1664
File diff suppressed because it is too large
Load Diff
+133
@@ -0,0 +1,133 @@
|
||||
␍
|
||||
␍
|
||||
Vivado Project Options:␍
|
||||
Target Device : xc7z045-ffg900␍
|
||||
Speed Grade : -2␍
|
||||
HDL : verilog␍
|
||||
Synthesis Tool : VIVADO␍
|
||||
␍
|
||||
MIG Output Options:␍
|
||||
Module Name : system_top_mig_7series_0_0␍
|
||||
No of Controllers : 1␍
|
||||
Selected Compatible Device(s) : --␍
|
||||
␍
|
||||
FPGA Options:␍
|
||||
System Clock Type : Differential␍
|
||||
Reference Clock Type : Use System Clock␍
|
||||
Debug Port : OFF␍
|
||||
Internal Vref : disabled␍
|
||||
IO Power Reduction : ON␍
|
||||
XADC instantiation in MIG : Enabled␍
|
||||
␍
|
||||
Extended FPGA Options:␍
|
||||
DCI for DQ,DQS/DQS#,DM : enabled␍
|
||||
Internal Termination (HR Banks) : 50 Ohms␍
|
||||
␍
|
||||
␍
|
||||
/*******************************************************/␍
|
||||
␍
|
||||
/* Controller 0 */␍
|
||||
␍
|
||||
/*******************************************************/␍
|
||||
␍
|
||||
Controller Options :␍
|
||||
␍
|
||||
Memory : DDR3_SDRAM␍
|
||||
␍
|
||||
Interface : AXI␍
|
||||
␍
|
||||
Design Clock Frequency : 1250 ps ( 0.00 MHz)␍
|
||||
␍
|
||||
Phy to Controller Clock Ratio : 4:1␍
|
||||
␍
|
||||
Input Clock Period : 5000 ps␍
|
||||
␍
|
||||
CLKFBOUT_MULT (PLL) : 8␍
|
||||
␍
|
||||
DIVCLK_DIVIDE (PLL) : 1␍
|
||||
␍
|
||||
VCC_AUX IO : 1.8V␍
|
||||
␍
|
||||
Memory Type : SODIMMs␍
|
||||
␍
|
||||
Memory Part : MT8JTF12864HZ-1G6␍
|
||||
␍
|
||||
Equivalent Part(s) : --␍
|
||||
␍
|
||||
Data Width : 64␍
|
||||
␍
|
||||
ECC : Disabled␍
|
||||
␍
|
||||
Data Mask : enabled␍
|
||||
␍
|
||||
ORDERING : Normal␍
|
||||
␍
|
||||
␍
|
||||
␍
|
||||
AXI Parameters :␍
|
||||
␍
|
||||
Data Width : 512␍
|
||||
␍
|
||||
Arbitration Scheme : RD_PRI_REG␍
|
||||
␍
|
||||
Narrow Burst Support : 0␍
|
||||
␍
|
||||
ID Width : 2␍
|
||||
␍
|
||||
␍
|
||||
␍
|
||||
Memory Options:␍
|
||||
␍
|
||||
Burst Length (MR0[1:0]) : 8 - Fixed␍
|
||||
␍
|
||||
Read Burst Type (MR0[3]) : Sequential␍
|
||||
␍
|
||||
CAS Latency (MR0[6:4]) : 11␍
|
||||
␍
|
||||
Output Drive Strength (MR1[5,1]) : RZQ/7␍
|
||||
␍
|
||||
Controller CS option : Enable␍
|
||||
␍
|
||||
Rtt_NOM - ODT (MR1[9,6,2]) : RZQ/6␍
|
||||
␍
|
||||
Rtt_WR - Dynamic ODT (MR2[10:9]) : Dynamic ODT off␍
|
||||
␍
|
||||
Memory Address Mapping : BANK_ROW_COLUMN␍
|
||||
␍
|
||||
␍
|
||||
␍
|
||||
␍
|
||||
Bank Selections:␍
|
||||
Bank: 33␍
|
||||
Byte Group T0: DQ[0-7]␍
|
||||
Byte Group T1: DQ[8-15]␍
|
||||
Byte Group T2: DQ[16-23]␍
|
||||
Byte Group T3: DQ[24-31]␍
|
||||
Bank: 34␍
|
||||
Byte Group T0: Address/Ctrl-2␍
|
||||
Byte Group T1: Address/Ctrl-0␍
|
||||
Byte Group T2: Address/Ctrl-1␍
|
||||
Byte Group T3: DQ[32-39]␍
|
||||
Bank: 35␍
|
||||
Byte Group T1: DQ[40-47]␍
|
||||
Byte Group T2: DQ[48-55]␍
|
||||
Byte Group T3: DQ[56-63]␍
|
||||
␍
|
||||
␍
|
||||
System_Clock: ␍
|
||||
SignalName: sys_clk_p/n␍
|
||||
PadLocation: H9/G9(CC_P/N) Bank: 34␍
|
||||
␍
|
||||
System_Control: ␍
|
||||
SignalName: sys_rst␍
|
||||
PadLocation: No connect Bank: Select Bank␍
|
||||
SignalName: init_calib_complete␍
|
||||
PadLocation: No connect Bank: Select Bank␍
|
||||
SignalName: tg_compare_error␍
|
||||
PadLocation: No connect Bank: Select Bank␍
|
||||
␍
|
||||
␍
|
||||
␍
|
||||
␍
|
||||
␍
|
||||
␍
|
||||
+12
@@ -0,0 +1,12 @@
|
||||
This file includes the information about the PHY layer support:
|
||||
|
||||
- Folder "<component name>/user_design/rtl/phy" includes the PHY layer
|
||||
RTL modules.
|
||||
- The top-level PHY module to be instantiated is ddr_phy_top (ddr_phy_top.v)
|
||||
- PHY modules can be used in any environment by taking the RTL modules
|
||||
listed in "phy" folder and PHY layer needs to be connected to
|
||||
the memory controller.
|
||||
- Refer to User Guide (UG586) section "Physical Layer Interface (Non-Memory
|
||||
Controller Design)" for more details on PHY interface signaling,
|
||||
parameter(s) and timing information.
|
||||
|
||||
+28
@@ -0,0 +1,28 @@
|
||||
##################################################################################################␍
|
||||
## ␍
|
||||
## Xilinx, Inc. 2010 www.xilinx.com ␍
|
||||
## Tue Apr 23 16:23:00 2024
|
||||
␍
|
||||
## Generated by MIG Version 4.2␍
|
||||
## ␍
|
||||
##################################################################################################␍
|
||||
## File name : example_top.xdc␍
|
||||
## Details : Constraints file␍
|
||||
## FPGA Family: ZYNQ␍
|
||||
## FPGA Part: XC7Z045-FFG900␍
|
||||
## Speedgrade: -2␍
|
||||
## Design Entry: VERILOG␍
|
||||
## Frequency: 800 MHz␍
|
||||
## Time Period: 1250 ps␍
|
||||
##################################################################################################␍
|
||||
␍
|
||||
##################################################################################################␍
|
||||
## Controller 0␍
|
||||
## Memory Device: DDR3_SDRAM->SODIMMs->MT8JTF12864HZ-1G6␍
|
||||
## Data Width: 64␍
|
||||
## Time Period: 1250␍
|
||||
## Data Mask: 1␍
|
||||
##################################################################################################␍
|
||||
############## NET - IOSTANDARD ##################␍
|
||||
␍
|
||||
␍
|
||||
+18
@@ -0,0 +1,18 @@
|
||||
Files in PAR folder :␍
|
||||
␍
|
||||
* "example_top.xdc" file is the constraint file for the design. This is used␍
|
||||
by Vivado. It has clock constraints, location constraints, IO standards ␍
|
||||
and false path/SLICE constraints if any.␍
|
||||
␍
|
||||
* LTX/probe file is required when programming BIT file to FPGA as it contains␍
|
||||
the information of debug signals like signal name and position with respect␍
|
||||
to ILA/VIO core. The probe file (debug_nets.ltx) is auto generated by ␍
|
||||
vivado tool and is found in <project_name>.runs/impl_1/debug_nets.ltx␍
|
||||
␍
|
||||
compatible_ucf folder:␍
|
||||
␍
|
||||
* MIG outputs this folder only when Pin Compatible FPGAs are checked in GUI␍
|
||||
(Pin Compatible FPGAs page in GUI). It generates the XDC files for all␍
|
||||
the Compatible FPGAs selected in GUI. If you want to switch to any of the␍
|
||||
Compatible FPGAs follow the steps mentioned below.␍
|
||||
␍
|
||||
+735
@@ -0,0 +1,735 @@
|
||||
//*****************************************************************************␍␍
|
||||
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.␍␍
|
||||
//␍␍
|
||||
// This file contains confidential and proprietary information␍␍
|
||||
// of Xilinx, Inc. and is protected under U.S. and␍␍
|
||||
// international copyright and other intellectual property␍␍
|
||||
// laws.␍␍
|
||||
//␍␍
|
||||
// DISCLAIMER␍␍
|
||||
// This disclaimer is not a license and does not grant any␍␍
|
||||
// rights to the materials distributed herewith. Except as␍␍
|
||||
// otherwise provided in a valid license issued to you by␍␍
|
||||
// Xilinx, and to the maximum extent permitted by applicable␍␍
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND␍␍
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES␍␍
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING␍␍
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-␍␍
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and␍␍
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,␍␍
|
||||
// including negligence, or under any other theory of␍␍
|
||||
// liability) for any loss or damage of any kind or nature␍␍
|
||||
// related to, arising under or in connection with these␍␍
|
||||
// materials, including for any direct, or any indirect,␍␍
|
||||
// special, incidental, or consequential loss or damage␍␍
|
||||
// (including loss of data, profits, goodwill, or any type of␍␍
|
||||
// loss or damage suffered as a result of any action brought␍␍
|
||||
// by a third party) even if such damage or loss was␍␍
|
||||
// reasonably foreseeable or Xilinx had been advised of the␍␍
|
||||
// possibility of the same.␍␍
|
||||
//␍␍
|
||||
// CRITICAL APPLICATIONS␍␍
|
||||
// Xilinx products are not designed or intended to be fail-␍␍
|
||||
// safe, or for use in any application requiring fail-safe␍␍
|
||||
// performance, such as life-support or safety devices or␍␍
|
||||
// systems, Class III medical devices, nuclear facilities,␍␍
|
||||
// applications related to the deployment of airbags, or any␍␍
|
||||
// other applications that could lead to death, personal␍␍
|
||||
// injury, or severe property or environmental damage␍␍
|
||||
// (individually and collectively, "Critical␍␍
|
||||
// Applications"). Customer assumes the sole risk and␍␍
|
||||
// liability of any use of Xilinx products in Critical␍␍
|
||||
// Applications, subject only to applicable laws and␍␍
|
||||
// regulations governing limitations on product liability.␍␍
|
||||
//␍␍
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS␍␍
|
||||
// PART OF THIS FILE AT ALL TIMES.␍␍
|
||||
//␍␍
|
||||
//*****************************************************************************␍␍
|
||||
// ____ ____␍␍
|
||||
// / /\/ /␍␍
|
||||
// /___/ \ / Vendor : Xilinx␍␍
|
||||
// \ \ \/ Version : 4.2␍␍
|
||||
// \ \ Application : MIG␍␍
|
||||
// / / Filename : example_top.v␍␍
|
||||
// /___/ /\ Date Last Modified : $Date: 2011/06/02 08:35:03 $␍␍
|
||||
// \ \ / \ Date Created : Tue Sept 21 2010␍␍
|
||||
// \___\/\___\␍␍
|
||||
//␍␍
|
||||
// Device : 7 Series␍␍
|
||||
// Design Name : DDR3 SDRAM␍␍
|
||||
// Purpose :␍␍
|
||||
// Top-level module. This module serves as an example,␍␍
|
||||
// and allows the user to synthesize a self-contained design,␍␍
|
||||
// which they can be used to test their hardware.␍␍
|
||||
// In addition to the memory controller, the module instantiates:␍␍
|
||||
// 1. Synthesizable testbench - used to model user's backend logic␍␍
|
||||
// and generate different traffic patterns␍␍
|
||||
// Reference :␍␍
|
||||
// Revision History :␍␍
|
||||
//*****************************************************************************␍␍
|
||||
␍␍
|
||||
//`define SKIP_CALIB␍␍
|
||||
`timescale 1ps/1ps␍␍
|
||||
␍␍
|
||||
module example_top #␍␍
|
||||
(␍␍
|
||||
␍␍
|
||||
//***************************************************************************␍␍
|
||||
// Traffic Gen related parameters␍␍
|
||||
//***************************************************************************␍␍
|
||||
parameter BEGIN_ADDRESS = 32'h00000000,␍␍
|
||||
parameter END_ADDRESS = 32'h00ffffff,␍␍
|
||||
parameter PRBS_EADDR_MASK_POS = 32'hff000000,␍␍
|
||||
parameter ENFORCE_RD_WR = 0,␍␍
|
||||
parameter ENFORCE_RD_WR_CMD = 8'h11,␍␍
|
||||
parameter ENFORCE_RD_WR_PATTERN = 3'b000,␍␍
|
||||
parameter C_EN_WRAP_TRANS = 0,␍␍
|
||||
parameter C_AXI_NBURST_TEST = 0,␍␍
|
||||
␍␍
|
||||
//***************************************************************************␍␍
|
||||
// The following parameters refer to width of various ports␍␍
|
||||
//***************************************************************************␍␍
|
||||
parameter CK_WIDTH = 1,␍␍
|
||||
// # of CK/CK# outputs to memory.␍␍
|
||||
parameter nCS_PER_RANK = 1,␍␍
|
||||
// # of unique CS outputs per rank for phy␍␍
|
||||
parameter CKE_WIDTH = 1,␍␍
|
||||
// # of CKE outputs to memory.␍␍
|
||||
parameter DM_WIDTH = 8,␍␍
|
||||
// # of DM (data mask)␍␍
|
||||
parameter ODT_WIDTH = 1,␍␍
|
||||
// # of ODT outputs to memory.␍␍
|
||||
parameter BANK_WIDTH = 3,␍␍
|
||||
// # of memory Bank Address bits.␍␍
|
||||
parameter COL_WIDTH = 10,␍␍
|
||||
// # of memory Column Address bits.␍␍
|
||||
parameter CS_WIDTH = 1,␍␍
|
||||
// # of unique CS outputs to memory.␍␍
|
||||
parameter DQ_WIDTH = 64,␍␍
|
||||
// # of DQ (data)␍␍
|
||||
parameter DQS_WIDTH = 8,␍␍
|
||||
parameter DQS_CNT_WIDTH = 3,␍␍
|
||||
// = ceil(log2(DQS_WIDTH))␍␍
|
||||
parameter DRAM_WIDTH = 8,␍␍
|
||||
// # of DQ per DQS␍␍
|
||||
parameter ECC = "OFF",␍␍
|
||||
parameter ECC_TEST = "OFF",␍␍
|
||||
//parameter nBANK_MACHS = 4,␍␍
|
||||
parameter nBANK_MACHS = 4,␍␍
|
||||
parameter RANKS = 1,␍␍
|
||||
// # of Ranks.␍␍
|
||||
parameter ROW_WIDTH = 14,␍␍
|
||||
// # of memory Row Address bits.␍␍
|
||||
parameter ADDR_WIDTH = 28,␍␍
|
||||
// # = RANK_WIDTH + BANK_WIDTH␍␍
|
||||
// + ROW_WIDTH + COL_WIDTH;␍␍
|
||||
// Chip Select is always tied to low for␍␍
|
||||
// single rank devices␍␍
|
||||
␍␍
|
||||
//***************************************************************************␍␍
|
||||
// The following parameters are mode register settings␍␍
|
||||
//***************************************************************************␍␍
|
||||
parameter BURST_MODE = "8",␍␍
|
||||
// DDR3 SDRAM:␍␍
|
||||
// Burst Length (Mode Register 0).␍␍
|
||||
// # = "8", "4", "OTF".␍␍
|
||||
// DDR2 SDRAM:␍␍
|
||||
// Burst Length (Mode Register).␍␍
|
||||
// # = "8", "4".␍␍
|
||||
␍␍
|
||||
␍␍
|
||||
//***************************************************************************␍␍
|
||||
// The following parameters are multiplier and divisor factors for PLLE2.␍␍
|
||||
// Based on the selected design frequency these parameters vary.␍␍
|
||||
//***************************************************************************␍␍
|
||||
parameter CLKIN_PERIOD = 5000,␍␍
|
||||
// Input Clock Period␍␍
|
||||
parameter CLKFBOUT_MULT = 8,␍␍
|
||||
// write PLL VCO multiplier␍␍
|
||||
parameter DIVCLK_DIVIDE = 1,␍␍
|
||||
// write PLL VCO divisor␍␍
|
||||
parameter CLKOUT0_PHASE = 337.5,␍␍
|
||||
// Phase for PLL output clock (CLKOUT0)␍␍
|
||||
parameter CLKOUT0_DIVIDE = 2,␍␍
|
||||
// VCO output divisor for PLL output clock (CLKOUT0)␍␍
|
||||
parameter CLKOUT1_DIVIDE = 2,␍␍
|
||||
// VCO output divisor for PLL output clock (CLKOUT1)␍␍
|
||||
parameter CLKOUT2_DIVIDE = 32,␍␍
|
||||
// VCO output divisor for PLL output clock (CLKOUT2)␍␍
|
||||
parameter CLKOUT3_DIVIDE = 8,␍␍
|
||||
// VCO output divisor for PLL output clock (CLKOUT3)␍␍
|
||||
parameter MMCM_VCO = 800,␍␍
|
||||
// Max Freq (MHz) of MMCM VCO␍␍
|
||||
parameter MMCM_MULT_F = 4,␍␍
|
||||
// write MMCM VCO multiplier␍␍
|
||||
parameter MMCM_DIVCLK_DIVIDE = 1,␍␍
|
||||
// write MMCM VCO divisor␍␍
|
||||
parameter MMCM_CLKOUT0_EN = "TRUE",␍␍
|
||||
// "TRUE" - MMCM output clock (CLKOUT0) is enabled␍␍
|
||||
// "FALSE" - MMCM output clock (CLKOUT0) is disabled␍␍
|
||||
parameter MMCM_CLKOUT1_EN = "FALSE",␍␍
|
||||
// "TRUE" - MMCM output clock (CLKOUT1) is enabled␍␍
|
||||
// "FALSE" - MMCM output clock (CLKOUT1) is disabled␍␍
|
||||
parameter MMCM_CLKOUT2_EN = "FALSE",␍␍
|
||||
// "TRUE" - MMCM output clock (CLKOUT2) is enabled␍␍
|
||||
// "FALSE" - MMCM output clock (CLKOUT2) is disabled␍␍
|
||||
parameter MMCM_CLKOUT3_EN = "FALSE",␍␍
|
||||
// "TRUE" - MMCM output clock (CLKOUT3) is enabled␍␍
|
||||
// "FALSE" - MMCM output clock (CLKOUT3) is disabled␍␍
|
||||
parameter MMCM_CLKOUT4_EN = "FALSE",␍␍
|
||||
// "TRUE" - MMCM output clock (CLKOUT4) is enabled␍␍
|
||||
// "FALSE" - MMCM output clock (CLKOUT4) is disabled␍␍
|
||||
parameter MMCM_CLKOUT0_DIVIDE = 8,␍␍
|
||||
// VCO output divisor for MMCM output clock (CLKOUT0)␍␍
|
||||
parameter MMCM_CLKOUT1_DIVIDE = 1,␍␍
|
||||
// VCO output divisor for MMCM output clock (CLKOUT1)␍␍
|
||||
parameter MMCM_CLKOUT2_DIVIDE = 1,␍␍
|
||||
// VCO output divisor for MMCM output clock (CLKOUT2)␍␍
|
||||
parameter MMCM_CLKOUT3_DIVIDE = 1,␍␍
|
||||
// VCO output divisor for MMCM output clock (CLKOUT3)␍␍
|
||||
parameter MMCM_CLKOUT4_DIVIDE = 1,␍␍
|
||||
// VCO output divisor for MMCM output clock (CLKOUT4)␍␍
|
||||
␍␍
|
||||
␍␍
|
||||
//***************************************************************************␍␍
|
||||
// Simulation parameters␍␍
|
||||
//***************************************************************************␍␍
|
||||
parameter SIMULATION = "FALSE",␍␍
|
||||
// Should be TRUE during design simulations and␍␍
|
||||
// FALSE during implementations␍␍
|
||||
␍␍
|
||||
//***************************************************************************␍␍
|
||||
// IODELAY and PHY related parameters␍␍
|
||||
//***************************************************************************␍␍
|
||||
parameter TCQ = 100,␍␍
|
||||
␍␍
|
||||
parameter DRAM_TYPE = "DDR3",␍␍
|
||||
␍␍
|
||||
␍␍
|
||||
//***************************************************************************␍␍
|
||||
// System clock frequency parameters␍␍
|
||||
//***************************************************************************␍␍
|
||||
parameter nCK_PER_CLK = 4,␍␍
|
||||
// # of memory CKs per fabric CLK␍␍
|
||||
␍␍
|
||||
␍␍
|
||||
//***************************************************************************␍␍
|
||||
// AXI4 Shim parameters␍␍
|
||||
//***************************************************************************␍␍
|
||||
parameter C_S_AXI_ID_WIDTH = 2,␍␍
|
||||
// Width of all master and slave ID signals.␍␍
|
||||
// # = >= 1.␍␍
|
||||
parameter C_S_AXI_ADDR_WIDTH = 32,␍␍
|
||||
// Width of S_AXI_AWADDR, S_AXI_ARADDR, M_AXI_AWADDR and␍␍
|
||||
// M_AXI_ARADDR for all SI/MI slots.␍␍
|
||||
// # = 32.␍␍
|
||||
parameter C_S_AXI_DATA_WIDTH = 512,␍␍
|
||||
// Width of WDATA and RDATA on SI slot.␍␍
|
||||
// Must be <= APP_DATA_WIDTH.␍␍
|
||||
// # = 32, 64, 128, 256.␍␍
|
||||
parameter C_S_AXI_SUPPORTS_NARROW_BURST = 0,␍␍
|
||||
// Indicates whether to instatiate upsizer␍␍
|
||||
// Range: 0, 1␍␍
|
||||
␍␍
|
||||
␍␍
|
||||
//***************************************************************************␍␍
|
||||
// Debug parameters␍␍
|
||||
//***************************************************************************␍␍
|
||||
parameter DEBUG_PORT = "OFF",␍␍
|
||||
// # = "ON" Enable debug signals/controls.␍␍
|
||||
// = "OFF" Disable debug signals/controls.␍␍
|
||||
␍␍
|
||||
parameter RST_ACT_LOW = 0␍␍
|
||||
// =1 for active low reset,␍␍
|
||||
// =0 for active high.␍␍
|
||||
)␍␍
|
||||
(␍␍
|
||||
␍␍
|
||||
// Inouts␍␍
|
||||
inout [63:0] ddr3_dq,␍␍
|
||||
inout [7:0] ddr3_dqs_n,␍␍
|
||||
inout [7:0] ddr3_dqs_p,␍␍
|
||||
␍␍
|
||||
// Outputs␍␍
|
||||
output [13:0] ddr3_addr,␍␍
|
||||
output [2:0] ddr3_ba,␍␍
|
||||
output ddr3_ras_n,␍␍
|
||||
output ddr3_cas_n,␍␍
|
||||
output ddr3_we_n,␍␍
|
||||
output ddr3_reset_n,␍␍
|
||||
output [0:0] ddr3_ck_p,␍␍
|
||||
output [0:0] ddr3_ck_n,␍␍
|
||||
output [0:0] ddr3_cke,␍␍
|
||||
␍␍
|
||||
output [0:0] ddr3_cs_n,␍␍
|
||||
␍␍
|
||||
output [7:0] ddr3_dm,␍␍
|
||||
␍␍
|
||||
output [0:0] ddr3_odt,␍␍
|
||||
␍␍
|
||||
␍␍
|
||||
// Inputs␍␍
|
||||
␍␍
|
||||
// Differential system clocks␍␍
|
||||
input sys_clk_p,␍␍
|
||||
input sys_clk_n,␍␍
|
||||
␍␍
|
||||
␍␍
|
||||
output tg_compare_error,␍␍
|
||||
output init_calib_complete,␍␍
|
||||
␍␍
|
||||
␍␍
|
||||
␍␍
|
||||
// System reset - Default polarity of sys_rst pin is Active Low.␍␍
|
||||
// System reset polarity will change based on the option ␍␍
|
||||
// selected in GUI.␍␍
|
||||
input sys_rst␍␍
|
||||
);␍␍
|
||||
␍␍
|
||||
function integer clogb2 (input integer size);␍␍
|
||||
begin␍␍
|
||||
size = size - 1;␍␍
|
||||
for (clogb2=1; size>1; clogb2=clogb2+1)␍␍
|
||||
size = size >> 1;␍␍
|
||||
end␍␍
|
||||
endfunction // clogb2␍␍
|
||||
␍␍
|
||||
function integer STR_TO_INT;␍␍
|
||||
input [7:0] in;␍␍
|
||||
begin␍␍
|
||||
if(in == "8")␍␍
|
||||
STR_TO_INT = 8;␍␍
|
||||
else if(in == "4")␍␍
|
||||
STR_TO_INT = 4;␍␍
|
||||
else␍␍
|
||||
STR_TO_INT = 0;␍␍
|
||||
end␍␍
|
||||
endfunction␍␍
|
||||
␍␍
|
||||
␍␍
|
||||
localparam DATA_WIDTH = 64;␍␍
|
||||
localparam RANK_WIDTH = clogb2(RANKS);␍␍
|
||||
localparam PAYLOAD_WIDTH = (ECC_TEST == "OFF") ? DATA_WIDTH : DQ_WIDTH;␍␍
|
||||
localparam BURST_LENGTH = STR_TO_INT(BURST_MODE);␍␍
|
||||
localparam APP_DATA_WIDTH = 2 * nCK_PER_CLK * PAYLOAD_WIDTH;␍␍
|
||||
localparam APP_MASK_WIDTH = APP_DATA_WIDTH / 8;␍␍
|
||||
␍␍
|
||||
//***************************************************************************␍␍
|
||||
// Traffic Gen related parameters (derived)␍␍
|
||||
//***************************************************************************␍␍
|
||||
localparam TG_ADDR_WIDTH = ((CS_WIDTH == 1) ? 0 : RANK_WIDTH)␍␍
|
||||
+ BANK_WIDTH + ROW_WIDTH + COL_WIDTH;␍␍
|
||||
localparam MASK_SIZE = DATA_WIDTH/8;␍␍
|
||||
localparam DBG_WR_STS_WIDTH = 40;␍␍
|
||||
localparam DBG_RD_STS_WIDTH = 40;␍␍
|
||||
␍␍
|
||||
␍␍
|
||||
// Wire declarations␍␍
|
||||
␍␍
|
||||
wire clk;␍␍
|
||||
wire rst;␍␍
|
||||
wire ui_addn_clk_0;␍␍
|
||||
wire ui_addn_clk_1;␍␍
|
||||
wire ui_addn_clk_2;␍␍
|
||||
wire ui_addn_clk_3;␍␍
|
||||
wire ui_addn_clk_4;␍␍
|
||||
wire mmcm_locked;␍␍
|
||||
reg aresetn;␍␍
|
||||
wire app_sr_active;␍␍
|
||||
wire app_ref_ack;␍␍
|
||||
wire app_zq_ack;␍␍
|
||||
wire app_rd_data_valid;␍␍
|
||||
wire [APP_DATA_WIDTH-1:0] app_rd_data;␍␍
|
||||
␍␍
|
||||
wire mem_pattern_init_done;␍␍
|
||||
␍␍
|
||||
wire cmd_err;␍␍
|
||||
wire data_msmatch_err;␍␍
|
||||
wire write_err;␍␍
|
||||
wire read_err;␍␍
|
||||
wire test_cmptd;␍␍
|
||||
wire write_cmptd;␍␍
|
||||
wire read_cmptd;␍␍
|
||||
wire cmptd_one_wr_rd;␍␍
|
||||
␍␍
|
||||
// Slave Interface Write Address Ports␍␍
|
||||
wire [C_S_AXI_ID_WIDTH-1:0] s_axi_awid;␍␍
|
||||
wire [C_S_AXI_ADDR_WIDTH-1:0] s_axi_awaddr;␍␍
|
||||
wire [7:0] s_axi_awlen;␍␍
|
||||
wire [2:0] s_axi_awsize;␍␍
|
||||
wire [1:0] s_axi_awburst;␍␍
|
||||
wire [0:0] s_axi_awlock;␍␍
|
||||
wire [3:0] s_axi_awcache;␍␍
|
||||
wire [2:0] s_axi_awprot;␍␍
|
||||
wire s_axi_awvalid;␍␍
|
||||
wire s_axi_awready;␍␍
|
||||
// Slave Interface Write Data Ports␍␍
|
||||
wire [C_S_AXI_DATA_WIDTH-1:0] s_axi_wdata;␍␍
|
||||
wire [(C_S_AXI_DATA_WIDTH/8)-1:0] s_axi_wstrb;␍␍
|
||||
wire s_axi_wlast;␍␍
|
||||
wire s_axi_wvalid;␍␍
|
||||
wire s_axi_wready;␍␍
|
||||
// Slave Interface Write Response Ports␍␍
|
||||
wire s_axi_bready;␍␍
|
||||
wire [C_S_AXI_ID_WIDTH-1:0] s_axi_bid;␍␍
|
||||
wire [1:0] s_axi_bresp;␍␍
|
||||
wire s_axi_bvalid;␍␍
|
||||
// Slave Interface Read Address Ports␍␍
|
||||
wire [C_S_AXI_ID_WIDTH-1:0] s_axi_arid;␍␍
|
||||
wire [C_S_AXI_ADDR_WIDTH-1:0] s_axi_araddr;␍␍
|
||||
wire [7:0] s_axi_arlen;␍␍
|
||||
wire [2:0] s_axi_arsize;␍␍
|
||||
wire [1:0] s_axi_arburst;␍␍
|
||||
wire [0:0] s_axi_arlock;␍␍
|
||||
wire [3:0] s_axi_arcache;␍␍
|
||||
wire [2:0] s_axi_arprot;␍␍
|
||||
wire s_axi_arvalid;␍␍
|
||||
wire s_axi_arready;␍␍
|
||||
// Slave Interface Read Data Ports␍␍
|
||||
wire s_axi_rready;␍␍
|
||||
wire [C_S_AXI_ID_WIDTH-1:0] s_axi_rid;␍␍
|
||||
wire [C_S_AXI_DATA_WIDTH-1:0] s_axi_rdata;␍␍
|
||||
wire [1:0] s_axi_rresp;␍␍
|
||||
wire s_axi_rlast;␍␍
|
||||
wire s_axi_rvalid;␍␍
|
||||
␍␍
|
||||
wire cmp_data_valid;␍␍
|
||||
wire [C_S_AXI_DATA_WIDTH-1:0] cmp_data; // Compare data␍␍
|
||||
wire [C_S_AXI_DATA_WIDTH-1:0] rdata_cmp; // Read data␍␍
|
||||
␍␍
|
||||
wire dbg_wr_sts_vld;␍␍
|
||||
wire [DBG_WR_STS_WIDTH-1:0] dbg_wr_sts;␍␍
|
||||
wire dbg_rd_sts_vld;␍␍
|
||||
wire [DBG_RD_STS_WIDTH-1:0] dbg_rd_sts;␍␍
|
||||
wire [11:0] device_temp;␍␍
|
||||
␍␍
|
||||
`ifdef SKIP_CALIB␍␍
|
||||
// skip calibration wires␍␍
|
||||
wire calib_tap_req;␍␍
|
||||
reg calib_tap_load;␍␍
|
||||
reg [6:0] calib_tap_addr;␍␍
|
||||
reg [7:0] calib_tap_val;␍␍
|
||||
reg calib_tap_load_done;␍␍
|
||||
`endif␍␍
|
||||
␍␍
|
||||
␍␍
|
||||
␍␍
|
||||
//***************************************************************************␍␍
|
||||
␍␍
|
||||
␍␍
|
||||
␍␍
|
||||
assign tg_compare_error = cmd_err | data_msmatch_err | write_err | read_err;␍␍
|
||||
␍␍
|
||||
␍␍
|
||||
␍␍
|
||||
␍␍
|
||||
␍␍
|
||||
// Start of User Design top instance␍␍
|
||||
//***************************************************************************␍␍
|
||||
// The User design is instantiated below. The memory interface ports are␍␍
|
||||
// connected to the top-level and the application interface ports are␍␍
|
||||
// connected to the traffic generator module. This provides a reference␍␍
|
||||
// for connecting the memory controller to system.␍␍
|
||||
//***************************************************************************␍␍
|
||||
␍␍
|
||||
system_top_mig_7series_0_0 u_system_top_mig_7series_0_0␍␍
|
||||
(␍␍
|
||||
␍␍
|
||||
␍␍
|
||||
// Memory interface ports␍␍
|
||||
.ddr3_addr (ddr3_addr),␍␍
|
||||
.ddr3_ba (ddr3_ba),␍␍
|
||||
.ddr3_cas_n (ddr3_cas_n),␍␍
|
||||
.ddr3_ck_n (ddr3_ck_n),␍␍
|
||||
.ddr3_ck_p (ddr3_ck_p),␍␍
|
||||
.ddr3_cke (ddr3_cke),␍␍
|
||||
.ddr3_ras_n (ddr3_ras_n),␍␍
|
||||
.ddr3_we_n (ddr3_we_n),␍␍
|
||||
.ddr3_dq (ddr3_dq),␍␍
|
||||
.ddr3_dqs_n (ddr3_dqs_n),␍␍
|
||||
.ddr3_dqs_p (ddr3_dqs_p),␍␍
|
||||
.ddr3_reset_n (ddr3_reset_n),␍␍
|
||||
.init_calib_complete (init_calib_complete),␍␍
|
||||
␍␍
|
||||
.ddr3_cs_n (ddr3_cs_n),␍␍
|
||||
.ddr3_dm (ddr3_dm),␍␍
|
||||
.ddr3_odt (ddr3_odt),␍␍
|
||||
// Application interface ports␍␍
|
||||
.ui_clk (clk),␍␍
|
||||
.ui_clk_sync_rst (rst),␍␍
|
||||
␍␍
|
||||
.ui_addn_clk_0 (ui_addn_clk_0),␍␍
|
||||
.ui_addn_clk_1 (ui_addn_clk_1),␍␍
|
||||
.ui_addn_clk_2 (ui_addn_clk_2),␍␍
|
||||
.ui_addn_clk_3 (ui_addn_clk_3),␍␍
|
||||
.ui_addn_clk_4 (ui_addn_clk_4),␍␍
|
||||
.mmcm_locked (mmcm_locked),␍␍
|
||||
.aresetn (aresetn),␍␍
|
||||
.app_sr_active (app_sr_active),␍␍
|
||||
.app_ref_ack (app_ref_ack),␍␍
|
||||
.app_zq_ack (app_zq_ack),␍␍
|
||||
␍␍
|
||||
// Slave Interface Write Address Ports␍␍
|
||||
.s_axi_awid (s_axi_awid),␍␍
|
||||
.s_axi_awaddr (s_axi_awaddr),␍␍
|
||||
.s_axi_awlen (s_axi_awlen),␍␍
|
||||
.s_axi_awsize (s_axi_awsize),␍␍
|
||||
.s_axi_awburst (s_axi_awburst),␍␍
|
||||
.s_axi_awlock (s_axi_awlock),␍␍
|
||||
.s_axi_awcache (s_axi_awcache),␍␍
|
||||
.s_axi_awprot (s_axi_awprot),␍␍
|
||||
.s_axi_awqos (4'h0),␍␍
|
||||
.s_axi_awvalid (s_axi_awvalid),␍␍
|
||||
.s_axi_awready (s_axi_awready),␍␍
|
||||
// Slave Interface Write Data Ports␍␍
|
||||
.s_axi_wdata (s_axi_wdata),␍␍
|
||||
.s_axi_wstrb (s_axi_wstrb),␍␍
|
||||
.s_axi_wlast (s_axi_wlast),␍␍
|
||||
.s_axi_wvalid (s_axi_wvalid),␍␍
|
||||
.s_axi_wready (s_axi_wready),␍␍
|
||||
// Slave Interface Write Response Ports␍␍
|
||||
.s_axi_bid (s_axi_bid),␍␍
|
||||
.s_axi_bresp (s_axi_bresp),␍␍
|
||||
.s_axi_bvalid (s_axi_bvalid),␍␍
|
||||
.s_axi_bready (s_axi_bready),␍␍
|
||||
// Slave Interface Read Address Ports␍␍
|
||||
.s_axi_arid (s_axi_arid),␍␍
|
||||
.s_axi_araddr (s_axi_araddr),␍␍
|
||||
.s_axi_arlen (s_axi_arlen),␍␍
|
||||
.s_axi_arsize (s_axi_arsize),␍␍
|
||||
.s_axi_arburst (s_axi_arburst),␍␍
|
||||
.s_axi_arlock (s_axi_arlock),␍␍
|
||||
.s_axi_arcache (s_axi_arcache),␍␍
|
||||
.s_axi_arprot (s_axi_arprot),␍␍
|
||||
.s_axi_arqos (4'h0),␍␍
|
||||
.s_axi_arvalid (s_axi_arvalid),␍␍
|
||||
.s_axi_arready (s_axi_arready),␍␍
|
||||
// Slave Interface Read Data Ports␍␍
|
||||
.s_axi_rid (s_axi_rid),␍␍
|
||||
.s_axi_rdata (s_axi_rdata),␍␍
|
||||
.s_axi_rresp (s_axi_rresp),␍␍
|
||||
.s_axi_rlast (s_axi_rlast),␍␍
|
||||
.s_axi_rvalid (s_axi_rvalid),␍␍
|
||||
.s_axi_rready (s_axi_rready),␍␍
|
||||
␍␍
|
||||
␍␍
|
||||
␍␍
|
||||
// System Clock Ports␍␍
|
||||
.sys_clk_p (sys_clk_p),␍␍
|
||||
.sys_clk_n (sys_clk_n),␍␍
|
||||
.device_temp (device_temp),␍␍
|
||||
`ifdef SKIP_CALIB␍␍
|
||||
.calib_tap_req (calib_tap_req),␍␍
|
||||
.calib_tap_load (calib_tap_load),␍␍
|
||||
.calib_tap_addr (calib_tap_addr),␍␍
|
||||
.calib_tap_val (calib_tap_val),␍␍
|
||||
.calib_tap_load_done (calib_tap_load_done),␍␍
|
||||
`endif␍␍
|
||||
␍␍
|
||||
.sys_rst (sys_rst)␍␍
|
||||
);␍␍
|
||||
// End of User Design top instance␍␍
|
||||
␍␍
|
||||
␍␍
|
||||
//***************************************************************************␍␍
|
||||
// The traffic generation module instantiated below drives traffic (patterns)␍␍
|
||||
// on the application interface of the memory controller␍␍
|
||||
//***************************************************************************␍␍
|
||||
␍␍
|
||||
always @(posedge clk) begin␍␍
|
||||
aresetn <= ~rst;␍␍
|
||||
end␍␍
|
||||
␍␍
|
||||
mig_7series_v4_2_axi4_tg #(␍␍
|
||||
␍␍
|
||||
.C_AXI_ID_WIDTH (C_S_AXI_ID_WIDTH),␍␍
|
||||
.C_AXI_ADDR_WIDTH (C_S_AXI_ADDR_WIDTH),␍␍
|
||||
.C_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),␍␍
|
||||
.C_AXI_NBURST_SUPPORT (C_AXI_NBURST_TEST),␍␍
|
||||
.C_EN_WRAP_TRANS (C_EN_WRAP_TRANS),␍␍
|
||||
.C_BEGIN_ADDRESS (BEGIN_ADDRESS),␍␍
|
||||
.C_END_ADDRESS (END_ADDRESS),␍␍
|
||||
.PRBS_EADDR_MASK_POS (PRBS_EADDR_MASK_POS),␍␍
|
||||
.DBG_WR_STS_WIDTH (DBG_WR_STS_WIDTH),␍␍
|
||||
.DBG_RD_STS_WIDTH (DBG_RD_STS_WIDTH),␍␍
|
||||
.ENFORCE_RD_WR (ENFORCE_RD_WR),␍␍
|
||||
.ENFORCE_RD_WR_CMD (ENFORCE_RD_WR_CMD),␍␍
|
||||
.EN_UPSIZER (C_S_AXI_SUPPORTS_NARROW_BURST),␍␍
|
||||
.ENFORCE_RD_WR_PATTERN (ENFORCE_RD_WR_PATTERN)␍␍
|
||||
␍␍
|
||||
) u_axi4_tg_inst␍␍
|
||||
(␍␍
|
||||
.aclk (clk),␍␍
|
||||
.aresetn (aresetn),␍␍
|
||||
␍␍
|
||||
// Input control signals␍␍
|
||||
.init_cmptd (init_calib_complete),␍␍
|
||||
.init_test (1'b0),␍␍
|
||||
.wdog_mask (~init_calib_complete),␍␍
|
||||
.wrap_en (1'b0),␍␍
|
||||
␍␍
|
||||
// AXI write address channel signals␍␍
|
||||
.axi_wready (s_axi_awready),␍␍
|
||||
.axi_wid (s_axi_awid),␍␍
|
||||
.axi_waddr (s_axi_awaddr),␍␍
|
||||
.axi_wlen (s_axi_awlen),␍␍
|
||||
.axi_wsize (s_axi_awsize),␍␍
|
||||
.axi_wburst (s_axi_awburst),␍␍
|
||||
.axi_wlock (s_axi_awlock),␍␍
|
||||
.axi_wcache (s_axi_awcache),␍␍
|
||||
.axi_wprot (s_axi_awprot),␍␍
|
||||
.axi_wvalid (s_axi_awvalid),␍␍
|
||||
␍␍
|
||||
// AXI write data channel signals␍␍
|
||||
.axi_wd_wready (s_axi_wready),␍␍
|
||||
.axi_wd_wid (s_axi_wid),␍␍
|
||||
.axi_wd_data (s_axi_wdata),␍␍
|
||||
.axi_wd_strb (s_axi_wstrb),␍␍
|
||||
.axi_wd_last (s_axi_wlast),␍␍
|
||||
.axi_wd_valid (s_axi_wvalid),␍␍
|
||||
␍␍
|
||||
// AXI write response channel signals␍␍
|
||||
.axi_wd_bid (s_axi_bid),␍␍
|
||||
.axi_wd_bresp (s_axi_bresp),␍␍
|
||||
.axi_wd_bvalid (s_axi_bvalid),␍␍
|
||||
.axi_wd_bready (s_axi_bready),␍␍
|
||||
␍␍
|
||||
// AXI read address channel signals␍␍
|
||||
.axi_rready (s_axi_arready),␍␍
|
||||
.axi_rid (s_axi_arid),␍␍
|
||||
.axi_raddr (s_axi_araddr),␍␍
|
||||
.axi_rlen (s_axi_arlen),␍␍
|
||||
.axi_rsize (s_axi_arsize),␍␍
|
||||
.axi_rburst (s_axi_arburst),␍␍
|
||||
.axi_rlock (s_axi_arlock),␍␍
|
||||
.axi_rcache (s_axi_arcache),␍␍
|
||||
.axi_rprot (s_axi_arprot),␍␍
|
||||
.axi_rvalid (s_axi_arvalid),␍␍
|
||||
␍␍
|
||||
// AXI read data channel signals␍␍
|
||||
.axi_rd_bid (s_axi_rid),␍␍
|
||||
.axi_rd_rresp (s_axi_rresp),␍␍
|
||||
.axi_rd_rvalid (s_axi_rvalid),␍␍
|
||||
.axi_rd_data (s_axi_rdata),␍␍
|
||||
.axi_rd_last (s_axi_rlast),␍␍
|
||||
.axi_rd_rready (s_axi_rready),␍␍
|
||||
␍␍
|
||||
// Error status signals␍␍
|
||||
.cmd_err (cmd_err),␍␍
|
||||
.data_msmatch_err (data_msmatch_err),␍␍
|
||||
.write_err (write_err),␍␍
|
||||
.read_err (read_err),␍␍
|
||||
.test_cmptd (test_cmptd),␍␍
|
||||
.write_cmptd (write_cmptd),␍␍
|
||||
.read_cmptd (read_cmptd),␍␍
|
||||
.cmptd_one_wr_rd (cmptd_one_wr_rd),␍␍
|
||||
␍␍
|
||||
// Debug status signals␍␍
|
||||
.cmp_data_en (cmp_data_valid),␍␍
|
||||
.cmp_data_o (cmp_data),␍␍
|
||||
.rdata_cmp (rdata_cmp),␍␍
|
||||
.dbg_wr_sts_vld (dbg_wr_sts_vld),␍␍
|
||||
.dbg_wr_sts (dbg_wr_sts),␍␍
|
||||
.dbg_rd_sts_vld (dbg_rd_sts_vld),␍␍
|
||||
.dbg_rd_sts (dbg_rd_sts)␍␍
|
||||
);␍␍
|
||||
␍␍
|
||||
␍␍
|
||||
␍␍
|
||||
␍␍
|
||||
//*****************************************************************␍␍
|
||||
// Default values are assigned to the debug inputs␍␍
|
||||
//*****************************************************************␍␍
|
||||
assign dbg_sel_pi_incdec = 'b0;␍␍
|
||||
assign dbg_sel_po_incdec = 'b0;␍␍
|
||||
assign dbg_pi_f_inc = 'b0;␍␍
|
||||
assign dbg_pi_f_dec = 'b0;␍␍
|
||||
assign dbg_po_f_inc = 'b0;␍␍
|
||||
assign dbg_po_f_dec = 'b0;␍␍
|
||||
assign dbg_po_f_stg23_sel = 'b0;␍␍
|
||||
assign po_win_tg_rst = 'b0;␍␍
|
||||
assign vio_tg_rst = 'b0;␍␍
|
||||
`ifdef SKIP_CALIB␍␍
|
||||
//***************************************************************************␍␍
|
||||
// Skip calib test logic␍␍
|
||||
//***************************************************************************␍␍
|
||||
␍␍
|
||||
reg[3*DQS_WIDTH-1:0] po_coarse_tap;␍␍
|
||||
reg[6*DQS_WIDTH-1:0] po_stg3_taps;␍␍
|
||||
reg[6*DQS_WIDTH-1:0] po_stg2_taps;␍␍
|
||||
reg[6*DQS_WIDTH-1:0] pi_stg2_taps;␍␍
|
||||
reg[5*DQS_WIDTH-1:0] idelay_taps;␍␍
|
||||
reg[11:0] cal_device_temp;␍␍
|
||||
␍␍
|
||||
␍␍
|
||||
always @(posedge clk) begin␍␍
|
||||
// tap values from golden run (factory)␍␍
|
||||
po_coarse_tap <= #TCQ 'h2;␍␍
|
||||
po_stg3_taps <= #TCQ 'h0D;␍␍
|
||||
po_stg2_taps <= #TCQ 'h1D;␍␍
|
||||
pi_stg2_taps <= #TCQ 'h1E;␍␍
|
||||
idelay_taps <= #TCQ 'h08;␍␍
|
||||
cal_device_temp <= #TCQ 'h000;␍␍
|
||||
end␍␍
|
||||
␍␍
|
||||
always @(posedge clk) begin␍␍
|
||||
if (rst)␍␍
|
||||
calib_tap_load <= #TCQ 1'b0;␍␍
|
||||
else if (calib_tap_req)␍␍
|
||||
calib_tap_load <= #TCQ 1'b1;␍␍
|
||||
end␍␍
|
||||
␍␍
|
||||
always @(posedge clk) begin␍␍
|
||||
if (rst) begin␍␍
|
||||
calib_tap_addr <= #TCQ 'd0;␍␍
|
||||
calib_tap_val <= #TCQ po_coarse_tap[3*calib_tap_addr[6:3]+:3]; //'d1;␍␍
|
||||
calib_tap_load_done <= #TCQ 1'b0;␍␍
|
||||
end else if (calib_tap_load) begin␍␍
|
||||
case (calib_tap_addr[2:0])␍␍
|
||||
3'b000: begin␍␍
|
||||
calib_tap_addr[2:0] <= #TCQ 3'b001;␍␍
|
||||
calib_tap_val <= #TCQ po_stg3_taps[6*calib_tap_addr[6:3]+:6]; //'d19;␍␍
|
||||
end␍␍
|
||||
3'b001: begin␍␍
|
||||
calib_tap_addr[2:0] <= #TCQ 3'b010;␍␍
|
||||
calib_tap_val <= #TCQ po_stg2_taps[6*calib_tap_addr[6:3]+:6]; //'d45;␍␍
|
||||
end␍␍
|
||||
3'b010: begin␍␍
|
||||
calib_tap_addr[2:0] <= #TCQ 3'b011;␍␍
|
||||
calib_tap_val <= #TCQ pi_stg2_taps[6*calib_tap_addr[6:3]+:6]; //'d20;␍␍
|
||||
end␍␍
|
||||
3'b011: begin␍␍
|
||||
calib_tap_addr[2:0] <= #TCQ 3'b100;␍␍
|
||||
calib_tap_val <= #TCQ idelay_taps[5*calib_tap_addr[6:3]+:5]; //'d1;␍␍
|
||||
end␍␍
|
||||
3'b100: begin␍␍
|
||||
if (calib_tap_addr[6:3] < DQS_WIDTH-1) begin␍␍
|
||||
calib_tap_addr[2:0] <= #TCQ 3'b000;␍␍
|
||||
calib_tap_val <= #TCQ po_coarse_tap[3*(calib_tap_addr[6:3]+1)+:3]; //'d1;␍␍
|
||||
calib_tap_addr[6:3] <= #TCQ calib_tap_addr[6:3] + 1;␍␍
|
||||
end else begin␍␍
|
||||
calib_tap_addr[2:0] <= #TCQ 3'b110;␍␍
|
||||
calib_tap_val <= #TCQ cal_device_temp[7:0];␍␍
|
||||
calib_tap_addr[6:3] <= #TCQ 4'b1111;␍␍
|
||||
end␍␍
|
||||
end␍␍
|
||||
3'b110: begin␍␍
|
||||
calib_tap_addr[2:0] <= #TCQ 3'b111;␍␍
|
||||
calib_tap_val <= #TCQ {4'h0,cal_device_temp[11:8]};␍␍
|
||||
calib_tap_addr[6:3] <= #TCQ 4'b1111;␍␍
|
||||
end␍␍
|
||||
3'b111: begin␍␍
|
||||
calib_tap_load_done <= #TCQ 1'b1;␍␍
|
||||
end␍␍
|
||||
endcase␍␍
|
||||
end␍␍
|
||||
end␍␍
|
||||
␍␍
|
||||
␍␍
|
||||
//****************skip calib test logic end**********************************␍␍
|
||||
`endif ␍␍
|
||||
␍␍
|
||||
endmodule␍␍
|
||||
␍␍
|
||||
␍
|
||||
+413
@@ -0,0 +1,413 @@
|
||||
//*****************************************************************************
|
||||
// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
//*****************************************************************************
|
||||
// ____ ____
|
||||
// / /\/ /
|
||||
// /___/ \ / Vendor: Xilinx
|
||||
// \ \ \/ Version: 3.6
|
||||
// \ \ Application: MIG
|
||||
// / / Filename: axi4_wrapper.v
|
||||
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:37:18 $
|
||||
// \ \ / \ Date Created: Sept 16, 2009
|
||||
// \___\/\___\
|
||||
//
|
||||
//Device: Virtex-6, Spartan-6 and 7series
|
||||
//Design Name: DDR3 SDRAM
|
||||
//Purpose:
|
||||
// This module is wrapper for converting the reads and writes to transactions
|
||||
// that follow the AXI protocol.
|
||||
//
|
||||
//Reference:
|
||||
//Revision History:
|
||||
//*****************************************************************************
|
||||
`timescale 1ps/1ps
|
||||
|
||||
module mig_7series_v4_2_axi4_tg #(
|
||||
|
||||
parameter C_AXI_ID_WIDTH = 4, // The AXI id width used for read and write
|
||||
// This is an integer between 1-16
|
||||
parameter C_AXI_ADDR_WIDTH = 32, // This is AXI address width for all
|
||||
// SI and MI slots
|
||||
parameter C_AXI_DATA_WIDTH = 32, // Width of the AXI write and read data
|
||||
|
||||
parameter C_AXI_NBURST_SUPPORT = 0, // Support for narrow burst transfers
|
||||
// 1-supported, 0-not supported
|
||||
parameter C_EN_WRAP_TRANS = 0, // Set 1 to enable wrap transactions
|
||||
|
||||
parameter C_BEGIN_ADDRESS = 0, // Start address of the address map
|
||||
|
||||
parameter C_END_ADDRESS = 32'hFFFF_FFFF, // End address of the address map
|
||||
|
||||
parameter PRBS_EADDR_MASK_POS = 32'hFFFFD000,
|
||||
|
||||
parameter PRBS_SADDR_MASK_POS = 32'h00002000,
|
||||
|
||||
parameter DBG_WR_STS_WIDTH = 40,
|
||||
|
||||
parameter DBG_RD_STS_WIDTH = 40,
|
||||
|
||||
parameter ENFORCE_RD_WR = 0,
|
||||
|
||||
parameter ENFORCE_RD_WR_CMD = 8'h11,
|
||||
|
||||
parameter EN_UPSIZER = 0,
|
||||
|
||||
parameter ENFORCE_RD_WR_PATTERN = 3'b000
|
||||
|
||||
)
|
||||
(
|
||||
input aclk, // AXI input clock
|
||||
input aresetn, // Active low AXI reset signal
|
||||
|
||||
// Input control signals
|
||||
input init_cmptd, // Initialization completed
|
||||
input init_test, // Initialize the test
|
||||
input wdog_mask, // Mask the watchdog timeouts
|
||||
input wrap_en, // Enable wrap transactions
|
||||
|
||||
// AXI write address channel signals
|
||||
input axi_wready, // Indicates slave is ready to accept a
|
||||
output [C_AXI_ID_WIDTH-1:0] axi_wid, // Write ID
|
||||
output [C_AXI_ADDR_WIDTH-1:0] axi_waddr, // Write address
|
||||
output [7:0] axi_wlen, // Write Burst Length
|
||||
output [2:0] axi_wsize, // Write Burst size
|
||||
output [1:0] axi_wburst, // Write Burst type
|
||||
output [1:0] axi_wlock, // Write lock type
|
||||
output [3:0] axi_wcache, // Write Cache type
|
||||
output [2:0] axi_wprot, // Write Protection type
|
||||
output axi_wvalid, // Write address valid
|
||||
|
||||
// AXI write data channel signals
|
||||
input axi_wd_wready, // Write data ready
|
||||
output [C_AXI_ID_WIDTH-1:0] axi_wd_wid, // Write ID tag
|
||||
output [C_AXI_DATA_WIDTH-1:0] axi_wd_data, // Write data
|
||||
output [C_AXI_DATA_WIDTH/8-1:0] axi_wd_strb, // Write strobes
|
||||
output axi_wd_last, // Last write transaction
|
||||
output axi_wd_valid, // Write valid
|
||||
|
||||
// AXI write response channel signals
|
||||
input [C_AXI_ID_WIDTH-1:0] axi_wd_bid, // Response ID
|
||||
input [1:0] axi_wd_bresp, // Write response
|
||||
input axi_wd_bvalid, // Write reponse valid
|
||||
output axi_wd_bready, // Response ready
|
||||
|
||||
// AXI read address channel signals
|
||||
input axi_rready, // Read address ready
|
||||
output [C_AXI_ID_WIDTH-1:0] axi_rid, // Read ID
|
||||
output [C_AXI_ADDR_WIDTH-1:0] axi_raddr, // Read address
|
||||
output [7:0] axi_rlen, // Read Burst Length
|
||||
output [2:0] axi_rsize, // Read Burst size
|
||||
output [1:0] axi_rburst, // Read Burst type
|
||||
output [1:0] axi_rlock, // Read lock type
|
||||
output [3:0] axi_rcache, // Read Cache type
|
||||
output [2:0] axi_rprot, // Read Protection type
|
||||
output axi_rvalid, // Read address valid
|
||||
|
||||
// AXI read data channel signals
|
||||
input [C_AXI_ID_WIDTH-1:0] axi_rd_bid, // Response ID
|
||||
input [1:0] axi_rd_rresp, // Read response
|
||||
input axi_rd_rvalid, // Read reponse valid
|
||||
input [C_AXI_DATA_WIDTH-1:0] axi_rd_data, // Read data
|
||||
input axi_rd_last, // Read last
|
||||
output axi_rd_rready, // Read Response ready
|
||||
|
||||
// Error status signals
|
||||
output cmd_err, // Error during command phase
|
||||
output data_msmatch_err, // Data mismatch
|
||||
output write_err, // Write error occured
|
||||
output read_err, // Read error occured
|
||||
output test_cmptd, // Data pattern test completed
|
||||
output write_cmptd, // Write test completed
|
||||
output read_cmptd, // Read test completed
|
||||
output reg cmptd_one_wr_rd, // Completed atleast one write
|
||||
// and read
|
||||
|
||||
// Debug status signals
|
||||
output cmp_data_en,
|
||||
output [C_AXI_DATA_WIDTH-1:0] cmp_data_o, // Compare data
|
||||
output [C_AXI_DATA_WIDTH-1:0] rdata_cmp, // Read data
|
||||
output dbg_wr_sts_vld, // Write debug status valid,
|
||||
output [DBG_WR_STS_WIDTH-1:0] dbg_wr_sts, // Write status
|
||||
output dbg_rd_sts_vld, // Read debug status valid
|
||||
output [DBG_RD_STS_WIDTH-1:0] dbg_rd_sts // Read status
|
||||
);
|
||||
|
||||
//*****************************************************************************
|
||||
// Parameter declarations
|
||||
//*****************************************************************************
|
||||
|
||||
localparam CTL_SIG_WIDTH = 3; // Control signal width
|
||||
localparam RD_STS_WIDTH = 16; // Read port status signal width
|
||||
localparam WDG_TIMER_WIDTH = 11;
|
||||
localparam WR_STS_WIDTH = 16; // Write port status signal width
|
||||
|
||||
//*****************************************************************************
|
||||
// Internal register and wire declarations
|
||||
//*****************************************************************************
|
||||
|
||||
wire cmd_en;
|
||||
wire [2:0] cmd;
|
||||
wire [7:0] blen;
|
||||
wire [31:0] addr;
|
||||
wire [CTL_SIG_WIDTH-1:0] ctl;
|
||||
wire cmd_ack;
|
||||
|
||||
// User interface write ports
|
||||
wire wrdata_vld;
|
||||
wire [C_AXI_DATA_WIDTH-1:0] wrdata;
|
||||
wire [C_AXI_DATA_WIDTH/8-1:0] wrdata_bvld;
|
||||
wire wrdata_cmptd;
|
||||
wire wrdata_rdy;
|
||||
wire wrdata_sts_vld;
|
||||
wire [WR_STS_WIDTH-1:0] wrdata_sts;
|
||||
|
||||
// User interface read ports
|
||||
wire rddata_rdy;
|
||||
wire rddata_vld;
|
||||
wire [C_AXI_DATA_WIDTH-1:0] rddata;
|
||||
wire [C_AXI_DATA_WIDTH/8-1:0] rddata_bvld;
|
||||
wire rddata_cmptd;
|
||||
wire [RD_STS_WIDTH-1:0] rddata_sts;
|
||||
reg cmptd_one_wr;
|
||||
reg cmptd_one_rd;
|
||||
|
||||
//*****************************************************************************
|
||||
// AXI4 wrapper instance
|
||||
//*****************************************************************************
|
||||
|
||||
mig_7series_v4_2_axi4_wrapper #
|
||||
(
|
||||
|
||||
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
|
||||
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
|
||||
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
|
||||
.C_AXI_NBURST_SUPPORT (C_AXI_NBURST_SUPPORT),
|
||||
.C_BEGIN_ADDRESS (C_BEGIN_ADDRESS),
|
||||
.C_END_ADDRESS (C_END_ADDRESS),
|
||||
.CTL_SIG_WIDTH (CTL_SIG_WIDTH),
|
||||
.WR_STS_WIDTH (WR_STS_WIDTH),
|
||||
.RD_STS_WIDTH (RD_STS_WIDTH),
|
||||
.EN_UPSIZER (EN_UPSIZER),
|
||||
.WDG_TIMER_WIDTH (WDG_TIMER_WIDTH)
|
||||
|
||||
) axi4_wrapper_inst
|
||||
(
|
||||
.aclk (aclk),
|
||||
.aresetn (aresetn),
|
||||
|
||||
// User interface command port
|
||||
.cmd_en (cmd_en),
|
||||
.cmd (cmd),
|
||||
.blen (blen),
|
||||
.addr (addr),
|
||||
.ctl (ctl),
|
||||
.wdog_mask (wdog_mask),
|
||||
.cmd_ack (cmd_ack),
|
||||
|
||||
// User interface write ports
|
||||
.wrdata_vld (wrdata_vld),
|
||||
.wrdata (wrdata),
|
||||
.wrdata_bvld (wrdata_bvld),
|
||||
.wrdata_cmptd (wrdata_cmptd),
|
||||
.wrdata_rdy (wrdata_rdy),
|
||||
.wrdata_sts_vld (wrdata_sts_vld),
|
||||
.wrdata_sts (wrdata_sts),
|
||||
|
||||
// User interface read ports
|
||||
.rddata_rdy (rddata_rdy),
|
||||
.rddata_vld (rddata_vld),
|
||||
.rddata (rddata),
|
||||
.rddata_bvld (rddata_bvld),
|
||||
.rddata_cmptd (rddata_cmptd),
|
||||
.rddata_sts (rddata_sts),
|
||||
|
||||
// AXI write address channel signals
|
||||
.axi_wready (axi_wready),
|
||||
.axi_wid (axi_wid),
|
||||
.axi_waddr (axi_waddr),
|
||||
.axi_wlen (axi_wlen),
|
||||
.axi_wsize (axi_wsize),
|
||||
.axi_wburst (axi_wburst),
|
||||
.axi_wlock (axi_wlock),
|
||||
.axi_wcache (axi_wcache),
|
||||
.axi_wprot (axi_wprot),
|
||||
.axi_wvalid (axi_wvalid),
|
||||
|
||||
// AXI write data channel signals
|
||||
.axi_wd_wready (axi_wd_wready),
|
||||
.axi_wd_wid (axi_wd_wid),
|
||||
.axi_wd_data (axi_wd_data),
|
||||
.axi_wd_strb (axi_wd_strb),
|
||||
.axi_wd_last (axi_wd_last),
|
||||
.axi_wd_valid (axi_wd_valid),
|
||||
|
||||
// AXI write response channel signals
|
||||
.axi_wd_bid (axi_wd_bid),
|
||||
.axi_wd_bresp (axi_wd_bresp),
|
||||
.axi_wd_bvalid (axi_wd_bvalid),
|
||||
.axi_wd_bready (axi_wd_bready),
|
||||
|
||||
// AXI read address channel signals
|
||||
.axi_rready (axi_rready),
|
||||
.axi_rid (axi_rid),
|
||||
.axi_raddr (axi_raddr),
|
||||
.axi_rlen (axi_rlen),
|
||||
.axi_rsize (axi_rsize),
|
||||
.axi_rburst (axi_rburst),
|
||||
.axi_rlock (axi_rlock),
|
||||
.axi_rcache (axi_rcache),
|
||||
.axi_rprot (axi_rprot),
|
||||
.axi_rvalid (axi_rvalid),
|
||||
|
||||
// AXI read data channel signals
|
||||
.axi_rd_bid (axi_rd_bid),
|
||||
.axi_rd_rresp (axi_rd_rresp),
|
||||
.axi_rd_rvalid (axi_rd_rvalid),
|
||||
.axi_rd_data (axi_rd_data),
|
||||
.axi_rd_last (axi_rd_last),
|
||||
.axi_rd_rready (axi_rd_rready)
|
||||
);
|
||||
|
||||
//*****************************************************************************
|
||||
// Traffic Generator instance
|
||||
//*****************************************************************************
|
||||
|
||||
mig_7series_v4_2_tg #
|
||||
(
|
||||
|
||||
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
|
||||
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
|
||||
.C_AXI_NBURST_SUPPORT (C_AXI_NBURST_SUPPORT),
|
||||
.C_BEGIN_ADDRESS (C_BEGIN_ADDRESS),
|
||||
.C_END_ADDRESS (C_END_ADDRESS),
|
||||
.C_EN_WRAP_TRANS (C_EN_WRAP_TRANS),
|
||||
.CTL_SIG_WIDTH (CTL_SIG_WIDTH),
|
||||
.WR_STS_WIDTH (WR_STS_WIDTH),
|
||||
.RD_STS_WIDTH (RD_STS_WIDTH),
|
||||
.DBG_WR_STS_WIDTH (DBG_WR_STS_WIDTH),
|
||||
.DBG_RD_STS_WIDTH (DBG_RD_STS_WIDTH),
|
||||
.ENFORCE_RD_WR (ENFORCE_RD_WR),
|
||||
.ENFORCE_RD_WR_CMD (ENFORCE_RD_WR_CMD),
|
||||
.PRBS_EADDR_MASK_POS (PRBS_EADDR_MASK_POS),
|
||||
.PRBS_SADDR_MASK_POS (PRBS_SADDR_MASK_POS),
|
||||
.ENFORCE_RD_WR_PATTERN (ENFORCE_RD_WR_PATTERN)
|
||||
|
||||
) traffic_gen_inst
|
||||
(
|
||||
.clk (aclk),
|
||||
.resetn (aresetn),
|
||||
|
||||
// Input start signals
|
||||
.init_cmptd (init_cmptd),
|
||||
.init_test (init_test),
|
||||
.wrap_en (wrap_en),
|
||||
|
||||
// Control ports
|
||||
.cmd_ack (cmd_ack),
|
||||
.cmd_en (cmd_en),
|
||||
.cmd (cmd),
|
||||
.blen (blen),
|
||||
.addr (addr),
|
||||
.ctl (ctl),
|
||||
|
||||
// Write port
|
||||
.wdata_rdy (wrdata_rdy),
|
||||
.wdata_vld (wrdata_vld),
|
||||
.wdata_cmptd (wrdata_cmptd),
|
||||
.wdata (wrdata),
|
||||
.wdata_bvld (wrdata_bvld),
|
||||
.wdata_sts_vld (wrdata_sts_vld),
|
||||
.wdata_sts (wrdata_sts),
|
||||
|
||||
// Read Port
|
||||
.rdata_vld (rddata_vld),
|
||||
.rdata (rddata),
|
||||
.rdata_bvld (rddata_bvld),
|
||||
.rdata_cmptd (rddata_cmptd),
|
||||
.rdata_sts (rddata_sts),
|
||||
.rdata_rdy (rddata_rdy),
|
||||
|
||||
// Error status signals
|
||||
.cmd_err (cmd_err),
|
||||
.data_msmatch_err (data_msmatch_err),
|
||||
.write_err (write_err),
|
||||
.read_err (read_err),
|
||||
.test_cmptd (test_cmptd),
|
||||
.write_cmptd (write_cmptd),
|
||||
.read_cmptd (read_cmptd),
|
||||
|
||||
// Debug status signals
|
||||
.cmp_data_en (cmp_data_en),
|
||||
.rdata_cmp (rdata_cmp),
|
||||
.dbg_wr_sts_vld (dbg_wr_sts_vld),
|
||||
.dbg_wr_sts (dbg_wr_sts),
|
||||
.dbg_rd_sts_vld (dbg_rd_sts_vld),
|
||||
.dbg_rd_sts (dbg_rd_sts)
|
||||
);
|
||||
|
||||
assign cmp_data_o = wrdata;
|
||||
|
||||
always @(posedge aclk)
|
||||
if (!aresetn)
|
||||
cmptd_one_wr <= 1'b0;
|
||||
else if (write_cmptd)
|
||||
cmptd_one_wr <= 1'b1;
|
||||
|
||||
always @(posedge aclk)
|
||||
if (!aresetn)
|
||||
cmptd_one_rd <= 1'b0;
|
||||
else if (read_cmptd)
|
||||
cmptd_one_rd <= 1'b1;
|
||||
|
||||
always @(posedge aclk)
|
||||
if (!aresetn)
|
||||
cmptd_one_wr_rd <= 1'b0;
|
||||
else if (cmptd_one_wr & cmptd_one_rd)
|
||||
cmptd_one_wr_rd <= 1'b1;
|
||||
|
||||
endmodule
|
||||
+869
@@ -0,0 +1,869 @@
|
||||
//*****************************************************************************
|
||||
// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
//*****************************************************************************
|
||||
// ____ ____
|
||||
// / /\/ /
|
||||
// /___/ \ / Vendor: Xilinx
|
||||
// \ \ \/ Version: 3.6
|
||||
// \ \ Application: MIG
|
||||
// / / Filename: axi4_wrapper.v
|
||||
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:37:18 $
|
||||
// \ \ / \ Date Created: Sept 16, 2009
|
||||
// \___\/\___\
|
||||
//
|
||||
//Device: Virtex-6, Spartan-6 and 7series
|
||||
//Design Name: DDR3 SDRAM
|
||||
//Purpose:
|
||||
// This module is wrapper for converting the reads and writes to transactions
|
||||
// that follow the AXI4 protocol.
|
||||
//
|
||||
//Reference:
|
||||
//Revision History:
|
||||
//*****************************************************************************
|
||||
`timescale 1ps/1ps
|
||||
|
||||
module mig_7series_v4_2_axi4_wrapper #(
|
||||
|
||||
parameter C_AXI_ID_WIDTH = 4, // The AXI id width used for read and write
|
||||
// This is an integer between 1-16
|
||||
parameter C_AXI_ADDR_WIDTH = 32, // This is AXI address width for all
|
||||
// SI and MI slots
|
||||
parameter C_AXI_DATA_WIDTH = 32, // Width of the AXI write and read data
|
||||
|
||||
parameter C_AXI_NBURST_SUPPORT = 0, // Support for narrow burst transfers
|
||||
// 1-supported, 0-not supported
|
||||
parameter C_BEGIN_ADDRESS = 0, // Start address of the address map
|
||||
|
||||
parameter C_END_ADDRESS = 32'hFFFF_FFFF, // End address of the address map
|
||||
|
||||
parameter CTL_SIG_WIDTH = 2, // Control signal width
|
||||
|
||||
parameter WR_STS_WIDTH = 16, // Write port status signal width
|
||||
|
||||
parameter RD_STS_WIDTH = 16, // Read port status signal width
|
||||
|
||||
parameter EN_UPSIZER = 0, // There is no upsizer code
|
||||
|
||||
parameter WDG_TIMER_WIDTH = 9
|
||||
|
||||
)
|
||||
(
|
||||
input aclk, // AXI input clock
|
||||
input aresetn, // Active low AXI reset signal
|
||||
|
||||
// User interface command port
|
||||
|
||||
input cmd_en, // Asserted to indicate a valid command
|
||||
// and address
|
||||
input [2:0] cmd, // Write or read command
|
||||
// 000 - READ with INCR bursts
|
||||
// 001 - READ with WRAP bursts
|
||||
// 01x - Reserved
|
||||
// 100 - WRITE with INCR bursts
|
||||
// 101 - WRITE with WRAP bursts
|
||||
input [7:0] blen, // Burst length calculated as blen+1
|
||||
input [31:0] addr, // Address for the read or the write
|
||||
// transaction
|
||||
input [CTL_SIG_WIDTH-1:0] ctl, // control command for read or write
|
||||
// transaction
|
||||
input wdog_mask, // Mask the watchdog timeouts
|
||||
output cmd_ack,// Indicates the command has been accepted
|
||||
|
||||
// User interface write ports
|
||||
|
||||
input wrdata_vld, // Asserted to indicate a valid write
|
||||
// data
|
||||
input [C_AXI_DATA_WIDTH-1:0] wrdata, // Write data
|
||||
input [C_AXI_DATA_WIDTH/8-1:0] wrdata_bvld, // Byte valids for the write data
|
||||
input wrdata_cmptd,// Last data to be transferred
|
||||
output reg wrdata_rdy, // Indicates that the write data is
|
||||
// ready to be accepted
|
||||
output reg wrdata_sts_vld, // Indicates a write status after
|
||||
// completion of a write transfer
|
||||
output [WR_STS_WIDTH-1:0] wrdata_sts, // Status of the write transaction
|
||||
|
||||
// User interface read ports
|
||||
|
||||
input rddata_rdy, // Data ready to be accepted
|
||||
output reg rddata_vld, // Indicates a valid read data available
|
||||
output reg [C_AXI_DATA_WIDTH-1:0] rddata, // Read data
|
||||
output [C_AXI_DATA_WIDTH/8-1:0] rddata_bvld, // Byte valids for read data
|
||||
output reg rddata_cmptd, // Indicates last data present and
|
||||
// valid status
|
||||
output [RD_STS_WIDTH-1:0] rddata_sts, // Status of the read transaction
|
||||
|
||||
// AXI write address channel signals
|
||||
|
||||
input axi_wready, // Indicates slave is ready to accept a
|
||||
// write address
|
||||
output [C_AXI_ID_WIDTH-1:0] axi_wid, // Write ID
|
||||
output [C_AXI_ADDR_WIDTH-1:0] axi_waddr, // Write address
|
||||
output [7:0] axi_wlen, // Write Burst Length
|
||||
output [2:0] axi_wsize, // Write Burst size
|
||||
output [1:0] axi_wburst, // Write Burst type
|
||||
output [1:0] axi_wlock, // Write lock type
|
||||
output [3:0] axi_wcache, // Write Cache type
|
||||
output [2:0] axi_wprot, // Write Protection type
|
||||
output reg axi_wvalid, // Write address valid
|
||||
|
||||
// AXI write data channel signals
|
||||
|
||||
input axi_wd_wready, // Write data ready
|
||||
output [C_AXI_ID_WIDTH-1:0] axi_wd_wid, // Write ID tag
|
||||
output reg [C_AXI_DATA_WIDTH-1:0] axi_wd_data, // Write data
|
||||
output reg [C_AXI_DATA_WIDTH/8-1:0] axi_wd_strb, // Write strobes
|
||||
output reg axi_wd_last, // Last write transaction
|
||||
output axi_wd_valid, // Write valid
|
||||
|
||||
// AXI write response channel signals
|
||||
input [C_AXI_ID_WIDTH-1:0] axi_wd_bid, // Response ID
|
||||
input [1:0] axi_wd_bresp, // Write response
|
||||
input axi_wd_bvalid, // Write reponse valid
|
||||
output reg axi_wd_bready, // Response ready
|
||||
|
||||
// AXI read address channel signals
|
||||
input axi_rready, // Read address ready
|
||||
output [C_AXI_ID_WIDTH-1:0] axi_rid, // Read ID
|
||||
output [C_AXI_ADDR_WIDTH-1:0] axi_raddr, // Read address
|
||||
output [7:0] axi_rlen, // Read Burst Length
|
||||
output [2:0] axi_rsize, // Read Burst size
|
||||
output [1:0] axi_rburst, // Read Burst type
|
||||
output [1:0] axi_rlock, // Read lock type
|
||||
output [3:0] axi_rcache, // Read Cache type
|
||||
output [2:0] axi_rprot, // Read Protection type
|
||||
output reg axi_rvalid, // Read address valid
|
||||
|
||||
// AXI read data channel signals
|
||||
input [C_AXI_ID_WIDTH-1:0] axi_rd_bid, // Response ID
|
||||
input [1:0] axi_rd_rresp, // Read response
|
||||
input axi_rd_rvalid, // Read reponse valid
|
||||
input [C_AXI_DATA_WIDTH-1:0] axi_rd_data, // Read data
|
||||
input axi_rd_last, // Read last
|
||||
output reg axi_rd_rready // Read Response ready
|
||||
);
|
||||
|
||||
//*****************************************************************************
|
||||
// Internal parameter declarations
|
||||
//*****************************************************************************
|
||||
|
||||
parameter [8:0] AXI_WRIDLE = 9'd0,
|
||||
AXI_WRCTL = 9'd1,
|
||||
AXI_WRRDY = 9'd2,
|
||||
AXI_WRDAT = 9'd3,
|
||||
AXI_WRDAT_WT = 9'd4,
|
||||
AXI_WRDAT_LST = 9'd5,
|
||||
AXI_WRDAT_DMY = 9'd6,
|
||||
AXI_WRRESP_WT = 9'd7,
|
||||
AXI_WRTO = 9'd8;
|
||||
|
||||
parameter [5:0] AXI_RDIDLE = 6'd0,
|
||||
AXI_RDCTL = 6'd1,
|
||||
AXI_RDDAT = 6'd2,
|
||||
AXI_RDDAT_LST = 6'd3,
|
||||
AXI_RDDAT_WT = 6'd4,
|
||||
AXI_RDTO = 6'd5;
|
||||
|
||||
//*****************************************************************************
|
||||
// Internal register and wire declarations
|
||||
//*****************************************************************************
|
||||
|
||||
reg wrap_w;
|
||||
reg [7:0] blen_w;
|
||||
reg [7:0] blen_w_minus_1;
|
||||
reg [C_AXI_ADDR_WIDTH-1:0] addr_w;
|
||||
reg [CTL_SIG_WIDTH-1:0] ctl_w;
|
||||
reg wrap_r;
|
||||
reg [7:0] blen_r;
|
||||
reg [C_AXI_ADDR_WIDTH-1:0] addr_r;
|
||||
reg [CTL_SIG_WIDTH-1:0] ctl_r;
|
||||
reg [8:0] wstate;
|
||||
reg [8:0] next_wstate;
|
||||
reg wr_cmd_start;
|
||||
reg [WDG_TIMER_WIDTH-1:0] wr_wdog_cntr;
|
||||
reg wrdata_vld_r;
|
||||
reg wrdata_cmptd_r;
|
||||
reg [7:0] wr_len_cntr;
|
||||
reg [7:0] rd_len_cntr;
|
||||
reg [7:0] blen_cntr;
|
||||
reg [3:0] wr_cntr;
|
||||
reg [C_AXI_DATA_WIDTH-1:0] wrdata_r1;
|
||||
reg [C_AXI_DATA_WIDTH-1:0] wrdata_r2;
|
||||
reg wrdata_mux_ctrl;
|
||||
reg [2:0] wrdata_fsm_sts;
|
||||
reg [3:0] brespid_r;
|
||||
reg [1:0] bresp_r;
|
||||
|
||||
reg [5:0] rstate;
|
||||
reg [5:0] next_rstate;
|
||||
reg [WDG_TIMER_WIDTH-1:0] rd_wdog_cntr;
|
||||
reg rd_cmd_start;
|
||||
reg rlast;
|
||||
reg [3:0] rd_cntr;
|
||||
reg rddata_ppld;
|
||||
reg [C_AXI_DATA_WIDTH-1:0] rddata_p1;
|
||||
reg err_resp;
|
||||
reg [1:0] rddata_fsm_sts;
|
||||
reg rrid_err;
|
||||
reg pending_one_trans;
|
||||
reg axi_wready_l;
|
||||
|
||||
wire wr_cmd_timeout;
|
||||
wire wr_done;
|
||||
wire wr_last;
|
||||
|
||||
wire rd_cmd_timeout;
|
||||
|
||||
//*****************************************************************************
|
||||
// Address and control register logic
|
||||
//*****************************************************************************
|
||||
|
||||
always @(posedge aclk) begin
|
||||
if (!aresetn) begin
|
||||
wrap_w <= 1'b0;
|
||||
blen_w <= 8'h0;
|
||||
blen_w_minus_1 <= 8'h0;
|
||||
addr_w <= {C_AXI_ADDR_WIDTH{1'b0}};
|
||||
ctl_w <= {CTL_SIG_WIDTH{1'b0}};
|
||||
end
|
||||
else if (wstate[AXI_WRIDLE] & next_wstate[AXI_WRIDLE] &
|
||||
cmd_en & cmd[2]) begin
|
||||
wrap_w <= cmd[0];
|
||||
blen_w <= blen;
|
||||
blen_w_minus_1 <= blen - 8'h01;
|
||||
addr_w <= addr;
|
||||
ctl_w <= ctl;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge aclk) begin
|
||||
if (!aresetn) begin
|
||||
wrap_r <= 1'b0;
|
||||
blen_r <= 8'h0;
|
||||
addr_r <= {C_AXI_ADDR_WIDTH{1'b0}};
|
||||
ctl_r <= {CTL_SIG_WIDTH{1'b0}};
|
||||
end
|
||||
else if (rstate[AXI_RDIDLE] & next_rstate[AXI_RDIDLE] &
|
||||
cmd_en & !cmd[2]) begin
|
||||
wrap_r <= cmd[0];
|
||||
blen_r <= blen;
|
||||
addr_r <= addr;
|
||||
ctl_r <= ctl;
|
||||
end
|
||||
end
|
||||
|
||||
assign cmd_ack = (wstate[AXI_WRIDLE] & next_wstate[AXI_WRCTL]) |
|
||||
(rstate[AXI_RDIDLE] & next_rstate[AXI_RDCTL]);
|
||||
|
||||
//*****************************************************************************
|
||||
// Write data state machine control signals
|
||||
//*****************************************************************************
|
||||
|
||||
always @(posedge aclk)
|
||||
if (!aresetn)
|
||||
wr_cmd_start <= 1'b0;
|
||||
else if (cmd_en & cmd[2] & wstate[AXI_WRIDLE])
|
||||
wr_cmd_start <= 1'b1;
|
||||
else if (wstate[AXI_WRCTL])
|
||||
wr_cmd_start <= 1'b0;
|
||||
|
||||
always @(posedge aclk)
|
||||
if (wstate[AXI_WRIDLE] |
|
||||
(axi_wd_wready & (wstate[AXI_WRDAT] | wstate[AXI_WRDAT_WT] | wstate[AXI_WRDAT_LST] | wstate[AXI_WRDAT_DMY])) |
|
||||
(axi_wd_bvalid & wstate[AXI_WRRESP_WT]))
|
||||
wr_wdog_cntr <= 'h0;
|
||||
else if (!wstate[AXI_WRTO] & !wdog_mask)
|
||||
wr_wdog_cntr <= wr_wdog_cntr + 'h1;
|
||||
|
||||
always @(posedge aclk)
|
||||
wrdata_vld_r <= wrdata_vld;
|
||||
|
||||
always @(posedge aclk)
|
||||
if (wstate[AXI_WRIDLE])
|
||||
wrdata_cmptd_r <= 1'b0;
|
||||
else if (wrdata_cmptd & wrdata_vld)
|
||||
wrdata_cmptd_r <= 1'b1;
|
||||
|
||||
always @(posedge aclk)
|
||||
if (wstate[AXI_WRIDLE])
|
||||
blen_cntr <= 8'h0;
|
||||
else if (wrdata_vld & wrdata_rdy)
|
||||
blen_cntr <= blen_cntr + 8'h01;
|
||||
|
||||
always @(posedge aclk)
|
||||
if (wstate[AXI_WRIDLE])
|
||||
pending_one_trans <= 1'b0;
|
||||
else if (next_wstate[AXI_WRDAT] & wstate[AXI_WRDAT_WT])
|
||||
pending_one_trans <= 1'b0;
|
||||
else if (wstate[AXI_WRDAT] & next_wstate[AXI_WRDAT_WT] & wr_last & !axi_wd_wready)
|
||||
pending_one_trans <= 1'b1;
|
||||
|
||||
always @(posedge aclk)
|
||||
if (wstate[AXI_WRIDLE])
|
||||
wr_len_cntr <= 8'h0;
|
||||
else if ((wstate[AXI_WRDAT_DMY] | wstate[AXI_WRDAT] | wstate[AXI_WRDAT_WT]) &
|
||||
axi_wd_valid & axi_wd_wready)
|
||||
wr_len_cntr <= wr_len_cntr + 8'h01;
|
||||
|
||||
always @(posedge aclk)
|
||||
if (wstate[AXI_WRIDLE])
|
||||
axi_wready_l <= 1'b0;
|
||||
else if (axi_wready)
|
||||
axi_wready_l <= 1'b1;
|
||||
|
||||
assign wr_cmd_timeout = wr_wdog_cntr[WDG_TIMER_WIDTH-1] & !wdog_mask;
|
||||
assign wr_last = (wr_len_cntr >= blen_w_minus_1);
|
||||
assign wr_done = (blen_cntr >= blen_w);
|
||||
|
||||
//*****************************************************************************
|
||||
// Write data state machine
|
||||
//*****************************************************************************
|
||||
|
||||
always @(posedge aclk) begin
|
||||
if (!aresetn)
|
||||
wstate <= 9'h1;
|
||||
else
|
||||
wstate <= next_wstate;
|
||||
end
|
||||
|
||||
always @(*) begin
|
||||
next_wstate = 9'h0;
|
||||
case (1'b1)
|
||||
wstate[AXI_WRIDLE]: begin // 9'h001
|
||||
if (wr_cmd_start)
|
||||
next_wstate[AXI_WRCTL] = 1'b1;
|
||||
else
|
||||
next_wstate[AXI_WRIDLE] = 1'b1;
|
||||
end
|
||||
wstate[AXI_WRCTL]: begin // 9'h002
|
||||
if (wr_cmd_timeout)
|
||||
next_wstate[AXI_WRTO] = 1'b1;
|
||||
else if (axi_wvalid)
|
||||
next_wstate[AXI_WRRDY] = 1'b1;
|
||||
else
|
||||
next_wstate[AXI_WRCTL] = 1'b1;
|
||||
end
|
||||
wstate[AXI_WRRDY]: begin // 9'h004
|
||||
if (wrdata_cmptd_r & wrdata_rdy)
|
||||
next_wstate[AXI_WRDAT_LST] = 1'b1;
|
||||
else if (wrdata_vld_r & wrdata_rdy)
|
||||
next_wstate[AXI_WRDAT] = 1'b1;
|
||||
else
|
||||
next_wstate[AXI_WRRDY] = 1'b1;
|
||||
end
|
||||
wstate[AXI_WRDAT]: begin // 9'h008
|
||||
if (wr_cmd_timeout)
|
||||
next_wstate[AXI_WRTO] = 1'b1;
|
||||
else if (axi_wd_wready & wrdata_cmptd_r & (wr_last | ~(|blen_w)))
|
||||
next_wstate[AXI_WRDAT_LST] = 1'b1;
|
||||
else if (axi_wd_wready & wrdata_cmptd_r & !wr_done &
|
||||
(wr_len_cntr != 8'h00))
|
||||
next_wstate[AXI_WRDAT_DMY] = 1'b1;
|
||||
else if (!axi_wd_wready)
|
||||
next_wstate[AXI_WRDAT_WT] = 1'b1;
|
||||
else
|
||||
next_wstate[AXI_WRDAT] = 1'b1;
|
||||
end
|
||||
wstate[AXI_WRDAT_WT]: begin // 9'h010
|
||||
if (wr_cmd_timeout)
|
||||
next_wstate[AXI_WRTO] = 1'b1;
|
||||
else if (axi_wd_wready) begin
|
||||
if (pending_one_trans & wrdata_cmptd_r & (wr_last | ~(|blen_w)))
|
||||
next_wstate[AXI_WRDAT_LST] = 1'b1;
|
||||
else if (!pending_one_trans & wrdata_cmptd_r & !wr_done &
|
||||
(wr_len_cntr != 8'h00))
|
||||
next_wstate[AXI_WRDAT_DMY] = 1'b1;
|
||||
else
|
||||
next_wstate[AXI_WRDAT] = 1'b1;
|
||||
end
|
||||
else
|
||||
next_wstate[AXI_WRDAT_WT] = 1'b1;
|
||||
end
|
||||
wstate[AXI_WRDAT_LST]: begin // 9'h020
|
||||
if (wr_cmd_timeout)
|
||||
next_wstate[AXI_WRTO] = 1'b1;
|
||||
else if (axi_wd_valid & axi_wd_wready)
|
||||
next_wstate[AXI_WRRESP_WT] = 1'b1;
|
||||
else
|
||||
next_wstate[AXI_WRDAT_LST] = 1'b1;
|
||||
end
|
||||
wstate[AXI_WRDAT_DMY]: begin // 9'h040
|
||||
if (wr_cmd_timeout)
|
||||
next_wstate[AXI_WRTO] = 1'b1;
|
||||
else if (wrdata_cmptd_r & wr_last)
|
||||
next_wstate[AXI_WRDAT_LST] = 1'b1;
|
||||
else if (!wr_last & !axi_wd_wready)
|
||||
next_wstate[AXI_WRDAT_WT] = 1'b1;
|
||||
else
|
||||
next_wstate[AXI_WRDAT_DMY] = 1'b1;
|
||||
end
|
||||
wstate[AXI_WRRESP_WT]: begin // 9'h080
|
||||
if (wr_cmd_timeout)
|
||||
next_wstate[AXI_WRTO] = 1'b1;
|
||||
else if (axi_wd_bvalid &
|
||||
(EN_UPSIZER == 1 || (EN_UPSIZER == 0 & axi_wready_l)))
|
||||
next_wstate[AXI_WRIDLE] = 1'b1;
|
||||
else
|
||||
next_wstate[AXI_WRRESP_WT] = 1'b1;
|
||||
end
|
||||
wstate[AXI_WRTO]: begin // 9'h100
|
||||
next_wstate[AXI_WRIDLE] = 1'b1;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
//*****************************************************************************
|
||||
// Write channel control signals
|
||||
//*****************************************************************************
|
||||
|
||||
always @(posedge aclk)
|
||||
if (!aresetn)
|
||||
wr_cntr <= 4'h0;
|
||||
else if (wstate[AXI_WRRESP_WT] & next_wstate[AXI_WRIDLE])
|
||||
wr_cntr <= wr_cntr + 4'h1;
|
||||
|
||||
always @(posedge aclk)
|
||||
if (!aresetn)
|
||||
axi_wvalid <= 1'b0;
|
||||
else if ((wstate[AXI_WRCTL] & next_wstate[AXI_WRRDY] & axi_wready) ||
|
||||
(axi_wready & !wstate[AXI_WRCTL]))
|
||||
axi_wvalid <= 1'b0;
|
||||
else if (wstate[AXI_WRCTL])
|
||||
axi_wvalid <= 1'b1;
|
||||
|
||||
assign awid = wr_cntr;
|
||||
|
||||
assign axi_waddr = addr_w;
|
||||
assign axi_wid = wr_cntr;
|
||||
assign axi_wlen = blen_w;
|
||||
assign axi_wburst = {1'b0, wrap_w} + 2'b01;
|
||||
assign axi_wsize = ctl_w[2:0];
|
||||
|
||||
// Not supported and hence assigned zeros
|
||||
assign axi_wlock = 2'b0;
|
||||
assign axi_wcache = 4'b0;
|
||||
assign axi_wprot = 3'b0;
|
||||
|
||||
//*****************************************************************************
|
||||
// Write channel data signals
|
||||
//*****************************************************************************
|
||||
|
||||
always @(posedge aclk) begin
|
||||
if (wstate[AXI_WRIDLE]) begin
|
||||
wrdata_r1 <= 'h0;
|
||||
wrdata_r2 <= 'h0;
|
||||
end
|
||||
else if (wrdata_rdy & wrdata_vld & (wstate[AXI_WRDAT] | wstate[AXI_WRRDY] |
|
||||
wstate[AXI_WRDAT_LST])) begin
|
||||
wrdata_r1 <= wrdata;
|
||||
wrdata_r2 <= wrdata_r1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge aclk)
|
||||
if (!aresetn)
|
||||
wrdata_rdy <= 1'b0;
|
||||
else if (wstate[AXI_WRDAT_LST] | (wstate[AXI_WRDAT] & next_wstate[AXI_WRDAT_WT]))
|
||||
wrdata_rdy <= 1'b0;
|
||||
else if (wstate[AXI_WRDAT] |
|
||||
(wstate[AXI_WRCTL] & next_wstate[AXI_WRRDY]) |
|
||||
(wstate[AXI_WRDAT_WT] & next_wstate[AXI_WRDAT]))
|
||||
wrdata_rdy <= 1'b1;
|
||||
|
||||
always @(posedge aclk)
|
||||
if (!aresetn)
|
||||
wrdata_sts_vld <= 1'b0;
|
||||
else if (wstate[AXI_WRIDLE])
|
||||
wrdata_sts_vld <= 1'b0;
|
||||
else if ((wstate[AXI_WRRESP_WT] | wstate[AXI_WRTO]) & next_wstate[AXI_WRIDLE])
|
||||
wrdata_sts_vld <= 1'b1;
|
||||
|
||||
always @(posedge aclk)
|
||||
if (!aresetn)
|
||||
wrdata_mux_ctrl <= 1'b0;
|
||||
else if ((wstate[AXI_WRDAT_WT] & (next_wstate[AXI_WRDAT] | next_wstate[AXI_WRDAT_LST])) |
|
||||
wstate[AXI_WRIDLE])
|
||||
wrdata_mux_ctrl <= 1'b0;
|
||||
else if (wstate[AXI_WRDAT] & next_wstate[AXI_WRDAT_WT] & !pending_one_trans)
|
||||
wrdata_mux_ctrl <= 1'b1;
|
||||
|
||||
always @(posedge aclk)
|
||||
if (!aresetn)
|
||||
axi_wd_last <= 1'b0;
|
||||
else if (wstate[AXI_WRDAT_LST] & next_wstate[AXI_WRRESP_WT])
|
||||
axi_wd_last <= 1'b0;
|
||||
else if ((wstate[AXI_WRDAT] | wstate[AXI_WRDAT_DMY] | wstate[AXI_WRRDY] | wstate[AXI_WRDAT_WT]) &
|
||||
next_wstate[AXI_WRDAT_LST])
|
||||
axi_wd_last <= 1'b1;
|
||||
|
||||
generate
|
||||
begin: data_axi_wr
|
||||
if (C_AXI_NBURST_SUPPORT != 1) begin
|
||||
|
||||
always @(posedge aclk)
|
||||
if (wstate[AXI_WRIDLE])
|
||||
axi_wd_data <= 'h0;
|
||||
else if (axi_wd_wready & (wstate[AXI_WRDAT] | wstate[AXI_WRDAT_WT]) & wrdata_mux_ctrl &
|
||||
~next_wstate[AXI_WRDAT_LST])
|
||||
axi_wd_data <= wrdata_r2;
|
||||
else if ((axi_wd_wready & (wstate[AXI_WRDAT] |
|
||||
(wstate[AXI_WRDAT_WT] & next_wstate[AXI_WRDAT_LST]) |
|
||||
(wstate[AXI_WRDAT_LST] & !next_wstate[AXI_WRRESP_WT]))) |
|
||||
(wstate[AXI_WRRDY] & next_wstate[AXI_WRDAT]))
|
||||
axi_wd_data <= wrdata_r1;
|
||||
|
||||
always @(posedge aclk)
|
||||
if (wstate[AXI_WRIDLE])
|
||||
axi_wd_strb <= {(C_AXI_DATA_WIDTH/8){1'b0}};
|
||||
else if ((axi_wd_wready & (wstate[AXI_WRDAT] |
|
||||
(next_wstate[AXI_WRDAT_LST] & (wstate[AXI_WRRDY] | wstate[AXI_WRDAT])) |
|
||||
((wstate[AXI_WRRDY] | wstate[AXI_WRDAT_WT]) &
|
||||
next_wstate[AXI_WRDAT]))) |
|
||||
(next_wstate[AXI_WRDAT_LST] & !axi_wd_wready &
|
||||
(wstate[AXI_WRDAT] | wstate[AXI_WRDAT_LST] |
|
||||
wstate[AXI_WRDAT_DMY] | wstate[AXI_WRDAT_WT])) |
|
||||
(wstate[AXI_WRRDY] & next_wstate[AXI_WRDAT]) |
|
||||
((wstate[AXI_WRDAT] | wstate[AXI_WRDAT_DMY]) & next_wstate[AXI_WRDAT_WT]) |
|
||||
(wstate[AXI_WRDAT_WT]))
|
||||
axi_wd_strb <= {(C_AXI_DATA_WIDTH/8){1'b1}};
|
||||
else
|
||||
axi_wd_strb <= {(C_AXI_DATA_WIDTH/8){1'b0}};
|
||||
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
assign axi_wd_wid = wr_cntr;
|
||||
assign axi_wd_valid = wstate[AXI_WRDAT] | wstate[AXI_WRDAT_LST] |
|
||||
wstate[AXI_WRDAT_DMY] | wstate[AXI_WRDAT_WT];
|
||||
|
||||
//*****************************************************************************
|
||||
// Write response and status signals
|
||||
//*****************************************************************************
|
||||
|
||||
always @(posedge aclk)
|
||||
if (!aresetn)
|
||||
axi_wd_bready <= 1'b0;
|
||||
else if (next_wstate[AXI_WRIDLE] & wstate[AXI_WRRESP_WT])
|
||||
axi_wd_bready <= 1'b0;
|
||||
else if (wstate[AXI_WRRESP_WT])
|
||||
axi_wd_bready <= 1'b1;
|
||||
|
||||
always @(posedge aclk)
|
||||
if (wstate[AXI_WRIDLE])
|
||||
wrdata_fsm_sts <= 3'b000;
|
||||
else begin
|
||||
if (next_wstate[AXI_WRTO]) begin
|
||||
if (wstate[AXI_WRDAT])
|
||||
wrdata_fsm_sts <= 3'b001;
|
||||
else if (wstate[AXI_WRDAT_WT])
|
||||
wrdata_fsm_sts <= 3'b010;
|
||||
else if (wstate[AXI_WRDAT_DMY])
|
||||
wrdata_fsm_sts <= 3'b011;
|
||||
else if (wstate[AXI_WRRESP_WT])
|
||||
wrdata_fsm_sts <= 3'b100;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge aclk)
|
||||
if (wstate[AXI_WRIDLE]) begin
|
||||
brespid_r <= 4'h0;
|
||||
bresp_r <= 2'b00;
|
||||
end
|
||||
else if (wstate[AXI_WRRESP_WT] & axi_wd_bvalid) begin
|
||||
brespid_r <= axi_wd_bid;
|
||||
bresp_r <= axi_wd_bresp;
|
||||
end
|
||||
|
||||
assign wrdata_sts = {{{WR_STS_WIDTH-8}{1'b0}},wrdata_fsm_sts,brespid_r[3:0],bresp_r};
|
||||
|
||||
//*****************************************************************************
|
||||
// Read data state machine control signals
|
||||
//*****************************************************************************
|
||||
|
||||
always @(posedge aclk)
|
||||
if (rstate[AXI_RDIDLE] | axi_rready | axi_rd_rvalid)
|
||||
rd_wdog_cntr <= 'h0;
|
||||
else if (!rstate[AXI_RDTO])
|
||||
rd_wdog_cntr <= rd_wdog_cntr + 'h1;
|
||||
|
||||
always @(posedge aclk)
|
||||
if (!aresetn)
|
||||
rd_cmd_start <= 1'b0;
|
||||
else if (cmd_en & !cmd[2] & rstate[AXI_RDIDLE])
|
||||
rd_cmd_start <= 1'b1;
|
||||
else if (rstate[AXI_RDCTL])
|
||||
rd_cmd_start <= 1'b0;
|
||||
|
||||
always @(posedge aclk)
|
||||
if (rstate[AXI_RDIDLE])
|
||||
rlast <= 1'b0;
|
||||
else if (axi_rd_last & axi_rd_rvalid)
|
||||
rlast <= 1'b1;
|
||||
|
||||
assign rd_cmd_timeout = rd_wdog_cntr[WDG_TIMER_WIDTH-1] & !wdog_mask;
|
||||
|
||||
//*****************************************************************************
|
||||
// Read data state machine
|
||||
//*****************************************************************************
|
||||
|
||||
always @(posedge aclk) begin
|
||||
if (!aresetn)
|
||||
rstate <= 6'h1;
|
||||
else
|
||||
rstate <= next_rstate;
|
||||
end
|
||||
|
||||
always @(*) begin
|
||||
next_rstate = 6'h0;
|
||||
case (1'b1)
|
||||
rstate[AXI_RDIDLE]: begin // 6'h01
|
||||
if (rd_cmd_start)
|
||||
next_rstate[AXI_RDCTL] = 1'b1;
|
||||
else
|
||||
next_rstate[AXI_RDIDLE] = 1'b1;
|
||||
end
|
||||
rstate[AXI_RDCTL]: begin // 6'h02
|
||||
if (rd_cmd_timeout)
|
||||
next_rstate[AXI_RDTO] = 1'b1;
|
||||
else if (axi_rready & axi_rvalid) begin
|
||||
if (rddata_rdy)
|
||||
next_rstate[AXI_RDDAT] = 1'b1;
|
||||
else
|
||||
next_rstate[AXI_RDDAT_WT] = 1'b1;
|
||||
end
|
||||
else
|
||||
next_rstate[AXI_RDCTL] = 1'b1;
|
||||
end
|
||||
rstate[AXI_RDDAT]: begin // 6'h04
|
||||
if (rd_cmd_timeout)
|
||||
next_rstate[AXI_RDTO] = 1'b1;
|
||||
else if (rddata_rdy) begin
|
||||
if (rlast)
|
||||
next_rstate[AXI_RDDAT_LST] = 1'b1;
|
||||
else
|
||||
next_rstate[AXI_RDDAT] = 1'b1;
|
||||
end
|
||||
else
|
||||
next_rstate[AXI_RDDAT_WT] = 1'b1;
|
||||
end
|
||||
rstate[AXI_RDDAT_LST]: begin // 6'h08
|
||||
if (rddata_cmptd & rddata_vld & rddata_rdy)
|
||||
next_rstate[AXI_RDIDLE] = 1'b1;
|
||||
else
|
||||
next_rstate[AXI_RDDAT_LST] = 1'b1;
|
||||
end
|
||||
rstate[AXI_RDDAT_WT]: begin // 6'h10
|
||||
if (rddata_rdy) begin
|
||||
if (rlast)
|
||||
next_rstate[AXI_RDDAT_LST] = 1'b1;
|
||||
else
|
||||
next_rstate[AXI_RDDAT] = 1'b1;
|
||||
end
|
||||
else
|
||||
next_rstate[AXI_RDDAT_WT] = 1'b1;
|
||||
end
|
||||
rstate[AXI_RDTO]: begin // 6'h20
|
||||
next_rstate[AXI_RDIDLE] = 1'b1;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
//*****************************************************************************
|
||||
// Read Address control signals
|
||||
//*****************************************************************************
|
||||
|
||||
always @(posedge aclk)
|
||||
if (!aresetn)
|
||||
rd_cntr <= 4'h0;
|
||||
else if (rstate[AXI_RDDAT_LST] & next_rstate[AXI_RDIDLE])
|
||||
rd_cntr <= rd_cntr + 4'h1;
|
||||
|
||||
always @(posedge aclk)
|
||||
if (!aresetn)
|
||||
axi_rvalid <= 1'b0;
|
||||
else if (rstate[AXI_RDCTL] & next_rstate[AXI_RDDAT])
|
||||
axi_rvalid <= 1'b0;
|
||||
else if (rstate[AXI_RDCTL])
|
||||
axi_rvalid <= 1'b1;
|
||||
|
||||
assign axi_rid = rd_cntr;
|
||||
|
||||
generate
|
||||
begin: addr_axi_rd
|
||||
if (C_AXI_DATA_WIDTH == 256)
|
||||
assign axi_raddr = {addr_r[C_AXI_ADDR_WIDTH-1:5], 5'b0};
|
||||
else if (C_AXI_DATA_WIDTH == 128)
|
||||
assign axi_raddr = {addr_r[C_AXI_ADDR_WIDTH-1:4], 4'b0};
|
||||
else if (C_AXI_DATA_WIDTH == 64)
|
||||
assign axi_raddr = {addr_r[C_AXI_ADDR_WIDTH-1:3], 3'b0};
|
||||
else
|
||||
assign axi_raddr = {addr_r[C_AXI_ADDR_WIDTH-1:2], 2'b0};
|
||||
end
|
||||
endgenerate
|
||||
|
||||
assign axi_rlen = blen_r;
|
||||
assign axi_rburst = {1'b0, wrap_r} + 2'b01;
|
||||
assign axi_rsize = ctl_r[2:0];
|
||||
|
||||
// Not supported and hence assigned zeros
|
||||
assign axi_rlock = 2'b0;
|
||||
assign axi_rcache = 4'b0;
|
||||
assign axi_rprot = 3'b0;
|
||||
|
||||
//*****************************************************************************
|
||||
// Read channel data signals
|
||||
//*****************************************************************************
|
||||
|
||||
always @(posedge aclk)
|
||||
if (!aresetn)
|
||||
rddata_vld <= 1'b0;
|
||||
else if ((rddata_vld & !axi_rd_rvalid & rstate[AXI_RDDAT]) |
|
||||
(rddata_rdy & rstate[AXI_RDDAT_LST]) |
|
||||
(rstate[AXI_RDDAT_WT] & next_rstate[AXI_RDDAT] & rddata_ppld) |
|
||||
(rddata_rdy & axi_rd_rvalid & axi_rd_last) |
|
||||
rstate[AXI_RDIDLE])
|
||||
rddata_vld <= 1'b0;
|
||||
else if ((rstate[AXI_RDDAT] & axi_rd_rvalid & !axi_rd_last) |
|
||||
((rstate[AXI_RDDAT] | rstate[AXI_RDDAT_WT]) & next_rstate[AXI_RDDAT_LST] & rlast) |
|
||||
(rstate[AXI_RDDAT_LST] & axi_rd_rvalid & axi_rd_last & axi_rd_rready) |
|
||||
rstate[AXI_RDTO])
|
||||
rddata_vld <= 1'b1;
|
||||
|
||||
always @(posedge aclk)
|
||||
if (!aresetn)
|
||||
rddata_ppld <= 1'b0;
|
||||
else if (rddata_vld & rddata_rdy)
|
||||
rddata_ppld <= 1'b0;
|
||||
else if (!rddata_vld & axi_rd_rvalid & axi_rd_rready & rstate[AXI_RDDAT_WT])
|
||||
rddata_ppld <= 1'b1;
|
||||
|
||||
always @(posedge aclk)
|
||||
if (!aresetn)
|
||||
axi_rd_rready <= 1'b0;
|
||||
else if (rstate[AXI_RDIDLE] |
|
||||
(rstate[AXI_RDDAT] & next_rstate[AXI_RDDAT_WT]) |
|
||||
(rstate[AXI_RDDAT_WT] & !next_rstate[AXI_RDDAT] & rddata_ppld) |
|
||||
(next_rstate[AXI_RDDAT_LST] & (rstate[AXI_RDDAT] | rstate[AXI_RDDAT_WT])))
|
||||
axi_rd_rready <= 1'b0;
|
||||
else if ((next_rstate[AXI_RDDAT] & (rstate[AXI_RDCTL] | rstate[AXI_RDDAT_WT])) |
|
||||
(next_rstate[AXI_RDDAT_LST] & rstate[AXI_RDDAT_WT] & rddata_ppld) |
|
||||
(rstate[AXI_RDDAT_WT] & !rddata_ppld) |
|
||||
(rstate[AXI_RDDAT_LST] & axi_rd_rvalid & axi_rd_last))
|
||||
axi_rd_rready <= 1'b1;
|
||||
|
||||
always @(posedge aclk)
|
||||
if (axi_rd_rvalid)
|
||||
rddata_p1 <= axi_rd_data;
|
||||
|
||||
generate
|
||||
begin: data_axi_rd
|
||||
if (C_AXI_NBURST_SUPPORT == 1) begin
|
||||
end
|
||||
else begin
|
||||
|
||||
always @(posedge aclk)
|
||||
if (axi_rd_rvalid & !rddata_ppld)
|
||||
rddata <= axi_rd_data;
|
||||
else if (rddata_rdy & rddata_vld & rddata_ppld)
|
||||
rddata <= rddata_p1;
|
||||
|
||||
assign rddata_bvld = {{C_AXI_DATA_WIDTH/32}{4'hF}};
|
||||
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
always @(posedge aclk)
|
||||
if (!aresetn)
|
||||
rddata_cmptd <= 1'b0;
|
||||
else if ((next_rstate[AXI_RDIDLE] & rstate[AXI_RDDAT_LST]) |
|
||||
rstate[AXI_RDIDLE])
|
||||
rddata_cmptd <= 1'b0;
|
||||
else if (((rstate[AXI_RDDAT] | rstate[AXI_RDDAT_WT]) & next_rstate[AXI_RDDAT_LST] & rlast) |
|
||||
(rstate[AXI_RDDAT_LST] & axi_rd_rvalid & axi_rd_last & axi_rd_rready) |
|
||||
rstate[AXI_RDTO])
|
||||
rddata_cmptd <= 1'b1;
|
||||
|
||||
always @(posedge aclk)
|
||||
if (rstate[AXI_RDIDLE])
|
||||
err_resp <= 1'b0;
|
||||
else if (axi_rd_rvalid & axi_rd_rresp[1])
|
||||
err_resp <= 1'b1;
|
||||
|
||||
always @(posedge aclk)
|
||||
if (rstate[AXI_RDIDLE] & next_rstate[AXI_RDCTL])
|
||||
rddata_fsm_sts <= 2'b00;
|
||||
else if (rstate[AXI_RDCTL] & next_rstate[AXI_RDTO])
|
||||
rddata_fsm_sts <= 2'b01;
|
||||
else if (rstate[AXI_RDDAT] & next_rstate[AXI_RDTO])
|
||||
rddata_fsm_sts <= 2'b10;
|
||||
|
||||
always @(posedge aclk)
|
||||
if (rstate[AXI_RDIDLE] & next_rstate[AXI_RDCTL])
|
||||
rrid_err <= 1'b0;
|
||||
else if (axi_rd_rvalid & axi_rd_bid != rd_cntr)
|
||||
rrid_err <= 1'b1;
|
||||
|
||||
always @(posedge aclk)
|
||||
if (rstate[AXI_RDIDLE])
|
||||
rd_len_cntr <= 8'h0;
|
||||
else if (axi_rd_rvalid & axi_rd_rready)
|
||||
rd_len_cntr <= rd_len_cntr + 8'h01;
|
||||
|
||||
assign rddata_sts = {{(RD_STS_WIDTH-12){1'b0}},rd_len_cntr,rddata_fsm_sts,rrid_err,err_resp};
|
||||
|
||||
// synthesis translate_off
|
||||
always @(posedge aclk) begin
|
||||
if (rd_cmd_timeout)
|
||||
$display ("ERR: Read timeout occured at time %t", $time);
|
||||
if (wr_cmd_timeout)
|
||||
$display ("ERR: Write timeout occured at time %t", $time);
|
||||
end
|
||||
// synthesis translate_on
|
||||
|
||||
endmodule
|
||||
+250
@@ -0,0 +1,250 @@
|
||||
//*****************************************************************************
|
||||
// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
//*****************************************************************************
|
||||
// ____ ____
|
||||
// / /\/ /
|
||||
// /___/ \ / Vendor: Xilinx
|
||||
// \ \ \/ Version: %version
|
||||
// \ \ Application: MIG
|
||||
// / / Filename: cmd_prbs_gen.v
|
||||
// /___/ /\ Date Last Modified:
|
||||
// \ \ / \ Date Created:
|
||||
// \___\/\___\
|
||||
//
|
||||
//Device: Spartan6
|
||||
//Design Name: DDR/DDR2/DDR3/LPDDR
|
||||
//Purpose: This moduel use LFSR to generate random address, isntructions
|
||||
// or burst_length.
|
||||
//Reference:
|
||||
//Revision History: 1.1 Added condition to zero out the LSB address bits according to
|
||||
// DWIDTH and FAMILY. 7/9/2009
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
`timescale 1ps/1ps
|
||||
|
||||
module mig_7series_v4_2_cmd_prbs_gen_axi #
|
||||
(
|
||||
parameter TCQ = 100,
|
||||
parameter FAMILY = "SPARTAN6",
|
||||
parameter ADDR_WIDTH = 29,
|
||||
parameter DWIDTH = 32,
|
||||
parameter PRBS_CMD = "ADDRESS", // "INSTR", "BLEN","ADDRESS"
|
||||
parameter PRBS_WIDTH = 64, // 64,15,20
|
||||
parameter SEED_WIDTH = 32, // 32,15,4
|
||||
|
||||
parameter PRBS_EADDR_MASK_POS = 32'hFFFFD000,
|
||||
parameter PRBS_SADDR_MASK_POS = 32'h00002000,
|
||||
parameter PRBS_EADDR = 32'h00002000,
|
||||
parameter PRBS_SADDR = 32'h00002000
|
||||
)
|
||||
(
|
||||
input clk_i,
|
||||
input prbs_seed_init, // when high the prbs_x_seed will be loaded
|
||||
input clk_en,
|
||||
input [SEED_WIDTH-1:0] prbs_seed_i,
|
||||
output[SEED_WIDTH-1:0] prbs_o // generated address
|
||||
);
|
||||
|
||||
wire[ADDR_WIDTH - 1:0] ZEROS;
|
||||
reg [SEED_WIDTH - 1:0] prbs;
|
||||
reg [PRBS_WIDTH :1] lfsr_q;
|
||||
|
||||
assign ZEROS = 'b0;
|
||||
//
|
||||
//**************************************************************
|
||||
//####################################################################################################################
|
||||
// #
|
||||
// #
|
||||
// 64 taps: [64,63,61,60]: {{8'b01011000}, {56'b0}} #
|
||||
// upper 32 bits are loadable #
|
||||
// #
|
||||
//
|
||||
//
|
||||
// ........................................................................................
|
||||
// ^ ^ ^ ^ |
|
||||
// | ____ | ___ ___ | ___ | ___ ___ ___ |
|
||||
// | | | |---|<- | | | | |---|<- | | |---|<- | |...| | | | | The first 32 bits are parallel loadable.
|
||||
// ----|64 |<--|xor|<-- |63 |-->|62 |-|xor|<--|61 |<-|xor|<--|60 |...|33 |<--|1|<<--
|
||||
// |___| --- |___| |___| --- |___| --- |___|...|___| |___|
|
||||
//
|
||||
//
|
||||
// <<-- shifting --
|
||||
//#####################################################################################################################
|
||||
|
||||
// use SRLC32E for lower 32 stages and 32 registers for upper 32 stages.
|
||||
// we need to provide 30 bits addres. SRLC32 has only one bit output.
|
||||
// address seed will be loaded to upper 32 bits.
|
||||
//
|
||||
// parallel load and serial shift out to LFSR during INIT time
|
||||
|
||||
generate
|
||||
if(PRBS_CMD == "ADDRESS" && PRBS_WIDTH == 64) begin :gen64_taps
|
||||
always @ (posedge clk_i) begin
|
||||
if(prbs_seed_init) begin//reset it to a known good state to prevent it locks up
|
||||
lfsr_q <= #TCQ {31'b0,prbs_seed_i};
|
||||
end else if(clk_en) begin
|
||||
lfsr_q[64] <= #TCQ lfsr_q[64] ^ lfsr_q[63];
|
||||
lfsr_q[63] <= #TCQ lfsr_q[62];
|
||||
lfsr_q[62] <= #TCQ lfsr_q[64] ^ lfsr_q[61];
|
||||
lfsr_q[61] <= #TCQ lfsr_q[64] ^ lfsr_q[60];
|
||||
lfsr_q[60:2] <= #TCQ lfsr_q[59:1];
|
||||
lfsr_q[1] <= #TCQ lfsr_q[64];
|
||||
end
|
||||
end
|
||||
|
||||
always @(lfsr_q[32:1]) begin
|
||||
prbs = lfsr_q[32:1];
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
function integer logb2;
|
||||
input [31:0] in;
|
||||
integer i;
|
||||
begin
|
||||
i = in;
|
||||
for(logb2=1; i>0; logb2=logb2+1)
|
||||
i = i >> 1;
|
||||
end
|
||||
endfunction
|
||||
|
||||
generate
|
||||
if(PRBS_CMD == "ADDRESS" && PRBS_WIDTH == 32) begin :gen32_taps
|
||||
always @ (posedge clk_i) begin
|
||||
if(prbs_seed_init) begin //reset it to a known good state to prevent it locks up
|
||||
lfsr_q <= #TCQ {prbs_seed_i};
|
||||
end else if(clk_en) begin
|
||||
lfsr_q[32:9] <= #TCQ lfsr_q[31:8];
|
||||
lfsr_q[8] <= #TCQ lfsr_q[32] ^ lfsr_q[7];
|
||||
lfsr_q[7] <= #TCQ lfsr_q[32] ^ lfsr_q[6];
|
||||
lfsr_q[6:4] <= #TCQ lfsr_q[5:3];
|
||||
|
||||
lfsr_q[3] <= #TCQ lfsr_q[32] ^ lfsr_q[2];
|
||||
lfsr_q[2] <= #TCQ lfsr_q[1] ;
|
||||
lfsr_q[1] <= #TCQ lfsr_q[32];
|
||||
end
|
||||
end
|
||||
|
||||
integer i;
|
||||
always @(lfsr_q[32:1]) begin
|
||||
|
||||
if (FAMILY == "SPARTAN6" ) begin // for 32 bits
|
||||
|
||||
for(i = logb2(DWIDTH) + 1; i <= SEED_WIDTH - 1; i = i + 1)
|
||||
|
||||
if(PRBS_SADDR_MASK_POS[i] == 1)
|
||||
prbs[i] = PRBS_SADDR[i] | lfsr_q[i+1];
|
||||
else if(PRBS_EADDR_MASK_POS[i] == 1)
|
||||
prbs[i] = PRBS_EADDR[i] & lfsr_q[i+1];
|
||||
else
|
||||
prbs[i] = lfsr_q[i+1];
|
||||
|
||||
prbs[logb2(DWIDTH ) :0] = {logb2(DWIDTH ) + 1{1'b0}};
|
||||
|
||||
end
|
||||
else begin
|
||||
for(i = logb2(DWIDTH)-4; i <= SEED_WIDTH - 1; i = i + 1)
|
||||
if(PRBS_SADDR_MASK_POS[i] == 1)
|
||||
prbs[i] = PRBS_SADDR[i] | lfsr_q[i+1];
|
||||
else if(PRBS_EADDR_MASK_POS[i] == 1)
|
||||
prbs[i] = PRBS_EADDR[i] & lfsr_q[i+1];
|
||||
else
|
||||
prbs[i] = lfsr_q[i+1];
|
||||
prbs[logb2(DWIDTH)-5:0] = {logb2(DWIDTH) - 4{1'b0}};
|
||||
|
||||
end
|
||||
|
||||
end
|
||||
end endgenerate
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////
|
||||
//####################################################################################################################
|
||||
// #
|
||||
// #
|
||||
// 15 taps: [15,14]: #
|
||||
// #
|
||||
// #
|
||||
//
|
||||
//
|
||||
// .............................................................
|
||||
// ^ ^ . ^
|
||||
// | ____ | ___ ___ ___ ___ ___ |
|
||||
// | | | |---|<- | | | | | |...| | | | |
|
||||
// ----|15 |<--|xor|<-- |14 |<--|13 |<--|12 |...|2 |<--|1 |<<--
|
||||
// |___| --- |___| |___| |___|...|___| |___|
|
||||
//
|
||||
//
|
||||
// <<-- shifting --
|
||||
//#####################################################################################################################
|
||||
|
||||
generate
|
||||
if(PRBS_CMD == "INSTR" | PRBS_CMD == "BLEN") begin :gen20_taps
|
||||
always @(posedge clk_i) begin
|
||||
if(prbs_seed_init) begin//reset it to a known good state to prevent it locks up
|
||||
lfsr_q <= #TCQ {5'b0,prbs_seed_i[14:0]};
|
||||
end else if(clk_en) begin
|
||||
lfsr_q[20] <= #TCQ lfsr_q[19];
|
||||
lfsr_q[19] <= #TCQ lfsr_q[18];
|
||||
|
||||
lfsr_q[18] <= #TCQ lfsr_q[20] ^lfsr_q[17];
|
||||
|
||||
lfsr_q[17:2] <= #TCQ lfsr_q[16:1];
|
||||
lfsr_q[1] <= #TCQ lfsr_q[20];
|
||||
end
|
||||
end
|
||||
|
||||
always @ (lfsr_q) begin
|
||||
prbs = lfsr_q[32:1];
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
assign prbs_o = prbs;
|
||||
|
||||
endmodule
|
||||
+193
@@ -0,0 +1,193 @@
|
||||
//*****************************************************************************
|
||||
// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
//*****************************************************************************
|
||||
// ____ ____
|
||||
// / /\/ /
|
||||
// /___/ \ / Vendor: Xilinx
|
||||
// \ \ \/ Version: %version
|
||||
// \ \ Application: MIG
|
||||
// / / Filename: data_gen_chk.v
|
||||
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:37:19 $
|
||||
// \ \ / \ Date Created: Fri Sep 01 2006
|
||||
// \___\/\___\
|
||||
//
|
||||
//Device: Virtex6/Spartan6/7series
|
||||
//Design Name: DDR/DDR2/DDR3/LPDDR
|
||||
//Purpose: This module is used LFSR to generate random data for memory
|
||||
// data write or memory data read comparison. This always
|
||||
// generates 32-bit data only. This also checks the received
|
||||
// data
|
||||
//Reference:
|
||||
//Revision History:
|
||||
//*****************************************************************************
|
||||
`timescale 1ps/1ps
|
||||
|
||||
module mig_7series_v4_2_data_gen_chk # (
|
||||
|
||||
parameter C_AXI_DATA_WIDTH = 32 // Width of the AXI write and read data
|
||||
|
||||
)
|
||||
(
|
||||
input clk,
|
||||
input data_en,
|
||||
input [2:0] data_pattern,
|
||||
input pattern_init, // when high the patterns are initialized
|
||||
input [31:0] prbs_seed_i,
|
||||
input [C_AXI_DATA_WIDTH-1:0] rdata,
|
||||
input [C_AXI_DATA_WIDTH/8-1:0] rdata_bvld,
|
||||
input rdata_vld,
|
||||
input wrd_cntr_rst,
|
||||
output msmatch_err, // Indicates there is a mismatch error
|
||||
output reg [7:0] wrd_cntr, // Word count output
|
||||
output reg [31:0] data_o // generated data
|
||||
);
|
||||
|
||||
reg [31:0] prbs;
|
||||
reg [32:1] lfsr_q;
|
||||
reg [31:0] walk0;
|
||||
reg [31:0] walk1;
|
||||
reg [C_AXI_DATA_WIDTH/32-1:0] msmatch_err_sig;
|
||||
|
||||
//*****************************************************************************
|
||||
// Data generate segment
|
||||
//*****************************************************************************
|
||||
|
||||
always @ (posedge clk) begin
|
||||
if (pattern_init) begin
|
||||
lfsr_q <= {prbs_seed_i + 32'h55555555};
|
||||
end
|
||||
else if (data_en) begin
|
||||
lfsr_q[32:9] <= lfsr_q[31:8];
|
||||
lfsr_q[8] <= lfsr_q[32] ^ lfsr_q[7];
|
||||
lfsr_q[7] <= lfsr_q[32] ^ lfsr_q[6];
|
||||
lfsr_q[6:4] <= lfsr_q[5:3];
|
||||
|
||||
lfsr_q[3] <= lfsr_q[32] ^ lfsr_q[2];
|
||||
lfsr_q[2] <= lfsr_q[1] ;
|
||||
lfsr_q[1] <= lfsr_q[32];
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk)
|
||||
if (pattern_init)
|
||||
walk0 <= 32'hFFFF_FFFE;
|
||||
else if (data_en)
|
||||
walk0 <= {walk0[30:0],walk0[31]};
|
||||
|
||||
always @(posedge clk)
|
||||
if (pattern_init)
|
||||
walk1 <= 32'h0000_0001;
|
||||
else if (data_en)
|
||||
walk1 <= {walk1[30:0],walk1[31]};
|
||||
|
||||
always @(*) begin
|
||||
prbs = lfsr_q[32:1];
|
||||
end
|
||||
|
||||
always @(*) begin
|
||||
case (data_pattern)
|
||||
3'b001: data_o = prbs; // PRBS pattern
|
||||
3'b010: data_o = walk0; // Walking zeros
|
||||
3'b011: data_o = walk1; // Walking ones
|
||||
3'b100: data_o = 32'hFFFF_FFFF; // All ones
|
||||
3'b101: data_o = 32'h0000_0000; // All zeros
|
||||
default: data_o = 32'h5A5A_A5A5;
|
||||
endcase
|
||||
end
|
||||
|
||||
//*****************************************************************************
|
||||
// Data check segment
|
||||
//*****************************************************************************
|
||||
|
||||
always @(posedge clk)
|
||||
if (wrd_cntr_rst)
|
||||
wrd_cntr <= 8'h00;
|
||||
else if (rdata_vld)
|
||||
wrd_cntr <= wrd_cntr + 8'h01;
|
||||
|
||||
genvar i;
|
||||
generate
|
||||
begin: data_check
|
||||
for (i = 0; i <= (C_AXI_DATA_WIDTH/32-1); i=i+1) begin: gen_data_check
|
||||
always @(posedge clk)
|
||||
if (wrd_cntr_rst)
|
||||
msmatch_err_sig[i] <= 1'b0;
|
||||
else if (rdata_vld &
|
||||
((rdata[((i*32)+7):i*32] != data_o[7:0] & rdata_bvld[(i*4)]) |
|
||||
(rdata[((i*32)+15):((i*32)+8)] != data_o[15:8] & rdata_bvld[(i*4)+1]) |
|
||||
(rdata[((i*32)+23):((i*32)+16)] != data_o[23:16] & rdata_bvld[(i*4)+2]) |
|
||||
(rdata[((i*32)+31):((i*32)+24)] != data_o[31:24] & rdata_bvld[(i*4)+3])))
|
||||
msmatch_err_sig[i] <= 1'b1;
|
||||
else
|
||||
msmatch_err_sig[i] <= 1'b0;
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
assign msmatch_err = |msmatch_err_sig;
|
||||
|
||||
// synthesis translate_off
|
||||
//*****************************************************************************
|
||||
// Simulation debug signals and messages
|
||||
//*****************************************************************************
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rdata_vld & ({{C_AXI_DATA_WIDTH/32}{data_o}} !== rdata)) begin
|
||||
$display ("[ERROR] : Written data and read data does not match");
|
||||
$display ("Data written : %h", {{C_AXI_DATA_WIDTH/32}{data_o}});
|
||||
$display ("Data read : %h", rdata);
|
||||
$display ("Word number : %h", wrd_cntr);
|
||||
$display ("Simulation time : %t", $time);
|
||||
end
|
||||
end
|
||||
|
||||
// synthesis translate_on
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
+780
@@ -0,0 +1,780 @@
|
||||
//*****************************************************************************
|
||||
// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
//*****************************************************************************
|
||||
// ____ ____
|
||||
// / /\/ /
|
||||
// /___/ \ / Vendor: Xilinx
|
||||
// \ \ \/ Version: 3.6
|
||||
// \ \ Application: MIG
|
||||
// / / Filename: tg.v
|
||||
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:37:24 $
|
||||
// \ \ / \ Date Created: Sept 16, 2009
|
||||
// \___\/\___\
|
||||
//
|
||||
//Device: Virtex-6, Spartan-6 and 7series
|
||||
//Design Name: DDR3 SDRAM
|
||||
//Purpose:
|
||||
// This module generates and checks the AXI traffic
|
||||
//
|
||||
//Reference:
|
||||
//Revision History:
|
||||
//*****************************************************************************
|
||||
`timescale 1ps/1ps
|
||||
|
||||
module mig_7series_v4_2_tg #(
|
||||
|
||||
parameter C_AXI_ADDR_WIDTH = 32, // This is AXI address width for all
|
||||
// SI and MI slots
|
||||
parameter C_AXI_DATA_WIDTH = 32, // Width of the AXI write and read data
|
||||
|
||||
parameter C_AXI_NBURST_SUPPORT = 0, // Support for narrow burst transfers
|
||||
// 1-supported, 0-not supported
|
||||
parameter C_BEGIN_ADDRESS = 32'h0, // Start address of the address map
|
||||
|
||||
parameter C_END_ADDRESS = 32'h0000_00FF, // End address of the address map
|
||||
|
||||
parameter C_EN_WRAP_TRANS = 0, // Should be set to 1 for wrap transactions
|
||||
|
||||
parameter CTL_SIG_WIDTH = 3, // Control signal width
|
||||
|
||||
parameter WR_STS_WIDTH = 16, // Write port status signal width
|
||||
|
||||
parameter RD_STS_WIDTH = 16, // Read port status signal width
|
||||
|
||||
parameter DBG_WR_STS_WIDTH = 40,
|
||||
|
||||
parameter DBG_RD_STS_WIDTH = 40,
|
||||
|
||||
parameter ENFORCE_RD_WR = 0,
|
||||
|
||||
parameter ENFORCE_RD_WR_CMD = 8'h11,
|
||||
|
||||
parameter PRBS_EADDR_MASK_POS = 32'hFFFFD000,
|
||||
|
||||
parameter PRBS_SADDR_MASK_POS = 32'h00002000,
|
||||
|
||||
parameter ENFORCE_RD_WR_PATTERN = 3'b000
|
||||
|
||||
)
|
||||
(
|
||||
input clk, // input clock
|
||||
input resetn, // Active low reset signal
|
||||
|
||||
// Input start signals
|
||||
input init_cmptd, // Initialization completed
|
||||
input init_test, // Initialize the test
|
||||
input wrap_en, // Enable wrap transactions
|
||||
|
||||
// Control ports
|
||||
input cmd_ack, // Command has been accepted
|
||||
output reg cmd_en, // Command enable
|
||||
output [2:0] cmd, // Command
|
||||
output reg [7:0] blen, // Length of the burst
|
||||
output reg [31:0] addr, // output address
|
||||
output [CTL_SIG_WIDTH-1:0] ctl, // Control signal
|
||||
|
||||
// Write port
|
||||
input wdata_rdy, // Write data ready to be accepted
|
||||
output wdata_vld, // Write data valid
|
||||
output reg wdata_cmptd, // Write data completed
|
||||
output [C_AXI_DATA_WIDTH-1:0] wdata, // Write data
|
||||
output [C_AXI_DATA_WIDTH/8-1:0] wdata_bvld, // Byte valids
|
||||
input wdata_sts_vld, // Status valid
|
||||
input [WR_STS_WIDTH-1:0] wdata_sts, // Write status
|
||||
|
||||
// Read Port
|
||||
input rdata_vld, // Read data valid
|
||||
input [C_AXI_DATA_WIDTH-1:0] rdata, // Write data
|
||||
input [C_AXI_DATA_WIDTH/8-1:0] rdata_bvld, // Byte valids
|
||||
input rdata_cmptd, // Read data completed
|
||||
input [RD_STS_WIDTH-1:0] rdata_sts, // Read status
|
||||
output rdata_rdy, // Read data ready
|
||||
|
||||
// Error status signals
|
||||
output reg cmd_err, // Error during command phase
|
||||
output reg data_msmatch_err, // Data mismatch
|
||||
output reg write_err, // Write error occured
|
||||
output reg read_err, // Read error occured
|
||||
output test_cmptd, // Completed testing with all patterns
|
||||
output write_cmptd, // Completed write operation
|
||||
output read_cmptd, // Completed write operation
|
||||
|
||||
// Debug status signals
|
||||
output cmp_data_en,
|
||||
output [C_AXI_DATA_WIDTH-1:0] rdata_cmp, // read data
|
||||
output reg dbg_wr_sts_vld, // Write debug status valid,
|
||||
output [DBG_WR_STS_WIDTH-1:0] dbg_wr_sts, // Write status
|
||||
output reg dbg_rd_sts_vld, // Read debug status valid
|
||||
output [DBG_RD_STS_WIDTH-1:0] dbg_rd_sts // Read status
|
||||
);
|
||||
|
||||
//*****************************************************************************
|
||||
// Internal parameter declarations
|
||||
//*****************************************************************************
|
||||
|
||||
parameter [8:0] TG_IDLE = 8'd0,
|
||||
TG_GEN_PRBS = 8'd1,
|
||||
TG_WR_CMD = 8'd2,
|
||||
TG_WR_DATA = 8'd3,
|
||||
TG_WR_DONE = 8'd4,
|
||||
TG_RD_CMD = 8'd5,
|
||||
TG_RD_DATA = 8'd6,
|
||||
TG_UPDT_CNTR = 8'd7;
|
||||
|
||||
//*****************************************************************************
|
||||
// Internal wire and reg declarations
|
||||
//*****************************************************************************
|
||||
|
||||
wire [2:0] data_pattern;
|
||||
wire dgen_en;
|
||||
wire dgen_init;
|
||||
wire [31:0] prbs_seed;
|
||||
wire msmatch_err;
|
||||
wire [31:0] prbs_data;
|
||||
wire [31:0] prbs_blen;
|
||||
wire [7:0] prbs_blen_mdfy;
|
||||
wire [31:0] prbs_addr;
|
||||
wire [31:0] prbs_addr_mdfy;
|
||||
wire cmd_gen_csr_sig;
|
||||
wire rdata_sig_vld;
|
||||
wire wdata_sig_vld;
|
||||
reg [7:0] rd_mismatch_wrd_cntr_r;
|
||||
wire [7:0] rd_wrd_cntr;
|
||||
reg [7:0] wr_wrd_cntr;
|
||||
reg [7:0] rd_wrd_cntr_r;
|
||||
reg [7:0] wr_wrd_cntr_r;
|
||||
wire wrd_cntr_rst;
|
||||
wire w_burst_4;
|
||||
wire w_burst_8;
|
||||
wire w_burst_16;
|
||||
|
||||
reg [7:0] tg_state;
|
||||
reg [7:0] next_tg_state;
|
||||
reg [2:0] shft_cntr;
|
||||
reg [2:0] seed_cntr;
|
||||
reg cmd_vld;
|
||||
reg [7:0] blen_cntr;
|
||||
reg wr_proc;
|
||||
reg curr_wr_ptr;
|
||||
reg curr_rd_ptr;
|
||||
reg [31:0] curr_addr1;
|
||||
reg [31:0] curr_addr2;
|
||||
reg [7:0] curr_blen1;
|
||||
reg [7:0] curr_blen2;
|
||||
reg cmd_wr_en;
|
||||
reg cmd_wr_en_r;
|
||||
reg cmd_rd_en;
|
||||
reg [7:0] cmd_gen_csr;
|
||||
reg cmd_err_dbg;
|
||||
reg data_msmatch_err_dbg;
|
||||
reg write_err_dbg;
|
||||
reg read_err_dbg;
|
||||
reg [WR_STS_WIDTH-1:0] wdata_sts_r; // Write status registered
|
||||
reg [RD_STS_WIDTH-1:0] rdata_sts_r; // Read status registered
|
||||
|
||||
//*****************************************************************************
|
||||
// FSM Control Block
|
||||
//*****************************************************************************
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (!resetn | init_test)
|
||||
tg_state <= 8'h1;
|
||||
else
|
||||
tg_state <= next_tg_state;
|
||||
end
|
||||
|
||||
always @(*) begin
|
||||
next_tg_state = 8'h0;
|
||||
case (1'b1)
|
||||
tg_state[TG_IDLE]: begin // 8'h01
|
||||
if (init_cmptd)
|
||||
next_tg_state[TG_GEN_PRBS] = 1'b1;
|
||||
else
|
||||
next_tg_state[TG_IDLE] = 1'b1;
|
||||
end
|
||||
tg_state[TG_GEN_PRBS]: begin // 8'h02
|
||||
if (cmd_vld) begin
|
||||
if (cmd_gen_csr_sig)
|
||||
next_tg_state[TG_WR_CMD] = 1'b1;
|
||||
else
|
||||
next_tg_state[TG_RD_CMD] = 1'b1;
|
||||
end else
|
||||
next_tg_state[TG_GEN_PRBS] = 1'b1;
|
||||
end
|
||||
tg_state[TG_WR_CMD]: begin // 8'h04
|
||||
if (wdata_sts_vld) begin
|
||||
if (&shft_cntr)
|
||||
next_tg_state[TG_UPDT_CNTR] = 1'b1;
|
||||
else
|
||||
next_tg_state[TG_GEN_PRBS] = 1'b1;
|
||||
end
|
||||
else if (wdata_rdy)
|
||||
next_tg_state[TG_WR_DATA] = 1'b1;
|
||||
else
|
||||
next_tg_state[TG_WR_CMD] = 1'b1;
|
||||
end
|
||||
tg_state[TG_WR_DATA]: begin // 8'h08
|
||||
if (wdata_sts_vld) begin
|
||||
if (&shft_cntr)
|
||||
next_tg_state[TG_UPDT_CNTR] = 1'b1;
|
||||
else
|
||||
next_tg_state[TG_GEN_PRBS] = 1'b1;
|
||||
end
|
||||
else if (blen_cntr == 8'h0 & wdata_rdy)
|
||||
next_tg_state[TG_WR_DONE] = 1'b1;
|
||||
else
|
||||
next_tg_state[TG_WR_DATA] = 1'b1;
|
||||
end
|
||||
tg_state[TG_WR_DONE]: begin // 8'h10
|
||||
if (wdata_sts_vld) begin
|
||||
if (&shft_cntr)
|
||||
next_tg_state[TG_UPDT_CNTR] = 1'b1;
|
||||
else
|
||||
next_tg_state[TG_GEN_PRBS] = 1'b1;
|
||||
end
|
||||
else
|
||||
next_tg_state[TG_WR_DONE] = 1'b1;
|
||||
end
|
||||
tg_state[TG_RD_CMD]: begin // 8'h20
|
||||
if (rdata_cmptd) begin
|
||||
if (&shft_cntr)
|
||||
next_tg_state[TG_UPDT_CNTR] = 1'b1;
|
||||
else
|
||||
next_tg_state[TG_GEN_PRBS] = 1'b1;
|
||||
end
|
||||
else if (cmd_ack)
|
||||
next_tg_state[TG_RD_DATA] = 1'b1;
|
||||
else
|
||||
next_tg_state[TG_RD_CMD] = 1'b1;
|
||||
end
|
||||
tg_state[TG_RD_DATA]: begin // 8'h040
|
||||
if (rdata_cmptd & rdata_vld & rdata_rdy) begin
|
||||
if (&shft_cntr)
|
||||
next_tg_state[TG_UPDT_CNTR] = 1'b1;
|
||||
else
|
||||
next_tg_state[TG_GEN_PRBS] = 1'b1;
|
||||
end
|
||||
else
|
||||
next_tg_state[TG_RD_DATA] = 1'b1;
|
||||
end
|
||||
tg_state[TG_UPDT_CNTR]: begin // 8'h80
|
||||
if (&seed_cntr)
|
||||
next_tg_state[TG_IDLE] = 1'b1;
|
||||
else
|
||||
next_tg_state[TG_GEN_PRBS] = 1'b1;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
//*****************************************************************************
|
||||
// Control Signals
|
||||
//*****************************************************************************
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (!resetn)
|
||||
cmd_wr_en <= 1'b0;
|
||||
else if (next_tg_state[TG_WR_CMD] & tg_state[TG_GEN_PRBS])
|
||||
cmd_wr_en <= 1'b1;
|
||||
else
|
||||
cmd_wr_en <= 1'b0;
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (!resetn)
|
||||
cmd_rd_en <= 1'b0;
|
||||
else if (next_tg_state[TG_RD_CMD] & tg_state[TG_GEN_PRBS])
|
||||
cmd_rd_en <= 1'b1;
|
||||
else
|
||||
cmd_rd_en <= 1'b0;
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (tg_state[TG_IDLE] | tg_state[TG_UPDT_CNTR])
|
||||
curr_wr_ptr <= 1'b0;
|
||||
else if (cmd_wr_en)
|
||||
curr_wr_ptr <= ~curr_wr_ptr;
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (tg_state[TG_IDLE] | tg_state[TG_UPDT_CNTR])
|
||||
curr_rd_ptr <= 1'b0;
|
||||
else if (cmd_rd_en)
|
||||
curr_rd_ptr <= ~curr_rd_ptr;
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (!resetn)
|
||||
cmd_vld <= 1'b0;
|
||||
else if (tg_state[TG_WR_CMD] | tg_state[TG_RD_CMD])
|
||||
cmd_vld <= 1'b0;
|
||||
else if (tg_state[TG_GEN_PRBS])
|
||||
cmd_vld <= 1'b1;
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (tg_state[TG_IDLE])
|
||||
wr_proc <= 1'b0;
|
||||
else if (cmd_wr_en)
|
||||
wr_proc <= 1'b1;
|
||||
else if (cmd_rd_en)
|
||||
wr_proc <= 1'b0;
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (tg_state[TG_IDLE] | tg_state[TG_UPDT_CNTR])
|
||||
shft_cntr <= 3'b000;
|
||||
else if (tg_state[TG_GEN_PRBS] & (next_tg_state[TG_WR_CMD] |
|
||||
next_tg_state[TG_RD_CMD]))
|
||||
shft_cntr <= shft_cntr + 3'b001;
|
||||
end
|
||||
|
||||
always @(posedge clk)
|
||||
cmd_wr_en_r <= cmd_wr_en;
|
||||
|
||||
assign prbs_seed = {{10{seed_cntr}}, 2'b10};
|
||||
assign dgen_init = next_tg_state[TG_GEN_PRBS] & !tg_state[TG_GEN_PRBS];
|
||||
assign agen_init = next_tg_state[TG_GEN_PRBS] & (tg_state[TG_IDLE] | tg_state[TG_UPDT_CNTR]);
|
||||
assign cgen_init = next_tg_state[TG_GEN_PRBS] & (tg_state[TG_IDLE] | tg_state[TG_UPDT_CNTR]);
|
||||
assign data_pattern = (ENFORCE_RD_WR == 1) ? ENFORCE_RD_WR_PATTERN :
|
||||
seed_cntr;
|
||||
assign dgen_en = wr_proc ? (tg_state[TG_WR_DATA] & wdata_rdy) :
|
||||
(tg_state[TG_RD_DATA] & rdata_vld) ;
|
||||
assign wrd_cntr_rst = tg_state[TG_GEN_PRBS] | tg_state[TG_IDLE];
|
||||
|
||||
//*****************************************************************************
|
||||
// Data Generation, FIFO, Checker and Data Sizer block
|
||||
//*****************************************************************************
|
||||
|
||||
mig_7series_v4_2_data_gen_chk #
|
||||
(
|
||||
|
||||
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH)
|
||||
|
||||
) data_gen_chk_inst
|
||||
(
|
||||
.clk (clk),
|
||||
.data_en (dgen_en),
|
||||
.data_pattern (data_pattern),
|
||||
.pattern_init (dgen_init),
|
||||
.prbs_seed_i (prbs_seed),
|
||||
.rdata (rdata),
|
||||
.rdata_bvld (rdata_bvld),
|
||||
.rdata_vld (rdata_sig_vld),
|
||||
.msmatch_err (msmatch_err),
|
||||
.wrd_cntr_rst (wrd_cntr_rst),
|
||||
.wrd_cntr (rd_wrd_cntr),
|
||||
.data_o (prbs_data)
|
||||
);
|
||||
|
||||
assign rdata_rdy = tg_state[TG_RD_DATA];
|
||||
|
||||
assign rdata_sig_vld = wr_proc ? 1'b0 : (rdata_vld & tg_state[TG_RD_DATA]);
|
||||
assign wdata_sig_vld = wr_proc ? (wdata_vld & tg_state[TG_WR_DATA]) : 1'b0;
|
||||
|
||||
|
||||
//*****************************************************************************
|
||||
// Command generation
|
||||
//*****************************************************************************
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (tg_state[TG_IDLE])
|
||||
seed_cntr <= 3'b000;
|
||||
else if (next_tg_state[TG_UPDT_CNTR] &
|
||||
(tg_state[TG_WR_DATA] | tg_state[TG_WR_DONE] |
|
||||
tg_state[TG_WR_CMD] | tg_state[TG_RD_CMD] |
|
||||
tg_state[TG_RD_DATA] ))
|
||||
seed_cntr <= seed_cntr + 3'b001;
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (tg_state[TG_IDLE] | tg_state[TG_UPDT_CNTR]) begin
|
||||
if (ENFORCE_RD_WR == 1)
|
||||
cmd_gen_csr <= ENFORCE_RD_WR_CMD;
|
||||
else
|
||||
cmd_gen_csr <= {seed_cntr, 1'b1, seed_cntr, 1'b1};
|
||||
end
|
||||
else if (next_tg_state[TG_GEN_PRBS] &
|
||||
(tg_state[TG_WR_CMD] | tg_state[TG_WR_DATA] |
|
||||
tg_state[TG_RD_DATA] | tg_state[TG_RD_CMD] |
|
||||
tg_state[TG_WR_DONE]))
|
||||
cmd_gen_csr <= cmd_gen_csr >> 1;
|
||||
end
|
||||
|
||||
assign cmd_gen_csr_sig = cmd_gen_csr[0];
|
||||
|
||||
//*****************************************************************************
|
||||
// Burst Length generation PRBS
|
||||
//*****************************************************************************
|
||||
|
||||
mig_7series_v4_2_cmd_prbs_gen_axi #
|
||||
(
|
||||
.PRBS_CMD ("BLEN"),
|
||||
.PRBS_WIDTH (32), // 64,15,20
|
||||
.SEED_WIDTH (32), // 32,15,4
|
||||
.ADDR_WIDTH (C_AXI_ADDR_WIDTH)
|
||||
) blen_gen_inst
|
||||
(
|
||||
.clk_i (clk),
|
||||
.prbs_seed_init (cgen_init),
|
||||
.clk_en (cmd_wr_en_r),
|
||||
.prbs_seed_i (prbs_seed),
|
||||
.prbs_o (prbs_blen)
|
||||
);
|
||||
|
||||
assign w_burst_4 = (|prbs_blen[7:2]);
|
||||
assign w_burst_8 = (|prbs_blen[7:3]);
|
||||
assign w_burst_16 = (|prbs_blen[7:4]);
|
||||
assign prbs_blen_mdfy = (C_EN_WRAP_TRANS == 1 && wrap_en) ? {4'h0, w_burst_16, w_burst_8,
|
||||
w_burst_4, 1'b1} : prbs_blen[7:0];
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (tg_state[TG_IDLE]) begin
|
||||
curr_blen1 <= 8'h0;
|
||||
curr_blen2 <= 8'h0;
|
||||
end
|
||||
else if (cmd_wr_en) begin
|
||||
if (curr_wr_ptr)
|
||||
curr_blen2 <= prbs_blen_mdfy;
|
||||
else
|
||||
curr_blen1 <= prbs_blen_mdfy;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (tg_state[TG_IDLE] | (next_tg_state[TG_GEN_PRBS] & !tg_state[TG_GEN_PRBS]))
|
||||
blen_cntr <= 8'h00;
|
||||
else if (tg_state[TG_GEN_PRBS] & next_tg_state[TG_GEN_PRBS])
|
||||
blen_cntr <= prbs_blen_mdfy;
|
||||
else if (tg_state[TG_WR_DATA] & wdata_rdy & (blen_cntr != 8'h00))
|
||||
blen_cntr <= blen_cntr - 8'h01;
|
||||
end
|
||||
|
||||
//*****************************************************************************
|
||||
// Address generation PRBS
|
||||
//*****************************************************************************
|
||||
|
||||
mig_7series_v4_2_cmd_prbs_gen_axi #
|
||||
(
|
||||
.FAMILY ("VIRTEX7"),
|
||||
.ADDR_WIDTH (C_AXI_ADDR_WIDTH),
|
||||
.PRBS_CMD ("ADDRESS"), // "INSTR", "BLEN","ADDRESS"
|
||||
.PRBS_WIDTH (32), // 64,15,20
|
||||
.SEED_WIDTH (32), // 32,15,4
|
||||
.PRBS_EADDR_MASK_POS (PRBS_EADDR_MASK_POS),
|
||||
.PRBS_SADDR_MASK_POS (PRBS_SADDR_MASK_POS),
|
||||
.PRBS_EADDR (C_END_ADDRESS),
|
||||
.PRBS_SADDR (C_BEGIN_ADDRESS)
|
||||
) addr_gen_inst
|
||||
(
|
||||
.clk_i (clk),
|
||||
.prbs_seed_init (agen_init),
|
||||
.clk_en (cmd_wr_en_r),
|
||||
.prbs_seed_i (prbs_seed),
|
||||
.prbs_o (prbs_addr)
|
||||
);
|
||||
|
||||
generate
|
||||
begin: addr_axi_wr
|
||||
if (C_AXI_DATA_WIDTH == 256)
|
||||
assign prbs_addr_mdfy = prbs_addr[31:0] & 32'hffff_ffe0;
|
||||
else if (C_AXI_DATA_WIDTH == 128)
|
||||
assign prbs_addr_mdfy = prbs_addr[31:0] & 32'hffff_fff0;
|
||||
else if (C_AXI_DATA_WIDTH == 64)
|
||||
assign prbs_addr_mdfy = prbs_addr[31:0] & 32'hffff_fff8;
|
||||
else
|
||||
assign prbs_addr_mdfy = prbs_addr[31:0] & 32'hffff_fffc;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (tg_state[TG_IDLE]) begin
|
||||
curr_addr1 <= 32'h0;
|
||||
curr_addr2 <= 32'h0;
|
||||
end
|
||||
else if (cmd_wr_en) begin
|
||||
if (curr_wr_ptr)
|
||||
curr_addr2 <= prbs_addr_mdfy;
|
||||
else
|
||||
curr_addr1 <= prbs_addr_mdfy;
|
||||
end
|
||||
end
|
||||
|
||||
//*****************************************************************************
|
||||
// Control Output Signals
|
||||
//*****************************************************************************
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (!resetn)
|
||||
cmd_en <= 1'b0;
|
||||
else if (tg_state[TG_WR_CMD] | tg_state[TG_RD_CMD])
|
||||
cmd_en <= 1'b1;
|
||||
else if (tg_state[TG_WR_DATA] | tg_state[TG_RD_DATA])
|
||||
cmd_en <= 1'b0;
|
||||
end
|
||||
|
||||
assign cmd = {cmd_gen_csr_sig, 1'b0, wrap_en};
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (tg_state[TG_IDLE]) begin
|
||||
blen <= 8'h0;
|
||||
addr <= 32'h0;
|
||||
end
|
||||
else if (cmd_gen_csr_sig & tg_state[TG_GEN_PRBS]) begin
|
||||
blen <= prbs_blen_mdfy;
|
||||
addr <= prbs_addr_mdfy;
|
||||
end
|
||||
else if (tg_state[TG_GEN_PRBS]) begin
|
||||
case ({curr_wr_ptr, curr_rd_ptr})
|
||||
2'b01: begin
|
||||
blen <= curr_blen2;
|
||||
addr <= curr_addr2;
|
||||
end
|
||||
default : begin
|
||||
blen <= curr_blen1;
|
||||
addr <= curr_addr1;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
generate
|
||||
begin: cntrl_sig
|
||||
if (C_AXI_NBURST_SUPPORT == 1) begin
|
||||
end
|
||||
else begin
|
||||
if (C_AXI_DATA_WIDTH == 1024)
|
||||
assign ctl[2:0] = 3'b111;
|
||||
else if (C_AXI_DATA_WIDTH == 512)
|
||||
assign ctl[2:0] = 3'b110;
|
||||
else if (C_AXI_DATA_WIDTH == 256)
|
||||
assign ctl[2:0] = 3'b101;
|
||||
else if (C_AXI_DATA_WIDTH == 128)
|
||||
assign ctl[2:0] = 3'b100;
|
||||
else if (C_AXI_DATA_WIDTH == 64)
|
||||
assign ctl[2:0] = 3'b011;
|
||||
else
|
||||
assign ctl[2:0] = 3'b010;
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
//*****************************************************************************
|
||||
// Write Output Signals
|
||||
//*****************************************************************************
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (!resetn)
|
||||
wdata_cmptd <= 1'b0;
|
||||
else if (tg_state[TG_WR_DONE])
|
||||
wdata_cmptd <= 1'b0;
|
||||
else if ((tg_state[TG_WR_DATA] & wdata_rdy & blen_cntr == 8'h01) |
|
||||
(next_tg_state[TG_WR_DATA] & tg_state[TG_WR_CMD] & blen_cntr == 8'h00))
|
||||
wdata_cmptd <= 1'b1;
|
||||
end
|
||||
|
||||
assign wdata_vld = tg_state[TG_WR_DATA];
|
||||
assign wdata = {{C_AXI_DATA_WIDTH/32}{prbs_data}};
|
||||
|
||||
generate
|
||||
begin: data_sig
|
||||
if (C_AXI_NBURST_SUPPORT == 1) begin
|
||||
end
|
||||
else begin
|
||||
assign wdata_bvld = {{C_AXI_DATA_WIDTH/32}{4'hF}};
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
//*****************************************************************************
|
||||
// Status and Debug Signals
|
||||
//*****************************************************************************
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (!resetn) begin
|
||||
cmd_err_dbg <= 1'b0;
|
||||
data_msmatch_err_dbg <= 1'b0;
|
||||
write_err_dbg <= 1'b0;
|
||||
read_err_dbg <= 1'b0;
|
||||
end
|
||||
else if (tg_state[TG_IDLE] & next_tg_state[TG_GEN_PRBS]) begin
|
||||
cmd_err_dbg <= 1'b0;
|
||||
data_msmatch_err_dbg <= 1'b0;
|
||||
write_err_dbg <= 1'b0;
|
||||
read_err_dbg <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
if ((next_tg_state[TG_GEN_PRBS] | next_tg_state[TG_UPDT_CNTR]) &
|
||||
(tg_state[TG_RD_CMD] | tg_state[TG_WR_CMD]))
|
||||
cmd_err_dbg <= 1'b0;
|
||||
if (msmatch_err & tg_state[TG_RD_DATA])
|
||||
data_msmatch_err_dbg <= 1'b1;
|
||||
if ((next_tg_state[TG_GEN_PRBS] | next_tg_state[TG_UPDT_CNTR]) &
|
||||
tg_state[TG_WR_DATA])
|
||||
write_err_dbg <= 1'b1;
|
||||
if (rdata_cmptd & rdata_vld & rdata_rdy)
|
||||
read_err_dbg <= (rdata_sts[3:2] == 2'b01);
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (!resetn) begin
|
||||
cmd_err <= 1'b0;
|
||||
data_msmatch_err <= 1'b0;
|
||||
write_err <= 1'b0;
|
||||
read_err <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
if (cmd_err_dbg)
|
||||
cmd_err <= 1'b1;
|
||||
if (data_msmatch_err_dbg)
|
||||
data_msmatch_err <= 1'b1;
|
||||
if (write_err_dbg)
|
||||
write_err <= 1'b1;
|
||||
if (read_err_dbg)
|
||||
read_err <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (!resetn) begin
|
||||
dbg_wr_sts_vld <= 1'b0;
|
||||
dbg_rd_sts_vld <= 1'b0;
|
||||
end
|
||||
else if (tg_state[TG_GEN_PRBS]) begin
|
||||
dbg_wr_sts_vld <= 1'b0;
|
||||
dbg_rd_sts_vld <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
if (wdata_sts_vld)
|
||||
dbg_wr_sts_vld <= 1'b1;
|
||||
if (rdata_cmptd & rdata_vld & rdata_rdy)
|
||||
dbg_rd_sts_vld <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (tg_state[TG_GEN_PRBS] | tg_state[TG_IDLE]) begin
|
||||
wdata_sts_r <= {WR_STS_WIDTH{1'b0}};
|
||||
rdata_sts_r <= {RD_STS_WIDTH{1'b0}};
|
||||
end
|
||||
else begin
|
||||
if (wdata_sts_vld)
|
||||
wdata_sts_r <= wdata_sts;
|
||||
if (rdata_cmptd & rdata_vld & rdata_rdy)
|
||||
rdata_sts_r <= rdata_sts;
|
||||
end
|
||||
end
|
||||
|
||||
//*****************************************************************************
|
||||
// Data count generation incremented for each burst to indicate activity
|
||||
//*****************************************************************************
|
||||
|
||||
// Write count within a burst
|
||||
always @(posedge clk)
|
||||
if (wrd_cntr_rst)
|
||||
wr_wrd_cntr <= 8'h00;
|
||||
else if (wdata_sig_vld)
|
||||
wr_wrd_cntr <= wr_wrd_cntr + 8'h01;
|
||||
|
||||
// Read count within a burst is implemented inside the data_gen_chk module
|
||||
|
||||
// Storing last burst count for read and write
|
||||
always @(posedge clk)
|
||||
if (!resetn)
|
||||
wr_wrd_cntr_r <= 8'h00;
|
||||
else if (dbg_wr_sts_vld)
|
||||
wr_wrd_cntr_r <= wr_wrd_cntr;
|
||||
|
||||
always @(posedge clk)
|
||||
if (!resetn)
|
||||
rd_wrd_cntr_r <= 8'h00;
|
||||
else if (dbg_rd_sts_vld)
|
||||
rd_wrd_cntr_r <= rd_wrd_cntr;
|
||||
|
||||
// Computing the word count at which first data mismatch occured
|
||||
always @(posedge clk)
|
||||
if (wrd_cntr_rst)
|
||||
rd_mismatch_wrd_cntr_r <= 8'h00;
|
||||
else if (~data_msmatch_err_dbg)
|
||||
rd_mismatch_wrd_cntr_r <= rd_wrd_cntr - 1;
|
||||
|
||||
assign dbg_wr_sts = {rd_wrd_cntr_r, 11'h0, data_pattern, write_err_dbg, cmd_err_dbg, wdata_sts_r};
|
||||
assign dbg_rd_sts = {wr_wrd_cntr_r, 2'b00, data_pattern, rd_mismatch_wrd_cntr_r, data_msmatch_err_dbg, read_err_dbg, cmd_err_dbg, rdata_sts_r};
|
||||
assign test_cmptd = tg_state[TG_UPDT_CNTR] & next_tg_state[TG_IDLE];
|
||||
assign write_cmptd = (tg_state[TG_WR_DATA] | tg_state[TG_WR_DONE]) &
|
||||
(next_tg_state[TG_GEN_PRBS] | next_tg_state[TG_UPDT_CNTR]);
|
||||
assign read_cmptd = tg_state[TG_RD_DATA] & (next_tg_state[TG_GEN_PRBS] | next_tg_state[TG_UPDT_CNTR]);
|
||||
assign cmp_data_en = dgen_en & tg_state[TG_RD_DATA];
|
||||
assign rdata_cmp = rdata;
|
||||
|
||||
// synthesis translate_off
|
||||
//*****************************************************************************
|
||||
// Simulation debug signals and messages
|
||||
//*****************************************************************************
|
||||
|
||||
|
||||
always @(*) begin
|
||||
if (test_cmptd) begin
|
||||
$display ("[INFO] : All tests have been completed");
|
||||
if (cmd_err)
|
||||
$display ("[ERROR] Command error has occured");
|
||||
if (data_msmatch_err)
|
||||
$display ("[ERROR] Data mismatch error occured");
|
||||
if (write_err)
|
||||
$display ("[ERROR] Timeout occured during write transaction");
|
||||
if (read_err)
|
||||
$display ("[ERROR] Timeout occured during read transaction");
|
||||
if (!cmd_err & !data_msmatch_err & !write_err & !read_err)
|
||||
$display ("[INFO] : Tests PASSED");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
|
||||
// synthesis translate_on
|
||||
|
||||
endmodule
|
||||
+2938
File diff suppressed because it is too large
Load Diff
+3413
File diff suppressed because it is too large
Load Diff
+103
@@ -0,0 +1,103 @@
|
||||
###############################################################################
|
||||
## (c) Copyright 2008 – 2009 Xilinx, Inc. All rights reserved.
|
||||
##
|
||||
## This file contains confidential and proprietary information
|
||||
## of Xilinx, Inc. and is protected under U.S. and
|
||||
## international copyright and other intellectual property
|
||||
## laws.
|
||||
##
|
||||
## DISCLAIMER
|
||||
## This disclaimer is not a license and does not grant any
|
||||
## rights to the materials distributed herewith. Except as
|
||||
## otherwise provided in a valid license issued to you by
|
||||
## Xilinx, and to the maximum extent permitted by applicable
|
||||
## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
## (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
## including negligence, or under any other theory of
|
||||
## liability) for any loss or damage of any kind or nature
|
||||
## related to, arising under or in connection with these
|
||||
## materials, including for any direct, or any indirect,
|
||||
## special, incidental, or consequential loss or damage
|
||||
## (including loss of data, profits, goodwill, or any type of
|
||||
## loss or damage suffered as a result of any action brought
|
||||
## by a third party) even if such damage or loss was
|
||||
## reasonably foreseeable or Xilinx had been advised of the
|
||||
## possibility of the same.
|
||||
##
|
||||
## CRITICAL APPLICATIONS
|
||||
## Xilinx products are not designed or intended to be fail-
|
||||
## safe, or for use in any application requiring fail-safe
|
||||
## performance, such as life-support or safety devices or
|
||||
## systems, Class III medical devices, nuclear facilities,
|
||||
## applications related to the deployment of airbags, or any
|
||||
## other applications that could lead to death, personal
|
||||
## injury, or severe property or environmental damage
|
||||
## (individually and collectively, "Critical
|
||||
## Applications"). Customer assumes the sole risk and
|
||||
## liability of any use of Xilinx products in Critical
|
||||
## Applications, subject only to applicable laws and
|
||||
## regulations governing limitations on product liability.
|
||||
##
|
||||
## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
## PART OF THIS FILE AT ALL TIMES.
|
||||
##
|
||||
###############################################################################
|
||||
## ____ ____
|
||||
## / /\/ /
|
||||
## /___/ \ / Vendor : Xilinx
|
||||
## \ \ \/ Version : 4.2
|
||||
## \ \ Application : MIG
|
||||
## / / Filename : ies_run.sh
|
||||
## /___/ /\ Date Last Modified : $Date: 2011/06/02 08:31:17 $
|
||||
## \ \ / \ Date Created : Tue Oct 29 2013
|
||||
## \___\/\___\
|
||||
##
|
||||
## Device : 7 Series
|
||||
## Purpose :
|
||||
## Sample ies_run.sh file to compile and simulate memory interface
|
||||
## design and run the simulation for specified period of time.
|
||||
## Display the waveforms that are listed with "add wave" command.
|
||||
## Assumptions :
|
||||
## Simulation takes place in \sim folder of MIG output directory.
|
||||
## Reference :
|
||||
## Revision History :
|
||||
###############################################################################
|
||||
|
||||
#echo Simulation Tool: IES
|
||||
|
||||
#Compile the required libraries here#
|
||||
#libraries path#
|
||||
|
||||
#Compile all modules#
|
||||
ncvlog -work worklib -sv -messages mig_7series*.v > ies_sim.log
|
||||
ncvlog -sv -work worklib -messages ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/system_top_mig_7series_0_0.v >> ies_sim.log
|
||||
ncvlog -sv -work worklib -messages ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/system_top_mig_7series_0_0_mig_sim.v >> ies_sim.log
|
||||
ncvlog -work worklib -messages -sv ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/clocking/*.v >> ies_sim.log
|
||||
ncvlog -work worklib -messages -sv ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/controller/*.v >> ies_sim.log
|
||||
ncvlog -work worklib -messages -sv ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/ecc/*.v >> ies_sim.log
|
||||
ncvlog -work worklib -messages -sv ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/ip_top/*.v >> ies_sim.log
|
||||
ncvlog -work worklib -messages -sv ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/phy/*.v >> ies_sim.log
|
||||
ncvlog -work worklib -messages -sv ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/ui/*.v >> ies_sim.log
|
||||
ncvlog -sv -work worklib -messages ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/axi/*.v >> ies_sim.log
|
||||
|
||||
|
||||
ncvlog -sv -work worklib -messages example_top.v >> ies_sim.log
|
||||
|
||||
#Compile files in sim folder (excluding model parameter file)#
|
||||
#$XILINX variable must be set
|
||||
ncvlog -work worklib -messages $XILINX_VIVADO/data/verilog/src/glbl.v >> ies_sim.log
|
||||
ncvlog -work worklib -messages wiredly.v >> ies_sim.log
|
||||
ncvlog -work worklib -messages sim_tb_top.v >> ies_sim.log
|
||||
|
||||
#Pass the parameters for memory model parameter file#
|
||||
ncvlog -work worklib -messages -sv +define+x1Gb +define+sg125 +define+x8 ddr3_model.sv >> ies_sim.log
|
||||
|
||||
#Simulate the design with sim_tb_top as the top module
|
||||
ncelab -namemap_mixgen -timescale '1ps/1ps' -vhdlsync -v93 -messages -nettype_port_relax -access +rwc sim_tb_top glbl >> ies_sim.log
|
||||
ncsim sim_tb_top >> ies_sim.log
|
||||
#echo done
|
||||
|
||||
+230
@@ -0,0 +1,230 @@
|
||||
###############################################################################
|
||||
## (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
|
||||
##
|
||||
## This file contains confidential and proprietary information
|
||||
## of Xilinx, Inc. and is protected under U.S. and
|
||||
## international copyright and other intellectual property
|
||||
## laws.
|
||||
##
|
||||
## DISCLAIMER
|
||||
## This disclaimer is not a license and does not grant any
|
||||
## rights to the materials distributed herewith. Except as
|
||||
## otherwise provided in a valid license issued to you by
|
||||
## Xilinx, and to the maximum extent permitted by applicable
|
||||
## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
## (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
## including negligence, or under any other theory of
|
||||
## liability) for any loss or damage of any kind or nature
|
||||
## related to, arising under or in connection with these
|
||||
## materials, including for any direct, or any indirect,
|
||||
## special, incidental, or consequential loss or damage
|
||||
## (including loss of data, profits, goodwill, or any type of
|
||||
## loss or damage suffered as a result of any action brought
|
||||
## by a third party) even if such damage or loss was
|
||||
## reasonably foreseeable or Xilinx had been advised of the
|
||||
## possibility of the same.
|
||||
##
|
||||
## CRITICAL APPLICATIONS
|
||||
## Xilinx products are not designed or intended to be fail-
|
||||
## safe, or for use in any application requiring fail-safe
|
||||
## performance, such as life-support or safety devices or
|
||||
## systems, Class III medical devices, nuclear facilities,
|
||||
## applications related to the deployment of airbags, or any
|
||||
## other applications that could lead to death, personal
|
||||
## injury, or severe property or environmental damage
|
||||
## (individually and collectively, "Critical
|
||||
## Applications"). Customer assumes the sole risk and
|
||||
## liability of any use of Xilinx products in Critical
|
||||
## Applications, subject only to applicable laws and
|
||||
## regulations governing limitations on product liability.
|
||||
##
|
||||
## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
## PART OF THIS FILE AT ALL TIMES.
|
||||
##
|
||||
###############################################################################
|
||||
## ____ ____
|
||||
## / /\/ /
|
||||
## /___/ \ / Vendor : Xilinx
|
||||
## \ \ \/ Version : 4.2
|
||||
## \ \ Application : MIG
|
||||
## / / Filename : readme.txt
|
||||
## /___/ /\ Date Last Modified : $Date: 2011/06/02 08:31:16 $
|
||||
## \ \ / \ Date Created : Tue Sept 21 2010
|
||||
## \___\/\___\
|
||||
##
|
||||
## Device : 7 Series
|
||||
## Design Name : DDR3 SDRAM
|
||||
## Purpose : Steps to run simulations using Modelsim/QuestaSim,
|
||||
## Cadence IES, and Synopsys VCS
|
||||
## Assumptions : Simulations are run in \sim folder of MIG output "Open IP
|
||||
## Example Design" directory
|
||||
## Reference :
|
||||
## Revision History:
|
||||
###############################################################################
|
||||
|
||||
MIG outputs script files required to run the simulations for Modelsim/QuestaSim,
|
||||
Vivado Simulator, IES and VCS. These scripts are valid only for running
|
||||
simulations for "Open IP Example Design"
|
||||
|
||||
1. How to run simulations in Modelsim/QuestaSim simulator
|
||||
|
||||
A) sim.do File :
|
||||
|
||||
a) The 'sim.do' file has commands to compile and simulate memory
|
||||
interface design and run the simulation for specified period of time.
|
||||
|
||||
b) It has the syntax to Map the required libraries (unisims_ver,
|
||||
unisim and secureip). The libraries should be mapped using
|
||||
the following command
|
||||
vmap unisims_ver <unisims_ver lib path>
|
||||
vmap unisim <unisim lib path>
|
||||
vmap secureip <secureip lib path>
|
||||
|
||||
Also, $XILINX_VIVADO environment variable must be set in order to compile glbl.v file
|
||||
|
||||
c) Displays the waveforms that are listed with "add wave" command.
|
||||
|
||||
B) Steps to run the Modelsim/QuestaSim simulation:
|
||||
|
||||
a) The user should invoke the Modelsim/QuestaSim simulator GUI.
|
||||
|
||||
b) Change the present working directory path to the sim folder.
|
||||
In Transcript window, at Modelsim/QuestaSim prompt, type the following
|
||||
command to change directory path.
|
||||
cd <sim directory path>
|
||||
|
||||
c) Run the simulation using sim.do file.
|
||||
At Modelsim/QuestaSim prompt, type the following command:
|
||||
do sim.do
|
||||
|
||||
d) To exit simulation, type the following command at Modelsim/QuestaSim
|
||||
prompt:
|
||||
quit -f
|
||||
|
||||
e) Verify the transcript file for the memory transactions.
|
||||
|
||||
2. How to run simulations in Vivado simulator
|
||||
|
||||
A) Following files are provided :
|
||||
|
||||
a) The 'xsim_run.bat' is the executable file for Vivado simulator under
|
||||
MicroSoft Windows environment.
|
||||
|
||||
b) The 'xsim_run.sh' is the executable file for Vivado simulator under
|
||||
Linux environment.
|
||||
|
||||
c) The 'xsim_run.bat'/'xsim_run.sh' file has commands to compile and
|
||||
simulate memory interface design and run the simulation for specified
|
||||
period of time.
|
||||
|
||||
d) xsim_options.tcl file has commands to add waveforms and simulation
|
||||
period.
|
||||
|
||||
e) xsim_files.prj file has list of rtl files for simulating the design.
|
||||
|
||||
f) $XILINX_VIVADO environment variable must be set in order to compile
|
||||
glbl.v file
|
||||
|
||||
B) Steps to run the Vivado Simulator simulation:
|
||||
|
||||
a) Change the present working directory path to the sim folder of "Open
|
||||
IP Example Design" path in the OS terminal.
|
||||
|
||||
b) Run the simulation using xsim_run.sh file under Linux environment and
|
||||
xsim_run.bat under MicroSoft Windows environment.
|
||||
|
||||
c) Verify the transcript file for the memory transactions.
|
||||
|
||||
3. How to run Cadence IES Simulations
|
||||
|
||||
A) ies_run.sh File :
|
||||
|
||||
a) The "ies_run.sh" file contains the commands for simulation of the
|
||||
hdl files.
|
||||
|
||||
b) Libraries must be mapped before running simulations. Following
|
||||
procedure must be followed to before running simulations
|
||||
|
||||
1. Create two files named cds.lib and hdl.var in this directory
|
||||
2. Create a directory 'worklib' in same directory.
|
||||
mkdir worklib
|
||||
3. Add following lines in the cds.lib file to map Xilinx libraries
|
||||
|
||||
DEFINE unisim /proj/xbuilds/2014.4_daily_latest/clibs/ius/13.20.005/lin64/lib/./unisim
|
||||
DEFINE unisims_ver /proj/xbuilds/2014.4_daily_latest/clibs/ius/13.20.005/lin64/lib/./unisims_ver
|
||||
DEFINE secureip /proj/xbuilds/2014.4_daily_latest/clibs/ius/13.20.005/lin64/lib/./secureip
|
||||
DEFINE worklib ./worklib
|
||||
|
||||
4. ATTENTION: In above lines replace the path for libraries as per your
|
||||
compiled Xilinx libraries directory
|
||||
5. ATTENTION: Add the lines in the same order given above
|
||||
6. Please make sure you need to map all Xilinx libraries mentioned above
|
||||
7. Save and close the cds.lib file
|
||||
|
||||
Also, $XILINX_VIVADO environment variable must be set in order to
|
||||
compile glbl.v file and the above mentioned library files
|
||||
|
||||
B) Steps to run the IES simulation:
|
||||
|
||||
a) Change the present working directory path to the sim folder of "Open
|
||||
IP Example Design" path in the OS terminal.
|
||||
|
||||
b) Run the simulation using ies_run.sh file. Type the following command:
|
||||
./ies_run.sh
|
||||
|
||||
c) Verify the ies_sim.log file for the memory transactions.
|
||||
|
||||
4. How to run Synopsys VCS Simulations
|
||||
|
||||
A) vcs_run.sh File :
|
||||
|
||||
a) The "vcs_run.sh" file contains the commands for simulation of hdl files.
|
||||
|
||||
b) Libraries must be mapped before running simulations. Following
|
||||
procedure must be followed to before running simulations
|
||||
|
||||
1. Create a file named synopsys_sim.setup in this directory
|
||||
2. Add following lines in the synopsys_sim.setup file to map Xilinx
|
||||
libraries
|
||||
|
||||
unisim : /proj/xbuilds/2014.4_daily_latest/clibs/vcs/I-2014.03/lin64/lib/unisim
|
||||
secureip : /proj/xbuilds/2014.4_daily_latest/clibs/vcs/I-2014.03/lin64/lib/secureip
|
||||
unisims_ver : /proj/xbuilds/2014.4_daily_latest/clibs/vcs/I-2014.03/lin64/lib/unisims_ver
|
||||
|
||||
3. ATTENTION: In above lines replace the path for libraries as per your
|
||||
Compiled Xilinx libraries directory
|
||||
4. Please make sure you need to map all Xilinx libraries mentioned above
|
||||
|
||||
Also, $XILINX_VIVADO environment variable must be set in order to
|
||||
compile glbl.v file and the above mentioned library files
|
||||
|
||||
B) Steps to run the VCS simulation:
|
||||
|
||||
a) Change the present working directory path to the sim folder of "Open
|
||||
IP Example Design" path in the OS terminal.
|
||||
|
||||
b) Run the simulation using vcs_run.sh file. Type the following command:
|
||||
./vcs_run.sh
|
||||
|
||||
c) Verify the vcs_sim.log file for the memory transactions.
|
||||
|
||||
5. SIM_BYPASS_INIT_CAL parameter value of SKIP, skips memory initialization sequence
|
||||
and calibration sequence. This could lead to simulation errors since design is not
|
||||
calibrated at all. Preferred values for parameter SIM_BYPASS_INIT_CAL to run
|
||||
simulations are FAST and OFF.
|
||||
|
||||
6. Simulations running with parameter MAX_MEM defined uses a temporary directory for model data.
|
||||
The default temporary directory specified in model file is /tmp which doesn't exist for Windows OS.
|
||||
Therfore users running on Windows OS should change the ddr3_model.v file as below
|
||||
|
||||
tmp_model_dir = "/tmp";
|
||||
to
|
||||
tmp_model_dir = ".";
|
||||
|
||||
This change works for All OS.
|
||||
|
||||
|
||||
+155
@@ -0,0 +1,155 @@
|
||||
###############################################################################
|
||||
## (c) Copyright 2008 – 2009 Xilinx, Inc. All rights reserved.
|
||||
##
|
||||
## This file contains confidential and proprietary information
|
||||
## of Xilinx, Inc. and is protected under U.S. and
|
||||
## international copyright and other intellectual property
|
||||
## laws.
|
||||
##
|
||||
## DISCLAIMER
|
||||
## This disclaimer is not a license and does not grant any
|
||||
## rights to the materials distributed herewith. Except as
|
||||
## otherwise provided in a valid license issued to you by
|
||||
## Xilinx, and to the maximum extent permitted by applicable
|
||||
## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
## (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
## including negligence, or under any other theory of
|
||||
## liability) for any loss or damage of any kind or nature
|
||||
## related to, arising under or in connection with these
|
||||
## materials, including for any direct, or any indirect,
|
||||
## special, incidental, or consequential loss or damage
|
||||
## (including loss of data, profits, goodwill, or any type of
|
||||
## loss or damage suffered as a result of any action brought
|
||||
## by a third party) even if such damage or loss was
|
||||
## reasonably foreseeable or Xilinx had been advised of the
|
||||
## possibility of the same.
|
||||
##
|
||||
## CRITICAL APPLICATIONS
|
||||
## Xilinx products are not designed or intended to be fail-
|
||||
## safe, or for use in any application requiring fail-safe
|
||||
## performance, such as life-support or safety devices or
|
||||
## systems, Class III medical devices, nuclear facilities,
|
||||
## applications related to the deployment of airbags, or any
|
||||
## other applications that could lead to death, personal
|
||||
## injury, or severe property or environmental damage
|
||||
## (individually and collectively, "Critical
|
||||
## Applications"). Customer assumes the sole risk and
|
||||
## liability of any use of Xilinx products in Critical
|
||||
## Applications, subject only to applicable laws and
|
||||
## regulations governing limitations on product liability.
|
||||
##
|
||||
## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
## PART OF THIS FILE AT ALL TIMES.
|
||||
##
|
||||
###############################################################################
|
||||
## ____ ____
|
||||
## / /\/ /
|
||||
## /___/ \ / Vendor : Xilinx
|
||||
## \ \ \/ Version : 4.2
|
||||
## \ \ Application : MIG
|
||||
## / / Filename : sim.do
|
||||
## /___/ /\ Date Last Modified : $Date: 2011/06/02 08:31:17 $
|
||||
## \ \ / \ Date Created : Tue Sept 21 2010
|
||||
## \___\/\___\
|
||||
##
|
||||
## Device : 7 Series
|
||||
## Purpose :
|
||||
## Sample sim .do file to compile and simulate memory interface
|
||||
## design and run the simulation for specified period of time.
|
||||
## Display the waveforms that are listed with "add wave" command.
|
||||
## Assumptions :
|
||||
## Simulation takes place in \sim folder of MIG output directory.
|
||||
## Reference :
|
||||
## Revision History :
|
||||
###############################################################################
|
||||
|
||||
vlib work
|
||||
|
||||
#Map the required libraries here#
|
||||
#vmap unisims_ver <unisims_ver lib path>
|
||||
#vmap unisim <unisim lib path>
|
||||
#vmap secureip <secureip lib path>
|
||||
|
||||
#Compile all modules#
|
||||
vlog -incr mig_7series*.v
|
||||
vlog ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/system_top_mig_7series_0_0.v
|
||||
vlog ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/system_top_mig_7series_0_0_mig_sim.v
|
||||
vlog -incr ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/clocking/*.v
|
||||
vlog -incr ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/controller/*.v
|
||||
vlog -incr ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/ecc/*.v
|
||||
vlog -incr ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/ip_top/*.v
|
||||
vlog -incr ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/phy/*.v
|
||||
vlog -incr ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/ui/*.v
|
||||
vlog -incr ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/axi/*
|
||||
|
||||
|
||||
vlog example_top.v
|
||||
|
||||
#Compile files in sim folder (excluding model parameter file)#
|
||||
#$XILINX variable must be set
|
||||
vlog -incr $env(XILINX_VIVADO)/data/verilog/src/glbl.v
|
||||
vlog wiredly.v
|
||||
vlog sim_tb_top.v
|
||||
|
||||
#Pass the parameters for memory model parameter file#
|
||||
vlog -sv +define+x1Gb +define+sg125 +define+x8 ddr3_model.sv
|
||||
|
||||
#Load the design. Use required libraries.#
|
||||
vsim -t fs -novopt +notimingchecks -L unisims_ver -L secureip work.sim_tb_top glbl
|
||||
|
||||
onerror {resume}
|
||||
#Log all the objects in design. These will appear in .wlf file#
|
||||
#This helps in viewing all signals of the design instead of
|
||||
#re-running the simulation for viewing the signals.
|
||||
#Uncomment below line to log all objects in the design.
|
||||
#log -r /*
|
||||
|
||||
#View sim_tb_top signals in waveform#
|
||||
add wave sim:/sim_tb_top/*
|
||||
#Change radix to Hexadecimal#
|
||||
radix hex
|
||||
#Supress Numeric Std package and Arith package warnings.#
|
||||
#For VHDL designs we get some warnings due to unknown values on some signals at startup#
|
||||
# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0#
|
||||
#We may also get some Arithmetic packeage warnings because of unknown values on#
|
||||
#some of the signals that are used in an Arithmetic operation.#
|
||||
#In order to suppress these warnings, we use following two commands#
|
||||
set NumericStdNoWarnings 1
|
||||
set StdArithNoWarnings 1
|
||||
|
||||
# Choose simulation run time by inserting a breakpoint and then run for specified #
|
||||
# period. For more details, refer to user guide (UG586).#
|
||||
# Status reporting logic exists both in simulation test bench (sim_tb_top)
|
||||
# and sim.do file for ModelSim. Any update in simulation run time or time out
|
||||
# in this file need to be updated in sim_tb_top file as well.
|
||||
when {/sim_tb_top/init_calib_complete = 1} {
|
||||
if {[when -label a_100] == ""} {
|
||||
when -label a_100 { $now = 50 us } {
|
||||
nowhen a_100
|
||||
report simulator control
|
||||
report simulator state
|
||||
if {[examine /sim_tb_top/tg_compare_error] == 0} {
|
||||
echo "TEST PASSED"
|
||||
stop
|
||||
}
|
||||
if {[examine /sim_tb_top/tg_compare_error] != 0} {
|
||||
echo "TEST FAILED: DATA ERROR"
|
||||
stop
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#In case calibration fails to complete, choose the run time and then stop#
|
||||
when {$now = @1000 us and /sim_tb_top/init_calib_complete != 1} {
|
||||
echo "TEST FAILED: CALIBRATION DID NOT COMPLETE"
|
||||
stop
|
||||
}
|
||||
|
||||
run -all
|
||||
stop
|
||||
|
||||
+583
@@ -0,0 +1,583 @@
|
||||
//*****************************************************************************
|
||||
// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
//*****************************************************************************
|
||||
// ____ ____
|
||||
// / /\/ /
|
||||
// /___/ \ / Vendor : Xilinx
|
||||
// \ \ \/ Version : 4.2
|
||||
// \ \ Application : MIG
|
||||
// / / Filename : sim_tb_top.v
|
||||
// /___/ /\ Date Last Modified : $Date: 2011/06/07 13:45:16 $
|
||||
// \ \ / \ Date Created : Tue Sept 21 2010
|
||||
// \___\/\___\
|
||||
//
|
||||
// Device : 7 Series
|
||||
// Design Name : DDR3 SDRAM
|
||||
// Purpose :
|
||||
// Top-level testbench for testing DDR3.
|
||||
// Instantiates:
|
||||
// 1. IP_TOP (top-level representing FPGA, contains core,
|
||||
// clocking, built-in testbench/memory checker and other
|
||||
// support structures)
|
||||
// 2. DDR3 Memory
|
||||
// 3. Miscellaneous clock generation and reset logic
|
||||
// 4. For ECC ON case inserts error on LSB bit
|
||||
// of data from DRAM to FPGA.
|
||||
// Reference :
|
||||
// Revision History :
|
||||
//*****************************************************************************
|
||||
|
||||
`timescale 1ps/100fs
|
||||
|
||||
module sim_tb_top;
|
||||
|
||||
|
||||
//***************************************************************************
|
||||
// Traffic Gen related parameters
|
||||
//***************************************************************************
|
||||
parameter SIMULATION = "TRUE";
|
||||
parameter BEGIN_ADDRESS = 32'h00000000;
|
||||
parameter END_ADDRESS = 32'h00000fff;
|
||||
parameter PRBS_EADDR_MASK_POS = 32'hff000000;
|
||||
|
||||
//***************************************************************************
|
||||
// The following parameters refer to width of various ports
|
||||
//***************************************************************************
|
||||
parameter COL_WIDTH = 10;
|
||||
// # of memory Column Address bits.
|
||||
parameter CS_WIDTH = 1;
|
||||
// # of unique CS outputs to memory.
|
||||
parameter DM_WIDTH = 8;
|
||||
// # of DM (data mask)
|
||||
parameter DQ_WIDTH = 64;
|
||||
// # of DQ (data)
|
||||
parameter DQS_WIDTH = 8;
|
||||
parameter DQS_CNT_WIDTH = 3;
|
||||
// = ceil(log2(DQS_WIDTH))
|
||||
parameter DRAM_WIDTH = 8;
|
||||
// # of DQ per DQS
|
||||
parameter ECC = "OFF";
|
||||
parameter RANKS = 1;
|
||||
// # of Ranks.
|
||||
parameter ODT_WIDTH = 1;
|
||||
// # of ODT outputs to memory.
|
||||
parameter ROW_WIDTH = 14;
|
||||
// # of memory Row Address bits.
|
||||
parameter ADDR_WIDTH = 28;
|
||||
// # = RANK_WIDTH + BANK_WIDTH
|
||||
// + ROW_WIDTH + COL_WIDTH;
|
||||
// Chip Select is always tied to low for
|
||||
// single rank devices
|
||||
//***************************************************************************
|
||||
// The following parameters are mode register settings
|
||||
//***************************************************************************
|
||||
parameter BURST_MODE = "8";
|
||||
// DDR3 SDRAM:
|
||||
// Burst Length (Mode Register 0).
|
||||
// # = "8", "4", "OTF".
|
||||
// DDR2 SDRAM:
|
||||
// Burst Length (Mode Register).
|
||||
// # = "8", "4".
|
||||
parameter CA_MIRROR = "OFF";
|
||||
// C/A mirror opt for DDR3 dual rank
|
||||
|
||||
//***************************************************************************
|
||||
// The following parameters are multiplier and divisor factors for PLLE2.
|
||||
// Based on the selected design frequency these parameters vary.
|
||||
//***************************************************************************
|
||||
parameter CLKIN_PERIOD = 5000;
|
||||
// Input Clock Period
|
||||
|
||||
|
||||
//***************************************************************************
|
||||
// Simulation parameters
|
||||
//***************************************************************************
|
||||
parameter SIM_BYPASS_INIT_CAL = "FAST";
|
||||
// # = "SIM_INIT_CAL_FULL" - Complete
|
||||
// memory init &
|
||||
// calibration sequence
|
||||
// # = "SKIP" - Not supported
|
||||
// # = "FAST" - Complete memory init & use
|
||||
// abbreviated calib sequence
|
||||
|
||||
//***************************************************************************
|
||||
// IODELAY and PHY related parameters
|
||||
//***************************************************************************
|
||||
parameter TCQ = 100;
|
||||
//***************************************************************************
|
||||
// IODELAY and PHY related parameters
|
||||
//***************************************************************************
|
||||
parameter RST_ACT_LOW = 0;
|
||||
// =1 for active low reset,
|
||||
// =0 for active high.
|
||||
|
||||
//***************************************************************************
|
||||
// Referece clock frequency parameters
|
||||
//***************************************************************************
|
||||
parameter REFCLK_FREQ = 200.0;
|
||||
// IODELAYCTRL reference clock frequency
|
||||
//***************************************************************************
|
||||
// System clock frequency parameters
|
||||
//***************************************************************************
|
||||
parameter tCK = 1250;
|
||||
// memory tCK paramter.
|
||||
// # = Clock Period in pS.
|
||||
parameter nCK_PER_CLK = 4;
|
||||
// # of memory CKs per fabric CLK
|
||||
|
||||
|
||||
//***************************************************************************
|
||||
// AXI4 Shim parameters
|
||||
//***************************************************************************
|
||||
parameter C_S_AXI_ID_WIDTH = 2;
|
||||
// Width of all master and slave ID signals.
|
||||
// # = >= 1.
|
||||
parameter C_S_AXI_ADDR_WIDTH = 32;
|
||||
// Width of S_AXI_AWADDR, S_AXI_ARADDR, M_AXI_AWADDR and
|
||||
// M_AXI_ARADDR for all SI/MI slots.
|
||||
// # = 32.
|
||||
parameter C_S_AXI_DATA_WIDTH = 512;
|
||||
// Width of WDATA and RDATA on SI slot.
|
||||
// Must be <= APP_DATA_WIDTH.
|
||||
// # = 32, 64, 128, 256.
|
||||
parameter C_S_AXI_SUPPORTS_NARROW_BURST = 0;
|
||||
// Indicates whether to instatiate upsizer
|
||||
// Range: 0, 1
|
||||
|
||||
|
||||
//***************************************************************************
|
||||
// Debug and Internal parameters
|
||||
//***************************************************************************
|
||||
parameter DEBUG_PORT = "OFF";
|
||||
// # = "ON" Enable debug signals/controls.
|
||||
// = "OFF" Disable debug signals/controls.
|
||||
//***************************************************************************
|
||||
// Debug and Internal parameters
|
||||
//***************************************************************************
|
||||
parameter DRAM_TYPE = "DDR3";
|
||||
|
||||
|
||||
|
||||
//**************************************************************************//
|
||||
// Local parameters Declarations
|
||||
//**************************************************************************//
|
||||
|
||||
localparam real TPROP_DQS = 0.00;
|
||||
// Delay for DQS signal during Write Operation
|
||||
localparam real TPROP_DQS_RD = 0.00;
|
||||
// Delay for DQS signal during Read Operation
|
||||
localparam real TPROP_PCB_CTRL = 0.00;
|
||||
// Delay for Address and Ctrl signals
|
||||
localparam real TPROP_PCB_DATA = 0.00;
|
||||
// Delay for data signal during Write operation
|
||||
localparam real TPROP_PCB_DATA_RD = 0.00;
|
||||
// Delay for data signal during Read operation
|
||||
|
||||
localparam MEMORY_WIDTH = 8;
|
||||
localparam NUM_COMP = DQ_WIDTH/MEMORY_WIDTH;
|
||||
localparam ECC_TEST = "OFF" ;
|
||||
localparam ERR_INSERT = (ECC_TEST == "ON") ? "OFF" : ECC ;
|
||||
|
||||
|
||||
localparam real REFCLK_PERIOD = (1000000.0/(2*REFCLK_FREQ));
|
||||
localparam RESET_PERIOD = 200000; //in pSec
|
||||
localparam real SYSCLK_PERIOD = tCK;
|
||||
|
||||
|
||||
|
||||
//**************************************************************************//
|
||||
// Wire Declarations
|
||||
//**************************************************************************//
|
||||
reg sys_rst_n;
|
||||
wire sys_rst;
|
||||
|
||||
|
||||
reg sys_clk_i;
|
||||
wire sys_clk_p;
|
||||
wire sys_clk_n;
|
||||
|
||||
|
||||
reg clk_ref_i;
|
||||
|
||||
|
||||
wire ddr3_reset_n;
|
||||
wire [DQ_WIDTH-1:0] ddr3_dq_fpga;
|
||||
wire [DQS_WIDTH-1:0] ddr3_dqs_p_fpga;
|
||||
wire [DQS_WIDTH-1:0] ddr3_dqs_n_fpga;
|
||||
wire [ROW_WIDTH-1:0] ddr3_addr_fpga;
|
||||
wire [3-1:0] ddr3_ba_fpga;
|
||||
wire ddr3_ras_n_fpga;
|
||||
wire ddr3_cas_n_fpga;
|
||||
wire ddr3_we_n_fpga;
|
||||
wire [1-1:0] ddr3_cke_fpga;
|
||||
wire [1-1:0] ddr3_ck_p_fpga;
|
||||
wire [1-1:0] ddr3_ck_n_fpga;
|
||||
|
||||
|
||||
wire init_calib_complete;
|
||||
wire tg_compare_error;
|
||||
wire [(CS_WIDTH*1)-1:0] ddr3_cs_n_fpga;
|
||||
|
||||
wire [DM_WIDTH-1:0] ddr3_dm_fpga;
|
||||
|
||||
wire [ODT_WIDTH-1:0] ddr3_odt_fpga;
|
||||
|
||||
|
||||
reg [(CS_WIDTH*1)-1:0] ddr3_cs_n_sdram_tmp;
|
||||
|
||||
reg [DM_WIDTH-1:0] ddr3_dm_sdram_tmp;
|
||||
|
||||
reg [ODT_WIDTH-1:0] ddr3_odt_sdram_tmp;
|
||||
|
||||
|
||||
|
||||
wire [DQ_WIDTH-1:0] ddr3_dq_sdram;
|
||||
reg [ROW_WIDTH-1:0] ddr3_addr_sdram [0:1];
|
||||
reg [3-1:0] ddr3_ba_sdram [0:1];
|
||||
reg ddr3_ras_n_sdram;
|
||||
reg ddr3_cas_n_sdram;
|
||||
reg ddr3_we_n_sdram;
|
||||
wire [(CS_WIDTH*1)-1:0] ddr3_cs_n_sdram;
|
||||
wire [ODT_WIDTH-1:0] ddr3_odt_sdram;
|
||||
reg [1-1:0] ddr3_cke_sdram;
|
||||
wire [DM_WIDTH-1:0] ddr3_dm_sdram;
|
||||
wire [DQS_WIDTH-1:0] ddr3_dqs_p_sdram;
|
||||
wire [DQS_WIDTH-1:0] ddr3_dqs_n_sdram;
|
||||
reg [1-1:0] ddr3_ck_p_sdram;
|
||||
reg [1-1:0] ddr3_ck_n_sdram;
|
||||
|
||||
|
||||
|
||||
//**************************************************************************//
|
||||
|
||||
//**************************************************************************//
|
||||
// Reset Generation
|
||||
//**************************************************************************//
|
||||
initial begin
|
||||
sys_rst_n = 1'b0;
|
||||
#RESET_PERIOD
|
||||
sys_rst_n = 1'b1;
|
||||
end
|
||||
|
||||
assign sys_rst = RST_ACT_LOW ? sys_rst_n : ~sys_rst_n;
|
||||
|
||||
//**************************************************************************//
|
||||
// Clock Generation
|
||||
//**************************************************************************//
|
||||
|
||||
initial
|
||||
sys_clk_i = 1'b0;
|
||||
always
|
||||
sys_clk_i = #(CLKIN_PERIOD/2.0) ~sys_clk_i;
|
||||
|
||||
assign sys_clk_p = sys_clk_i;
|
||||
assign sys_clk_n = ~sys_clk_i;
|
||||
|
||||
initial
|
||||
clk_ref_i = 1'b0;
|
||||
always
|
||||
clk_ref_i = #REFCLK_PERIOD ~clk_ref_i;
|
||||
|
||||
|
||||
|
||||
|
||||
always @( * ) begin
|
||||
ddr3_ck_p_sdram <= #(TPROP_PCB_CTRL) ddr3_ck_p_fpga;
|
||||
ddr3_ck_n_sdram <= #(TPROP_PCB_CTRL) ddr3_ck_n_fpga;
|
||||
ddr3_addr_sdram[0] <= #(TPROP_PCB_CTRL) ddr3_addr_fpga;
|
||||
ddr3_addr_sdram[1] <= #(TPROP_PCB_CTRL) (CA_MIRROR == "ON") ?
|
||||
{ddr3_addr_fpga[ROW_WIDTH-1:9],
|
||||
ddr3_addr_fpga[7], ddr3_addr_fpga[8],
|
||||
ddr3_addr_fpga[5], ddr3_addr_fpga[6],
|
||||
ddr3_addr_fpga[3], ddr3_addr_fpga[4],
|
||||
ddr3_addr_fpga[2:0]} :
|
||||
ddr3_addr_fpga;
|
||||
ddr3_ba_sdram[0] <= #(TPROP_PCB_CTRL) ddr3_ba_fpga;
|
||||
ddr3_ba_sdram[1] <= #(TPROP_PCB_CTRL) (CA_MIRROR == "ON") ?
|
||||
{ddr3_ba_fpga[3-1:2],
|
||||
ddr3_ba_fpga[0],
|
||||
ddr3_ba_fpga[1]} :
|
||||
ddr3_ba_fpga;
|
||||
ddr3_ras_n_sdram <= #(TPROP_PCB_CTRL) ddr3_ras_n_fpga;
|
||||
ddr3_cas_n_sdram <= #(TPROP_PCB_CTRL) ddr3_cas_n_fpga;
|
||||
ddr3_we_n_sdram <= #(TPROP_PCB_CTRL) ddr3_we_n_fpga;
|
||||
ddr3_cke_sdram <= #(TPROP_PCB_CTRL) ddr3_cke_fpga;
|
||||
end
|
||||
|
||||
|
||||
always @( * )
|
||||
ddr3_cs_n_sdram_tmp <= #(TPROP_PCB_CTRL) ddr3_cs_n_fpga;
|
||||
assign ddr3_cs_n_sdram = ddr3_cs_n_sdram_tmp;
|
||||
|
||||
|
||||
always @( * )
|
||||
ddr3_dm_sdram_tmp <= #(TPROP_PCB_DATA) ddr3_dm_fpga;//DM signal generation
|
||||
assign ddr3_dm_sdram = ddr3_dm_sdram_tmp;
|
||||
|
||||
|
||||
always @( * )
|
||||
ddr3_odt_sdram_tmp <= #(TPROP_PCB_CTRL) ddr3_odt_fpga;
|
||||
assign ddr3_odt_sdram = ddr3_odt_sdram_tmp;
|
||||
|
||||
|
||||
// Controlling the bi-directional BUS
|
||||
|
||||
genvar dqwd;
|
||||
generate
|
||||
for (dqwd = 1;dqwd < DQ_WIDTH;dqwd = dqwd+1) begin : dq_delay
|
||||
WireDelay #
|
||||
(
|
||||
.Delay_g (TPROP_PCB_DATA),
|
||||
.Delay_rd (TPROP_PCB_DATA_RD),
|
||||
.ERR_INSERT ("OFF")
|
||||
)
|
||||
u_delay_dq
|
||||
(
|
||||
.A (ddr3_dq_fpga[dqwd]),
|
||||
.B (ddr3_dq_sdram[dqwd]),
|
||||
.reset (sys_rst_n),
|
||||
.phy_init_done (init_calib_complete)
|
||||
);
|
||||
end
|
||||
WireDelay #
|
||||
(
|
||||
.Delay_g (TPROP_PCB_DATA),
|
||||
.Delay_rd (TPROP_PCB_DATA_RD),
|
||||
.ERR_INSERT ("OFF")
|
||||
)
|
||||
u_delay_dq_0
|
||||
(
|
||||
.A (ddr3_dq_fpga[0]),
|
||||
.B (ddr3_dq_sdram[0]),
|
||||
.reset (sys_rst_n),
|
||||
.phy_init_done (init_calib_complete)
|
||||
);
|
||||
endgenerate
|
||||
|
||||
genvar dqswd;
|
||||
generate
|
||||
for (dqswd = 0;dqswd < DQS_WIDTH;dqswd = dqswd+1) begin : dqs_delay
|
||||
WireDelay #
|
||||
(
|
||||
.Delay_g (TPROP_DQS),
|
||||
.Delay_rd (TPROP_DQS_RD),
|
||||
.ERR_INSERT ("OFF")
|
||||
)
|
||||
u_delay_dqs_p
|
||||
(
|
||||
.A (ddr3_dqs_p_fpga[dqswd]),
|
||||
.B (ddr3_dqs_p_sdram[dqswd]),
|
||||
.reset (sys_rst_n),
|
||||
.phy_init_done (init_calib_complete)
|
||||
);
|
||||
|
||||
WireDelay #
|
||||
(
|
||||
.Delay_g (TPROP_DQS),
|
||||
.Delay_rd (TPROP_DQS_RD),
|
||||
.ERR_INSERT ("OFF")
|
||||
)
|
||||
u_delay_dqs_n
|
||||
(
|
||||
.A (ddr3_dqs_n_fpga[dqswd]),
|
||||
.B (ddr3_dqs_n_sdram[dqswd]),
|
||||
.reset (sys_rst_n),
|
||||
.phy_init_done (init_calib_complete)
|
||||
);
|
||||
end
|
||||
endgenerate
|
||||
|
||||
|
||||
|
||||
|
||||
//===========================================================================
|
||||
// FPGA Memory Controller
|
||||
//===========================================================================
|
||||
|
||||
example_top #
|
||||
(
|
||||
|
||||
.SIMULATION (SIMULATION),
|
||||
.BEGIN_ADDRESS (BEGIN_ADDRESS),
|
||||
.END_ADDRESS (END_ADDRESS),
|
||||
.PRBS_EADDR_MASK_POS (PRBS_EADDR_MASK_POS),
|
||||
|
||||
.COL_WIDTH (COL_WIDTH),
|
||||
.CS_WIDTH (CS_WIDTH),
|
||||
.DM_WIDTH (DM_WIDTH),
|
||||
|
||||
.DQ_WIDTH (DQ_WIDTH),
|
||||
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
|
||||
.DRAM_WIDTH (DRAM_WIDTH),
|
||||
.ECC_TEST (ECC_TEST),
|
||||
.RANKS (RANKS),
|
||||
.ROW_WIDTH (ROW_WIDTH),
|
||||
.ADDR_WIDTH (ADDR_WIDTH),
|
||||
.BURST_MODE (BURST_MODE),
|
||||
.TCQ (TCQ),
|
||||
|
||||
|
||||
.DRAM_TYPE (DRAM_TYPE),
|
||||
|
||||
|
||||
.nCK_PER_CLK (nCK_PER_CLK),
|
||||
|
||||
|
||||
.C_S_AXI_ID_WIDTH (C_S_AXI_ID_WIDTH),
|
||||
.C_S_AXI_ADDR_WIDTH (C_S_AXI_ADDR_WIDTH),
|
||||
.C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
|
||||
.C_S_AXI_SUPPORTS_NARROW_BURST (C_S_AXI_SUPPORTS_NARROW_BURST),
|
||||
|
||||
.DEBUG_PORT (DEBUG_PORT),
|
||||
|
||||
.RST_ACT_LOW (RST_ACT_LOW)
|
||||
)
|
||||
u_ip_top
|
||||
(
|
||||
|
||||
.ddr3_dq (ddr3_dq_fpga),
|
||||
.ddr3_dqs_n (ddr3_dqs_n_fpga),
|
||||
.ddr3_dqs_p (ddr3_dqs_p_fpga),
|
||||
|
||||
.ddr3_addr (ddr3_addr_fpga),
|
||||
.ddr3_ba (ddr3_ba_fpga),
|
||||
.ddr3_ras_n (ddr3_ras_n_fpga),
|
||||
.ddr3_cas_n (ddr3_cas_n_fpga),
|
||||
.ddr3_we_n (ddr3_we_n_fpga),
|
||||
.ddr3_reset_n (ddr3_reset_n),
|
||||
.ddr3_ck_p (ddr3_ck_p_fpga),
|
||||
.ddr3_ck_n (ddr3_ck_n_fpga),
|
||||
.ddr3_cke (ddr3_cke_fpga),
|
||||
.ddr3_cs_n (ddr3_cs_n_fpga),
|
||||
|
||||
.ddr3_dm (ddr3_dm_fpga),
|
||||
|
||||
.ddr3_odt (ddr3_odt_fpga),
|
||||
|
||||
|
||||
.sys_clk_p (sys_clk_p),
|
||||
.sys_clk_n (sys_clk_n),
|
||||
|
||||
.init_calib_complete (init_calib_complete),
|
||||
.tg_compare_error (tg_compare_error),
|
||||
.sys_rst (sys_rst)
|
||||
);
|
||||
|
||||
//**************************************************************************//
|
||||
// Memory Models instantiations
|
||||
//**************************************************************************//
|
||||
|
||||
genvar r,i;
|
||||
generate
|
||||
for (r = 0; r < CS_WIDTH; r = r + 1) begin: mem_rnk
|
||||
for (i = 0; i < NUM_COMP; i = i + 1) begin: gen_mem
|
||||
ddr3_model u_comp_ddr3
|
||||
(
|
||||
.rst_n (ddr3_reset_n),
|
||||
.ck (ddr3_ck_p_sdram[(i*MEMORY_WIDTH)/72]),
|
||||
.ck_n (ddr3_ck_n_sdram[(i*MEMORY_WIDTH)/72]),
|
||||
.cke (ddr3_cke_sdram[((i*MEMORY_WIDTH)/72)+(1*r)]),
|
||||
.cs_n (ddr3_cs_n_sdram[((i*MEMORY_WIDTH)/72)+(1*r)]),
|
||||
.ras_n (ddr3_ras_n_sdram),
|
||||
.cas_n (ddr3_cas_n_sdram),
|
||||
.we_n (ddr3_we_n_sdram),
|
||||
.dm_tdqs (ddr3_dm_sdram[i]),
|
||||
.ba (ddr3_ba_sdram[r]),
|
||||
.addr (ddr3_addr_sdram[r]),
|
||||
.dq (ddr3_dq_sdram[MEMORY_WIDTH*(i+1)-1:MEMORY_WIDTH*(i)]),
|
||||
.dqs (ddr3_dqs_p_sdram[i]),
|
||||
.dqs_n (ddr3_dqs_n_sdram[i]),
|
||||
.tdqs_n (),
|
||||
.odt (ddr3_odt_sdram[((i*MEMORY_WIDTH)/72)+(1*r)])
|
||||
);
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
|
||||
|
||||
|
||||
//***************************************************************************
|
||||
// Reporting the test case status
|
||||
// Status reporting logic exists both in simulation test bench (sim_tb_top)
|
||||
// and sim.do file for ModelSim. Any update in simulation run time or time out
|
||||
// in this file need to be updated in sim.do file as well.
|
||||
//***************************************************************************
|
||||
initial
|
||||
begin : Logging
|
||||
fork
|
||||
begin : calibration_done
|
||||
wait (init_calib_complete);
|
||||
$display("Calibration Done");
|
||||
#50000000.0;
|
||||
if (!tg_compare_error) begin
|
||||
$display("TEST PASSED");
|
||||
end
|
||||
else begin
|
||||
$display("TEST FAILED: DATA ERROR");
|
||||
end
|
||||
disable calib_not_done;
|
||||
$finish;
|
||||
end
|
||||
|
||||
begin : calib_not_done
|
||||
if (SIM_BYPASS_INIT_CAL == "SIM_INIT_CAL_FULL")
|
||||
#2500000000.0;
|
||||
else
|
||||
#1000000000.0;
|
||||
if (!init_calib_complete) begin
|
||||
$display("TEST FAILED: INITIALIZATION DID NOT COMPLETE");
|
||||
end
|
||||
disable calibration_done;
|
||||
$finish;
|
||||
end
|
||||
join
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
+103
@@ -0,0 +1,103 @@
|
||||
###############################################################################
|
||||
## (c) Copyright 2008 – 2009 Xilinx, Inc. All rights reserved.
|
||||
##
|
||||
## This file contains confidential and proprietary information
|
||||
## of Xilinx, Inc. and is protected under U.S. and
|
||||
## international copyright and other intellectual property
|
||||
## laws.
|
||||
##
|
||||
## DISCLAIMER
|
||||
## This disclaimer is not a license and does not grant any
|
||||
## rights to the materials distributed herewith. Except as
|
||||
## otherwise provided in a valid license issued to you by
|
||||
## Xilinx, and to the maximum extent permitted by applicable
|
||||
## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
## (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
## including negligence, or under any other theory of
|
||||
## liability) for any loss or damage of any kind or nature
|
||||
## related to, arising under or in connection with these
|
||||
## materials, including for any direct, or any indirect,
|
||||
## special, incidental, or consequential loss or damage
|
||||
## (including loss of data, profits, goodwill, or any type of
|
||||
## loss or damage suffered as a result of any action brought
|
||||
## by a third party) even if such damage or loss was
|
||||
## reasonably foreseeable or Xilinx had been advised of the
|
||||
## possibility of the same.
|
||||
##
|
||||
## CRITICAL APPLICATIONS
|
||||
## Xilinx products are not designed or intended to be fail-
|
||||
## safe, or for use in any application requiring fail-safe
|
||||
## performance, such as life-support or safety devices or
|
||||
## systems, Class III medical devices, nuclear facilities,
|
||||
## applications related to the deployment of airbags, or any
|
||||
## other applications that could lead to death, personal
|
||||
## injury, or severe property or environmental damage
|
||||
## (individually and collectively, "Critical
|
||||
## Applications"). Customer assumes the sole risk and
|
||||
## liability of any use of Xilinx products in Critical
|
||||
## Applications, subject only to applicable laws and
|
||||
## regulations governing limitations on product liability.
|
||||
##
|
||||
## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
## PART OF THIS FILE AT ALL TIMES.
|
||||
##
|
||||
###############################################################################
|
||||
## ____ ____
|
||||
## / /\/ /
|
||||
## /___/ \ / Vendor : Xilinx
|
||||
## \ \ \/ Version : 4.2
|
||||
## \ \ Application : MIG
|
||||
## / / Filename : vcs_run.sh
|
||||
## /___/ /\ Date Last Modified : $Date: 2011/06/02 08:31:17 $
|
||||
## \ \ / \ Date Created : Tue Oct 29 2013
|
||||
## \___\/\___\
|
||||
##
|
||||
## Device : 7 Series
|
||||
## Purpose :
|
||||
## Sample vcs_run.sh file to compile and simulate memory interface
|
||||
## design and run the simulation for specified period of time.
|
||||
## Display the waveforms that are listed with "add wave" command.
|
||||
## Assumptions :
|
||||
## Simulation takes place in \sim folder of MIG output directory.
|
||||
## Reference :
|
||||
## Revision History :
|
||||
###############################################################################
|
||||
|
||||
#echo Simulation Tool: VCS
|
||||
|
||||
#Compile the required libraries here#
|
||||
#libraries path#
|
||||
|
||||
#Compile all modules#
|
||||
vlogan -sverilog ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/system_top_mig_7series_0_0.v > vcs_sim.log
|
||||
vlogan -sverilog ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/system_top_mig_7series_0_0_mig_sim.v >> vcs_sim.log
|
||||
vlogan -sverilog mig_7series*.v >> vcs_sim.log
|
||||
vlogan -sverilog ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/clocking/*.v >> vcs_sim.log
|
||||
vlogan -sverilog ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/controller/*.v >> vcs_sim.log
|
||||
vlogan -sverilog ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/ecc/*.v >> vcs_sim.log
|
||||
vlogan -sverilog ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/ip_top/*.v >> vcs_sim.log
|
||||
vlogan -sverilog ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/phy/*.v >> vcs_sim.log
|
||||
vlogan -sverilog ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/ui/*.v >> vcs_sim.log
|
||||
|
||||
vlogan -sverilog ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/axi/*.v >> vcs_sim.log
|
||||
|
||||
|
||||
vlogan -sverilog example_top.v >> vcs_sim.log
|
||||
|
||||
#Compile files in sim folder (excluding model parameter file)#
|
||||
#$XILINX variable must be set
|
||||
vlogan $XILINX_VIVADO/data/verilog/src/glbl.v >> vcs_sim.log
|
||||
vlogan -sverilog wiredly.v >> vcs_sim.log
|
||||
vlogan -sverilog sim_tb_top.v >> vcs_sim.log
|
||||
|
||||
#Pass the parameters for memory model parameter file#
|
||||
vlogan -Xcheck_p1800_2009=char -sverilog +define+x1Gb +define+sg125 +define+x8 ddr3_model.sv >> vcs_sim.log
|
||||
|
||||
#Simulate the design with sim_tb_top as the top module
|
||||
vcs -R -debug_pp -lca sim_tb_top glbl >> vcs_sim.log
|
||||
#echo done
|
||||
|
||||
+160
@@ -0,0 +1,160 @@
|
||||
//*****************************************************************************
|
||||
// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
//*****************************************************************************
|
||||
// ____ ____
|
||||
// / /\/ /
|
||||
// /___/ \ / Vendor : Xilinx
|
||||
// \ \ \/ Version : 4.2
|
||||
// \ \ Application : MIG
|
||||
// / / Filename : wiredly.v
|
||||
// /___/ /\ Date Last Modified : $Date: 2011/06/23 08:25:20 $
|
||||
// \ \ / \ Date Created : Tue Sept 21 2010
|
||||
// \___\/\___\
|
||||
//
|
||||
// Device : 7Series
|
||||
// Design Name : DDR3 SDRAM
|
||||
// Purpose :
|
||||
// This module provide the definition of a zero ohm component (A, B).
|
||||
//
|
||||
// The applications of this component include:
|
||||
// . Normal operation of a jumper wire (data flowing in both directions)
|
||||
// This can corrupt data from DRAM to FPGA useful for verifying ECC function.
|
||||
//
|
||||
// The component consists of 2 ports:
|
||||
// . Port A: One side of the pass-through switch
|
||||
// . Port B: The other side of the pass-through switch
|
||||
|
||||
// The model is sensitive to transactions on all ports. Once a transaction
|
||||
// is detected, all other transactions are ignored for that simulation time
|
||||
// (i.e. further transactions in that delta time are ignored).
|
||||
|
||||
// Model Limitations and Restrictions:
|
||||
// Signals asserted on the ports of the error injector should not have
|
||||
// transactions occuring in multiple delta times because the model
|
||||
// is sensitive to transactions on port A, B ONLY ONCE during
|
||||
// a simulation time. Thus, once fired, a process will
|
||||
// not refire if there are multiple transactions occuring in delta times.
|
||||
// This condition may occur in gate level simulations with
|
||||
// ZERO delays because transactions may occur in multiple delta times.
|
||||
//
|
||||
// Reference :
|
||||
// Revision History :
|
||||
//*****************************************************************************
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
module WireDelay # (
|
||||
parameter Delay_g = 0,
|
||||
parameter Delay_rd = 0,
|
||||
parameter ERR_INSERT = "OFF"
|
||||
)
|
||||
(
|
||||
inout A,
|
||||
inout B,
|
||||
input reset,
|
||||
input phy_init_done
|
||||
);
|
||||
|
||||
reg A_r;
|
||||
reg B_r;
|
||||
reg B_inv ;
|
||||
reg line_en;
|
||||
|
||||
reg B_nonX;
|
||||
|
||||
assign A = A_r;
|
||||
assign B = B_r;
|
||||
|
||||
always @ (*)
|
||||
begin
|
||||
if (B === 1'bx)
|
||||
B_nonX <= $random;
|
||||
else
|
||||
B_nonX <= B;
|
||||
end
|
||||
|
||||
always@(*)
|
||||
begin
|
||||
if((B_nonX == 'b1) || (B_nonX == 'b0))
|
||||
B_inv <= #0 ~B_nonX ;
|
||||
else
|
||||
B_inv <= #0 'bz ;
|
||||
end
|
||||
|
||||
always @(*) begin
|
||||
if (!reset) begin
|
||||
A_r <= 1'bz;
|
||||
B_r <= 1'bz;
|
||||
line_en <= 1'b0;
|
||||
end else begin
|
||||
if (line_en) begin
|
||||
B_r <= 1'bz;
|
||||
if ((ERR_INSERT == "ON") & (phy_init_done))
|
||||
A_r <= #Delay_rd B_inv;
|
||||
else
|
||||
A_r <= #Delay_rd B_nonX;
|
||||
end else begin
|
||||
B_r <= #Delay_g A;
|
||||
A_r <= 1'bz;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(A or B) begin
|
||||
if (!reset) begin
|
||||
line_en <= 1'b0;
|
||||
end else if (A !== A_r) begin
|
||||
line_en <= 1'b0;
|
||||
end else if (B_r !== B) begin
|
||||
line_en <= 1'b1;
|
||||
end else begin
|
||||
line_en <= line_en;
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
||||
+181
@@ -0,0 +1,181 @@
|
||||
-------------------------------------------------------------------------------
|
||||
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-------------------------------------------------------------------------------
|
||||
-- ____ ____
|
||||
-- / /\/ /
|
||||
-- /___/ \ / Vendor : Xilinx
|
||||
-- \ \ \/ Version : 4.2
|
||||
-- \ \ Application : MIG
|
||||
-- / / Filename : xsim_files.prj
|
||||
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 08:31:16 $
|
||||
-- \ \ / \ Date Created : Tue Jun 05 2012
|
||||
-- \___\/\___\
|
||||
--
|
||||
-- Device : 7 Series
|
||||
-- Design Name : DDR3 SDRAM
|
||||
-- Purpose : Contains a list of all the files associated with a design
|
||||
-- Assumptions:
|
||||
-- - Simulation takes place in \sim folder of MIG output directory
|
||||
-- Reference :
|
||||
-- Revision History:
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
verilog work mig_7series_v4_2_axi4_tg.v
|
||||
verilog work mig_7series_v4_2_axi4_wrapper.v
|
||||
verilog work mig_7series_v4_2_cmd_prbs_gen_axi.v
|
||||
verilog work mig_7series_v4_2_data_gen_chk.v
|
||||
verilog work mig_7series_v4_2_tg.v
|
||||
verilog work example_top.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_ctrl_addr_decode.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_ctrl_read.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_ctrl_reg.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_ctrl_reg_bank.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_ctrl_top.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_ctrl_write.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_mc.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_mc_ar_channel.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_mc_aw_channel.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_mc_b_channel.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_mc_cmd_arbiter.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_mc_cmd_fsm.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_mc_cmd_translator.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_mc_fifo.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_mc_incr_cmd.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_mc_r_channel.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_mc_simple_fifo.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_mc_wrap_cmd.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_mc_wr_cmd_fsm.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_mc_w_channel.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_ddr_axic_register_slice.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_ddr_axi_register_slice.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_ddr_axi_upsizer.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_ddr_a_upsizer.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_ddr_carry_and.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_ddr_carry_latch_and.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_ddr_carry_latch_or.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_ddr_carry_or.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_ddr_command_fifo.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_ddr_comparator.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_ddr_comparator_sel.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_ddr_comparator_sel_static.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_ddr_r_upsizer.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_ddr_w_upsizer.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/clocking/mig_7series_v4_2_clk_ibuf.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/clocking/mig_7series_v4_2_iodelay_ctrl.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/clocking/mig_7series_v4_2_tempmon.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/controller/mig_7series_v4_2_arb_mux.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/controller/mig_7series_v4_2_arb_row_col.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/controller/mig_7series_v4_2_arb_select.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/controller/mig_7series_v4_2_bank_common.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/controller/mig_7series_v4_2_bank_compare.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/controller/mig_7series_v4_2_bank_mach.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/controller/mig_7series_v4_2_bank_state.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/controller/mig_7series_v4_2_col_mach.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/controller/mig_7series_v4_2_mc.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/controller/mig_7series_v4_2_rank_cntrl.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/controller/mig_7series_v4_2_rank_common.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/controller/mig_7series_v4_2_rank_mach.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/ecc/mig_7series_v4_2_ecc_buf.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/ecc/mig_7series_v4_2_ecc_dec_fix.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/ecc/mig_7series_v4_2_ecc_gen.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/ecc/mig_7series_v4_2_ecc_merge_enc.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/ecc/mig_7series_v4_2_fi_xor.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/ip_top/mig_7series_v4_2_memc_ui_top_axi.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/ip_top/mig_7series_v4_2_mem_intfc.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_if_post_fifo.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal_hr.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_cntlr.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_data.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_edge.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_lim.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_mux.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_po_cntlr.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_samp.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_oclkdelay_cal.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_tempmon.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_top.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl_off_delay.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_prbs_gen.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_skip_calib_tap.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_poc_cc.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_poc_edge_store.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_poc_meta.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_poc_pd.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_poc_tap_base.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_poc_top.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/system_top_mig_7series_0_0.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/system_top_mig_7series_0_0_mig_sim.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/ui/mig_7series_v4_2_ui_cmd.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/ui/mig_7series_v4_2_ui_top.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/ui/mig_7series_v4_2_ui_wr_data.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/system_top_mig_7series_0_0.v
|
||||
verilog work ../system_top_mig_7series_0_0_ex.srcs/sources_1/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/user_design/rtl/system_top_mig_7series_0_0_mig_sim.v
|
||||
verilog work $XILINX_VIVADO/data/verilog/src/glbl.v
|
||||
sv work ddr3_model.sv -d x1Gb -d sg125 -d x8
|
||||
verilog work wiredly.v
|
||||
verilog work sim_tb_top.v
|
||||
|
||||
+71
@@ -0,0 +1,71 @@
|
||||
###############################################################################
|
||||
## (c) Copyright 2012 Xilinx, Inc. All rights reserved.
|
||||
##
|
||||
## This file contains confidential and proprietary information
|
||||
## of Xilinx, Inc. and is protected under U.S. and
|
||||
## international copyright and other intellectual property
|
||||
## laws.
|
||||
##
|
||||
## DISCLAIMER
|
||||
## This disclaimer is not a license and does not grant any
|
||||
## rights to the materials distributed herewith. Except as
|
||||
## otherwise provided in a valid license issued to you by
|
||||
## Xilinx, and to the maximum extent permitted by applicable
|
||||
## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
## (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
## including negligence, or under any other theory of
|
||||
## liability) for any loss or damage of any kind or nature
|
||||
## related to, arising under or in connection with these
|
||||
## materials, including for any direct, or any indirect,
|
||||
## special, incidental, or consequential loss or damage
|
||||
## (including loss of data, profits, goodwill, or any type of
|
||||
## loss or damage suffered as a result of any action brought
|
||||
## by a third party) even if such damage or loss was
|
||||
## reasonably foreseeable or Xilinx had been advised of the
|
||||
## possibility of the same.
|
||||
##
|
||||
## CRITICAL APPLICATIONS
|
||||
## Xilinx products are not designed or intended to be fail-
|
||||
## safe, or for use in any application requiring fail-safe
|
||||
## performance, such as life-support or safety devices or
|
||||
## systems, Class III medical devices, nuclear facilities,
|
||||
## applications related to the deployment of airbags, or any
|
||||
## other applications that could lead to death, personal
|
||||
## injury, or severe property or environmental damage
|
||||
## (individually and collectively, "Critical
|
||||
## Applications"). Customer assumes the sole risk and
|
||||
## liability of any use of Xilinx products in Critical
|
||||
## Applications, subject only to applicable laws and
|
||||
## regulations governing limitations on product liability.
|
||||
##
|
||||
## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
## PART OF THIS FILE AT ALL TIMES.
|
||||
##
|
||||
###############################################################################
|
||||
## ____ ____
|
||||
## / /\/ /
|
||||
## /___/ \ / Vendor : Xilinx
|
||||
## \ \ \/ Version : 4.2
|
||||
## \ \ Application : MIG
|
||||
## / / Filename : xsim_options.tcl
|
||||
## /___/ /\ Date Last Modified : $Date: 2011/06/02 08:31:16 $
|
||||
## \ \ / \ Date Created : Tue Jun 05 2012
|
||||
## \___\/\___\
|
||||
##
|
||||
## Device : 7 Series
|
||||
## Design Name : DDR3 SDRAM
|
||||
## Purpose : To give commands to XSIM Simulator through batch mode
|
||||
## Assumptions:
|
||||
## - Simulation takes place in \sim folder of MIG output directory
|
||||
## Reference :
|
||||
## Revision History:
|
||||
###############################################################################
|
||||
|
||||
|
||||
add_wave -radix hex /sim_tb_top
|
||||
run 1000 us
|
||||
|
||||
+72
@@ -0,0 +1,72 @@
|
||||
::!/bin/csh -f
|
||||
::*****************************************************************************
|
||||
:: (c) Copyright 2012 Xilinx, Inc. All rights reserved.
|
||||
::
|
||||
:: This file contains confidential and proprietary information
|
||||
:: of Xilinx, Inc. and is protected under U.S. and
|
||||
:: international copyright and other intellectual property
|
||||
:: laws.
|
||||
::
|
||||
:: DISCLAIMER
|
||||
:: This disclaimer is not a license and does not grant any
|
||||
:: rights to the materials distributed herewith. Except as
|
||||
:: otherwise provided in a valid license issued to you by
|
||||
:: Xilinx, and to the maximum extent permitted by applicable
|
||||
:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
:: (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
:: including negligence, or under any other theory of
|
||||
:: liability) for any loss or damage of any kind or nature
|
||||
:: related to, arising under or in connection with these
|
||||
:: materials, including for any direct, or any indirect,
|
||||
:: special, incidental, or consequential loss or damage
|
||||
:: (including loss of data, profits, goodwill, or any type of
|
||||
:: loss or damage suffered as a result of any action brought
|
||||
:: by a third party) even if such damage or loss was
|
||||
:: reasonably foreseeable or Xilinx had been advised of the
|
||||
:: possibility of the same.
|
||||
::
|
||||
:: CRITICAL APPLICATIONS
|
||||
:: Xilinx products are not designed or intended to be fail-
|
||||
:: safe, or for use in any application requiring fail-safe
|
||||
:: performance, such as life-support or safety devices or
|
||||
:: systems, Class III medical devices, nuclear facilities,
|
||||
:: applications related to the deployment of airbags, or any
|
||||
:: other applications that could lead to death, personal
|
||||
:: injury, or severe property or environmental damage
|
||||
:: (individually and collectively, "Critical
|
||||
:: Applications"). Customer assumes the sole risk and
|
||||
:: liability of any use of Xilinx products in Critical
|
||||
:: Applications, subject only to applicable laws and
|
||||
:: regulations governing limitations on product liability.
|
||||
::
|
||||
:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
:: PART OF THIS FILE AT ALL TIMES.
|
||||
::
|
||||
:: ****************************************************************************
|
||||
:: ____ ____
|
||||
:: / /\/ /
|
||||
:: /___/ \ / Vendor : Xilinx
|
||||
:: \ \ \/ Version : 4.2
|
||||
:: \ \ Application : MIG
|
||||
:: / / Filename : xsim_run.bat
|
||||
:: /___/ /\ Date Last Modified : $Date: 2011/06/02 08:31:16 $
|
||||
:: \ \ / \ Date Created : Tue Jun 05 2012
|
||||
:: \___\/\___\
|
||||
::
|
||||
:: Device : 7 Series
|
||||
:: Design Name : DDR3 SDRAM
|
||||
:: Purpose : Batch file to run Simulation through Vivado Simulator
|
||||
:: Reference :
|
||||
:: Revision History :
|
||||
:: ****************************************************************************
|
||||
|
||||
|
||||
echo Simulation Tool: Viavdo Simulator
|
||||
call xelab work.sim_tb_top work.glbl -prj xsim_files.prj -L unisims_ver -L secureip -s xsim_test -debug typical
|
||||
xsim -g -t xsim_options.tcl -wdb xsim_database.wdb xsim_test
|
||||
echo done
|
||||
|
||||
+222
@@ -0,0 +1,222 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<Project NoOfControllers="1">
|
||||
|
||||
<ModuleName>system_top_mig_7series_0_0</ModuleName>
|
||||
|
||||
<dci_inouts_inputs>1</dci_inouts_inputs>
|
||||
|
||||
<dci_inputs>1</dci_inputs>
|
||||
|
||||
<Debug_En>OFF</Debug_En>
|
||||
|
||||
<DataDepth_En>1024</DataDepth_En>
|
||||
|
||||
<LowPower_En>ON</LowPower_En>
|
||||
|
||||
<XADC_En>Enabled</XADC_En>
|
||||
|
||||
<TargetFPGA>xc7z045-ffg900/-2</TargetFPGA>
|
||||
|
||||
<Version>4.2</Version>
|
||||
|
||||
<SystemClock>Differential</SystemClock>
|
||||
|
||||
<ReferenceClock>Use System Clock</ReferenceClock>
|
||||
|
||||
<SysResetPolarity>ACTIVE HIGH</SysResetPolarity>
|
||||
|
||||
<BankSelectionFlag>FALSE</BankSelectionFlag>
|
||||
|
||||
<InternalVref>0</InternalVref>
|
||||
|
||||
<dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs>
|
||||
|
||||
<dci_cascade>1</dci_cascade>
|
||||
|
||||
<Controller number="0">
|
||||
<MemoryDevice>DDR3_SDRAM/SODIMMs/MT8JTF12864HZ-1G6</MemoryDevice>
|
||||
<TimePeriod>1250</TimePeriod>
|
||||
<VccAuxIO>1.8V</VccAuxIO>
|
||||
<PHYRatio>4:1</PHYRatio>
|
||||
<InputClkFreq>200</InputClkFreq>
|
||||
<UIExtraClocks>1</UIExtraClocks>
|
||||
<MMCM_VCO>800</MMCM_VCO>
|
||||
<MMCMClkOut0> 8.000</MMCMClkOut0>
|
||||
<MMCMClkOut1>1</MMCMClkOut1>
|
||||
<MMCMClkOut2>1</MMCMClkOut2>
|
||||
<MMCMClkOut3>1</MMCMClkOut3>
|
||||
<MMCMClkOut4>1</MMCMClkOut4>
|
||||
<DataWidth>64</DataWidth>
|
||||
<DeepMemory>1</DeepMemory>
|
||||
<DataMask>1</DataMask>
|
||||
<ECC>Disabled</ECC>
|
||||
<Ordering>Normal</Ordering>
|
||||
<BankMachineCnt>4</BankMachineCnt>
|
||||
<CustomPart>FALSE</CustomPart>
|
||||
<NewPartName></NewPartName>
|
||||
<RowAddress>14</RowAddress>
|
||||
<ColAddress>10</ColAddress>
|
||||
<BankAddress>3</BankAddress>
|
||||
<MemoryVoltage>1.5V</MemoryVoltage>
|
||||
<C0_MEM_SIZE>1073741824</C0_MEM_SIZE>
|
||||
<UserMemoryAddressMap>BANK_ROW_COLUMN</UserMemoryAddressMap>
|
||||
<PinSelection>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="E10" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_addr[0]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="D6" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_addr[10]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="B7" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_addr[11]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="H12" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_addr[12]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="A10" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_addr[13]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="B9" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_addr[1]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="E11" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_addr[2]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="A9" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_addr[3]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="D11" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_addr[4]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="B6" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_addr[5]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="F9" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_addr[6]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="E8" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_addr[7]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="B10" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_addr[8]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="J8" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_addr[9]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="F8" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_ba[0]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="H7" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_ba[1]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="A7" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_ba[2]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="E7" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_cas_n"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL15" PADName="F10" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_ck_n[0]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL15" PADName="G10" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_ck_p[0]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="D10" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_cke[0]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="J11" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_cs_n[0]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="J3" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dm[0]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="F2" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dm[1]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="E1" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dm[2]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="C2" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dm[3]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="L12" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dm[4]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="G14" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dm[5]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="C16" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dm[6]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="C11" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dm[7]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="L1" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dq[0]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="H6" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dq[10]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="H3" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dq[11]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="G1" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dq[12]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="H2" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dq[13]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="G5" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dq[14]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="G4" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dq[15]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="E2" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dq[16]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="E3" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dq[17]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="D4" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dq[18]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="E5" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dq[19]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="L2" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dq[1]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="F4" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dq[20]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="F3" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dq[21]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="D1" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dq[22]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="D3" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dq[23]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="A2" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dq[24]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="B2" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dq[25]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="B4" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dq[26]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="B5" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dq[27]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="A3" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dq[28]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="B1" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dq[29]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="K5" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dq[2]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="C1" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dq[30]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="C4" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dq[31]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="K10" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dq[32]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="L9" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dq[33]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="K12" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dq[34]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="J9" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dq[35]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="K11" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dq[36]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="L10" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dq[37]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="J10" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dq[38]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="L7" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dq[39]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="J4" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dq[3]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="F14" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dq[40]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="F15" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dq[41]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="F13" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dq[42]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="G16" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dq[43]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="G15" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dq[44]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="E12" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dq[45]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="D13" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dq[46]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="E13" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dq[47]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="D15" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dq[48]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="E15" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dq[49]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="K1" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dq[4]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="D16" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dq[50]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="E16" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dq[51]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="C17" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dq[52]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="B16" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dq[53]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="D14" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dq[54]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="B17" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dq[55]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="B12" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dq[56]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="C12" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dq[57]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="A12" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dq[58]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="A14" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dq[59]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="L3" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dq[5]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="A13" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dq[60]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="B11" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dq[61]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="C14" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dq[62]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="B14" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dq[63]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="J5" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dq[6]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="K6" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dq[7]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="G6" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dq[8]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="H4" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dq[9]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="K2" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dqs_n[0]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="H1" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dqs_n[1]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="D5" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dqs_n[2]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="A4" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dqs_n[3]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="K8" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dqs_n[4]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="F12" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dqs_n[5]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="E17" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dqs_n[6]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="A15" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dqs_n[7]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="K3" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dqs_p[0]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="J1" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dqs_p[1]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="E6" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dqs_p[2]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="A5" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dqs_p[3]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="L8" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dqs_p[4]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="G12" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dqs_p[5]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="F17" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dqs_p[6]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="B15" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_dqs_p[7]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="G7" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_odt[0]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="H11" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_ras_n"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="LVCMOS15" PADName="G17" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_reset_n"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="F7" SLEW="FAST" VCCAUX_IO="NORMAL" name="ddr3_we_n"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL15" PADName="G9" SLEW="" VCCAUX_IO="DONTCARE" name="sys_clk_n"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL15" PADName="H9" SLEW="" VCCAUX_IO="DONTCARE" name="sys_clk_p"/>
|
||||
</PinSelection>
|
||||
<System_Clock>
|
||||
<Pin Bank="34" PADName="H9/G9(CC_P/N)" name="sys_clk_p/n"/>
|
||||
</System_Clock>
|
||||
<System_Control>
|
||||
<Pin Bank="Select Bank" PADName="No connect" name="sys_rst"/>
|
||||
<Pin Bank="Select Bank" PADName="No connect" name="init_calib_complete"/>
|
||||
<Pin Bank="Select Bank" PADName="No connect" name="tg_compare_error"/>
|
||||
</System_Control>
|
||||
<TimingParameters>
|
||||
<Parameters tcke="5" tfaw="30" tras="35" trcd="13.125" trefi="7.8" trfc="110" trp="13.125" trrd="6" trtp="7.5" twtr="7.5"/>
|
||||
</TimingParameters>
|
||||
<mrBurstLength name="Burst Length">8 - Fixed</mrBurstLength>
|
||||
<mrBurstType name="Read Burst Type and Length">Sequential</mrBurstType>
|
||||
<mrCasLatency name="CAS Latency">11</mrCasLatency>
|
||||
<mrMode name="Mode">Normal</mrMode>
|
||||
<mrDllReset name="DLL Reset">No</mrDllReset>
|
||||
<mrPdMode name="DLL control for precharge PD">Slow Exit</mrPdMode>
|
||||
<emrDllEnable name="DLL Enable">Enable</emrDllEnable>
|
||||
<emrOutputDriveStrength name="Output Driver Impedance Control">RZQ/7</emrOutputDriveStrength>
|
||||
<emrMirrorSelection name="Address Mirroring">Disable</emrMirrorSelection>
|
||||
<emrCSSelection name="Controller Chip Select Pin">Enable</emrCSSelection>
|
||||
<emrRTT name="RTT (nominal) - On Die Termination (ODT)">RZQ/6</emrRTT>
|
||||
<emrPosted name="Additive Latency (AL)">0</emrPosted>
|
||||
<emrOCD name="Write Leveling Enable">Disabled</emrOCD>
|
||||
<emrDQS name="TDQS enable">Enabled</emrDQS>
|
||||
<emrRDQS name="Qoff">Output Buffer Enabled</emrRDQS>
|
||||
<mr2PartialArraySelfRefresh name="Partial-Array Self Refresh">Full Array</mr2PartialArraySelfRefresh>
|
||||
<mr2CasWriteLatency name="CAS write latency">8</mr2CasWriteLatency>
|
||||
<mr2AutoSelfRefresh name="Auto Self Refresh">Enabled</mr2AutoSelfRefresh>
|
||||
<mr2SelfRefreshTempRange name="High Temparature Self Refresh Rate">Normal</mr2SelfRefreshTempRange>
|
||||
<mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)">Dynamic ODT off</mr2RTTWR>
|
||||
<PortInterface>AXI</PortInterface>
|
||||
<AXIParameters>
|
||||
<C0_C_RD_WR_ARB_ALGORITHM>RD_PRI_REG</C0_C_RD_WR_ARB_ALGORITHM>
|
||||
<C0_S_AXI_ADDR_WIDTH>32</C0_S_AXI_ADDR_WIDTH>
|
||||
<C0_S_AXI_DATA_WIDTH>512</C0_S_AXI_DATA_WIDTH>
|
||||
<C0_S_AXI_ID_WIDTH>2</C0_S_AXI_ID_WIDTH>
|
||||
<C0_S_AXI_SUPPORTS_NARROW_BURST>0</C0_S_AXI_SUPPORTS_NARROW_BURST>
|
||||
</AXIParameters>
|
||||
</Controller>
|
||||
|
||||
</Project>
|
||||
+303157
File diff suppressed because one or more lines are too long
+341710
File diff suppressed because it is too large
Load Diff
+97
@@ -0,0 +1,97 @@
|
||||
// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
|
||||
// Date : Mon Jun 13 15:55:53 2022
|
||||
// Host : CXHPWKS01 running 64-bit Service Pack 1 (build 7601)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top system_top_mig_7series_0_0 -prefix
|
||||
// system_top_mig_7series_0_0_ system_top_mig_7series_0_0_stub.v
|
||||
// Design : system_top_mig_7series_0_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z045ffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
module system_top_mig_7series_0_0(ddr3_dq, ddr3_dqs_n, ddr3_dqs_p, ddr3_addr,
|
||||
ddr3_ba, ddr3_ras_n, ddr3_cas_n, ddr3_we_n, ddr3_reset_n, ddr3_ck_p, ddr3_ck_n, ddr3_cke,
|
||||
ddr3_cs_n, ddr3_dm, ddr3_odt, sys_clk_p, sys_clk_n, ui_clk, ui_clk_sync_rst, ui_addn_clk_0,
|
||||
ui_addn_clk_1, ui_addn_clk_2, ui_addn_clk_3, ui_addn_clk_4, mmcm_locked, aresetn,
|
||||
app_sr_active, app_ref_ack, app_zq_ack, s_axi_awid, s_axi_awaddr, s_axi_awlen, s_axi_awsize,
|
||||
s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot, s_axi_awqos, s_axi_awvalid,
|
||||
s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wlast, s_axi_wvalid, s_axi_wready,
|
||||
s_axi_bready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_arid, s_axi_araddr, s_axi_arlen,
|
||||
s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache, s_axi_arprot, s_axi_arqos,
|
||||
s_axi_arvalid, s_axi_arready, s_axi_rready, s_axi_rid, s_axi_rdata, s_axi_rresp, s_axi_rlast,
|
||||
s_axi_rvalid, init_calib_complete, device_temp, sys_rst)
|
||||
/* synthesis syn_black_box black_box_pad_pin="ddr3_dq[63:0],ddr3_dqs_n[7:0],ddr3_dqs_p[7:0],ddr3_addr[13:0],ddr3_ba[2:0],ddr3_ras_n,ddr3_cas_n,ddr3_we_n,ddr3_reset_n,ddr3_ck_p[0:0],ddr3_ck_n[0:0],ddr3_cke[0:0],ddr3_cs_n[0:0],ddr3_dm[7:0],ddr3_odt[0:0],sys_clk_p,sys_clk_n,ui_clk,ui_clk_sync_rst,ui_addn_clk_0,ui_addn_clk_1,ui_addn_clk_2,ui_addn_clk_3,ui_addn_clk_4,mmcm_locked,aresetn,app_sr_active,app_ref_ack,app_zq_ack,s_axi_awid[1:0],s_axi_awaddr[31:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[0:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[511:0],s_axi_wstrb[63:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bready,s_axi_bid[1:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_arid[1:0],s_axi_araddr[31:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[0:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rready,s_axi_rid[1:0],s_axi_rdata[511:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,init_calib_complete,device_temp[11:0],sys_rst" */;
|
||||
inout [63:0]ddr3_dq;
|
||||
inout [7:0]ddr3_dqs_n;
|
||||
inout [7:0]ddr3_dqs_p;
|
||||
output [13:0]ddr3_addr;
|
||||
output [2:0]ddr3_ba;
|
||||
output ddr3_ras_n;
|
||||
output ddr3_cas_n;
|
||||
output ddr3_we_n;
|
||||
output ddr3_reset_n;
|
||||
output [0:0]ddr3_ck_p;
|
||||
output [0:0]ddr3_ck_n;
|
||||
output [0:0]ddr3_cke;
|
||||
output [0:0]ddr3_cs_n;
|
||||
output [7:0]ddr3_dm;
|
||||
output [0:0]ddr3_odt;
|
||||
input sys_clk_p;
|
||||
input sys_clk_n;
|
||||
output ui_clk;
|
||||
output ui_clk_sync_rst;
|
||||
output ui_addn_clk_0;
|
||||
output ui_addn_clk_1;
|
||||
output ui_addn_clk_2;
|
||||
output ui_addn_clk_3;
|
||||
output ui_addn_clk_4;
|
||||
output mmcm_locked;
|
||||
input aresetn;
|
||||
output app_sr_active;
|
||||
output app_ref_ack;
|
||||
output app_zq_ack;
|
||||
input [1:0]s_axi_awid;
|
||||
input [31:0]s_axi_awaddr;
|
||||
input [7:0]s_axi_awlen;
|
||||
input [2:0]s_axi_awsize;
|
||||
input [1:0]s_axi_awburst;
|
||||
input [0:0]s_axi_awlock;
|
||||
input [3:0]s_axi_awcache;
|
||||
input [2:0]s_axi_awprot;
|
||||
input [3:0]s_axi_awqos;
|
||||
input s_axi_awvalid;
|
||||
output s_axi_awready;
|
||||
input [511:0]s_axi_wdata;
|
||||
input [63:0]s_axi_wstrb;
|
||||
input s_axi_wlast;
|
||||
input s_axi_wvalid;
|
||||
output s_axi_wready;
|
||||
input s_axi_bready;
|
||||
output [1:0]s_axi_bid;
|
||||
output [1:0]s_axi_bresp;
|
||||
output s_axi_bvalid;
|
||||
input [1:0]s_axi_arid;
|
||||
input [31:0]s_axi_araddr;
|
||||
input [7:0]s_axi_arlen;
|
||||
input [2:0]s_axi_arsize;
|
||||
input [1:0]s_axi_arburst;
|
||||
input [0:0]s_axi_arlock;
|
||||
input [3:0]s_axi_arcache;
|
||||
input [2:0]s_axi_arprot;
|
||||
input [3:0]s_axi_arqos;
|
||||
input s_axi_arvalid;
|
||||
output s_axi_arready;
|
||||
input s_axi_rready;
|
||||
output [1:0]s_axi_rid;
|
||||
output [511:0]s_axi_rdata;
|
||||
output [1:0]s_axi_rresp;
|
||||
output s_axi_rlast;
|
||||
output s_axi_rvalid;
|
||||
output init_calib_complete;
|
||||
output [11:0]device_temp;
|
||||
input sys_rst;
|
||||
endmodule
|
||||
+96
@@ -0,0 +1,96 @@
|
||||
-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
|
||||
-- Date : Mon Jun 13 15:55:53 2022
|
||||
-- Host : CXHPWKS01 running 64-bit Service Pack 1 (build 7601)
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top system_top_mig_7series_0_0 -prefix
|
||||
-- system_top_mig_7series_0_0_ system_top_mig_7series_0_0_stub.vhdl
|
||||
-- Design : system_top_mig_7series_0_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z045ffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity system_top_mig_7series_0_0 is
|
||||
Port (
|
||||
ddr3_dq : inout STD_LOGIC_VECTOR ( 63 downto 0 );
|
||||
ddr3_dqs_n : inout STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
ddr3_dqs_p : inout STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
ddr3_addr : out STD_LOGIC_VECTOR ( 13 downto 0 );
|
||||
ddr3_ba : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
ddr3_ras_n : out STD_LOGIC;
|
||||
ddr3_cas_n : out STD_LOGIC;
|
||||
ddr3_we_n : out STD_LOGIC;
|
||||
ddr3_reset_n : out STD_LOGIC;
|
||||
ddr3_ck_p : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
ddr3_ck_n : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
ddr3_cke : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
ddr3_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
ddr3_dm : out STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
ddr3_odt : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
sys_clk_p : in STD_LOGIC;
|
||||
sys_clk_n : in STD_LOGIC;
|
||||
ui_clk : out STD_LOGIC;
|
||||
ui_clk_sync_rst : out STD_LOGIC;
|
||||
ui_addn_clk_0 : out STD_LOGIC;
|
||||
ui_addn_clk_1 : out STD_LOGIC;
|
||||
ui_addn_clk_2 : out STD_LOGIC;
|
||||
ui_addn_clk_3 : out STD_LOGIC;
|
||||
ui_addn_clk_4 : out STD_LOGIC;
|
||||
mmcm_locked : out STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
app_sr_active : out STD_LOGIC;
|
||||
app_ref_ack : out STD_LOGIC;
|
||||
app_zq_ack : out STD_LOGIC;
|
||||
s_axi_awid : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_awvalid : in STD_LOGIC;
|
||||
s_axi_awready : out STD_LOGIC;
|
||||
s_axi_wdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
s_axi_wstrb : in STD_LOGIC_VECTOR ( 63 downto 0 );
|
||||
s_axi_wlast : in STD_LOGIC;
|
||||
s_axi_wvalid : in STD_LOGIC;
|
||||
s_axi_wready : out STD_LOGIC;
|
||||
s_axi_bready : in STD_LOGIC;
|
||||
s_axi_bid : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_bvalid : out STD_LOGIC;
|
||||
s_axi_arid : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_arvalid : in STD_LOGIC;
|
||||
s_axi_arready : out STD_LOGIC;
|
||||
s_axi_rready : in STD_LOGIC;
|
||||
s_axi_rid : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_rdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_rlast : out STD_LOGIC;
|
||||
s_axi_rvalid : out STD_LOGIC;
|
||||
init_calib_complete : out STD_LOGIC;
|
||||
device_temp : out STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
sys_rst : in STD_LOGIC
|
||||
);
|
||||
|
||||
end system_top_mig_7series_0_0;
|
||||
|
||||
architecture stub of system_top_mig_7series_0_0 is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "ddr3_dq[63:0],ddr3_dqs_n[7:0],ddr3_dqs_p[7:0],ddr3_addr[13:0],ddr3_ba[2:0],ddr3_ras_n,ddr3_cas_n,ddr3_we_n,ddr3_reset_n,ddr3_ck_p[0:0],ddr3_ck_n[0:0],ddr3_cke[0:0],ddr3_cs_n[0:0],ddr3_dm[7:0],ddr3_odt[0:0],sys_clk_p,sys_clk_n,ui_clk,ui_clk_sync_rst,ui_addn_clk_0,ui_addn_clk_1,ui_addn_clk_2,ui_addn_clk_3,ui_addn_clk_4,mmcm_locked,aresetn,app_sr_active,app_ref_ack,app_zq_ack,s_axi_awid[1:0],s_axi_awaddr[31:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[0:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[511:0],s_axi_wstrb[63:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bready,s_axi_bid[1:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_arid[1:0],s_axi_araddr[31:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[0:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rready,s_axi_rid[1:0],s_axi_rdata[511:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,init_calib_complete,device_temp[11:0],sys_rst";
|
||||
begin
|
||||
end;
|
||||
+455
@@ -0,0 +1,455 @@
|
||||
# The package naming convention is <core_name>_xmdf
|
||||
package provide system_top_mig_7series_0_0_xmdf 1.0
|
||||
|
||||
# This includes some utilities that support common XMDF operations
|
||||
package require utilities_xmdf
|
||||
|
||||
# Define a namespace for this package. The name of the name space
|
||||
# is <core_name>_xmdf
|
||||
namespace eval ::system_top_mig_7series_0_0_xmdf {
|
||||
# Use this to define any statics
|
||||
}
|
||||
|
||||
# Function called by client to rebuild the params and port arrays
|
||||
# Optional when the use context does not require the param or ports
|
||||
# arrays to be available.
|
||||
proc ::system_top_mig_7series_0_0_xmdf::xmdfInit { instance } {
|
||||
# Variable containing name of library into which module is compiled
|
||||
# Recommendation: <module_name>
|
||||
# Required
|
||||
utilities_xmdf::xmdfSetData $instance Module Attributes Name system_top_mig_7series_0_0
|
||||
}
|
||||
# ::system_top_mig_7series_0_0_xmdf::xmdfInit
|
||||
|
||||
# Function called by client to fill in all the xmdf* data variables
|
||||
# based on the current settings of the parameters
|
||||
proc ::system_top_mig_7series_0_0_xmdf::xmdfApplyParams { instance } {
|
||||
|
||||
set fcount 0
|
||||
# Array containing libraries that are assumed to exist
|
||||
# Examples include unisim and xilinxcorelib
|
||||
# Optional
|
||||
# In this example, we assume that the unisim library will
|
||||
# be magically
|
||||
# available to the simulation and synthesis tool
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_ctrl_addr_decode.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_ctrl_read.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_ctrl_reg.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_ctrl_reg_bank.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_ctrl_top.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_ctrl_write.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_mc.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_mc_ar_channel.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_mc_aw_channel.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_mc_b_channel.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_mc_cmd_arbiter.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_mc_cmd_fsm.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_mc_cmd_translator.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_mc_fifo.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_mc_incr_cmd.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_mc_r_channel.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_mc_simple_fifo.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_mc_wrap_cmd.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_mc_wr_cmd_fsm.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_mc_w_channel.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_ddr_axic_register_slice.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_ddr_axi_register_slice.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_ddr_axi_upsizer.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_ddr_a_upsizer.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_ddr_carry_and.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_ddr_carry_latch_and.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_ddr_carry_latch_or.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_ddr_carry_or.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_ddr_command_fifo.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_ddr_comparator.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_ddr_comparator_sel.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_ddr_comparator_sel_static.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_ddr_r_upsizer.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_ddr_w_upsizer.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/clocking/mig_7series_v4_2_clk_ibuf.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/clocking/mig_7series_v4_2_iodelay_ctrl.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/clocking/mig_7series_v4_2_tempmon.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/controller/mig_7series_v4_2_arb_mux.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/controller/mig_7series_v4_2_arb_row_col.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/controller/mig_7series_v4_2_arb_select.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/controller/mig_7series_v4_2_bank_common.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/controller/mig_7series_v4_2_bank_compare.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/controller/mig_7series_v4_2_bank_mach.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/controller/mig_7series_v4_2_bank_state.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/controller/mig_7series_v4_2_col_mach.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/controller/mig_7series_v4_2_mc.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/controller/mig_7series_v4_2_rank_cntrl.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/controller/mig_7series_v4_2_rank_common.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/controller/mig_7series_v4_2_rank_mach.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/ecc/mig_7series_v4_2_ecc_buf.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/ecc/mig_7series_v4_2_ecc_dec_fix.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/ecc/mig_7series_v4_2_ecc_gen.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/ecc/mig_7series_v4_2_ecc_merge_enc.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/ecc/mig_7series_v4_2_fi_xor.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/ip_top/mig_7series_v4_2_memc_ui_top_axi.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/ip_top/mig_7series_v4_2_mem_intfc.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_if_post_fifo.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal_hr.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_cntlr.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_data.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_edge.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_lim.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_mux.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_po_cntlr.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_samp.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_oclkdelay_cal.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_tempmon.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_top.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl_off_delay.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_prbs_gen.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_skip_calib_tap.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_poc_cc.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_poc_edge_store.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_poc_meta.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_poc_pd.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_poc_tap_base.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_poc_top.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/system_top_mig_7series_0_0.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/system_top_mig_7series_0_0_mig.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/ui/mig_7series_v4_2_ui_cmd.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/ui/mig_7series_v4_2_ui_top.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/rtl/ui/mig_7series_v4_2_ui_wr_data.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/constraints/system_top_mig_7series_0_0.ucf
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ucf
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module system_top_mig_7series_0_0
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path system_top_mig_7series_0_0/user_design/constraints/system_top_mig_7series_0_0.xdc
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type xdc
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module system_top_mig_7series_0_0
|
||||
incr fcount
|
||||
|
||||
}
|
||||
|
||||
# ::gen_comp_name_xmdf::xmdfApplyParams
|
||||
+24
@@ -0,0 +1,24 @@
|
||||
SET_FLAG MODE BATCH
|
||||
SET_FLAG STANDALONE_MODE TRUE
|
||||
SET_PREFERENCE ipi_mode yes
|
||||
SET_PREFERENCE is_ip_locked false
|
||||
SET_PREFERENCE devicefamily zynq
|
||||
SET_PREFERENCE device xc7z045
|
||||
SET_PREFERENCE speedgrade -2
|
||||
SET_PREFERENCE package ffg900
|
||||
SET_PREFERENCE verilogsim true
|
||||
SET_PREFERENCE vhdlsim false
|
||||
SET_PREFERENCE designentry Verilog
|
||||
SET_PREFERENCE outputdirectory c:/Users/Dell/Desktop/syb/20240418cxhop/project_fix_dac.srcs/sources_1/bd/system_top/ip/system_top_mig_7series_0_0/_tmp/
|
||||
SET_PREFERENCE subworkingdirectory c:/Users/Dell/Desktop/syb/20240418cxhop/project_fix_dac.srcs/sources_1/bd/system_top/ip/system_top_mig_7series_0_0/_tmp/
|
||||
SET_PREFERENCE flowvendor Other
|
||||
SET_PREFERENCE tool vivado
|
||||
SET_PREFERENCE compnamestatus 0
|
||||
SET_PARAMETER component_name system_top_mig_7series_0_0
|
||||
SET_PARAMETER xml_input_file C:/Users/Dell/Desktop/syb/20240418cxhop/project_fix_dac.srcs/sources_1/bd/system_top/ip/system_top_mig_7series_0_0/board.prj
|
||||
SET_PARAMETER data_dir_path c:/Xilinx/Vivado/2018.3/data/ip/xilinx/mig_7series_v4_2
|
||||
SET_CORE_NAME Memory Interface Generator (MIG 7 Series)
|
||||
SET_CORE_VERSION 4.2
|
||||
SET_CORE_VLNV xilinx.com:ip:mig_7series:4.2
|
||||
SET_CORE_PATH c:/Xilinx/Vivado/2018.3/data/ip/xilinx/mig_7series_v4_2
|
||||
SET_CORE_DATASHEET c:/Xilinx/Vivado/2018.3/data/ip/xilinx/mig_7series_v4_2/data/docs/ds176_7series_MIS.pdf
|
||||
+4
@@ -0,0 +1,4 @@
|
||||
SET_ERROR_CODE 0
|
||||
SET_XMDF_PATH ./system_top_mig_7series_0_0_xmdf.tcl
|
||||
SET_PARAMETER component_name system_top_mig_7series_0_0
|
||||
SET_PARAMETER xml_input_file ./system_top_mig_7series_0_0/mig.prj
|
||||
+196
@@ -0,0 +1,196 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "system_top_proc_sys_reset_0_0",
|
||||
"cell_name": "proc_sys_reset_0",
|
||||
"component_reference": "xilinx.com:ip:proc_sys_reset:5.0",
|
||||
"ip_revision": "15",
|
||||
"gen_directory": "../../../../../../project_fix_dac.gen/sources_1/bd/system_top/ip/system_top_proc_sys_reset_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"C_NUM_PERP_ARESETN": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_INTERCONNECT_ARESETN": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_PERP_RST": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_BUS_RST": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_AUX_RESET_HIGH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_EXT_RESET_HIGH": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_AUX_RST_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_EXT_RST_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "system_top_proc_sys_reset_0_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"USE_BOARD_FLOW": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"RESET_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_FAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_EXT_RST_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AUX_RST_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_EXT_RESET_HIGH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AUX_RESET_HIGH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_BUS_RST": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_PERP_RST": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_INTERCONNECT_ARESETN": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_PERP_ARESETN": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "xilinx.com:zc706:part0:1.4" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z045" } ],
|
||||
"NEXTGEN_VERSAL": [ { "value": "0" } ],
|
||||
"PACKAGE": [ { "value": "ffg900" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "15" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../project_fix_dac.gen/sources_1/bd/system_top/ip/system_top_proc_sys_reset_0_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2024.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"slowest_sync_clk": [ { "direction": "in" } ],
|
||||
"ext_reset_in": [ { "direction": "in" } ],
|
||||
"aux_reset_in": [ { "direction": "in", "driver_value": "1" } ],
|
||||
"mb_debug_sys_rst": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"dcm_locked": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"mb_reset": [ { "direction": "out", "driver_value": "0x0" } ],
|
||||
"bus_struct_reset": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"peripheral_reset": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"interconnect_aresetn": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "1" } ],
|
||||
"peripheral_aresetn": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "1" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"clock": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_RESET": [ { "value": "mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "200000000", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_mig_7series_0_0_ui_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "slowest_sync_clk" } ]
|
||||
}
|
||||
},
|
||||
"ext_reset": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"BOARD.ASSOCIATED_PARAM": [ { "value": "RESET_BOARD_INTERFACE", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "ext_reset_in" } ]
|
||||
}
|
||||
},
|
||||
"aux_reset": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "aux_reset_in" } ]
|
||||
}
|
||||
},
|
||||
"dbg_reset": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "mb_debug_sys_rst" } ]
|
||||
}
|
||||
},
|
||||
"mb_rst": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"TYPE": [ { "value": "PROCESSOR", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "mb_reset" } ]
|
||||
}
|
||||
},
|
||||
"bus_struct_reset": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"TYPE": [ { "value": "INTERCONNECT", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "bus_struct_reset" } ]
|
||||
}
|
||||
},
|
||||
"interconnect_low_rst": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"TYPE": [ { "value": "INTERCONNECT", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "interconnect_aresetn" } ]
|
||||
}
|
||||
},
|
||||
"peripheral_high_rst": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"TYPE": [ { "value": "PERIPHERAL", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "peripheral_reset" } ]
|
||||
}
|
||||
},
|
||||
"peripheral_low_rst": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"TYPE": [ { "value": "PERIPHERAL", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "peripheral_aresetn" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+643
@@ -0,0 +1,643 @@
|
||||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<!DOCTYPE designInfo PUBLIC "designInfo" "designInfo.dtd" >
|
||||
<designInfo version="1.0" >
|
||||
<MODULE IP_TYPE="SOC" MOD_CLASS="CONFIGURABLE" MODTYPE="processing_system7" >
|
||||
<PARAMETERS >
|
||||
<PARAMETER NAME="PCW_APU_CLK_RATIO_ENABLE" VALUE="6:2:1" />
|
||||
<PARAMETER NAME="PCW_APU_PERIPHERAL_FREQMHZ" VALUE="667.000000" />
|
||||
<PARAMETER NAME="PCW_ARMPLL_CTRL_FBDIV" VALUE="40" />
|
||||
<PARAMETER NAME="PCW_CAN0_CAN0_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_CAN0_GRP_CLK_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_CAN0_GRP_CLK_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_CAN0_PERIPHERAL_CLKSRC" VALUE="External" />
|
||||
<PARAMETER NAME="PCW_CAN0_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_CAN0_PERIPHERAL_FREQMHZ" VALUE="" />
|
||||
<PARAMETER NAME="PCW_CAN1_CAN1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_CAN1_GRP_CLK_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_CAN1_GRP_CLK_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_CAN1_PERIPHERAL_CLKSRC" VALUE="External" />
|
||||
<PARAMETER NAME="PCW_CAN1_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_CAN1_PERIPHERAL_FREQMHZ" VALUE="" />
|
||||
<PARAMETER NAME="PCW_CAN_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_CAN_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_CAN_PERIPHERAL_DIVISOR1" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_CAN_PERIPHERAL_FREQMHZ" VALUE="100" />
|
||||
<PARAMETER NAME="PCW_CPU_CPU_PLL_FREQMHZ" VALUE="1333.333" />
|
||||
<PARAMETER NAME="PCW_CPU_PERIPHERAL_CLKSRC" VALUE="ARM PLL" />
|
||||
<PARAMETER NAME="PCW_CPU_PERIPHERAL_DIVISOR0" VALUE="2" />
|
||||
<PARAMETER NAME="PCW_CRYSTAL_PERIPHERAL_FREQMHZ" VALUE="33.333333" />
|
||||
<PARAMETER NAME="PCW_DCI_PERIPHERAL_CLKSRC" VALUE="DDR PLL" />
|
||||
<PARAMETER NAME="PCW_DCI_PERIPHERAL_DIVISOR0" VALUE="15" />
|
||||
<PARAMETER NAME="PCW_DCI_PERIPHERAL_DIVISOR1" VALUE="7" />
|
||||
<PARAMETER NAME="PCW_DCI_PERIPHERAL_FREQMHZ" VALUE="10.159" />
|
||||
<PARAMETER NAME="PCW_DDRPLL_CTRL_FBDIV" VALUE="32" />
|
||||
<PARAMETER NAME="PCW_DDR_DDR_PLL_FREQMHZ" VALUE="1066.667" />
|
||||
<PARAMETER NAME="PCW_DDR_HPRLPR_QUEUE_PARTITION" VALUE="HPR(0)/LPR(32)" />
|
||||
<PARAMETER NAME="PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL" VALUE="15" />
|
||||
<PARAMETER NAME="PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL" VALUE="2" />
|
||||
<PARAMETER NAME="PCW_DDR_PERIPHERAL_CLKSRC" VALUE="DDR PLL" />
|
||||
<PARAMETER NAME="PCW_DDR_PERIPHERAL_DIVISOR0" VALUE="2" />
|
||||
<PARAMETER NAME="PCW_DDR_PORT0_HPR_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PORT1_HPR_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PORT2_HPR_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PORT3_HPR_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_0" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_1" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_2" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_3" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_0" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_1" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_2" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_3" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL" VALUE="2" />
|
||||
<PARAMETER NAME="PCW_DUAL_PARALLEL_QSPI_DATA_MODE" VALUE="x8" />
|
||||
<PARAMETER NAME="PCW_DUAL_STACK_QSPI_DATA_MODE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET0_ENET0_IO" VALUE="MIO 16 .. 27" />
|
||||
<PARAMETER NAME="PCW_ENET0_GRP_MDIO_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_ENET0_GRP_MDIO_IO" VALUE="MIO 52 .. 53" />
|
||||
<PARAMETER NAME="PCW_ENET0_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_ENET0_PERIPHERAL_DIVISOR0" VALUE="8" />
|
||||
<PARAMETER NAME="PCW_ENET0_PERIPHERAL_DIVISOR1" VALUE="5" />
|
||||
<PARAMETER NAME="PCW_ENET0_PERIPHERAL_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_ENET0_PERIPHERAL_FREQMHZ" VALUE="100 Mbps" />
|
||||
<PARAMETER NAME="PCW_ENET0_RESET_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_ENET0_RESET_IO" VALUE="MIO 47" />
|
||||
<PARAMETER NAME="PCW_ENET1_ENET1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET1_GRP_MDIO_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET1_GRP_MDIO_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET1_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_ENET1_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_ENET1_PERIPHERAL_DIVISOR1" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_ENET1_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_ENET1_PERIPHERAL_FREQMHZ" VALUE="1000 Mbps" />
|
||||
<PARAMETER NAME="PCW_ENET1_RESET_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET1_RESET_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET_RESET_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_ENET_RESET_POLARITY" VALUE="Active Low" />
|
||||
<PARAMETER NAME="PCW_ENET_RESET_SELECT" VALUE="Share reset pin" />
|
||||
<PARAMETER NAME="PCW_EN_4K_TIMER" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_EN_CLK0_PORT" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_EN_CLK1_PORT" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_EN_CLK2_PORT" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_EN_CLK3_PORT" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_FCLK0_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_FCLK0_PERIPHERAL_DIVISOR0" VALUE="5" />
|
||||
<PARAMETER NAME="PCW_FCLK0_PERIPHERAL_DIVISOR1" VALUE="2" />
|
||||
<PARAMETER NAME="PCW_FCLK1_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_FCLK1_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_FCLK1_PERIPHERAL_DIVISOR1" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_FCLK2_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_FCLK2_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_FCLK2_PERIPHERAL_DIVISOR1" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_FCLK3_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_FCLK3_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_FCLK3_PERIPHERAL_DIVISOR1" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_FCLK_CLK0_BUF" VALUE="TRUE" />
|
||||
<PARAMETER NAME="PCW_FCLK_CLK1_BUF" VALUE="FALSE" />
|
||||
<PARAMETER NAME="PCW_FCLK_CLK2_BUF" VALUE="FALSE" />
|
||||
<PARAMETER NAME="PCW_FCLK_CLK3_BUF" VALUE="FALSE" />
|
||||
<PARAMETER NAME="PCW_FPGA0_PERIPHERAL_FREQMHZ" VALUE="100" />
|
||||
<PARAMETER NAME="PCW_FPGA1_PERIPHERAL_FREQMHZ" VALUE="50" />
|
||||
<PARAMETER NAME="PCW_FPGA2_PERIPHERAL_FREQMHZ" VALUE="50" />
|
||||
<PARAMETER NAME="PCW_FPGA3_PERIPHERAL_FREQMHZ" VALUE="50" />
|
||||
<PARAMETER NAME="PCW_FTM_CTI_IN0" VALUE="" />
|
||||
<PARAMETER NAME="PCW_FTM_CTI_IN1" VALUE="" />
|
||||
<PARAMETER NAME="PCW_FTM_CTI_IN2" VALUE="" />
|
||||
<PARAMETER NAME="PCW_FTM_CTI_IN3" VALUE="" />
|
||||
<PARAMETER NAME="PCW_FTM_CTI_OUT0" VALUE="" />
|
||||
<PARAMETER NAME="PCW_FTM_CTI_OUT1" VALUE="" />
|
||||
<PARAMETER NAME="PCW_FTM_CTI_OUT2" VALUE="" />
|
||||
<PARAMETER NAME="PCW_FTM_CTI_OUT3" VALUE="" />
|
||||
<PARAMETER NAME="PCW_GPIO_EMIO_GPIO_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_GPIO_EMIO_GPIO_IO" VALUE="64" />
|
||||
<PARAMETER NAME="PCW_GPIO_MIO_GPIO_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_GPIO_MIO_GPIO_IO" VALUE="MIO" />
|
||||
<PARAMETER NAME="PCW_GPIO_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_I2C0_GRP_INT_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_I2C0_GRP_INT_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_I2C0_I2C0_IO" VALUE="MIO 50 .. 51" />
|
||||
<PARAMETER NAME="PCW_I2C0_PERIPHERAL_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_I2C0_RESET_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_I2C0_RESET_IO" VALUE="MIO 46" />
|
||||
<PARAMETER NAME="PCW_I2C1_GRP_INT_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_I2C1_GRP_INT_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_I2C1_I2C1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_I2C1_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_I2C1_RESET_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_I2C1_RESET_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_I2C_RESET_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_I2C_RESET_POLARITY" VALUE="Active Low" />
|
||||
<PARAMETER NAME="PCW_I2C_RESET_SELECT" VALUE="Share reset pin" />
|
||||
<PARAMETER NAME="PCW_IOPLL_CTRL_FBDIV" VALUE="30" />
|
||||
<PARAMETER NAME="PCW_IO_IO_PLL_FREQMHZ" VALUE="1000.000" />
|
||||
<PARAMETER NAME="PCW_IRQ_F2P_MODE" VALUE="DIRECT" />
|
||||
<PARAMETER NAME="PCW_MIO_0_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_0_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_0_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_0_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_10_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_10_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_10_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_10_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_11_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_11_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_11_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_11_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_12_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_12_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_12_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_12_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_13_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_13_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_13_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_13_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_14_DIRECTION" VALUE="in" />
|
||||
<PARAMETER NAME="PCW_MIO_14_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_14_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_14_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_15_DIRECTION" VALUE="in" />
|
||||
<PARAMETER NAME="PCW_MIO_15_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_15_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_15_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_16_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_16_IOTYPE" VALUE="HSTL 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_16_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_16_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_17_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_17_IOTYPE" VALUE="HSTL 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_17_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_17_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_18_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_18_IOTYPE" VALUE="HSTL 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_18_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_18_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_19_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_19_IOTYPE" VALUE="HSTL 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_19_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_19_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_1_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_1_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_1_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_1_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_20_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_20_IOTYPE" VALUE="HSTL 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_20_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_20_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_21_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_21_IOTYPE" VALUE="HSTL 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_21_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_21_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_22_DIRECTION" VALUE="in" />
|
||||
<PARAMETER NAME="PCW_MIO_22_IOTYPE" VALUE="HSTL 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_22_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_22_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_23_DIRECTION" VALUE="in" />
|
||||
<PARAMETER NAME="PCW_MIO_23_IOTYPE" VALUE="HSTL 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_23_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_23_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_24_DIRECTION" VALUE="in" />
|
||||
<PARAMETER NAME="PCW_MIO_24_IOTYPE" VALUE="HSTL 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_24_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_24_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_25_DIRECTION" VALUE="in" />
|
||||
<PARAMETER NAME="PCW_MIO_25_IOTYPE" VALUE="HSTL 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_25_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_25_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_26_DIRECTION" VALUE="in" />
|
||||
<PARAMETER NAME="PCW_MIO_26_IOTYPE" VALUE="HSTL 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_26_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_26_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_27_DIRECTION" VALUE="in" />
|
||||
<PARAMETER NAME="PCW_MIO_27_IOTYPE" VALUE="HSTL 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_27_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_27_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_28_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_28_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_28_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_28_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_29_DIRECTION" VALUE="in" />
|
||||
<PARAMETER NAME="PCW_MIO_29_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_29_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_29_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_2_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_2_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_2_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_2_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_30_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_30_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_30_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_30_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_31_DIRECTION" VALUE="in" />
|
||||
<PARAMETER NAME="PCW_MIO_31_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_31_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_31_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_32_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_32_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_32_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_32_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_33_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_33_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_33_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_33_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_34_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_34_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_34_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_34_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_35_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_35_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_35_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_35_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_36_DIRECTION" VALUE="in" />
|
||||
<PARAMETER NAME="PCW_MIO_36_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_36_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_36_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_37_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_37_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_37_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_37_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_38_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_38_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_38_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_38_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_39_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_39_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_39_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_39_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_3_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_3_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_3_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_3_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_40_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_40_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_40_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_40_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_41_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_41_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_41_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_41_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_42_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_42_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_42_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_42_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_43_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_43_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_43_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_43_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_44_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_44_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_44_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_44_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_45_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_45_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_45_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_45_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_46_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_46_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_46_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_46_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_47_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_47_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_47_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_47_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_48_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_48_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_48_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_48_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_49_DIRECTION" VALUE="in" />
|
||||
<PARAMETER NAME="PCW_MIO_49_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_49_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_49_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_4_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_4_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_4_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_4_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_50_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_50_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_50_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_50_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_51_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_51_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_51_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_51_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_52_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_52_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_52_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_52_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_53_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_53_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_53_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_53_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_5_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_5_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_5_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_5_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_6_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_6_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_6_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_6_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_7_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_7_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_7_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_7_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_8_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_8_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_8_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_8_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_9_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_9_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_9_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_9_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_NAND_CYCLES_T_AR" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NAND_CYCLES_T_CLR" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NAND_CYCLES_T_RC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NAND_CYCLES_T_REA" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NAND_CYCLES_T_RR" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NAND_CYCLES_T_WC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NAND_CYCLES_T_WP" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NAND_GRP_D8_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NAND_GRP_D8_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NAND_NAND_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NAND_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_NOR_CS0_T_CEOE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_CS0_T_PC" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_CS0_T_RC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NOR_CS0_T_TR" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_CS0_T_WC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NOR_CS0_T_WP" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_CS0_WE_TIME" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_NOR_CS1_T_CEOE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_CS1_T_PC" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_CS1_T_RC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NOR_CS1_T_TR" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_CS1_T_WC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NOR_CS1_T_WP" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_CS1_WE_TIME" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_A25_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_A25_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_CS0_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_CS0_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_CS1_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_CS1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_SRAM_CS0_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_SRAM_CS0_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_SRAM_CS1_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_SRAM_CS1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_SRAM_INT_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_SRAM_INT_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_NOR_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS0_T_CEOE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS0_T_PC" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS0_T_RC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS0_T_TR" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS0_T_WC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS0_T_WP" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS0_WE_TIME" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_CEOE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_PC" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_RC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_TR" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_WC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_WP" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS1_WE_TIME" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_OVERRIDE_BASIC_CLOCK" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_PCAP_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_PCAP_PERIPHERAL_DIVISOR0" VALUE="5" />
|
||||
<PARAMETER NAME="PCW_PCAP_PERIPHERAL_FREQMHZ" VALUE="200" />
|
||||
<PARAMETER NAME="PCW_PJTAG_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_PJTAG_PJTAG_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_PLL_BYPASSMODE_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_PRESET_BANK0_VOLTAGE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_PRESET_BANK1_VOLTAGE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_QSPI_GRP_FBCLK_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_QSPI_GRP_FBCLK_IO" VALUE="MIO 8" />
|
||||
<PARAMETER NAME="PCW_QSPI_GRP_IO1_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_QSPI_GRP_IO1_IO" VALUE="MIO 0 9 .. 13" />
|
||||
<PARAMETER NAME="PCW_QSPI_GRP_SINGLE_SS_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_QSPI_GRP_SINGLE_SS_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_QSPI_GRP_SS1_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_QSPI_GRP_SS1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_QSPI_INTERNAL_HIGHADDRESS" VALUE="0xFDFFFFFF" />
|
||||
<PARAMETER NAME="PCW_QSPI_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_QSPI_PERIPHERAL_DIVISOR0" VALUE="5" />
|
||||
<PARAMETER NAME="PCW_QSPI_PERIPHERAL_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_QSPI_PERIPHERAL_FREQMHZ" VALUE="200" />
|
||||
<PARAMETER NAME="PCW_QSPI_QSPI_IO" VALUE="MIO 1 .. 6" />
|
||||
<PARAMETER NAME="PCW_SD0_GRP_CD_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_SD0_GRP_CD_IO" VALUE="MIO 14" />
|
||||
<PARAMETER NAME="PCW_SD0_GRP_POW_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_SD0_GRP_POW_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD0_GRP_WP_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_SD0_GRP_WP_IO" VALUE="MIO 15" />
|
||||
<PARAMETER NAME="PCW_SD0_PERIPHERAL_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_SD0_SD0_IO" VALUE="MIO 40 .. 45" />
|
||||
<PARAMETER NAME="PCW_SD1_GRP_CD_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD1_GRP_CD_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD1_GRP_POW_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD1_GRP_POW_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD1_GRP_WP_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD1_GRP_WP_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD1_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_SD1_SD1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SDIO_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_SDIO_PERIPHERAL_DIVISOR0" VALUE="20" />
|
||||
<PARAMETER NAME="PCW_SDIO_PERIPHERAL_FREQMHZ" VALUE="50" />
|
||||
<PARAMETER NAME="PCW_SINGLE_QSPI_DATA_MODE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SMC_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_SMC_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_SMC_PERIPHERAL_FREQMHZ" VALUE="100" />
|
||||
<PARAMETER NAME="PCW_SPI0_GRP_SS0_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_SPI0_GRP_SS0_IO" VALUE="EMIO" />
|
||||
<PARAMETER NAME="PCW_SPI0_GRP_SS1_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_SPI0_GRP_SS1_IO" VALUE="EMIO" />
|
||||
<PARAMETER NAME="PCW_SPI0_GRP_SS2_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_SPI0_GRP_SS2_IO" VALUE="EMIO" />
|
||||
<PARAMETER NAME="PCW_SPI0_PERIPHERAL_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_SPI0_SPI0_IO" VALUE="EMIO" />
|
||||
<PARAMETER NAME="PCW_SPI1_GRP_SS0_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI1_GRP_SS0_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI1_GRP_SS1_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI1_GRP_SS1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI1_GRP_SS2_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI1_GRP_SS2_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI1_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_SPI1_SPI1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_SPI_PERIPHERAL_DIVISOR0" VALUE="6" />
|
||||
<PARAMETER NAME="PCW_SPI_PERIPHERAL_FREQMHZ" VALUE="166.666666" />
|
||||
<PARAMETER NAME="PCW_S_AXI_HP0_DATA_WIDTH" VALUE="64" />
|
||||
<PARAMETER NAME="PCW_S_AXI_HP1_DATA_WIDTH" VALUE="64" />
|
||||
<PARAMETER NAME="PCW_S_AXI_HP2_DATA_WIDTH" VALUE="64" />
|
||||
<PARAMETER NAME="PCW_S_AXI_HP3_DATA_WIDTH" VALUE="64" />
|
||||
<PARAMETER NAME="PCW_TPIU_PERIPHERAL_CLKSRC" VALUE="External" />
|
||||
<PARAMETER NAME="PCW_TPIU_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_TPIU_PERIPHERAL_FREQMHZ" VALUE="200" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_16BIT_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_16BIT_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_2BIT_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_2BIT_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_32BIT_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_32BIT_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_4BIT_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_4BIT_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_8BIT_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_8BIT_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_INTERNAL_WIDTH" VALUE="2" />
|
||||
<PARAMETER NAME="PCW_TRACE_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_TRACE_TRACE_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TTC0_CLK0_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
|
||||
<PARAMETER NAME="PCW_TTC0_CLK0_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
|
||||
<PARAMETER NAME="PCW_TTC0_CLK1_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
|
||||
<PARAMETER NAME="PCW_TTC0_CLK1_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
|
||||
<PARAMETER NAME="PCW_TTC0_CLK2_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
|
||||
<PARAMETER NAME="PCW_TTC0_CLK2_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
|
||||
<PARAMETER NAME="PCW_TTC0_PERIPHERAL_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_TTC0_TTC0_IO" VALUE="EMIO" />
|
||||
<PARAMETER NAME="PCW_TTC1_CLK0_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
|
||||
<PARAMETER NAME="PCW_TTC1_CLK0_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
|
||||
<PARAMETER NAME="PCW_TTC1_CLK1_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
|
||||
<PARAMETER NAME="PCW_TTC1_CLK1_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
|
||||
<PARAMETER NAME="PCW_TTC1_CLK2_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
|
||||
<PARAMETER NAME="PCW_TTC1_CLK2_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
|
||||
<PARAMETER NAME="PCW_TTC1_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_TTC1_TTC1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TTC_PERIPHERAL_FREQMHZ" VALUE="50" />
|
||||
<PARAMETER NAME="PCW_UART0_BAUD_RATE" VALUE="115200" />
|
||||
<PARAMETER NAME="PCW_UART0_GRP_FULL_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_UART0_GRP_FULL_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_UART0_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UART0_UART0_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_UART1_BAUD_RATE" VALUE="115200" />
|
||||
<PARAMETER NAME="PCW_UART1_GRP_FULL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UART1_GRP_FULL_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_UART1_PERIPHERAL_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_UART1_UART1_IO" VALUE="MIO 48 .. 49" />
|
||||
<PARAMETER NAME="PCW_UART_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_UART_PERIPHERAL_DIVISOR0" VALUE="20" />
|
||||
<PARAMETER NAME="PCW_UART_PERIPHERAL_FREQMHZ" VALUE="50" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_ADV_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_AL" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_BANK_ADDR_COUNT" VALUE="3" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_BL" VALUE="8" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY0" VALUE="0.521" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY1" VALUE="0.636" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY2" VALUE="0.54" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY3" VALUE="0.621" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_BUS_WIDTH" VALUE="32 Bit" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CL" VALUE="7" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH" VALUE="92.3275" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH" VALUE="92.3275" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH" VALUE="92.3275" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH" VALUE="92.3275" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_STOP_EN" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_COL_ADDR_COUNT" VALUE="10" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CWL" VALUE="6" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DEVICE_CAPACITY" VALUE="2048 MBits" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_0_LENGTH_MM" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH" VALUE="108.9255" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_1_LENGTH_MM" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH" VALUE="131.286" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_2_LENGTH_MM" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH" VALUE="131.83" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_3_LENGTH_MM" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH" VALUE="108.5285" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0" VALUE="0.226" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1" VALUE="0.278" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2" VALUE="0.184" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3" VALUE="0.309" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_0_LENGTH_MM" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH" VALUE="107.643" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_1_LENGTH_MM" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH" VALUE="132.917" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_2_LENGTH_MM" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH" VALUE="129.6135" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_3_LENGTH_MM" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH" VALUE="108.6395" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DRAM_WIDTH" VALUE="8 Bits" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_ECC" VALUE="Disabled" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_FREQ_MHZ" VALUE="533.333313" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_HIGH_TEMP" VALUE="Normal (0-85)" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_MEMORY_TYPE" VALUE="DDR 3" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_PARTNO" VALUE="Custom" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_ROW_ADDR_COUNT" VALUE="15" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_SPEED_BIN" VALUE="DDR3_1066F" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_TRAIN_DATA_EYE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_TRAIN_READ_GATE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_T_FAW" VALUE="30.0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_T_RAS_MIN" VALUE="36.0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_T_RC" VALUE="49.5" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_T_RCD" VALUE="7" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_T_RP" VALUE="7" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_USE_INTERNAL_VREF" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_USB0_PERIPHERAL_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_USB0_PERIPHERAL_FREQMHZ" VALUE="60" />
|
||||
<PARAMETER NAME="PCW_USB0_RESET_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_USB0_RESET_IO" VALUE="MIO 7" />
|
||||
<PARAMETER NAME="PCW_USB0_USB0_IO" VALUE="MIO 28 .. 39" />
|
||||
<PARAMETER NAME="PCW_USB1_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USB1_PERIPHERAL_FREQMHZ" VALUE="60" />
|
||||
<PARAMETER NAME="PCW_USB1_RESET_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_USB1_RESET_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_USB1_USB1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_USB_RESET_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_USB_RESET_POLARITY" VALUE="Active Low" />
|
||||
<PARAMETER NAME="PCW_USB_RESET_SELECT" VALUE="Share reset pin" />
|
||||
<PARAMETER NAME="PCW_USE_AXI_NONSECURE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USE_CROSS_TRIGGER" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USE_M_AXI_GP0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_USE_M_AXI_GP1" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_USE_S_AXI_ACP" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USE_S_AXI_GP0" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USE_S_AXI_GP1" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USE_S_AXI_HP0" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USE_S_AXI_HP1" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USE_S_AXI_HP2" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USE_S_AXI_HP3" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_WDT_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
|
||||
<PARAMETER NAME="PCW_WDT_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_WDT_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_WDT_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
|
||||
<PARAMETER NAME="PCW_WDT_WDT_IO" VALUE="" />
|
||||
</PARAMETERS>
|
||||
<BUSINTERFACES >
|
||||
<BUSINTERFACE NAME="M_AXI_GP0" TYPE="MASTER" WIDTH="32" PARAMTOENABLE="PCW_USE_M_AXI_GP0" VALUE="1" />
|
||||
<BUSINTERFACE NAME="M_AXI_GP1" TYPE="MASTER" WIDTH="32" PARAMTOENABLE="PCW_USE_M_AXI_GP1" VALUE="1" />
|
||||
<BUSINTERFACE NAME="S_AXI_GP0" TYPE="TARGET" WIDTH="32" PARAMTOENABLE="PCW_USE_S_AXI_GP0" VALUE="0" />
|
||||
<BUSINTERFACE NAME="S_AXI_GP0" TYPE="TARGET" WIDTH="32" PARAMTOENABLE="PCW_USE_S_AXI_GP1" VALUE="0" />
|
||||
<BUSINTERFACE NAME="S_AXI_HP0" TYPE="TARGET" WIDTH="64" PARAMTOENABLE="PCW_USE_S_AXI_HP0" VALUE="0" />
|
||||
<BUSINTERFACE NAME="S_AXI_HP1" TYPE="TARGET" WIDTH="64" PARAMTOENABLE="PCW_USE_S_AXI_HP1" VALUE="0" />
|
||||
<BUSINTERFACE NAME="S_AXI_HP2" TYPE="TARGET" WIDTH="64" PARAMTOENABLE="PCW_USE_S_AXI_HP2" VALUE="0" />
|
||||
<BUSINTERFACE NAME="S_AXI_HP3" TYPE="TARGET" WIDTH="64" PARAMTOENABLE="PCW_USE_S_AXI_HP1" VALUE="0" />
|
||||
</BUSINTERFACES>
|
||||
<CLOCKOUTS >
|
||||
<CLOCKOUT NAME="FCLK_CLK0" FREQUENCY="100.000000" />
|
||||
<CLOCKOUT NAME="FCLK_CLK1" FREQUENCY="10.000000" />
|
||||
<CLOCKOUT NAME="FCLK_CLK2" FREQUENCY="10.000000" />
|
||||
<CLOCKOUT NAME="FCLK_CLK3" FREQUENCY="10.000000" />
|
||||
</CLOCKOUTS>
|
||||
</MODULE>
|
||||
</designInfo>
|
||||
+1473
File diff suppressed because it is too large
Load Diff
+196
@@ -0,0 +1,196 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "system_top_rst_ps7_0_200M_0",
|
||||
"cell_name": "rst_ps7_0_200M",
|
||||
"component_reference": "xilinx.com:ip:proc_sys_reset:5.0",
|
||||
"ip_revision": "15",
|
||||
"gen_directory": "../../../../../../project_fix_dac.gen/sources_1/bd/system_top/ip/system_top_rst_ps7_0_200M_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"C_NUM_PERP_ARESETN": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_INTERCONNECT_ARESETN": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_PERP_RST": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_BUS_RST": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_AUX_RESET_HIGH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_EXT_RESET_HIGH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_AUX_RST_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_EXT_RST_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "system_top_rst_ps7_0_200M_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"USE_BOARD_FLOW": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"RESET_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_FAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_EXT_RST_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AUX_RST_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_EXT_RESET_HIGH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AUX_RESET_HIGH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_BUS_RST": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_PERP_RST": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_INTERCONNECT_ARESETN": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_PERP_ARESETN": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "xilinx.com:zc706:part0:1.4" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z045" } ],
|
||||
"NEXTGEN_VERSAL": [ { "value": "0" } ],
|
||||
"PACKAGE": [ { "value": "ffg900" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "15" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../project_fix_dac.gen/sources_1/bd/system_top/ip/system_top_rst_ps7_0_200M_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2024.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"slowest_sync_clk": [ { "direction": "in" } ],
|
||||
"ext_reset_in": [ { "direction": "in" } ],
|
||||
"aux_reset_in": [ { "direction": "in", "driver_value": "1" } ],
|
||||
"mb_debug_sys_rst": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"dcm_locked": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"mb_reset": [ { "direction": "out", "driver_value": "0x0" } ],
|
||||
"bus_struct_reset": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"peripheral_reset": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"interconnect_aresetn": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "1" } ],
|
||||
"peripheral_aresetn": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "1" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"clock": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_RESET": [ { "value": "mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "slowest_sync_clk" } ]
|
||||
}
|
||||
},
|
||||
"ext_reset": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
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|
||||
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||||
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||||
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||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+4021
File diff suppressed because it is too large
Load Diff
+52
@@ -0,0 +1,52 @@
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||||
{
|
||||
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|
||||
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|
||||
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|
||||
"cell_name": "util_vector_logic_0",
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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|
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}
|
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}
|
||||
}
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}
|
||||
+52
@@ -0,0 +1,52 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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||||
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||||
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|
||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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|
||||
}
|
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}
|
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|
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|
||||
+50
@@ -0,0 +1,50 @@
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||||
{
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"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "system_top_xlconstant_0_0",
|
||||
"cell_name": "xlconstant_0",
|
||||
"component_reference": "xilinx.com:ip:xlconstant:1.1",
|
||||
"ip_revision": "9",
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||||
"gen_directory": "../../../../../../project_fix_dac.gen/sources_1/bd/system_top/ip/system_top_xlconstant_0_0",
|
||||
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||||
"component_parameters": {
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||||
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||||
"CONST_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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+50
@@ -0,0 +1,50 @@
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||||
{
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
||||
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|
||||
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|
||||
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|
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|
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|
||||
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|
||||
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|
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|
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|
||||
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|
||||
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|
||||
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|
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|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
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"SWVERSION": [ { "value": "2024.1" } ],
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"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
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}
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"boundary": {
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}
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}
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}
|
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}
|
||||
+193146
File diff suppressed because it is too large
Load Diff
+50
@@ -0,0 +1,50 @@
|
||||
/*----------------------------------------------------------------------------
|
||||
* Copyright (c) 2008 AMD, Inc.
|
||||
* This design is confidential and proprietary of AMD, All Rights Reserved.
|
||||
*-----------------------------------------------------------------------------
|
||||
* ____ ____
|
||||
* / /\/ /
|
||||
* /___/ \ / Vendor: AMD
|
||||
* \ \ \/ Date Created: 2008/08/18
|
||||
* \ \
|
||||
* / /
|
||||
* /___/ /\
|
||||
* \ \ / \
|
||||
* \___\/\___\
|
||||
*
|
||||
*Device: All
|
||||
*Purpose:
|
||||
* Define Values for Verilog instatiation of icn2xsdb_mstrbr_ver
|
||||
*
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
*-- C O N S T A N T S
|
||||
*-----------------------------------------------------------------------------*/
|
||||
|
||||
`define GC_XSDB_MSI_SL_SEL_WIDTH 8 /* Slave Select Width */
|
||||
`define GC_XSDB_MSI_ADDR_WIDTH 17 /* Address Width */
|
||||
`define GC_XSDB_MSI_BRST_WD_LEN_WIDTH 17
|
||||
`define GC_XSDB_MSI_DATA_WIDTH 16 /* Data Width */
|
||||
`define GC_XSDB_MSI_BRST_CNT_WIDTH 16 /* Burst Count Width */
|
||||
`define GC_XSDB_S_IPORT_WIDTH 37 /* Slave Port input interface width */
|
||||
|
||||
`define GC_XSDB_S_OPORT_WIDTH 17 /* Slave Port output interface width */
|
||||
|
||||
`define GC_XSDB_S_ADDR_WIDTH `GC_XSDB_MSI_ADDR_WIDTH /* Slave Addr width */
|
||||
`define GC_XSDB_S_DATA_WIDTH `GC_XSDB_MSI_DATA_WIDTH /* Slave Data width */
|
||||
|
||||
`define GC_IPORT_RST_IDX 0
|
||||
`define GC_IPORT_DCLK_IDX 1
|
||||
`define GC_IPORT_DEN_IDX 2
|
||||
`define GC_IPORT_DWE_IDX 3
|
||||
`define GC_IPORT_DADDR_IDX 4
|
||||
`define GC_IPORT_DI_IDX `GC_IPORT_DADDR_IDX+`GC_XSDB_S_ADDR_WIDTH
|
||||
`define GC_OPORT_RDY_IDX 0
|
||||
`define GC_OPORT_DO_IDX 1
|
||||
|
||||
`define GC_ICN_CTL_WIDTH 36
|
||||
`define GC_ICN_CMD4_WIDTH 3 + `GC_XSDB_MSI_SL_SEL_WIDTH+ `GC_XSDB_MSI_BRST_WD_LEN_WIDTH
|
||||
`define GC_ICN_CMD5_WIDTH 1 + `GC_XSDB_MSI_ADDR_WIDTH
|
||||
`define GC_ICN_CMD6_WIDTH `GC_XSDB_MSI_DATA_WIDTH
|
||||
|
||||
+107
@@ -0,0 +1,107 @@
|
||||
/*----------------------------------------------------------------------------
|
||||
* Copyright (c) 2008 AMD, Inc.
|
||||
* This design is confidential and proprietary of AMD, All Rights Reserved.
|
||||
*-----------------------------------------------------------------------------
|
||||
* ____ ____
|
||||
* / /\/ /
|
||||
* /___/ \ / Vendor: AMD
|
||||
* \ \ \/ Date Created: 2008/08/18
|
||||
* \ \
|
||||
* / /
|
||||
* /___/ /\
|
||||
* \ \ / \
|
||||
* \___\/\___\
|
||||
*
|
||||
*Device: All
|
||||
*Purpose:
|
||||
* Define values for Verilog instatiation of labtools ip
|
||||
*
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
*-- C O N S T A N T S
|
||||
*-----------------------------------------------------------------------------*/
|
||||
|
||||
//
|
||||
// Core type (non-negative integers from 0 to 255)
|
||||
//
|
||||
`define RESERVED_MFG_ID 0
|
||||
`define XILINX_MFG_ID 1
|
||||
`define XILINX_AND_AGILENT_MFG_ID 2
|
||||
`define GC_XILINX_MFG_ID `XILINX_MFG_ID
|
||||
|
||||
//
|
||||
// Core type (non-negative integers from 0 to 255)
|
||||
//
|
||||
`define RESERVED_CORE_TYPE 0
|
||||
`define ICON_CORE_TYPE 1
|
||||
`define ILA_CORE_TYPE 2
|
||||
`define IBA_GENERIC_CORE_TYPE 3
|
||||
`define IBA_OPB_CORE_TYPE 4
|
||||
`define IBA_PLB_CORE_TYPE 5
|
||||
`define ILA_ATC_CORE_TYPE 6
|
||||
`define IBA_OPB_ATC_CORE_TYPE 7
|
||||
`define IBA_PLB_ATC_CORE_TYPE 8
|
||||
`define VIO_CORE_TYPE 9
|
||||
`define ATC2_CORE_TYPE 10
|
||||
`define ATC3_CORE_TYPE 11
|
||||
`define GC_RESERVED_CORE_TYPE2 12
|
||||
`define IBERT_CORE_TYPE 13
|
||||
`define GC_XSDB_MASTER_V1_0 14
|
||||
`define GC_ICON_NULL_CORE_TYPE 15
|
||||
|
||||
//
|
||||
// Width of the ChipScope Pro Core CONTROL port
|
||||
//
|
||||
`define CONTROL_WIDTH 36
|
||||
|
||||
// Match unit type
|
||||
`define MATCH_UNIT_TYPEA_ALLX 0
|
||||
//`define MATCH_UNIT_TYPE_GANDOR 2
|
||||
//`define MATCH_UNIT_TYPE_GANDORX 3
|
||||
|
||||
|
||||
|
||||
//
|
||||
// Device family constants
|
||||
//
|
||||
`define FAMILY_NAME_LENGTH 15 //leave room for radhard/automotive and low power part names
|
||||
`define FAMILY_VIRTEX6 "virtex6"
|
||||
`define FAMILY_VIRTEX7 "virtex7"
|
||||
`define FAMILY_VIRTEX7_LENGTH 7
|
||||
`define FAMILY_KINTEX7 "kintex7"
|
||||
`define FAMILY_KINTEX7_LENGTH 7
|
||||
`define FAMILY_ARTIX7 "artix7"
|
||||
`define FAMILY_ARTIX7_LENGTH 6
|
||||
`define FAMILY_ZYNQ "zynq"
|
||||
`define FAMILY_ZYNQ_LENGTH 4
|
||||
|
||||
//
|
||||
// Architecture match type constants, start at 100 so that code can't incorrectly mix up family and match unit type
|
||||
//
|
||||
`define ARCH_MATCH_TYPE_A 100
|
||||
|
||||
//
|
||||
// Device JTAG Stuff
|
||||
//
|
||||
`define GC_SBT_IR_W 10;
|
||||
`define GC_SBT_IR_ID_INSTR 10'b1111001001
|
||||
`define GC_SBT_IR_USER1_INSTR 10'b11_1100_0010
|
||||
`define GC_CHIP_ID_CHIPSCOPE_SBT 32'b0000_1010_0000_0000_0011_0000_1001_0011
|
||||
// 0a00_3093
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Virtex7
|
||||
//
|
||||
// IR Info
|
||||
`define GC_V7_IR_W 6
|
||||
`define GC_V7_IR_ID_INSTR 6'b00_1001
|
||||
`define GC_V7_IR_USER1_INSTR 6'b00_0010
|
||||
`define GC_V7_IR_USER2_INSTR 6'b00_0011
|
||||
`define GC_V7_IR_USER3_INSTR 6'b10_0010
|
||||
`define GC_V7_IR_USER4_INSTR 6'b10_0011
|
||||
// Chip IDs
|
||||
`define GC_CHIP_ID_XC7V285T 32'b0000_0011_1010_0110_0100_0000_1001_0011
|
||||
// 0424a093
|
||||
|
||||
|
||||
+551
@@ -0,0 +1,551 @@
|
||||
`pragma protect begin_protected
|
||||
`pragma protect version = 1
|
||||
`pragma protect encrypt_agent = "XILINX"
|
||||
`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2024.1"
|
||||
`pragma protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-2", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
|
||||
`pragma protect key_block
|
||||
lB6Fw7WYHikERyqzAwFiAj8hK0T4MEVIDm75G3ELoSLa4boGBe6RZdIGk41QtmVKhtNNBaf0fvem
|
||||
m9zmwCITlzzQb2wcRJpnOd2vmmm4Q4yH4/m3GovlRoCHQUeYn7weph1lGZwB3P8LsfuRnGSLh1qQ
|
||||
CocgouGU8FsiQ7VsDKE=
|
||||
|
||||
`pragma protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
y7UNXVYAO5qBktx2Y8WVjkjEhqy1HbQye/j3iWYObsIR2D6hh9dZYR0OhHmw78Ozifu1QtZ8ECN8
|
||||
f0VfiOcJFDem1indqbbLu7hk6PZJuUMLCUghWjhiLWsGa2Kpd8xH++5+fB5QliM/Z7lwCuWKUskt
|
||||
x8ruMCmzt/UK6M7LjNrc06kLcLhbhLLXoBboEidWfkmzbTF0NRMSPkJzphte5/boglA/OGeu2z97
|
||||
+6oDOl2y3ZvY8xVUo8y0FQlLZ3MEhTRfmlc4P6W92rAI6Omxy5MJOioheH0oMTygoniQj5PSlODp
|
||||
pgBCX11IT86M/HZ6gWYSuFA0nkwLoWhph4rBIA==
|
||||
|
||||
`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VELOCE-RSA", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
|
||||
`pragma protect key_block
|
||||
EESvLJy10IW2TJcL9bENTHCy2GW7KwoizF36VdmRN25PPwf93oFz60qNBZY7yuzwqRlGyFwInvLD
|
||||
bR47GfaAz3wyNBFu4YD2WW5d3QYjZaRUt3NWMjlwKmdhUcmZhcxpKe7PaUit2IeF0fKM+90mh3NL
|
||||
YrOXhU7eg/KblHalLwY=
|
||||
|
||||
`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-2", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
UqtfRMOcNYB9tQ8qz7Cl9sJ2TWBHWR8T2V2KnNdCTDubba+sxOnQNFdT5NUoXGFLL/0HmR/DBt+d
|
||||
YHS9Ehm8gth0Flg+lDk4DrVPK9UJlUmBPPbZ+XT5bNid21TImRhfI6Q8nPTeMamUCvmWNn/jaOxG
|
||||
MYgXMpz3ZbDTbkvl5dHRmvSMFqkrOWV1FQig0xEkt1nDCMG5Ca4atPc65doWCWDlbDRn/hfbvJfS
|
||||
iCyk2IGcXqCz6aFGh7/zbuWx6zg8lnm7iBJ9U6yQ+ZYXaRiUZpmH3GnfYdwMSIZsVXuMdnVSIMpC
|
||||
FLEpuz95Ox3AzZ1s5CmMft4/8BdgIjNDe5krjg==
|
||||
|
||||
`pragma protect key_keyowner = "Real Intent", key_keyname = "RI-RSA-KEY-1", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
moVLHksG9tOKbsurETzSQuJkFUhiJ09op+mlpfK8bRWL4xFqfrhVTOBAO7ml3fFRHqB9eZNFYf6n
|
||||
ijpRO6re5n5hglg1t2JZFcKzKAnVRuTfqbG7qNgHZu0YpiIlKmFZru3uuQa09Hu9oQMOOpoGUYx/
|
||||
EyyyG5ECtkPmypAlHEneX88VyQGV8FDm9o/B2LPUReaHUslL6DDathwbpDKnNM6GwyVOX0ieev0i
|
||||
gbifDWIgY6vMbF5uhAABfrrYC80HwRe9OQcUZoF1c7BFV2aRHdaoJrSa4U/wZSvjrNzZxT9HUzP/
|
||||
yQD994ICRM9q997fbsidyABY3mH/VXy9jIp5rw==
|
||||
|
||||
`pragma protect key_keyowner = "Metrics Technologies Inc.", key_keyname = "DSim", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
gu8mokpade0RyIEFP6MwIzUm+m9/rlyfmQvFe7/e/o7VMQ5ydrMGWlJUxwSy4xRLex4kVCHe3gEd
|
||||
EOaIjKvjKmYBbjKIkz0xtIe9YTYJA7k+2TTNjvVpSuacPyVrivyIBcGsFf3P3vfqhqFIE7cAs8/g
|
||||
vP5dJgvOHwnn3wxgqiCk7OdX2PWWIDCq3IEtZ8qyK+tvUkAzSPJTbAc03L1HTFSLEXqCiiiMwv4Z
|
||||
6hqhmTic96S6X4Jq+OoQlL8gcsvaAgf/KTDvsleobiRb9fm5Zpzj+kzPr7xNfewym8HosvTupBVx
|
||||
3R9hlT+V/qsE51jvGbTyNYurPRSW0ixBkq/96A==
|
||||
|
||||
`pragma protect key_keyowner = "Xilinx", key_keyname = "xilinxt_2023_11", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
d/uxydgxMj19c0AyUS7gzl9Lio7Arjjdh7lgeViQg8Sj4zOVsrl/FCE7Y+QLaD74oF1bQBCoozYu
|
||||
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|
||||
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|
||||
IGZIk2DZFmiecrFH+I3BaCS9igJI6kGuQPqxJxXlkEGvAXDazTRP6+6lvh+7GBdTTAiCYvQVVkeB
|
||||
xXurlXAHX7WUGlOKrinDQl826Bwh7rELCyFVtQ==
|
||||
|
||||
`pragma protect key_keyowner = "Atrenta", key_keyname = "ATR-SG-RSA-1", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 384)
|
||||
`pragma protect key_block
|
||||
s1+FCOI5pFtZQZyr1s37QQ3G6FC9fXGWUoIf8zAKU7HP8JrIw939WdDEwhJ84Rjt9NdMFsT7oWfE
|
||||
TVpleg3GXKqPfBqkjIZT320JNYc3fWsDh3JzygIpD9VSbnlfcIXE4OCq4CoCsNGFTPWDzsVodEjk
|
||||
3nlEKx0FINRmdsaXOC6GzJaLRRNwBnp2LCGHs+YW9+OtYX7s+dlNhxtfSF3l4BOJtWQmSQHuT4sZ
|
||||
GZ0tiqINJnq+6MWAS02t63fH6EPF87XIEhxKK8g89HuTmuwKlwV2p3WYVYLZHsy6BmEQEUOgWohS
|
||||
e3oVzctYorl6yEv3wdJqf+QngAXg1zdVWaaxHpJMkyE5rHDv9stuJpD9hiLkwM9ToVYGBqHFTtcr
|
||||
pKg2mmKEkcpm1NweKrK6z6BoUPzl6/Fo6/UU9mUV4LaA5yIwxMgry/kLg8crnq2M4FE8/rqBDzbx
|
||||
lCuzGymzHGIYnkq8UtBf1cQKZHZBTzLtVkVNmvWDFewwTafTMxnOY4r4
|
||||
|
||||
`pragma protect key_keyowner = "Cadence Design Systems.", key_keyname = "CDS_RSA_KEY_VER_1", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
S1ncenbNpKjKJletwqr/lYSd4fWGBAohtc9+CwEVHMEpRs1AkU56NJUjs2t8yT7diJ0JeVLtZH+/
|
||||
KwOTuDB77YdlW71kfk9WNGvi77CCUU4x2EIFJMS02FKlJsQEsNIp1fKBdDBzBosp/yE+cp4aG1nL
|
||||
WU/ObfJZImbaDbn8ZU7OvW2DUIW3xa1Oisp7b+eulp3kCXM0eSVcjC48wY9x+m+LZXSeU1ODyu6L
|
||||
STlaTrKTJYn+oJCgOiQWlg/KnGNTwAiFHiFkkKKX1RxX3U5xSwik+uZ/8LDEjP7DBKfY55XHROGy
|
||||
OIUHcyT7eSRRZk3eQAu8V9x57XybKd3opRjuJA==
|
||||
|
||||
`pragma protect key_keyowner = "Synplicity", key_keyname = "SYNP15_1", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
LewSLYRinJ6BmwTc8plgGL3FdWSWo7w/+h8YHrlNLizMv4dtbB9ISeLgAZgOSTjvH19JmV7vyBxo
|
||||
Lgiw+TqhXnM2wOuyUaBMuZ2rzr9LEqWhIUxMX4z5sWJR6oDPplGZqz0Dm+KiG6WwCpfLJHBV7+93
|
||||
XOK+enHuwJ0tfCk59SeJXA0qfgLyTUWP2DFk7IESSMIcYqAoPgtmwkgXhgCfUKOTc3uohmo9VwLA
|
||||
EkisA94Z4aNOgwRt4ql8X7iCEE5cV/isYo46FnRc9H8ou3FrSIQqqKY7qroAGth3HERxbnKVbWUq
|
||||
1wXY/26vl2GJTwwuHO9FAEHy2/MLOWBZfZYYJg==
|
||||
|
||||
`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-PREC-RSA", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
HiwxPcyyS+DXozEnup3F37/qTjzABWOVHn3NY7CmM4QNFkcmw3XFpsMPNxXwHBTcvYM0R+dHlxs5
|
||||
/LX0GIr//xbd4W/rXwG/6zpN3Is+y+ZgBwY38NyNtOee5lhW1FYDufMDIXvlsApHl+5rl21AMs4m
|
||||
hzAHQuslKDto6R3aU8WlKc4c4v9mo/ZnyfJlyzlBReizxut6+Pdhn3NfMMysd+mJRbhm4cca5uLx
|
||||
vI+PWWHh3H08rQI+0x3lIO/3/7ldba6Kyr6LRlx7K9rCbtxtKxDnaY3CGGxChCnMiW6B2kc0afK9
|
||||
vrrdtH9swg81NVcYYRkZXuf+yp7At/R4H02JDg==
|
||||
|
||||
`pragma protect data_method = "AES128-CBC"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 25408)
|
||||
`pragma protect data_block
|
||||
j5lM+obhUeYD9ScWi2nBqzaCP72D/TnZHiIUsZq82epcPsAS/ZzWkV5fqVq0r8jvxHcWqBHOznKb
|
||||
5mQWwH4vcrGpSLjIemnHV2y+fAnF2p2fMVdo5ymqCRiBlyYqr4JYh5bHNkersN3nbBt4YSEx3PWJ
|
||||
xyxtmZKqfv4SahggRAOx36TaeGnmt2U8s0CVi0MFu1RH5SfOan65G+m6tcop6V+x96D94mZQyvxn
|
||||
EASls37tyr9i0qu9MNfqHzFL4qQ5wStFD+nwsaqq5xZ7LUGPjwcuqhFvVCcPFMs21Uq+pRNF0UPX
|
||||
m8+phfWzga4DywgpNVXhqW2zqUaHkRDaaesyN47w0nboVHCPgbKCYKc7cue2MeEkX/J/pZqn5Rha
|
||||
WLPbC+WEWWQiVydf4EHWtKHi+Z/IQxBrBR6Bnjq8fKE2NMoNA03KsAq4ZRqmNpTm9DT1CtVNyogv
|
||||
g5jC/7xr0TMYCkepPl0vXt7V38kDah5K24enZtTWrWmhoZmfpnt4qo3rRjcYkXQltAzJ3EUWm2aX
|
||||
IgjxSEg3EhT/lCUw/78PABzVYO29UEKs1LrGWBHieTLmIBmSbvoQvl1otelQJywyseSG1naUT3g0
|
||||
gTQE7SS3exo1wRdCNLnpaLGB7IXnC6mDqpu+mxz/AEVT86rLVC3Td2+i/S4lRz5UxlvlKvLmhTQe
|
||||
dAAiy5nAG8N4Uc/aIJnG4o1ujOf5Il5KEJEpG247rXZFJ8XJzh5F3Xr/tuIAWgHBxHXi/OP6GzMs
|
||||
C+zTsKDo7W8Yqaiv28OkUrXdyW/KffzvBG7dKWM7+3386OoZwG698gqfQUsSOd8BDaw5nwAV7eNg
|
||||
Fz2lFr9kMvRFJeIjcT3y0dS1ti8kopd20cDEXK55r8nRsCqwWKy6HTyqLtxk5mchndiei/VRDV/d
|
||||
8FCrJ4xvuZjiqJPykLeOQUBmep7uFRaf9G1dHpiStCQmVWqyuQGPojy2iULtZ1mfB7zPNr1ZNZuj
|
||||
5DGRWicXjl8lAu/xVExpNIceeeG2sJGox0L8Whpv+ctvFaveEnFS2ZMUHKyv/mieAa0ZH2bHAz2e
|
||||
u/UxJ8x3fwQGDEXgVscXydpfJScHBkigXUCNsFkLoOMdETMG/ll/VycJobMNdQJRGqWaOAVC0avL
|
||||
FdOhNZ36rHqAYfJJzc0+ITTWP7h1NL/IYNU8AMlialo+N+Z/egMUBOjGWMZhbqh0ByCQkXr1f0zD
|
||||
SjtA1UZkyhdZdhhOmWXXfdRLS5eQyAMOKkqssbJw0Pn0BFKRyqyP0Xni1kahqaNVPAJNaIqLz2Uw
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
BMxf+9X87LiDOX52pl1XbQk0TeGhANcRVB9RWdPMu84HbZ83vOD6aHpWITlb1d1jn0kPJDLnTqsY
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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||||
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|
||||
/RzOVCDPCXHavwZGd7DnBiLM1NsWSl2kWoesWfx/tmAze9zqMGzUoKAZUMQsZz+g8vBcv9UAz6jM
|
||||
GQVuQ3BX9TXLnArCm4poQIGyfoyqnpzOIJq70AKib9MEadBP5TUHmItf2wa4dLH1wkeHZD7EiChz
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||||
6p5BBtKCwnSEpI+uATaq6tz9O9Mn+uUK/H9QZTj2ByfEkRqIxmIpZyR7KVD5JEGW02c/Pevt5eAg
|
||||
fBrUHGkvdYLGD31HjIZBCZVPeAaDYUmHxI0AsSoM3VMhc+PrUmaOaltNx4T3PpG/SPbmzxNEMxsi
|
||||
uhnokEh+rQbWLa2ZYnjO5+jfBJeEJpRenZfulV0k9klHGL/YCkqfyN0Ui4fcBAPwfm70Uz5va9D4
|
||||
ZxqAT8MHCo45LdQ8uIiDmSB1wNjioLAoRL+a3eB71ncI40oPl2ghMDIzXvjKa0lJw4+1uKbblfvu
|
||||
7wP61uYmyoZTcK+jdu5WvHR/Hc6d07bAfsFD41QJlHKEqj9ErBcEx3Qu4JuLXJvIB351VoOm2IZ/
|
||||
TKfANQERfKBXvJKA6NIE46WuWhAS/MKyebwU9+zaR4mPFi5pEPqzuG55Vw1y4fqwecuLSz8ak23s
|
||||
2f9kROyV1FAFNr9VRDJo3zQ0LiS2aJVxb9Ct6SjWT0ZB2heWOyj6IH1H+cf9uqu0YrqrV1xqc3Il
|
||||
SNaL2o9AZBFSUqTXwCp408jxDp8dKWPUiOuuLRVdMHyyiGA/C3Oy8QHC7ZGK8o5A4yho4htL4UdT
|
||||
WNlc/EUHYCNWfHlVrdfPayiXZ3fNRluAeUQvIgXf3aM76NbF/7n3XpQ6X2lrZ4PKtxd0T8xTMqyd
|
||||
309Gy5oq9EM12AvK+Vq+Sw8UITuTZ5H+ttjJqOtZSkRhCuOVGD5XOge/ekMknicyFt55BmZV4g7K
|
||||
WlvzpaMsiZv3M8C72DQWsQO7EsChjdGtOEqC4MLukynJC5x6HHvICe35mNO0NKSAQ6cxK2434sgW
|
||||
LCZJxhY/qJVPxKpHPLrKO6AKoxlxgpJQLr2G4pcuYAlsb+CCqD9uk9t+Mlnhbev5+oUahJ2RUmt0
|
||||
A3h72ldJA7jRXRGUBNSyHFilL+YJxg8jGLOuWJZcEqJxsiMfys2kXBkeGX/Z6YNBEnlYzmWM7Pxj
|
||||
VknH8YC204syrZifQ3hp2e1NRpfoR7rByKkz1DCaP32zw6rO5UYzj2LAbKgzqJDo7xQuscdd/f6L
|
||||
/tscRKzjcI1PGId5biYk7mY+AYe2N0OTQxfQ3oT2IXwIucRh20CT66gjyqmIZQRR0dNqS1M7kR/M
|
||||
lpkIwpxA2PDIKnABfJ1ymAatt5F9vAdX4pZk+LUzA9O7rrrFE8jryo3VkgedcXvFaIm1HgJgSLoe
|
||||
A/24kp+iCCZfr999NauiZXJkbGDwoP1by5HlWJhPlKdlcqXUUpFz5SmEX40cIEOzTTLhUJ5RQjpd
|
||||
hYgCg0keOSTAk0MWiAjoiiKw8PrSQCB/jwpq8KQsTs0XaPc5e1HD8gxeLOAyqKqgorGLfc+hHMU6
|
||||
/+VB1M3NxQPnNQDe5HEGS4GsM8/HTNgaGPZxBUSCxKeZY7wqJCkOpeSPvm11LIo8NskgY+lXzeBv
|
||||
/on3GCfSO0BgqGXZj3tX30HmBE83pWaN+w5O7zPztzOUknfCmTRsW9fTH2xD0deHR+1bjy/ziPA8
|
||||
LWfsHqz/Ds4stD+NR3Dw/Gos0Q5/mRHP4EtkEuqu1lprI4U6VNYKdUw4mGJjh4lGNND3wepHgap3
|
||||
2Snb1l7hcSUgJ91PBF4tj8e4IAqqmvgR+GS4KSiTwTNQr6O5oIXmiKwNChKTiDr4Gb0LberDmkeK
|
||||
tVG9FQCSOioMF7/RmXFYUB/lOrY7Om9qYag+Z0LOBOXmIyrbnN4rO/Vel8jbNqxqem8uYIzZIZ3o
|
||||
ezOp5gvg2C9LFw6GD1UR5AY8IyrZFpQm31AsjSc37NCZQ7/Zg/sY6LVAnd6qVAM3vbBB7bTzQ/5w
|
||||
g46P3RB25u9p1dp9O17m5/1IYRdoYp2Mj5tdDUrzD6FuqoOSQhCBoOS/j6R92mlvLBRuM9WFYfJA
|
||||
HpHfi1pgJcWBUjisDuuPQlHpb5M8lL11grxtu8QK03Pg4aL9LktiKoW0FQ==
|
||||
`pragma protect end_protected
|
||||
+31388
File diff suppressed because it is too large
Load Diff
+193099
File diff suppressed because it is too large
Load Diff
+5433
File diff suppressed because it is too large
Load Diff
+8447
File diff suppressed because it is too large
Load Diff
+1078
File diff suppressed because it is too large
Load Diff
+157
@@ -0,0 +1,157 @@
|
||||
// (c) Copyright 2023 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
////////////////////////////////////////////////////////////
|
||||
/*******************************************************************************
|
||||
|
||||
*Device: All
|
||||
*Purpose:
|
||||
* Verilog functions required by ila_lib
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
function integer size_of_data;
|
||||
input integer num_match_units;
|
||||
input [`GC_TRIG_WIDTH_VEC_ARRAY_W-1:0] match_width_string;
|
||||
input [`GC_TRIG_TYPEID_VEC_ARRAY_W-1:0] match_tpid_string;
|
||||
integer i;
|
||||
begin
|
||||
size_of_data = match_width_string[0+:16]+1;
|
||||
for (i=1; i<num_match_units; i=i+1)
|
||||
begin
|
||||
if (match_tpid_string[(16*(i))+:16] > match_tpid_string[(16*(i-1))+:16])
|
||||
size_of_data = size_of_data + match_width_string[(match_tpid_string[(i*`GC_TRIG_TYPEID_VEC_W)+:16]*16)+:16]+1;
|
||||
end
|
||||
end
|
||||
|
||||
endfunction
|
||||
|
||||
function integer match_units_count;
|
||||
input integer num_probes;
|
||||
input [`GC_MU_CNT_VEC_ARRAY_W-1:0] match_cnt_string;
|
||||
integer i;
|
||||
begin
|
||||
match_units_count = match_cnt_string[0+:4]+1;
|
||||
for (i=1; i<num_probes; i=i+1)
|
||||
begin
|
||||
match_units_count = match_units_count + match_cnt_string[(4*i)+:4]+1;
|
||||
end
|
||||
end
|
||||
endfunction
|
||||
|
||||
function [255:0] match_tpid;
|
||||
// Cast as bit16. Replace with null_value if not qualified.
|
||||
input [15:0] arg_ddr;
|
||||
input [15:0] arg;
|
||||
input qual;
|
||||
input [15:0] val;
|
||||
integer i;
|
||||
integer j;
|
||||
integer arg_temp;
|
||||
begin
|
||||
arg_temp = qual ? arg_ddr : arg;
|
||||
|
||||
for (i=0; i<arg_temp; i=i+1)
|
||||
begin
|
||||
match_tpid[i*16+:16] = val[15:0];
|
||||
end
|
||||
for (j=arg_temp; j<16; j=j+1)
|
||||
begin
|
||||
match_tpid[j*16+:16] = 16'h0000;
|
||||
end
|
||||
end
|
||||
endfunction
|
||||
|
||||
function integer match_units_count_en;
|
||||
input integer num_mu;
|
||||
input [1023:0] is_string;
|
||||
integer i;
|
||||
begin
|
||||
//match_units_count = match_cnt_string[0+:2]+1;
|
||||
match_units_count_en = 0;
|
||||
for (i=0; i<num_mu; i=i+1)
|
||||
begin
|
||||
if (is_string[i] == 1'b1) begin
|
||||
match_units_count_en = match_units_count_en + 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
endfunction
|
||||
|
||||
function integer size_of_data_less;
|
||||
input integer num_match_units;
|
||||
input [`GC_TRIG_WIDTH_VEC_ARRAY_W-1:0] match_width_string;
|
||||
input [`GC_TRIG_TYPEID_VEC_ARRAY_W-1:0] match_tpid_string;
|
||||
input [1023:0] is_string;
|
||||
integer i;
|
||||
begin
|
||||
if (is_string[0] == 1'b1) begin
|
||||
size_of_data_less = match_width_string[0+:16]+1;
|
||||
end else begin
|
||||
size_of_data_less = 0 ;
|
||||
end
|
||||
for (i=1; i<num_match_units; i=i+1)
|
||||
begin
|
||||
if (is_string[i] == 1'b1) begin
|
||||
size_of_data_less = size_of_data_less + match_width_string[i*16+:16]+1;
|
||||
end
|
||||
end
|
||||
end
|
||||
endfunction
|
||||
|
||||
function integer size_of_data_full;
|
||||
input integer num_match_units;
|
||||
input [`GC_TRIG_WIDTH_VEC_ARRAY_W-1:0] match_width_string;
|
||||
input [`GC_TRIG_TYPEID_VEC_ARRAY_W-1:0] match_tpid_string;
|
||||
input [1023:0] is_string;
|
||||
integer i;
|
||||
begin
|
||||
size_of_data_full = match_width_string[0+:16]+1;
|
||||
for (i=1; i<num_match_units; i=i+1)
|
||||
begin
|
||||
size_of_data_full = size_of_data_full + match_width_string[i*16+:16]+1;
|
||||
end
|
||||
end
|
||||
endfunction
|
||||
|
||||
+8443
File diff suppressed because it is too large
Load Diff
+3181
File diff suppressed because it is too large
Load Diff
+155
@@ -0,0 +1,155 @@
|
||||
// (c) Copyright 2023 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
////////////////////////////////////////////////////////////
|
||||
/*******************************************************************************
|
||||
|
||||
*Device: All
|
||||
*Purpose:
|
||||
* ILA constant values library
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
//--
|
||||
//-- ILA Pro command types:
|
||||
//--
|
||||
//-- These command values match those found in the documentation. The
|
||||
//-- CONTROL bus bit offset can be derived by adding CONTROL_OFFSET to
|
||||
//-- these values.
|
||||
//--
|
||||
`define READ_STATIC_STAT_CMD 0
|
||||
`define READ_DYNAMIC_STAT_CMD 1
|
||||
`define READ_DATA_CMD 2
|
||||
`define READ_TSTAMP_CMD 3
|
||||
`define WRITE_TRIG_SETUP_CMD 4
|
||||
`define WRITE_CAP_CTRL_SETUP_CMD 5
|
||||
`define WRITE_ENABLE_EXTCAP_CMD 6
|
||||
`define WRITE_DISABLE_EXTCAP_CMD 7
|
||||
`define WRITE_ARM_CMD 8
|
||||
`define WRITE_HALT_CMD 9
|
||||
`define WRITE_RESET_CMD 10
|
||||
`define WRITE_RESET_DCM_CMD 11
|
||||
`define RESERVED_0C_CMD 12
|
||||
`define RESERVED_0D_CMD 13
|
||||
`define RESERVED_0E_CMD 14
|
||||
`define WRITE_TSEQ_TRIGOUT 15
|
||||
`define WRITE_M0_SETUP_CMD 16
|
||||
`define WRITE_M1_SETUP_CMD 17
|
||||
`define WRITE_M2_SETUP_CMD 18
|
||||
`define WRITE_M3_SETUP_CMD 19
|
||||
`define WRITE_M4_SETUP_CMD 20
|
||||
`define WRITE_M5_SETUP_CMD 21
|
||||
`define WRITE_M6_SETUP_CMD 22
|
||||
`define WRITE_M7_SETUP_CMD 23
|
||||
`define WRITE_M8_SETUP_CMD 24
|
||||
`define WRITE_M9_SETUP_CMD 25
|
||||
`define WRITE_M10_SETUP_CMD 26
|
||||
`define WRITE_M11_SETUP_CMD 27
|
||||
`define WRITE_M12_SETUP_CMD 28
|
||||
`define WRITE_M13_SETUP_CMD 29
|
||||
`define WRITE_M14_SETUP_CMD 30
|
||||
`define WRITE_M15_SETUP_CMD 31
|
||||
|
||||
`define CONTROL_CMD_OFFSET 3
|
||||
|
||||
`define CFG_CLK_BIT 0
|
||||
`define CFG_DIN_BIT 1
|
||||
`define UNUSED_BIT 2
|
||||
`define CFG_DOUT_BIT 3
|
||||
`define READ_STATIC_STAT_CMD_BIT `READ_STATIC_STAT_CMD + `CONTROL_CMD_OFFSET
|
||||
`define READ_DYNAMIC_STAT_CMD_BIT `READ_DYNAMIC_STAT_CMD + `CONTROL_CMD_OFFSET
|
||||
`define READ_DATA_CMD_BIT `READ_DATA_CMD + `CONTROL_CMD_OFFSET
|
||||
`define READ_TSTAMP_CMD_BIT `READ_TSTAMP_CMD + `CONTROL_CMD_OFFSET
|
||||
`define WRITE_TRIG_SETUP_CMD_BIT `WRITE_TRIG_SETUP_CMD + `CONTROL_CMD_OFFSET
|
||||
`define WRITE_CAP_CTRL_SETUP_CMD_BIT `WRITE_CAP_CTRL_SETUP_CMD + `CONTROL_CMD_OFFSET
|
||||
`define WRITE_ENABLE_EXTCAP_CMD_BIT `WRITE_ENABLE_EXTCAP_CMD + `CONTROL_CMD_OFFSET
|
||||
`define WRITE_DISABLE_EXTCAP_CMD_BIT `WRITE_DISABLE_EXTCAP_CMD + `CONTROL_CMD_OFFSET
|
||||
`define WRITE_ARM_CMD_BIT `WRITE_ARM_CMD + `CONTROL_CMD_OFFSET
|
||||
`define WRITE_HALT_CMD_BIT `WRITE_HALT_CMD + `CONTROL_CMD_OFFSET
|
||||
`define WRITE_RESET_CMD_BIT `WRITE_RESET_CMD + `CONTROL_CMD_OFFSET
|
||||
`define WRITE_RESET_DCM_CMD_BIT `WRITE_RESET_DCM_CMD + `CONTROL_CMD_OFFSET
|
||||
`define RESERVED_0C_CMD_BIT `RESERVED_0C_CMD + `CONTROL_CMD_OFFSET
|
||||
`define RESERVED_0D_CMD_BIT `RESERVED_0D_CMD + `CONTROL_CMD_OFFSET
|
||||
`define RESERVED_0E_CMD_BIT `RESERVED_0E_CMD + `CONTROL_CMD_OFFSET
|
||||
`define WRITE_TSEQ_TRIGOUT_BIT `WRITE_TSEQ_TRIGOUT + `CONTROL_CMD_OFFSET
|
||||
`define WRITE_M0_SETUP_CMD_BIT `WRITE_M0_SETUP_CMD + `CONTROL_CMD_OFFSET
|
||||
`define WRITE_M1_SETUP_CMD_BIT `WRITE_M1_SETUP_CMD + `CONTROL_CMD_OFFSET
|
||||
`define WRITE_M2_SETUP_CMD_BIT `WRITE_M2_SETUP_CMD + `CONTROL_CMD_OFFSET
|
||||
`define WRITE_M3_SETUP_CMD_BIT `WRITE_M3_SETUP_CMD + `CONTROL_CMD_OFFSET
|
||||
`define WRITE_M4_SETUP_CMD_BIT `WRITE_M4_SETUP_CMD + `CONTROL_CMD_OFFSET
|
||||
`define WRITE_M5_SETUP_CMD_BIT `WRITE_M5_SETUP_CMD + `CONTROL_CMD_OFFSET
|
||||
`define WRITE_M6_SETUP_CMD_BIT `WRITE_M6_SETUP_CMD + `CONTROL_CMD_OFFSET
|
||||
`define WRITE_M7_SETUP_CMD_BIT `WRITE_M7_SETUP_CMD + `CONTROL_CMD_OFFSET
|
||||
`define WRITE_M8_SETUP_CMD_BIT `WRITE_M8_SETUP_CMD + `CONTROL_CMD_OFFSET
|
||||
`define WRITE_M9_SETUP_CMD_BIT `WRITE_M9_SETUP_CMD + `CONTROL_CMD_OFFSET
|
||||
`define WRITE_M10_SETUP_CMD_BIT `WRITE_M10_SETUP_CMD + `CONTROL_CMD_OFFSET
|
||||
`define WRITE_M11_SETUP_CMD_BIT `WRITE_M11_SETUP_CMD + `CONTROL_CMD_OFFSET
|
||||
`define WRITE_M12_SETUP_CMD_BIT `WRITE_M12_SETUP_CMD + `CONTROL_CMD_OFFSET
|
||||
`define WRITE_M13_SETUP_CMD_BIT `WRITE_M13_SETUP_CMD + `CONTROL_CMD_OFFSET
|
||||
`define WRITE_M14_SETUP_CMD_BIT `WRITE_M14_SETUP_CMD + `CONTROL_CMD_OFFSET
|
||||
`define WRITE_M15_SETUP_CMD_BIT `WRITE_M15_SETUP_CMD + `CONTROL_CMD_OFFSET
|
||||
|
||||
//--
|
||||
//-- Delay of data due to trigger delay
|
||||
//--
|
||||
`define ILA_PRO_DATA_DELAY 9
|
||||
//--constant ILA_PRO_DATA_DELAY : integer := 8;
|
||||
|
||||
//-- Width of vector used to encode each Trigger Width value (see ila_core)
|
||||
`define GC_MAX_NUM_MU 1024
|
||||
`define GC_TRIG_WIDTH_VEC_W 16
|
||||
`define GC_TRIG_WIDTH_VEC_ARRAY_W `GC_TRIG_WIDTH_VEC_W*`GC_MAX_NUM_MU
|
||||
`define GC_TRIG_TYPEID_VEC_W 16
|
||||
`define GC_TRIG_TYPEID_VEC_ARRAY_W `GC_TRIG_TYPEID_VEC_W*`GC_MAX_NUM_MU
|
||||
`define GC_MU_CNT_VEC_W 4
|
||||
`define GC_MU_CNT_VEC_ARRAY_W `GC_MU_CNT_VEC_W*`GC_MAX_NUM_MU
|
||||
|
||||
//-- Width of vector used to encode each Trigger Width value (see ila_core)
|
||||
`define GC_TRIG_TYPE_ID_W 15
|
||||
|
||||
|
||||
//-- Static Status Width
|
||||
`define GC_STATIC_STAT_W 672
|
||||
|
||||
|
||||
+1263
File diff suppressed because it is too large
Load Diff
+1140
File diff suppressed because it is too large
Load Diff
+247
@@ -0,0 +1,247 @@
|
||||
`pragma protect begin_protected
|
||||
`pragma protect version = 1
|
||||
`pragma protect encrypt_agent = "XILINX"
|
||||
`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2024.1"
|
||||
`pragma protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-2", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
|
||||
`pragma protect key_block
|
||||
aHbVSd437vBI2R10TkKRNxXGmnmkohUBn37NorC3CUImIgV2uSaj7ibcKLMgKm1rBGbQ3pT+qc3E
|
||||
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|
||||
HrDWRfdwHieeL4NKSOw=
|
||||
|
||||
`pragma protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
UB6rHHOO6x9R2wShvvNToNu++GWqdVKB76ATBT7LTDHqURc32TFkpbx/11jCpFZX7OoFR+K8AF+s
|
||||
XokYrCWAYQarBbldISlVV165+Q/Ajggs4R+MUq1dtiaXim6cyqiExcJuMtJCyVqb/bCEMSZYk9Nj
|
||||
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|
||||
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|
||||
2f73gBNrkqJl/TwI8KEPAcicXcDQt2V4MhZ5Aw==
|
||||
|
||||
`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VELOCE-RSA", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
|
||||
`pragma protect key_block
|
||||
OsjY8cixXA9vzd/3IHJ5zfNllZ7VntlBnceX2u/JM7Do9N5jvXs2+UYiCaJBuJA9lvpKgMq1d+pP
|
||||
7Oq/5Ex4ynvtl6BtrMWA9NviQA4IQKcPQ0eb2j5QeUERYtlGgDhQImKRwJzlUr4fYisH8SxoFx2X
|
||||
5qfGWHwJEAWSl9R3cbs=
|
||||
|
||||
`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-2", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
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|
||||
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|
||||
CjlpZZWmaNlG7VSM4Wes1kz/7dh3aJTsK+/zScl8bvQ7jDqGkg2PEapBlCfgbe9c186lQcUBds5D
|
||||
d9O/yqGdkIL8QdLuFkPkO3UIKZTfYX9Ok28SnynHcbex3LYe33wkeXUMHJfCXFAE5L6eWx5OJxzK
|
||||
VRqHCcAx96sXDVTabxCS2Zj3uf0q6tsUxtH/JA==
|
||||
|
||||
`pragma protect key_keyowner = "Real Intent", key_keyname = "RI-RSA-KEY-1", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
NXRsKSvTYFqKkKYaYbHCcxD/llk+qd/2lr8gX8E+3YHjElpCOZdhOgVmIQ5GrHEOIjAwkrbXr4x+
|
||||
tVGXdWJ7191O6Ymu8N+DSnn7tExLr5ctpPouvp/WLRURSZ3Drwqacqcup6S+SL6FVVB1aUa7Fa+3
|
||||
8VeJu5SIIF9kPxkP+mrLj0sf3QfV6YvL2mFyarJyJHG6INHh1Vm+JCiog8/CaE67TwjgSz6RZwhe
|
||||
Vd/1YFi7iKQSF3qOAq0XYXRYNEc+Zo17LUDYeBRjZo5zP7IRcLhiFPqvscSqGJQdHk+0CUFdv4H9
|
||||
x8K04kbxzGEz1UTo7xH3D4Bcz07/7LXIwXGOiw==
|
||||
|
||||
`pragma protect key_keyowner = "Metrics Technologies Inc.", key_keyname = "DSim", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
WggZ6nWWRYaiygfYqfFf0uDuskgnsClNlFQMsvCrJLTk6kzscNvfDew9lJvZKeG86PAoZf6x6DNr
|
||||
rF82XBea46E/BRWe/upsaIrBsyNnmKbNldOGa5GNW96LDCnvfjRxfrXK6LZ8kfTqdN1sQEgFApHk
|
||||
Z3KrywM6C8yIlLtbvDwykIzVTFvBh4EWr1oq1Nbp/APcMW2SDB3WhP6eJIeGs2h2s+UROFRcL90p
|
||||
F4Cr4YkHDnYE26SBDrk+1SYYKoh09yy9U7tIPTf4pTsGMCKNFEUSVB8QR+iT52mnUddOpTjM7TJy
|
||||
+54v2ouxLyMDz4Mmw6sgOWjEIjwnpTyXcWzVZw==
|
||||
|
||||
`pragma protect key_keyowner = "Xilinx", key_keyname = "xilinxt_2023_11", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
W3Q2Mqi1yhba4oPIiXk4hA2yrKc0DbYbHg9OwQBCTnmD4dTMysnUHsrDMn4GRvAjwuB2Dif8hMqw
|
||||
PDdp2rEPt/h5JeMPnIXHx9p8B8R+VaU0zIVX7EZX5eZfbX++mwXb3AUXOYBJDRuq8gdh5MP8JbpK
|
||||
4f8W1AySrdPJSdvMckjXq3EiJ8rjXAKZaZcJ4XtCGwpD6dlNRue3a/dmk26H2xD46CwudGYPAuOZ
|
||||
JBy/dD7aBAiOd6CpDkU7ZUrpTqzgo6GP2bVwV+0pbr1zxRXACp4HlFbmXcQLH4PvP/QaMgUZ3urp
|
||||
6TRmDhayoUmYNh0t+WCfdLQl8PQ4MjEzxryCzg==
|
||||
|
||||
`pragma protect key_keyowner = "Atrenta", key_keyname = "ATR-SG-RSA-1", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 384)
|
||||
`pragma protect key_block
|
||||
H0IIoenK18u2x/coBRgUTxAZ2BoMw6jQkWq51R1HtrOZIKMhtY4/lLHE/+qfuAiQpyofYOrWH8o8
|
||||
zGxKgx3uXfoB+7tLJ8qF0p818ENRx5IYa7qbIQLjCJJNuK5gzngJ/e+Js4U5zPra6z9cb6hlJ2eM
|
||||
dDPjgnZXkwXke0caPO9O2AeDPG3z1u2hBYShm8XWfX/WVr9fk8QP1b52VaSBkck+Hk/8XSQ76FIs
|
||||
30oETt5iIHQxnxLI7ZH2yXny9C6jjp2PtaSqX69vaj6C/n2lu8JZLbq/XfDTC2zQTsxD22MqlPmM
|
||||
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|
||||
hQhTfa5K0+fokRQ8mwIrIMqKky2HE1+jKJo614OM8WFbavmxOuywggzBF4EBJjQGjgANL3MNPOaD
|
||||
cKjEOW8sUkVoJ0qE8dxoi/28QFTEz+um8h/4FOP39W3QEPtkR19Cv/+g
|
||||
|
||||
`pragma protect key_keyowner = "Cadence Design Systems.", key_keyname = "CDS_RSA_KEY_VER_1", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
ATi6NbbTT7JV6BGzHOZiAakxl24D+jNnguXdivYcZJsoUxdwO5YuvbX866KlESum+dZFuRJ1KPGF
|
||||
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|
||||
SbYC1DHC2cR5Bu2QvtVIqYk/QxWMMO+vooIUcjjfVRUUYGXSGAL2ayqbJd9gBCbFc79XIRsJ+Gmi
|
||||
IQ+pqql6EHeAazyOEAzxO/tbFbfukruGaeRF/MUZ/qFnl97XNrtWvJtBIBn4mwpMkOSD3n2dCJIw
|
||||
wr8TjozuJ8tjwuFKqNJxG1lkhIaGPtEpES8idg==
|
||||
|
||||
`pragma protect data_method = "AES128-CBC"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 9104)
|
||||
`pragma protect data_block
|
||||
M/BFSjD9Uqa4x2ltskM+cx3DNAD+Ymwqkmji2sc24dN0PYw272QIKn9NAmf6eHmBth35P9BvoRLS
|
||||
2i9u3yitB4kDETymCN/lf7uIpiAPTKOwSfPhVMcM6C/n714lAZ/t6w0tmVHitLr6CmsukhsUDDi6
|
||||
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|
||||
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|
||||
blv7gzK1HtLzZvK9W8j0q+hM3b8cWO/pSyg7gF7EVbeevIYKyxeYmle7LTL7WbzRuEvYDAKR/vOn
|
||||
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|
||||
ty/Dgsx/3yr9i//q+DNy+JmD+UMY+wzr75TpXqX/EiFYKKFvrdA9VVS4q460p6eYNztDMSiHjAV6
|
||||
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|
||||
du0jXkaHnIZb/1zjaBhg96rN79LJT+EnScu9GdinNcntL5MZ6Gc6MnOSvlzcX7O48/lpGdFt7R8T
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
AQYhrMIIz5K/VY3M1e4xdfdbQ9NXgX8GknRknD1mxHw0JA08HC2ZidIuhe9lnZyBssRY38E/eKgb
|
||||
P7/lSSm4C/Sen+U8J2mKnD9gFspEAJxIEp2uig44liraH9adyNlGu9SI5iikKB5tJbSC9RK/9cwv
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
/Bx6A770YhJiRfkF6598IaHuKIB0smjOejkK6t+yaJTqelKo+Y3y9A4ERPyP2Va+EVsOSN9s0vpb
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
ZRBrhB0zzgWpTVsT6y8UXhD7WBefekpxJoES30j1xV5+aVR9oLQobQYHRgPlAoFCbdoGvkHXMmFU
|
||||
SgT4Os4WLhomhVQmcSzpy7QYhtFfLH48EdV2hHPvjiLcvNKv9pgx2c/nZdUuq33vjRhF4Tz8KHz0
|
||||
gmt6Sg5RqpVXx7cGn5yQCejlLfYYldc/ZnSST0j70+76whN5r55djGkLjtjlFfWavseSpE30YpuN
|
||||
CzGM5EEDNpOD4oPZu+QtKqpc3vI1xO/euhbWVkkhZ93iv490TX5aC8S7G3/TLm5DmetVyFr8qirK
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||||
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`pragma protect end_protected
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||||
+1653
File diff suppressed because it is too large
Load Diff
+1086
File diff suppressed because it is too large
Load Diff
+287
@@ -0,0 +1,287 @@
|
||||
`pragma protect begin_protected
|
||||
`pragma protect version = 1
|
||||
`pragma protect encrypt_agent = "XILINX"
|
||||
`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2024.1"
|
||||
`pragma protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-2", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
|
||||
`pragma protect key_block
|
||||
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||||
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|
||||
5ksxZI/Aupdkv5bFTBU=
|
||||
|
||||
`pragma protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
|
||||
`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VELOCE-RSA", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
|
||||
`pragma protect key_block
|
||||
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||||
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|
||||
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|
||||
|
||||
`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-2", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
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||||
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|
||||
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|
||||
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|
||||
o0JbfR5OJwyttzPSNGkeOs6PXNSdOiSXaHCXCg==
|
||||
|
||||
`pragma protect key_keyowner = "Real Intent", key_keyname = "RI-RSA-KEY-1", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
|
||||
`pragma protect key_keyowner = "Metrics Technologies Inc.", key_keyname = "DSim", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
|
||||
`pragma protect key_keyowner = "Xilinx", key_keyname = "xilinxt_2023_11", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
|
||||
`pragma protect key_keyowner = "Atrenta", key_keyname = "ATR-SG-RSA-1", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 384)
|
||||
`pragma protect key_block
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
|
||||
`pragma protect key_keyowner = "Cadence Design Systems.", key_keyname = "CDS_RSA_KEY_VER_1", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
|
||||
`pragma protect data_method = "AES128-CBC"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 11376)
|
||||
`pragma protect data_block
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
`pragma protect end_protected
|
||||
+370
@@ -0,0 +1,370 @@
|
||||
`pragma protect begin_protected
|
||||
`pragma protect version = 1
|
||||
`pragma protect encrypt_agent = "XILINX"
|
||||
`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2024.1"
|
||||
`pragma protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-2", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
|
||||
`pragma protect key_block
|
||||
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|
||||
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|
||||
r3vLYxeoZnq6gVRlGok=
|
||||
|
||||
`pragma protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
m3Q41M/VvWRABK8HvC3+A087vRuuruP6wy6uBg==
|
||||
|
||||
`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VELOCE-RSA", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
|
||||
`pragma protect key_block
|
||||
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|
||||
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|
||||
ClWSfzRY4gUVS90efQ4=
|
||||
|
||||
`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-2", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
l/x1Wq23CMUf8oQ6GNTuG7ZN7wUQKR6iymdBFg==
|
||||
|
||||
`pragma protect key_keyowner = "Real Intent", key_keyname = "RI-RSA-KEY-1", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
U599+67z3hzf1CYha/2gf7y+QjvdzYLMbbtP9w==
|
||||
|
||||
`pragma protect key_keyowner = "Metrics Technologies Inc.", key_keyname = "DSim", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
TkHTaYu5Ene4hMQxVFsaWjS65nyIzGmX9kUomA==
|
||||
|
||||
`pragma protect key_keyowner = "Xilinx", key_keyname = "xilinxt_2023_11", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
yG/3u/8LN3MlTQH9jNGKaJof0SRWlse+37wsUA==
|
||||
|
||||
`pragma protect key_keyowner = "Atrenta", key_keyname = "ATR-SG-RSA-1", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 384)
|
||||
`pragma protect key_block
|
||||
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|
||||
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|
||||
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|
||||
chovw0I+BaCFeRnbcJgPi7Wr+pKgwlRkRgehmjWXYuNUUBM0hEzTzitXtUkir9vdHhjLO5pQaD0D
|
||||
OJf+aqEVVkq7Anys6HhPui7kluvLIzQe6dQvvsrDwB/cu5YLKvMxTAWzz+FX40SEhyQdFU0hYLT/
|
||||
lt6wpw4ltikOAaoy7C1vUrfZqzhbhkc7L1uuztXOlBj704pFhGGDv7IDQF3Ls2HPIMNUTE37Dd46
|
||||
zXp4x0dzAmJAA4HSgrkgK7ldWJiexPDUGXa4drx0AbBvEJV4NZ8M6Let
|
||||
|
||||
`pragma protect key_keyowner = "Cadence Design Systems.", key_keyname = "CDS_RSA_KEY_VER_1", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
WVOLA1immgWndGRhqlG2r1joEP+9QHH9V9X6ukav5u4xe/VtcklWA0nJCqXpJVK6YV4gPbhVPeTa
|
||||
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|
||||
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|
||||
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|
||||
wLV25+Xs0rAuakLfEICo5MXpdXlXmggLOTET/g==
|
||||
|
||||
`pragma protect data_method = "AES128-CBC"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 16096)
|
||||
`pragma protect data_block
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
KeF7pwPdJVfV7Q061lT5G0X0sN8NPw==
|
||||
`pragma protect end_protected
|
||||
+1238
File diff suppressed because it is too large
Load Diff
+105
@@ -0,0 +1,105 @@
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* Copyright (c) 2011 AMD, Inc.
|
||||
* This design is confidential and proprietary of AMD, All Rights Reserved.
|
||||
*-----------------------------------------------------------------------------
|
||||
* ____ ____
|
||||
* / /\/ /
|
||||
* /___/ \ / Vendor: AMD
|
||||
* \ \ \/ Date Created: 2011/04/26
|
||||
* \ \
|
||||
* / /
|
||||
* /___/ /\
|
||||
* \ \ / \
|
||||
* \___\/\___\
|
||||
*
|
||||
*Device: All
|
||||
*Purpose:
|
||||
* General functions used by other Labtools IP cores. Functions will
|
||||
* be added as needed.
|
||||
*
|
||||
*Notes:
|
||||
* Include the file inside the Verilog module after the module and port
|
||||
* section. Do not include at the top of the module.
|
||||
*
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
`include "ltlib_v1_0_2_ver.vh"
|
||||
|
||||
function integer clogb2;
|
||||
input integer depth;
|
||||
integer d;
|
||||
begin
|
||||
if (depth == 0)
|
||||
clogb2 = 1;
|
||||
else
|
||||
begin
|
||||
d = depth;
|
||||
for (clogb2=0; d > 0; clogb2 = clogb2+1)
|
||||
d = d >> 1;
|
||||
end
|
||||
end
|
||||
endfunction
|
||||
|
||||
function string_contains;
|
||||
input [`FAMILY_NAME_LENGTH*8-1:0] familyName;
|
||||
input [`FAMILY_NAME_LENGTH*8-1:0] expectedName;
|
||||
input integer expectedLength;
|
||||
integer i;
|
||||
integer j;
|
||||
reg temp_contain;
|
||||
begin
|
||||
string_contains = 1;
|
||||
temp_contain = 0;
|
||||
for (i=0; i<`FAMILY_NAME_LENGTH; i=i+1)
|
||||
begin
|
||||
if (familyName[(8*i)+:8] == expectedName[0+:8])
|
||||
begin
|
||||
temp_contain = 1;
|
||||
for (j=0; j<expectedLength; j=j+1)
|
||||
begin
|
||||
if (familyName[((8*i)+(8*j))+:8] != expectedName[(8*j)+:8])
|
||||
begin
|
||||
temp_contain = 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
if (temp_contain == 1)
|
||||
begin
|
||||
string_contains = 1;
|
||||
i = `FAMILY_NAME_LENGTH;
|
||||
end
|
||||
end
|
||||
endfunction
|
||||
|
||||
function integer supports_bscane2;
|
||||
input [`FAMILY_NAME_LENGTH-1:0] familyName;
|
||||
begin
|
||||
if (string_contains(familyName,`FAMILY_VIRTEX7,`FAMILY_VIRTEX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_KINTEX7,`FAMILY_KINTEX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_ARTIX7,`FAMILY_ARTIX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_ZYNQ,`FAMILY_ZYNQ_LENGTH) == 1)
|
||||
supports_bscane2 = 1;
|
||||
else
|
||||
supports_bscane2 = 0;
|
||||
end
|
||||
endfunction
|
||||
|
||||
function integer supports_series7_bufr;
|
||||
input [`FAMILY_NAME_LENGTH-1:0] familyName;
|
||||
begin
|
||||
if (string_contains(familyName,`FAMILY_VIRTEX7,`FAMILY_VIRTEX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_KINTEX7,`FAMILY_KINTEX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_ARTIX7,`FAMILY_ARTIX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_ZYNQ,`FAMILY_ZYNQ_LENGTH) == 1)
|
||||
supports_series7_bufr = 1;
|
||||
else
|
||||
supports_series7_bufr = 0;
|
||||
end
|
||||
endfunction
|
||||
|
||||
function integer supports_series7_startup;
|
||||
input [`FAMILY_NAME_LENGTH-1:0] familyName;
|
||||
begin
|
||||
if (string_contains(familyName,`FAMILY_VIRTEX7,`FAMILY_VIRTEX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_KINTEX7,`FAMILY_KINTEX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_ARTIX7,`FAMILY_ARTIX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_ZYNQ,`FAMILY_ZYNQ_LENGTH) == 1)
|
||||
supports_series7_startup = 1;
|
||||
else
|
||||
supports_series7_startup = 0;
|
||||
end
|
||||
endfunction
|
||||
|
||||
+107
@@ -0,0 +1,107 @@
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* Copyright (c) 2008 AMD, Inc.
|
||||
* This design is confidential and proprietary of AMD, All Rights Reserved.
|
||||
*-----------------------------------------------------------------------------
|
||||
* ____ ____
|
||||
* / /\/ /
|
||||
* /___/ \ / Vendor: AMD
|
||||
* \ \ \/ Date Created: 2008/08/18
|
||||
* \ \
|
||||
* / /
|
||||
* /___/ /\
|
||||
* \ \ / \
|
||||
* \___\/\___\
|
||||
*
|
||||
*Device: All
|
||||
*Purpose:
|
||||
* Define values for Verilog instatiation of labtools ip
|
||||
*
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
*-- C O N S T A N T S
|
||||
*-----------------------------------------------------------------------------*/
|
||||
|
||||
//
|
||||
// Core type (non-negative integers from 0 to 255)
|
||||
//
|
||||
`define RESERVED_MFG_ID 0
|
||||
`define XILINX_MFG_ID 1
|
||||
`define XILINX_AND_AGILENT_MFG_ID 2
|
||||
`define GC_XILINX_MFG_ID `XILINX_MFG_ID
|
||||
|
||||
//
|
||||
// Core type (non-negative integers from 0 to 255)
|
||||
//
|
||||
`define RESERVED_CORE_TYPE 0
|
||||
`define ICON_CORE_TYPE 1
|
||||
`define ILA_CORE_TYPE 2
|
||||
`define IBA_GENERIC_CORE_TYPE 3
|
||||
`define IBA_OPB_CORE_TYPE 4
|
||||
`define IBA_PLB_CORE_TYPE 5
|
||||
`define ILA_ATC_CORE_TYPE 6
|
||||
`define IBA_OPB_ATC_CORE_TYPE 7
|
||||
`define IBA_PLB_ATC_CORE_TYPE 8
|
||||
`define VIO_CORE_TYPE 9
|
||||
`define ATC2_CORE_TYPE 10
|
||||
`define ATC3_CORE_TYPE 11
|
||||
`define GC_RESERVED_CORE_TYPE2 12
|
||||
`define IBERT_CORE_TYPE 13
|
||||
`define GC_XSDB_MASTER_V1_0 14
|
||||
`define GC_ICON_NULL_CORE_TYPE 15
|
||||
|
||||
//
|
||||
// Width of the ChipScope Pro Core CONTROL port
|
||||
//
|
||||
`define CONTROL_WIDTH 36
|
||||
|
||||
// Match unit type
|
||||
`define MATCH_UNIT_TYPEA_ALLX 0
|
||||
//`define MATCH_UNIT_TYPE_GANDOR 2
|
||||
//`define MATCH_UNIT_TYPE_GANDORX 3
|
||||
|
||||
|
||||
|
||||
//
|
||||
// Device family constants
|
||||
//
|
||||
`define FAMILY_NAME_LENGTH 15 //leave room for radhard/automotive and low power part names
|
||||
`define FAMILY_VIRTEX7 "virtex7"
|
||||
`define FAMILY_VIRTEX7_LENGTH 7
|
||||
`define FAMILY_KINTEX7 "kintex7"
|
||||
`define FAMILY_KINTEX7_LENGTH 7
|
||||
`define FAMILY_ARTIX7 "artix7"
|
||||
`define FAMILY_ARTIX7_LENGTH 6
|
||||
`define FAMILY_ZYNQ "zynq"
|
||||
`define FAMILY_ZYNQ_LENGTH 4
|
||||
|
||||
//
|
||||
// Architecture match type constants, start at 100 so that code can't incorrectly mix up family and match unit type
|
||||
//
|
||||
`define ARCH_MATCH_TYPE_A 100
|
||||
|
||||
//
|
||||
// Device JTAG Stuff
|
||||
//
|
||||
`define GC_SBT_IR_W 10;
|
||||
`define GC_SBT_IR_ID_INSTR 10'b1111001001
|
||||
`define GC_SBT_IR_USER1_INSTR 10'b11_1100_0010
|
||||
`define GC_CHIP_ID_CHIPSCOPE_SBT 32'b0000_1010_0000_0000_0011_0000_1001_0011
|
||||
// 0a00_3093
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Virtex7
|
||||
//
|
||||
// IR Info
|
||||
`define GC_V7_IR_W 6
|
||||
`define GC_V7_IR_ID_INSTR 6'b00_1001
|
||||
`define GC_V7_IR_USER1_INSTR 6'b00_0010
|
||||
`define GC_V7_IR_USER2_INSTR 6'b00_0011
|
||||
`define GC_V7_IR_USER3_INSTR 6'b10_0010
|
||||
`define GC_V7_IR_USER4_INSTR 6'b10_0011
|
||||
// Chip IDs
|
||||
`define GC_CHIP_ID_XC7V285T 32'b0000_0011_1010_0110_0100_0000_1001_0011
|
||||
// 0424a093
|
||||
|
||||
|
||||
+638
@@ -0,0 +1,638 @@
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 3)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_2_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 4)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_2_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 5)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_2_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 6)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_2_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 7)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_2_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 8)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_2_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 9)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_2_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 10)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_2_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 11)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_2_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
assign bscanid_en_10 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 12)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_2_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
assign bscanid_en_10 = bscanid_en_int;
|
||||
assign bscanid_en_11 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 13)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_2_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_12,drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_12,capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_12,update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_12,shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_12,reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_12,sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_12,tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_12,tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_12,tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_12,tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_12,runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
assign bscanid_en_10 = bscanid_en_int;
|
||||
assign bscanid_en_11 = bscanid_en_int;
|
||||
assign bscanid_en_12 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 14)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_2_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_13,drck_12,drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_13,capture_12,capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_13,update_12,update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_13,shift_12,shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_13,reset_12,reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_13,sel_12,sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_13,tdi_12,tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_13,tdo_12,tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_13,tms_12,tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_13,tck_12,tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_13,runtest_12,runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
assign bscanid_en_10 = bscanid_en_int;
|
||||
assign bscanid_en_11 = bscanid_en_int;
|
||||
assign bscanid_en_12 = bscanid_en_int;
|
||||
assign bscanid_en_13 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 15)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_2_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_14,drck_13,drck_12,drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_14,capture_13,capture_12,capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_14,update_13,update_12,update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_14,shift_13,shift_12,shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_14,reset_13,reset_12,reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_14,sel_13,sel_12,sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_14,tdi_13,tdi_12,tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_14,tdo_13,tdo_12,tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_14,tms_13,tms_12,tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_14,tck_13,tck_12,tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_14,runtest_13,runtest_12,runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
assign bscanid_en_10 = bscanid_en_int;
|
||||
assign bscanid_en_11 = bscanid_en_int;
|
||||
assign bscanid_en_12 = bscanid_en_int;
|
||||
assign bscanid_en_13 = bscanid_en_int;
|
||||
assign bscanid_en_14 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 16)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_2_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_15,drck_14,drck_13,drck_12,drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_15,capture_14,capture_13,capture_12,capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_15,update_14,update_13,update_12,update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_15,shift_14,shift_13,shift_12,shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_15,reset_14,reset_13,reset_12,reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_15,sel_14,sel_13,sel_12,sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_15,tdi_14,tdi_13,tdi_12,tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_15,tdo_14,tdo_13,tdo_12,tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_15,tms_14,tms_13,tms_12,tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_15,tck_14,tck_13,tck_12,tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_15,runtest_14,runtest_13,runtest_12,runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
assign bscanid_en_10 = bscanid_en_int;
|
||||
assign bscanid_en_11 = bscanid_en_int;
|
||||
assign bscanid_en_12 = bscanid_en_int;
|
||||
assign bscanid_en_13 = bscanid_en_int;
|
||||
assign bscanid_en_14 = bscanid_en_int;
|
||||
assign bscanid_en_15 = bscanid_en_int;
|
||||
end
|
||||
|
||||
+638
@@ -0,0 +1,638 @@
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 3)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_2_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 4)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_2_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_3,tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 5)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_2_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 6)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_2_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 7)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_2_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 8)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_2_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 9)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_2_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 10)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_2_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 11)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_2_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
assign bscanid_en_10 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 12)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_2_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
assign bscanid_en_10 = bscanid_en_int;
|
||||
assign bscanid_en_11 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 13)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_2_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_12,drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_12,capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_12,update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_12,shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_12,reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_12,sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_12,tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_12,tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_12,tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_12,tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_12,runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
assign bscanid_en_10 = bscanid_en_int;
|
||||
assign bscanid_en_11 = bscanid_en_int;
|
||||
assign bscanid_en_12 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 14)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_2_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_13,drck_12,drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_13,capture_12,capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_13,update_12,update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_13,shift_12,shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_13,reset_12,reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_13,sel_12,sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_13,tdi_12,tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_13,tdo_12,tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_13,tms_12,tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_13,tck_12,tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_13,runtest_12,runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
assign bscanid_en_10 = bscanid_en_int;
|
||||
assign bscanid_en_11 = bscanid_en_int;
|
||||
assign bscanid_en_12 = bscanid_en_int;
|
||||
assign bscanid_en_13 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 15)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_2_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_14,drck_13,drck_12,drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_14,capture_13,capture_12,capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_14,update_13,update_12,update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_14,shift_13,shift_12,shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_14,reset_13,reset_12,reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_14,sel_13,sel_12,sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_14,tdi_13,tdi_12,tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_14,tdo_13,tdo_12,tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_14,tms_13,tms_12,tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_14,tck_13,tck_12,tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_14,runtest_13,runtest_12,runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
assign bscanid_en_10 = bscanid_en_int;
|
||||
assign bscanid_en_11 = bscanid_en_int;
|
||||
assign bscanid_en_12 = bscanid_en_int;
|
||||
assign bscanid_en_13 = bscanid_en_int;
|
||||
assign bscanid_en_14 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 16)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_2_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_15,drck_14,drck_13,drck_12,drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_15,capture_14,capture_13,capture_12,capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_15,update_14,update_13,update_12,update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_15,shift_14,shift_13,shift_12,shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_15,reset_14,reset_13,reset_12,reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_15,sel_14,sel_13,sel_12,sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_15,tdi_14,tdi_13,tdi_12,tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_15,tdo_14,tdo_13,tdo_12,tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_15,tms_14,tms_13,tms_12,tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_15,tck_14,tck_13,tck_12,tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_15,runtest_14,runtest_13,runtest_12,runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
assign bscanid_en_10 = bscanid_en_int;
|
||||
assign bscanid_en_11 = bscanid_en_int;
|
||||
assign bscanid_en_12 = bscanid_en_int;
|
||||
assign bscanid_en_13 = bscanid_en_int;
|
||||
assign bscanid_en_14 = bscanid_en_int;
|
||||
assign bscanid_en_15 = bscanid_en_int;
|
||||
end
|
||||
|
||||
+638
@@ -0,0 +1,638 @@
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 3)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_2_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 4)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_2_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_3,tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 5)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_2_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 6)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_2_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 7)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_2_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 8)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_2_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 9)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_2_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 10)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_2_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 11)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_2_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
assign bscanid_en_10 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 12)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_2_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
assign bscanid_en_10 = bscanid_en_int;
|
||||
assign bscanid_en_11 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 13)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_2_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_12,drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_12,capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_12,update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_12,shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_12,reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_12,sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_12,tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_12,tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_12,tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_12,tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_12,runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
assign bscanid_en_10 = bscanid_en_int;
|
||||
assign bscanid_en_11 = bscanid_en_int;
|
||||
assign bscanid_en_12 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 14)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_2_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_13,drck_12,drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_13,capture_12,capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_13,update_12,update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_13,shift_12,shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_13,reset_12,reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_13,sel_12,sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_13,tdi_12,tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_13,tdo_12,tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_13,tms_12,tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_13,tck_12,tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_13,runtest_12,runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
assign bscanid_en_10 = bscanid_en_int;
|
||||
assign bscanid_en_11 = bscanid_en_int;
|
||||
assign bscanid_en_12 = bscanid_en_int;
|
||||
assign bscanid_en_13 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 15)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_2_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_14,drck_13,drck_12,drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_14,capture_13,capture_12,capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_14,update_13,update_12,update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_14,shift_13,shift_12,shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_14,reset_13,reset_12,reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_14,sel_13,sel_12,sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_14,tdi_13,tdi_12,tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_14,tdo_13,tdo_12,tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_14,tms_13,tms_12,tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_14,tck_13,tck_12,tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_14,runtest_13,runtest_12,runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
assign bscanid_en_10 = bscanid_en_int;
|
||||
assign bscanid_en_11 = bscanid_en_int;
|
||||
assign bscanid_en_12 = bscanid_en_int;
|
||||
assign bscanid_en_13 = bscanid_en_int;
|
||||
assign bscanid_en_14 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 16)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_2_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_15,drck_14,drck_13,drck_12,drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_15,capture_14,capture_13,capture_12,capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_15,update_14,update_13,update_12,update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_15,shift_14,shift_13,shift_12,shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_15,reset_14,reset_13,reset_12,reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_15,sel_14,sel_13,sel_12,sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_15,tdi_14,tdi_13,tdi_12,tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_15,tdo_14,tdo_13,tdo_12,tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_15,tms_14,tms_13,tms_12,tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_15,tck_14,tck_13,tck_12,tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_15,runtest_14,runtest_13,runtest_12,runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
assign bscanid_en_10 = bscanid_en_int;
|
||||
assign bscanid_en_11 = bscanid_en_int;
|
||||
assign bscanid_en_12 = bscanid_en_int;
|
||||
assign bscanid_en_13 = bscanid_en_int;
|
||||
assign bscanid_en_14 = bscanid_en_int;
|
||||
assign bscanid_en_15 = bscanid_en_int;
|
||||
end
|
||||
|
||||
+491
@@ -0,0 +1,491 @@
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 3)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_2,tdo_1,tdo_0,TDO}),
|
||||
.m_bscan_tms ({tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid ({bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0],C_BSCANID})
|
||||
);
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 4)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_3,tdo_2,tdo_1,tdo_0,TDO}),
|
||||
.m_bscan_tms ({tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid ({bscanid_3[31:0],bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0],C_BSCANID})
|
||||
);
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 5)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,TDO}),
|
||||
.m_bscan_tms ({tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid ({bscanid_4[31:0],bscanid_3[31:0],bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0],C_BSCANID})
|
||||
);
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 6)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,TDO}),
|
||||
.m_bscan_tms ({tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid ({bscanid_5[31:0],bscanid_4[31:0],bscanid_3[31:0],bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0],C_BSCANID})
|
||||
);
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 7)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,TDO}),
|
||||
.m_bscan_tms ({tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid ({bscanid_6[31:0],bscanid_5[31:0],bscanid_4[31:0],bscanid_3[31:0],bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0],C_BSCANID})
|
||||
);
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 8)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,TDO}),
|
||||
.m_bscan_tms ({tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid ({bscanid_7[31:0],bscanid_6[31:0],bscanid_5[31:0],bscanid_4[31:0],bscanid_3[31:0],bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0],C_BSCANID})
|
||||
);
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 9)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,TDO}),
|
||||
.m_bscan_tms ({tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid ({bscanid_8[31:0],bscanid_7[31:0],bscanid_6[31:0],bscanid_5[31:0],bscanid_4[31:0],bscanid_3[31:0],bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0],C_BSCANID})
|
||||
);
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 10)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,TDO}),
|
||||
.m_bscan_tms ({tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid ({bscanid_9[31:0],bscanid_8[31:0],bscanid_7[31:0],bscanid_6[31:0],bscanid_5[31:0],bscanid_4[31:0],bscanid_3[31:0],bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0],C_BSCANID})
|
||||
);
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 11)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,TDO}),
|
||||
.m_bscan_tms ({tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid ({bscanid_10[31:0],bscanid_9[31:0],bscanid_8[31:0],bscanid_7[31:0],bscanid_6[31:0],bscanid_5[31:0],bscanid_4[31:0],bscanid_3[31:0],bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0],C_BSCANID})
|
||||
);
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 12)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,TDO}),
|
||||
.m_bscan_tms ({tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid ({bscanid_11[31:0],bscanid_10[31:0],bscanid_9[31:0],bscanid_8[31:0],bscanid_7[31:0],bscanid_6[31:0],bscanid_5[31:0],bscanid_4[31:0],bscanid_3[31:0],bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0],C_BSCANID})
|
||||
);
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 13)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_12,drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_12,capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_12,update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_12,shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_12,reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_12,sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_12,tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_12,tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,TDO}),
|
||||
.m_bscan_tms ({tms_12,tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_12,tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_12,runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid ({bscanid_12[31:0],bscanid_11[31:0],bscanid_10[31:0],bscanid_9[31:0],bscanid_8[31:0],bscanid_7[31:0],bscanid_6[31:0],bscanid_5[31:0],bscanid_4[31:0],bscanid_3[31:0],bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0],C_BSCANID})
|
||||
);
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 14)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_13,drck_12,drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_13,capture_12,capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_13,update_12,update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_13,shift_12,shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_13,reset_12,reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_13,sel_12,sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_13,tdi_12,tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_13,tdo_12,tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,TDO}),
|
||||
.m_bscan_tms ({tms_13,tms_12,tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_13,tck_12,tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_13,runtest_12,runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid ({bscanid_13[31:0],bscanid_12[31:0],bscanid_11[31:0],bscanid_10[31:0],bscanid_9[31:0],bscanid_8[31:0],bscanid_7[31:0],bscanid_6[31:0],bscanid_5[31:0],bscanid_4[31:0],bscanid_3[31:0],bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0],C_BSCANID})
|
||||
);
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 15)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_14,drck_13,drck_12,drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_14,capture_13,capture_12,capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_14,update_13,update_12,update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_14,shift_13,shift_12,shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_14,reset_13,reset_12,reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_14,sel_13,sel_12,sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_14,tdi_13,tdi_12,tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_14,tdo_13,tdo_12,tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,TDO}),
|
||||
.m_bscan_tms ({tms_14,tms_13,tms_12,tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_14,tck_13,tck_12,tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_14,runtest_13,runtest_12,runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid ({bscanid_14[31:0],bscanid_13[31:0],bscanid_12[31:0],bscanid_11[31:0],bscanid_10[31:0],bscanid_9[31:0],bscanid_8[31:0],bscanid_7[31:0],bscanid_6[31:0],bscanid_5[31:0],bscanid_4[31:0],bscanid_3[31:0],bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0],C_BSCANID})
|
||||
);
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 16)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_15,drck_14,drck_13,drck_12,drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_15,capture_14,capture_13,capture_12,capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_15,update_14,update_13,update_12,update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_15,shift_14,shift_13,shift_12,shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_15,reset_14,reset_13,reset_12,reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_15,sel_14,sel_13,sel_12,sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_15,tdi_14,tdi_13,tdi_12,tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_15,tdo_14,tdo_13,tdo_12,tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,TDO}),
|
||||
.m_bscan_tms ({tms_15,tms_14,tms_13,tms_12,tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_15,tck_14,tck_13,tck_12,tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_15,runtest_14,runtest_13,runtest_12,runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid ({bscanid_15[31:0],bscanid_14[31:0],bscanid_13[31:0],bscanid_12[31:0],bscanid_11[31:0],bscanid_10[31:0],bscanid_9[31:0],bscanid_8[31:0],bscanid_7[31:0],bscanid_6[31:0],bscanid_5[31:0],bscanid_4[31:0],bscanid_3[31:0],bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0],C_BSCANID})
|
||||
);
|
||||
end
|
||||
|
||||
+638
@@ -0,0 +1,638 @@
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 3)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_2_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 4)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_2_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 5)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_2_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 6)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_2_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 7)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_2_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 8)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_2_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 9)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_2_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 10)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_2_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 11)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_2_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
assign bscanid_en_10 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 12)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_2_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
assign bscanid_en_10 = bscanid_en_int;
|
||||
assign bscanid_en_11 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 13)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_2_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_12,drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_12,capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_12,update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_12,shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_12,reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_12,sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_12,tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_12,tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_12,tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_12,tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_12,runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
assign bscanid_en_10 = bscanid_en_int;
|
||||
assign bscanid_en_11 = bscanid_en_int;
|
||||
assign bscanid_en_12 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 14)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_2_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_13,drck_12,drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_13,capture_12,capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_13,update_12,update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_13,shift_12,shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_13,reset_12,reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_13,sel_12,sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_13,tdi_12,tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_13,tdo_12,tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_13,tms_12,tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_13,tck_12,tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_13,runtest_12,runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
assign bscanid_en_10 = bscanid_en_int;
|
||||
assign bscanid_en_11 = bscanid_en_int;
|
||||
assign bscanid_en_12 = bscanid_en_int;
|
||||
assign bscanid_en_13 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 15)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_2_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_14,drck_13,drck_12,drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_14,capture_13,capture_12,capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_14,update_13,update_12,update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_14,shift_13,shift_12,shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_14,reset_13,reset_12,reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_14,sel_13,sel_12,sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_14,tdi_13,tdi_12,tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_14,tdo_13,tdo_12,tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_14,tms_13,tms_12,tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_14,tck_13,tck_12,tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_14,runtest_13,runtest_12,runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
assign bscanid_en_10 = bscanid_en_int;
|
||||
assign bscanid_en_11 = bscanid_en_int;
|
||||
assign bscanid_en_12 = bscanid_en_int;
|
||||
assign bscanid_en_13 = bscanid_en_int;
|
||||
assign bscanid_en_14 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 16)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_2_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_15,drck_14,drck_13,drck_12,drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_15,capture_14,capture_13,capture_12,capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_15,update_14,update_13,update_12,update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_15,shift_14,shift_13,shift_12,shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_15,reset_14,reset_13,reset_12,reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_15,sel_14,sel_13,sel_12,sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_15,tdi_14,tdi_13,tdi_12,tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_15,tdo_14,tdo_13,tdo_12,tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_15,tms_14,tms_13,tms_12,tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_15,tck_14,tck_13,tck_12,tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_15,runtest_14,runtest_13,runtest_12,runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
assign bscanid_en_10 = bscanid_en_int;
|
||||
assign bscanid_en_11 = bscanid_en_int;
|
||||
assign bscanid_en_12 = bscanid_en_int;
|
||||
assign bscanid_en_13 = bscanid_en_int;
|
||||
assign bscanid_en_14 = bscanid_en_int;
|
||||
assign bscanid_en_15 = bscanid_en_int;
|
||||
end
|
||||
|
||||
+176
@@ -0,0 +1,176 @@
|
||||
(* BSCAN_SLAVE_INDEX = 0 *)output update_0,
|
||||
(* BSCAN_SLAVE_INDEX = 0 *)output capture_0,
|
||||
(* BSCAN_SLAVE_INDEX = 0 *)output reset_0,
|
||||
(* BSCAN_SLAVE_INDEX = 0 *)output runtest_0,
|
||||
(* BSCAN_SLAVE_INDEX = 0 *)output tms_0,
|
||||
(* BSCAN_SLAVE_INDEX = 0 *)output tck_0,
|
||||
(* BSCAN_SLAVE_INDEX = 0 *)output tdi_0,
|
||||
(* BSCAN_SLAVE_INDEX = 0 *)output sel_0,
|
||||
(* BSCAN_SLAVE_INDEX = 0 *)output shift_0,
|
||||
(* BSCAN_SLAVE_INDEX = 0 *)output drck_0,
|
||||
(* BSCAN_SLAVE_INDEX = 0 *)input tdo_0,
|
||||
(* BSCAN_SLAVE_INDEX = 1 *)output update_1,
|
||||
(* BSCAN_SLAVE_INDEX = 1 *)output capture_1,
|
||||
(* BSCAN_SLAVE_INDEX = 1 *)output reset_1,
|
||||
(* BSCAN_SLAVE_INDEX = 1 *)output runtest_1,
|
||||
(* BSCAN_SLAVE_INDEX = 1 *)output tms_1,
|
||||
(* BSCAN_SLAVE_INDEX = 1 *)output tck_1,
|
||||
(* BSCAN_SLAVE_INDEX = 1 *)output tdi_1,
|
||||
(* BSCAN_SLAVE_INDEX = 1 *)output sel_1,
|
||||
(* BSCAN_SLAVE_INDEX = 1 *)output shift_1,
|
||||
(* BSCAN_SLAVE_INDEX = 1 *)output drck_1,
|
||||
(* BSCAN_SLAVE_INDEX = 1 *)input tdo_1,
|
||||
(* BSCAN_SLAVE_INDEX = 2 *)output update_2,
|
||||
(* BSCAN_SLAVE_INDEX = 2 *)output capture_2,
|
||||
(* BSCAN_SLAVE_INDEX = 2 *)output reset_2,
|
||||
(* BSCAN_SLAVE_INDEX = 2 *)output runtest_2,
|
||||
(* BSCAN_SLAVE_INDEX = 2 *)output tms_2,
|
||||
(* BSCAN_SLAVE_INDEX = 2 *)output tck_2,
|
||||
(* BSCAN_SLAVE_INDEX = 2 *)output tdi_2,
|
||||
(* BSCAN_SLAVE_INDEX = 2 *)output sel_2,
|
||||
(* BSCAN_SLAVE_INDEX = 2 *)output shift_2,
|
||||
(* BSCAN_SLAVE_INDEX = 2 *)output drck_2,
|
||||
(* BSCAN_SLAVE_INDEX = 2 *)input tdo_2,
|
||||
(* BSCAN_SLAVE_INDEX = 3 *)output update_3,
|
||||
(* BSCAN_SLAVE_INDEX = 3 *)output capture_3,
|
||||
(* BSCAN_SLAVE_INDEX = 3 *)output reset_3,
|
||||
(* BSCAN_SLAVE_INDEX = 3 *)output runtest_3,
|
||||
(* BSCAN_SLAVE_INDEX = 3 *)output tms_3,
|
||||
(* BSCAN_SLAVE_INDEX = 3 *)output tck_3,
|
||||
(* BSCAN_SLAVE_INDEX = 3 *)output tdi_3,
|
||||
(* BSCAN_SLAVE_INDEX = 3 *)output sel_3,
|
||||
(* BSCAN_SLAVE_INDEX = 3 *)output shift_3,
|
||||
(* BSCAN_SLAVE_INDEX = 3 *)output drck_3,
|
||||
(* BSCAN_SLAVE_INDEX = 3 *)input tdo_3,
|
||||
(* BSCAN_SLAVE_INDEX = 4 *)output update_4,
|
||||
(* BSCAN_SLAVE_INDEX = 4 *)output capture_4,
|
||||
(* BSCAN_SLAVE_INDEX = 4 *)output reset_4,
|
||||
(* BSCAN_SLAVE_INDEX = 4 *)output runtest_4,
|
||||
(* BSCAN_SLAVE_INDEX = 4 *)output tms_4,
|
||||
(* BSCAN_SLAVE_INDEX = 4 *)output tck_4,
|
||||
(* BSCAN_SLAVE_INDEX = 4 *)output tdi_4,
|
||||
(* BSCAN_SLAVE_INDEX = 4 *)output sel_4,
|
||||
(* BSCAN_SLAVE_INDEX = 4 *)output shift_4,
|
||||
(* BSCAN_SLAVE_INDEX = 4 *)output drck_4,
|
||||
(* BSCAN_SLAVE_INDEX = 4 *)input tdo_4,
|
||||
(* BSCAN_SLAVE_INDEX = 5 *)output update_5,
|
||||
(* BSCAN_SLAVE_INDEX = 5 *)output capture_5,
|
||||
(* BSCAN_SLAVE_INDEX = 5 *)output reset_5,
|
||||
(* BSCAN_SLAVE_INDEX = 5 *)output runtest_5,
|
||||
(* BSCAN_SLAVE_INDEX = 5 *)output tms_5,
|
||||
(* BSCAN_SLAVE_INDEX = 5 *)output tck_5,
|
||||
(* BSCAN_SLAVE_INDEX = 5 *)output tdi_5,
|
||||
(* BSCAN_SLAVE_INDEX = 5 *)output sel_5,
|
||||
(* BSCAN_SLAVE_INDEX = 5 *)output shift_5,
|
||||
(* BSCAN_SLAVE_INDEX = 5 *)output drck_5,
|
||||
(* BSCAN_SLAVE_INDEX = 5 *)input tdo_5,
|
||||
(* BSCAN_SLAVE_INDEX = 6 *)output update_6,
|
||||
(* BSCAN_SLAVE_INDEX = 6 *)output capture_6,
|
||||
(* BSCAN_SLAVE_INDEX = 6 *)output reset_6,
|
||||
(* BSCAN_SLAVE_INDEX = 6 *)output runtest_6,
|
||||
(* BSCAN_SLAVE_INDEX = 6 *)output tms_6,
|
||||
(* BSCAN_SLAVE_INDEX = 6 *)output tck_6,
|
||||
(* BSCAN_SLAVE_INDEX = 6 *)output tdi_6,
|
||||
(* BSCAN_SLAVE_INDEX = 6 *)output sel_6,
|
||||
(* BSCAN_SLAVE_INDEX = 6 *)output shift_6,
|
||||
(* BSCAN_SLAVE_INDEX = 6 *)output drck_6,
|
||||
(* BSCAN_SLAVE_INDEX = 6 *)input tdo_6,
|
||||
(* BSCAN_SLAVE_INDEX = 7 *)output update_7,
|
||||
(* BSCAN_SLAVE_INDEX = 7 *)output capture_7,
|
||||
(* BSCAN_SLAVE_INDEX = 7 *)output reset_7,
|
||||
(* BSCAN_SLAVE_INDEX = 7 *)output runtest_7,
|
||||
(* BSCAN_SLAVE_INDEX = 7 *)output tms_7,
|
||||
(* BSCAN_SLAVE_INDEX = 7 *)output tck_7,
|
||||
(* BSCAN_SLAVE_INDEX = 7 *)output tdi_7,
|
||||
(* BSCAN_SLAVE_INDEX = 7 *)output sel_7,
|
||||
(* BSCAN_SLAVE_INDEX = 7 *)output shift_7,
|
||||
(* BSCAN_SLAVE_INDEX = 7 *)output drck_7,
|
||||
(* BSCAN_SLAVE_INDEX = 7 *)input tdo_7,
|
||||
(* BSCAN_SLAVE_INDEX = 8 *)output update_8,
|
||||
(* BSCAN_SLAVE_INDEX = 8 *)output capture_8,
|
||||
(* BSCAN_SLAVE_INDEX = 8 *)output reset_8,
|
||||
(* BSCAN_SLAVE_INDEX = 8 *)output runtest_8,
|
||||
(* BSCAN_SLAVE_INDEX = 8 *)output tms_8,
|
||||
(* BSCAN_SLAVE_INDEX = 8 *)output tck_8,
|
||||
(* BSCAN_SLAVE_INDEX = 8 *)output tdi_8,
|
||||
(* BSCAN_SLAVE_INDEX = 8 *)output sel_8,
|
||||
(* BSCAN_SLAVE_INDEX = 8 *)output shift_8,
|
||||
(* BSCAN_SLAVE_INDEX = 8 *)output drck_8,
|
||||
(* BSCAN_SLAVE_INDEX = 8 *)input tdo_8,
|
||||
(* BSCAN_SLAVE_INDEX = 9 *)output update_9,
|
||||
(* BSCAN_SLAVE_INDEX = 9 *)output capture_9,
|
||||
(* BSCAN_SLAVE_INDEX = 9 *)output reset_9,
|
||||
(* BSCAN_SLAVE_INDEX = 9 *)output runtest_9,
|
||||
(* BSCAN_SLAVE_INDEX = 9 *)output tms_9,
|
||||
(* BSCAN_SLAVE_INDEX = 9 *)output tck_9,
|
||||
(* BSCAN_SLAVE_INDEX = 9 *)output tdi_9,
|
||||
(* BSCAN_SLAVE_INDEX = 9 *)output sel_9,
|
||||
(* BSCAN_SLAVE_INDEX = 9 *)output shift_9,
|
||||
(* BSCAN_SLAVE_INDEX = 9 *)output drck_9,
|
||||
(* BSCAN_SLAVE_INDEX = 9 *)input tdo_9,
|
||||
(* BSCAN_SLAVE_INDEX = 10 *)output update_10,
|
||||
(* BSCAN_SLAVE_INDEX = 10 *)output capture_10,
|
||||
(* BSCAN_SLAVE_INDEX = 10 *)output reset_10,
|
||||
(* BSCAN_SLAVE_INDEX = 10 *)output runtest_10,
|
||||
(* BSCAN_SLAVE_INDEX = 10 *)output tms_10,
|
||||
(* BSCAN_SLAVE_INDEX = 10 *)output tck_10,
|
||||
(* BSCAN_SLAVE_INDEX = 10 *)output tdi_10,
|
||||
(* BSCAN_SLAVE_INDEX = 10 *)output sel_10,
|
||||
(* BSCAN_SLAVE_INDEX = 10 *)output shift_10,
|
||||
(* BSCAN_SLAVE_INDEX = 10 *)output drck_10,
|
||||
(* BSCAN_SLAVE_INDEX = 10 *)input tdo_10,
|
||||
(* BSCAN_SLAVE_INDEX = 11 *)output update_11,
|
||||
(* BSCAN_SLAVE_INDEX = 11 *)output capture_11,
|
||||
(* BSCAN_SLAVE_INDEX = 11 *)output reset_11,
|
||||
(* BSCAN_SLAVE_INDEX = 11 *)output runtest_11,
|
||||
(* BSCAN_SLAVE_INDEX = 11 *)output tms_11,
|
||||
(* BSCAN_SLAVE_INDEX = 11 *)output tck_11,
|
||||
(* BSCAN_SLAVE_INDEX = 11 *)output tdi_11,
|
||||
(* BSCAN_SLAVE_INDEX = 11 *)output sel_11,
|
||||
(* BSCAN_SLAVE_INDEX = 11 *)output shift_11,
|
||||
(* BSCAN_SLAVE_INDEX = 11 *)output drck_11,
|
||||
(* BSCAN_SLAVE_INDEX = 11 *)input tdo_11,
|
||||
(* BSCAN_SLAVE_INDEX = 12 *)output update_12,
|
||||
(* BSCAN_SLAVE_INDEX = 12 *)output capture_12,
|
||||
(* BSCAN_SLAVE_INDEX = 12 *)output reset_12,
|
||||
(* BSCAN_SLAVE_INDEX = 12 *)output runtest_12,
|
||||
(* BSCAN_SLAVE_INDEX = 12 *)output tms_12,
|
||||
(* BSCAN_SLAVE_INDEX = 12 *)output tck_12,
|
||||
(* BSCAN_SLAVE_INDEX = 12 *)output tdi_12,
|
||||
(* BSCAN_SLAVE_INDEX = 12 *)output sel_12,
|
||||
(* BSCAN_SLAVE_INDEX = 12 *)output shift_12,
|
||||
(* BSCAN_SLAVE_INDEX = 12 *)output drck_12,
|
||||
(* BSCAN_SLAVE_INDEX = 12 *)input tdo_12,
|
||||
(* BSCAN_SLAVE_INDEX = 13 *)output update_13,
|
||||
(* BSCAN_SLAVE_INDEX = 13 *)output capture_13,
|
||||
(* BSCAN_SLAVE_INDEX = 13 *)output reset_13,
|
||||
(* BSCAN_SLAVE_INDEX = 13 *)output runtest_13,
|
||||
(* BSCAN_SLAVE_INDEX = 13 *)output tms_13,
|
||||
(* BSCAN_SLAVE_INDEX = 13 *)output tck_13,
|
||||
(* BSCAN_SLAVE_INDEX = 13 *)output tdi_13,
|
||||
(* BSCAN_SLAVE_INDEX = 13 *)output sel_13,
|
||||
(* BSCAN_SLAVE_INDEX = 13 *)output shift_13,
|
||||
(* BSCAN_SLAVE_INDEX = 13 *)output drck_13,
|
||||
(* BSCAN_SLAVE_INDEX = 13 *)input tdo_13,
|
||||
(* BSCAN_SLAVE_INDEX = 14 *)output update_14,
|
||||
(* BSCAN_SLAVE_INDEX = 14 *)output capture_14,
|
||||
(* BSCAN_SLAVE_INDEX = 14 *)output reset_14,
|
||||
(* BSCAN_SLAVE_INDEX = 14 *)output runtest_14,
|
||||
(* BSCAN_SLAVE_INDEX = 14 *)output tms_14,
|
||||
(* BSCAN_SLAVE_INDEX = 14 *)output tck_14,
|
||||
(* BSCAN_SLAVE_INDEX = 14 *)output tdi_14,
|
||||
(* BSCAN_SLAVE_INDEX = 14 *)output sel_14,
|
||||
(* BSCAN_SLAVE_INDEX = 14 *)output shift_14,
|
||||
(* BSCAN_SLAVE_INDEX = 14 *)output drck_14,
|
||||
(* BSCAN_SLAVE_INDEX = 14 *)input tdo_14,
|
||||
(* BSCAN_SLAVE_INDEX = 15 *)output update_15,
|
||||
(* BSCAN_SLAVE_INDEX = 15 *)output capture_15,
|
||||
(* BSCAN_SLAVE_INDEX = 15 *)output reset_15,
|
||||
(* BSCAN_SLAVE_INDEX = 15 *)output runtest_15,
|
||||
(* BSCAN_SLAVE_INDEX = 15 *)output tms_15,
|
||||
(* BSCAN_SLAVE_INDEX = 15 *)output tck_15,
|
||||
(* BSCAN_SLAVE_INDEX = 15 *)output tdi_15,
|
||||
(* BSCAN_SLAVE_INDEX = 15 *)output sel_15,
|
||||
(* BSCAN_SLAVE_INDEX = 15 *)output shift_15,
|
||||
(* BSCAN_SLAVE_INDEX = 15 *)output drck_15,
|
||||
(* BSCAN_SLAVE_INDEX = 15 *)input tdo_15,
|
||||
+491
@@ -0,0 +1,491 @@
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 3)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid ({bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0]})
|
||||
);
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 4)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid ({bscanid_3[31:0],bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0]})
|
||||
);
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 5)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid ({bscanid_4[31:0],bscanid_3[31:0],bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0]})
|
||||
);
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 6)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid ({bscanid_5[31:0],bscanid_4[31:0],bscanid_3[31:0],bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0]})
|
||||
);
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 7)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid ({bscanid_6[31:0],bscanid_5[31:0],bscanid_4[31:0],bscanid_3[31:0],bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0]})
|
||||
);
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 8)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid ({bscanid_7[31:0],bscanid_6[31:0],bscanid_5[31:0],bscanid_4[31:0],bscanid_3[31:0],bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0]})
|
||||
);
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 9)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid ({bscanid_8[31:0],bscanid_7[31:0],bscanid_6[31:0],bscanid_5[31:0],bscanid_4[31:0],bscanid_3[31:0],bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0]})
|
||||
);
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 10)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid ({bscanid_9[31:0],bscanid_8[31:0],bscanid_7[31:0],bscanid_6[31:0],bscanid_5[31:0],bscanid_4[31:0],bscanid_3[31:0],bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0]})
|
||||
);
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 11)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid ({bscanid_10[31:0],bscanid_9[31:0],bscanid_8[31:0],bscanid_7[31:0],bscanid_6[31:0],bscanid_5[31:0],bscanid_4[31:0],bscanid_3[31:0],bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0]})
|
||||
);
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 12)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid ({bscanid_11[31:0],bscanid_10[31:0],bscanid_9[31:0],bscanid_8[31:0],bscanid_7[31:0],bscanid_6[31:0],bscanid_5[31:0],bscanid_4[31:0],bscanid_3[31:0],bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0]})
|
||||
);
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 13)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_12,drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_12,capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_12,update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_12,shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_12,reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_12,sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_12,tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_12,tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_12,tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_12,tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_12,runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid ({bscanid_12[31:0],bscanid_11[31:0],bscanid_10[31:0],bscanid_9[31:0],bscanid_8[31:0],bscanid_7[31:0],bscanid_6[31:0],bscanid_5[31:0],bscanid_4[31:0],bscanid_3[31:0],bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0]})
|
||||
);
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 14)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_13,drck_12,drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_13,capture_12,capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_13,update_12,update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_13,shift_12,shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_13,reset_12,reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_13,sel_12,sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_13,tdi_12,tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_13,tdo_12,tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_13,tms_12,tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_13,tck_12,tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_13,runtest_12,runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid ({bscanid_13[31:0],bscanid_12[31:0],bscanid_11[31:0],bscanid_10[31:0],bscanid_9[31:0],bscanid_8[31:0],bscanid_7[31:0],bscanid_6[31:0],bscanid_5[31:0],bscanid_4[31:0],bscanid_3[31:0],bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0]})
|
||||
);
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 15)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_14,drck_13,drck_12,drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_14,capture_13,capture_12,capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_14,update_13,update_12,update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_14,shift_13,shift_12,shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_14,reset_13,reset_12,reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_14,sel_13,sel_12,sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_14,tdi_13,tdi_12,tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_14,tdo_13,tdo_12,tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_14,tms_13,tms_12,tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_14,tck_13,tck_12,tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_14,runtest_13,runtest_12,runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid ({bscanid_14[31:0],bscanid_13[31:0],bscanid_12[31:0],bscanid_11[31:0],bscanid_10[31:0],bscanid_9[31:0],bscanid_8[31:0],bscanid_7[31:0],bscanid_6[31:0],bscanid_5[31:0],bscanid_4[31:0],bscanid_3[31:0],bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0]})
|
||||
);
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 16)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_15,drck_14,drck_13,drck_12,drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_15,capture_14,capture_13,capture_12,capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_15,update_14,update_13,update_12,update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_15,shift_14,shift_13,shift_12,shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_15,reset_14,reset_13,reset_12,reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_15,sel_14,sel_13,sel_12,sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_15,tdi_14,tdi_13,tdi_12,tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_15,tdo_14,tdo_13,tdo_12,tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_15,tms_14,tms_13,tms_12,tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_15,tck_14,tck_13,tck_12,tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_15,runtest_14,runtest_13,runtest_12,runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid ({bscanid_15[31:0],bscanid_14[31:0],bscanid_13[31:0],bscanid_12[31:0],bscanid_11[31:0],bscanid_10[31:0],bscanid_9[31:0],bscanid_8[31:0],bscanid_7[31:0],bscanid_6[31:0],bscanid_5[31:0],bscanid_4[31:0],bscanid_3[31:0],bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0]})
|
||||
);
|
||||
end
|
||||
|
||||
+16
@@ -0,0 +1,16 @@
|
||||
(* BSCAN_SLAVE_INDEX = 0 *)output bscanid_en_0,
|
||||
(* BSCAN_SLAVE_INDEX = 1 *)output bscanid_en_1,
|
||||
(* BSCAN_SLAVE_INDEX = 2 *)output bscanid_en_2,
|
||||
(* BSCAN_SLAVE_INDEX = 3 *)output bscanid_en_3,
|
||||
(* BSCAN_SLAVE_INDEX = 4 *)output bscanid_en_4,
|
||||
(* BSCAN_SLAVE_INDEX = 5 *)output bscanid_en_5,
|
||||
(* BSCAN_SLAVE_INDEX = 6 *)output bscanid_en_6,
|
||||
(* BSCAN_SLAVE_INDEX = 7 *)output bscanid_en_7,
|
||||
(* BSCAN_SLAVE_INDEX = 8 *)output bscanid_en_8,
|
||||
(* BSCAN_SLAVE_INDEX = 9 *)output bscanid_en_9,
|
||||
(* BSCAN_SLAVE_INDEX = 10 *)output bscanid_en_10,
|
||||
(* BSCAN_SLAVE_INDEX = 11 *)output bscanid_en_11,
|
||||
(* BSCAN_SLAVE_INDEX = 12 *)output bscanid_en_12,
|
||||
(* BSCAN_SLAVE_INDEX = 13 *)output bscanid_en_13,
|
||||
(* BSCAN_SLAVE_INDEX = 14 *)output bscanid_en_14,
|
||||
(* BSCAN_SLAVE_INDEX = 15 *)output bscanid_en_15,
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user