feat: 新增工程,由20241025技术支持包中的coms工程upgrade得到,发端修改为演示验证QPSK

cx9261a_demo_cmos_20240829/.gitignore

@@ -0,0 +1,130 @@
+################################################################################
+############################### Project Specific ###############################
+################################################################################
+# everything
+*
+
+# git related
+!/.gitignore
+!/.gitattributes
+
+# project documents
+!/*.md
+!/*.txt
+
+################################################################################
+############################### Vivado Specific ################################
+################################################################################
+
+# xpr: needed for recreating design
+!/*.xpr
+
+# source: include everything
+!/*.srcs/
+!/*.srcs/**/*
+
+# runs: exclude everything but design run results
+!/*.runs/
+!/*.runs/impl_*/
+!/*.runs/impl_*/*.bit
+!/*.runs/impl_*/*.ltx
+
+# xsa (Xilinx support archive): include for ps
+!/*.xsa
+
+################################################################################
+################################ Vitis Specific ################################
+################################################################################
+
+# include sdk directory and everything in it
+!/vitis*/
+!/vitis*/**
+/vitis*/**.log
+/vitis*/.analytics
+
+# exclude some obscure hidden SDK folders
+/vitis*/.metadata/
+/vitis*/.sdk/
+/vitis*/RemoteSystemsTempFiles/
+/vitis*/webtalk/
+
+# hw_platform: exclude the entire hw_platform folder, as everything can be
+# generated from the .hdf file. Make sure to include the bitstream in the .hdf
+# file when exporting from Vivado!
+/vitis*/*_hw_platform_*/
+
+# BSP: only keep `.cproject`, `.project`, `.sdkproject`, `.system.mss` and
+# Makefile, ps lib files are regenerated automatically
+/vitis*/*_bsp/*
+!/vitis*/*_bsp/*.cproject
+!/vitis*/*_bsp/*.project
+!/vitis*/*_bsp/*.sdkproject
+!/vitis*/*_bsp/system.mss
+!/vitis*/*_bsp/Makefile
+
+# Application: ignored file patterns, exclude Debug & Release folders
+/vitis*/**/*.o
+/vitis*/**/*.d
+/vitis*/**/*.a
+/vitis*/*/Debug/
+/vitis*/*/Release/
+
+################################################################################
+############################ Vivado & Vitis Common #############################
+################################################################################
+
+# file patterns that should always be ignored (journal files, log files, dump
+# files that are created upon Vivado/SDK errors)
+*.jou
+*.log
+*.backup.jou
+*.backup.log
+*.upgrade_log
+*.dmp
+*.debug
+vivado_pid*
+
+# vivado workspace files
+xsim.dir/
+xvlog.pb
+
+# Xilinx tools generated files
+.metadata/
+.settings/
+.wsdata/
+.Xil/
+logs/
+Packages/
+*.log*
+
+# System generated files
+# -- macOS
+.DS_Store
+.AppleDouble
+.LSOverride
+._*
+
+# -- Windows
+Thumbs.db
+ehthumbs.db
+Desktop.ini
+
+# -- Linux
+*~
+
+# IDEs and editors' files
+*.idea
+*.vscode
+*.sublime-workspace
+*.sublime-project
+
+################################################################################
+############################### Project Specific ###############################
+################################################################################
+
+!/bootimage/
+!/bootimage/**/*
+!/ip_repo/
+!/ip_repo/**/*
+!/rom_data/
+!/rom_data/**/*

cx9261a_demo_cmos_20240829/bootimage/20240315/v20240315.bif

@@ -0,0 +1,7 @@
+//arch = zynq; split = false; format = BIN
+the_ROM_image:
+{
+	[bootloader]C:\Users\cxlab\Desktop\fpga_project\01_CX7045_demo\cmos\CX9261A_FPGA_DEMO240318\project_fix_dac.sdk\FSBL\Debug\FSBL.elf
+	C:\Users\cxlab\Desktop\fpga_project\01_CX7045_demo\cmos\CX9261A_FPGA_DEMO240318\project_fix_dac.runs\impl_2\CX9261A_ZC706.bit
+	C:\Users\cxlab\Desktop\fpga_project\01_CX7045_demo\cmos\CX9261A_FPGA_DEMO240318\project_fix_dac.sdk\CX9261A_DEMO\Debug\CX9261A_DEMO.elf
+}

cx9261a_demo_cmos_20240829/bootimage/20240407/v20240407.bif

@@ -0,0 +1,7 @@
+//arch = zynq; split = false; format = BIN
+the_ROM_image:
+{
+	[bootloader]C:\Users\cxlab\Desktop\fpga_project\01_CX7045_demo\cmos\CX9261A_FPGA_DEMO240318\project_fix_dac.sdk\FSBL\Debug\FSBL.elf
+	C:\Users\cxlab\Desktop\fpga_project\01_CX7045_demo\cmos\CX9261A_FPGA_DEMO240318\project_fix_dac.runs\impl_1\CX9261A_ZC706.bit
+	C:\Users\cxlab\Desktop\fpga_project\01_CX7045_demo\cmos\CX9261A_FPGA_DEMO240318\project_fix_dac.sdk\CX9261A_DEMO\Debug\CX9261A_DEMO.elf
+}

cx9261a_demo_cmos_20240829/ip_repo/Axis_adc_data_packer_1.0/bd/bd.tcl

@@ -0,0 +1,86 @@
+
+proc init { cellpath otherInfo } {                                                                   
+                                                                                                             
+	set cell_handle [get_bd_cells $cellpath]                                                                 
+	set all_busif [get_bd_intf_pins $cellpath/*]		                                                     
+	set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
+	set full_sbusif_list [list  ]
+			                                                                                                 
+	foreach busif $all_busif {                                                                               
+		if { [string equal -nocase [get_property MODE $busif] "slave"] == 1 } {                            
+			set busif_param_list [list]                                                                      
+			set busif_name [get_property NAME $busif]					                                     
+			if { [lsearch -exact -nocase $full_sbusif_list $busif_name ] == -1 } {					         
+			    continue                                                                                     
+			}                                                                                                
+			foreach tparam $axi_standard_param_list {                                                        
+				lappend busif_param_list "C_${busif_name}_${tparam}"                                       
+			}                                                                                                
+			bd::mark_propagate_only $cell_handle $busif_param_list			                                 
+		}		                                                                                             
+	}                                                                                                        
+}
+
+
+proc pre_propagate {cellpath otherInfo } {                                                           
+                                                                                                             
+	set cell_handle [get_bd_cells $cellpath]                                                                 
+	set all_busif [get_bd_intf_pins $cellpath/*]		                                                     
+	set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
+	                                                                                                         
+	foreach busif $all_busif {	                                                                             
+		if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {                  
+			continue                                                                                         
+		}                                                                                                    
+		if { [string equal -nocase [get_property MODE $busif] "master"] != 1 } {                           
+			continue                                                                                         
+		}			                                                                                         
+		                                                                                                     
+		set busif_name [get_property NAME $busif]			                                                 
+		foreach tparam $axi_standard_param_list {		                                                     
+			set busif_param_name "C_${busif_name}_${tparam}"			                                     
+			                                                                                                 
+			set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]                                  
+			set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]                           
+			                                                                                                 
+			if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {                          
+				if { $val_on_cell != "" } {                                                                  
+					set_property CONFIG.${tparam} $val_on_cell $busif                                        
+				}                                                                                            
+			}			                                                                                     
+		}		                                                                                             
+	}                                                                                                        
+}
+
+
+proc propagate {cellpath otherInfo } {                                                               
+                                                                                                             
+	set cell_handle [get_bd_cells $cellpath]                                                                 
+	set all_busif [get_bd_intf_pins $cellpath/*]		                                                     
+	set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
+	                                                                                                         
+	foreach busif $all_busif {                                                                               
+		if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {                  
+			continue                                                                                         
+		}                                                                                                    
+		if { [string equal -nocase [get_property MODE $busif] "slave"] != 1 } {                            
+			continue                                                                                         
+		}			                                                                                         
+	                                                                                                         
+		set busif_name [get_property NAME $busif]		                                                     
+		foreach tparam $axi_standard_param_list {			                                                 
+			set busif_param_name "C_${busif_name}_${tparam}"			                                     
+                                                                                                             
+			set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]                                  
+			set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]                           
+			                                                                                                 
+			if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {                          
+				#override property of bd_interface_net to bd_cell -- only for slaves.  May check for supported values..
+				if { $val_on_cell_intf_pin != "" } {                                                         
+					set_property CONFIG.${busif_param_name} $val_on_cell_intf_pin $cell_handle               
+				}                                                                                            
+			}                                                                                                
+		}		                                                                                             
+	}                                                                                                        
+}
+

cx9261a_demo_cmos_20240829/ip_repo/Axis_adc_data_packer_1.0/drivers/Axis_adc_data_packer_v1_0/data/Axis_adc_data_packer.mdd

@@ -0,0 +1,10 @@
+
+
+OPTION psf_version = 2.1;
+
+BEGIN DRIVER Axis_adc_data_packer
+	OPTION supported_peripherals = (Axis_adc_data_packer);
+	OPTION copyfiles = all;
+	OPTION VERSION = 1.0;
+	OPTION NAME = Axis_adc_data_packer;
+END DRIVER

cx9261a_demo_cmos_20240829/ip_repo/Axis_adc_data_packer_1.0/drivers/Axis_adc_data_packer_v1_0/data/Axis_adc_data_packer.tcl

@@ -0,0 +1,5 @@
+
+
+proc generate {drv_handle} {
+	xdefine_include_file $drv_handle "xparameters.h" "Axis_adc_data_packer" "NUM_INSTANCES" "DEVICE_ID"  "C_S00_AXI_BASEADDR" "C_S00_AXI_HIGHADDR"
+}

cx9261a_demo_cmos_20240829/ip_repo/Axis_adc_data_packer_1.0/drivers/Axis_adc_data_packer_v1_0/src/Axis_adc_data_packer.c

@@ -0,0 +1,6 @@
+
+
+/***************************** Include Files *******************************/
+#include "Axis_adc_data_packer.h"
+
+/************************** Function Definitions ***************************/

cx9261a_demo_cmos_20240829/ip_repo/Axis_adc_data_packer_1.0/drivers/Axis_adc_data_packer_v1_0/src/Axis_adc_data_packer.h

@@ -0,0 +1,79 @@
+
+#ifndef AXIS_ADC_DATA_PACKER_H
+#define AXIS_ADC_DATA_PACKER_H
+
+
+/****************** Include Files ********************/
+#include "xil_types.h"
+#include "xstatus.h"
+
+#define AXIS_ADC_DATA_PACKER_S00_AXI_SLV_REG0_OFFSET 0
+#define AXIS_ADC_DATA_PACKER_S00_AXI_SLV_REG1_OFFSET 4
+#define AXIS_ADC_DATA_PACKER_S00_AXI_SLV_REG2_OFFSET 8
+#define AXIS_ADC_DATA_PACKER_S00_AXI_SLV_REG3_OFFSET 12
+
+
+/**************************** Type Definitions *****************************/
+/**
+ *
+ * Write a value to a AXIS_ADC_DATA_PACKER register. A 32 bit write is performed.
+ * If the component is implemented in a smaller width, only the least
+ * significant data is written.
+ *
+ * @param   BaseAddress is the base address of the AXIS_ADC_DATA_PACKERdevice.
+ * @param   RegOffset is the register offset from the base to write to.
+ * @param   Data is the data written to the register.
+ *
+ * @return  None.
+ *
+ * @note
+ * C-style signature:
+ * 	void AXIS_ADC_DATA_PACKER_mWriteReg(u32 BaseAddress, unsigned RegOffset, u32 Data)
+ *
+ */
+#define AXIS_ADC_DATA_PACKER_mWriteReg(BaseAddress, RegOffset, Data) \
+  	Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data))
+
+/**
+ *
+ * Read a value from a AXIS_ADC_DATA_PACKER register. A 32 bit read is performed.
+ * If the component is implemented in a smaller width, only the least
+ * significant data is read from the register. The most significant data
+ * will be read as 0.
+ *
+ * @param   BaseAddress is the base address of the AXIS_ADC_DATA_PACKER device.
+ * @param   RegOffset is the register offset from the base to write to.
+ *
+ * @return  Data is the data from the register.
+ *
+ * @note
+ * C-style signature:
+ * 	u32 AXIS_ADC_DATA_PACKER_mReadReg(u32 BaseAddress, unsigned RegOffset)
+ *
+ */
+#define AXIS_ADC_DATA_PACKER_mReadReg(BaseAddress, RegOffset) \
+    Xil_In32((BaseAddress) + (RegOffset))
+
+/************************** Function Prototypes ****************************/
+/**
+ *
+ * Run a self-test on the driver/device. Note this may be a destructive test if
+ * resets of the device are performed.
+ *
+ * If the hardware system is not built correctly, this function may never
+ * return to the caller.
+ *
+ * @param   baseaddr_p is the base address of the AXIS_ADC_DATA_PACKER instance to be worked on.
+ *
+ * @return
+ *
+ *    - XST_SUCCESS   if all self-test code passed
+ *    - XST_FAILURE   if any self-test code failed
+ *
+ * @note    Caching must be turned off for this function to work.
+ * @note    Self test may fail if data memory and device are not on the same bus.
+ *
+ */
+XStatus AXIS_ADC_DATA_PACKER_Reg_SelfTest(void * baseaddr_p);
+
+#endif // AXIS_ADC_DATA_PACKER_H

cx9261a_demo_cmos_20240829/ip_repo/Axis_adc_data_packer_1.0/drivers/Axis_adc_data_packer_v1_0/src/Axis_adc_data_packer_selftest.c

@@ -0,0 +1,60 @@
+
+/***************************** Include Files *******************************/
+#include "Axis_adc_data_packer.h"
+#include "xparameters.h"
+#include "stdio.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions ***************************/
+#define READ_WRITE_MUL_FACTOR 0x10
+
+/************************** Function Definitions ***************************/
+/**
+ *
+ * Run a self-test on the driver/device. Note this may be a destructive test if
+ * resets of the device are performed.
+ *
+ * If the hardware system is not built correctly, this function may never
+ * return to the caller.
+ *
+ * @param   baseaddr_p is the base address of the AXIS_ADC_DATA_PACKERinstance to be worked on.
+ *
+ * @return
+ *
+ *    - XST_SUCCESS   if all self-test code passed
+ *    - XST_FAILURE   if any self-test code failed
+ *
+ * @note    Caching must be turned off for this function to work.
+ * @note    Self test may fail if data memory and device are not on the same bus.
+ *
+ */
+XStatus AXIS_ADC_DATA_PACKER_Reg_SelfTest(void * baseaddr_p)
+{
+	u32 baseaddr;
+	int write_loop_index;
+	int read_loop_index;
+	int Index;
+
+	baseaddr = (u32) baseaddr_p;
+
+	xil_printf("******************************\n\r");
+	xil_printf("* User Peripheral Self Test\n\r");
+	xil_printf("******************************\n\n\r");
+
+	/*
+	 * Write to user logic slave module register(s) and read back
+	 */
+	xil_printf("User logic slave module test...\n\r");
+
+	for (write_loop_index = 0 ; write_loop_index < 4; write_loop_index++)
+	  AXIS_ADC_DATA_PACKER_mWriteReg (baseaddr, write_loop_index*4, (write_loop_index+1)*READ_WRITE_MUL_FACTOR);
+	for (read_loop_index = 0 ; read_loop_index < 4; read_loop_index++)
+	  if ( AXIS_ADC_DATA_PACKER_mReadReg (baseaddr, read_loop_index*4) != (read_loop_index+1)*READ_WRITE_MUL_FACTOR){
+	    xil_printf ("Error reading register value at address %x\n", (int)baseaddr + read_loop_index*4);
+	    return XST_FAILURE;
+	  }
+
+	xil_printf("   - slave register write/read passed\n\n\r");
+
+	return XST_SUCCESS;
+}

cx9261a_demo_cmos_20240829/ip_repo/Axis_adc_data_packer_1.0/drivers/Axis_adc_data_packer_v1_0/src/Makefile

@@ -0,0 +1,26 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+INCLUDEFILES=*.h
+LIBSOURCES=*.c
+OUTS = *.o
+
+libs:
+	echo "Compiling Axis_adc_data_packer..."
+	$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
+	make clean
+
+include:
+	${CP} $(INCLUDEFILES) $(INCLUDEDIR)
+
+clean:
+	rm -rf ${OUTS}

cx9261a_demo_cmos_20240829/ip_repo/Axis_adc_data_packer_1.0/example_designs/bfm_design/Axis_adc_data_packer_v1_0_tb.sv

@@ -0,0 +1,197 @@
+
+`timescale 1ns / 1ps
+`include "Axis_adc_data_packer_v1_0_tb_include.svh"
+
+import axi_vip_pkg::*;
+import Axis_adc_data_packer_v1_0_bfm_1_master_0_0_pkg::*;
+
+module Axis_adc_data_packer_v1_0_tb();
+
+
+xil_axi_uint                            error_cnt = 0;
+xil_axi_uint                            comparison_cnt = 0;
+axi_transaction                         wr_transaction;   
+axi_transaction                         rd_transaction;   
+axi_monitor_transaction                 mst_monitor_transaction;  
+axi_monitor_transaction                 master_moniter_transaction_queue[$];  
+xil_axi_uint                            master_moniter_transaction_queue_size =0;  
+axi_monitor_transaction                 mst_scb_transaction;  
+axi_monitor_transaction                 passthrough_monitor_transaction;  
+axi_monitor_transaction                 passthrough_master_moniter_transaction_queue[$];  
+xil_axi_uint                            passthrough_master_moniter_transaction_queue_size =0;  
+axi_monitor_transaction                 passthrough_mst_scb_transaction;  
+axi_monitor_transaction                 passthrough_slave_moniter_transaction_queue[$];  
+xil_axi_uint                            passthrough_slave_moniter_transaction_queue_size =0;  
+axi_monitor_transaction                 passthrough_slv_scb_transaction;  
+axi_monitor_transaction                 slv_monitor_transaction;  
+axi_monitor_transaction                 slave_moniter_transaction_queue[$];  
+xil_axi_uint                            slave_moniter_transaction_queue_size =0;  
+axi_monitor_transaction                 slv_scb_transaction;  
+xil_axi_uint                           mst_agent_verbosity = 0;  
+xil_axi_uint                           slv_agent_verbosity = 0;  
+xil_axi_uint                           passthrough_agent_verbosity = 0;  
+bit                                     clock;
+bit                                     reset;
+integer result_slave;  
+bit [31:0] S00_AXI_test_data[3:0]; 
+ localparam LC_AXI_BURST_LENGTH = 8; 
+ localparam LC_AXI_DATA_WIDTH = 32; 
+task automatic COMPARE_DATA; 
+  input [(LC_AXI_BURST_LENGTH * LC_AXI_DATA_WIDTH)-1:0]expected; 
+  input [(LC_AXI_BURST_LENGTH * LC_AXI_DATA_WIDTH)-1:0]actual; 
+  begin 
+    if (expected === 'hx || actual === 'hx) begin 
+      $display("TESTBENCH ERROR! COMPARE_DATA cannot be performed with an expected or actual vector that is all 'x'!"); 
+ result_slave = 0;    $stop; 
+  end 
+  if (actual != expected) begin 
+    $display("TESTBENCH ERROR! Data expected is not equal to actual.",     " expected = 0x%h",expected,     " actual   = 0x%h",actual); 
+    result_slave = 0; 
+    $stop; 
+  end 
+  else  
+    begin 
+     $display("TESTBENCH Passed! Data expected is equal to actual.", 
+              " expected = 0x%h",expected,               " actual   = 0x%h",actual); 
+    end 
+  end 
+endtask 
+integer                                 i; 
+integer                                 j;  
+xil_axi_uint                            trans_cnt_before_switch = 48;  
+xil_axi_uint                            passthrough_cmd_switch_cnt = 0;  
+event                                   passthrough_mastermode_start_event;  
+event                                   passthrough_mastermode_end_event;  
+event                                   passthrough_slavemode_end_event;  
+xil_axi_uint                            mtestID;  
+xil_axi_ulong                           mtestADDR;  
+xil_axi_len_t                           mtestBurstLength;  
+xil_axi_size_t                          mtestDataSize;   
+xil_axi_burst_t                         mtestBurstType;   
+xil_axi_lock_t                          mtestLOCK;  
+xil_axi_cache_t                         mtestCacheType = 0;  
+xil_axi_prot_t                          mtestProtectionType = 3'b000;  
+xil_axi_region_t                        mtestRegion = 4'b000;  
+xil_axi_qos_t                           mtestQOS = 4'b000;  
+xil_axi_data_beat                       dbeat;  
+xil_axi_data_beat [255:0]               mtestWUSER;   
+xil_axi_data_beat                       mtestAWUSER = 'h0;  
+xil_axi_data_beat                       mtestARUSER = 0;  
+xil_axi_data_beat [255:0]               mtestRUSER;      
+xil_axi_uint                            mtestBUSER = 0;  
+xil_axi_resp_t                          mtestBresp;  
+xil_axi_resp_t[255:0]                   mtestRresp;  
+bit [63:0]                              mtestWDataL; 
+bit [63:0]                              mtestRDataL; 
+axi_transaction                         pss_wr_transaction;   
+axi_transaction                         pss_rd_transaction;   
+axi_transaction                         reactive_transaction;   
+axi_transaction                         rd_payload_transaction;  
+axi_transaction                         wr_rand;  
+axi_transaction                         rd_rand;  
+axi_transaction                         wr_reactive;  
+axi_transaction                         rd_reactive;  
+axi_transaction                         wr_reactive2;   
+axi_transaction                         rd_reactive2;  
+axi_ready_gen                           bready_gen;  
+axi_ready_gen                           rready_gen;  
+axi_ready_gen                           awready_gen;  
+axi_ready_gen                           wready_gen;  
+axi_ready_gen                           arready_gen;  
+axi_ready_gen                           bready_gen2;  
+axi_ready_gen                           rready_gen2;  
+axi_ready_gen                           awready_gen2;  
+axi_ready_gen                           wready_gen2;  
+axi_ready_gen                           arready_gen2;  
+xil_axi_payload_byte                    data_mem[xil_axi_ulong];  
+Axis_adc_data_packer_v1_0_bfm_1_master_0_0_mst_t          mst_agent_0;
+
+  `BD_WRAPPER DUT(
+      .ARESETN(reset), 
+      .ACLK(clock) 
+    ); 
+  
+initial begin
+     mst_agent_0 = new("master vip agent",DUT.`BD_INST_NAME.master_0.inst.IF);//ms  
+   mst_agent_0.vif_proxy.set_dummy_drive_type(XIL_AXI_VIF_DRIVE_NONE); 
+   mst_agent_0.set_agent_tag("Master VIP"); 
+   mst_agent_0.set_verbosity(mst_agent_verbosity); 
+   mst_agent_0.start_master(); 
+     $timeformat (-12, 1, " ps", 1);
+  end
+  initial begin
+    reset <= 1'b0;
+    #200ns;
+    reset <= 1'b1;
+    repeat (5) @(negedge clock); 
+  end
+  always #5 clock <= ~clock;
+  initial begin
+      S_AXI_TEST ( );
+
+      #1ns;
+      $finish;
+  end
+task automatic S_AXI_TEST;  
+begin   
+#1; 
+   $display("Sequential write transfers example similar to  AXI BFM WRITE_BURST method starts"); 
+   mtestID = 0; 
+   mtestADDR = 64'h00000000; 
+   mtestBurstLength = 0; 
+   mtestDataSize = xil_axi_size_t'(xil_clog2(32/8)); 
+   mtestBurstType = XIL_AXI_BURST_TYPE_INCR;  
+   mtestLOCK = XIL_AXI_ALOCK_NOLOCK;  
+   mtestCacheType = 0;  
+   mtestProtectionType = 0;  
+   mtestRegion = 0; 
+   mtestQOS = 0; 
+   result_slave = 1; 
+  mtestWDataL[31:0] = 32'h00000001; 
+  for(int i = 0; i < 4;i++) begin 
+  S00_AXI_test_data[i] <= mtestWDataL[31:0];   
+  mst_agent_0.AXI4LITE_WRITE_BURST( 
+  mtestADDR, 
+  mtestProtectionType, 
+  mtestWDataL, 
+  mtestBresp 
+  );   
+  mtestWDataL[31:0] = mtestWDataL[31:0] + 1; 
+  mtestADDR = mtestADDR + 64'h4; 
+  end 
+     $display("Sequential write transfers example similar to  AXI BFM WRITE_BURST method completes"); 
+     $display("Sequential read transfers example similar to  AXI BFM READ_BURST method starts"); 
+     mtestID = 0; 
+     mtestADDR = 64'h00000000; 
+     mtestBurstLength = 0; 
+     mtestDataSize = xil_axi_size_t'(xil_clog2(32/8)); 
+     mtestBurstType = XIL_AXI_BURST_TYPE_INCR;  
+     mtestLOCK = XIL_AXI_ALOCK_NOLOCK;  
+     mtestCacheType = 0;  
+     mtestProtectionType = 0;  
+     mtestRegion = 0; 
+     mtestQOS = 0; 
+ for(int i = 0; i < 4;i++) begin 
+   mst_agent_0.AXI4LITE_READ_BURST( 
+        mtestADDR, 
+        mtestProtectionType, 
+        mtestRDataL, 
+        mtestRresp 
+      ); 
+   mtestADDR = mtestADDR + 64'h4; 
+   COMPARE_DATA(S00_AXI_test_data[i],mtestRDataL); 
+ end 
+     $display("Sequential read transfers example similar to  AXI BFM READ_BURST method completes"); 
+     $display("Sequential read transfers example similar to  AXI VIP READ_BURST method completes"); 
+     $display("---------------------------------------------------------"); 
+     $display("EXAMPLE TEST S00_AXI: PTGEN_TEST_FINISHED!"); 
+     if ( result_slave ) begin                    
+       $display("PTGEN_TEST: PASSED!");                  
+     end    else begin                                       
+       $display("PTGEN_TEST: FAILED!");                  
+     end                                
+     $display("---------------------------------------------------------"); 
+  end 
+endtask  
+
+endmodule

cx9261a_demo_cmos_20240829/ip_repo/Axis_adc_data_packer_1.0/example_designs/bfm_design/design.tcl

@@ -0,0 +1,88 @@
+proc create_ipi_design { offsetfile design_name } {
+	create_bd_design $design_name
+	open_bd_design $design_name
+
+	# Create Clock and Reset Ports
+	set ACLK [ create_bd_port -dir I -type clk ACLK ]
+	set_property -dict [ list CONFIG.FREQ_HZ {100000000} CONFIG.PHASE {0.000} CONFIG.CLK_DOMAIN "${design_name}_ACLK" ] $ACLK
+	set ARESETN [ create_bd_port -dir I -type rst ARESETN ]
+	set_property -dict [ list CONFIG.POLARITY {ACTIVE_LOW}  ] $ARESETN
+	set_property CONFIG.ASSOCIATED_RESET ARESETN $ACLK
+
+	# Create instance: Axis_adc_data_packer_0, and set properties
+	set Axis_adc_data_packer_0 [ create_bd_cell -type ip -vlnv labnet.com:user:Axis_adc_data_packer:1.0 Axis_adc_data_packer_0]
+
+	# Create instance: master_0, and set properties
+	set master_0 [ create_bd_cell -type ip -vlnv  xilinx.com:ip:axi_vip master_0]
+	set_property -dict [ list CONFIG.PROTOCOL {AXI4LITE} CONFIG.INTERFACE_MODE {MASTER} ] $master_0
+
+	# Create interface connections
+	connect_bd_intf_net [get_bd_intf_pins master_0/M_AXI ] [get_bd_intf_pins Axis_adc_data_packer_0/S00_AXI]
+
+	# Create port connections
+	connect_bd_net -net aclk_net [get_bd_ports ACLK] [get_bd_pins master_0/ACLK] [get_bd_pins Axis_adc_data_packer_0/S00_AXI_ACLK]
+	connect_bd_net -net aresetn_net [get_bd_ports ARESETN] [get_bd_pins master_0/ARESETN] [get_bd_pins Axis_adc_data_packer_0/S00_AXI_ARESETN]
+set_property target_simulator XSim [current_project]
+set_property -name {xsim.simulate.runtime} -value {100ms} -objects [get_filesets sim_1]
+
+	# Auto assign address
+	assign_bd_address
+
+	# Copy all address to interface_address.vh file
+	set bd_path [file dirname [get_property NAME [get_files ${design_name}.bd]]]
+	upvar 1 $offsetfile offset_file
+	set offset_file "${bd_path}/Axis_adc_data_packer_v1_0_tb_include.svh"
+	set fp [open $offset_file "w"]
+	puts $fp "`ifndef Axis_adc_data_packer_v1_0_tb_include_vh_"
+	puts $fp "`define Axis_adc_data_packer_v1_0_tb_include_vh_\n"
+	puts $fp "//Configuration current bd names"
+	puts $fp "`define BD_NAME ${design_name}"
+	puts $fp "`define BD_INST_NAME ${design_name}_i"
+	puts $fp "`define BD_WRAPPER ${design_name}_wrapper\n"
+	puts $fp "//Configuration address parameters"
+
+	puts $fp "`endif"
+	close $fp
+}
+
+set ip_path [file dirname [file normalize [get_property XML_FILE_NAME [ipx::get_cores labnet.com:user:Axis_adc_data_packer:1.0]]]]
+set test_bench_file ${ip_path}/example_designs/bfm_design/Axis_adc_data_packer_v1_0_tb.sv
+set interface_address_vh_file ""
+
+# Set IP Repository and Update IP Catalogue 
+set repo_paths [get_property ip_repo_paths [current_fileset]] 
+if { [lsearch -exact -nocase $repo_paths $ip_path ] == -1 } {
+	set_property ip_repo_paths "$ip_path [get_property ip_repo_paths [current_fileset]]" [current_fileset]
+	update_ip_catalog
+}
+
+set design_name ""
+set all_bd {}
+set all_bd_files [get_files *.bd -quiet]
+foreach file $all_bd_files {
+set file_name [string range $file [expr {[string last "/" $file] + 1}] end]
+set bd_name [string range $file_name 0 [expr {[string last "." $file_name] -1}]]
+lappend all_bd $bd_name
+}
+
+for { set i 1 } { 1 } { incr i } {
+	set design_name "Axis_adc_data_packer_v1_0_bfm_${i}"
+	if { [lsearch -exact -nocase $all_bd $design_name ] == -1 } {
+		break
+	}
+}
+
+create_ipi_design interface_address_vh_file ${design_name}
+validate_bd_design
+
+set wrapper_file [make_wrapper -files [get_files ${design_name}.bd] -top -force]
+import_files -force -norecurse $wrapper_file
+
+set_property SOURCE_SET sources_1 [get_filesets sim_1]
+import_files -fileset sim_1 -norecurse -force $test_bench_file
+remove_files -quiet -fileset sim_1 Axis_adc_data_packer_v1_0_tb_include.vh
+import_files -fileset sim_1 -norecurse -force $interface_address_vh_file
+set_property top Axis_adc_data_packer_v1_0_tb [get_filesets sim_1]
+set_property top_lib {} [get_filesets sim_1]
+set_property top_file {} [get_filesets sim_1]
+launch_simulation -simset sim_1 -mode behavioral

cx9261a_demo_cmos_20240829/ip_repo/Axis_adc_data_packer_1.0/example_designs/debug_hw_design/Axis_adc_data_packer_v1_0_hw_test.tcl

@@ -0,0 +1,45 @@
+# Runtime Tcl commands to interact with - Axis_adc_data_packer_v1_0
+
+# Sourcing design address info tcl
+set bd_path [get_property DIRECTORY [current_project]]/[current_project].srcs/[current_fileset]/bd
+source ${bd_path}/Axis_adc_data_packer_v1_0_include.tcl
+
+# jtag axi master interface hardware name, change as per your design.
+set jtag_axi_master hw_axi_1
+set ec 0
+
+# hw test script
+# Delete all previous axis transactions
+if { [llength [get_hw_axi_txns -quiet]] } {
+	delete_hw_axi_txn [get_hw_axi_txns -quiet]
+}
+
+
+# Test all lite slaves.
+set wdata_1 abcd1234
+
+# Test: S00_AXI
+# Create a write transaction at s00_axi_addr address
+create_hw_axi_txn w_s00_axi_addr [get_hw_axis $jtag_axi_master] -type write -address $s00_axi_addr -data $wdata_1
+# Create a read transaction at s00_axi_addr address
+create_hw_axi_txn r_s00_axi_addr [get_hw_axis $jtag_axi_master] -type read -address $s00_axi_addr
+# Initiate transactions
+run_hw_axi r_s00_axi_addr
+run_hw_axi w_s00_axi_addr
+run_hw_axi r_s00_axi_addr
+set rdata_tmp [get_property DATA [get_hw_axi_txn r_s00_axi_addr]]
+# Compare read data
+if { $rdata_tmp == $wdata_1 } {
+	puts "Data comparison test pass for - S00_AXI"
+} else {
+	puts "Data comparison test fail for - S00_AXI, expected-$wdata_1 actual-$rdata_tmp"
+	inc ec
+}
+
+# Check error flag
+if { $ec == 0 } {
+	 puts "PTGEN_TEST: PASSED!" 
+} else {
+	 puts "PTGEN_TEST: FAILED!" 
+}
+

cx9261a_demo_cmos_20240829/ip_repo/Axis_adc_data_packer_1.0/example_designs/debug_hw_design/design.tcl

@@ -0,0 +1,118 @@
+
+proc create_ipi_design { offsetfile design_name } {
+
+	create_bd_design $design_name
+	open_bd_design $design_name
+
+	# Create and configure Clock/Reset
+	create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz sys_clk_0
+	create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset sys_reset_0
+
+	#Constraints will be provided manually while pin planning.
+		create_bd_port -dir I -type rst reset_rtl
+		set_property CONFIG.POLARITY [get_property CONFIG.POLARITY [get_bd_pins sys_clk_0/reset]] [get_bd_ports reset_rtl]
+		connect_bd_net [get_bd_pins sys_reset_0/ext_reset_in] [get_bd_ports reset_rtl]
+		connect_bd_net [get_bd_ports reset_rtl] [get_bd_pins sys_clk_0/reset]
+		set external_reset_port reset_rtl
+		create_bd_port -dir I -type clk clock_rtl
+		connect_bd_net [get_bd_pins sys_clk_0/clk_in1] [get_bd_ports clock_rtl]
+		set external_clock_port clock_rtl
+	
+	#Avoid IPI DRC, make clock port synchronous to reset
+	if { $external_clock_port ne "" && $external_reset_port ne "" } {
+		set_property CONFIG.ASSOCIATED_RESET $external_reset_port [get_bd_ports $external_clock_port]
+	}
+
+	# Connect other sys_reset pins
+	connect_bd_net [get_bd_pins sys_reset_0/slowest_sync_clk] [get_bd_pins sys_clk_0/clk_out1]
+	connect_bd_net [get_bd_pins sys_clk_0/locked] [get_bd_pins sys_reset_0/dcm_locked]
+
+	# Create instance: Axis_adc_data_packer_0, and set properties
+	set Axis_adc_data_packer_0 [ create_bd_cell -type ip -vlnv labnet.com:user:Axis_adc_data_packer:1.0 Axis_adc_data_packer_0 ]
+
+	# Create instance: jtag_axi_0, and set properties
+	set jtag_axi_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:jtag_axi jtag_axi_0 ]
+	set_property -dict [list CONFIG.PROTOCOL {0}] [get_bd_cells jtag_axi_0]
+	connect_bd_net [get_bd_pins jtag_axi_0/aclk] [get_bd_pins sys_clk_0/clk_out1]
+	connect_bd_net [get_bd_pins jtag_axi_0/aresetn] [get_bd_pins sys_reset_0/peripheral_aresetn]
+
+	# Create instance: axi_peri_interconnect, and set properties
+	set axi_peri_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect axi_peri_interconnect ]
+	connect_bd_net [get_bd_pins axi_peri_interconnect/ACLK] [get_bd_pins sys_clk_0/clk_out1]
+	connect_bd_net [get_bd_pins axi_peri_interconnect/ARESETN] [get_bd_pins sys_reset_0/interconnect_aresetn]
+	set_property -dict [ list CONFIG.NUM_SI {1}  ] $axi_peri_interconnect
+	connect_bd_net [get_bd_pins axi_peri_interconnect/S00_ACLK] [get_bd_pins sys_clk_0/clk_out1]
+	connect_bd_net [get_bd_pins axi_peri_interconnect/S00_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn]
+	connect_bd_intf_net [get_bd_intf_pins jtag_axi_0/M_AXI] [get_bd_intf_pins axi_peri_interconnect/S00_AXI]
+
+	set_property -dict [ list CONFIG.NUM_MI {1} ] $axi_peri_interconnect
+	connect_bd_net [get_bd_pins axi_peri_interconnect/M00_ACLK] [get_bd_pins sys_clk_0/clk_out1]
+	connect_bd_net [get_bd_pins axi_peri_interconnect/M00_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn]
+
+	# Connect all clock & reset of Axis_adc_data_packer_0 slave interfaces..
+	connect_bd_intf_net [get_bd_intf_pins axi_peri_interconnect/M00_AXI] [get_bd_intf_pins Axis_adc_data_packer_0/S00_AXI]
+	connect_bd_net [get_bd_pins Axis_adc_data_packer_0/s00_axi_aclk] [get_bd_pins sys_clk_0/clk_out1]
+	connect_bd_net [get_bd_pins Axis_adc_data_packer_0/s00_axi_aresetn] [get_bd_pins sys_reset_0/peripheral_aresetn]
+
+
+	# Auto assign address
+	assign_bd_address
+
+	# Copy all address to Axis_adc_data_packer_v1_0_include.tcl file
+	set bd_path [get_property DIRECTORY [current_project]]/[current_project].srcs/[current_fileset]/bd
+	upvar 1 $offsetfile offset_file
+	set offset_file "${bd_path}/Axis_adc_data_packer_v1_0_include.tcl"
+	set fp [open $offset_file "w"]
+	puts $fp "# Configuration address parameters"
+
+	set offset [get_property OFFSET [get_bd_addr_segs /jtag_axi_0/Data/SEG_Axis_adc_data_packer_0_S00_AXI_* ]]
+	puts $fp "set s00_axi_addr ${offset}"
+
+	close $fp
+}
+
+# Set IP Repository and Update IP Catalogue 
+set ip_path [file dirname [file normalize [get_property XML_FILE_NAME [ipx::get_cores labnet.com:user:Axis_adc_data_packer:1.0]]]]
+set hw_test_file ${ip_path}/example_designs/debug_hw_design/Axis_adc_data_packer_v1_0_hw_test.tcl
+
+set repo_paths [get_property ip_repo_paths [current_fileset]] 
+if { [lsearch -exact -nocase $repo_paths $ip_path ] == -1 } {
+	set_property ip_repo_paths "$ip_path [get_property ip_repo_paths [current_fileset]]" [current_fileset]
+	update_ip_catalog
+}
+
+set design_name ""
+set all_bd {}
+set all_bd_files [get_files *.bd -quiet]
+foreach file $all_bd_files {
+set file_name [string range $file [expr {[string last "/" $file] + 1}] end]
+set bd_name [string range $file_name 0 [expr {[string last "." $file_name] -1}]]
+lappend all_bd $bd_name
+}
+
+for { set i 1 } { 1 } { incr i } {
+	set design_name "Axis_adc_data_packer_v1_0_hw_${i}"
+	if { [lsearch -exact -nocase $all_bd $design_name ] == -1 } {
+		break
+	}
+}
+
+set intf_address_include_file ""
+create_ipi_design intf_address_include_file ${design_name}
+save_bd_design
+validate_bd_design
+
+set wrapper_file [make_wrapper -files [get_files ${design_name}.bd] -top -force]
+import_files -force -norecurse $wrapper_file
+
+puts "-------------------------------------------------------------------------------------------------"
+puts "INFO NEXT STEPS : Until this stage, debug hardware design has been created, "
+puts "   please perform following steps to test design in targeted board."
+puts "1. Generate bitstream"
+puts "2. Setup your targeted board, open hardware manager and open new(or existing) hardware target"
+puts "3. Download generated bitstream"
+puts "4. Run generated hardware test using below command, this invokes basic read/write operation"
+puts "   to every interface present in the peripheral : xilinx.com:user:myip:1.0"
+puts "   : source -notrace ${hw_test_file}"
+puts "-------------------------------------------------------------------------------------------------"
+

cx9261a_demo_cmos_20240829/ip_repo/Axis_adc_data_packer_1.0/hdl/Axis_adc_data_packer_v1_0.v

@@ -0,0 +1,98 @@
+`timescale 1 ns / 1 ps
+
+	module Axis_adc_data_packer_v1_0 #
+	(
+		// Users to add parameters here
+
+		// User parameters ends
+		// Do not modify the parameters beyond this line
+
+
+		// Parameters of Axi Slave Bus Interface S00_AXI
+		parameter integer C_S00_AXI_DATA_WIDTH	= 32,
+		parameter integer C_S00_AXI_ADDR_WIDTH	= 4
+	)
+	(
+		// Users to add ports here
+    input wire aclk,		
+    input wire aresetn,
+    input wire  axis_tvalid,
+    input wire axis_tlast,
+    output wire axis_ready,
+    input  wire [63:0] axis_tdata,
+      
+    output wire m_axis_tvalid,
+    output wire m_axis_tlast,
+    input wire m_axis_ready,
+    output wire [63:0] m_axis_tdata,
+		// User ports ends
+		
+		// Do not modify the ports beyond this line
+
+
+		// Ports of Axi Slave Bus Interface S00_AXI
+		input wire  s00_axi_aclk,
+		input wire  s00_axi_aresetn,
+		input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
+		input wire [2 : 0] s00_axi_awprot,
+		input wire  s00_axi_awvalid,
+		output wire  s00_axi_awready,
+		input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
+		input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
+		input wire  s00_axi_wvalid,
+		output wire  s00_axi_wready,
+		output wire [1 : 0] s00_axi_bresp,
+		output wire  s00_axi_bvalid,
+		input wire  s00_axi_bready,
+		input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
+		input wire [2 : 0] s00_axi_arprot,
+		input wire  s00_axi_arvalid,
+		output wire  s00_axi_arready,
+		output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
+		output wire [1 : 0] s00_axi_rresp,
+		output wire  s00_axi_rvalid,
+		input wire  s00_axi_rready
+	);
+// Instantiation of Axi Bus Interface S00_AXI
+	Axis_adc_data_packer_v1_0_S00_AXI # ( 
+		.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
+		.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
+	) Axis_adc_data_packer_v1_0_S00_AXI_inst (
+		.S_AXI_ACLK(s00_axi_aclk),
+		.S_AXI_ARESETN(s00_axi_aresetn),
+		.S_AXI_AWADDR(s00_axi_awaddr),
+		.S_AXI_AWPROT(s00_axi_awprot),
+		.S_AXI_AWVALID(s00_axi_awvalid),
+		.S_AXI_AWREADY(s00_axi_awready),
+		.S_AXI_WDATA(s00_axi_wdata),
+		.S_AXI_WSTRB(s00_axi_wstrb),
+		.S_AXI_WVALID(s00_axi_wvalid),
+		.S_AXI_WREADY(s00_axi_wready),
+		.S_AXI_BRESP(s00_axi_bresp),
+		.S_AXI_BVALID(s00_axi_bvalid),
+		.S_AXI_BREADY(s00_axi_bready),
+		.S_AXI_ARADDR(s00_axi_araddr),
+		.S_AXI_ARPROT(s00_axi_arprot),
+		.S_AXI_ARVALID(s00_axi_arvalid),
+		.S_AXI_ARREADY(s00_axi_arready),
+		.S_AXI_RDATA(s00_axi_rdata),
+		.S_AXI_RRESP(s00_axi_rresp),
+		.S_AXI_RVALID(s00_axi_rvalid),
+		.S_AXI_RREADY(s00_axi_rready),
+    .axis_tvalid(axis_tvalid),
+    .axis_ready(axis_ready),
+    .axis_tdata(axis_tdata),
+    
+    .aclk(aclk),
+    .aresetn(aresetn),
+    .m_axis_tvalid(m_axis_tvalid),
+    .m_axis_tlast(m_axis_tlast),
+    .m_axis_ready(m_axis_ready),
+    .m_axis_tdata(m_axis_tdata)   
+	);
+
+	// Add user logic here
+
+	// User logic ends
+
+	endmodule

cx9261a_demo_cmos_20240829/ip_repo/Axis_adc_data_packer_1.0/hdl/Axis_adc_data_packer_v1_0_S00_AXI.v

@@ -0,0 +1,469 @@
+`timescale 1 ns / 1 ps
+
+	module Axis_adc_data_packer_v1_0_S00_AXI #
+	(
+		// Users to add parameters here
+
+		// User parameters ends
+		// Do not modify the parameters beyond this line
+
+		// Width of S_AXI data bus
+		parameter integer C_S_AXI_DATA_WIDTH	= 32,
+		// Width of S_AXI address bus
+		parameter integer C_S_AXI_ADDR_WIDTH	= 4
+	)
+	(
+		// Users to add ports here
+	input wire aclk,
+    input wire aresetn,
+    input wire axis_tvalid,
+    output wire  axis_ready,
+    input wire [63:0] axis_tdata,
+      
+    output wire m_axis_tvalid,
+    output wire m_axis_tlast,
+    input wire m_axis_ready,
+    output wire [63:0] m_axis_tdata,
+
+		// User ports ends
+		// Do not modify the ports beyond this line
+
+		// Global Clock Signal
+		input wire  S_AXI_ACLK,
+		// Global Reset Signal. This Signal is Active LOW
+		input wire  S_AXI_ARESETN,
+		// Write address (issued by master, acceped by Slave)
+		input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
+		// Write channel Protection type. This signal indicates the
+    		// privilege and security level of the transaction, and whether
+    		// the transaction is a data access or an instruction access.
+		input wire [2 : 0] S_AXI_AWPROT,
+		// Write address valid. This signal indicates that the master signaling
+    		// valid write address and control information.
+		input wire  S_AXI_AWVALID,
+		// Write address ready. This signal indicates that the slave is ready
+    		// to accept an address and associated control signals.
+		output wire  S_AXI_AWREADY,
+		// Write data (issued by master, acceped by Slave) 
+		input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
+		// Write strobes. This signal indicates which byte lanes hold
+    		// valid data. There is one write strobe bit for each eight
+    		// bits of the write data bus.    
+		input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
+		// Write valid. This signal indicates that valid write
+    		// data and strobes are available.
+		input wire  S_AXI_WVALID,
+		// Write ready. This signal indicates that the slave
+    		// can accept the write data.
+		output wire  S_AXI_WREADY,
+		// Write response. This signal indicates the status
+    		// of the write transaction.
+		output wire [1 : 0] S_AXI_BRESP,
+		// Write response valid. This signal indicates that the channel
+    		// is signaling a valid write response.
+		output wire  S_AXI_BVALID,
+		// Response ready. This signal indicates that the master
+    		// can accept a write response.
+		input wire  S_AXI_BREADY,
+		// Read address (issued by master, acceped by Slave)
+		input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
+		// Protection type. This signal indicates the privilege
+    		// and security level of the transaction, and whether the
+    		// transaction is a data access or an instruction access.
+		input wire [2 : 0] S_AXI_ARPROT,
+		// Read address valid. This signal indicates that the channel
+    		// is signaling valid read address and control information.
+		input wire  S_AXI_ARVALID,
+		// Read address ready. This signal indicates that the slave is
+    		// ready to accept an address and associated control signals.
+		output wire  S_AXI_ARREADY,
+		// Read data (issued by slave)
+		output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
+		// Read response. This signal indicates the status of the
+    		// read transfer.
+		output wire [1 : 0] S_AXI_RRESP,
+		// Read valid. This signal indicates that the channel is
+    		// signaling the required read data.
+		output wire  S_AXI_RVALID,
+		// Read ready. This signal indicates that the master can
+    		// accept the read data and response information.
+		input wire  S_AXI_RREADY
+	);
+
+	// AXI4LITE signals
+	reg [C_S_AXI_ADDR_WIDTH-1 : 0] 	axi_awaddr;
+	reg  	axi_awready;
+	reg  	axi_wready;
+	reg [1 : 0] 	axi_bresp;
+	reg  	axi_bvalid;
+	reg [C_S_AXI_ADDR_WIDTH-1 : 0] 	axi_araddr;
+	reg  	axi_arready;
+	reg [C_S_AXI_DATA_WIDTH-1 : 0] 	axi_rdata;
+	reg [1 : 0] 	axi_rresp;
+	reg  	axi_rvalid;
+
+	// Example-specific design signals
+	// local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
+	// ADDR_LSB is used for addressing 32/64 bit registers/memories
+	// ADDR_LSB = 2 for 32 bits (n downto 2)
+	// ADDR_LSB = 3 for 64 bits (n downto 3)
+	localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1;
+	localparam integer OPT_MEM_ADDR_BITS = 1;
+	//----------------------------------------------
+	//-- Signals for user logic register space example
+	//------------------------------------------------
+	//-- Number of Slave Registers 4
+	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg0;
+	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg1;
+	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg2;
+	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg3;
+	wire	 slv_reg_rden;
+	wire	 slv_reg_wren;
+	reg [C_S_AXI_DATA_WIDTH-1:0]	 reg_data_out;
+	integer	 byte_index;
+	reg	 aw_en;
+
+	// I/O Connections assignments
+
+	assign S_AXI_AWREADY	= axi_awready;
+	assign S_AXI_WREADY	= axi_wready;
+	assign S_AXI_BRESP	= axi_bresp;
+	assign S_AXI_BVALID	= axi_bvalid;
+	assign S_AXI_ARREADY	= axi_arready;
+	assign S_AXI_RDATA	= axi_rdata;
+	assign S_AXI_RRESP	= axi_rresp;
+	assign S_AXI_RVALID	= axi_rvalid;
+	// Implement axi_awready generation
+	// axi_awready is asserted for one S_AXI_ACLK clock cycle when both
+	// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
+	// de-asserted when reset is low.
+
+	always @( posedge S_AXI_ACLK )
+	begin
+	  if ( S_AXI_ARESETN == 1'b0 )
+	    begin
+	      axi_awready <= 1'b0;
+	      aw_en <= 1'b1;
+	    end 
+	  else
+	    begin    
+	      if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
+	        begin
+	          // slave is ready to accept write address when 
+	          // there is a valid write address and write data
+	          // on the write address and data bus. This design 
+	          // expects no outstanding transactions. 
+	          axi_awready <= 1'b1;
+	          aw_en <= 1'b0;
+	        end
+	        else if (S_AXI_BREADY && axi_bvalid)
+	            begin
+	              aw_en <= 1'b1;
+	              axi_awready <= 1'b0;
+	            end
+	      else           
+	        begin
+	          axi_awready <= 1'b0;
+	        end
+	    end 
+	end       
+
+	// Implement axi_awaddr latching
+	// This process is used to latch the address when both 
+	// S_AXI_AWVALID and S_AXI_WVALID are valid. 
+
+	always @( posedge S_AXI_ACLK )
+	begin
+	  if ( S_AXI_ARESETN == 1'b0 )
+	    begin
+	      axi_awaddr <= 0;
+	    end 
+	  else
+	    begin    
+	      if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
+	        begin
+	          // Write Address latching 
+	          axi_awaddr <= S_AXI_AWADDR;
+	        end
+	    end 
+	end       
+
+	// Implement axi_wready generation
+	// axi_wready is asserted for one S_AXI_ACLK clock cycle when both
+	// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is 
+	// de-asserted when reset is low. 
+
+	always @( posedge S_AXI_ACLK )
+	begin
+	  if ( S_AXI_ARESETN == 1'b0 )
+	    begin
+	      axi_wready <= 1'b0;
+	    end 
+	  else
+	    begin    
+	      if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID && aw_en )
+	        begin
+	          // slave is ready to accept write data when 
+	          // there is a valid write address and write data
+	          // on the write address and data bus. This design 
+	          // expects no outstanding transactions. 
+	          axi_wready <= 1'b1;
+	        end
+	      else
+	        begin
+	          axi_wready <= 1'b0;
+	        end
+	    end 
+	end       
+
+	// Implement memory mapped register select and write logic generation
+	// The write data is accepted and written to memory mapped registers when
+	// axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
+	// select byte enables of slave registers while writing.
+	// These registers are cleared when reset (active low) is applied.
+	// Slave register write enable is asserted when valid address and data are available
+	// and the slave is ready to accept the write address and write data.
+	assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;
+
+	always @( posedge S_AXI_ACLK )
+	begin
+	  if ( S_AXI_ARESETN == 1'b0 )
+	    begin
+	      slv_reg0 <= 0;
+	      slv_reg1 <= 0;
+	      slv_reg2 <= 0;
+	      slv_reg3 <= 0;
+	    end 
+	  else begin
+	    if (slv_reg_wren)
+	      begin
+	        case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
+	          2'h0:
+	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
+	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
+	                // Respective byte enables are asserted as per write strobes 
+	                // Slave register 0
+	                slv_reg0[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
+	              end  
+	          2'h1:
+	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
+	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
+	                // Respective byte enables are asserted as per write strobes 
+	                // Slave register 1
+	                slv_reg1[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
+	              end  
+	          2'h2:
+	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
+	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
+	                // Respective byte enables are asserted as per write strobes 
+	                // Slave register 2
+	                slv_reg2[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
+	              end  
+	          2'h3:
+	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
+	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
+	                // Respective byte enables are asserted as per write strobes 
+	                // Slave register 3
+	                slv_reg3[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
+	              end  
+	          default : begin
+	                      slv_reg0 <= slv_reg0;
+	                      slv_reg1 <= slv_reg1;
+	                      slv_reg2 <= slv_reg2;
+	                      slv_reg3 <= slv_reg3;
+	                    end
+	        endcase
+	      end
+	  end
+	end    
+
+	// Implement write response logic generation
+	// The write response and response valid signals are asserted by the slave 
+	// when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.  
+	// This marks the acceptance of address and indicates the status of 
+	// write transaction.
+
+	always @( posedge S_AXI_ACLK )
+	begin
+	  if ( S_AXI_ARESETN == 1'b0 )
+	    begin
+	      axi_bvalid  <= 0;
+	      axi_bresp   <= 2'b0;
+	    end 
+	  else
+	    begin    
+	      if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
+	        begin
+	          // indicates a valid write response is available
+	          axi_bvalid <= 1'b1;
+	          axi_bresp  <= 2'b0; // 'OKAY' response 
+	        end                   // work error responses in future
+	      else
+	        begin
+	          if (S_AXI_BREADY && axi_bvalid) 
+	            //check if bready is asserted while bvalid is high) 
+	            //(there is a possibility that bready is always asserted high)   
+	            begin
+	              axi_bvalid <= 1'b0; 
+	            end  
+	        end
+	    end
+	end   
+
+	// Implement axi_arready generation
+	// axi_arready is asserted for one S_AXI_ACLK clock cycle when
+	// S_AXI_ARVALID is asserted. axi_awready is 
+	// de-asserted when reset (active low) is asserted. 
+	// The read address is also latched when S_AXI_ARVALID is 
+	// asserted. axi_araddr is reset to zero on reset assertion.
+
+	always @( posedge S_AXI_ACLK )
+	begin
+	  if ( S_AXI_ARESETN == 1'b0 )
+	    begin
+	      axi_arready <= 1'b0;
+	      axi_araddr  <= 32'b0;
+	    end 
+	  else
+	    begin    
+	      if (~axi_arready && S_AXI_ARVALID)
+	        begin
+	          // indicates that the slave has acceped the valid read address
+	          axi_arready <= 1'b1;
+	          // Read address latching
+	          axi_araddr  <= S_AXI_ARADDR;
+	        end
+	      else
+	        begin
+	          axi_arready <= 1'b0;
+	        end
+	    end 
+	end       
+
+	// Implement axi_arvalid generation
+	// axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both 
+	// S_AXI_ARVALID and axi_arready are asserted. The slave registers 
+	// data are available on the axi_rdata bus at this instance. The 
+	// assertion of axi_rvalid marks the validity of read data on the 
+	// bus and axi_rresp indicates the status of read transaction.axi_rvalid 
+	// is deasserted on reset (active low). axi_rresp and axi_rdata are 
+	// cleared to zero on reset (active low).  
+	always @( posedge S_AXI_ACLK )
+	begin
+	  if ( S_AXI_ARESETN == 1'b0 )
+	    begin
+	      axi_rvalid <= 0;
+	      axi_rresp  <= 0;
+	    end 
+	  else
+	    begin    
+	      if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
+	        begin
+	          // Valid read data is available at the read data bus
+	          axi_rvalid <= 1'b1;
+	          axi_rresp  <= 2'b0; // 'OKAY' response
+	        end   
+	      else if (axi_rvalid && S_AXI_RREADY)
+	        begin
+	          // Read data is accepted by the master
+	          axi_rvalid <= 1'b0;
+	        end                
+	    end
+	end    
+
+	// Implement memory mapped register select and read logic generation
+	// Slave register read enable is asserted when valid address is available
+	// and the slave is ready to accept the read address.
+	assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
+	always @(*)
+	begin
+	      // Address decoding for reading registers
+	      case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
+	        2'h0   : reg_data_out <= slv_reg0;
+	        2'h1   : reg_data_out <= slv_reg1;
+	        2'h2   : reg_data_out <= slv_reg2;
+	        2'h3   : reg_data_out <= slv_reg3;
+	        default : reg_data_out <= 0;
+	      endcase
+	end
+
+	// Output register or memory read data
+	always @( posedge S_AXI_ACLK )
+	begin
+	  if ( S_AXI_ARESETN == 1'b0 )
+	    begin
+	      axi_rdata  <= 0;
+	    end 
+	  else
+	    begin    
+	      // When there is a valid read address (S_AXI_ARVALID) with 
+	      // acceptance of read address by the slave (axi_arready), 
+	      // output the read dada 
+	      if (slv_reg_rden)
+	        begin
+	          axi_rdata <= reg_data_out;     // register read data
+	        end   
+	    end
+	end    
+	
+	wire capture_cdc;
+	wire [25:0] length_cdc;
+	
+	   xpm_cdc_array_single #(
+      .DEST_SYNC_FF(4),   // DECIMAL; range: 2-10
+      .INIT_SYNC_FF(0),   // DECIMAL; 0=disable simulation init values, 1=enable simulation init values
+      .SIM_ASSERT_CHK(0), // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
+      .SRC_INPUT_REG(1),  // DECIMAL; 0=do not register input, 1=register input
+      .WIDTH(1)           // DECIMAL; range: 1-1024
+   )
+   xpm_cdc_array_single_inst0 (
+      .dest_out(capture_cdc), // WIDTH-bit output: src_in synchronized to the destination clock domain. This
+                           // output is registered.
+
+      .dest_clk(aclk), // 1-bit input: Clock signal for the destination clock domain.
+      .src_clk(S_AXI_ACLK),   // 1-bit input: optional; required when SRC_INPUT_REG = 1
+      .src_in(slv_reg0[0])      // WIDTH-bit input: Input single-bit array to be synchronized to destination clock
+                           // domain. It is assumed that each bit of the array is unrelated to the others. This
+                           // is reflected in the constraints applied to this macro. To transfer a binary value
+                           // losslessly across the two clock domains, use the XPM_CDC_GRAY macro instead.
+
+   );
+   
+   	   xpm_cdc_array_single #(
+      .DEST_SYNC_FF(4),   // DECIMAL; range: 2-10
+      .INIT_SYNC_FF(0),   // DECIMAL; 0=disable simulation init values, 1=enable simulation init values
+      .SIM_ASSERT_CHK(0), // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
+      .SRC_INPUT_REG(1),  // DECIMAL; 0=do not register input, 1=register input
+      .WIDTH(26)           // DECIMAL; range: 1-1024
+   )
+   xpm_cdc_array_single_inst1 (
+      .dest_out(length_cdc), // WIDTH-bit output: src_in synchronized to the destination clock domain. This
+                           // output is registered.
+
+      .dest_clk(aclk), // 1-bit input: Clock signal for the destination clock domain.
+      .src_clk(S_AXI_ACLK),   // 1-bit input: optional; required when SRC_INPUT_REG = 1
+      .src_in(slv_reg1[25:0])      // WIDTH-bit input: Input single-bit array to be synchronized to destination clock
+                           // domain. It is assumed that each bit of the array is unrelated to the others. This
+                           // is reflected in the constraints applied to this macro. To transfer a binary value
+                           // losslessly across the two clock domains, use the XPM_CDC_GRAY macro instead.
+
+   );
+   
+	
+	// Add user logic here
+    axis_adc_data_packer axis_adc_data_packer(
+    .aclk(aclk),
+    .aresetn(aresetn),
+    .axis_tvalid(axis_tvalid),
+    .axis_ready(axis_ready),
+    .axis_tdata(axis_tdata),
+    .capture(capture_cdc),
+    .length(length_cdc),
+    .m_axis_tvalid(m_axis_tvalid),
+    .m_axis_tlast(m_axis_tlast),
+    .m_axis_ready(m_axis_ready),
+    .m_axis_tdata(m_axis_tdata)     
+    );
+	// User logic ends
+
+	endmodule

cx9261a_demo_cmos_20240829/ip_repo/Axis_adc_data_packer_1.0/hdl/axis_adc_data_packer.v

@@ -0,0 +1,104 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2021/09/07 14:33:53
+// Design Name: 
+// Module Name: axis_adc_data_packer
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module axis_adc_data_packer(
+aclk,aresetn,axis_tvalid,axis_ready,axis_tdata,
+capture,length,
+m_axis_tvalid,m_axis_tlast,m_axis_ready,m_axis_tdata
+    );
+    input wire aclk;
+    input wire aresetn;
+    input wire axis_tvalid;
+    output reg axis_ready;
+    input wire [63:0] axis_tdata;
+    
+    input capture;
+    input [25:0] length; 
+   
+    output reg m_axis_tvalid;
+    output reg m_axis_tlast;
+    input wire m_axis_ready;
+    output reg [63:0] m_axis_tdata;
+    
+    reg [7:0]capture_d;
+    always@(posedge aclk)begin
+        if(~aresetn)begin
+            capture_d<='d0;
+        end
+        begin
+            capture_d<={capture_d[6:0],capture};
+        end
+    end
+    
+       (* keep="true" *)reg [25:0] cnt;
+       (* keep="true" *)reg [7:0] state;
+    always@(posedge aclk)begin
+        if(~aresetn)begin
+            cnt<='d0;
+            axis_ready<='d0;
+            m_axis_tvalid<='d0;
+            m_axis_tlast<='d0;
+            m_axis_tdata<='d0;      
+            state  <='d0;   
+        end
+        else begin
+            case(state)
+            0:begin
+            m_axis_tlast<=1'b0;
+            m_axis_tvalid<=1'b0;
+			m_axis_tdata<=m_axis_tdata;
+			cnt<='d0;
+                if(capture_d == 8'b01111111)begin
+                    state<=1;
+                end
+				else state<=0;
+            end
+            1:begin
+              if(axis_tvalid)begin
+                m_axis_tdata<=axis_tdata;
+                m_axis_tvalid<=axis_tvalid;
+                if(cnt >= (length-1))begin
+                    cnt<='d0;
+                    state<='d0;
+                    m_axis_tlast<=1'b1;
+                end
+                else begin
+                    cnt<=cnt+1'b1;
+                    m_axis_tlast<=1'b0;
+                end
+              end
+              else begin
+                m_axis_tdata<=m_axis_tdata;
+                m_axis_tvalid<=1'b0;
+                m_axis_tlast<=1'b0;              
+              end  
+            end
+			default:begin
+				state<='d0;
+			end
+            endcase
+        
+        
+        end
+        
+    end     
+    endmodule

cx9261a_demo_cmos_20240829/ip_repo/Axis_adc_data_packer_1.0/xgui/Axis_adc_data_packer_v1_0.tcl

@@ -0,0 +1,62 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+  ipgui::add_param $IPINST -name "Component_Name"
+  #Adding Page
+  set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
+  set C_S00_AXI_DATA_WIDTH [ipgui::add_param $IPINST -name "C_S00_AXI_DATA_WIDTH" -parent ${Page_0} -widget comboBox]
+  set_property tooltip {Width of S_AXI data bus} ${C_S00_AXI_DATA_WIDTH}
+  set C_S00_AXI_ADDR_WIDTH [ipgui::add_param $IPINST -name "C_S00_AXI_ADDR_WIDTH" -parent ${Page_0}]
+  set_property tooltip {Width of S_AXI address bus} ${C_S00_AXI_ADDR_WIDTH}
+  ipgui::add_param $IPINST -name "C_S00_AXI_BASEADDR" -parent ${Page_0}
+  ipgui::add_param $IPINST -name "C_S00_AXI_HIGHADDR" -parent ${Page_0}
+
+
+}
+
+proc update_PARAM_VALUE.C_S00_AXI_DATA_WIDTH { PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
+	# Procedure called to update C_S00_AXI_DATA_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_S00_AXI_DATA_WIDTH { PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
+	# Procedure called to validate C_S00_AXI_DATA_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_S00_AXI_ADDR_WIDTH { PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
+	# Procedure called to update C_S00_AXI_ADDR_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_S00_AXI_ADDR_WIDTH { PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
+	# Procedure called to validate C_S00_AXI_ADDR_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_S00_AXI_BASEADDR { PARAM_VALUE.C_S00_AXI_BASEADDR } {
+	# Procedure called to update C_S00_AXI_BASEADDR when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_S00_AXI_BASEADDR { PARAM_VALUE.C_S00_AXI_BASEADDR } {
+	# Procedure called to validate C_S00_AXI_BASEADDR
+	return true
+}
+
+proc update_PARAM_VALUE.C_S00_AXI_HIGHADDR { PARAM_VALUE.C_S00_AXI_HIGHADDR } {
+	# Procedure called to update C_S00_AXI_HIGHADDR when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_S00_AXI_HIGHADDR { PARAM_VALUE.C_S00_AXI_HIGHADDR } {
+	# Procedure called to validate C_S00_AXI_HIGHADDR
+	return true
+}
+
+
+proc update_MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH { MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH { MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH}
+}
+

cx9261a_demo_cmos_20240829/ip_repo/edit_Axis_adc_data_packer_v1_0.cache/wt/gui_handlers.wdf

@@ -0,0 +1,40 @@
+version:1
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:616273747261637473656172636861626c6570616e656c5f73686f775f736561726368:32:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f63616e63656c:3234:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:3236:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f6e73747261696e747363686f6f73657270616e656c5f6372656174655f66696c65:31:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f6e73747261696e747363686f6f73657270616e656c5f66696c655f7461626c65:31:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:637265617465636f6e73747261696e747366696c6570616e656c5f66696c655f6e616d65:31:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:65646974696e746572666163656469616c6f675f7461626265645f70616e65:3130:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:3235:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:666c6f776e6176696761746f727472656570616e656c5f666c6f775f6e6176696761746f725f74726565:3131:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:68636f6465656469746f725f7365617263685f746578745f636f6d626f5f626f78:3132:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:696e74657266616365636f6e66696775726174696f6e70616e656c5f6e616d65:33:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:696e74657266616365646566696e6974696f6e63686f6f7365725f696e746572666163655f646566696e6974696f6e5f63686f6f736572:31:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:696e74657266616365646566696e6974696f6e747265657461626c655f696e74657266616365735f747265655f7461626c65:31:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:696e74657266616365706f72746d617070696e6770616e656c5f696e74657266616365735f6c6f676963616c5f706f727473:34:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:696e74657266616365706f72746d617070696e6770616e656c5f6970735f706879736963616c5f706f727473:33:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:696e74657266616365706f72746d617070696e6770616e656c5f6d61705f706f727473:31:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6c616e677561676574656d706c617465736469616c6f675f74656d706c617465735f74726565:36:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d65737361676562616e6e65725f6368616e6765735f64657465637465645f696e5f69705f746861745f72657175697265:31:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d65737361676562616e6e65725f6368616e6765735f64657465637465645f696e5f76697661646f5f70726f6a6563745f74686174:34:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d73677472656570616e656c5f6d6573736167655f766965775f74726565:37:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d7367766965775f636c6561725f6d657373616765735f726573756c74696e675f66726f6d5f757365725f6578656375746564:31:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6e65746c69737474726565766965775f6e65746c6973745f74726565:3132:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f676f746f5f6e65746c6973745f64657369676e:31:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f7061636b616765725f6164645f6275735f696e74657266616365:32:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f7061636b616765:31:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f7061636b6167655f6970:32:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f70726f6a6563745f73756d6d617279:32:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f736368656d61746963:32:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636b6167657273746570636f6e74656e7470616e656c5f6d65737361676573:35:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636b61676572737465707370616e656c5f7061636b616765725f73746570735f6c697374:3334:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706f7274616e64696e74657266616365636f6e74656e7470616e656c5f72656672657368:3231:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706f7274616e64696e7465726661636566616365747461626c655f6173736f63696174655f636c6f636b73:3433:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706f7274616e64696e7465726661636566616365747461626c655f656469745f696e74657266616365:33:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706f7274616e64696e7465726661636566616365747461626c655f706f72745f616e645f696e746572666163655f66616365745f7461626c65:323138:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706f7274616e64696e7465726661636566616365747461626c655f72656d6f76655f696e74657266616365:31:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:726576696577636f6e74656e7470616e656c5f656469745f7061636b6167696e675f73657474696e6773:31:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:726576696577636f6e74656e7470616e656c5f72655f7061636b6167655f6970:32:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7361766570726f6a6563747574696c735f646f6e745f73617665:31:00:00
+eof:2254748156

cx9261a_demo_cmos_20240829/ip_repo/edit_Axis_adc_data_packer_v1_0.cache/wt/java_command_handlers.wdf

@@ -0,0 +1,15 @@
+version:1
+70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:616464627573696e7465726661636568616e646c6572:32:00:00
+70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:65646974756e646f:37:00:00
+70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:666c6970746f766965777461736b73796e746865736973:31:00:00
+70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:69707061636b6167657268616e646c6572:36:00:00
+70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7265706f7274636c6f636b696e746572616374696f6e:31:00:00
+70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e736368656d61746963:37:00:00
+70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e73796e746865736973:32:00:00
+70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7361766566696c6570726f787968616e646c6572:31:00:00
+70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:74696d696e67636f6e73747261696e747377697a617264:31:00:00
+70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:746f6f6c7373657474696e6773:31:00:00
+70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:746f6f6c7374656d706c61746573:32:00:00
+70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:766965777461736b70726f6a6563746d616e61676572:31:00:00
+70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:766965777461736b73796e746865736973:31:00:00
+eof:944012437

cx9261a_demo_cmos_20240829/ip_repo/edit_Axis_adc_data_packer_v1_0.cache/wt/project.wpc

@@ -0,0 +1,3 @@
+version:1
+6d6f64655f636f756e7465727c4755494d6f6465:8
+eof:

cx9261a_demo_cmos_20240829/ip_repo/edit_Axis_adc_data_packer_v1_0.cache/wt/synthesis.wdf

@@ -0,0 +1,39 @@
+version:1
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:78637a753765762d66667663313135362d322d65:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e616d65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:417869735f6164635f646174615f7061636b65725f76315f30:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d696e636c7564655f64697273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67656e65726963:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d766572696c6f675f646566696e65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636f6e737472736574:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7365755f70726f74656374:64656661756c743a3a6e6f6e65:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d666c617474656e5f686965726172636879:64656661756c743a3a72656275696c74:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67617465645f636c6f636b5f636f6e76657273696f6e:64656661756c743a3a6f6666:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d646972656374697665:64656661756c743a3a64656661756c74:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c5f736b69705f6970:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c5f736b69705f636f6e73747261696e7473:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f6c63:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d62756667:64656661756c743a3a3132:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d66616e6f75745f6c696d6974:64656661756c743a3a3130303030:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73687265675f6d696e5f73697a65:64656661756c743a3a33:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d6f6465:64656661756c743a3a64656661756c74:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d66736d5f65787472616374696f6e:64656661756c743a3a6175746f:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6b6565705f6571756976616c656e745f726567697374657273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7265736f757263655f73686172696e67:64656661756c743a3a6175746f:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636173636164655f647370:64656661756c743a3a6175746f:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636f6e74726f6c5f7365745f6f70745f7468726573686f6c64:64656661756c743a3a6175746f:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f6272616d:64656661756c743a3a2d31:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f7572616d:64656661756c743a3a2d31:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f647370:64656661756c743a3a2d31:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f6272616d5f636173636164655f686569676874:64656661756c743a3a2d31:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f7572616d5f636173636164655f686569676874:64656661756c743a3a2d31:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d726574696d696e67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f73726c65787472616374:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d617373657274:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a323473:00:00
+73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:323030372e3634314d42:00:00
+73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:313635372e3438304d42:00:00
+eof:974587738

cx9261a_demo_cmos_20240829/ip_repo/edit_Axis_adc_data_packer_v1_0.cache/wt/synthesis_details.wdf

@@ -0,0 +1,3 @@
+version:1
+73796e746865736973:73796e7468657369735c7573616765:686c735f6970:30:00:00
+eof:2511430288

cx9261a_demo_cmos_20240829/ip_repo/edit_Axis_adc_data_packer_v1_0.cache/wt/webtalk_pa.xml

@@ -0,0 +1,81 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<document>
+<!--The data in this file is primarily intended for consumption by Xilinx tools.
+The structure and the elements are likely to change over the next few releases.
+This means code written to parse this file will need to be revisited each subsequent release.-->
+<application name="pa" timeStamp="Fri Dec 24 10:35:31 2021">
+<section name="Project Information" visible="false">
+<property name="ProjectID" value="8b6833958267472dad005008c4feb711" type="ProjectID"/>
+<property name="ProjectIteration" value="1" type="ProjectIteration"/>
+</section>
+<section name="PlanAhead Usage" visible="true">
+<item name="Project Data">
+<property name="SrcSetCount" value="1" type="SrcSetCount"/>
+<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
+<property name="DesignMode" value="RTL" type="DesignMode"/>
+<property name="SynthesisStrategy" value="Vivado Synthesis Defaults" type="SynthesisStrategy"/>
+<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
+</item>
+<item name="Java Command Handlers">
+<property name="AddBusInterfaceHandler" value="2" type="JavaHandler"/>
+<property name="EditUndo" value="7" type="JavaHandler"/>
+<property name="FlipToViewTaskSynthesis" value="1" type="JavaHandler"/>
+<property name="IPPackagerHandler" value="6" type="JavaHandler"/>
+<property name="ReportClockInteraction" value="1" type="JavaHandler"/>
+<property name="RunSchematic" value="7" type="JavaHandler"/>
+<property name="RunSynthesis" value="2" type="JavaHandler"/>
+<property name="SaveFileProxyHandler" value="1" type="JavaHandler"/>
+<property name="TimingConstraintsWizard" value="1" type="JavaHandler"/>
+<property name="ToolsSettings" value="1" type="JavaHandler"/>
+<property name="ToolsTemplates" value="2" type="JavaHandler"/>
+<property name="ViewTaskProjectManager" value="1" type="JavaHandler"/>
+<property name="ViewTaskSynthesis" value="1" type="JavaHandler"/>
+</item>
+<item name="Gui Handlers">
+<property name="AbstractSearchablePanel_SHOW_SEARCH" value="2" type="GuiHandlerData"/>
+<property name="BaseDialog_CANCEL" value="24" type="GuiHandlerData"/>
+<property name="BaseDialog_OK" value="26" type="GuiHandlerData"/>
+<property name="ConstraintsChooserPanel_CREATE_FILE" value="1" type="GuiHandlerData"/>
+<property name="ConstraintsChooserPanel_FILE_TABLE" value="1" type="GuiHandlerData"/>
+<property name="CreateConstraintsFilePanel_FILE_NAME" value="1" type="GuiHandlerData"/>
+<property name="EditInterfaceDialog_TABBED_PANE" value="10" type="GuiHandlerData"/>
+<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="25" type="GuiHandlerData"/>
+<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="11" type="GuiHandlerData"/>
+<property name="HCodeEditor_SEARCH_TEXT_COMBO_BOX" value="12" type="GuiHandlerData"/>
+<property name="InterfaceConfigurationPanel_NAME" value="3" type="GuiHandlerData"/>
+<property name="InterfaceDefinitionChooser_INTERFACE_DEFINITION_CHOOSER" value="1" type="GuiHandlerData"/>
+<property name="InterfaceDefinitionTreeTable_INTERFACES_TREE_TABLE" value="1" type="GuiHandlerData"/>
+<property name="InterfacePortMappingPanel_INTERFACES_LOGICAL_PORTS" value="4" type="GuiHandlerData"/>
+<property name="InterfacePortMappingPanel_IPS_PHYSICAL_PORTS" value="3" type="GuiHandlerData"/>
+<property name="InterfacePortMappingPanel_MAP_PORTS" value="1" type="GuiHandlerData"/>
+<property name="LanguageTemplatesDialog_TEMPLATES_TREE" value="6" type="GuiHandlerData"/>
+<property name="MessageBanner_CHANGES_DETECTED_IN_IP_THAT_REQUIRE" value="1" type="GuiHandlerData"/>
+<property name="MessageBanner_CHANGES_DETECTED_IN_VIVADO_PROJECT_THAT" value="4" type="GuiHandlerData"/>
+<property name="MsgTreePanel_MESSAGE_VIEW_TREE" value="7" type="GuiHandlerData"/>
+<property name="MsgView_CLEAR_MESSAGES_RESULTING_FROM_USER_EXECUTED" value="1" type="GuiHandlerData"/>
+<property name="NetlistTreeView_NETLIST_TREE" value="12" type="GuiHandlerData"/>
+<property name="PACommandNames_GOTO_NETLIST_DESIGN" value="1" type="GuiHandlerData"/>
+<property name="PACommandNames_PACKAGER_ADD_BUS_INTERFACE" value="2" type="GuiHandlerData"/>
+<property name="PAViews_PACKAGE" value="1" type="GuiHandlerData"/>
+<property name="PAViews_PACKAGE_IP" value="2" type="GuiHandlerData"/>
+<property name="PAViews_PROJECT_SUMMARY" value="2" type="GuiHandlerData"/>
+<property name="PAViews_SCHEMATIC" value="2" type="GuiHandlerData"/>
+<property name="PackagerStepContentPanel_MESSAGES" value="5" type="GuiHandlerData"/>
+<property name="PackagerStepsPanel_PACKAGER_STEPS_LIST" value="34" type="GuiHandlerData"/>
+<property name="PortAndInterfaceContentPanel_REFRESH" value="21" type="GuiHandlerData"/>
+<property name="PortAndInterfaceFacetTable_ASSOCIATE_CLOCKS" value="43" type="GuiHandlerData"/>
+<property name="PortAndInterfaceFacetTable_EDIT_INTERFACE" value="3" type="GuiHandlerData"/>
+<property name="PortAndInterfaceFacetTable_PORT_AND_INTERFACE_FACET_TABLE" value="218" type="GuiHandlerData"/>
+<property name="PortAndInterfaceFacetTable_REMOVE_INTERFACE" value="1" type="GuiHandlerData"/>
+<property name="ReviewContentPanel_EDIT_PACKAGING_SETTINGS" value="1" type="GuiHandlerData"/>
+<property name="ReviewContentPanel_RE_PACKAGE_IP" value="2" type="GuiHandlerData"/>
+<property name="SaveProjectUtils_DONT_SAVE" value="1" type="GuiHandlerData"/>
+</item>
+<item name="Other">
+<property name="GuiMode" value="242" type="GuiMode"/>
+<property name="BatchMode" value="0" type="BatchMode"/>
+<property name="TclMode" value="185" type="TclMode"/>
+</item>
+</section>
+</application>
+</document>

cx9261a_demo_cmos_20240829/ip_repo/edit_Axis_adc_data_packer_v1_0.hw/edit_Axis_adc_data_packer_v1_0.lpr

@@ -0,0 +1,6 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2018.3 (64-bit)                     -->
+<!--                                                              -->
+<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.        -->
+
+<labtools version="1" minor="0"/>

cx9261a_demo_cmos_20240829/ip_repo/edit_Axis_adc_data_packer_v1_0.ip_user_files/README.txt

@@ -0,0 +1 @@
+The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.

cx9261a_demo_cmos_20240829/ip_repo/edit_Axis_adc_data_packer_v1_0.runs/.jobs/vrs_config_1.xml

@@ -0,0 +1,8 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+	<Run Id="synth_1" LaunchDir="C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/edit_Axis_adc_data_packer_v1_0.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+	<Parameters>
+		<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+	</Parameters>
+</Runs>
+

cx9261a_demo_cmos_20240829/ip_repo/edit_Axis_adc_data_packer_v1_0.runs/.jobs/vrs_config_2.xml

@@ -0,0 +1,8 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+	<Run Id="synth_1" LaunchDir="C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/edit_Axis_adc_data_packer_v1_0.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+	<Parameters>
+		<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+	</Parameters>
+</Runs>
+

cx9261a_demo_cmos_20240829/ip_repo/edit_Axis_adc_data_packer_v1_0.runs/synth_1/.vivado.begin.rst

@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+    <Process Command="vivado.bat" Owner="swang" Host="HPZ240A" Pid="8716">
+    </Process>
+</ProcessHandle>

cx9261a_demo_cmos_20240829/ip_repo/edit_Axis_adc_data_packer_v1_0.runs/synth_1/Axis_adc_data_packer_v1_0.tcl

@@ -0,0 +1,67 @@
+# 
+# Synthesis run script generated by Vivado
+# 
+
+set TIME_start [clock seconds] 
+proc create_report { reportName command } {
+  set status "."
+  append status $reportName ".fail"
+  if { [file exists $status] } {
+    eval file delete [glob $status]
+  }
+  send_msg_id runtcl-4 info "Executing : $command"
+  set retval [eval catch { $command } msg]
+  if { $retval != 0 } {
+    set fp [open $status w]
+    close $fp
+    send_msg_id runtcl-5 warning "$msg"
+  }
+}
+set_param power.BramSDPPropagationFix 1
+set_param power.enableUnconnectedCarry8PinPower 1
+set_param power.enableCarry8RouteBelPower 1
+set_param power.enableLutRouteBelPower 1
+set_msg_config -id {HDL-1065} -limit 10000
+create_project -in_memory -part xczu7ev-ffvc1156-2-e
+
+set_param project.singleFileAddWarning.threshold 0
+set_param project.compositeFile.enableAutoGeneration 0
+set_param synth.vivado.isSynthRun true
+set_property webtalk.parent_dir C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/edit_Axis_adc_data_packer_v1_0.cache/wt [current_project]
+set_property parent.project_path C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/edit_Axis_adc_data_packer_v1_0.xpr [current_project]
+set_property XPM_LIBRARIES XPM_CDC [current_project]
+set_property default_lib xil_defaultlib [current_project]
+set_property target_language Verilog [current_project]
+set_property board_part xilinx.com:zcu106:part0:2.3 [current_project]
+set_property ip_repo_paths c:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work [current_project]
+update_ip_catalog
+set_property ip_output_repo c:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/edit_Axis_adc_data_packer_v1_0.cache/ip [current_project]
+set_property ip_cache_permissions {read write} [current_project]
+read_verilog -library "" {
+  C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/Axis_adc_data_packer_v1_0_S00_AXI.v
+  C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/Axis_adc_data_packer_v1_0.v
+}
+read_verilog -library xil_defaultlib C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/axis_adc_data_packer.v
+# Mark all dcp files as not used in implementation to prevent them from being
+# stitched into the results of this synthesis run. Any black boxes in the
+# design are intentionally left as such for best results. Dcp files will be
+# stitched into the design at a later time, either when this synthesis run is
+# opened, or when it is stitched into a dependent implementation run.
+foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
+  set_property used_in_implementation false $dcp
+}
+read_xdc C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/edit_Axis_adc_data_packer_v1_0.srcs/constrs_1/new/constrains.xdc
+set_property used_in_implementation false [get_files C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/edit_Axis_adc_data_packer_v1_0.srcs/constrs_1/new/constrains.xdc]
+
+set_param ips.enableIPCacheLiteLoad 1
+close [open __synthesis_is_running__ w]
+
+synth_design -top Axis_adc_data_packer_v1_0 -part xczu7ev-ffvc1156-2-e
+
+
+# disable binary constraint mode for synth run checkpoints
+set_param constraints.enableBinaryConstraints false
+write_checkpoint -force -noxdef Axis_adc_data_packer_v1_0.dcp
+create_report "synth_1_synth_report_utilization_0" "report_utilization -file Axis_adc_data_packer_v1_0_utilization_synth.rpt -pb Axis_adc_data_packer_v1_0_utilization_synth.pb"
+file delete __synthesis_is_running__
+close [open __synthesis_is_complete__ w]

cx9261a_demo_cmos_20240829/ip_repo/edit_Axis_adc_data_packer_v1_0.runs/synth_1/Axis_adc_data_packer_v1_0.vds

@@ -0,0 +1,410 @@
+#-----------------------------------------------------------
+# Vivado v2018.3 (64-bit)
+# SW Build 2405991 on Thu Dec  6 23:38:27 MST 2018
+# IP Build 2404404 on Fri Dec  7 01:43:56 MST 2018
+# Start of session at: Thu Dec 23 15:59:40 2021
+# Process ID: 9796
+# Current directory: C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/edit_Axis_adc_data_packer_v1_0.runs/synth_1
+# Command line: vivado.exe -log Axis_adc_data_packer_v1_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source Axis_adc_data_packer_v1_0.tcl
+# Log file: C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/edit_Axis_adc_data_packer_v1_0.runs/synth_1/Axis_adc_data_packer_v1_0.vds
+# Journal file: C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/edit_Axis_adc_data_packer_v1_0.runs/synth_1\vivado.jou
+#-----------------------------------------------------------
+source Axis_adc_data_packer_v1_0.tcl -notrace
+INFO: [IP_Flow 19-234] Refreshing IP repositories
+INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work'.
+WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'c:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'c:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/edit_Axis_adc_data_packer_v1_0.runs/synth_1'.)
+INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/xilinx/Vivado/2018.3/data/ip'.
+WARNING: [IP_Flow 19-4995] The host OS only allows 260 characters in a normal path. The IP cache path is more than 80 characters. If you experience issues with IP caching, please consider changing the IP cache to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter. 
+Current IP cache path is c:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/edit_Axis_adc_data_packer_v1_0.cache/ip 
+WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/Axis_adc_data_packer_v1_0_S00_AXI.v:]
+WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/Axis_adc_data_packer_v1_0.v:]
+Command: synth_design -top Axis_adc_data_packer_v1_0 -part xczu7ev-ffvc1156-2-e
+Starting synth_design
+Attempting to get a license for feature 'Synthesis' and/or device 'xczu7ev'
+INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xczu7ev'
+INFO: Launching helper process for spawning children vivado processes
+INFO: Helper process launched with PID 1944 
+---------------------------------------------------------------------------------
+Starting RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 465.340 ; gain = 103.711
+---------------------------------------------------------------------------------
+INFO: [Synth 8-6157] synthesizing module 'Axis_adc_data_packer_v1_0' [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/Axis_adc_data_packer_v1_0.v:3]
+	Parameter C_S00_AXI_DATA_WIDTH bound to: 32 - type: integer 
+	Parameter C_S00_AXI_ADDR_WIDTH bound to: 4 - type: integer 
+INFO: [Synth 8-6157] synthesizing module 'Axis_adc_data_packer_v1_0_S00_AXI' [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/Axis_adc_data_packer_v1_0_S00_AXI.v:3]
+	Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer 
+	Parameter C_S_AXI_ADDR_WIDTH bound to: 4 - type: integer 
+	Parameter ADDR_LSB bound to: 2 - type: integer 
+	Parameter OPT_MEM_ADDR_BITS bound to: 1 - type: integer 
+INFO: [Synth 8-226] default block is never used [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/Axis_adc_data_packer_v1_0_S00_AXI.v:240]
+INFO: [Synth 8-226] default block is never used [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/Axis_adc_data_packer_v1_0_S00_AXI.v:381]
+INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_array_single' [D:/xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:903]
+	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
+	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
+	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
+	Parameter SRC_INPUT_REG bound to: 1 - type: integer 
+	Parameter VERSION bound to: 0 - type: integer 
+	Parameter WIDTH bound to: 1 - type: integer 
+INFO: [Synth 8-5534] Detected attribute (* ASYNC_REG = "TRUE" *) [D:/xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:958]
+INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_array_single' (1#1) [D:/xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:903]
+INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_array_single__parameterized0' [D:/xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:903]
+	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
+	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
+	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
+	Parameter SRC_INPUT_REG bound to: 1 - type: integer 
+	Parameter VERSION bound to: 0 - type: integer 
+	Parameter WIDTH bound to: 26 - type: integer 
+INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_array_single__parameterized0' (1#1) [D:/xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:903]
+INFO: [Synth 8-6157] synthesizing module 'axis_adc_data_packer' [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/axis_adc_data_packer.v:23]
+INFO: [Synth 8-5534] Detected attribute (* keep = "true" *) [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/axis_adc_data_packer.v:52]
+INFO: [Synth 8-5534] Detected attribute (* keep = "true" *) [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/axis_adc_data_packer.v:53]
+INFO: [Synth 8-6155] done synthesizing module 'axis_adc_data_packer' (2#1) [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/axis_adc_data_packer.v:23]
+INFO: [Synth 8-6155] done synthesizing module 'Axis_adc_data_packer_v1_0_S00_AXI' (3#1) [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/Axis_adc_data_packer_v1_0_S00_AXI.v:3]
+INFO: [Synth 8-6155] done synthesizing module 'Axis_adc_data_packer_v1_0' (4#1) [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/Axis_adc_data_packer_v1_0.v:3]
+WARNING: [Synth 8-3331] design axis_adc_data_packer has unconnected port m_axis_ready
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0_S00_AXI has unconnected port S_AXI_AWPROT[2]
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0_S00_AXI has unconnected port S_AXI_AWPROT[1]
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0_S00_AXI has unconnected port S_AXI_AWPROT[0]
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0_S00_AXI has unconnected port S_AXI_ARPROT[2]
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0_S00_AXI has unconnected port S_AXI_ARPROT[1]
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0_S00_AXI has unconnected port S_AXI_ARPROT[0]
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0 has unconnected port axis_tlast
+---------------------------------------------------------------------------------
+Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 515.703 ; gain = 154.074
+---------------------------------------------------------------------------------
+
+Report Check Netlist: 
++------+------------------+-------+---------+-------+------------------+
+|      |Item              |Errors |Warnings |Status |Description       |
++------+------------------+-------+---------+-------+------------------+
+|1     |multi_driven_nets |      0|        0|Passed |Multi driven nets |
++------+------------------+-------+---------+-------+------------------+
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 515.703 ; gain = 154.074
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 515.703 ; gain = 154.074
+---------------------------------------------------------------------------------
+INFO: [Device 21-403] Loading part xczu7ev-ffvc1156-2-e
+INFO: [Project 1-570] Preparing netlist for logic optimization
+
+Processing XDC Constraints
+Initializing timing engine
+Parsing XDC File [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/edit_Axis_adc_data_packer_v1_0.srcs/constrs_1/new/constrains.xdc]
+Finished Parsing XDC File [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/edit_Axis_adc_data_packer_v1_0.srcs/constrs_1/new/constrains.xdc]
+Sourcing Tcl File [D:/xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'Axis_adc_data_packer_v1_0_S00_AXI_inst/xpm_cdc_array_single_inst0'
+Finished Sourcing Tcl File [D:/xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'Axis_adc_data_packer_v1_0_S00_AXI_inst/xpm_cdc_array_single_inst0'
+Sourcing Tcl File [D:/xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'Axis_adc_data_packer_v1_0_S00_AXI_inst/xpm_cdc_array_single_inst1'
+Finished Sourcing Tcl File [D:/xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'Axis_adc_data_packer_v1_0_S00_AXI_inst/xpm_cdc_array_single_inst1'
+INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [D:/xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/Axis_adc_data_packer_v1_0_propImpl.xdc].
+Resolution: To avoid this warning, move constraints listed in [.Xil/Axis_adc_data_packer_v1_0_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1584.711 ; gain = 0.000
+WARNING: [Constraints 18-5210] No constraints selected for write.
+Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
+Completed Processing XDC Constraints
+
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1584.711 ; gain = 0.000
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1584.711 ; gain = 0.000
+Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.007 . Memory (MB): peak = 1584.711 ; gain = 0.000
+---------------------------------------------------------------------------------
+Finished Constraint Validation : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 1584.711 ; gain = 1223.082
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Loading Part and Timing Information
+---------------------------------------------------------------------------------
+Loading part: xczu7ev-ffvc1156-2-e
+INFO: [Synth 8-6742] Reading net delay rules and data
+---------------------------------------------------------------------------------
+Finished Loading Part and Timing Information : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 1584.711 ; gain = 1223.082
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Applying 'set_property' XDC Constraints
+---------------------------------------------------------------------------------
+Applied set_property DONT_TOUCH = true for Axis_adc_data_packer_v1_0_S00_AXI_inst/xpm_cdc_array_single_inst0. (constraint file  auto generated constraint, line ).
+Applied set_property DONT_TOUCH = true for Axis_adc_data_packer_v1_0_S00_AXI_inst/xpm_cdc_array_single_inst1. (constraint file  auto generated constraint, line ).
+---------------------------------------------------------------------------------
+Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 1584.711 ; gain = 1223.082
+---------------------------------------------------------------------------------
+INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'axis_adc_data_packer'
+INFO: [Synth 8-5546] ROM "cnt" won't be mapped to RAM because it is too sparse
+INFO: [Synth 8-5546] ROM "state" won't be mapped to RAM because it is too sparse
+INFO: [Synth 8-6159] Found Keep on FSM register 'state_reg' in module 'axis_adc_data_packer', re-encoding will not be performed
+---------------------------------------------------------------------------------------------------
+                   State |                     New Encoding |                Previous Encoding 
+---------------------------------------------------------------------------------------------------
+*
+                  iSTATE |                         00000000 |                         00000000
+                 iSTATE0 |                         00000001 |                         00000001
+---------------------------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 1584.711 ; gain = 1223.082
+---------------------------------------------------------------------------------
+
+Report RTL Partitions: 
++-+--------------+------------+----------+
+| |RTL Partition |Replication |Instances |
++-+--------------+------------+----------+
++-+--------------+------------+----------+
+---------------------------------------------------------------------------------
+Start RTL Component Statistics 
+---------------------------------------------------------------------------------
+Detailed RTL Component Info : 
++---Adders : 
+	   2 Input     32 Bit       Adders := 1     
+	   2 Input     26 Bit       Adders := 1     
++---Registers : 
+	               64 Bit    Registers := 1     
+	               32 Bit    Registers := 5     
+	               26 Bit    Registers := 6     
+	                8 Bit    Registers := 1     
+	                4 Bit    Registers := 2     
+	                2 Bit    Registers := 2     
+	                1 Bit    Registers := 14    
++---Muxes : 
+	   2 Input     32 Bit        Muxes := 4     
+	   4 Input     32 Bit        Muxes := 5     
+	   2 Input     26 Bit        Muxes := 4     
+	   3 Input      8 Bit        Muxes := 1     
+	   2 Input      8 Bit        Muxes := 2     
+	   2 Input      1 Bit        Muxes := 14    
+---------------------------------------------------------------------------------
+Finished RTL Component Statistics 
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start RTL Hierarchical Component Statistics 
+---------------------------------------------------------------------------------
+Hierarchical RTL Component report 
+Module xpm_cdc_array_single 
+Detailed RTL Component Info : 
++---Registers : 
+	                1 Bit    Registers := 5     
+Module xpm_cdc_array_single__parameterized0 
+Detailed RTL Component Info : 
++---Registers : 
+	               26 Bit    Registers := 5     
+Module axis_adc_data_packer 
+Detailed RTL Component Info : 
++---Adders : 
+	   2 Input     32 Bit       Adders := 1     
+	   2 Input     26 Bit       Adders := 1     
++---Registers : 
+	               64 Bit    Registers := 1     
+	               26 Bit    Registers := 1     
+	                8 Bit    Registers := 1     
+	                1 Bit    Registers := 3     
++---Muxes : 
+	   2 Input     26 Bit        Muxes := 4     
+	   3 Input      8 Bit        Muxes := 1     
+	   2 Input      8 Bit        Muxes := 2     
+	   2 Input      1 Bit        Muxes := 9     
+Module Axis_adc_data_packer_v1_0_S00_AXI 
+Detailed RTL Component Info : 
++---Registers : 
+	               32 Bit    Registers := 5     
+	                4 Bit    Registers := 2     
+	                2 Bit    Registers := 2     
+	                1 Bit    Registers := 6     
++---Muxes : 
+	   2 Input     32 Bit        Muxes := 4     
+	   4 Input     32 Bit        Muxes := 5     
+	   2 Input      1 Bit        Muxes := 5     
+---------------------------------------------------------------------------------
+Finished RTL Hierarchical Component Statistics
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Part Resource Summary
+---------------------------------------------------------------------------------
+Part Resources:
+DSPs: 1728 (col length:144)
+BRAMs: 624 (col length: RAMB18 144 RAMB36 72)
+---------------------------------------------------------------------------------
+Finished Part Resource Summary
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Cross Boundary and Area Optimization
+---------------------------------------------------------------------------------
+Warning: Parallel synthesis criteria is not met 
+INFO: [Synth 8-5546] ROM "Axis_adc_data_packer_v1_0_S00_AXI_inst/axis_adc_data_packer/state" won't be mapped to RAM because it is too sparse
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0 has unconnected port axis_tlast
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0 has unconnected port m_axis_ready
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0 has unconnected port s00_axi_awprot[2]
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0 has unconnected port s00_axi_awprot[1]
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0 has unconnected port s00_axi_awprot[0]
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0 has unconnected port s00_axi_arprot[2]
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0 has unconnected port s00_axi_arprot[1]
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0 has unconnected port s00_axi_arprot[0]
+INFO: [Synth 8-3886] merging instance 'Axis_adc_data_packer_v1_0_S00_AXI_inst/axi_rresp_reg[0]' (FDRE) to 'Axis_adc_data_packer_v1_0_S00_AXI_inst/axi_rresp_reg[1]'
+INFO: [Synth 8-3333] propagating constant 0 across sequential element (\Axis_adc_data_packer_v1_0_S00_AXI_inst/axi_rresp_reg[1] )
+INFO: [Synth 8-3886] merging instance 'Axis_adc_data_packer_v1_0_S00_AXI_inst/axi_bresp_reg[0]' (FDRE) to 'Axis_adc_data_packer_v1_0_S00_AXI_inst/axi_bresp_reg[1]'
+INFO: [Synth 8-3333] propagating constant 0 across sequential element (\Axis_adc_data_packer_v1_0_S00_AXI_inst/axi_bresp_reg[1] )
+INFO: [Synth 8-3333] propagating constant 0 across sequential element (\Axis_adc_data_packer_v1_0_S00_AXI_inst/axis_adc_data_packer/axis_ready_reg )
+---------------------------------------------------------------------------------
+Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 1584.711 ; gain = 1223.082
+---------------------------------------------------------------------------------
+
+Report RTL Partitions: 
++-+--------------+------------+----------+
+| |RTL Partition |Replication |Instances |
++-+--------------+------------+----------+
++-+--------------+------------+----------+
+---------------------------------------------------------------------------------
+Start Applying XDC Timing Constraints
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:20 ; elapsed = 00:00:22 . Memory (MB): peak = 1995.184 ; gain = 1633.555
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Timing Optimization
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Timing Optimization : Time (s): cpu = 00:00:20 ; elapsed = 00:00:22 . Memory (MB): peak = 1995.496 ; gain = 1633.867
+---------------------------------------------------------------------------------
+
+Report RTL Partitions: 
++-+--------------+------------+----------+
+| |RTL Partition |Replication |Instances |
++-+--------------+------------+----------+
++-+--------------+------------+----------+
+---------------------------------------------------------------------------------
+Start Technology Mapping
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Technology Mapping : Time (s): cpu = 00:00:20 ; elapsed = 00:00:22 . Memory (MB): peak = 2007.641 ; gain = 1646.012
+---------------------------------------------------------------------------------
+
+Report RTL Partitions: 
++-+--------------+------------+----------+
+| |RTL Partition |Replication |Instances |
++-+--------------+------------+----------+
++-+--------------+------------+----------+
+---------------------------------------------------------------------------------
+Start IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Final Netlist Cleanup
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Final Netlist Cleanup
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished IO Insertion : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2007.641 ; gain = 1646.012
+---------------------------------------------------------------------------------
+
+Report Check Netlist: 
++------+------------------+-------+---------+-------+------------------+
+|      |Item              |Errors |Warnings |Status |Description       |
++------+------------------+-------+---------+-------+------------------+
+|1     |multi_driven_nets |      0|        0|Passed |Multi driven nets |
++------+------------------+-------+---------+-------+------------------+
+---------------------------------------------------------------------------------
+Start Renaming Generated Instances
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Instances : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2007.641 ; gain = 1646.012
+---------------------------------------------------------------------------------
+
+Report RTL Partitions: 
++-+--------------+------------+----------+
+| |RTL Partition |Replication |Instances |
++-+--------------+------------+----------+
++-+--------------+------------+----------+
+---------------------------------------------------------------------------------
+Start Rebuilding User Hierarchy
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2007.641 ; gain = 1646.012
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Ports
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Ports : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2007.641 ; gain = 1646.012
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2007.641 ; gain = 1646.012
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Nets
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Nets : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2007.641 ; gain = 1646.012
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Writing Synthesis Report
+---------------------------------------------------------------------------------
+
+Report BlackBoxes: 
++-+--------------+----------+
+| |BlackBox name |Instances |
++-+--------------+----------+
++-+--------------+----------+
+
+Report Cell Usage: 
++------+-------+------+
+|      |Cell   |Count |
++------+-------+------+
+|1     |BUFG   |     2|
+|2     |CARRY8 |    10|
+|3     |LUT1   |    27|
+|4     |LUT2   |     3|
+|5     |LUT3   |     2|
+|6     |LUT4   |    49|
+|7     |LUT5   |    25|
+|8     |LUT6   |    38|
+|9     |FDRE   |   412|
+|10    |FDSE   |     1|
+|11    |IBUF   |   114|
+|12    |OBUF   |   108|
++------+-------+------+
+
+Report Instance Areas: 
++------+-----------------------------------------+-------------------------------------+------+
+|      |Instance                                 |Module                               |Cells |
++------+-----------------------------------------+-------------------------------------+------+
+|1     |top                                      |                                     |   791|
+|2     |  Axis_adc_data_packer_v1_0_S00_AXI_inst |Axis_adc_data_packer_v1_0_S00_AXI    |   567|
+|3     |    xpm_cdc_array_single_inst0           |xpm_cdc_array_single                 |     5|
+|4     |    xpm_cdc_array_single_inst1           |xpm_cdc_array_single__parameterized0 |   130|
+|5     |    axis_adc_data_packer                 |axis_adc_data_packer                 |   205|
++------+-----------------------------------------+-------------------------------------+------+
+---------------------------------------------------------------------------------
+Finished Writing Synthesis Report : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2007.641 ; gain = 1646.012
+---------------------------------------------------------------------------------
+Synthesis finished with 0 errors, 0 critical warnings and 8 warnings.
+Synthesis Optimization Runtime : Time (s): cpu = 00:00:11 ; elapsed = 00:00:14 . Memory (MB): peak = 2007.641 ; gain = 577.004
+Synthesis Optimization Complete : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2007.641 ; gain = 1646.012
+INFO: [Project 1-571] Translating synthesized netlist
+INFO: [Netlist 29-17] Analyzing 126 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-570] Preparing netlist for logic optimization
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2043.539 ; gain = 0.000
+INFO: [Project 1-111] Unisim Transformation Summary:
+  A total of 116 instances were transformed.
+  BUFG => BUFGCE: 2 instances
+  IBUF => IBUF (IBUFCTRL, INBUF): 114 instances
+
+INFO: [Common 17-83] Releasing license: Synthesis
+41 Infos, 21 Warnings, 0 Critical Warnings and 0 Errors encountered.
+synth_design completed successfully
+synth_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2043.539 ; gain = 1693.754
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 2043.539 ; gain = 0.000
+WARNING: [Constraints 18-5210] No constraints selected for write.
+Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
+INFO: [Common 17-1381] The checkpoint 'C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/edit_Axis_adc_data_packer_v1_0.runs/synth_1/Axis_adc_data_packer_v1_0.dcp' has been generated.
+INFO: [runtcl-4] Executing : report_utilization -file Axis_adc_data_packer_v1_0_utilization_synth.rpt -pb Axis_adc_data_packer_v1_0_utilization_synth.pb
+INFO: [Common 17-206] Exiting Vivado at Thu Dec 23 16:00:12 2021...

cx9261a_demo_cmos_20240829/ip_repo/edit_Axis_adc_data_packer_v1_0.runs/synth_1/Axis_adc_data_packer_v1_0_utilization_synth.rpt

@@ -0,0 +1,189 @@
+Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec  6 23:38:27 MST 2018
+| Date         : Thu Dec 23 16:00:12 2021
+| Host         : HPZ240A running 64-bit Service Pack 1  (build 7601)
+| Command      : report_utilization -file Axis_adc_data_packer_v1_0_utilization_synth.rpt -pb Axis_adc_data_packer_v1_0_utilization_synth.pb
+| Design       : Axis_adc_data_packer_v1_0
+| Device       : xczu7evffvc1156-2
+| Design State : Synthesized
+---------------------------------------------------------------------------------------------------------------------------------------------
+
+Utilization Design Information
+
+Table of Contents
+-----------------
+1. CLB Logic
+1.1 Summary of Registers by Type
+2. BLOCKRAM
+3. ARITHMETIC
+4. I/O
+5. CLOCK
+6. ADVANCED
+7. CONFIGURATION
+8. Primitives
+9. Black Boxes
+10. Instantiated Netlists
+
+1. CLB Logic
+------------
+
++-------------------------+------+-------+-----------+-------+
+|        Site Type        | Used | Fixed | Available | Util% |
++-------------------------+------+-------+-----------+-------+
+| CLB LUTs*               |  130 |     0 |    230400 |  0.06 |
+|   LUT as Logic          |  130 |     0 |    230400 |  0.06 |
+|   LUT as Memory         |    0 |     0 |    101760 |  0.00 |
+| CLB Registers           |  413 |     0 |    460800 |  0.09 |
+|   Register as Flip Flop |  413 |     0 |    460800 |  0.09 |
+|   Register as Latch     |    0 |     0 |    460800 |  0.00 |
+| CARRY8                  |   10 |     0 |     28800 |  0.03 |
+| F7 Muxes                |    0 |     0 |    115200 |  0.00 |
+| F8 Muxes                |    0 |     0 |     57600 |  0.00 |
+| F9 Muxes                |    0 |     0 |     28800 |  0.00 |
++-------------------------+------+-------+-----------+-------+
+* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
+
+
+1.1 Summary of Registers by Type
+--------------------------------
+
++-------+--------------+-------------+--------------+
+| Total | Clock Enable | Synchronous | Asynchronous |
++-------+--------------+-------------+--------------+
+| 0     |            _ |           - |            - |
+| 0     |            _ |           - |          Set |
+| 0     |            _ |           - |        Reset |
+| 0     |            _ |         Set |            - |
+| 0     |            _ |       Reset |            - |
+| 0     |          Yes |           - |            - |
+| 0     |          Yes |           - |          Set |
+| 0     |          Yes |           - |        Reset |
+| 1     |          Yes |         Set |            - |
+| 412   |          Yes |       Reset |            - |
++-------+--------------+-------------+--------------+
+
+
+2. BLOCKRAM
+-----------
+
++----------------+------+-------+-----------+-------+
+|    Site Type   | Used | Fixed | Available | Util% |
++----------------+------+-------+-----------+-------+
+| Block RAM Tile |    0 |     0 |       312 |  0.00 |
+|   RAMB36/FIFO* |    0 |     0 |       312 |  0.00 |
+|   RAMB18       |    0 |     0 |       624 |  0.00 |
+| URAM           |    0 |     0 |        96 |  0.00 |
++----------------+------+-------+-----------+-------+
+* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E2 or one FIFO18E2. However, if a FIFO18E2 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E2
+
+
+3. ARITHMETIC
+-------------
+
++-----------+------+-------+-----------+-------+
+| Site Type | Used | Fixed | Available | Util% |
++-----------+------+-------+-----------+-------+
+| DSPs      |    0 |     0 |      1728 |  0.00 |
++-----------+------+-------+-----------+-------+
+
+
+4. I/O
+------
+
++------------+------+-------+-----------+-------+
+|  Site Type | Used | Fixed | Available | Util% |
++------------+------+-------+-----------+-------+
+| Bonded IOB |  222 |     0 |       360 | 61.67 |
++------------+------+-------+-----------+-------+
+
+
+5. CLOCK
+--------
+
++----------------------+------+-------+-----------+-------+
+|       Site Type      | Used | Fixed | Available | Util% |
++----------------------+------+-------+-----------+-------+
+| GLOBAL CLOCK BUFFERs |    2 |     0 |       544 |  0.37 |
+|   BUFGCE             |    2 |     0 |       208 |  0.96 |
+|   BUFGCE_DIV         |    0 |     0 |        32 |  0.00 |
+|   BUFG_GT            |    0 |     0 |       144 |  0.00 |
+|   BUFG_PS            |    0 |     0 |        96 |  0.00 |
+|   BUFGCTRL*          |    0 |     0 |        64 |  0.00 |
+| PLL                  |    0 |     0 |        16 |  0.00 |
+| MMCM                 |    0 |     0 |         8 |  0.00 |
++----------------------+------+-------+-----------+-------+
+* Note: Each used BUFGCTRL counts as two global buffer resources. This table does not include global clocking resources, only buffer cell usage. See the Clock Utilization Report (report_clock_utilization) for detailed accounting of global clocking resource availability.
+
+
+6. ADVANCED
+-----------
+
++-----------------+------+-------+-----------+-------+
+|    Site Type    | Used | Fixed | Available | Util% |
++-----------------+------+-------+-----------+-------+
+| GTHE4_CHANNEL   |    0 |     0 |        20 |  0.00 |
+| GTHE4_COMMON    |    0 |     0 |         5 |  0.00 |
+| OBUFDS_GTE4     |    0 |     0 |        10 |  0.00 |
+| OBUFDS_GTE4_ADV |    0 |     0 |        10 |  0.00 |
+| PCIE40E4        |    0 |     0 |         2 |  0.00 |
+| PS8             |    0 |     0 |         1 |  0.00 |
+| SYSMONE4        |    0 |     0 |         1 |  0.00 |
+| VCU             |    0 |     0 |         1 |  0.00 |
++-----------------+------+-------+-----------+-------+
+
+
+7. CONFIGURATION
+----------------
+
++-------------+------+-------+-----------+-------+
+|  Site Type  | Used | Fixed | Available | Util% |
++-------------+------+-------+-----------+-------+
+| BSCANE2     |    0 |     0 |         4 |  0.00 |
+| DNA_PORTE2  |    0 |     0 |         1 |  0.00 |
+| EFUSE_USR   |    0 |     0 |         1 |  0.00 |
+| FRAME_ECCE4 |    0 |     0 |         1 |  0.00 |
+| ICAPE3      |    0 |     0 |         2 |  0.00 |
+| MASTER_JTAG |    0 |     0 |         1 |  0.00 |
+| STARTUPE3   |    0 |     0 |         1 |  0.00 |
++-------------+------+-------+-----------+-------+
+
+
+8. Primitives
+-------------
+
++----------+------+---------------------+
+| Ref Name | Used | Functional Category |
++----------+------+---------------------+
+| FDRE     |  412 |            Register |
+| INBUF    |  114 |                 I/O |
+| IBUFCTRL |  114 |              Others |
+| OBUF     |  108 |                 I/O |
+| LUT4     |   49 |                 CLB |
+| LUT6     |   38 |                 CLB |
+| LUT1     |   27 |                 CLB |
+| LUT5     |   25 |                 CLB |
+| CARRY8   |   10 |                 CLB |
+| LUT2     |    3 |                 CLB |
+| LUT3     |    2 |                 CLB |
+| BUFGCE   |    2 |               Clock |
+| FDSE     |    1 |            Register |
++----------+------+---------------------+
+
+
+9. Black Boxes
+--------------
+
++----------+------+
+| Ref Name | Used |
++----------+------+
+
+
+10. Instantiated Netlists
+-------------------------
+
++----------+------+
+| Ref Name | Used |
++----------+------+
+
+

cx9261a_demo_cmos_20240829/ip_repo/edit_Axis_adc_data_packer_v1_0.runs/synth_1/ISEWrap.js

@@ -0,0 +1,244 @@
+//
+//  Vivado(TM)
+//  ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
+//  Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. 
+//
+
+// GLOBAL VARIABLES
+var ISEShell = new ActiveXObject( "WScript.Shell" );
+var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
+var ISERunDir = "";
+var ISELogFile = "runme.log";
+var ISELogFileStr = null;
+var ISELogEcho = true;
+var ISEOldVersionWSH = false;
+
+
+
+// BOOTSTRAP
+ISEInit();
+
+
+
+//
+// ISE FUNCTIONS
+//
+function ISEInit() {
+
+  // 1. RUN DIR setup
+  var ISEScrFP = WScript.ScriptFullName;
+  var ISEScrN = WScript.ScriptName;
+  ISERunDir = 
+    ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
+
+  // 2. LOG file setup
+  ISELogFileStr = ISEOpenFile( ISELogFile );
+
+  // 3. LOG echo?
+  var ISEScriptArgs = WScript.Arguments;
+  for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
+    if ( ISEScriptArgs(loopi) == "-quiet" ) {
+      ISELogEcho = false;
+      break;
+    }
+  }
+
+  // 4. WSH version check
+  var ISEOptimalVersionWSH = 5.6;
+  var ISECurrentVersionWSH = WScript.Version;
+  if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
+
+    ISEStdErr( "" );
+    ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
+	       ISEOptimalVersionWSH + " or higher. Downloads" );
+    ISEStdErr( "         for upgrading your Windows Scripting Host can be found here: " );
+    ISEStdErr( "             http://msdn.microsoft.com/downloads/list/webdev.asp" );
+    ISEStdErr( "" );
+
+    ISEOldVersionWSH = true;
+  }
+
+}
+
+function ISEStep( ISEProg, ISEArgs ) {
+
+  // CHECK for a STOP FILE
+  if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
+    ISEStdErr( "" );
+    ISEStdErr( "*** Halting run - EA reset detected ***" );
+    ISEStdErr( "" );
+    WScript.Quit( 1 );
+  }
+
+  // WRITE STEP HEADER to LOG
+  ISEStdOut( "" );
+  ISEStdOut( "*** Running " + ISEProg );
+  ISEStdOut( "    with args " + ISEArgs );
+  ISEStdOut( "" );
+
+  // LAUNCH!
+  var ISEExitCode = ISEExec( ISEProg, ISEArgs );  
+  if ( ISEExitCode != 0 ) {
+    WScript.Quit( ISEExitCode );
+  }
+
+}
+
+function ISEExec( ISEProg, ISEArgs ) {
+
+  var ISEStep = ISEProg;
+  if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
+    ISEProg += ".bat";
+  }
+
+  var ISECmdLine = ISEProg + " " + ISEArgs;
+  var ISEExitCode = 1;
+
+  if ( ISEOldVersionWSH ) { // WSH 5.1
+
+    // BEGIN file creation
+    ISETouchFile( ISEStep, "begin" );
+
+    // LAUNCH!
+    ISELogFileStr.Close();
+    ISECmdLine = 
+      "%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
+    ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
+    ISELogFileStr = ISEOpenFile( ISELogFile );
+
+  } else {  // WSH 5.6
+
+    // LAUNCH!
+    ISEShell.CurrentDirectory = ISERunDir;
+
+    // Redirect STDERR to STDOUT
+    ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
+    var ISEProcess = ISEShell.Exec( ISECmdLine );
+    
+    // BEGIN file creation
+    var ISENetwork = WScript.CreateObject( "WScript.Network" );
+    var ISEHost = ISENetwork.ComputerName;
+    var ISEUser = ISENetwork.UserName;
+    var ISEPid = ISEProcess.ProcessID;
+    var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
+    ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
+    ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
+    ISEBeginFile.WriteLine( "    <Process Command=\"" + ISEProg + 
+			    "\" Owner=\"" + ISEUser + 
+			    "\" Host=\"" + ISEHost + 
+			    "\" Pid=\"" + ISEPid +
+			    "\">" );
+    ISEBeginFile.WriteLine( "    </Process>" );
+    ISEBeginFile.WriteLine( "</ProcessHandle>" );
+    ISEBeginFile.Close();
+    
+    var ISEOutStr = ISEProcess.StdOut;
+    var ISEErrStr = ISEProcess.StdErr;
+    
+    // WAIT for ISEStep to finish
+    while ( ISEProcess.Status == 0 ) {
+      
+      // dump stdout then stderr - feels a little arbitrary
+      while ( !ISEOutStr.AtEndOfStream ) {
+        ISEStdOut( ISEOutStr.ReadLine() );
+      }  
+      
+      WScript.Sleep( 100 );
+    }
+
+    ISEExitCode = ISEProcess.ExitCode;
+  }
+
+  ISELogFileStr.Close();
+
+  // END/ERROR file creation
+  if ( ISEExitCode != 0 ) {    
+    ISETouchFile( ISEStep, "error" );
+    
+  } else {
+    ISETouchFile( ISEStep, "end" );
+  }
+
+  return ISEExitCode;
+}
+
+
+//
+// UTILITIES
+//
+function ISEStdOut( ISELine ) {
+
+  ISELogFileStr.WriteLine( ISELine );
+  
+  if ( ISELogEcho ) {
+    WScript.StdOut.WriteLine( ISELine );
+  }
+}
+
+function ISEStdErr( ISELine ) {
+  
+  ISELogFileStr.WriteLine( ISELine );
+
+  if ( ISELogEcho ) {
+    WScript.StdErr.WriteLine( ISELine );
+  }
+}
+
+function ISETouchFile( ISERoot, ISEStatus ) {
+
+  var ISETFile = 
+    ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
+  ISETFile.Close();
+}
+
+function ISEOpenFile( ISEFilename ) {
+
+  // This function has been updated to deal with a problem seen in CR #870871.
+  // In that case the user runs a script that runs impl_1, and then turns around
+  // and runs impl_1 -to_step write_bitstream. That second run takes place in
+  // the same directory, which means we may hit some of the same files, and in
+  // particular, we will open the runme.log file. Even though this script closes
+  // the file (now), we see cases where a subsequent attempt to open the file
+  // fails. Perhaps the OS is slow to release the lock, or the disk comes into
+  // play? In any case, we try to work around this by first waiting if the file
+  // is already there for an arbitrary 5 seconds. Then we use a try-catch block
+  // and try to open the file 10 times with a one second delay after each attempt.
+  // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
+  // If there is an unrecognized exception when trying to open the file, we output
+  // an error message and write details to an exception.log file.
+  var ISEFullPath = ISERunDir + "/" + ISEFilename;
+  if (ISEFileSys.FileExists(ISEFullPath)) {
+    // File is already there. This could be a problem. Wait in case it is still in use.
+    WScript.Sleep(5000);
+  }
+  var i;
+  for (i = 0; i < 10; ++i) {
+    try {
+      return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
+    } catch (exception) {
+      var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
+      if (error_code == 52) { // 52 is bad file name or number.
+        // Wait a second and try again.
+        WScript.Sleep(1000);
+        continue;
+      } else {
+        WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
+        var exceptionFilePath = ISERunDir + "/exception.log";
+        if (!ISEFileSys.FileExists(exceptionFilePath)) {
+          WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
+          var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
+          exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
+          exceptionFile.WriteLine("\tException name: " + exception.name);
+          exceptionFile.WriteLine("\tException error code: " + error_code);
+          exceptionFile.WriteLine("\tException message: " + exception.message);
+          exceptionFile.Close();
+        }
+        throw exception;
+      }
+    }
+  }
+  // If we reached this point, we failed to open the file after 10 attempts.
+  // We need to error out.
+  WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
+  WScript.Quit(1);
+}

cx9261a_demo_cmos_20240829/ip_repo/edit_Axis_adc_data_packer_v1_0.runs/synth_1/ISEWrap.sh

@@ -0,0 +1,63 @@
+#!/bin/sh
+
+#
+#  Vivado(TM)
+#  ISEWrap.sh: Vivado Runs Script for UNIX
+#  Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. 
+#
+
+HD_LOG=$1
+shift
+
+# CHECK for a STOP FILE
+if [ -f .stop.rst ]
+then
+echo ""                                        >> $HD_LOG
+echo "*** Halting run - EA reset detected ***" >> $HD_LOG
+echo ""                                        >> $HD_LOG
+exit 1
+fi
+
+ISE_STEP=$1
+shift
+
+# WRITE STEP HEADER to LOG
+echo ""                      >> $HD_LOG
+echo "*** Running $ISE_STEP" >> $HD_LOG
+echo "    with args $@"      >> $HD_LOG
+echo ""                      >> $HD_LOG
+
+# LAUNCH!
+$ISE_STEP "$@" >> $HD_LOG 2>&1 &
+
+# BEGIN file creation
+ISE_PID=$!
+if [ X != X$HOSTNAME ]
+then
+ISE_HOST=$HOSTNAME #bash
+else
+ISE_HOST=$HOST     #csh
+fi
+ISE_USER=$USER
+ISE_BEGINFILE=.$ISE_STEP.begin.rst
+/bin/touch $ISE_BEGINFILE
+echo "<?xml version=\"1.0\"?>"                                                                     >> $ISE_BEGINFILE
+echo "<ProcessHandle Version=\"1\" Minor=\"0\">"                                                   >> $ISE_BEGINFILE
+echo "    <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\">" >> $ISE_BEGINFILE
+echo "    </Process>"                                                                              >> $ISE_BEGINFILE
+echo "</ProcessHandle>"                                                                            >> $ISE_BEGINFILE
+
+# WAIT for ISEStep to finish
+wait $ISE_PID
+
+# END/ERROR file creation
+RETVAL=$?
+if [ $RETVAL -eq 0 ]
+then
+    /bin/touch .$ISE_STEP.end.rst
+else
+    /bin/touch .$ISE_STEP.error.rst
+fi
+
+exit $RETVAL
+

cx9261a_demo_cmos_20240829/ip_repo/edit_Axis_adc_data_packer_v1_0.runs/synth_1/gen_run.xml

@@ -0,0 +1,66 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<GenRun Id="synth_1" LaunchPart="xczu7ev-ffvc1156-2-e" LaunchTime="1640246379">
+  <File Type="PA-TCL" Name="Axis_adc_data_packer_v1_0.tcl"/>
+  <File Type="REPORTS-TCL" Name="Axis_adc_data_packer_v1_0_reports.tcl"/>
+  <File Type="RDS-RDS" Name="Axis_adc_data_packer_v1_0.vds"/>
+  <File Type="RDS-UTIL" Name="Axis_adc_data_packer_v1_0_utilization_synth.rpt"/>
+  <File Type="RDS-UTIL-PB" Name="Axis_adc_data_packer_v1_0_utilization_synth.pb"/>
+  <File Type="RDS-DCP" Name="Axis_adc_data_packer_v1_0.dcp"/>
+  <FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
+    <Filter Type="Srcs"/>
+    <File Path="$PPRDIR/Axis_adc_data_packer_1.0/hdl/Axis_adc_data_packer_v1_0_S00_AXI.v">
+      <FileInfo>
+        <Attr Name="Library" Val=""/>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/Axis_adc_data_packer_1.0/hdl/axis_adc_data_packer.v">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/Axis_adc_data_packer_1.0/hdl/Axis_adc_data_packer_v1_0.v">
+      <FileInfo>
+        <Attr Name="Library" Val=""/>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/Axis_adc_data_packer_1.0/component.xml">
+      <FileInfo SFType="IPXACT"/>
+    </File>
+    <Config>
+      <Option Name="DesignMode" Val="RTL"/>
+      <Option Name="TopModule" Val="Axis_adc_data_packer_v1_0"/>
+      <Option Name="TopRTLFile" Val="$PPRDIR/Axis_adc_data_packer_1.0/hdl/Axis_adc_data_packer_v1_0.v"/>
+    </Config>
+  </FileSet>
+  <FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
+    <Filter Type="Constrs"/>
+    <File Path="$PSRCDIR/constrs_1/new/constrains.xdc">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+      </FileInfo>
+    </File>
+    <Config>
+      <Option Name="TargetConstrsFile" Val="$PSRCDIR/constrs_1/new/constrains.xdc"/>
+      <Option Name="ConstrsType" Val="XDC"/>
+    </Config>
+  </FileSet>
+  <FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
+    <Filter Type="Utils"/>
+    <Config>
+      <Option Name="TopAutoSet" Val="TRUE"/>
+    </Config>
+  </FileSet>
+  <Strategy Version="1" Minor="2">
+    <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018"/>
+    <Step Id="synth_design"/>
+  </Strategy>
+</GenRun>

cx9261a_demo_cmos_20240829/ip_repo/edit_Axis_adc_data_packer_v1_0.runs/synth_1/htr.txt

@@ -0,0 +1,9 @@
+REM
+REM Vivado(TM)
+REM htr.txt: a Vivado-generated description of how-to-repeat the
+REM          the basic steps of a run.  Note that runme.bat/sh needs
+REM          to be invoked for Vivado to track run status.
+REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
+REM
+
+vivado -log Axis_adc_data_packer_v1_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Axis_adc_data_packer_v1_0.tcl

cx9261a_demo_cmos_20240829/ip_repo/edit_Axis_adc_data_packer_v1_0.runs/synth_1/project.wdf

@@ -0,0 +1,31 @@
+version:1
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:34:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:31:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:31:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:31:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:66616c7365:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:566572696c6f67:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00
+5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:6335643931336632613664323462303262616164333333346666633564313432:506172656e742050412070726f6a656374204944:00
+eof:7738646

cx9261a_demo_cmos_20240829/ip_repo/edit_Axis_adc_data_packer_v1_0.runs/synth_1/rundef.js

@@ -0,0 +1,36 @@
+//
+// Vivado(TM)
+// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
+// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
+//
+
+var WshShell = new ActiveXObject( "WScript.Shell" );
+var ProcEnv = WshShell.Environment( "Process" );
+var PathVal = ProcEnv("PATH");
+if ( PathVal.length == 0 ) {
+  PathVal = "D:/xilinx/SDK/2018.3/bin;D:/xilinx/Vivado/2018.3/ids_lite/ISE/bin/nt64;D:/xilinx/Vivado/2018.3/ids_lite/ISE/lib/nt64;D:/xilinx/Vivado/2018.3/bin;";
+} else {
+  PathVal = "D:/xilinx/SDK/2018.3/bin;D:/xilinx/Vivado/2018.3/ids_lite/ISE/bin/nt64;D:/xilinx/Vivado/2018.3/ids_lite/ISE/lib/nt64;D:/xilinx/Vivado/2018.3/bin;" + PathVal;
+}
+
+ProcEnv("PATH") = PathVal;
+
+var RDScrFP = WScript.ScriptFullName;
+var RDScrN = WScript.ScriptName;
+var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
+var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
+eval( EAInclude(ISEJScriptLib) );
+
+
+ISEStep( "vivado",
+         "-log Axis_adc_data_packer_v1_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Axis_adc_data_packer_v1_0.tcl" );
+
+
+
+function EAInclude( EAInclFilename ) {
+  var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
+  var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
+  var EAIFContents = EAInclFile.ReadAll();
+  EAInclFile.Close();
+  return EAIFContents;
+}

cx9261a_demo_cmos_20240829/ip_repo/edit_Axis_adc_data_packer_v1_0.runs/synth_1/runme.bat

@@ -0,0 +1,10 @@
+@echo off
+
+rem  Vivado (TM)
+rem  runme.bat: a Vivado-generated Script
+rem  Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
+
+
+set HD_SDIR=%~dp0
+cd /d "%HD_SDIR%"
+cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*

cx9261a_demo_cmos_20240829/ip_repo/edit_Axis_adc_data_packer_v1_0.runs/synth_1/runme.log

@@ -0,0 +1,417 @@
+
+*** Running vivado
+    with args -log Axis_adc_data_packer_v1_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Axis_adc_data_packer_v1_0.tcl
+
+
+****** Vivado v2018.3 (64-bit)
+  **** SW Build 2405991 on Thu Dec  6 23:38:27 MST 2018
+  **** IP Build 2404404 on Fri Dec  7 01:43:56 MST 2018
+    ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
+
+source Axis_adc_data_packer_v1_0.tcl -notrace
+INFO: [IP_Flow 19-234] Refreshing IP repositories
+INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work'.
+WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'c:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'c:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/edit_Axis_adc_data_packer_v1_0.runs/synth_1'.)
+INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/xilinx/Vivado/2018.3/data/ip'.
+WARNING: [IP_Flow 19-4995] The host OS only allows 260 characters in a normal path. The IP cache path is more than 80 characters. If you experience issues with IP caching, please consider changing the IP cache to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter. 
+Current IP cache path is c:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/edit_Axis_adc_data_packer_v1_0.cache/ip 
+WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/Axis_adc_data_packer_v1_0_S00_AXI.v:]
+WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/Axis_adc_data_packer_v1_0.v:]
+Command: synth_design -top Axis_adc_data_packer_v1_0 -part xczu7ev-ffvc1156-2-e
+Starting synth_design
+Attempting to get a license for feature 'Synthesis' and/or device 'xczu7ev'
+INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xczu7ev'
+INFO: Launching helper process for spawning children vivado processes
+INFO: Helper process launched with PID 1944 
+---------------------------------------------------------------------------------
+Starting RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 465.340 ; gain = 103.711
+---------------------------------------------------------------------------------
+INFO: [Synth 8-6157] synthesizing module 'Axis_adc_data_packer_v1_0' [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/Axis_adc_data_packer_v1_0.v:3]
+	Parameter C_S00_AXI_DATA_WIDTH bound to: 32 - type: integer 
+	Parameter C_S00_AXI_ADDR_WIDTH bound to: 4 - type: integer 
+INFO: [Synth 8-6157] synthesizing module 'Axis_adc_data_packer_v1_0_S00_AXI' [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/Axis_adc_data_packer_v1_0_S00_AXI.v:3]
+	Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer 
+	Parameter C_S_AXI_ADDR_WIDTH bound to: 4 - type: integer 
+	Parameter ADDR_LSB bound to: 2 - type: integer 
+	Parameter OPT_MEM_ADDR_BITS bound to: 1 - type: integer 
+INFO: [Synth 8-226] default block is never used [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/Axis_adc_data_packer_v1_0_S00_AXI.v:240]
+INFO: [Synth 8-226] default block is never used [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/Axis_adc_data_packer_v1_0_S00_AXI.v:381]
+INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_array_single' [D:/xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:903]
+	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
+	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
+	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
+	Parameter SRC_INPUT_REG bound to: 1 - type: integer 
+	Parameter VERSION bound to: 0 - type: integer 
+	Parameter WIDTH bound to: 1 - type: integer 
+INFO: [Synth 8-5534] Detected attribute (* ASYNC_REG = "TRUE" *) [D:/xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:958]
+INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_array_single' (1#1) [D:/xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:903]
+INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_array_single__parameterized0' [D:/xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:903]
+	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
+	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
+	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
+	Parameter SRC_INPUT_REG bound to: 1 - type: integer 
+	Parameter VERSION bound to: 0 - type: integer 
+	Parameter WIDTH bound to: 26 - type: integer 
+INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_array_single__parameterized0' (1#1) [D:/xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:903]
+INFO: [Synth 8-6157] synthesizing module 'axis_adc_data_packer' [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/axis_adc_data_packer.v:23]
+INFO: [Synth 8-5534] Detected attribute (* keep = "true" *) [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/axis_adc_data_packer.v:52]
+INFO: [Synth 8-5534] Detected attribute (* keep = "true" *) [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/axis_adc_data_packer.v:53]
+INFO: [Synth 8-6155] done synthesizing module 'axis_adc_data_packer' (2#1) [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/axis_adc_data_packer.v:23]
+INFO: [Synth 8-6155] done synthesizing module 'Axis_adc_data_packer_v1_0_S00_AXI' (3#1) [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/Axis_adc_data_packer_v1_0_S00_AXI.v:3]
+INFO: [Synth 8-6155] done synthesizing module 'Axis_adc_data_packer_v1_0' (4#1) [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/Axis_adc_data_packer_v1_0.v:3]
+WARNING: [Synth 8-3331] design axis_adc_data_packer has unconnected port m_axis_ready
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0_S00_AXI has unconnected port S_AXI_AWPROT[2]
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0_S00_AXI has unconnected port S_AXI_AWPROT[1]
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0_S00_AXI has unconnected port S_AXI_AWPROT[0]
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0_S00_AXI has unconnected port S_AXI_ARPROT[2]
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0_S00_AXI has unconnected port S_AXI_ARPROT[1]
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0_S00_AXI has unconnected port S_AXI_ARPROT[0]
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0 has unconnected port axis_tlast
+---------------------------------------------------------------------------------
+Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 515.703 ; gain = 154.074
+---------------------------------------------------------------------------------
+
+Report Check Netlist: 
++------+------------------+-------+---------+-------+------------------+
+|      |Item              |Errors |Warnings |Status |Description       |
++------+------------------+-------+---------+-------+------------------+
+|1     |multi_driven_nets |      0|        0|Passed |Multi driven nets |
++------+------------------+-------+---------+-------+------------------+
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 515.703 ; gain = 154.074
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 515.703 ; gain = 154.074
+---------------------------------------------------------------------------------
+INFO: [Device 21-403] Loading part xczu7ev-ffvc1156-2-e
+INFO: [Project 1-570] Preparing netlist for logic optimization
+
+Processing XDC Constraints
+Initializing timing engine
+Parsing XDC File [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/edit_Axis_adc_data_packer_v1_0.srcs/constrs_1/new/constrains.xdc]
+Finished Parsing XDC File [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/edit_Axis_adc_data_packer_v1_0.srcs/constrs_1/new/constrains.xdc]
+Sourcing Tcl File [D:/xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'Axis_adc_data_packer_v1_0_S00_AXI_inst/xpm_cdc_array_single_inst0'
+Finished Sourcing Tcl File [D:/xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'Axis_adc_data_packer_v1_0_S00_AXI_inst/xpm_cdc_array_single_inst0'
+Sourcing Tcl File [D:/xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'Axis_adc_data_packer_v1_0_S00_AXI_inst/xpm_cdc_array_single_inst1'
+Finished Sourcing Tcl File [D:/xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'Axis_adc_data_packer_v1_0_S00_AXI_inst/xpm_cdc_array_single_inst1'
+INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [D:/xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/Axis_adc_data_packer_v1_0_propImpl.xdc].
+Resolution: To avoid this warning, move constraints listed in [.Xil/Axis_adc_data_packer_v1_0_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1584.711 ; gain = 0.000
+WARNING: [Constraints 18-5210] No constraints selected for write.
+Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
+Completed Processing XDC Constraints
+
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1584.711 ; gain = 0.000
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1584.711 ; gain = 0.000
+Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.007 . Memory (MB): peak = 1584.711 ; gain = 0.000
+---------------------------------------------------------------------------------
+Finished Constraint Validation : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 1584.711 ; gain = 1223.082
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Loading Part and Timing Information
+---------------------------------------------------------------------------------
+Loading part: xczu7ev-ffvc1156-2-e
+INFO: [Synth 8-6742] Reading net delay rules and data
+---------------------------------------------------------------------------------
+Finished Loading Part and Timing Information : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 1584.711 ; gain = 1223.082
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Applying 'set_property' XDC Constraints
+---------------------------------------------------------------------------------
+Applied set_property DONT_TOUCH = true for Axis_adc_data_packer_v1_0_S00_AXI_inst/xpm_cdc_array_single_inst0. (constraint file  auto generated constraint, line ).
+Applied set_property DONT_TOUCH = true for Axis_adc_data_packer_v1_0_S00_AXI_inst/xpm_cdc_array_single_inst1. (constraint file  auto generated constraint, line ).
+---------------------------------------------------------------------------------
+Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 1584.711 ; gain = 1223.082
+---------------------------------------------------------------------------------
+.p 4
+.s 3
+.r iSTATE
+	 Default iSTATE 
+	 iSTATE iSTATE0 
+	 iSTATE iSTATE 
+	 iSTATE0 iSTATE 
+.e
+INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'axis_adc_data_packer'
+INFO: [Synth 8-5546] ROM "cnt" won't be mapped to RAM because it is too sparse
+INFO: [Synth 8-5546] ROM "state" won't be mapped to RAM because it is too sparse
+INFO: [Synth 8-6159] Found Keep on FSM register 'state_reg' in module 'axis_adc_data_packer', re-encoding will not be performed
+---------------------------------------------------------------------------------------------------
+                   State |                     New Encoding |                Previous Encoding 
+---------------------------------------------------------------------------------------------------
+*
+                  iSTATE |                         00000000 |                         00000000
+                 iSTATE0 |                         00000001 |                         00000001
+---------------------------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 1584.711 ; gain = 1223.082
+---------------------------------------------------------------------------------
+
+Report RTL Partitions: 
++-+--------------+------------+----------+
+| |RTL Partition |Replication |Instances |
++-+--------------+------------+----------+
++-+--------------+------------+----------+
+---------------------------------------------------------------------------------
+Start RTL Component Statistics 
+---------------------------------------------------------------------------------
+Detailed RTL Component Info : 
++---Adders : 
+	   2 Input     32 Bit       Adders := 1     
+	   2 Input     26 Bit       Adders := 1     
++---Registers : 
+	               64 Bit    Registers := 1     
+	               32 Bit    Registers := 5     
+	               26 Bit    Registers := 6     
+	                8 Bit    Registers := 1     
+	                4 Bit    Registers := 2     
+	                2 Bit    Registers := 2     
+	                1 Bit    Registers := 14    
++---Muxes : 
+	   2 Input     32 Bit        Muxes := 4     
+	   4 Input     32 Bit        Muxes := 5     
+	   2 Input     26 Bit        Muxes := 4     
+	   3 Input      8 Bit        Muxes := 1     
+	   2 Input      8 Bit        Muxes := 2     
+	   2 Input      1 Bit        Muxes := 14    
+---------------------------------------------------------------------------------
+Finished RTL Component Statistics 
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start RTL Hierarchical Component Statistics 
+---------------------------------------------------------------------------------
+Hierarchical RTL Component report 
+Module xpm_cdc_array_single 
+Detailed RTL Component Info : 
++---Registers : 
+	                1 Bit    Registers := 5     
+Module xpm_cdc_array_single__parameterized0 
+Detailed RTL Component Info : 
++---Registers : 
+	               26 Bit    Registers := 5     
+Module axis_adc_data_packer 
+Detailed RTL Component Info : 
++---Adders : 
+	   2 Input     32 Bit       Adders := 1     
+	   2 Input     26 Bit       Adders := 1     
++---Registers : 
+	               64 Bit    Registers := 1     
+	               26 Bit    Registers := 1     
+	                8 Bit    Registers := 1     
+	                1 Bit    Registers := 3     
++---Muxes : 
+	   2 Input     26 Bit        Muxes := 4     
+	   3 Input      8 Bit        Muxes := 1     
+	   2 Input      8 Bit        Muxes := 2     
+	   2 Input      1 Bit        Muxes := 9     
+Module Axis_adc_data_packer_v1_0_S00_AXI 
+Detailed RTL Component Info : 
++---Registers : 
+	               32 Bit    Registers := 5     
+	                4 Bit    Registers := 2     
+	                2 Bit    Registers := 2     
+	                1 Bit    Registers := 6     
++---Muxes : 
+	   2 Input     32 Bit        Muxes := 4     
+	   4 Input     32 Bit        Muxes := 5     
+	   2 Input      1 Bit        Muxes := 5     
+---------------------------------------------------------------------------------
+Finished RTL Hierarchical Component Statistics
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Part Resource Summary
+---------------------------------------------------------------------------------
+Part Resources:
+DSPs: 1728 (col length:144)
+BRAMs: 624 (col length: RAMB18 144 RAMB36 72)
+---------------------------------------------------------------------------------
+Finished Part Resource Summary
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Cross Boundary and Area Optimization
+---------------------------------------------------------------------------------
+Warning: Parallel synthesis criteria is not met 
+INFO: [Synth 8-5546] ROM "Axis_adc_data_packer_v1_0_S00_AXI_inst/axis_adc_data_packer/state" won't be mapped to RAM because it is too sparse
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0 has unconnected port axis_tlast
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0 has unconnected port m_axis_ready
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0 has unconnected port s00_axi_awprot[2]
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0 has unconnected port s00_axi_awprot[1]
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0 has unconnected port s00_axi_awprot[0]
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0 has unconnected port s00_axi_arprot[2]
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0 has unconnected port s00_axi_arprot[1]
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0 has unconnected port s00_axi_arprot[0]
+INFO: [Synth 8-3886] merging instance 'Axis_adc_data_packer_v1_0_S00_AXI_inst/axi_rresp_reg[0]' (FDRE) to 'Axis_adc_data_packer_v1_0_S00_AXI_inst/axi_rresp_reg[1]'
+INFO: [Synth 8-3333] propagating constant 0 across sequential element (\Axis_adc_data_packer_v1_0_S00_AXI_inst/axi_rresp_reg[1] )
+INFO: [Synth 8-3886] merging instance 'Axis_adc_data_packer_v1_0_S00_AXI_inst/axi_bresp_reg[0]' (FDRE) to 'Axis_adc_data_packer_v1_0_S00_AXI_inst/axi_bresp_reg[1]'
+INFO: [Synth 8-3333] propagating constant 0 across sequential element (\Axis_adc_data_packer_v1_0_S00_AXI_inst/axi_bresp_reg[1] )
+INFO: [Synth 8-3333] propagating constant 0 across sequential element (\Axis_adc_data_packer_v1_0_S00_AXI_inst/axis_adc_data_packer/axis_ready_reg )
+---------------------------------------------------------------------------------
+Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 1584.711 ; gain = 1223.082
+---------------------------------------------------------------------------------
+
+Report RTL Partitions: 
++-+--------------+------------+----------+
+| |RTL Partition |Replication |Instances |
++-+--------------+------------+----------+
++-+--------------+------------+----------+
+---------------------------------------------------------------------------------
+Start Applying XDC Timing Constraints
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:20 ; elapsed = 00:00:22 . Memory (MB): peak = 1995.184 ; gain = 1633.555
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Timing Optimization
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Timing Optimization : Time (s): cpu = 00:00:20 ; elapsed = 00:00:22 . Memory (MB): peak = 1995.496 ; gain = 1633.867
+---------------------------------------------------------------------------------
+
+Report RTL Partitions: 
++-+--------------+------------+----------+
+| |RTL Partition |Replication |Instances |
++-+--------------+------------+----------+
++-+--------------+------------+----------+
+---------------------------------------------------------------------------------
+Start Technology Mapping
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Technology Mapping : Time (s): cpu = 00:00:20 ; elapsed = 00:00:22 . Memory (MB): peak = 2007.641 ; gain = 1646.012
+---------------------------------------------------------------------------------
+
+Report RTL Partitions: 
++-+--------------+------------+----------+
+| |RTL Partition |Replication |Instances |
++-+--------------+------------+----------+
++-+--------------+------------+----------+
+---------------------------------------------------------------------------------
+Start IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Final Netlist Cleanup
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Final Netlist Cleanup
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished IO Insertion : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2007.641 ; gain = 1646.012
+---------------------------------------------------------------------------------
+
+Report Check Netlist: 
++------+------------------+-------+---------+-------+------------------+
+|      |Item              |Errors |Warnings |Status |Description       |
++------+------------------+-------+---------+-------+------------------+
+|1     |multi_driven_nets |      0|        0|Passed |Multi driven nets |
++------+------------------+-------+---------+-------+------------------+
+---------------------------------------------------------------------------------
+Start Renaming Generated Instances
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Instances : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2007.641 ; gain = 1646.012
+---------------------------------------------------------------------------------
+
+Report RTL Partitions: 
++-+--------------+------------+----------+
+| |RTL Partition |Replication |Instances |
++-+--------------+------------+----------+
++-+--------------+------------+----------+
+---------------------------------------------------------------------------------
+Start Rebuilding User Hierarchy
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2007.641 ; gain = 1646.012
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Ports
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Ports : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2007.641 ; gain = 1646.012
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2007.641 ; gain = 1646.012
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Nets
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Nets : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2007.641 ; gain = 1646.012
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Writing Synthesis Report
+---------------------------------------------------------------------------------
+
+Report BlackBoxes: 
++-+--------------+----------+
+| |BlackBox name |Instances |
++-+--------------+----------+
++-+--------------+----------+
+
+Report Cell Usage: 
++------+-------+------+
+|      |Cell   |Count |
++------+-------+------+
+|1     |BUFG   |     2|
+|2     |CARRY8 |    10|
+|3     |LUT1   |    27|
+|4     |LUT2   |     3|
+|5     |LUT3   |     2|
+|6     |LUT4   |    49|
+|7     |LUT5   |    25|
+|8     |LUT6   |    38|
+|9     |FDRE   |   412|
+|10    |FDSE   |     1|
+|11    |IBUF   |   114|
+|12    |OBUF   |   108|
++------+-------+------+
+
+Report Instance Areas: 
++------+-----------------------------------------+-------------------------------------+------+
+|      |Instance                                 |Module                               |Cells |
++------+-----------------------------------------+-------------------------------------+------+
+|1     |top                                      |                                     |   791|
+|2     |  Axis_adc_data_packer_v1_0_S00_AXI_inst |Axis_adc_data_packer_v1_0_S00_AXI    |   567|
+|3     |    xpm_cdc_array_single_inst0           |xpm_cdc_array_single                 |     5|
+|4     |    xpm_cdc_array_single_inst1           |xpm_cdc_array_single__parameterized0 |   130|
+|5     |    axis_adc_data_packer                 |axis_adc_data_packer                 |   205|
++------+-----------------------------------------+-------------------------------------+------+
+---------------------------------------------------------------------------------
+Finished Writing Synthesis Report : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2007.641 ; gain = 1646.012
+---------------------------------------------------------------------------------
+Synthesis finished with 0 errors, 0 critical warnings and 8 warnings.
+Synthesis Optimization Runtime : Time (s): cpu = 00:00:11 ; elapsed = 00:00:14 . Memory (MB): peak = 2007.641 ; gain = 577.004
+Synthesis Optimization Complete : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2007.641 ; gain = 1646.012
+INFO: [Project 1-571] Translating synthesized netlist
+INFO: [Netlist 29-17] Analyzing 126 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-570] Preparing netlist for logic optimization
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2043.539 ; gain = 0.000
+INFO: [Project 1-111] Unisim Transformation Summary:
+  A total of 116 instances were transformed.
+  BUFG => BUFGCE: 2 instances
+  IBUF => IBUF (IBUFCTRL, INBUF): 114 instances
+
+INFO: [Common 17-83] Releasing license: Synthesis
+41 Infos, 21 Warnings, 0 Critical Warnings and 0 Errors encountered.
+synth_design completed successfully
+synth_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2043.539 ; gain = 1693.754
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 2043.539 ; gain = 0.000
+WARNING: [Constraints 18-5210] No constraints selected for write.
+Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
+INFO: [Common 17-1381] The checkpoint 'C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/edit_Axis_adc_data_packer_v1_0.runs/synth_1/Axis_adc_data_packer_v1_0.dcp' has been generated.
+INFO: [runtcl-4] Executing : report_utilization -file Axis_adc_data_packer_v1_0_utilization_synth.rpt -pb Axis_adc_data_packer_v1_0_utilization_synth.pb
+INFO: [Common 17-206] Exiting Vivado at Thu Dec 23 16:00:12 2021...

cx9261a_demo_cmos_20240829/ip_repo/edit_Axis_adc_data_packer_v1_0.runs/synth_1/runme.sh

@@ -0,0 +1,43 @@
+#!/bin/sh
+
+# 
+# Vivado(TM)
+# runme.sh: a Vivado-generated Runs Script for UNIX
+# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
+# 
+
+echo "This script was generated under a different operating system."
+echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script"
+exit
+
+if [ -z "$PATH" ]; then
+  PATH=D:/xilinx/SDK/2018.3/bin;D:/xilinx/Vivado/2018.3/ids_lite/ISE/bin/nt64;D:/xilinx/Vivado/2018.3/ids_lite/ISE/lib/nt64:D:/xilinx/Vivado/2018.3/bin
+else
+  PATH=D:/xilinx/SDK/2018.3/bin;D:/xilinx/Vivado/2018.3/ids_lite/ISE/bin/nt64;D:/xilinx/Vivado/2018.3/ids_lite/ISE/lib/nt64:D:/xilinx/Vivado/2018.3/bin:$PATH
+fi
+export PATH
+
+if [ -z "$LD_LIBRARY_PATH" ]; then
+  LD_LIBRARY_PATH=
+else
+  LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
+fi
+export LD_LIBRARY_PATH
+
+HD_PWD='C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/edit_Axis_adc_data_packer_v1_0.runs/synth_1'
+cd "$HD_PWD"
+
+HD_LOG=runme.log
+/bin/touch $HD_LOG
+
+ISEStep="./ISEWrap.sh"
+EAStep()
+{
+     $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
+     if [ $? -ne 0 ]
+     then
+         exit
+     fi
+}
+
+EAStep vivado -log Axis_adc_data_packer_v1_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Axis_adc_data_packer_v1_0.tcl

cx9261a_demo_cmos_20240829/ip_repo/edit_Axis_adc_data_packer_v1_0.runs/synth_1/vivado.jou

@@ -0,0 +1,12 @@
+#-----------------------------------------------------------
+# Vivado v2018.3 (64-bit)
+# SW Build 2405991 on Thu Dec  6 23:38:27 MST 2018
+# IP Build 2404404 on Fri Dec  7 01:43:56 MST 2018
+# Start of session at: Thu Dec 23 15:59:40 2021
+# Process ID: 9796
+# Current directory: C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/edit_Axis_adc_data_packer_v1_0.runs/synth_1
+# Command line: vivado.exe -log Axis_adc_data_packer_v1_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source Axis_adc_data_packer_v1_0.tcl
+# Log file: C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/edit_Axis_adc_data_packer_v1_0.runs/synth_1/Axis_adc_data_packer_v1_0.vds
+# Journal file: C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/edit_Axis_adc_data_packer_v1_0.runs/synth_1\vivado.jou
+#-----------------------------------------------------------
+source Axis_adc_data_packer_v1_0.tcl -notrace

cx9261a_demo_cmos_20240829/ip_repo/edit_Axis_adc_data_packer_v1_0.xpr

@@ -0,0 +1,200 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2018.3 (64-bit)              -->
+<!--                                                         -->
+<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.   -->
+
+<Project Version="7" Minor="39" Path="C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/edit_Axis_adc_data_packer_v1_0.xpr">
+  <DefaultLaunch Dir="$PRUNDIR"/>
+  <Configuration>
+    <Option Name="Id" Val="c5d913f2a6d24b02baad3334ffc5d142"/>
+    <Option Name="Part" Val="xczu7ev-ffvc1156-2-e"/>
+    <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
+    <Option Name="CompiledLibDirXSim" Val=""/>
+    <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
+    <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
+    <Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
+    <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
+    <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
+    <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
+    <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
+    <Option Name="BoardPart" Val="xilinx.com:zcu106:part0:2.3"/>
+    <Option Name="ActiveSimSet" Val="sim_1"/>
+    <Option Name="DefaultLib" Val="xil_defaultlib"/>
+    <Option Name="ProjectType" Val="Default"/>
+    <Option Name="IPRepoPath" Val="$PPRDIR/."/>
+    <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
+    <Option Name="IPCachePermission" Val="read"/>
+    <Option Name="IPCachePermission" Val="write"/>
+    <Option Name="EnableCoreContainer" Val="FALSE"/>
+    <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
+    <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
+    <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
+    <Option Name="EnableBDX" Val="FALSE"/>
+    <Option Name="DSAVendor" Val="xilinx"/>
+    <Option Name="DSABoardId" Val="zcu106"/>
+    <Option Name="DSANumComputeUnits" Val="60"/>
+    <Option Name="WTXSimLaunchSim" Val="0"/>
+    <Option Name="WTModelSimLaunchSim" Val="0"/>
+    <Option Name="WTQuestaLaunchSim" Val="0"/>
+    <Option Name="WTIesLaunchSim" Val="0"/>
+    <Option Name="WTVcsLaunchSim" Val="0"/>
+    <Option Name="WTRivieraLaunchSim" Val="0"/>
+    <Option Name="WTActivehdlLaunchSim" Val="0"/>
+    <Option Name="WTXSimExportSim" Val="0"/>
+    <Option Name="WTModelSimExportSim" Val="0"/>
+    <Option Name="WTQuestaExportSim" Val="0"/>
+    <Option Name="WTIesExportSim" Val="0"/>
+    <Option Name="WTVcsExportSim" Val="0"/>
+    <Option Name="WTRivieraExportSim" Val="0"/>
+    <Option Name="WTActivehdlExportSim" Val="0"/>
+    <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
+    <Option Name="XSimRadix" Val="hex"/>
+    <Option Name="XSimTimeUnit" Val="ns"/>
+    <Option Name="XSimArrayDisplayLimit" Val="1024"/>
+    <Option Name="XSimTraceLimit" Val="65536"/>
+    <Option Name="SimTypes" Val="rtl"/>
+    <Option Name="SimTypes" Val="bfm"/>
+    <Option Name="SimTypes" Val="tlm"/>
+    <Option Name="SimTypes" Val="tlm_dpi"/>
+    <Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
+  </Configuration>
+  <FileSets Version="1" Minor="31">
+    <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
+      <Filter Type="Srcs"/>
+      <File Path="$PPRDIR/Axis_adc_data_packer_1.0/hdl/Axis_adc_data_packer_v1_0_S00_AXI.v">
+        <FileInfo>
+          <Attr Name="Library" Val=""/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/Axis_adc_data_packer_1.0/hdl/axis_adc_data_packer.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/Axis_adc_data_packer_1.0/hdl/Axis_adc_data_packer_v1_0.v">
+        <FileInfo>
+          <Attr Name="Library" Val=""/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/Axis_adc_data_packer_1.0/component.xml">
+        <FileInfo SFType="IPXACT"/>
+      </File>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="Axis_adc_data_packer_v1_0"/>
+        <Option Name="TopRTLFile" Val="$PPRDIR/Axis_adc_data_packer_1.0/hdl/Axis_adc_data_packer_v1_0.v"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
+      <Filter Type="Constrs"/>
+      <Config>
+        <Option Name="ConstrsType" Val="XDC"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
+      <Filter Type="Srcs"/>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="Axis_adc_data_packer_v1_0"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+        <Option Name="TransportPathDelay" Val="0"/>
+        <Option Name="TransportIntDelay" Val="0"/>
+        <Option Name="SrcSet" Val="sources_1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
+      <Filter Type="Utils"/>
+      <Config>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+      </Config>
+    </FileSet>
+  </FileSets>
+  <Simulators>
+    <Simulator Name="XSim">
+      <Option Name="Description" Val="Vivado Simulator"/>
+      <Option Name="CompiledLib" Val="0"/>
+    </Simulator>
+    <Simulator Name="ModelSim">
+      <Option Name="Description" Val="ModelSim Simulator"/>
+    </Simulator>
+    <Simulator Name="Questa">
+      <Option Name="Description" Val="Questa Advanced Simulator"/>
+    </Simulator>
+    <Simulator Name="Riviera">
+      <Option Name="Description" Val="Riviera-PRO Simulator"/>
+    </Simulator>
+    <Simulator Name="ActiveHDL">
+      <Option Name="Description" Val="Active-HDL Simulator"/>
+    </Simulator>
+  </Simulators>
+  <Runs Version="1" Minor="10">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xczu7ev-ffvc1156-2-e" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2018"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+    </Run>
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xczu7ev-ffvc1156-2-e" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2018"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+    </Run>
+  </Runs>
+  <Board>
+    <Jumpers/>
+  </Board>
+  <DashboardSummary Version="1" Minor="0">
+    <Dashboards>
+      <Dashboard Name="default_dashboard">
+        <Gadgets>
+          <Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
+          </Gadget>
+          <Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
+          </Gadget>
+          <Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
+          </Gadget>
+          <Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
+          </Gadget>
+          <Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
+            <GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
+            <GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
+          </Gadget>
+          <Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
+          </Gadget>
+        </Gadgets>
+      </Dashboard>
+      <CurrentDashboard>default_dashboard</CurrentDashboard>
+    </Dashboards>
+  </DashboardSummary>
+  <BootPmcSettings Version="1" Minor="0">
+    <Parameters/>
+  </BootPmcSettings>
+</Project>

cx9261a_demo_cmos_20240829/project_fix_dac.srcs/constrs_1/new/cx9261a_zc706.xdc

@@ -0,0 +1,141 @@
+################ 1 #CX9261A Interface PACKAGE_PIN and IOStandard constraints####################
+############CX9261A SPI and Control pin Interface##############
+set_property PACKAGE_PIN V28 [get_ports SCLK       ]
+set_property PACKAGE_PIN V29 [get_ports CSB        ]
+set_property PACKAGE_PIN T28 [get_ports SDO        ]
+set_property PACKAGE_PIN R28 [get_ports SDIO       ]
+set_property PACKAGE_PIN N27 [get_ports NRST       ]
+set_property PACKAGE_PIN U26 [get_ports OSC_OUT    ]
+set_property PACKAGE_PIN P26 [get_ports ENABLE_TRX2]
+set_property PACKAGE_PIN P25 [get_ports ENABLE_TRX1]
+set_property PACKAGE_PIN N26 [get_ports ENABLE_RXFB]
+set_property PACKAGE_PIN P29 [get_ports TXNRX_TRX1 ]
+set_property PACKAGE_PIN N29 [get_ports TXNRX_TRX2 ]
+set_property PACKAGE_PIN U27 [get_ports TXNRX_RXFB ]
+set_property IOSTANDARD LVCMOS25 [get_ports SCLK       ]
+set_property IOSTANDARD LVCMOS25 [get_ports CSB        ]
+set_property IOSTANDARD LVCMOS25 [get_ports SDO        ]
+set_property IOSTANDARD LVCMOS25 [get_ports SDIO       ]
+set_property IOSTANDARD LVCMOS25 [get_ports NRST       ]
+set_property IOSTANDARD LVCMOS25 [get_ports OSC_OUT    ]
+set_property IOSTANDARD LVCMOS25 [get_ports ENABLE_TRX1]
+set_property IOSTANDARD LVCMOS25 [get_ports ENABLE_TRX2]
+set_property IOSTANDARD LVCMOS25 [get_ports ENABLE_RXFB]
+set_property IOSTANDARD LVCMOS25 [get_ports TXNRX_TRX1 ]
+set_property IOSTANDARD LVCMOS25 [get_ports TXNRX_TRX2 ]
+set_property IOSTANDARD LVCMOS25 [get_ports TXNRX_RXFB ]
+###############################################################
+####################CX9261A data Interface#####################
+set_property PACKAGE_PIN W25  [get_ports RXFB_MCLK_IN     ]
+set_property PACKAGE_PIN W26  [get_ports RXFB_FRAME_IN    ]
+set_property PACKAGE_PIN AF22 [get_ports RX1_MCLK_IN_N    ]
+set_property PACKAGE_PIN AE22 [get_ports RX2_MCLK_IN_P    ]
+set_property PACKAGE_PIN AH24 [get_ports RX1_FRAME_IN_N   ]
+set_property PACKAGE_PIN AH23 [get_ports RX2_FRAME_IN_P   ]
+set_property PACKAGE_PIN R26  [get_ports TX1_FCLK_OUT_N   ]
+set_property PACKAGE_PIN R25  [get_ports TX2_FCLK_OUT_P   ]
+set_property PACKAGE_PIN T25  [get_ports TX1_FRAME_OUT_N  ]
+set_property PACKAGE_PIN T24  [get_ports TX2_FRAME_OUT_P  ]
+set_property PACKAGE_PIN P30  [get_ports {RXFB_RX_DATA[7]}]
+set_property PACKAGE_PIN R30  [get_ports {RXFB_RX_DATA[6]}]
+set_property PACKAGE_PIN P23  [get_ports {RXFB_RX_DATA[5]}]
+set_property PACKAGE_PIN P24  [get_ports {RXFB_RX_DATA[4]}]
+set_property PACKAGE_PIN P21  [get_ports {RXFB_RX_DATA[3]}]
+set_property PACKAGE_PIN R21  [get_ports {RXFB_RX_DATA[2]}]
+set_property PACKAGE_PIN W29  [get_ports {RXFB_RX_DATA[1]}]
+set_property PACKAGE_PIN W30  [get_ports {RXFB_RX_DATA[0]}]
+set_property PACKAGE_PIN U25  [get_ports {RXFB_TX_DATA[7]}]
+set_property PACKAGE_PIN V26  [get_ports {RXFB_TX_DATA[6]}]
+set_property PACKAGE_PIN V27  [get_ports {RXFB_TX_DATA[5]}]
+set_property PACKAGE_PIN W28  [get_ports {RXFB_TX_DATA[4]}]
+set_property PACKAGE_PIN T29  [get_ports {RXFB_TX_DATA[3]}]
+set_property PACKAGE_PIN U29  [get_ports {RXFB_TX_DATA[2]}]
+set_property PACKAGE_PIN T30  [get_ports {RXFB_TX_DATA[1]}]
+set_property PACKAGE_PIN U30  [get_ports {RXFB_TX_DATA[0]}]
+set_property PACKAGE_PIN AH19 [get_ports {RX1_FDD_DATA[7]}]
+set_property PACKAGE_PIN AJ19 [get_ports {RX1_FDD_DATA[6]}]
+set_property PACKAGE_PIN AF19 [get_ports {RX1_FDD_DATA[5]}]
+set_property PACKAGE_PIN AG19 [get_ports {RX1_FDD_DATA[4]}]
+set_property PACKAGE_PIN AF23 [get_ports {RX1_FDD_DATA[3]}]
+set_property PACKAGE_PIN AF24 [get_ports {RX1_FDD_DATA[2]}]
+set_property PACKAGE_PIN AA24 [get_ports {RX1_FDD_DATA[1]}]
+set_property PACKAGE_PIN AB24 [get_ports {RX1_FDD_DATA[0]}]
+set_property PACKAGE_PIN Y22  [get_ports {RX2_FDD_DATA[7]}]
+set_property PACKAGE_PIN Y23  [get_ports {RX2_FDD_DATA[6]}]
+set_property PACKAGE_PIN AC24 [get_ports {RX2_FDD_DATA[5]}]
+set_property PACKAGE_PIN AD24 [get_ports {RX2_FDD_DATA[4]}]
+set_property PACKAGE_PIN AG24 [get_ports {RX2_FDD_DATA[3]}]
+set_property PACKAGE_PIN AG25 [get_ports {RX2_FDD_DATA[2]}]
+set_property PACKAGE_PIN AF20 [get_ports {RX2_FDD_DATA[1]}]
+set_property PACKAGE_PIN AG20 [get_ports {RX2_FDD_DATA[0]}]
+set_property PACKAGE_PIN AG22 [get_ports {TX1_FDD_DATA[7]}]
+set_property PACKAGE_PIN AH22 [get_ports {TX1_FDD_DATA[6]}]
+set_property PACKAGE_PIN AA22 [get_ports {TX1_FDD_DATA[5]}]
+set_property PACKAGE_PIN AA23 [get_ports {TX1_FDD_DATA[4]}]
+set_property PACKAGE_PIN AG21 [get_ports {TX1_FDD_DATA[3]}]
+set_property PACKAGE_PIN AH21 [get_ports {TX1_FDD_DATA[2]}]
+set_property PACKAGE_PIN AD21 [get_ports {TX1_FDD_DATA[1]}]
+set_property PACKAGE_PIN AE21 [get_ports {TX1_FDD_DATA[0]}]
+set_property PACKAGE_PIN AK17 [get_ports {TX2_FDD_DATA[7]}]
+set_property PACKAGE_PIN AK18 [get_ports {TX2_FDD_DATA[6]}]
+set_property PACKAGE_PIN AJ20 [get_ports {TX2_FDD_DATA[5]}]
+set_property PACKAGE_PIN AK20 [get_ports {TX2_FDD_DATA[4]}]
+set_property PACKAGE_PIN AJ23 [get_ports {TX2_FDD_DATA[3]}]
+set_property PACKAGE_PIN AJ24 [get_ports {TX2_FDD_DATA[2]}]
+set_property PACKAGE_PIN AD23 [get_ports {TX2_FDD_DATA[1]}]
+set_property PACKAGE_PIN AE23 [get_ports {TX2_FDD_DATA[0]}]
+set_property IOSTANDARD LVCMOS25 [get_ports RXFB_MCLK_IN     ]
+set_property IOSTANDARD LVCMOS25 [get_ports RXFB_FRAME_IN    ]
+set_property IOSTANDARD LVCMOS25 [get_ports RX1_MCLK_IN_N    ]
+set_property IOSTANDARD LVCMOS25 [get_ports RX2_MCLK_IN_P    ]
+set_property IOSTANDARD LVCMOS25 [get_ports RX1_FRAME_IN_N   ]
+set_property IOSTANDARD LVCMOS25 [get_ports RX2_FRAME_IN_P   ]
+set_property IOSTANDARD LVCMOS25 [get_ports TX1_FCLK_OUT_N   ]
+set_property IOSTANDARD LVCMOS25 [get_ports TX2_FCLK_OUT_P   ]
+set_property IOSTANDARD LVCMOS25 [get_ports TX1_FRAME_OUT_N  ]
+set_property IOSTANDARD LVCMOS25 [get_ports TX2_FRAME_OUT_P  ]
+set_property IOSTANDARD LVCMOS25 [get_ports {RXFB_RX_DATA[*]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {RXFB_TX_DATA[*]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {RX1_FDD_DATA[*]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {RX2_FDD_DATA[*]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {TX1_FDD_DATA[*]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {TX2_FDD_DATA[*]}]
+###############################################################
+################################################################################################
+########### 2 #CX3E04 and Debug Interface PACKAGE_PIN and IOStandard constraints################
+######################CX3E04 Interface#########################
+set_property PACKAGE_PIN W23  [get_ports CX3E04_NRST  ]
+set_property PACKAGE_PIN AJ25 [get_ports CX3E04_CSB   ]
+set_property PACKAGE_PIN AK25 [get_ports CX3E04_SDIO  ]
+set_property PACKAGE_PIN AK22 [get_ports CX3E04_SCLK  ]
+set_property IOSTANDARD LVCMOS25 [get_ports CX3E04_NRST ]
+set_property IOSTANDARD LVCMOS25 [get_ports CX3E04_CSB  ]
+set_property IOSTANDARD LVCMOS25 [get_ports CX3E04_SDIO ]
+set_property IOSTANDARD LVCMOS25 [get_ports CX3E04_SCLK ]
+
+set_property PACKAGE_PIN AE28 [get_ports CX3E04_CLK_P ]
+set_property PACKAGE_PIN AF28 [get_ports CX3E04_CLK_N ]
+set_property PACKAGE_PIN AC29 [get_ports CX3E04_SYNC_P]
+set_property PACKAGE_PIN AD29 [get_ports CX3E04_SYNC_N]
+set_property IOSTANDARD LVDS_25 [get_ports CX3E04_CLK_P ]
+set_property IOSTANDARD LVDS_25 [get_ports CX3E04_CLK_N ]
+set_property IOSTANDARD LVDS_25 [get_ports CX3E04_SYNC_P]
+set_property IOSTANDARD LVDS_25 [get_ports CX3E04_SYNC_N]
+###############################################################
+######################Debug Interface##########################
+#set_property PACKAGE_PIN AD18 [get_ports power_on_trigger]
+#set_property IOSTANDARD LVCMOS25 [get_ports power_on_trigger]
+###############################################################
+################################################################################################
+################# 3 #clock Period/Route and hardcore Position constraints#######################
+create_clock -period 6.25 -name RX1_MCLK_IN_N -waveform {0.000 3.125} [get_ports RX1_MCLK_IN_N]
+create_clock -period 6.25 -name RX2_MCLK_IN_P -waveform {0.000 3.125} [get_ports RX2_MCLK_IN_P]
+create_clock -period 6.25 -name RXFB_MCLK_IN  -waveform {0.000 3.125} [get_ports RXFB_MCLK_IN ]
+
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets u_mclk_delay/MCLK1]
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets u_mclk_delay/MCLK2]
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets u_mclk_delay/MCLK3]
+
+set_property LOC IDELAYCTRL_X0Y2 [get_cells u_mclk_delay/IDELAYCTRL_RX12]
+set_property LOC IDELAYCTRL_X0Y4 [get_cells u_mclk_delay/IDELAYCTRL_RX3]
+################################################################################################

cx9261a_demo_cmos_20240829/project_fix_dac.srcs/constrs_1/new/cx9621a_dbg.xdc

@@ -0,0 +1,103 @@
+##################################### 1 #set false path########################################
+set_false_path -from [get_pins {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[7].ram.r/SAFETY_CKT_GEN.RSTB_SHFT_REG_reg[3]_srl3/CLK}] -to [get_pins {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[7].ram.r/SAFETY_CKT_GEN.RSTB_SHFT_REG_reg[4]/D}]
+set_false_path -from [get_pins {system_top_i/fifo_generator_0/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/SAFETY_CKT_GEN.RSTA_SHFT_REG_reg[3]_srl3/CLK}] -to [get_pins {system_top_i/fifo_generator_0/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/SAFETY_CKT_GEN.RSTA_SHFT_REG_reg[4]/D}]
+
+set_false_path -from [get_clocks RX1_MCLK_IN_N] -to [get_clocks -of_objects [get_pins system_top_i/mig_7series_0/u_system_top_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKFBOUT]]
+set_false_path -from [get_clocks RX2_MCLK_IN_P] -to [get_clocks -of_objects [get_pins system_top_i/mig_7series_0/u_system_top_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKFBOUT]]
+
+set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks RX2_MCLK_IN_P]
+################################################################################################
+#################################### 2 #CX9261A data ila########################################
+create_debug_core u_ila_0 ila
+set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
+set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0]
+set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0]
+set_property C_DATA_DEPTH 16384 [get_debug_cores u_ila_0]
+set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0]
+set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
+set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
+set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
+set_property port_width 1 [get_debug_ports u_ila_0/clk]
+connect_debug_port u_ila_0/clk [get_nets [list system_top_i/processing_system7_0/inst/FCLK_CLK0]]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
+set_property port_width 24 [get_debug_ports u_ila_0/probe0]
+connect_debug_port u_ila_0/probe0 [get_nets [list {hop_intr/r_hop_cnt[0]} {hop_intr/r_hop_cnt[1]} {hop_intr/r_hop_cnt[2]} {hop_intr/r_hop_cnt[3]} {hop_intr/r_hop_cnt[4]} {hop_intr/r_hop_cnt[5]} {hop_intr/r_hop_cnt[6]} {hop_intr/r_hop_cnt[7]} {hop_intr/r_hop_cnt[8]} {hop_intr/r_hop_cnt[9]} {hop_intr/r_hop_cnt[10]} {hop_intr/r_hop_cnt[11]} {hop_intr/r_hop_cnt[12]} {hop_intr/r_hop_cnt[13]} {hop_intr/r_hop_cnt[14]} {hop_intr/r_hop_cnt[15]} {hop_intr/r_hop_cnt[16]} {hop_intr/r_hop_cnt[17]} {hop_intr/r_hop_cnt[18]} {hop_intr/r_hop_cnt[19]} {hop_intr/r_hop_cnt[20]} {hop_intr/r_hop_cnt[21]} {hop_intr/r_hop_cnt[22]} {hop_intr/r_hop_cnt[23]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
+set_property port_width 1 [get_debug_ports u_ila_0/probe1]
+connect_debug_port u_ila_0/probe1 [get_nets [list hop_intr/hop_flag]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
+set_property port_width 1 [get_debug_ports u_ila_0/probe2]
+connect_debug_port u_ila_0/probe2 [get_nets [list hop_intr/r_SPI_0_0_ss_o]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
+set_property port_width 1 [get_debug_ports u_ila_0/probe3]
+connect_debug_port u_ila_0/probe3 [get_nets [list hop_intr/spi_pose_flag]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
+set_property port_width 1 [get_debug_ports u_ila_0/probe4]
+connect_debug_port u_ila_0/probe4 [get_nets [list hop_intr/r_hop_cnt_flag]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
+set_property port_width 1 [get_debug_ports u_ila_0/probe5]
+connect_debug_port u_ila_0/probe5 [get_nets [list hop_intr/hop_neg_flag]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
+set_property port_width 1 [get_debug_ports u_ila_0/probe6]
+connect_debug_port u_ila_0/probe6 [get_nets [list hop_intr/hop_signal]]
+create_debug_core u_ila_1 ila
+set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_1]
+set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_1]
+set_property C_ADV_TRIGGER true [get_debug_cores u_ila_1]
+set_property C_DATA_DEPTH 16384 [get_debug_cores u_ila_1]
+set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_1]
+set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_1]
+set_property C_TRIGIN_EN false [get_debug_cores u_ila_1]
+set_property C_TRIGOUT_EN false [get_debug_cores u_ila_1]
+set_property port_width 1 [get_debug_ports u_ila_1/clk]
+connect_debug_port u_ila_1/clk [get_nets [list cx9261a_if_cmos/u_cx9261a_if_cmos_port/mclk_g1]]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe0]
+set_property port_width 16 [get_debug_ports u_ila_1/probe0]
+connect_debug_port u_ila_1/probe0 [get_nets [list {rx1_i_data[0]} {rx1_i_data[1]} {rx1_i_data[2]} {rx1_i_data[3]} {rx1_i_data[4]} {rx1_i_data[5]} {rx1_i_data[6]} {rx1_i_data[7]} {rx1_i_data[8]} {rx1_i_data[9]} {rx1_i_data[10]} {rx1_i_data[11]} {rx1_i_data[12]} {rx1_i_data[13]} {rx1_i_data[14]} {rx1_i_data[15]}]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe1]
+set_property port_width 16 [get_debug_ports u_ila_1/probe1]
+connect_debug_port u_ila_1/probe1 [get_nets [list {rx2_q_data[0]} {rx2_q_data[1]} {rx2_q_data[2]} {rx2_q_data[3]} {rx2_q_data[4]} {rx2_q_data[5]} {rx2_q_data[6]} {rx2_q_data[7]} {rx2_q_data[8]} {rx2_q_data[9]} {rx2_q_data[10]} {rx2_q_data[11]} {rx2_q_data[12]} {rx2_q_data[13]} {rx2_q_data[14]} {rx2_q_data[15]}]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe2]
+set_property port_width 16 [get_debug_ports u_ila_1/probe2]
+connect_debug_port u_ila_1/probe2 [get_nets [list {tx1_i_data[0]} {tx1_i_data[1]} {tx1_i_data[2]} {tx1_i_data[3]} {tx1_i_data[4]} {tx1_i_data[5]} {tx1_i_data[6]} {tx1_i_data[7]} {tx1_i_data[8]} {tx1_i_data[9]} {tx1_i_data[10]} {tx1_i_data[11]} {tx1_i_data[12]} {tx1_i_data[13]} {tx1_i_data[14]} {tx1_i_data[15]}]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe3]
+set_property port_width 16 [get_debug_ports u_ila_1/probe3]
+connect_debug_port u_ila_1/probe3 [get_nets [list {tx2_q_data[0]} {tx2_q_data[1]} {tx2_q_data[2]} {tx2_q_data[3]} {tx2_q_data[4]} {tx2_q_data[5]} {tx2_q_data[6]} {tx2_q_data[7]} {tx2_q_data[8]} {tx2_q_data[9]} {tx2_q_data[10]} {tx2_q_data[11]} {tx2_q_data[12]} {tx2_q_data[13]} {tx2_q_data[14]} {tx2_q_data[15]}]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe4]
+set_property port_width 16 [get_debug_ports u_ila_1/probe4]
+connect_debug_port u_ila_1/probe4 [get_nets [list {rx2_i_data[0]} {rx2_i_data[1]} {rx2_i_data[2]} {rx2_i_data[3]} {rx2_i_data[4]} {rx2_i_data[5]} {rx2_i_data[6]} {rx2_i_data[7]} {rx2_i_data[8]} {rx2_i_data[9]} {rx2_i_data[10]} {rx2_i_data[11]} {rx2_i_data[12]} {rx2_i_data[13]} {rx2_i_data[14]} {rx2_i_data[15]}]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe5]
+set_property port_width 16 [get_debug_ports u_ila_1/probe5]
+connect_debug_port u_ila_1/probe5 [get_nets [list {rx1_q_data[0]} {rx1_q_data[1]} {rx1_q_data[2]} {rx1_q_data[3]} {rx1_q_data[4]} {rx1_q_data[5]} {rx1_q_data[6]} {rx1_q_data[7]} {rx1_q_data[8]} {rx1_q_data[9]} {rx1_q_data[10]} {rx1_q_data[11]} {rx1_q_data[12]} {rx1_q_data[13]} {rx1_q_data[14]} {rx1_q_data[15]}]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe6]
+set_property port_width 16 [get_debug_ports u_ila_1/probe6]
+connect_debug_port u_ila_1/probe6 [get_nets [list {rx3_q_data[0]} {rx3_q_data[1]} {rx3_q_data[2]} {rx3_q_data[3]} {rx3_q_data[4]} {rx3_q_data[5]} {rx3_q_data[6]} {rx3_q_data[7]} {rx3_q_data[8]} {rx3_q_data[9]} {rx3_q_data[10]} {rx3_q_data[11]} {rx3_q_data[12]} {rx3_q_data[13]} {rx3_q_data[14]} {rx3_q_data[15]}]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe7]
+set_property port_width 16 [get_debug_ports u_ila_1/probe7]
+connect_debug_port u_ila_1/probe7 [get_nets [list {rx3_i_data[0]} {rx3_i_data[1]} {rx3_i_data[2]} {rx3_i_data[3]} {rx3_i_data[4]} {rx3_i_data[5]} {rx3_i_data[6]} {rx3_i_data[7]} {rx3_i_data[8]} {rx3_i_data[9]} {rx3_i_data[10]} {rx3_i_data[11]} {rx3_i_data[12]} {rx3_i_data[13]} {rx3_i_data[14]} {rx3_i_data[15]}]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe8]
+set_property port_width 16 [get_debug_ports u_ila_1/probe8]
+connect_debug_port u_ila_1/probe8 [get_nets [list {tx2_i_data[0]} {tx2_i_data[1]} {tx2_i_data[2]} {tx2_i_data[3]} {tx2_i_data[4]} {tx2_i_data[5]} {tx2_i_data[6]} {tx2_i_data[7]} {tx2_i_data[8]} {tx2_i_data[9]} {tx2_i_data[10]} {tx2_i_data[11]} {tx2_i_data[12]} {tx2_i_data[13]} {tx2_i_data[14]} {tx2_i_data[15]}]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe9]
+set_property port_width 16 [get_debug_ports u_ila_1/probe9]
+connect_debug_port u_ila_1/probe9 [get_nets [list {tx1_q_data[0]} {tx1_q_data[1]} {tx1_q_data[2]} {tx1_q_data[3]} {tx1_q_data[4]} {tx1_q_data[5]} {tx1_q_data[6]} {tx1_q_data[7]} {tx1_q_data[8]} {tx1_q_data[9]} {tx1_q_data[10]} {tx1_q_data[11]} {tx1_q_data[12]} {tx1_q_data[13]} {tx1_q_data[14]} {tx1_q_data[15]}]]
+set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
+set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
+set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
+connect_debug_port dbg_hub/clk [get_nets MCLK2]
+################################################################################################

cx9261a_demo_cmos_20240829/project_fix_dac.srcs/constrs_1/new/cx9621a_dbg2.xdc

@@ -0,0 +1,163 @@
+set_false_path -from [get_pins {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[7].ram.r/SAFETY_CKT_GEN.RSTB_SHFT_REG_reg[3]_srl3/CLK}] -to [get_pins {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[7].ram.r/SAFETY_CKT_GEN.RSTB_SHFT_REG_reg[4]/D}]
+set_false_path -from [get_pins {system_top_i/fifo_generator_0/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/SAFETY_CKT_GEN.RSTA_SHFT_REG_reg[3]_srl3/CLK}] -to [get_pins {system_top_i/fifo_generator_0/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/SAFETY_CKT_GEN.RSTA_SHFT_REG_reg[4]/D}]
+
+
+
+
+
+create_debug_core u_ila_0 ila
+set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
+set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
+set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
+set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
+set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
+set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
+set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
+set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
+set_property port_width 1 [get_debug_ports u_ila_0/clk]
+connect_debug_port u_ila_0/clk [get_nets [list cx9261a_if_cmos/u_cx9261a_if_cmos_port/mclk_g1]]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
+set_property port_width 8 [get_debug_ports u_ila_0/probe0]
+connect_debug_port u_ila_0/probe0 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
+set_property port_width 8 [get_debug_ports u_ila_0/probe1]
+connect_debug_port u_ila_0/probe1 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
+set_property port_width 8 [get_debug_ports u_ila_0/probe2]
+connect_debug_port u_ila_0/probe2 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA_pos_o[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA_pos_o[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA_pos_o[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA_pos_o[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA_pos_o[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA_pos_o[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA_pos_o[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA_pos_o[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
+set_property port_width 8 [get_debug_ports u_ila_0/probe3]
+connect_debug_port u_ila_0/probe3 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA_neg_o[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA_neg_o[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA_neg_o[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA_neg_o[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA_neg_o[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA_neg_o[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA_neg_o[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA_neg_o[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
+set_property port_width 8 [get_debug_ports u_ila_0/probe4]
+connect_debug_port u_ila_0/probe4 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA_pos_o[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA_pos_o[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA_pos_o[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA_pos_o[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA_pos_o[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA_pos_o[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA_pos_o[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA_pos_o[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
+set_property port_width 8 [get_debug_ports u_ila_0/probe5]
+connect_debug_port u_ila_0/probe5 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA_neg_o[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA_neg_o[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA_neg_o[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA_neg_o[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA_neg_o[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA_neg_o[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA_neg_o[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA_neg_o[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
+set_property port_width 16 [get_debug_ports u_ila_0/probe6]
+connect_debug_port u_ila_0/probe6 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_i_data[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_i_data[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_i_data[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_i_data[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_i_data[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_i_data[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_i_data[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_i_data[7]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_i_data[8]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_i_data[9]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_i_data[10]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_i_data[11]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_i_data[12]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_i_data[13]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_i_data[14]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_i_data[15]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
+set_property port_width 16 [get_debug_ports u_ila_0/probe7]
+connect_debug_port u_ila_0/probe7 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_q_data[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_q_data[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_q_data[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_q_data[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_q_data[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_q_data[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_q_data[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_q_data[7]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_q_data[8]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_q_data[9]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_q_data[10]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_q_data[11]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_q_data[12]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_q_data[13]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_q_data[14]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_q_data[15]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
+set_property port_width 16 [get_debug_ports u_ila_0/probe8]
+connect_debug_port u_ila_0/probe8 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_i_data[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_i_data[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_i_data[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_i_data[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_i_data[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_i_data[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_i_data[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_i_data[7]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_i_data[8]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_i_data[9]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_i_data[10]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_i_data[11]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_i_data[12]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_i_data[13]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_i_data[14]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_i_data[15]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
+set_property port_width 16 [get_debug_ports u_ila_0/probe9]
+connect_debug_port u_ila_0/probe9 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_q_data[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_q_data[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_q_data[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_q_data[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_q_data[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_q_data[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_q_data[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_q_data[7]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_q_data[8]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_q_data[9]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_q_data[10]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_q_data[11]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_q_data[12]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_q_data[13]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_q_data[14]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_q_data[15]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
+set_property port_width 1 [get_debug_ports u_ila_0/probe10]
+connect_debug_port u_ila_0/probe10 [get_nets [list cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_data_valid]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
+set_property port_width 1 [get_debug_ports u_ila_0/probe11]
+connect_debug_port u_ila_0/probe11 [get_nets [list cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_data_ready]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
+set_property port_width 1 [get_debug_ports u_ila_0/probe12]
+connect_debug_port u_ila_0/probe12 [get_nets [list cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_frame_neg]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
+set_property port_width 1 [get_debug_ports u_ila_0/probe13]
+connect_debug_port u_ila_0/probe13 [get_nets [list cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_frame_pos]]
+create_debug_core u_ila_1 ila
+set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_1]
+set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_1]
+set_property C_ADV_TRIGGER false [get_debug_cores u_ila_1]
+set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_1]
+set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_1]
+set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_1]
+set_property C_TRIGIN_EN false [get_debug_cores u_ila_1]
+set_property C_TRIGOUT_EN false [get_debug_cores u_ila_1]
+set_property port_width 1 [get_debug_ports u_ila_1/clk]
+connect_debug_port u_ila_1/clk [get_nets [list cx9261a_if_cmos/u_cx9261a_if_cmos_port/data_clk2]]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe0]
+set_property port_width 2 [get_debug_ports u_ila_1/probe0]
+connect_debug_port u_ila_1/probe0 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX_FRAME_N[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX_FRAME_N[1]}]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe1]
+set_property port_width 8 [get_debug_ports u_ila_1/probe1]
+connect_debug_port u_ila_1/probe1 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA_neg_o[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA_neg_o[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA_neg_o[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA_neg_o[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA_neg_o[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA_neg_o[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA_neg_o[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA_neg_o[7]}]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe2]
+set_property port_width 8 [get_debug_ports u_ila_1/probe2]
+connect_debug_port u_ila_1/probe2 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA[7]}]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe3]
+set_property port_width 8 [get_debug_ports u_ila_1/probe3]
+connect_debug_port u_ila_1/probe3 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA_neg_o[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA_neg_o[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA_neg_o[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA_neg_o[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA_neg_o[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA_neg_o[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA_neg_o[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA_neg_o[7]}]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe4]
+set_property port_width 8 [get_debug_ports u_ila_1/probe4]
+connect_debug_port u_ila_1/probe4 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA_pos_o[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA_pos_o[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA_pos_o[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA_pos_o[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA_pos_o[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA_pos_o[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA_pos_o[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA_pos_o[7]}]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe5]
+set_property port_width 8 [get_debug_ports u_ila_1/probe5]
+connect_debug_port u_ila_1/probe5 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA_pos_o[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA_pos_o[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA_pos_o[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA_pos_o[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA_pos_o[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA_pos_o[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA_pos_o[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA_pos_o[7]}]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe6]
+set_property port_width 8 [get_debug_ports u_ila_1/probe6]
+connect_debug_port u_ila_1/probe6 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA[7]}]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe7]
+set_property port_width 16 [get_debug_ports u_ila_1/probe7]
+connect_debug_port u_ila_1/probe7 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_q_data[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_q_data[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_q_data[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_q_data[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_q_data[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_q_data[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_q_data[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_q_data[7]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_q_data[8]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_q_data[9]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_q_data[10]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_q_data[11]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_q_data[12]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_q_data[13]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_q_data[14]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_q_data[15]}]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe8]
+set_property port_width 16 [get_debug_ports u_ila_1/probe8]
+connect_debug_port u_ila_1/probe8 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_i_data[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_i_data[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_i_data[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_i_data[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_i_data[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_i_data[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_i_data[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_i_data[7]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_i_data[8]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_i_data[9]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_i_data[10]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_i_data[11]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_i_data[12]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_i_data[13]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_i_data[14]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_i_data[15]}]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe9]
+set_property port_width 16 [get_debug_ports u_ila_1/probe9]
+connect_debug_port u_ila_1/probe9 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_i_data[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_i_data[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_i_data[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_i_data[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_i_data[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_i_data[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_i_data[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_i_data[7]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_i_data[8]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_i_data[9]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_i_data[10]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_i_data[11]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_i_data[12]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_i_data[13]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_i_data[14]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_i_data[15]}]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe10]
+set_property port_width 16 [get_debug_ports u_ila_1/probe10]
+connect_debug_port u_ila_1/probe10 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_q_data[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_q_data[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_q_data[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_q_data[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_q_data[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_q_data[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_q_data[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_q_data[7]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_q_data[8]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_q_data[9]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_q_data[10]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_q_data[11]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_q_data[12]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_q_data[13]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_q_data[14]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_q_data[15]}]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe11]
+set_property port_width 1 [get_debug_ports u_ila_1/probe11]
+connect_debug_port u_ila_1/probe11 [get_nets [list cx9261a_if_cmos/u_cx9261a_if_cmos_port/r1t1_r2t2_sel]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe12]
+set_property port_width 1 [get_debug_ports u_ila_1/probe12]
+connect_debug_port u_ila_1/probe12 [get_nets [list cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_data_valid]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe13]
+set_property port_width 1 [get_debug_ports u_ila_1/probe13]
+connect_debug_port u_ila_1/probe13 [get_nets [list cx9261a_if_cmos/u_cx9261a_if_cmos_port/sp_dp_sel]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe14]
+set_property port_width 1 [get_debug_ports u_ila_1/probe14]
+connect_debug_port u_ila_1/probe14 [get_nets [list cx9261a_if_cmos/u_cx9261a_if_cmos_port/tdd_fdd_sel]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe15]
+set_property port_width 1 [get_debug_ports u_ila_1/probe15]
+connect_debug_port u_ila_1/probe15 [get_nets [list cx9261a_if_cmos/u_cx9261a_if_cmos_port/tr_sel]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe16]
+set_property port_width 1 [get_debug_ports u_ila_1/probe16]
+connect_debug_port u_ila_1/probe16 [get_nets [list cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_data_ready]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe17]
+set_property port_width 1 [get_debug_ports u_ila_1/probe17]
+connect_debug_port u_ila_1/probe17 [get_nets [list cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_frame_neg]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe18]
+set_property port_width 1 [get_debug_ports u_ila_1/probe18]
+connect_debug_port u_ila_1/probe18 [get_nets [list cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_frame_pos]]
+set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
+set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
+set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
+connect_debug_port dbg_hub/clk [get_nets data_clk2]

cx9261a_demo_cmos_20240829/project_fix_dac.srcs/constrs_1/new/dbg.xdc

@@ -0,0 +1,763 @@
+set_property MARK_DEBUG true [get_nets {data_i[10]}]
+set_property MARK_DEBUG true [get_nets {data_i[1]}]
+set_property MARK_DEBUG true [get_nets {data_i[4]}]
+set_property MARK_DEBUG true [get_nets {data_i[6]}]
+set_property MARK_DEBUG true [get_nets {data_i[13]}]
+set_property MARK_DEBUG true [get_nets {data_q[2]}]
+set_property MARK_DEBUG true [get_nets {data_q[6]}]
+set_property MARK_DEBUG true [get_nets {data_q[10]}]
+set_property MARK_DEBUG true [get_nets {data_q[15]}]
+set_property MARK_DEBUG true [get_nets {data_i[0]}]
+set_property MARK_DEBUG true [get_nets {data_i[5]}]
+set_property MARK_DEBUG true [get_nets {data_i[8]}]
+set_property MARK_DEBUG true [get_nets {data_i[15]}]
+set_property MARK_DEBUG true [get_nets {data_q[1]}]
+set_property MARK_DEBUG true [get_nets {data_q[5]}]
+set_property MARK_DEBUG true [get_nets {data_q[8]}]
+set_property MARK_DEBUG true [get_nets {data_q[12]}]
+set_property MARK_DEBUG true [get_nets {data_i[3]}]
+set_property MARK_DEBUG true [get_nets {data_i[7]}]
+set_property MARK_DEBUG true [get_nets {data_i[12]}]
+set_property MARK_DEBUG true [get_nets {data_q[0]}]
+set_property MARK_DEBUG true [get_nets {data_q[4]}]
+set_property MARK_DEBUG true [get_nets {data_q[7]}]
+set_property MARK_DEBUG true [get_nets {data_q[13]}]
+set_property MARK_DEBUG true [get_nets {data_i[2]}]
+set_property MARK_DEBUG true [get_nets {data_i[9]}]
+set_property MARK_DEBUG true [get_nets {data_i[11]}]
+set_property MARK_DEBUG true [get_nets {data_i[14]}]
+set_property MARK_DEBUG true [get_nets {data_q[3]}]
+set_property MARK_DEBUG true [get_nets {data_q[9]}]
+set_property MARK_DEBUG true [get_nets {data_q[11]}]
+set_property MARK_DEBUG true [get_nets {data_q[14]}]
+
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_1_Q[0]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_1_Q[2]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_1_Q[4]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_1_Q[6]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_1_Q[7]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_1_Q[10]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_1_Q[12]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_1_Q[14]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_1_Q[1]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_1_Q[3]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_1_Q[5]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_1_Q[8]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_1_Q[9]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_1_Q[11]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_1_Q[13]}]
+
+set_property MARK_DEBUG true [get_nets system_top_i/CE]
+set_property MARK_DEBUG true [get_nets NRST_OBUF]
+
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[13]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[29]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[54]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[12]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[42]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[17]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[34]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[37]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[35]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[41]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[61]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[24]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[39]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[45]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[23]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[56]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[21]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[35]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[54]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[56]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[42]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[10]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[53]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[63]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[1]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[6]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[58]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[9]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[21]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[23]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[38]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[14]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[12]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[50]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[55]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[57]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[61]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[5]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[50]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[31]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[43]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[55]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[10]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[12]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[39]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[32]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[16]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[63]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[49]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[40]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[58]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[4]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[27]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[13]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[22]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[44]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[15]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[58]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[4]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[7]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[49]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[5]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[59]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[19]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[28]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[3]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[27]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[30]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[9]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[26]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[1]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[6]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[27]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[46]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[3]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[53]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[56]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[8]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[25]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[26]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[47]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[59]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[11]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[29]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[52]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[18]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[24]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[7]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[50]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[33]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[41]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[61]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[1]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[15]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[18]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[0]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[16]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[19]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[51]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[55]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[2]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[20]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[31]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[13]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[49]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[3]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[51]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[7]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[14]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[15]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[32]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[53]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[17]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[23]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[4]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[14]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[45]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[24]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[22]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[59]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[62]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[11]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[22]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[37]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[45]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[60]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[18]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[28]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[0]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[17]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[36]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[39]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[43]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[63]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[2]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[30]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[42]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[60]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[52]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[54]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[26]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[9]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[20]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[33]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[44]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[48]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[60]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[21]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[41]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[48]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[38]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[47]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[29]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[36]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[38]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[44]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[51]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[43]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[48]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[11]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[16]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[35]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[10]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[34]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[40]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[46]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[62]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[0]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[25]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[32]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[8]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[19]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[37]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[57]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[62]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[6]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[52]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[8]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[31]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[20]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[25]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[34]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[40]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[46]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[2]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[57]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[5]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[28]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[47]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[33]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[36]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[30]}]
+set_property MARK_DEBUG true [get_nets system_top_i/SPI_0_0_io0_t]
+set_property MARK_DEBUG true [get_nets system_top_i/SPI_0_0_io1_t]
+set_property MARK_DEBUG true [get_nets system_top_i/SPI_0_0_sck_o]
+set_property MARK_DEBUG true [get_nets system_top_i/SPI_0_0_ss_i]
+set_property MARK_DEBUG true [get_nets system_top_i/SPI_0_0_io0_i]
+set_property MARK_DEBUG true [get_nets system_top_i/SPI_0_0_sck_i]
+set_property MARK_DEBUG true [get_nets system_top_i/SPI_0_0_sck_t]
+set_property MARK_DEBUG true [get_nets system_top_i/SPI_0_0_ss1_o]
+set_property MARK_DEBUG true [get_nets system_top_i/SPI_0_0_ss2_o]
+set_property MARK_DEBUG true [get_nets system_top_i/SPI_0_0_io0_o]
+set_property MARK_DEBUG true [get_nets system_top_i/SPI_0_0_io1_i]
+set_property MARK_DEBUG true [get_nets system_top_i/SPI_0_0_io1_o]
+set_property MARK_DEBUG true [get_nets system_top_i/SPI_0_0_ss_o]
+set_property MARK_DEBUG true [get_nets system_top_i/SPI_0_0_ss_t]
+
+
+set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/addrb[3]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/addrb[5]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/addrb[7]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/addrb[10]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/addrb[11]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/addrb[12]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/addrb[14]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/addrb[2]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/addrb[4]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/addrb[6]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/addrb[8]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/addrb[9]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/addrb[13]}]
+set_property MARK_DEBUG true [get_nets system_top_i/blk_mem_gen_0/U0/rstb_busy]
+set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[1]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[3]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[6]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[10]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[4]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[0]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[2]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[5]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[8]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[12]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[9]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[11]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[7]}]
+
+set_property MARK_DEBUG true [get_nets system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/capture_cdc]
+set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[3]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[8]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[24]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[25]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[9]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[0]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[2]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[5]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[18]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[19]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[20]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[21]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[6]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[10]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[17]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[22]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[23]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[12]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[16]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[1]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[4]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[7]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[11]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[13]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[14]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[15]}]
+#connect_debug_port dbg_hub/clk [get_nets data_clk]
+
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_neg[3]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_neg[0]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_neg[1]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_neg[2]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_neg[4]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_neg[5]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_neg[6]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_neg[7]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_pos[0]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_pos[1]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_pos[2]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_pos[3]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_pos[4]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_pos[5]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_pos[6]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_pos[7]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_neg[4]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_neg[5]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_neg[7]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_neg[2]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_neg[3]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_neg[6]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_neg[0]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_neg[1]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_pos[0]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_pos[1]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_pos[2]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_pos[3]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_pos[4]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_pos[5]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_pos[6]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_pos[7]}]
+set_property MARK_DEBUG true [get_nets cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FRAME_neg]
+set_property MARK_DEBUG true [get_nets cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FRAME_pos]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_neg[2]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_pos[0]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_pos[6]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_neg[1]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_neg[5]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_pos[0]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_pos[4]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_pos[2]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_neg[3]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_neg[7]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_pos[1]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_neg[2]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_neg[6]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_pos[1]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_pos[7]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_pos[3]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_neg[0]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_neg[4]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_pos[4]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_pos[7]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_neg[3]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_pos[2]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_pos[5]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_neg[6]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_neg[1]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_neg[5]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_pos[5]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_neg[0]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_neg[4]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_neg[7]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_pos[3]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_pos[6]}]
+set_property MARK_DEBUG true [get_nets cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FRAME_neg]
+set_property MARK_DEBUG true [get_nets cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FRAME_pos]
+
+set_property MARK_DEBUG true [get_nets {rx1_q_data[1]}]
+set_property MARK_DEBUG true [get_nets {rx1_i_data[1]}]
+set_property MARK_DEBUG true [get_nets {rx1_i_data[8]}]
+set_property MARK_DEBUG true [get_nets {rx1_q_data[8]}]
+set_property MARK_DEBUG true [get_nets {rx2_i_data[8]}]
+set_property MARK_DEBUG true [get_nets {rx2_i_data[1]}]
+set_property MARK_DEBUG true [get_nets {rx2_q_data[1]}]
+set_property MARK_DEBUG true [get_nets {rx2_q_data[8]}]
+set_property MARK_DEBUG true [get_nets {rx1_i_data[4]}]
+set_property MARK_DEBUG true [get_nets {rx1_i_data[12]}]
+set_property MARK_DEBUG true [get_nets {rx1_q_data[4]}]
+set_property MARK_DEBUG true [get_nets {rx2_i_data[12]}]
+set_property MARK_DEBUG true [get_nets {rx1_q_data[12]}]
+set_property MARK_DEBUG true [get_nets {rx2_i_data[4]}]
+set_property MARK_DEBUG true [get_nets {rx2_q_data[4]}]
+set_property MARK_DEBUG true [get_nets {rx2_q_data[12]}]
+set_property MARK_DEBUG true [get_nets {rx1_q_data[11]}]
+set_property MARK_DEBUG true [get_nets {rx1_i_data[3]}]
+set_property MARK_DEBUG true [get_nets {rx1_i_data[11]}]
+set_property MARK_DEBUG true [get_nets {rx1_q_data[3]}]
+set_property MARK_DEBUG true [get_nets {rx2_i_data[3]}]
+set_property MARK_DEBUG true [get_nets {rx2_i_data[11]}]
+set_property MARK_DEBUG true [get_nets {rx2_q_data[3]}]
+set_property MARK_DEBUG true [get_nets {rx2_q_data[11]}]
+set_property MARK_DEBUG true [get_nets {rx1_i_data[9]}]
+set_property MARK_DEBUG true [get_nets {rx1_i_data[14]}]
+set_property MARK_DEBUG true [get_nets {rx1_q_data[6]}]
+set_property MARK_DEBUG true [get_nets {rx1_q_data[14]}]
+set_property MARK_DEBUG true [get_nets {rx2_i_data[6]}]
+set_property MARK_DEBUG true [get_nets {rx2_i_data[14]}]
+set_property MARK_DEBUG true [get_nets {rx2_q_data[6]}]
+set_property MARK_DEBUG true [get_nets {rx2_q_data[14]}]
+set_property MARK_DEBUG true [get_nets {rx1_i_data[5]}]
+set_property MARK_DEBUG true [get_nets {rx1_i_data[13]}]
+set_property MARK_DEBUG true [get_nets {rx1_q_data[5]}]
+set_property MARK_DEBUG true [get_nets {rx1_q_data[13]}]
+set_property MARK_DEBUG true [get_nets {rx2_i_data[5]}]
+set_property MARK_DEBUG true [get_nets {rx2_i_data[13]}]
+set_property MARK_DEBUG true [get_nets {rx2_q_data[5]}]
+set_property MARK_DEBUG true [get_nets {rx2_q_data[13]}]
+set_property MARK_DEBUG true [get_nets {rx1_q_data[7]}]
+set_property MARK_DEBUG true [get_nets {rx1_q_data[0]}]
+set_property MARK_DEBUG true [get_nets {rx1_i_data[6]}]
+set_property MARK_DEBUG true [get_nets {rx1_i_data[0]}]
+set_property MARK_DEBUG true [get_nets {rx2_i_data[7]}]
+set_property MARK_DEBUG true [get_nets {rx2_i_data[0]}]
+set_property MARK_DEBUG true [get_nets {rx2_q_data[0]}]
+set_property MARK_DEBUG true [get_nets {rx2_q_data[7]}]
+set_property MARK_DEBUG true [get_nets {rx1_i_data[7]}]
+set_property MARK_DEBUG true [get_nets {rx1_i_data[15]}]
+set_property MARK_DEBUG true [get_nets {rx1_q_data[9]}]
+set_property MARK_DEBUG true [get_nets {rx1_q_data[15]}]
+set_property MARK_DEBUG true [get_nets {rx2_i_data[15]}]
+set_property MARK_DEBUG true [get_nets {rx2_i_data[9]}]
+set_property MARK_DEBUG true [get_nets {rx2_q_data[9]}]
+set_property MARK_DEBUG true [get_nets {rx2_q_data[15]}]
+set_property MARK_DEBUG true [get_nets {rx1_q_data[2]}]
+set_property MARK_DEBUG true [get_nets {rx1_i_data[2]}]
+set_property MARK_DEBUG true [get_nets {rx1_i_data[10]}]
+set_property MARK_DEBUG true [get_nets {rx1_q_data[10]}]
+set_property MARK_DEBUG true [get_nets {rx2_i_data[2]}]
+set_property MARK_DEBUG true [get_nets {rx2_i_data[10]}]
+set_property MARK_DEBUG true [get_nets {rx2_q_data[2]}]
+set_property MARK_DEBUG true [get_nets {rx2_q_data[10]}]
+
+set_property MARK_DEBUG true [get_nets {tx1_i_data[4]}]
+set_property MARK_DEBUG true [get_nets {tx1_i_data[12]}]
+set_property MARK_DEBUG true [get_nets {tx1_q_data[4]}]
+set_property MARK_DEBUG true [get_nets {tx1_q_data[12]}]
+set_property MARK_DEBUG true [get_nets {tx2_i_data[12]}]
+set_property MARK_DEBUG true [get_nets {tx2_i_data[4]}]
+set_property MARK_DEBUG true [get_nets {tx2_q_data[4]}]
+set_property MARK_DEBUG true [get_nets {tx2_q_data[12]}]
+set_property MARK_DEBUG true [get_nets {tx1_q_data[1]}]
+set_property MARK_DEBUG true [get_nets {tx1_i_data[1]}]
+set_property MARK_DEBUG true [get_nets {tx1_i_data[8]}]
+set_property MARK_DEBUG true [get_nets {tx1_q_data[8]}]
+set_property MARK_DEBUG true [get_nets {tx2_i_data[1]}]
+set_property MARK_DEBUG true [get_nets {tx2_i_data[8]}]
+set_property MARK_DEBUG true [get_nets {tx2_q_data[1]}]
+set_property MARK_DEBUG true [get_nets {tx2_q_data[8]}]
+set_property MARK_DEBUG true [get_nets {tx1_i_data[2]}]
+set_property MARK_DEBUG true [get_nets {tx1_i_data[10]}]
+set_property MARK_DEBUG true [get_nets {tx1_q_data[2]}]
+set_property MARK_DEBUG true [get_nets {tx1_q_data[10]}]
+set_property MARK_DEBUG true [get_nets {tx2_i_data[2]}]
+set_property MARK_DEBUG true [get_nets {tx2_i_data[10]}]
+set_property MARK_DEBUG true [get_nets {tx2_q_data[2]}]
+set_property MARK_DEBUG true [get_nets {tx2_q_data[10]}]
+set_property MARK_DEBUG true [get_nets {tx1_i_data[15]}]
+set_property MARK_DEBUG true [get_nets {tx1_i_data[9]}]
+set_property MARK_DEBUG true [get_nets {tx1_q_data[9]}]
+set_property MARK_DEBUG true [get_nets {tx1_q_data[15]}]
+set_property MARK_DEBUG true [get_nets {tx2_i_data[9]}]
+set_property MARK_DEBUG true [get_nets {tx2_i_data[15]}]
+set_property MARK_DEBUG true [get_nets {tx2_q_data[9]}]
+set_property MARK_DEBUG true [get_nets {tx2_q_data[15]}]
+set_property MARK_DEBUG true [get_nets {tx1_q_data[7]}]
+set_property MARK_DEBUG true [get_nets {tx1_i_data[7]}]
+set_property MARK_DEBUG true [get_nets {tx1_q_data[0]}]
+set_property MARK_DEBUG true [get_nets {tx1_i_data[0]}]
+set_property MARK_DEBUG true [get_nets {tx2_i_data[0]}]
+set_property MARK_DEBUG true [get_nets {tx2_i_data[7]}]
+set_property MARK_DEBUG true [get_nets {tx2_q_data[0]}]
+set_property MARK_DEBUG true [get_nets {tx2_q_data[7]}]
+set_property MARK_DEBUG true [get_nets {tx1_i_data[5]}]
+set_property MARK_DEBUG true [get_nets {tx1_i_data[13]}]
+set_property MARK_DEBUG true [get_nets {tx1_q_data[5]}]
+set_property MARK_DEBUG true [get_nets {tx1_q_data[13]}]
+set_property MARK_DEBUG true [get_nets {tx2_i_data[13]}]
+set_property MARK_DEBUG true [get_nets {tx2_i_data[5]}]
+set_property MARK_DEBUG true [get_nets {tx2_q_data[5]}]
+set_property MARK_DEBUG true [get_nets {tx2_q_data[13]}]
+set_property MARK_DEBUG true [get_nets {tx1_i_data[14]}]
+set_property MARK_DEBUG true [get_nets {tx1_i_data[6]}]
+set_property MARK_DEBUG true [get_nets {tx1_q_data[6]}]
+set_property MARK_DEBUG true [get_nets {tx1_q_data[14]}]
+set_property MARK_DEBUG true [get_nets {tx2_i_data[6]}]
+set_property MARK_DEBUG true [get_nets {tx2_i_data[14]}]
+set_property MARK_DEBUG true [get_nets {tx2_q_data[6]}]
+set_property MARK_DEBUG true [get_nets {tx2_q_data[14]}]
+set_property MARK_DEBUG true [get_nets {tx1_i_data[3]}]
+set_property MARK_DEBUG true [get_nets {tx1_i_data[11]}]
+set_property MARK_DEBUG true [get_nets {tx1_q_data[3]}]
+set_property MARK_DEBUG true [get_nets {tx1_q_data[11]}]
+set_property MARK_DEBUG true [get_nets {tx2_i_data[11]}]
+set_property MARK_DEBUG true [get_nets {tx2_i_data[3]}]
+set_property MARK_DEBUG true [get_nets {tx2_q_data[3]}]
+set_property MARK_DEBUG true [get_nets {tx2_q_data[11]}]
+
+set_property MARK_DEBUG true [get_nets system_top_i/CE_1]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[1]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[4]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[15]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[16]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[17]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[19]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[24]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[31]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[3]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[5]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[6]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[7]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[10]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[18]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[22]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[2]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[0]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[8]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[29]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[9]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[12]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[30]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[13]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[20]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[21]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[27]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[11]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[14]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[23]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[25]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[26]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[28]}]
+create_debug_core u_ila_0 ila
+set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
+set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
+set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
+set_property C_DATA_DEPTH 8192 [get_debug_cores u_ila_0]
+set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
+set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
+set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
+set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
+set_property port_width 1 [get_debug_ports u_ila_0/clk]
+connect_debug_port u_ila_0/clk [get_nets [list system_top_i/mig_7series_0/u_system_top_mig_7series_0_0_mig/u_ddr3_infrastructure/CLK]]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
+set_property port_width 26 [get_debug_ports u_ila_0/probe0]
+connect_debug_port u_ila_0/probe0 [get_nets [list {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[0]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[1]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[2]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[3]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[4]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[5]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[6]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[7]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[8]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[9]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[10]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[11]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[12]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[13]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[14]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[15]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[16]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[17]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[18]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[19]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[20]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[21]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[22]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[23]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[24]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[25]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
+set_property port_width 64 [get_debug_ports u_ila_0/probe1]
+connect_debug_port u_ila_0/probe1 [get_nets [list {system_top_i/GPIO_0_0_tri_o[0]} {system_top_i/GPIO_0_0_tri_o[1]} {system_top_i/GPIO_0_0_tri_o[2]} {system_top_i/GPIO_0_0_tri_o[3]} {system_top_i/GPIO_0_0_tri_o[4]} {system_top_i/GPIO_0_0_tri_o[5]} {system_top_i/GPIO_0_0_tri_o[6]} {system_top_i/GPIO_0_0_tri_o[7]} {system_top_i/GPIO_0_0_tri_o[8]} {system_top_i/GPIO_0_0_tri_o[9]} {system_top_i/GPIO_0_0_tri_o[10]} {system_top_i/GPIO_0_0_tri_o[11]} {system_top_i/GPIO_0_0_tri_o[12]} {system_top_i/GPIO_0_0_tri_o[13]} {system_top_i/GPIO_0_0_tri_o[14]} {system_top_i/GPIO_0_0_tri_o[15]} {system_top_i/GPIO_0_0_tri_o[16]} {system_top_i/GPIO_0_0_tri_o[17]} {system_top_i/GPIO_0_0_tri_o[18]} {system_top_i/GPIO_0_0_tri_o[19]} {system_top_i/GPIO_0_0_tri_o[20]} {system_top_i/GPIO_0_0_tri_o[21]} {system_top_i/GPIO_0_0_tri_o[22]} {system_top_i/GPIO_0_0_tri_o[23]} {system_top_i/GPIO_0_0_tri_o[24]} {system_top_i/GPIO_0_0_tri_o[25]} {system_top_i/GPIO_0_0_tri_o[26]} {system_top_i/GPIO_0_0_tri_o[27]} {system_top_i/GPIO_0_0_tri_o[28]} {system_top_i/GPIO_0_0_tri_o[29]} {system_top_i/GPIO_0_0_tri_o[30]} {system_top_i/GPIO_0_0_tri_o[31]} {system_top_i/GPIO_0_0_tri_o[32]} {system_top_i/GPIO_0_0_tri_o[33]} {system_top_i/GPIO_0_0_tri_o[34]} {system_top_i/GPIO_0_0_tri_o[35]} {system_top_i/GPIO_0_0_tri_o[36]} {system_top_i/GPIO_0_0_tri_o[37]} {system_top_i/GPIO_0_0_tri_o[38]} {system_top_i/GPIO_0_0_tri_o[39]} {system_top_i/GPIO_0_0_tri_o[40]} {system_top_i/GPIO_0_0_tri_o[41]} {system_top_i/GPIO_0_0_tri_o[42]} {system_top_i/GPIO_0_0_tri_o[43]} {system_top_i/GPIO_0_0_tri_o[44]} {system_top_i/GPIO_0_0_tri_o[45]} {system_top_i/GPIO_0_0_tri_o[46]} {system_top_i/GPIO_0_0_tri_o[47]} {system_top_i/GPIO_0_0_tri_o[48]} {system_top_i/GPIO_0_0_tri_o[49]} {system_top_i/GPIO_0_0_tri_o[50]} {system_top_i/GPIO_0_0_tri_o[51]} {system_top_i/GPIO_0_0_tri_o[52]} {system_top_i/GPIO_0_0_tri_o[53]} {system_top_i/GPIO_0_0_tri_o[54]} {system_top_i/GPIO_0_0_tri_o[55]} {system_top_i/GPIO_0_0_tri_o[56]} {system_top_i/GPIO_0_0_tri_o[57]} {system_top_i/GPIO_0_0_tri_o[58]} {system_top_i/GPIO_0_0_tri_o[59]} {system_top_i/GPIO_0_0_tri_o[60]} {system_top_i/GPIO_0_0_tri_o[61]} {system_top_i/GPIO_0_0_tri_o[62]} {system_top_i/GPIO_0_0_tri_o[63]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
+set_property port_width 64 [get_debug_ports u_ila_0/probe2]
+connect_debug_port u_ila_0/probe2 [get_nets [list {system_top_i/GPIO_0_0_tri_t[0]} {system_top_i/GPIO_0_0_tri_t[1]} {system_top_i/GPIO_0_0_tri_t[2]} {system_top_i/GPIO_0_0_tri_t[3]} {system_top_i/GPIO_0_0_tri_t[4]} {system_top_i/GPIO_0_0_tri_t[5]} {system_top_i/GPIO_0_0_tri_t[6]} {system_top_i/GPIO_0_0_tri_t[7]} {system_top_i/GPIO_0_0_tri_t[8]} {system_top_i/GPIO_0_0_tri_t[9]} {system_top_i/GPIO_0_0_tri_t[10]} {system_top_i/GPIO_0_0_tri_t[11]} {system_top_i/GPIO_0_0_tri_t[12]} {system_top_i/GPIO_0_0_tri_t[13]} {system_top_i/GPIO_0_0_tri_t[14]} {system_top_i/GPIO_0_0_tri_t[15]} {system_top_i/GPIO_0_0_tri_t[16]} {system_top_i/GPIO_0_0_tri_t[17]} {system_top_i/GPIO_0_0_tri_t[18]} {system_top_i/GPIO_0_0_tri_t[19]} {system_top_i/GPIO_0_0_tri_t[20]} {system_top_i/GPIO_0_0_tri_t[21]} {system_top_i/GPIO_0_0_tri_t[22]} {system_top_i/GPIO_0_0_tri_t[23]} {system_top_i/GPIO_0_0_tri_t[24]} {system_top_i/GPIO_0_0_tri_t[25]} {system_top_i/GPIO_0_0_tri_t[26]} {system_top_i/GPIO_0_0_tri_t[27]} {system_top_i/GPIO_0_0_tri_t[28]} {system_top_i/GPIO_0_0_tri_t[29]} {system_top_i/GPIO_0_0_tri_t[30]} {system_top_i/GPIO_0_0_tri_t[31]} {system_top_i/GPIO_0_0_tri_t[32]} {system_top_i/GPIO_0_0_tri_t[33]} {system_top_i/GPIO_0_0_tri_t[34]} {system_top_i/GPIO_0_0_tri_t[35]} {system_top_i/GPIO_0_0_tri_t[36]} {system_top_i/GPIO_0_0_tri_t[37]} {system_top_i/GPIO_0_0_tri_t[38]} {system_top_i/GPIO_0_0_tri_t[39]} {system_top_i/GPIO_0_0_tri_t[40]} {system_top_i/GPIO_0_0_tri_t[41]} {system_top_i/GPIO_0_0_tri_t[42]} {system_top_i/GPIO_0_0_tri_t[43]} {system_top_i/GPIO_0_0_tri_t[44]} {system_top_i/GPIO_0_0_tri_t[45]} {system_top_i/GPIO_0_0_tri_t[46]} {system_top_i/GPIO_0_0_tri_t[47]} {system_top_i/GPIO_0_0_tri_t[48]} {system_top_i/GPIO_0_0_tri_t[49]} {system_top_i/GPIO_0_0_tri_t[50]} {system_top_i/GPIO_0_0_tri_t[51]} {system_top_i/GPIO_0_0_tri_t[52]} {system_top_i/GPIO_0_0_tri_t[53]} {system_top_i/GPIO_0_0_tri_t[54]} {system_top_i/GPIO_0_0_tri_t[55]} {system_top_i/GPIO_0_0_tri_t[56]} {system_top_i/GPIO_0_0_tri_t[57]} {system_top_i/GPIO_0_0_tri_t[58]} {system_top_i/GPIO_0_0_tri_t[59]} {system_top_i/GPIO_0_0_tri_t[60]} {system_top_i/GPIO_0_0_tri_t[61]} {system_top_i/GPIO_0_0_tri_t[62]} {system_top_i/GPIO_0_0_tri_t[63]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
+set_property port_width 13 [get_debug_ports u_ila_0/probe3]
+connect_debug_port u_ila_0/probe3 [get_nets [list {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[0]} {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[1]} {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[2]} {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[3]} {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[4]} {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[5]} {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[6]} {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[7]} {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[8]} {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[9]} {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[10]} {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[11]} {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[12]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
+set_property port_width 1 [get_debug_ports u_ila_0/probe4]
+connect_debug_port u_ila_0/probe4 [get_nets [list system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/capture_cdc]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
+set_property port_width 1 [get_debug_ports u_ila_0/probe5]
+connect_debug_port u_ila_0/probe5 [get_nets [list NRST_OBUF]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
+set_property port_width 1 [get_debug_ports u_ila_0/probe6]
+connect_debug_port u_ila_0/probe6 [get_nets [list system_top_i/blk_mem_gen_0/U0/rstb_busy]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
+set_property port_width 1 [get_debug_ports u_ila_0/probe7]
+connect_debug_port u_ila_0/probe7 [get_nets [list system_top_i/SPI_0_0_io0_i]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
+set_property port_width 1 [get_debug_ports u_ila_0/probe8]
+connect_debug_port u_ila_0/probe8 [get_nets [list system_top_i/SPI_0_0_io0_o]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
+set_property port_width 1 [get_debug_ports u_ila_0/probe9]
+connect_debug_port u_ila_0/probe9 [get_nets [list system_top_i/SPI_0_0_io0_t]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
+set_property port_width 1 [get_debug_ports u_ila_0/probe10]
+connect_debug_port u_ila_0/probe10 [get_nets [list system_top_i/SPI_0_0_io1_i]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
+set_property port_width 1 [get_debug_ports u_ila_0/probe11]
+connect_debug_port u_ila_0/probe11 [get_nets [list system_top_i/SPI_0_0_io1_o]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
+set_property port_width 1 [get_debug_ports u_ila_0/probe12]
+connect_debug_port u_ila_0/probe12 [get_nets [list system_top_i/SPI_0_0_io1_t]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
+set_property port_width 1 [get_debug_ports u_ila_0/probe13]
+connect_debug_port u_ila_0/probe13 [get_nets [list system_top_i/SPI_0_0_sck_i]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
+set_property port_width 1 [get_debug_ports u_ila_0/probe14]
+connect_debug_port u_ila_0/probe14 [get_nets [list system_top_i/SPI_0_0_sck_o]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
+set_property port_width 1 [get_debug_ports u_ila_0/probe15]
+connect_debug_port u_ila_0/probe15 [get_nets [list system_top_i/SPI_0_0_sck_t]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
+set_property port_width 1 [get_debug_ports u_ila_0/probe16]
+connect_debug_port u_ila_0/probe16 [get_nets [list system_top_i/SPI_0_0_ss1_o]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
+set_property port_width 1 [get_debug_ports u_ila_0/probe17]
+connect_debug_port u_ila_0/probe17 [get_nets [list system_top_i/SPI_0_0_ss2_o]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
+set_property port_width 1 [get_debug_ports u_ila_0/probe18]
+connect_debug_port u_ila_0/probe18 [get_nets [list system_top_i/SPI_0_0_ss_i]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
+set_property port_width 1 [get_debug_ports u_ila_0/probe19]
+connect_debug_port u_ila_0/probe19 [get_nets [list system_top_i/SPI_0_0_ss_o]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
+set_property port_width 1 [get_debug_ports u_ila_0/probe20]
+connect_debug_port u_ila_0/probe20 [get_nets [list system_top_i/SPI_0_0_ss_t]]
+create_debug_core u_ila_1 ila
+set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_1]
+set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_1]
+set_property C_ADV_TRIGGER false [get_debug_cores u_ila_1]
+set_property C_DATA_DEPTH 8192 [get_debug_cores u_ila_1]
+set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_1]
+set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_1]
+set_property C_TRIGIN_EN false [get_debug_cores u_ila_1]
+set_property C_TRIGOUT_EN false [get_debug_cores u_ila_1]
+set_property port_width 1 [get_debug_ports u_ila_1/clk]
+connect_debug_port u_ila_1/clk [get_nets [list cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/CLK]]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe0]
+set_property port_width 8 [get_debug_ports u_ila_1/probe0]
+connect_debug_port u_ila_1/probe0 [get_nets [list {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_neg[0]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_neg[1]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_neg[2]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_neg[3]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_neg[4]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_neg[5]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_neg[6]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_neg[7]}]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe1]
+set_property port_width 16 [get_debug_ports u_ila_1/probe1]
+connect_debug_port u_ila_1/probe1 [get_nets [list {rx1_i_data[0]} {rx1_i_data[1]} {rx1_i_data[2]} {rx1_i_data[3]} {rx1_i_data[4]} {rx1_i_data[5]} {rx1_i_data[6]} {rx1_i_data[7]} {rx1_i_data[8]} {rx1_i_data[9]} {rx1_i_data[10]} {rx1_i_data[11]} {rx1_i_data[12]} {rx1_i_data[13]} {rx1_i_data[14]} {rx1_i_data[15]}]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe2]
+set_property port_width 8 [get_debug_ports u_ila_1/probe2]
+connect_debug_port u_ila_1/probe2 [get_nets [list {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_pos[0]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_pos[1]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_pos[2]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_pos[3]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_pos[4]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_pos[5]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_pos[6]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_pos[7]}]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe3]
+set_property port_width 8 [get_debug_ports u_ila_1/probe3]
+connect_debug_port u_ila_1/probe3 [get_nets [list {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_pos[0]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_pos[1]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_pos[2]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_pos[3]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_pos[4]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_pos[5]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_pos[6]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_pos[7]}]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe4]
+set_property port_width 16 [get_debug_ports u_ila_1/probe4]
+connect_debug_port u_ila_1/probe4 [get_nets [list {tx1_i_data[0]} {tx1_i_data[1]} {tx1_i_data[2]} {tx1_i_data[3]} {tx1_i_data[4]} {tx1_i_data[5]} {tx1_i_data[6]} {tx1_i_data[7]} {tx1_i_data[8]} {tx1_i_data[9]} {tx1_i_data[10]} {tx1_i_data[11]} {tx1_i_data[12]} {tx1_i_data[13]} {tx1_i_data[14]} {tx1_i_data[15]}]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe5]
+set_property port_width 16 [get_debug_ports u_ila_1/probe5]
+connect_debug_port u_ila_1/probe5 [get_nets [list {tx1_q_data[0]} {tx1_q_data[1]} {tx1_q_data[2]} {tx1_q_data[3]} {tx1_q_data[4]} {tx1_q_data[5]} {tx1_q_data[6]} {tx1_q_data[7]} {tx1_q_data[8]} {tx1_q_data[9]} {tx1_q_data[10]} {tx1_q_data[11]} {tx1_q_data[12]} {tx1_q_data[13]} {tx1_q_data[14]} {tx1_q_data[15]}]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe6]
+set_property port_width 16 [get_debug_ports u_ila_1/probe6]
+connect_debug_port u_ila_1/probe6 [get_nets [list {rx1_q_data[0]} {rx1_q_data[1]} {rx1_q_data[2]} {rx1_q_data[3]} {rx1_q_data[4]} {rx1_q_data[5]} {rx1_q_data[6]} {rx1_q_data[7]} {rx1_q_data[8]} {rx1_q_data[9]} {rx1_q_data[10]} {rx1_q_data[11]} {rx1_q_data[12]} {rx1_q_data[13]} {rx1_q_data[14]} {rx1_q_data[15]}]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe7]
+set_property port_width 8 [get_debug_ports u_ila_1/probe7]
+connect_debug_port u_ila_1/probe7 [get_nets [list {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_neg[0]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_neg[1]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_neg[2]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_neg[3]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_neg[4]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_neg[5]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_neg[6]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_neg[7]}]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe8]
+set_property port_width 32 [get_debug_ports u_ila_1/probe8]
+connect_debug_port u_ila_1/probe8 [get_nets [list {system_top_i/c_counter_binary_1_Q[0]} {system_top_i/c_counter_binary_1_Q[1]} {system_top_i/c_counter_binary_1_Q[2]} {system_top_i/c_counter_binary_1_Q[3]} {system_top_i/c_counter_binary_1_Q[4]} {system_top_i/c_counter_binary_1_Q[5]} {system_top_i/c_counter_binary_1_Q[6]} {system_top_i/c_counter_binary_1_Q[7]} {system_top_i/c_counter_binary_1_Q[8]} {system_top_i/c_counter_binary_1_Q[9]} {system_top_i/c_counter_binary_1_Q[10]} {system_top_i/c_counter_binary_1_Q[11]} {system_top_i/c_counter_binary_1_Q[12]} {system_top_i/c_counter_binary_1_Q[13]} {system_top_i/c_counter_binary_1_Q[14]} {system_top_i/c_counter_binary_1_Q[15]} {system_top_i/c_counter_binary_1_Q[16]} {system_top_i/c_counter_binary_1_Q[17]} {system_top_i/c_counter_binary_1_Q[18]} {system_top_i/c_counter_binary_1_Q[19]} {system_top_i/c_counter_binary_1_Q[20]} {system_top_i/c_counter_binary_1_Q[21]} {system_top_i/c_counter_binary_1_Q[22]} {system_top_i/c_counter_binary_1_Q[23]} {system_top_i/c_counter_binary_1_Q[24]} {system_top_i/c_counter_binary_1_Q[25]} {system_top_i/c_counter_binary_1_Q[26]} {system_top_i/c_counter_binary_1_Q[27]} {system_top_i/c_counter_binary_1_Q[28]} {system_top_i/c_counter_binary_1_Q[29]} {system_top_i/c_counter_binary_1_Q[30]} {system_top_i/c_counter_binary_1_Q[31]}]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe9]
+set_property port_width 1 [get_debug_ports u_ila_1/probe9]
+connect_debug_port u_ila_1/probe9 [get_nets [list system_top_i/CE]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe10]
+set_property port_width 1 [get_debug_ports u_ila_1/probe10]
+connect_debug_port u_ila_1/probe10 [get_nets [list cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FRAME_neg]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe11]
+set_property port_width 1 [get_debug_ports u_ila_1/probe11]
+connect_debug_port u_ila_1/probe11 [get_nets [list cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FRAME_pos]]
+create_debug_core u_ila_2 ila
+set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_2]
+set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_2]
+set_property C_ADV_TRIGGER false [get_debug_cores u_ila_2]
+set_property C_DATA_DEPTH 8192 [get_debug_cores u_ila_2]
+set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_2]
+set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_2]
+set_property C_TRIGIN_EN false [get_debug_cores u_ila_2]
+set_property C_TRIGOUT_EN false [get_debug_cores u_ila_2]
+set_property port_width 1 [get_debug_ports u_ila_2/clk]
+connect_debug_port u_ila_2/clk [get_nets [list cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/CLK]]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe0]
+set_property port_width 16 [get_debug_ports u_ila_2/probe0]
+connect_debug_port u_ila_2/probe0 [get_nets [list {rx2_i_data[0]} {rx2_i_data[1]} {rx2_i_data[2]} {rx2_i_data[3]} {rx2_i_data[4]} {rx2_i_data[5]} {rx2_i_data[6]} {rx2_i_data[7]} {rx2_i_data[8]} {rx2_i_data[9]} {rx2_i_data[10]} {rx2_i_data[11]} {rx2_i_data[12]} {rx2_i_data[13]} {rx2_i_data[14]} {rx2_i_data[15]}]]
+create_debug_port u_ila_2 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe1]
+set_property port_width 8 [get_debug_ports u_ila_2/probe1]
+connect_debug_port u_ila_2/probe1 [get_nets [list {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_neg[0]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_neg[1]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_neg[2]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_neg[3]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_neg[4]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_neg[5]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_neg[6]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_neg[7]}]]
+create_debug_port u_ila_2 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe2]
+set_property port_width 8 [get_debug_ports u_ila_2/probe2]
+connect_debug_port u_ila_2/probe2 [get_nets [list {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_neg[0]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_neg[1]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_neg[2]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_neg[3]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_neg[4]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_neg[5]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_neg[6]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_neg[7]}]]
+create_debug_port u_ila_2 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe3]
+set_property port_width 16 [get_debug_ports u_ila_2/probe3]
+connect_debug_port u_ila_2/probe3 [get_nets [list {tx2_i_data[0]} {tx2_i_data[1]} {tx2_i_data[2]} {tx2_i_data[3]} {tx2_i_data[4]} {tx2_i_data[5]} {tx2_i_data[6]} {tx2_i_data[7]} {tx2_i_data[8]} {tx2_i_data[9]} {tx2_i_data[10]} {tx2_i_data[11]} {tx2_i_data[12]} {tx2_i_data[13]} {tx2_i_data[14]} {tx2_i_data[15]}]]
+create_debug_port u_ila_2 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe4]
+set_property port_width 32 [get_debug_ports u_ila_2/probe4]
+connect_debug_port u_ila_2/probe4 [get_nets [list {system_top_i/c_counter_binary_2_Q[0]} {system_top_i/c_counter_binary_2_Q[1]} {system_top_i/c_counter_binary_2_Q[2]} {system_top_i/c_counter_binary_2_Q[3]} {system_top_i/c_counter_binary_2_Q[4]} {system_top_i/c_counter_binary_2_Q[5]} {system_top_i/c_counter_binary_2_Q[6]} {system_top_i/c_counter_binary_2_Q[7]} {system_top_i/c_counter_binary_2_Q[8]} {system_top_i/c_counter_binary_2_Q[9]} {system_top_i/c_counter_binary_2_Q[10]} {system_top_i/c_counter_binary_2_Q[11]} {system_top_i/c_counter_binary_2_Q[12]} {system_top_i/c_counter_binary_2_Q[13]} {system_top_i/c_counter_binary_2_Q[14]} {system_top_i/c_counter_binary_2_Q[15]} {system_top_i/c_counter_binary_2_Q[16]} {system_top_i/c_counter_binary_2_Q[17]} {system_top_i/c_counter_binary_2_Q[18]} {system_top_i/c_counter_binary_2_Q[19]} {system_top_i/c_counter_binary_2_Q[20]} {system_top_i/c_counter_binary_2_Q[21]} {system_top_i/c_counter_binary_2_Q[22]} {system_top_i/c_counter_binary_2_Q[23]} {system_top_i/c_counter_binary_2_Q[24]} {system_top_i/c_counter_binary_2_Q[25]} {system_top_i/c_counter_binary_2_Q[26]} {system_top_i/c_counter_binary_2_Q[27]} {system_top_i/c_counter_binary_2_Q[28]} {system_top_i/c_counter_binary_2_Q[29]} {system_top_i/c_counter_binary_2_Q[30]} {system_top_i/c_counter_binary_2_Q[31]}]]
+create_debug_port u_ila_2 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe5]
+set_property port_width 16 [get_debug_ports u_ila_2/probe5]
+connect_debug_port u_ila_2/probe5 [get_nets [list {tx2_q_data[0]} {tx2_q_data[1]} {tx2_q_data[2]} {tx2_q_data[3]} {tx2_q_data[4]} {tx2_q_data[5]} {tx2_q_data[6]} {tx2_q_data[7]} {tx2_q_data[8]} {tx2_q_data[9]} {tx2_q_data[10]} {tx2_q_data[11]} {tx2_q_data[12]} {tx2_q_data[13]} {tx2_q_data[14]} {tx2_q_data[15]}]]
+create_debug_port u_ila_2 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe6]
+set_property port_width 16 [get_debug_ports u_ila_2/probe6]
+connect_debug_port u_ila_2/probe6 [get_nets [list {rx2_q_data[0]} {rx2_q_data[1]} {rx2_q_data[2]} {rx2_q_data[3]} {rx2_q_data[4]} {rx2_q_data[5]} {rx2_q_data[6]} {rx2_q_data[7]} {rx2_q_data[8]} {rx2_q_data[9]} {rx2_q_data[10]} {rx2_q_data[11]} {rx2_q_data[12]} {rx2_q_data[13]} {rx2_q_data[14]} {rx2_q_data[15]}]]
+create_debug_port u_ila_2 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe7]
+set_property port_width 8 [get_debug_ports u_ila_2/probe7]
+connect_debug_port u_ila_2/probe7 [get_nets [list {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_pos[0]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_pos[1]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_pos[2]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_pos[3]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_pos[4]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_pos[5]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_pos[6]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_pos[7]}]]
+create_debug_port u_ila_2 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe8]
+set_property port_width 8 [get_debug_ports u_ila_2/probe8]
+connect_debug_port u_ila_2/probe8 [get_nets [list {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_pos[0]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_pos[1]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_pos[2]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_pos[3]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_pos[4]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_pos[5]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_pos[6]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_pos[7]}]]
+create_debug_port u_ila_2 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe9]
+set_property port_width 1 [get_debug_ports u_ila_2/probe9]
+connect_debug_port u_ila_2/probe9 [get_nets [list system_top_i/CE_1]]
+create_debug_port u_ila_2 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe10]
+set_property port_width 1 [get_debug_ports u_ila_2/probe10]
+connect_debug_port u_ila_2/probe10 [get_nets [list cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FRAME_neg]]
+create_debug_port u_ila_2 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe11]
+set_property port_width 1 [get_debug_ports u_ila_2/probe11]
+connect_debug_port u_ila_2/probe11 [get_nets [list cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FRAME_pos]]
+set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
+set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
+set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
+connect_debug_port dbg_hub/clk [get_nets ui_clk]

cx9261a_demo_cmos_20240829/project_fix_dac.srcs/sim_1/new/tb.v

@@ -0,0 +1,86 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2022/05/19 13:23:50
+// Design Name: 
+// Module Name: tb
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module tb(
+
+    );
+    reg aclk,S_AXI_ACLK;
+    
+    reg[31:0] slv_reg0,slv_reg1;
+    
+    
+    initial begin
+    aclk = 0;
+    S_AXI_ACLK = 0;
+        #100 slv_reg0 = 0;
+        #100 slv_reg1 = 8192;
+        #100 slv_reg0 = 1;
+    end
+    
+    always #2 aclk=~aclk;
+    always #1 S_AXI_ACLK=~S_AXI_ACLK;
+    
+    
+    wire capture_cdc;
+	wire [25:0] length_cdc;
+    
+    xpm_cdc_array_single #(
+      .DEST_SYNC_FF(4),   // DECIMAL; range: 2-10
+      .INIT_SYNC_FF(0),   // DECIMAL; 0=disable simulation init values, 1=enable simulation init values
+      .SIM_ASSERT_CHK(0), // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
+      .SRC_INPUT_REG(1),  // DECIMAL; 0=do not register input, 1=register input
+      .WIDTH(1)           // DECIMAL; range: 1-1024
+   )
+       xpm_cdc_array_single_inst0 (
+      .dest_out(capture_cdc), // WIDTH-bit output: src_in synchronized to the destination clock domain. This
+                           // output is registered.
+
+      .dest_clk(aclk), // 1-bit input: Clock signal for the destination clock domain.
+      .src_clk(S_AXI_ACLK),   // 1-bit input: optional; required when SRC_INPUT_REG = 1
+      .src_in(slv_reg0[0])      // WIDTH-bit input: Input single-bit array to be synchronized to destination clock
+                           // domain. It is assumed that each bit of the array is unrelated to the others. This
+                           // is reflected in the constraints applied to this macro. To transfer a binary value
+                           // losslessly across the two clock domains, use the XPM_CDC_GRAY macro instead.
+
+   );
+   
+   	   xpm_cdc_array_single #(
+      .DEST_SYNC_FF(4),   // DECIMAL; range: 2-10
+      .INIT_SYNC_FF(0),   // DECIMAL; 0=disable simulation init values, 1=enable simulation init values
+      .SIM_ASSERT_CHK(0), // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
+      .SRC_INPUT_REG(1),  // DECIMAL; 0=do not register input, 1=register input
+      .WIDTH(26)           // DECIMAL; range: 1-1024
+   )
+   xpm_cdc_array_single_inst1 (
+      .dest_out(length_cdc), // WIDTH-bit output: src_in synchronized to the destination clock domain. This
+                           // output is registered.
+
+      .dest_clk(aclk), // 1-bit input: Clock signal for the destination clock domain.
+      .src_clk(S_AXI_ACLK),   // 1-bit input: optional; required when SRC_INPUT_REG = 1
+      .src_in(slv_reg1[25:0])      // WIDTH-bit input: Input single-bit array to be synchronized to destination clock
+                           // domain. It is assumed that each bit of the array is unrelated to the others. This
+                           // is reflected in the constraints applied to this macro. To transfer a binary value
+                           // losslessly across the two clock domains, use the XPM_CDC_GRAY macro instead.
+
+   );
+   
+endmodule

cx9261a_demo_cmos_20240829/project_fix_dac.srcs/sources_1/bd/bin_rom/bin_rom.bd

@@ -0,0 +1,11 @@
+{
+  "design": {
+    "design_info": {
+      "boundary_crc": "0x0",
+      "name": "bin_rom",
+      "synth_flow_mode": "Hierarchical",
+      "tool_version": "2018.3"
+    },
+    "design_tree": {}
+  }
+}

cx9261a_demo_cmos_20240829/project_fix_dac.srcs/sources_1/bd/bin_rom/bin_rom.bxml

@@ -0,0 +1,11 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Root MajorVersion="0" MinorVersion="36">
+  <CompositeFile CompositeFileTopName="bin_rom" CanBeSetAsTop="false" CanDisplayChildGraph="true">
+    <Description>Composite Fileset</Description>
+    <Generation Name="SYNTHESIS" State="STALE" Timestamp="1700708194"/>
+    <Generation Name="IMPLEMENTATION" State="STALE" Timestamp="1700708194"/>
+    <Generation Name="SIMULATION" State="STALE" Timestamp="1700708194"/>
+    <Generation Name="HW_HANDOFF" State="STALE" Timestamp="1700708194"/>
+    <FileCollection Name="SOURCES" Type="SOURCES"/>
+  </CompositeFile>
+</Root>

cx9261a_demo_cmos_20240829/project_fix_dac.srcs/sources_1/bd/system_top/ip/system_top_Axis_adc_data_packer_0_0/system_top_Axis_adc_data_packer_0_0.xci

@@ -0,0 +1,269 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "system_top_Axis_adc_data_packer_0_0",
+    "cell_name": "Axis_adc_data_packer_0",
+    "component_reference": "labnet.com:user:Axis_adc_data_packer:1.0",
+    "ip_revision": "9",
+    "gen_directory": "../../../../../../project_fix_dac.gen/sources_1/bd/system_top/ip/system_top_Axis_adc_data_packer_0_0",
+    "parameters": {
+      "component_parameters": {
+        "C_S00_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_S00_AXI_ADDR_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_S00_AXI_BASEADDR": [ { "value": "0xFFFFFFFF", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
+        "C_S00_AXI_HIGHADDR": [ { "value": "0x00000000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
+        "Component_Name": [ { "value": "system_top_Axis_adc_data_packer_0_0", "resolve_type": "user", "usage": "all" } ]
+      },
+      "model_parameters": {
+        "C_S00_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S00_AXI_ADDR_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "zynq" } ],
+        "BASE_BOARD_PART": [ { "value": "xilinx.com:zc706:part0:1.4" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xc7z045" } ],
+        "NEXTGEN_VERSAL": [ { "value": "0" } ],
+        "PACKAGE": [ { "value": "ffg900" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Integrator" } ],
+        "IPREVISION": [ { "value": "9" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../../../project_fix_dac.gen/sources_1/bd/system_top/ip/system_top_Axis_adc_data_packer_0_0" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "../../ipshared" } ],
+        "SWVERSION": [ { "value": "2024.1" } ],
+        "SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "aclk": [ { "direction": "in" } ],
+        "aresetn": [ { "direction": "in" } ],
+        "axis_tvalid": [ { "direction": "in" } ],
+        "axis_tlast": [ { "direction": "in", "driver_value": "0" } ],
+        "axis_ready": [ { "direction": "out" } ],
+        "axis_tdata": [ { "direction": "in", "size_left": "63", "size_right": "0", "driver_value": "0" } ],
+        "m_axis_tvalid": [ { "direction": "out" } ],
+        "m_axis_tlast": [ { "direction": "out" } ],
+        "m_axis_ready": [ { "direction": "in" } ],
+        "m_axis_tdata": [ { "direction": "out", "size_left": "63", "size_right": "0" } ],
+        "s00_axi_awaddr": [ { "direction": "in", "size_left": "3", "size_right": "0" } ],
+        "s00_axi_awprot": [ { "direction": "in", "size_left": "2", "size_right": "0" } ],
+        "s00_axi_awvalid": [ { "direction": "in" } ],
+        "s00_axi_awready": [ { "direction": "out" } ],
+        "s00_axi_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
+        "s00_axi_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0" } ],
+        "s00_axi_wvalid": [ { "direction": "in" } ],
+        "s00_axi_wready": [ { "direction": "out" } ],
+        "s00_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
+        "s00_axi_bvalid": [ { "direction": "out" } ],
+        "s00_axi_bready": [ { "direction": "in" } ],
+        "s00_axi_araddr": [ { "direction": "in", "size_left": "3", "size_right": "0" } ],
+        "s00_axi_arprot": [ { "direction": "in", "size_left": "2", "size_right": "0" } ],
+        "s00_axi_arvalid": [ { "direction": "in" } ],
+        "s00_axi_arready": [ { "direction": "out" } ],
+        "s00_axi_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
+        "s00_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
+        "s00_axi_rvalid": [ { "direction": "out" } ],
+        "s00_axi_rready": [ { "direction": "in" } ],
+        "s00_axi_aclk": [ { "direction": "in" } ],
+        "s00_axi_aresetn": [ { "direction": "in" } ]
+      },
+      "interfaces": {
+        "S00_AXI": {
+          "vlnv": "xilinx.com:interface:aximm:1.0",
+          "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
+          "mode": "slave",
+          "memory_map_ref": "S00_AXI",
+          "parameters": {
+            "WIZ_DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
+            "WIZ_NUM_REG": [ { "value": "4", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
+            "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
+            "DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "ADDR_WIDTH": [ { "value": "4", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
+            "HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_PROT": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "MAX_BURST_LENGTH": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "PHASE": [ { "value": "0.000", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_top_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
+            "NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "AWADDR": [ { "physical_name": "s00_axi_awaddr" } ],
+            "AWPROT": [ { "physical_name": "s00_axi_awprot" } ],
+            "AWVALID": [ { "physical_name": "s00_axi_awvalid" } ],
+            "AWREADY": [ { "physical_name": "s00_axi_awready" } ],
+            "WDATA": [ { "physical_name": "s00_axi_wdata" } ],
+            "WSTRB": [ { "physical_name": "s00_axi_wstrb" } ],
+            "WVALID": [ { "physical_name": "s00_axi_wvalid" } ],
+            "WREADY": [ { "physical_name": "s00_axi_wready" } ],
+            "BRESP": [ { "physical_name": "s00_axi_bresp" } ],
+            "BVALID": [ { "physical_name": "s00_axi_bvalid" } ],
+            "BREADY": [ { "physical_name": "s00_axi_bready" } ],
+            "ARADDR": [ { "physical_name": "s00_axi_araddr" } ],
+            "ARPROT": [ { "physical_name": "s00_axi_arprot" } ],
+            "ARVALID": [ { "physical_name": "s00_axi_arvalid" } ],
+            "ARREADY": [ { "physical_name": "s00_axi_arready" } ],
+            "RDATA": [ { "physical_name": "s00_axi_rdata" } ],
+            "RRESP": [ { "physical_name": "s00_axi_rresp" } ],
+            "RVALID": [ { "physical_name": "s00_axi_rvalid" } ],
+            "RREADY": [ { "physical_name": "s00_axi_rready" } ]
+          }
+        },
+        "S00_AXI_RST": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "s00_axi_aresetn" } ]
+          }
+        },
+        "S00_AXI_CLK": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "S00_AXI", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "s00_axi_aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "PHASE": [ { "value": "0.000", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_top_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "s00_axi_aclk" } ]
+          }
+        },
+        "m_axis": {
+          "vlnv": "xilinx.com:interface:axis:1.0",
+          "abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "TDATA_NUM_BYTES": [ { "value": "8", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_TLAST": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_top_data_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
+            "LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "TDATA": [ { "physical_name": "m_axis_tdata" } ],
+            "TLAST": [ { "physical_name": "m_axis_tlast" } ],
+            "TVALID": [ { "physical_name": "m_axis_tvalid" } ],
+            "TREADY": [ { "physical_name": "m_axis_ready" } ]
+          }
+        },
+        "aclk": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "axis:m_axis", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_top_data_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "aclk" } ]
+          }
+        },
+        "aresetn": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "aresetn" } ]
+          }
+        },
+        "axis": {
+          "vlnv": "xilinx.com:interface:axis:1.0",
+          "abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "TDATA_NUM_BYTES": [ { "value": "8", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_TLAST": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_top_data_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
+            "LAYERED_METADATA": [ { "value": "undef", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "TDATA": [ { "physical_name": "axis_tdata" } ],
+            "TLAST": [ { "physical_name": "axis_tlast" } ],
+            "TVALID": [ { "physical_name": "axis_tvalid" } ],
+            "TREADY": [ { "physical_name": "axis_ready" } ]
+          }
+        }
+      },
+      "memory_maps": {
+        "S00_AXI": {
+          "address_blocks": {
+            "S00_AXI_reg": {
+              "base_address": "0",
+              "range": "4096",
+              "usage": "register",
+              "parameters": {
+                "OFFSET_BASE_PARAM": [ { "value": "C_S00_AXI_BASEADDR" } ],
+                "OFFSET_HIGH_PARAM": [ { "value": "C_S00_AXI_HIGHADDR" } ]
+              }
+            }
+          }
+        }
+      }
+    }
+  }
+}

cx9261a_demo_cmos_20240829/project_fix_dac.srcs/sources_1/bd/system_top/ip/system_top_Axis_adc_data_packer_1_0/system_top_Axis_adc_data_packer_1_0.xci

@@ -0,0 +1,269 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "system_top_Axis_adc_data_packer_1_0",
+    "cell_name": "Axis_adc_data_packer_1",
+    "component_reference": "labnet.com:user:Axis_adc_data_packer:1.0",
+    "ip_revision": "9",
+    "gen_directory": "../../../../../../project_fix_dac.gen/sources_1/bd/system_top/ip/system_top_Axis_adc_data_packer_1_0",
+    "parameters": {
+      "component_parameters": {
+        "C_S00_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_S00_AXI_ADDR_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_S00_AXI_BASEADDR": [ { "value": "0xFFFFFFFF", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
+        "C_S00_AXI_HIGHADDR": [ { "value": "0x00000000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
+        "Component_Name": [ { "value": "system_top_Axis_adc_data_packer_1_0", "resolve_type": "user", "usage": "all" } ]
+      },
+      "model_parameters": {
+        "C_S00_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S00_AXI_ADDR_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "zynq" } ],
+        "BASE_BOARD_PART": [ { "value": "xilinx.com:zc706:part0:1.4" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xc7z045" } ],
+        "NEXTGEN_VERSAL": [ { "value": "0" } ],
+        "PACKAGE": [ { "value": "ffg900" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Integrator" } ],
+        "IPREVISION": [ { "value": "9" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../../../project_fix_dac.gen/sources_1/bd/system_top/ip/system_top_Axis_adc_data_packer_1_0" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "../../ipshared" } ],
+        "SWVERSION": [ { "value": "2024.1" } ],
+        "SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "aclk": [ { "direction": "in" } ],
+        "aresetn": [ { "direction": "in" } ],
+        "axis_tvalid": [ { "direction": "in" } ],
+        "axis_tlast": [ { "direction": "in", "driver_value": "0" } ],
+        "axis_ready": [ { "direction": "out" } ],
+        "axis_tdata": [ { "direction": "in", "size_left": "63", "size_right": "0", "driver_value": "0" } ],
+        "m_axis_tvalid": [ { "direction": "out" } ],
+        "m_axis_tlast": [ { "direction": "out" } ],
+        "m_axis_ready": [ { "direction": "in" } ],
+        "m_axis_tdata": [ { "direction": "out", "size_left": "63", "size_right": "0" } ],
+        "s00_axi_awaddr": [ { "direction": "in", "size_left": "3", "size_right": "0" } ],
+        "s00_axi_awprot": [ { "direction": "in", "size_left": "2", "size_right": "0" } ],
+        "s00_axi_awvalid": [ { "direction": "in" } ],
+        "s00_axi_awready": [ { "direction": "out" } ],
+        "s00_axi_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
+        "s00_axi_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0" } ],
+        "s00_axi_wvalid": [ { "direction": "in" } ],
+        "s00_axi_wready": [ { "direction": "out" } ],
+        "s00_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
+        "s00_axi_bvalid": [ { "direction": "out" } ],
+        "s00_axi_bready": [ { "direction": "in" } ],
+        "s00_axi_araddr": [ { "direction": "in", "size_left": "3", "size_right": "0" } ],
+        "s00_axi_arprot": [ { "direction": "in", "size_left": "2", "size_right": "0" } ],
+        "s00_axi_arvalid": [ { "direction": "in" } ],
+        "s00_axi_arready": [ { "direction": "out" } ],
+        "s00_axi_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
+        "s00_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
+        "s00_axi_rvalid": [ { "direction": "out" } ],
+        "s00_axi_rready": [ { "direction": "in" } ],
+        "s00_axi_aclk": [ { "direction": "in" } ],
+        "s00_axi_aresetn": [ { "direction": "in" } ]
+      },
+      "interfaces": {
+        "S00_AXI": {
+          "vlnv": "xilinx.com:interface:aximm:1.0",
+          "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
+          "mode": "slave",
+          "memory_map_ref": "S00_AXI",
+          "parameters": {
+            "WIZ_DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
+            "WIZ_NUM_REG": [ { "value": "4", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
+            "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
+            "DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "ADDR_WIDTH": [ { "value": "4", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
+            "HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_PROT": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "MAX_BURST_LENGTH": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "PHASE": [ { "value": "0.000", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_top_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
+            "NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "AWADDR": [ { "physical_name": "s00_axi_awaddr" } ],
+            "AWPROT": [ { "physical_name": "s00_axi_awprot" } ],
+            "AWVALID": [ { "physical_name": "s00_axi_awvalid" } ],
+            "AWREADY": [ { "physical_name": "s00_axi_awready" } ],
+            "WDATA": [ { "physical_name": "s00_axi_wdata" } ],
+            "WSTRB": [ { "physical_name": "s00_axi_wstrb" } ],
+            "WVALID": [ { "physical_name": "s00_axi_wvalid" } ],
+            "WREADY": [ { "physical_name": "s00_axi_wready" } ],
+            "BRESP": [ { "physical_name": "s00_axi_bresp" } ],
+            "BVALID": [ { "physical_name": "s00_axi_bvalid" } ],
+            "BREADY": [ { "physical_name": "s00_axi_bready" } ],
+            "ARADDR": [ { "physical_name": "s00_axi_araddr" } ],
+            "ARPROT": [ { "physical_name": "s00_axi_arprot" } ],
+            "ARVALID": [ { "physical_name": "s00_axi_arvalid" } ],
+            "ARREADY": [ { "physical_name": "s00_axi_arready" } ],
+            "RDATA": [ { "physical_name": "s00_axi_rdata" } ],
+            "RRESP": [ { "physical_name": "s00_axi_rresp" } ],
+            "RVALID": [ { "physical_name": "s00_axi_rvalid" } ],
+            "RREADY": [ { "physical_name": "s00_axi_rready" } ]
+          }
+        },
+        "S00_AXI_RST": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "s00_axi_aresetn" } ]
+          }
+        },
+        "S00_AXI_CLK": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "S00_AXI", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "s00_axi_aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "PHASE": [ { "value": "0.000", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_top_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "s00_axi_aclk" } ]
+          }
+        },
+        "m_axis": {
+          "vlnv": "xilinx.com:interface:axis:1.0",
+          "abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "TDATA_NUM_BYTES": [ { "value": "8", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_TLAST": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_top_data_clk_1", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
+            "LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "TDATA": [ { "physical_name": "m_axis_tdata" } ],
+            "TLAST": [ { "physical_name": "m_axis_tlast" } ],
+            "TVALID": [ { "physical_name": "m_axis_tvalid" } ],
+            "TREADY": [ { "physical_name": "m_axis_ready" } ]
+          }
+        },
+        "aclk": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "axis:m_axis", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_top_data_clk_1", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "aclk" } ]
+          }
+        },
+        "aresetn": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "aresetn" } ]
+          }
+        },
+        "axis": {
+          "vlnv": "xilinx.com:interface:axis:1.0",
+          "abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "TDATA_NUM_BYTES": [ { "value": "8", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_TLAST": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_top_data_clk_1", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
+            "LAYERED_METADATA": [ { "value": "undef", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "TDATA": [ { "physical_name": "axis_tdata" } ],
+            "TLAST": [ { "physical_name": "axis_tlast" } ],
+            "TVALID": [ { "physical_name": "axis_tvalid" } ],
+            "TREADY": [ { "physical_name": "axis_ready" } ]
+          }
+        }
+      },
+      "memory_maps": {
+        "S00_AXI": {
+          "address_blocks": {
+            "S00_AXI_reg": {
+              "base_address": "0",
+              "range": "4096",
+              "usage": "register",
+              "parameters": {
+                "OFFSET_BASE_PARAM": [ { "value": "C_S00_AXI_BASEADDR" } ],
+                "OFFSET_HIGH_PARAM": [ { "value": "C_S00_AXI_HIGHADDR" } ]
+              }
+            }
+          }
+        }
+      }
+    }
+  }
+}

cx9261a_demo_cmos_20240829/project_fix_dac.srcs/sources_1/bd/system_top/ip/system_top_Axis_adc_data_packer_2_0/system_top_Axis_adc_data_packer_2_0.xci

@@ -0,0 +1,269 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "system_top_Axis_adc_data_packer_2_0",
+    "cell_name": "Axis_adc_data_packer_2",
+    "component_reference": "labnet.com:user:Axis_adc_data_packer:1.0",
+    "ip_revision": "9",
+    "gen_directory": "../../../../../../project_fix_dac.gen/sources_1/bd/system_top/ip/system_top_Axis_adc_data_packer_2_0",
+    "parameters": {
+      "component_parameters": {
+        "C_S00_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_S00_AXI_ADDR_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_S00_AXI_BASEADDR": [ { "value": "0xFFFFFFFF", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
+        "C_S00_AXI_HIGHADDR": [ { "value": "0x00000000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
+        "Component_Name": [ { "value": "system_top_Axis_adc_data_packer_2_0", "resolve_type": "user", "usage": "all" } ]
+      },
+      "model_parameters": {
+        "C_S00_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S00_AXI_ADDR_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "zynq" } ],
+        "BASE_BOARD_PART": [ { "value": "xilinx.com:zc706:part0:1.4" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xc7z045" } ],
+        "NEXTGEN_VERSAL": [ { "value": "0" } ],
+        "PACKAGE": [ { "value": "ffg900" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Integrator" } ],
+        "IPREVISION": [ { "value": "9" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../../../project_fix_dac.gen/sources_1/bd/system_top/ip/system_top_Axis_adc_data_packer_2_0" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "../../ipshared" } ],
+        "SWVERSION": [ { "value": "2024.1" } ],
+        "SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "aclk": [ { "direction": "in" } ],
+        "aresetn": [ { "direction": "in" } ],
+        "axis_tvalid": [ { "direction": "in" } ],
+        "axis_tlast": [ { "direction": "in", "driver_value": "0" } ],
+        "axis_ready": [ { "direction": "out" } ],
+        "axis_tdata": [ { "direction": "in", "size_left": "63", "size_right": "0", "driver_value": "0" } ],
+        "m_axis_tvalid": [ { "direction": "out" } ],
+        "m_axis_tlast": [ { "direction": "out" } ],
+        "m_axis_ready": [ { "direction": "in" } ],
+        "m_axis_tdata": [ { "direction": "out", "size_left": "63", "size_right": "0" } ],
+        "s00_axi_awaddr": [ { "direction": "in", "size_left": "3", "size_right": "0" } ],
+        "s00_axi_awprot": [ { "direction": "in", "size_left": "2", "size_right": "0" } ],
+        "s00_axi_awvalid": [ { "direction": "in" } ],
+        "s00_axi_awready": [ { "direction": "out" } ],
+        "s00_axi_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
+        "s00_axi_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0" } ],
+        "s00_axi_wvalid": [ { "direction": "in" } ],
+        "s00_axi_wready": [ { "direction": "out" } ],
+        "s00_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
+        "s00_axi_bvalid": [ { "direction": "out" } ],
+        "s00_axi_bready": [ { "direction": "in" } ],
+        "s00_axi_araddr": [ { "direction": "in", "size_left": "3", "size_right": "0" } ],
+        "s00_axi_arprot": [ { "direction": "in", "size_left": "2", "size_right": "0" } ],
+        "s00_axi_arvalid": [ { "direction": "in" } ],
+        "s00_axi_arready": [ { "direction": "out" } ],
+        "s00_axi_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
+        "s00_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
+        "s00_axi_rvalid": [ { "direction": "out" } ],
+        "s00_axi_rready": [ { "direction": "in" } ],
+        "s00_axi_aclk": [ { "direction": "in" } ],
+        "s00_axi_aresetn": [ { "direction": "in" } ]
+      },
+      "interfaces": {
+        "S00_AXI": {
+          "vlnv": "xilinx.com:interface:aximm:1.0",
+          "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
+          "mode": "slave",
+          "memory_map_ref": "S00_AXI",
+          "parameters": {
+            "WIZ_DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
+            "WIZ_NUM_REG": [ { "value": "4", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
+            "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
+            "DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "ADDR_WIDTH": [ { "value": "4", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
+            "HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_PROT": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "MAX_BURST_LENGTH": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "PHASE": [ { "value": "0.000", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_top_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
+            "NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "AWADDR": [ { "physical_name": "s00_axi_awaddr" } ],
+            "AWPROT": [ { "physical_name": "s00_axi_awprot" } ],
+            "AWVALID": [ { "physical_name": "s00_axi_awvalid" } ],
+            "AWREADY": [ { "physical_name": "s00_axi_awready" } ],
+            "WDATA": [ { "physical_name": "s00_axi_wdata" } ],
+            "WSTRB": [ { "physical_name": "s00_axi_wstrb" } ],
+            "WVALID": [ { "physical_name": "s00_axi_wvalid" } ],
+            "WREADY": [ { "physical_name": "s00_axi_wready" } ],
+            "BRESP": [ { "physical_name": "s00_axi_bresp" } ],
+            "BVALID": [ { "physical_name": "s00_axi_bvalid" } ],
+            "BREADY": [ { "physical_name": "s00_axi_bready" } ],
+            "ARADDR": [ { "physical_name": "s00_axi_araddr" } ],
+            "ARPROT": [ { "physical_name": "s00_axi_arprot" } ],
+            "ARVALID": [ { "physical_name": "s00_axi_arvalid" } ],
+            "ARREADY": [ { "physical_name": "s00_axi_arready" } ],
+            "RDATA": [ { "physical_name": "s00_axi_rdata" } ],
+            "RRESP": [ { "physical_name": "s00_axi_rresp" } ],
+            "RVALID": [ { "physical_name": "s00_axi_rvalid" } ],
+            "RREADY": [ { "physical_name": "s00_axi_rready" } ]
+          }
+        },
+        "S00_AXI_RST": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "s00_axi_aresetn" } ]
+          }
+        },
+        "S00_AXI_CLK": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "S00_AXI", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "s00_axi_aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "PHASE": [ { "value": "0.000", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_top_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "s00_axi_aclk" } ]
+          }
+        },
+        "m_axis": {
+          "vlnv": "xilinx.com:interface:axis:1.0",
+          "abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "TDATA_NUM_BYTES": [ { "value": "8", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_TLAST": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_top_data_clk_2", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
+            "LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "TDATA": [ { "physical_name": "m_axis_tdata" } ],
+            "TLAST": [ { "physical_name": "m_axis_tlast" } ],
+            "TVALID": [ { "physical_name": "m_axis_tvalid" } ],
+            "TREADY": [ { "physical_name": "m_axis_ready" } ]
+          }
+        },
+        "aclk": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "axis:m_axis", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_top_data_clk_2", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "aclk" } ]
+          }
+        },
+        "aresetn": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "aresetn" } ]
+          }
+        },
+        "axis": {
+          "vlnv": "xilinx.com:interface:axis:1.0",
+          "abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "TDATA_NUM_BYTES": [ { "value": "8", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_TLAST": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_top_data_clk_2", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
+            "LAYERED_METADATA": [ { "value": "undef", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "TDATA": [ { "physical_name": "axis_tdata" } ],
+            "TLAST": [ { "physical_name": "axis_tlast" } ],
+            "TVALID": [ { "physical_name": "axis_tvalid" } ],
+            "TREADY": [ { "physical_name": "axis_ready" } ]
+          }
+        }
+      },
+      "memory_maps": {
+        "S00_AXI": {
+          "address_blocks": {
+            "S00_AXI_reg": {
+              "base_address": "0",
+              "range": "4096",
+              "usage": "register",
+              "parameters": {
+                "OFFSET_BASE_PARAM": [ { "value": "C_S00_AXI_BASEADDR" } ],
+                "OFFSET_HIGH_PARAM": [ { "value": "C_S00_AXI_HIGHADDR" } ]
+              }
+            }
+          }
+        }
+      }
+    }
+  }
+}

cx9261a_demo_cmos_20240829/project_fix_dac.srcs/sources_1/bd/system_top/ip/system_top_axi4_lite_spi_0_0/system_top_axi4_lite_spi_0_0.xci

@@ -0,0 +1,184 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "system_top_axi4_lite_spi_0_0",
+    "cell_name": "axi4_lite_spi_0",
+    "component_reference": "cxkj.com:user:axi4_lite_spi:1.0",
+    "ip_revision": "2",
+    "gen_directory": "../../../../../../project_fix_dac.gen/sources_1/bd/system_top/ip/system_top_axi4_lite_spi_0_0",
+    "parameters": {
+      "component_parameters": {
+        "C_S_AXI_ADDR_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_S_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "REGS_SIZE": [ { "value": "24", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "SPI_CONFIG": [ { "value": "\"1011101\"", "value_src": "user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
+        "BAUD_RATE": [ { "value": "0x0002", "value_src": "user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
+        "REG_WIDTH": [ { "value": "8", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "CHIP_ADDR_WIDTH": [ { "value": "12", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "FOUR_WIRE_SPI": [ { "value": "false", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Component_Name": [ { "value": "system_top_axi4_lite_spi_0_0", "resolve_type": "user", "usage": "all" } ]
+      },
+      "model_parameters": {
+        "C_S_AXI_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "REGS_SIZE": [ { "value": "24", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "SPI_CONFIG": [ { "value": "\"1011101\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
+        "BAUD_RATE": [ { "value": "0x0002", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
+        "REG_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "CHIP_ADDR_WIDTH": [ { "value": "12", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "FOUR_WIRE_SPI": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "zynq" } ],
+        "BASE_BOARD_PART": [ { "value": "xilinx.com:zc706:part0:1.4" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xc7z045" } ],
+        "NEXTGEN_VERSAL": [ { "value": "0" } ],
+        "PACKAGE": [ { "value": "ffg900" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Integrator" } ],
+        "IPREVISION": [ { "value": "2" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../../../project_fix_dac.gen/sources_1/bd/system_top/ip/system_top_axi4_lite_spi_0_0" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "../../ipshared" } ],
+        "SWVERSION": [ { "value": "2024.1" } ],
+        "SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "s_axi_aclk": [ { "direction": "in" } ],
+        "s_axi_aresetn": [ { "direction": "in" } ],
+        "s_axi_awaddr": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
+        "s_axi_awvalid": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axi_awready": [ { "direction": "out" } ],
+        "s_axi_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
+        "s_axi_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "1" } ],
+        "s_axi_wvalid": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axi_wready": [ { "direction": "out" } ],
+        "s_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
+        "s_axi_bvalid": [ { "direction": "out" } ],
+        "s_axi_bready": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axi_araddr": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
+        "s_axi_arvalid": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axi_arready": [ { "direction": "out" } ],
+        "s_axi_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
+        "s_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
+        "s_axi_rvalid": [ { "direction": "out" } ],
+        "s_axi_rready": [ { "direction": "in", "driver_value": "0" } ],
+        "sclk_o": [ { "direction": "out" } ],
+        "ssn_o": [ { "direction": "out" } ],
+        "miso_i": [ { "direction": "in" } ],
+        "mosi_o": [ { "direction": "out" } ],
+        "sdio": [ { "direction": "inout" } ]
+      },
+      "interfaces": {
+        "s_axi": {
+          "vlnv": "xilinx.com:interface:aximm:1.0",
+          "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
+          "mode": "slave",
+          "memory_map_ref": "s_axi",
+          "parameters": {
+            "DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "ADDR_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_static_object": false } ],
+            "HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_PROT": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "NUM_READ_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "MAX_BURST_LENGTH": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "PHASE": [ { "value": "0.000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_top_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_static_object": false } ],
+            "NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "AWADDR": [ { "physical_name": "s_axi_awaddr" } ],
+            "AWVALID": [ { "physical_name": "s_axi_awvalid" } ],
+            "AWREADY": [ { "physical_name": "s_axi_awready" } ],
+            "WDATA": [ { "physical_name": "s_axi_wdata" } ],
+            "WSTRB": [ { "physical_name": "s_axi_wstrb" } ],
+            "WVALID": [ { "physical_name": "s_axi_wvalid" } ],
+            "WREADY": [ { "physical_name": "s_axi_wready" } ],
+            "BRESP": [ { "physical_name": "s_axi_bresp" } ],
+            "BVALID": [ { "physical_name": "s_axi_bvalid" } ],
+            "BREADY": [ { "physical_name": "s_axi_bready" } ],
+            "ARADDR": [ { "physical_name": "s_axi_araddr" } ],
+            "ARVALID": [ { "physical_name": "s_axi_arvalid" } ],
+            "ARREADY": [ { "physical_name": "s_axi_arready" } ],
+            "RDATA": [ { "physical_name": "s_axi_rdata" } ],
+            "RRESP": [ { "physical_name": "s_axi_rresp" } ],
+            "RVALID": [ { "physical_name": "s_axi_rvalid" } ],
+            "RREADY": [ { "physical_name": "s_axi_rready" } ]
+          }
+        },
+        "s_axi_aresetn": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "s_axi_aresetn" } ]
+          }
+        },
+        "s_axi_aclk": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "s_axi", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "s_axi_aresetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "PHASE": [ { "value": "0.000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_top_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "s_axi_aclk" } ]
+          }
+        }
+      },
+      "memory_maps": {
+        "s_axi": {
+          "address_blocks": {
+            "reg0": {
+              "base_address": "0",
+              "range": "4294967296",
+              "usage": "register"
+            }
+          }
+        }
+      }
+    }
+  }
+}

cx9261a_demo_cmos_20240829/project_fix_dac.srcs/sources_1/bd/system_top/ip/system_top_axi4_lite_spi_0_1/system_top_axi4_lite_spi_0_1.xci

@@ -0,0 +1,184 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "system_top_axi4_lite_spi_0_1",
+    "cell_name": "axi4_lite_spi_1",
+    "component_reference": "cxkj.com:user:axi4_lite_spi:1.0",
+    "ip_revision": "2",
+    "gen_directory": "../../../../../../project_fix_dac.gen/sources_1/bd/system_top/ip/system_top_axi4_lite_spi_0_1",
+    "parameters": {
+      "component_parameters": {
+        "C_S_AXI_ADDR_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_S_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "REGS_SIZE": [ { "value": "24", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "SPI_CONFIG": [ { "value": "\"1011101\"", "value_src": "user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
+        "BAUD_RATE": [ { "value": "0x0002", "value_src": "user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
+        "REG_WIDTH": [ { "value": "8", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "CHIP_ADDR_WIDTH": [ { "value": "13", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "FOUR_WIRE_SPI": [ { "value": "true", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Component_Name": [ { "value": "system_top_axi4_lite_spi_0_1", "resolve_type": "user", "usage": "all" } ]
+      },
+      "model_parameters": {
+        "C_S_AXI_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "REGS_SIZE": [ { "value": "24", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "SPI_CONFIG": [ { "value": "\"1011101\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
+        "BAUD_RATE": [ { "value": "0x0002", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
+        "REG_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "CHIP_ADDR_WIDTH": [ { "value": "13", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "FOUR_WIRE_SPI": [ { "value": "true", "resolve_type": "generated", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "zynq" } ],
+        "BASE_BOARD_PART": [ { "value": "xilinx.com:zc706:part0:1.4" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xc7z045" } ],
+        "NEXTGEN_VERSAL": [ { "value": "0" } ],
+        "PACKAGE": [ { "value": "ffg900" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Integrator" } ],
+        "IPREVISION": [ { "value": "2" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../../../project_fix_dac.gen/sources_1/bd/system_top/ip/system_top_axi4_lite_spi_0_1" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "../../ipshared" } ],
+        "SWVERSION": [ { "value": "2024.1" } ],
+        "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "s_axi_aclk": [ { "direction": "in" } ],
+        "s_axi_aresetn": [ { "direction": "in" } ],
+        "s_axi_awaddr": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
+        "s_axi_awvalid": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axi_awready": [ { "direction": "out" } ],
+        "s_axi_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
+        "s_axi_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "1" } ],
+        "s_axi_wvalid": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axi_wready": [ { "direction": "out" } ],
+        "s_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
+        "s_axi_bvalid": [ { "direction": "out" } ],
+        "s_axi_bready": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axi_araddr": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
+        "s_axi_arvalid": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axi_arready": [ { "direction": "out" } ],
+        "s_axi_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
+        "s_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
+        "s_axi_rvalid": [ { "direction": "out" } ],
+        "s_axi_rready": [ { "direction": "in", "driver_value": "0" } ],
+        "sclk_o": [ { "direction": "out" } ],
+        "ssn_o": [ { "direction": "out" } ],
+        "miso_i": [ { "direction": "in" } ],
+        "mosi_o": [ { "direction": "out" } ],
+        "sdio": [ { "direction": "inout" } ]
+      },
+      "interfaces": {
+        "s_axi": {
+          "vlnv": "xilinx.com:interface:aximm:1.0",
+          "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
+          "mode": "slave",
+          "memory_map_ref": "s_axi",
+          "parameters": {
+            "DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "ADDR_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_static_object": false } ],
+            "HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_PROT": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "NUM_READ_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "MAX_BURST_LENGTH": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "PHASE": [ { "value": "0.000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_top_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_static_object": false } ],
+            "NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "AWADDR": [ { "physical_name": "s_axi_awaddr" } ],
+            "AWVALID": [ { "physical_name": "s_axi_awvalid" } ],
+            "AWREADY": [ { "physical_name": "s_axi_awready" } ],
+            "WDATA": [ { "physical_name": "s_axi_wdata" } ],
+            "WSTRB": [ { "physical_name": "s_axi_wstrb" } ],
+            "WVALID": [ { "physical_name": "s_axi_wvalid" } ],
+            "WREADY": [ { "physical_name": "s_axi_wready" } ],
+            "BRESP": [ { "physical_name": "s_axi_bresp" } ],
+            "BVALID": [ { "physical_name": "s_axi_bvalid" } ],
+            "BREADY": [ { "physical_name": "s_axi_bready" } ],
+            "ARADDR": [ { "physical_name": "s_axi_araddr" } ],
+            "ARVALID": [ { "physical_name": "s_axi_arvalid" } ],
+            "ARREADY": [ { "physical_name": "s_axi_arready" } ],
+            "RDATA": [ { "physical_name": "s_axi_rdata" } ],
+            "RRESP": [ { "physical_name": "s_axi_rresp" } ],
+            "RVALID": [ { "physical_name": "s_axi_rvalid" } ],
+            "RREADY": [ { "physical_name": "s_axi_rready" } ]
+          }
+        },
+        "s_axi_aresetn": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "s_axi_aresetn" } ]
+          }
+        },
+        "s_axi_aclk": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "s_axi", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "s_axi_aresetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "PHASE": [ { "value": "0.000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_top_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "s_axi_aclk" } ]
+          }
+        }
+      },
+      "memory_maps": {
+        "s_axi": {
+          "address_blocks": {
+            "reg0": {
+              "base_address": "0",
+              "range": "4294967296",
+              "usage": "register"
+            }
+          }
+        }
+      }
+    }
+  }
+}

cx9261a_demo_cmos_20240829/project_fix_dac.srcs/sources_1/bd/system_top/ip/system_top_axi_bram_ctrl_0_0/system_top_axi_bram_ctrl_0_0.xci

@@ -0,0 +1,259 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "system_top_axi_bram_ctrl_0_0",
+    "cell_name": "axi_bram_ctrl_0",
+    "component_reference": "xilinx.com:ip:axi_bram_ctrl:4.1",
+    "ip_revision": "10",
+    "gen_directory": "../../../../../../project_fix_dac.gen/sources_1/bd/system_top/ip/system_top_axi_bram_ctrl_0_0",
+    "parameters": {
+      "component_parameters": {
+        "DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "ID_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PROTOCOL": [ { "value": "AXI4", "resolve_type": "user", "usage": "all" } ],
+        "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "SINGLE_PORT_BRAM": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "ECC_TYPE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "USE_ECC": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "FAULT_INJECT": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "ECC_ONOFF_RESET_VALUE": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Component_Name": [ { "value": "system_top_axi_bram_ctrl_0_0", "resolve_type": "user", "usage": "all" } ],
+        "BMG_INSTANCE": [ { "value": "EXTERNAL", "value_permission": "bd", "resolve_type": "user", "usage": "all" } ],
+        "MEM_DEPTH": [ { "value": "8192", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "READ_LATENCY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "RD_CMD_OPTIMIZATION": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ]
+      },
+      "model_parameters": {
+        "C_BRAM_INST_MODE": [ { "value": "EXTERNAL", "resolve_type": "generated", "usage": "all" } ],
+        "C_MEMORY_DEPTH": [ { "value": "8192", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_BRAM_ADDR_WIDTH": [ { "value": "13", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXI_ADDR_WIDTH": [ { "value": "15", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXI_ID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXI_PROTOCOL": [ { "value": "AXI4", "resolve_type": "generated", "usage": "all" } ],
+        "C_S_AXI_SUPPORTS_NARROW_BURST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_SINGLE_PORT_BRAM": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_FAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ],
+        "C_READ_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_RD_CMD_OPTIMIZATION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXI_CTRL_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXI_CTRL_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ECC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ECC_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_FAULT_INJECT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ECC_ONOFF_RESET_VALUE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "zynq" } ],
+        "BASE_BOARD_PART": [ { "value": "xilinx.com:zc706:part0:1.4" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xc7z045" } ],
+        "NEXTGEN_VERSAL": [ { "value": "0" } ],
+        "PACKAGE": [ { "value": "ffg900" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Integrator" } ],
+        "IPREVISION": [ { "value": "10" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../../../project_fix_dac.gen/sources_1/bd/system_top/ip/system_top_axi_bram_ctrl_0_0" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "../../ipshared" } ],
+        "SWVERSION": [ { "value": "2024.1" } ],
+        "SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "s_axi_aclk": [ { "direction": "in" } ],
+        "s_axi_aresetn": [ { "direction": "in" } ],
+        "s_axi_awaddr": [ { "direction": "in", "size_left": "14", "size_right": "0", "driver_value": "0" } ],
+        "s_axi_awlen": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
+        "s_axi_awsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
+        "s_axi_awburst": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
+        "s_axi_awlock": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axi_awcache": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
+        "s_axi_awprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
+        "s_axi_awvalid": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axi_awready": [ { "direction": "out" } ],
+        "s_axi_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
+        "s_axi_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
+        "s_axi_wlast": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axi_wvalid": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axi_wready": [ { "direction": "out" } ],
+        "s_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
+        "s_axi_bvalid": [ { "direction": "out" } ],
+        "s_axi_bready": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axi_araddr": [ { "direction": "in", "size_left": "14", "size_right": "0", "driver_value": "0" } ],
+        "s_axi_arlen": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
+        "s_axi_arsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
+        "s_axi_arburst": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
+        "s_axi_arlock": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axi_arcache": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
+        "s_axi_arprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
+        "s_axi_arvalid": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axi_arready": [ { "direction": "out" } ],
+        "s_axi_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
+        "s_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
+        "s_axi_rlast": [ { "direction": "out", "driver_value": "0" } ],
+        "s_axi_rvalid": [ { "direction": "out" } ],
+        "s_axi_rready": [ { "direction": "in", "driver_value": "0" } ],
+        "bram_rst_a": [ { "direction": "out" } ],
+        "bram_clk_a": [ { "direction": "out" } ],
+        "bram_en_a": [ { "direction": "out" } ],
+        "bram_we_a": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
+        "bram_addr_a": [ { "direction": "out", "size_left": "14", "size_right": "0" } ],
+        "bram_wrdata_a": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
+        "bram_rddata_a": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ]
+      },
+      "interfaces": {
+        "S_AXI": {
+          "vlnv": "xilinx.com:interface:aximm:1.0",
+          "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
+          "mode": "slave",
+          "memory_map_ref": "S_AXI",
+          "parameters": {
+            "DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "PROTOCOL": [ { "value": "AXI4", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "ID_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "ADDR_WIDTH": [ { "value": "15", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_BURST": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_LOCK": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_PROT": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_CACHE": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "MAX_BURST_LENGTH": [ { "value": "16", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_top_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "ARADDR": [ { "physical_name": "s_axi_araddr" } ],
+            "ARBURST": [ { "physical_name": "s_axi_arburst" } ],
+            "ARCACHE": [ { "physical_name": "s_axi_arcache" } ],
+            "ARLEN": [ { "physical_name": "s_axi_arlen" } ],
+            "ARLOCK": [ { "physical_name": "s_axi_arlock" } ],
+            "ARPROT": [ { "physical_name": "s_axi_arprot" } ],
+            "ARREADY": [ { "physical_name": "s_axi_arready" } ],
+            "ARSIZE": [ { "physical_name": "s_axi_arsize" } ],
+            "ARVALID": [ { "physical_name": "s_axi_arvalid" } ],
+            "AWADDR": [ { "physical_name": "s_axi_awaddr" } ],
+            "AWBURST": [ { "physical_name": "s_axi_awburst" } ],
+            "AWCACHE": [ { "physical_name": "s_axi_awcache" } ],
+            "AWLEN": [ { "physical_name": "s_axi_awlen" } ],
+            "AWLOCK": [ { "physical_name": "s_axi_awlock" } ],
+            "AWPROT": [ { "physical_name": "s_axi_awprot" } ],
+            "AWREADY": [ { "physical_name": "s_axi_awready" } ],
+            "AWSIZE": [ { "physical_name": "s_axi_awsize" } ],
+            "AWVALID": [ { "physical_name": "s_axi_awvalid" } ],
+            "BREADY": [ { "physical_name": "s_axi_bready" } ],
+            "BRESP": [ { "physical_name": "s_axi_bresp" } ],
+            "BVALID": [ { "physical_name": "s_axi_bvalid" } ],
+            "RDATA": [ { "physical_name": "s_axi_rdata" } ],
+            "RLAST": [ { "physical_name": "s_axi_rlast" } ],
+            "RREADY": [ { "physical_name": "s_axi_rready" } ],
+            "RRESP": [ { "physical_name": "s_axi_rresp" } ],
+            "RVALID": [ { "physical_name": "s_axi_rvalid" } ],
+            "WDATA": [ { "physical_name": "s_axi_wdata" } ],
+            "WLAST": [ { "physical_name": "s_axi_wlast" } ],
+            "WREADY": [ { "physical_name": "s_axi_wready" } ],
+            "WSTRB": [ { "physical_name": "s_axi_wstrb" } ],
+            "WVALID": [ { "physical_name": "s_axi_wvalid" } ]
+          }
+        },
+        "BRAM_PORTA": {
+          "vlnv": "xilinx.com:interface:bram:1.0",
+          "abstraction_type": "xilinx.com:interface:bram_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "MASTER_TYPE": [ { "value": "BRAM_CTRL", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "MEM_SIZE": [ { "value": "32768", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "MEM_WIDTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "MEM_ECC": [ { "value": "NONE", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "READ_LATENCY": [ { "value": "1", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "MEM_ADDRESS_MODE": [ { "value": "", "value_src": "weak", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "ADDR": [ { "physical_name": "bram_addr_a" } ],
+            "CLK": [ { "physical_name": "bram_clk_a" } ],
+            "DIN": [ { "physical_name": "bram_wrdata_a" } ],
+            "DOUT": [ { "physical_name": "bram_rddata_a" } ],
+            "EN": [ { "physical_name": "bram_en_a" } ],
+            "RST": [ { "physical_name": "bram_rst_a" } ],
+            "WE": [ { "physical_name": "bram_we_a" } ]
+          }
+        },
+        "RSTIF": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "s_axi_aresetn" } ]
+          }
+        },
+        "CLKIF": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "S_AXI:S_AXI_CTRL", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "s_axi_aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_top_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "s_axi_aclk" } ]
+          }
+        }
+      },
+      "memory_maps": {
+        "S_AXI": {
+          "display_name": "S_AXI_MEM",
+          "description": "Memory Map for S_AXI",
+          "address_blocks": {
+            "Mem0": {
+              "base_address": "0",
+              "range": "4096",
+              "display_name": "Mem0",
+              "description": "Register Block",
+              "usage": "memory",
+              "access": "read-write"
+            }
+          }
+        }
+      }
+    }
+  }
+}

cx9261a_demo_cmos_20240829/project_fix_dac.srcs/sources_1/bd/system_top/ip/system_top_axi_bram_ctrl_1_0/system_top_axi_bram_ctrl_1_0.xci

@@ -0,0 +1,259 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "system_top_axi_bram_ctrl_1_0",
+    "cell_name": "axi_bram_ctrl_1",
+    "component_reference": "xilinx.com:ip:axi_bram_ctrl:4.1",
+    "ip_revision": "10",
+    "gen_directory": "../../../../../../project_fix_dac.gen/sources_1/bd/system_top/ip/system_top_axi_bram_ctrl_1_0",
+    "parameters": {
+      "component_parameters": {
+        "DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "ID_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PROTOCOL": [ { "value": "AXI4", "resolve_type": "user", "usage": "all" } ],
+        "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "SINGLE_PORT_BRAM": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "ECC_TYPE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "USE_ECC": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "FAULT_INJECT": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "ECC_ONOFF_RESET_VALUE": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Component_Name": [ { "value": "system_top_axi_bram_ctrl_1_0", "resolve_type": "user", "usage": "all" } ],
+        "BMG_INSTANCE": [ { "value": "EXTERNAL", "value_permission": "bd", "resolve_type": "user", "usage": "all" } ],
+        "MEM_DEPTH": [ { "value": "8192", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "READ_LATENCY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "RD_CMD_OPTIMIZATION": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ]
+      },
+      "model_parameters": {
+        "C_BRAM_INST_MODE": [ { "value": "EXTERNAL", "resolve_type": "generated", "usage": "all" } ],
+        "C_MEMORY_DEPTH": [ { "value": "8192", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_BRAM_ADDR_WIDTH": [ { "value": "13", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXI_ADDR_WIDTH": [ { "value": "15", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXI_ID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXI_PROTOCOL": [ { "value": "AXI4", "resolve_type": "generated", "usage": "all" } ],
+        "C_S_AXI_SUPPORTS_NARROW_BURST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_SINGLE_PORT_BRAM": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_FAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ],
+        "C_READ_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_RD_CMD_OPTIMIZATION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXI_CTRL_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXI_CTRL_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ECC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ECC_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_FAULT_INJECT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ECC_ONOFF_RESET_VALUE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "zynq" } ],
+        "BASE_BOARD_PART": [ { "value": "xilinx.com:zc706:part0:1.4" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xc7z045" } ],
+        "NEXTGEN_VERSAL": [ { "value": "0" } ],
+        "PACKAGE": [ { "value": "ffg900" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Integrator" } ],
+        "IPREVISION": [ { "value": "10" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../../../project_fix_dac.gen/sources_1/bd/system_top/ip/system_top_axi_bram_ctrl_1_0" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "../../ipshared" } ],
+        "SWVERSION": [ { "value": "2024.1" } ],
+        "SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "s_axi_aclk": [ { "direction": "in" } ],
+        "s_axi_aresetn": [ { "direction": "in" } ],
+        "s_axi_awaddr": [ { "direction": "in", "size_left": "14", "size_right": "0", "driver_value": "0" } ],
+        "s_axi_awlen": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
+        "s_axi_awsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
+        "s_axi_awburst": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
+        "s_axi_awlock": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axi_awcache": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
+        "s_axi_awprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
+        "s_axi_awvalid": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axi_awready": [ { "direction": "out" } ],
+        "s_axi_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
+        "s_axi_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
+        "s_axi_wlast": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axi_wvalid": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axi_wready": [ { "direction": "out" } ],
+        "s_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
+        "s_axi_bvalid": [ { "direction": "out" } ],
+        "s_axi_bready": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axi_araddr": [ { "direction": "in", "size_left": "14", "size_right": "0", "driver_value": "0" } ],
+        "s_axi_arlen": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
+        "s_axi_arsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
+        "s_axi_arburst": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
+        "s_axi_arlock": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axi_arcache": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
+        "s_axi_arprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
+        "s_axi_arvalid": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axi_arready": [ { "direction": "out" } ],
+        "s_axi_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
+        "s_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
+        "s_axi_rlast": [ { "direction": "out", "driver_value": "0" } ],
+        "s_axi_rvalid": [ { "direction": "out" } ],
+        "s_axi_rready": [ { "direction": "in", "driver_value": "0" } ],
+        "bram_rst_a": [ { "direction": "out" } ],
+        "bram_clk_a": [ { "direction": "out" } ],
+        "bram_en_a": [ { "direction": "out" } ],
+        "bram_we_a": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
+        "bram_addr_a": [ { "direction": "out", "size_left": "14", "size_right": "0" } ],
+        "bram_wrdata_a": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
+        "bram_rddata_a": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ]
+      },
+      "interfaces": {
+        "S_AXI": {
+          "vlnv": "xilinx.com:interface:aximm:1.0",
+          "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
+          "mode": "slave",
+          "memory_map_ref": "S_AXI",
+          "parameters": {
+            "DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "PROTOCOL": [ { "value": "AXI4", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "ID_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "ADDR_WIDTH": [ { "value": "15", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_BURST": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_LOCK": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_PROT": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_CACHE": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "MAX_BURST_LENGTH": [ { "value": "16", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_top_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "ARADDR": [ { "physical_name": "s_axi_araddr" } ],
+            "ARBURST": [ { "physical_name": "s_axi_arburst" } ],
+            "ARCACHE": [ { "physical_name": "s_axi_arcache" } ],
+            "ARLEN": [ { "physical_name": "s_axi_arlen" } ],
+            "ARLOCK": [ { "physical_name": "s_axi_arlock" } ],
+            "ARPROT": [ { "physical_name": "s_axi_arprot" } ],
+            "ARREADY": [ { "physical_name": "s_axi_arready" } ],
+            "ARSIZE": [ { "physical_name": "s_axi_arsize" } ],
+            "ARVALID": [ { "physical_name": "s_axi_arvalid" } ],
+            "AWADDR": [ { "physical_name": "s_axi_awaddr" } ],
+            "AWBURST": [ { "physical_name": "s_axi_awburst" } ],
+            "AWCACHE": [ { "physical_name": "s_axi_awcache" } ],
+            "AWLEN": [ { "physical_name": "s_axi_awlen" } ],
+            "AWLOCK": [ { "physical_name": "s_axi_awlock" } ],
+            "AWPROT": [ { "physical_name": "s_axi_awprot" } ],
+            "AWREADY": [ { "physical_name": "s_axi_awready" } ],
+            "AWSIZE": [ { "physical_name": "s_axi_awsize" } ],
+            "AWVALID": [ { "physical_name": "s_axi_awvalid" } ],
+            "BREADY": [ { "physical_name": "s_axi_bready" } ],
+            "BRESP": [ { "physical_name": "s_axi_bresp" } ],
+            "BVALID": [ { "physical_name": "s_axi_bvalid" } ],
+            "RDATA": [ { "physical_name": "s_axi_rdata" } ],
+            "RLAST": [ { "physical_name": "s_axi_rlast" } ],
+            "RREADY": [ { "physical_name": "s_axi_rready" } ],
+            "RRESP": [ { "physical_name": "s_axi_rresp" } ],
+            "RVALID": [ { "physical_name": "s_axi_rvalid" } ],
+            "WDATA": [ { "physical_name": "s_axi_wdata" } ],
+            "WLAST": [ { "physical_name": "s_axi_wlast" } ],
+            "WREADY": [ { "physical_name": "s_axi_wready" } ],
+            "WSTRB": [ { "physical_name": "s_axi_wstrb" } ],
+            "WVALID": [ { "physical_name": "s_axi_wvalid" } ]
+          }
+        },
+        "BRAM_PORTA": {
+          "vlnv": "xilinx.com:interface:bram:1.0",
+          "abstraction_type": "xilinx.com:interface:bram_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "MASTER_TYPE": [ { "value": "BRAM_CTRL", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "MEM_SIZE": [ { "value": "32768", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "MEM_WIDTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "MEM_ECC": [ { "value": "NONE", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "READ_LATENCY": [ { "value": "1", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "MEM_ADDRESS_MODE": [ { "value": "", "value_src": "weak", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "ADDR": [ { "physical_name": "bram_addr_a" } ],
+            "CLK": [ { "physical_name": "bram_clk_a" } ],
+            "DIN": [ { "physical_name": "bram_wrdata_a" } ],
+            "DOUT": [ { "physical_name": "bram_rddata_a" } ],
+            "EN": [ { "physical_name": "bram_en_a" } ],
+            "RST": [ { "physical_name": "bram_rst_a" } ],
+            "WE": [ { "physical_name": "bram_we_a" } ]
+          }
+        },
+        "RSTIF": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "s_axi_aresetn" } ]
+          }
+        },
+        "CLKIF": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "S_AXI:S_AXI_CTRL", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "s_axi_aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_top_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "s_axi_aclk" } ]
+          }
+        }
+      },
+      "memory_maps": {
+        "S_AXI": {
+          "display_name": "S_AXI_MEM",
+          "description": "Memory Map for S_AXI",
+          "address_blocks": {
+            "Mem0": {
+              "base_address": "0",
+              "range": "4096",
+              "display_name": "Mem0",
+              "description": "Register Block",
+              "usage": "memory",
+              "access": "read-write"
+            }
+          }
+        }
+      }
+    }
+  }
+}

cx9261a_demo_cmos_20240829/project_fix_dac.srcs/sources_1/bd/system_top/ip/system_top_axi_dma_0_0/system_top_axi_dma_0_0.xci

@@ -0,0 +1,976 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "system_top_axi_dma_0_0",
+    "cell_name": "axi_dma_0",
+    "component_reference": "xilinx.com:ip:axi_dma:7.1",
+    "ip_revision": "32",
+    "gen_directory": "../../../../../../project_fix_dac.gen/sources_1/bd/system_top/ip/system_top_axi_dma_0_0",
+    "parameters": {
+      "component_parameters": {
+        "Component_Name": [ { "value": "system_top_axi_dma_0_0", "resolve_type": "user", "usage": "all" } ],
+        "c_include_sg": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "c_enable_multi_channel": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "c_num_mm2s_channels": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "c_num_s2mm_channels": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "c_sg_length_width": [ { "value": "26", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "c_dlytmr_resolution": [ { "value": "125", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "c_prmry_is_aclk_async": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "c_sg_include_stscntrl_strm": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "c_micro_dma": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "c_include_mm2s": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "c_m_axi_mm2s_data_width": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "c_m_axis_mm2s_tdata_width": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "c_include_mm2s_dre": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "c_include_mm2s_sf": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "c_mm2s_burst_size": [ { "value": "16", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "c_include_s2mm": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "c_sg_use_stsapp_length": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "c_m_axi_s2mm_data_width": [ { "value": "64", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "c_s_axis_s2mm_tdata_width": [ { "value": "64", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "c_include_s2mm_dre": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "c_include_s2mm_sf": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "c_s2mm_burst_size": [ { "value": "16", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "c_addr_width": [ { "value": "40", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "c_single_interface": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "c_increase_throughput": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ]
+      },
+      "model_parameters": {
+        "C_S_AXI_LITE_ADDR_WIDTH": [ { "value": "10", "format": "long", "usage": "all" } ],
+        "C_S_AXI_LITE_DATA_WIDTH": [ { "value": "32", "format": "long", "usage": "all" } ],
+        "C_DLYTMR_RESOLUTION": [ { "value": "125", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PRMRY_IS_ACLK_ASYNC": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ENABLE_MULTI_CHANNEL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_NUM_MM2S_CHANNELS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_NUM_S2MM_CHANNELS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_INCLUDE_SG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_SG_INCLUDE_STSCNTRL_STRM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_SG_USE_STSAPP_LENGTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_SG_LENGTH_WIDTH": [ { "value": "26", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_M_AXI_SG_ADDR_WIDTH": [ { "value": "40", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_M_AXI_SG_DATA_WIDTH": [ { "value": "32", "format": "long", "usage": "all" } ],
+        "C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_S_AXIS_S2MM_STS_TDATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_MICRO_DMA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_INCLUDE_MM2S": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_INCLUDE_MM2S_SF": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_MM2S_BURST_SIZE": [ { "value": "16", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_M_AXI_MM2S_ADDR_WIDTH": [ { "value": "40", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_M_AXI_MM2S_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_M_AXIS_MM2S_TDATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_INCLUDE_MM2S_DRE": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_INCLUDE_S2MM": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_INCLUDE_S2MM_SF": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S2MM_BURST_SIZE": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_M_AXI_S2MM_ADDR_WIDTH": [ { "value": "40", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_M_AXI_S2MM_DATA_WIDTH": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXIS_S2MM_TDATA_WIDTH": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_INCLUDE_S2MM_DRE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_INCREASE_THROUGHPUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_FAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "zynq" } ],
+        "BASE_BOARD_PART": [ { "value": "xilinx.com:zc706:part0:1.4" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xc7z045" } ],
+        "NEXTGEN_VERSAL": [ { "value": "0" } ],
+        "PACKAGE": [ { "value": "ffg900" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Integrator" } ],
+        "IPREVISION": [ { "value": "32" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../../../project_fix_dac.gen/sources_1/bd/system_top/ip/system_top_axi_dma_0_0" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "../../ipshared" } ],
+        "SWVERSION": [ { "value": "2024.1" } ],
+        "SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "s_axi_lite_aclk": [ { "direction": "in", "driver_value": "0" } ],
+        "m_axi_s2mm_aclk": [ { "direction": "in", "driver_value": "0" } ],
+        "axi_resetn": [ { "direction": "in", "driver_value": "1" } ],
+        "s_axi_lite_awvalid": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axi_lite_awready": [ { "direction": "out" } ],
+        "s_axi_lite_awaddr": [ { "direction": "in", "size_left": "9", "size_right": "0", "driver_value": "0" } ],
+        "s_axi_lite_wvalid": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axi_lite_wready": [ { "direction": "out" } ],
+        "s_axi_lite_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
+        "s_axi_lite_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
+        "s_axi_lite_bvalid": [ { "direction": "out" } ],
+        "s_axi_lite_bready": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axi_lite_arvalid": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axi_lite_arready": [ { "direction": "out" } ],
+        "s_axi_lite_araddr": [ { "direction": "in", "size_left": "9", "size_right": "0", "driver_value": "0" } ],
+        "s_axi_lite_rvalid": [ { "direction": "out" } ],
+        "s_axi_lite_rready": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axi_lite_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
+        "s_axi_lite_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
+        "m_axi_s2mm_awaddr": [ { "direction": "out", "size_left": "39", "size_right": "0" } ],
+        "m_axi_s2mm_awlen": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
+        "m_axi_s2mm_awsize": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
+        "m_axi_s2mm_awburst": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
+        "m_axi_s2mm_awprot": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
+        "m_axi_s2mm_awcache": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
+        "m_axi_s2mm_awvalid": [ { "direction": "out" } ],
+        "m_axi_s2mm_awready": [ { "direction": "in", "driver_value": "0" } ],
+        "m_axi_s2mm_wdata": [ { "direction": "out", "size_left": "63", "size_right": "0" } ],
+        "m_axi_s2mm_wstrb": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
+        "m_axi_s2mm_wlast": [ { "direction": "out" } ],
+        "m_axi_s2mm_wvalid": [ { "direction": "out" } ],
+        "m_axi_s2mm_wready": [ { "direction": "in", "driver_value": "0" } ],
+        "m_axi_s2mm_bresp": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
+        "m_axi_s2mm_bvalid": [ { "direction": "in", "driver_value": "0" } ],
+        "m_axi_s2mm_bready": [ { "direction": "out" } ],
+        "s2mm_prmry_reset_out_n": [ { "direction": "out" } ],
+        "s_axis_s2mm_tdata": [ { "direction": "in", "size_left": "63", "size_right": "0", "driver_value": "0" } ],
+        "s_axis_s2mm_tkeep": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0xFF" } ],
+        "s_axis_s2mm_tvalid": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axis_s2mm_tready": [ { "direction": "out" } ],
+        "s_axis_s2mm_tlast": [ { "direction": "in", "driver_value": "0" } ],
+        "s2mm_introut": [ { "direction": "out" } ],
+        "axi_dma_tstvec": [ { "direction": "out", "size_left": "31", "size_right": "0" } ]
+      },
+      "interfaces": {
+        "S_AXI_LITE": {
+          "vlnv": "xilinx.com:interface:aximm:1.0",
+          "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
+          "mode": "slave",
+          "memory_map_ref": "S_AXI_LITE",
+          "parameters": {
+            "DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "ADDR_WIDTH": [ { "value": "10", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_PROT": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_WSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "MAX_BURST_LENGTH": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_top_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "ARADDR": [ { "physical_name": "s_axi_lite_araddr" } ],
+            "ARREADY": [ { "physical_name": "s_axi_lite_arready" } ],
+            "ARVALID": [ { "physical_name": "s_axi_lite_arvalid" } ],
+            "AWADDR": [ { "physical_name": "s_axi_lite_awaddr" } ],
+            "AWREADY": [ { "physical_name": "s_axi_lite_awready" } ],
+            "AWVALID": [ { "physical_name": "s_axi_lite_awvalid" } ],
+            "BREADY": [ { "physical_name": "s_axi_lite_bready" } ],
+            "BRESP": [ { "physical_name": "s_axi_lite_bresp" } ],
+            "BVALID": [ { "physical_name": "s_axi_lite_bvalid" } ],
+            "RDATA": [ { "physical_name": "s_axi_lite_rdata" } ],
+            "RREADY": [ { "physical_name": "s_axi_lite_rready" } ],
+            "RRESP": [ { "physical_name": "s_axi_lite_rresp" } ],
+            "RVALID": [ { "physical_name": "s_axi_lite_rvalid" } ],
+            "WDATA": [ { "physical_name": "s_axi_lite_wdata" } ],
+            "WREADY": [ { "physical_name": "s_axi_lite_wready" } ],
+            "WVALID": [ { "physical_name": "s_axi_lite_wvalid" } ]
+          }
+        },
+        "M_AXI_S2MM": {
+          "vlnv": "xilinx.com:interface:aximm:1.0",
+          "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
+          "mode": "master",
+          "address_space_ref": "Data_S2MM",
+          "parameters": {
+            "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
+            "NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
+            "DATA_WIDTH": [ { "value": "64", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PROTOCOL": [ { "value": "AXI4", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "200000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "ADDR_WIDTH": [ { "value": "40", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "AWUSER_WIDTH": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "WRITE_ONLY", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_PROT": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_CACHE": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_WSTRB": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_BRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_RRESP": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "MAX_BURST_LENGTH": [ { "value": "16", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_top_mig_7series_0_0_ui_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "AWADDR": [ { "physical_name": "m_axi_s2mm_awaddr" } ],
+            "AWBURST": [ { "physical_name": "m_axi_s2mm_awburst" } ],
+            "AWCACHE": [ { "physical_name": "m_axi_s2mm_awcache" } ],
+            "AWLEN": [ { "physical_name": "m_axi_s2mm_awlen" } ],
+            "AWPROT": [ { "physical_name": "m_axi_s2mm_awprot" } ],
+            "AWREADY": [ { "physical_name": "m_axi_s2mm_awready" } ],
+            "AWSIZE": [ { "physical_name": "m_axi_s2mm_awsize" } ],
+            "AWVALID": [ { "physical_name": "m_axi_s2mm_awvalid" } ],
+            "BREADY": [ { "physical_name": "m_axi_s2mm_bready" } ],
+            "BRESP": [ { "physical_name": "m_axi_s2mm_bresp" } ],
+            "BVALID": [ { "physical_name": "m_axi_s2mm_bvalid" } ],
+            "WDATA": [ { "physical_name": "m_axi_s2mm_wdata" } ],
+            "WLAST": [ { "physical_name": "m_axi_s2mm_wlast" } ],
+            "WREADY": [ { "physical_name": "m_axi_s2mm_wready" } ],
+            "WSTRB": [ { "physical_name": "m_axi_s2mm_wstrb" } ],
+            "WVALID": [ { "physical_name": "m_axi_s2mm_wvalid" } ]
+          }
+        },
+        "S_AXIS_S2MM": {
+          "vlnv": "xilinx.com:interface:axis:1.0",
+          "abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "TDATA_NUM_BYTES": [ { "value": "8", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TDEST_WIDTH": [ { "value": "0", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TID_WIDTH": [ { "value": "0", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TREADY": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TKEEP": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TLAST": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "200000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_top_mig_7series_0_0_ui_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "TDATA": [ { "physical_name": "s_axis_s2mm_tdata" } ],
+            "TKEEP": [ { "physical_name": "s_axis_s2mm_tkeep" } ],
+            "TLAST": [ { "physical_name": "s_axis_s2mm_tlast" } ],
+            "TREADY": [ { "physical_name": "s_axis_s2mm_tready" } ],
+            "TVALID": [ { "physical_name": "s_axis_s2mm_tvalid" } ]
+          }
+        },
+        "AXI_RESETN": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "axi_resetn" } ]
+          }
+        },
+        "MM2S_INTROUT": {
+          "vlnv": "xilinx.com:signal:interrupt:1.0",
+          "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "SENSITIVITY": [ { "value": "LEVEL_HIGH", "value_src": "constant", "usage": "all" } ],
+            "PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "S2MM_INTROUT": {
+          "vlnv": "xilinx.com:signal:interrupt:1.0",
+          "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "SENSITIVITY": [ { "value": "LEVEL_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "PortWidth": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "INTERRUPT": [ { "physical_name": "s2mm_introut" } ]
+          }
+        },
+        "M_AXI_SG_CLK": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "M_AXI_SG", "value_src": "constant", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "M_AXI_MM2S_CLK": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "M_AXI_MM2S:M_AXIS_MM2S:M_AXIS_CNTRL", "value_src": "constant", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "mm2s_prmry_reset_out_n:mm2s_cntrl_reset_out_n", "value_src": "constant", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "M_AXI_S2MM_CLK": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "M_AXI_S2MM:S_AXIS_S2MM:S_AXIS_STS", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "s2mm_prmry_reset_out_n:s2mm_sts_reset_out_n", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "200000000", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_top_mig_7series_0_0_ui_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "m_axi_s2mm_aclk" } ]
+          }
+        },
+        "S_AXI_LITE_ACLK": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "S_AXI_LITE:M_AXI", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "axi_resetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_top_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "s_axi_lite_aclk" } ]
+          }
+        },
+        "MM2S_PRMRY_RESET_OUT_N": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "S2MM_PRMRY_RESET_OUT_N": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "s2mm_prmry_reset_out_n" } ]
+          }
+        },
+        "MM2S_CNTRL_RESET_OUT_N": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "S2MM_STS_RESET_OUT_N": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        }
+      },
+      "address_spaces": {
+        "Data_S2MM": {
+          "range": "1099511627776",
+          "width": "40"
+        }
+      },
+      "memory_maps": {
+        "S_AXI_LITE": {
+          "display_name": "S_AXI_MEM",
+          "description": "Memory Map for S_AXI_LITE",
+          "address_blocks": {
+            "Reg": {
+              "base_address": "0",
+              "range": "4096",
+              "display_name": "Reg",
+              "description": "Register Block",
+              "usage": "register",
+              "access": "read-write",
+              "registers": {
+                "MM2S_DMACR": {
+                  "address_offset": "0x0",
+                  "size": 32,
+                  "display_name": "MM2S DMA Control Register",
+                  "description": "MM2S DMA Control Register",
+                  "is_volatile": true,
+                  "access": "read-write",
+                  "reset_value": "0x10002",
+                  "fields": {
+                    "RS": {
+                      "bit_offset": 0,
+                      "bit_width": 1,
+                      "display_name": "Run/Stop Control",
+                      "description": "Run / Stop control for controlling running and stopping of the DMA channel.\n  0 - Stop, DMA stops when current (if any) DMA operations are complete. For Scatter / Gather Mode pending commands/transfers are flushed or completed. \n  AXI4-Stream outs are potentially terminated early. Descriptors in the update queue are allowed to finish updating to remote memory before engine halt.\n  For Direct Register mode pending commands/transfers are flushed or completed. AXI4-Stream outs are potentially terminated.\n  The halted bit in the DMA Status register asserts to 1 when the DMA engine is halted. This bit is cleared by AXI DMA hardware when an error occurs. The CPU can also choose to clear this bit to stop DMA operations.\n  1 - Run, Start DMA operations. The halted bit in the DMA Status register deasserts to 0 when the DMA engine begins operations.\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    },
+                    "Reset": {
+                      "bit_offset": 2,
+                      "bit_width": 1,
+                      "display_name": "Soft Reset",
+                      "description": "Soft reset for resetting the AXI DMA core. Setting this bit to a 1 causes the AXI DMA to be reset. Reset is accomplished gracefully. Pending commands/transfers are flushed or completed.\nAXI4-Stream outs are potentially terminated early. Setting either MM2S_DMACR. Reset = 1 or S2MM_DMACR.Reset = 1 resets the entire AXI DMA engine. After completion of a soft reset, all registers and bits are in the Reset State.      0 - Normal operation.   1 - Reset in progress.\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    },
+                    "Keyhole": {
+                      "bit_offset": 3,
+                      "bit_width": 1,
+                      "display_name": "Keyhole Read",
+                      "description": "Keyhole Read. Setting this bit to 1 causes AXI DMA to initiate MM2S reads (AXI4read) in non-incrementing address mode (Fixed Address Burst transfer on AXI4). This bit can be updated when AXI DMA is in idle. When using keyhole operation the Max Burst Length should not exceed 16. This bit should not be set when DRE is enabled.\nThis bit is non functional when the multichannel feature is enabled or in Direct Register mode.\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    },
+                    "Cyclic_BD_Enable": {
+                      "bit_offset": 4,
+                      "bit_width": 1,
+                      "display_name": "Cyclic BD Enable",
+                      "description": "When set to 1, the DMA operates in Cyclic Buffer Descriptor (BD) mode without any user intervention. In this mode, the Scatter Gather module ignores the Completed bit of the BD. With this bit set, you can use the same BDs in cyclic manner without worrying about any stale descriptor errors.\nThis bit should be set/unset only when the DMA is idle or when not running. Updating this bit while the DMA is running can result in unexpected behavior.\nThis bit is non functional when DMA operates in multichannel mode.\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    },
+                    "IOC_IrqEn": {
+                      "bit_offset": 12,
+                      "bit_width": 1,
+                      "display_name": "Interrupt on Complete (IOC) Interrupt Enable",
+                      "description": "Interrupt on Complete (IOC) Interrupt Enable. When set to 1, allows DMASR.IOC_Irq to generate an interrupt out for descriptors with the IOC bit set.   0 - IOC Interrupt disabled      1 - IOC Interrupt enabled\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    },
+                    "Dly_IrqEn": {
+                      "bit_offset": 13,
+                      "bit_width": 1,
+                      "display_name": "Interrupt on Delay Timer Interrupt Enable",
+                      "description": "Interrupt on Delay Timer Interrupt Enable. When set to 1, allows DMASR.Dly_Irq to generate an interrupt out.      0 - Delay Interrupt disabled   1 - Delay Interrupt enabled Note: This field is ignored when AXI DMA is configured for Direct Register Mode.\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    },
+                    "Err_IrqEn": {
+                      "bit_offset": 14,
+                      "bit_width": 1,
+                      "display_name": "Interrupt on Error Interrupt Enable",
+                      "description": "Interrupt on Error Interrupt Enable.\n  0 - Error Interrupt disabled\n  1 - Error Interrupt enabled\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    },
+                    "IRQThreshold": {
+                      "bit_offset": 16,
+                      "bit_width": 8,
+                      "display_name": "Interrupt Threshold",
+                      "description": "Interrupt Threshold. This value is used for setting the interrupt threshold. When IOC interrupt events occur, an internal counter counts down from the Interrupt Threshold setting. When the count reaches zero, an interrupt out is generated by the DMA engine.   Note: The minimum setting for the threshold is 0x01. A write of 0x00 to this register has no effect.   Note: This field is ignored when AXI DMA is configured for Direct Register Mode.\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    },
+                    "IRQDelay": {
+                      "bit_offset": 24,
+                      "bit_width": 8,
+                      "display_name": "Interrupt Delay Time Out",
+                      "description": "Interrupt Delay Time Out. This value is used for setting the interrupt timeout value. The interrupt timeout mechanism causes the DMA engine to generate an interrupt after the delay time period has expired. Timer begins counting at the end of a packet and resets with receipt of a new packet or a timeout event occurs.\nNote: Setting this value to zero disables the delay timer interrupt.\nNote: This field is ignored when AXI DMA is configured for Direct Register Mode.\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    }
+                  }
+                },
+                "MM2S_DMASR": {
+                  "address_offset": "0x04",
+                  "size": 32,
+                  "display_name": "MM2S DMA Status Register",
+                  "description": "MM2S DMA Status Register",
+                  "is_volatile": true,
+                  "access": "read-write",
+                  "reset_value": "0x10000",
+                  "fields": {
+                    "Halted": {
+                      "bit_offset": 0,
+                      "bit_width": 1,
+                      "display_name": "DMA Channel Halted",
+                      "description": "DMA Channel Halted. Indicates the run/stop state of the DMA channel.      0 - DMA channel running.      1 - DMA channel halted.  For Scatter / Gather Mode this bit gets set when DMACR.RS = 0 and DMA and SG operations have halted. For Direct Register mode (C_INCLUDE_SG = 0) this bit gets set when DMACR.RS = 0 and DMA operations have halted. There can be a lag of time between when DMACR.RS = 0 and when DMASR.Halted = 1 Note: When halted (RS= 0 and Halted = 1), writing to CURDESC_PTR or TAILDESC_PTR pointer registers has no effect on DMA operations when in Scatter Gather Mode. For Direct Register Mode, writing to the LENGTH register has no effect on DMA operations.\n",
+                      "is_volatile": true,
+                      "access": "read-only"
+                    },
+                    "Idle": {
+                      "bit_offset": 1,
+                      "bit_width": 1,
+                      "display_name": "DMA Channel Idle",
+                      "description": "DMA Channel Idle. Indicates the state of AXI DMA operations.\nFor Scatter / Gather Mode when IDLE indicates the SG Engine has reached the tail pointer for the associated channel and all queued descriptors have been processed. Writing to the tail pointer register automatically restarts DMA operations.\nFor Direct Register Mode when IDLE indicates the current transfer has completed.      0 - Not Idle. For Scatter / Gather Mode, SG has not reached tail descriptor pointer and/or DMA operations in progress. For Direct Register Mode, transfer is not complete.      1 - Idle. For Scatter / Gather Mode, SG has reached tail descriptor pointer and DMA operation paused. for Direct Register Mode, DMA transfer has completed and controller is paused.  Note: This bit is 0 when channel is halted (DMASR.Halted=1). This bit is also 0 prior to initial transfer when AXI DMA configured for Direct Register Mode.\n",
+                      "is_volatile": true,
+                      "access": "read-only"
+                    },
+                    "SGIncld": {
+                      "bit_offset": 3,
+                      "bit_width": 1,
+                      "display_name": "SGIncld",
+                      "description": "1 - Scatter Gather Enabled\n0 - Scatter Gather not enabled\n",
+                      "is_volatile": true,
+                      "access": "read-only"
+                    },
+                    "DMAIntErr": {
+                      "bit_offset": 4,
+                      "bit_width": 1,
+                      "display_name": "DMA Internal Error",
+                      "description": "DMA Internal Error. Internal error occurs if the buffer length specified in the fetched descriptor is set to 0. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No DMA Internal Errors        1 - DMA Internal Error detected. DMA Engine halts\n",
+                      "is_volatile": true,
+                      "access": "read-only"
+                    },
+                    "DMASlvErr": {
+                      "bit_offset": 5,
+                      "bit_width": 1,
+                      "display_name": "DMA Slave Error",
+                      "description": "DMA Slave Error. This error occurs if the slave read from the Memory Map interface issues a Slave Error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No DMA Slave Errors.      1 - DMA Slave Error detected. DMA Engine halts\n",
+                      "is_volatile": true,
+                      "access": "read-only"
+                    },
+                    "DMADecErr": {
+                      "bit_offset": 6,
+                      "bit_width": 1,
+                      "display_name": "DMA Decode Error",
+                      "description": "DMA Decode Error. This error occurs if the address request points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No DMA Decode Errors.      1 - DMA Decode Error detected. DMA Engine halts.\n",
+                      "is_volatile": true,
+                      "access": "read-only"
+                    },
+                    "SGIntErr": {
+                      "bit_offset": 8,
+                      "bit_width": 1,
+                      "display_name": "Scatter Gather Internal Error",
+                      "description": "Scatter Gather Internal Error. This error occurs if a descriptor with the \"Complete bit\" already set is fetched. Refer to the Scatter Gather Descriptor section for more information.This indicates to the SG Engine that the descriptor is a stale descriptor. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No SG Internal Errors.      1 - SG Internal Error detected. DMA Engine halts.  Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode.\n",
+                      "is_volatile": true,
+                      "access": "read-only"
+                    },
+                    "SGSlvErr": {
+                      "bit_offset": 9,
+                      "bit_width": 1,
+                      "display_name": "Scatter Gather Slave Error",
+                      "description": "Scatter Gather Slave Error. This error occurs if the slave read from on the Memory Map interface issues a Slave error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No SG Slave Errors.      1 - SG Slave Error detected. DMA Engine halts.  Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode. \n",
+                      "is_volatile": true,
+                      "access": "read-only"
+                    },
+                    "SGDecErr": {
+                      "bit_offset": 10,
+                      "bit_width": 1,
+                      "display_name": "Scatter Gather Decode Error",
+                      "description": "Scatter Gather Decode Error. This error occurs if CURDESC_PTR and/or NXTDESC_PTR points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No SG Decode Errors.      1 - SG Decode Error detected. DMA Engine halts.  Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode. \n",
+                      "is_volatile": true,
+                      "access": "read-only"
+                    },
+                    "IOC_Irq": {
+                      "bit_offset": 12,
+                      "bit_width": 1,
+                      "display_name": "Interrupt on Complete",
+                      "description": "Interrupt on Complete. When set to 1 for Scatter/Gather Mode, indicates an interrupt event was generated on completion of a descriptor. This occurs for descriptors with the End of Frame (EOF) bit set. When set to 1 for Direct Register Mode, indicates an interrupt event was generated on completion of a transfer. If the corresponding bit is enabled in the MM2S_DMACR (IOC_IrqEn = 1) and if the interrupt threshold has been met, causes an interrupt out to be generated from the AXI DMA.      0 - No IOC Interrupt.      1 - IOC Interrupt detected.  Writing a 1 to this bit will clear it.\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    },
+                    "Dly_Irq": {
+                      "bit_offset": 13,
+                      "bit_width": 1,
+                      "display_name": "Interrupt on Delay",
+                      "description": "Interrupt on Delay. When set to 1, indicates an interrupt event was generated on delay timer time out. If the corresponding bit is enabled in the MM2S_DMACR (Dly_IrqEn = 1), an interrupt out is generated from the AXI DMA.      0 - No Delay Interrupt.      1 - Delay Interrupt detected. Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode. \n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    },
+                    "Err_Irq": {
+                      "bit_offset": 14,
+                      "bit_width": 1,
+                      "display_name": "Interrupt on Error",
+                      "description": "Interrupt on Error. When set to 1, indicates an interrupt event was generated on error. If the corresponding bit is enabled in the MM2S_DMACR (Err_IrqEn = 1), an interrupt out is generated from the AXI DMA.\nWriting a 1 to this bit will clear it.   \n0 - No error Interrupt.   \n1 - Error interrupt detected.\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    },
+                    "IRQThresholdSts": {
+                      "bit_offset": 16,
+                      "bit_width": 8,
+                      "display_name": "Interrupt Threshold Status",
+                      "description": "Interrupt Threshold Status. Indicates current interrupt threshold value.\nNote: Applicable only when Scatter Gather is enabled.\n",
+                      "is_volatile": true,
+                      "access": "read-only"
+                    },
+                    "IRQDelaySts": {
+                      "bit_offset": 24,
+                      "bit_width": 8,
+                      "display_name": "Interrupt Delay Time Status",
+                      "description": "Interrupt Delay Time Status. Indicates current interrupt delay time value.\nNote: Applicable only when Scatter Gather is enabled.\n",
+                      "is_volatile": true,
+                      "access": "read-only"
+                    }
+                  }
+                },
+                "MM2S_SA": {
+                  "address_offset": "0x18",
+                  "size": 32,
+                  "display_name": "MM2S Source Address Register",
+                  "description": "MM2S Source Address Register",
+                  "is_volatile": true,
+                  "access": "read-write",
+                  "reset_value": "0x0",
+                  "fields": {
+                    "Source_Address": {
+                      "bit_offset": 0,
+                      "bit_width": 32,
+                      "display_name": "Source Address",
+                      "description": "Indicates the source address AXI DMA reads from to transfer data to AXI4-Stream on the MM2S Channel.\nNote: If Data Realignment Engine is included, the Source Address can be at any byte offset. If Data Realignment Engine is not included, the Source Address must be MM2S Memory Map data width aligned.\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    }
+                  }
+                },
+                "MM2S_SA_MSB": {
+                  "address_offset": "0x1C",
+                  "size": 32,
+                  "display_name": "MM2S Source Address Register",
+                  "description": "MM2S Source Address Register",
+                  "is_volatile": true,
+                  "access": "read-write",
+                  "reset_value": "0x0",
+                  "fields": {
+                    "Source_Address": {
+                      "bit_offset": 0,
+                      "bit_width": 32,
+                      "display_name": "Source Address",
+                      "description": "Indicates the MSB 32 bits of the source address AXI DMA reads from to transfer data to AXI4-Stream on the MM2S Channel.\nNote: If Data Realignment Engine is included, the Source Address can be at any byte offset. If Data Realignment Engine is not included, the Source Address must be MM2S Memory Map data width aligned.\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    }
+                  }
+                },
+                "MM2S_LENGTH": {
+                  "address_offset": "0x28",
+                  "size": 32,
+                  "display_name": "MM2S DMA Transfer Length Register",
+                  "description": "MM2S DMA Transfer Length Register",
+                  "is_volatile": true,
+                  "access": "read-write",
+                  "reset_value": "0x0",
+                  "fields": {
+                    "Length": {
+                      "bit_offset": 0,
+                      "bit_width": 26,
+                      "display_name": "Length",
+                      "description": "Indicates the number of bytes to transfer for the MM2S channel. Writing a non-zero value to this register starts the MM2S transfer.\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    }
+                  }
+                },
+                "S2MM_DMACR": {
+                  "address_offset": "0x30",
+                  "size": 32,
+                  "display_name": "S2MM DMA Control Register",
+                  "description": "S2MM DMA Control Register",
+                  "is_volatile": true,
+                  "access": "read-write",
+                  "reset_value": "0x10002",
+                  "fields": {
+                    "RS": {
+                      "bit_offset": 0,
+                      "bit_width": 1,
+                      "display_name": "Run/Stop Control",
+                      "description": "Run / Stop control for controlling running and stopping of the DMA channel.\n  0 - Stop, DMA stops when current (if any) DMA operations are complete. For Scatter / Gather Mode pending commands/transfers are flushed or completed. \n  AXI4-Stream outs are potentially terminated early. Descriptors in the update queue are allowed to finish updating to remote memory before engine halt.\n  For Direct Register mode pending commands/transfers are flushed or completed. AXI4-Stream outs are potentially terminated. Data integrity on S2MM AXI4 cannot be guaranteed.\n  The halted bit in the DMA Status register asserts to 1 when the DMA engine is halted. This bit is cleared by AXI DMA hardware when an error occurs. The CPU can also choose to clear this bit to stop DMA operations.\n  1 - Run, Start DMA operations. The halted bit in the DMA Status register deasserts to 0 when the DMA engine begins operations.\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    },
+                    "Reset": {
+                      "bit_offset": 2,
+                      "bit_width": 1,
+                      "display_name": "Soft Reset",
+                      "description": "Soft reset for resetting the AXI DMA core. Setting this bit to a 1 causes the AXI DMA to be reset. Reset is accomplished gracefully. Pending commands/transfers are flushed or completed.\nAXI4-Stream outs are terminated early, if necessary with associated TLAST. Setting either MM2S_DMACR.Reset = 1 or S2MM_DMACR.Reset = 1 resets the entire AXI DMA engine. After completion of a soft reset, all registers and bits are in the Reset State.      0 - Reset not in progress. Normal operation.      1 - Reset in progress\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    },
+                    "Keyhole": {
+                      "bit_offset": 3,
+                      "bit_width": 1,
+                      "display_name": "Keyhole Write",
+                      "description": "Keyhole Write. Setting this bit to 1 causes AXI DMA to initiate S2MM writes (AXI4 Writes) in non-incrementing address mode (Fixed Address Burst transfer on AXI4). This bit can be modified when AXI DMA is in idle. When enabling Key hole operation the maximum burst length cannot be more than 16. This bit should not be set when DRE is enabled.\nThis bit is non functional when DMA is used in multichannel mode.\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    },
+                    "Cyclic_BD_Enable": {
+                      "bit_offset": 4,
+                      "bit_width": 1,
+                      "display_name": "Cyclic BD Enable",
+                      "description": "When set to 1, the DMA operates in Cyclic Buffer Descriptor (BD) mode without any user intervention. In this mode, the Scatter Gather module ignores the Completed bit of the BD. With this bit set, you can use the same BDs in cyclic manner without worrying about any stale descriptor errors.\nThis bit is non functional when DMA operates in Multichannel mode. or in Direct Register Mode\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    },
+                    "IOC_IrqEn": {
+                      "bit_offset": 12,
+                      "bit_width": 1,
+                      "display_name": "Interrupt on Complete (IOC) Interrupt Enable",
+                      "description": "Interrupt on Complete (IOC) Interrupt Enable. When set to 1, allows Interrupt On Complete events to generate an interrupt out for descriptors with the Complete bit set.      0 - IOC Interrupt disabled      1 - IOC Interrupt enabled\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    },
+                    "Dly_IrqEn": {
+                      "bit_offset": 13,
+                      "bit_width": 1,
+                      "display_name": "Interrupt on Delay Timer Interrupt Enable",
+                      "description": "Interrupt on Delay Timer Interrupt Enable. When set to 1, allows error events to generate an interrupt out.      0 - Delay Interrupt disabled      1 - Delay Interrupt enabled  Note: Applicable only when Scatter Gather is enabled.\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    },
+                    "Err_IrqEn": {
+                      "bit_offset": 14,
+                      "bit_width": 1,
+                      "display_name": "Interrupt on Error Interrupt Enable",
+                      "description": "Interrupt on Error Interrupt Enable. When set to 1, allows error events to generate an interrupt out.      0 - Error Interrupt disabled      1 - Error Interrupt enabled\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    },
+                    "IRQThreshold": {
+                      "bit_offset": 16,
+                      "bit_width": 8,
+                      "display_name": "Interrupt Threshold",
+                      "description": "Interrupt Threshold. This value is used for setting the interrupt threshold. When IOC interrupt events occur, an internal counter counts down from the Interrupt Threshold setting. When the count reaches zero, an interrupt out is generated by the DMA engine.\nNote: The minimum setting for the threshold is 0x01. A write of 0x00 to this register has no effect.\nNote: Applicable only when Scatter Gather is enabled.\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    },
+                    "IRQDelay": {
+                      "bit_offset": 24,
+                      "bit_width": 8,
+                      "display_name": "Interrupt Delay Time Out",
+                      "description": "Interrupt Delay Time Out. This value is used for setting the interrupt timeout value. The interrupt timeout mechanism causes the DMA engine to generate an interrupt after the delay time period has expired. Timer begins counting at the end of a packet and resets with receipt of a new packet or a timeout event occurs.\nNote: Setting this value to zero disables the delay timer interrupt.\nNote: Applicable only when Scatter Gather is enabled.\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    }
+                  }
+                },
+                "S2MM_DMASR": {
+                  "address_offset": "0x34",
+                  "size": 32,
+                  "display_name": "S2MM DMA Status Register",
+                  "description": "S2MM DMA Status Register",
+                  "is_volatile": true,
+                  "access": "read-write",
+                  "reset_value": "0x10000",
+                  "fields": {
+                    "Halted": {
+                      "bit_offset": 0,
+                      "bit_width": 1,
+                      "display_name": "DMA Channel Halted",
+                      "description": "DMA Channel Halted. Indicates the run/stop state of the DMA channel.      0 - DMA channel running.      1 - DMA channel halted.  For Scatter/Gather Mode this bit gets set when DMACR.RS = 0 and DMA and SG operations have halted. For Direct Register Mode this bit gets set when DMACR.RS = 0 and DMA operations have halted. There can be a lag of time between when DMACR.RS = 0 and when DMASR.Halted = 1 \nNote: When halted (RS= 0 and Halted = 1), writing to CURDESC_PTR or TAILDESC_PTR pointer registers has no effect on DMA operations when in Scatter Gather Mode. For Direct Register Mode, writing to the LENGTH register has no effect on DMA operations.\n",
+                      "is_volatile": true,
+                      "access": "read-only"
+                    },
+                    "Idle": {
+                      "bit_offset": 1,
+                      "bit_width": 1,
+                      "display_name": "DMA Channel Idle",
+                      "description": "DMA Channel Idle. Indicates the state of AXI DMA operations.\nFor Scatter / Gather Mode when IDLE indicates the SG Engine has reached the tail pointer for the associated channel and all queued descriptors have been processed. Writing to the tail pointer register automatically restarts DMA operations.\nFor Direct Register Mode when IDLE indicates the current transfer has completed.      0 - Not Idle.      1 - Idle.   Note: This bit is 0 when channel is halted (DMASR.Halted=1). This bit is also 0 prior to initial transfer when AXI DMA configured for Direct Register Mode.\n",
+                      "is_volatile": true,
+                      "access": "read-only"
+                    },
+                    "SGIncld": {
+                      "bit_offset": 3,
+                      "bit_width": 1,
+                      "display_name": "SGIncld",
+                      "description": "Scatter Gather Engine Included. DMASR.SGIncld = 1 indicates the Scatter Gather engine is included and the AXI DMA is configured for Scatter Gather mode. DMASR.SGIncld = 0 indicates the Scatter Gather engine is excluded and the AXI DMA is configured for Direct Register Mode.\n",
+                      "is_volatile": true,
+                      "access": "read-only"
+                    },
+                    "DMAIntErr": {
+                      "bit_offset": 4,
+                      "bit_width": 1,
+                      "display_name": "DMA Internal Error",
+                      "description": "DMA Internal Error. This error occurs if the buffer length specified in the fetched descriptor is set to 0. Also, when in Scatter Gather Mode and using the status app length field, this error occurs when the Status AXI4-Stream packet RxLength field does not match the S2MM packet being received by the S_AXIS_S2MM interface. When Scatter Gather is disabled, this error is flagged if any error occurs during Memory write or if the incoming packet is bigger than what is specified in the DMA length register.\nThis error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No DMA Internal Errors      1 - DMA Internal Error detected.\n",
+                      "is_volatile": true,
+                      "access": "read-only"
+                    },
+                    "DMASlvErr": {
+                      "bit_offset": 5,
+                      "bit_width": 1,
+                      "display_name": "DMA Slave Error",
+                      "description": "DMA Slave Error. This error occurs if the slave read from the Memory Map interface issues a Slave Error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No DMA Slave Errors.      1 - DMA Slave Error detected.\n",
+                      "is_volatile": true,
+                      "access": "read-only"
+                    },
+                    "DMADecErr": {
+                      "bit_offset": 6,
+                      "bit_width": 1,
+                      "display_name": "DMA Decode Error",
+                      "description": "DMA Decode Error. This error occurs if the address request points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.     0 - No DMA Decode Errors.   1 - DMA Decode Error detected.\n",
+                      "is_volatile": true,
+                      "access": "read-only"
+                    },
+                    "SGIntErr": {
+                      "bit_offset": 8,
+                      "bit_width": 1,
+                      "display_name": "Scatter Gather Internal Error",
+                      "description": "Scatter Gather Internal Error. This error occurs if a descriptor with the \"Complete bit\" already set is fetched. This indicates to the SG Engine that the descriptor is a tail descriptor. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No SG Internal Errors.      1 - SG Internal Error detected.  Note: Applicable only when Scatter Gather is enabled. \n",
+                      "is_volatile": true,
+                      "access": "read-only"
+                    },
+                    "SGSlvErr": {
+                      "bit_offset": 9,
+                      "bit_width": 1,
+                      "display_name": "Scatter Gather Slave Error",
+                      "description": "Scatter Gather Slave Error. This error occurs if the slave read from on the Memory Map interface issues a Slave error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No SG Slave Errors.      1 - SG Slave Error detected. DMA Engine halts. Note: Applicable only when Scatter Gather is enabled. \n",
+                      "is_volatile": true,
+                      "access": "read-only"
+                    },
+                    "SGDecErr": {
+                      "bit_offset": 10,
+                      "bit_width": 1,
+                      "display_name": "Scatter Gather Decode Error",
+                      "description": "Scatter Gather Decode Error. This error occurs if CURDESC_PTR and/or NXTDESC_PTR points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No SG Decode Errors.      1 - SG Decode Error detected. DMA Engine halts. Note: Applicable only when Scatter Gather is enabled. \n",
+                      "is_volatile": true,
+                      "access": "read-only"
+                    },
+                    "IOC_Irq": {
+                      "bit_offset": 12,
+                      "bit_width": 1,
+                      "display_name": "Interrupt on Complete",
+                      "description": "Interrupt on Complete. When set to 1 for Scatter/Gather Mode, indicates an interrupt event was generated on completion of a descriptor. This occurs for descriptors with the End of Frame (EOF) bit set. When set to 1 for Direct Register Mode, indicates an interrupt event was generated on completion of a transfer. If the corresponding bit in S2MM_DMACR is enabled (IOC_IrqEn = 1) and if the interrupt threshold has been met, causes an interrupt out to be generated from the AXI DMA.      0 - No IOC Interrupt.      1 - IOC Interrupt detected. Writing a 1 to this bit will clear it.\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    },
+                    "Dly_Irq": {
+                      "bit_offset": 13,
+                      "bit_width": 1,
+                      "display_name": "Interrupt on Delay",
+                      "description": "Interrupt on Delay. When set to 1, indicates an interrupt event was generated on delay timer time out. If the corresponding bit is enabled in the S2MM_DMACR (Dly_IrqEn = 1), an interrupt out is generated from the AXI DMA.      0 - No Delay Interrupt.      1 - Delay Interrupt detected.1 = IOC Interrupt detected. Writing a 1 to this bit will clear it. Note: Applicable only when Scatter Gather is enabled. \n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    },
+                    "Err_Irq": {
+                      "bit_offset": 14,
+                      "bit_width": 1,
+                      "display_name": "Interrupt on Error",
+                      "description": "Interrupt on Error. When set to 1, indicates an interrupt event was generated on error. If the corresponding bit is enabled in the S2MM_DMACR (Err_IrqEn = 1), an interrupt out is generated from the AXI DMA.\nWriting a 1 to this bit will clear it.      0 - No error Interrupt.      1 - Error interrupt detected.\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    },
+                    "IRQThresholdSts": {
+                      "bit_offset": 16,
+                      "bit_width": 8,
+                      "display_name": "Interrupt Threshold Status",
+                      "description": "Interrupt Threshold Status. Indicates current interrupt threshold value.\nNote: Applicable only when Scatter Gather is enabled.\n",
+                      "is_volatile": true,
+                      "access": "read-only"
+                    },
+                    "IRQDelaySts": {
+                      "bit_offset": 24,
+                      "bit_width": 8,
+                      "display_name": "Interrupt Delay Time Status",
+                      "description": "Interrupt Delay Time Status. Indicates current interrupt delay time value.\nNote: Applicable only when Scatter Gather is enabled.\n",
+                      "is_volatile": true,
+                      "access": "read-only"
+                    }
+                  }
+                },
+                "S2MM_DA": {
+                  "address_offset": "0x48",
+                  "size": 32,
+                  "display_name": "S2MM DMA Destination Address Register",
+                  "description": "S2MM DMA Destination Address Register",
+                  "is_volatile": true,
+                  "access": "read-write",
+                  "reset_value": "0x0",
+                  "fields": {
+                    "Destination_Address": {
+                      "bit_offset": 0,
+                      "bit_width": 32,
+                      "display_name": "Destination Address",
+                      "description": "Indicates the destination address the AXI DMA writes to transfer data from AXI4-Stream on S2MM Channel.\nNote: If Data Realignment Engine is included, the Destination Address can be at any byte offset. If Data Realignment Engine is not included, the Destination Address must be S2MM Memory Map data width aligned.\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    }
+                  }
+                },
+                "S2MM_DA_MSB": {
+                  "address_offset": "0x4C",
+                  "size": 32,
+                  "display_name": "S2MM Destination Address Register",
+                  "description": "S2MM Destination Address Register",
+                  "is_volatile": true,
+                  "access": "read-write",
+                  "reset_value": "0x0",
+                  "fields": {
+                    "Destination_Address": {
+                      "bit_offset": 0,
+                      "bit_width": 32,
+                      "display_name": "Destination Address",
+                      "description": "Indicates the MSB 32 bits of the Destination address AXI DMA writes to transfer data from AXI4-Stream on the S2MM Channel.\nNote: If Data Realignment Engine is included, the Destination Address can be at any byte offset. If Data Realignment Engine is not included, the Dstination Address must be S2MM Memory Map data width aligned.\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    }
+                  }
+                },
+                "S2MM_LENGTH": {
+                  "address_offset": "0x58",
+                  "size": 32,
+                  "display_name": "S2MM DMA Transfer Length Register",
+                  "description": "S2MM DMA Transfer Length Register",
+                  "is_volatile": true,
+                  "access": "read-write",
+                  "reset_value": "0x0",
+                  "fields": {
+                    "Length": {
+                      "bit_offset": 0,
+                      "bit_width": 26,
+                      "display_name": "Length",
+                      "description": "Indicates the length in bytes of the S2MM buffer available to write receive data from the S2MM channel. Writing a non-zero value to this register enables S2MM channel to receive packet data.\nAt the completion of the S2MM transfer, the number of actual bytes written on the S2MM AXI4 interface is updated to the S2MM_LENGTH register.\nNote: This value must be greater than or equal to the largest expected packet to be received on S2MM AXI4-Stream. Values smaller than the received packet result in undefined behavior. \n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    }
+                  }
+                }
+              }
+            }
+          }
+        }
+      }
+    }
+  }
+}

cx9261a_demo_cmos_20240829/project_fix_dac.srcs/sources_1/bd/system_top/ip/system_top_axi_dma_1_0/system_top_axi_dma_1_0.xci

@@ -0,0 +1,976 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "system_top_axi_dma_1_0",
+    "cell_name": "axi_dma_1",
+    "component_reference": "xilinx.com:ip:axi_dma:7.1",
+    "ip_revision": "32",
+    "gen_directory": "../../../../../../project_fix_dac.gen/sources_1/bd/system_top/ip/system_top_axi_dma_1_0",
+    "parameters": {
+      "component_parameters": {
+        "Component_Name": [ { "value": "system_top_axi_dma_1_0", "resolve_type": "user", "usage": "all" } ],
+        "c_include_sg": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "c_enable_multi_channel": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "c_num_mm2s_channels": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "c_num_s2mm_channels": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "c_sg_length_width": [ { "value": "26", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "c_dlytmr_resolution": [ { "value": "125", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "c_prmry_is_aclk_async": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "c_sg_include_stscntrl_strm": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "c_micro_dma": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "c_include_mm2s": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "c_m_axi_mm2s_data_width": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "c_m_axis_mm2s_tdata_width": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "c_include_mm2s_dre": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "c_include_mm2s_sf": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "c_mm2s_burst_size": [ { "value": "16", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "c_include_s2mm": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "c_sg_use_stsapp_length": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "c_m_axi_s2mm_data_width": [ { "value": "64", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "c_s_axis_s2mm_tdata_width": [ { "value": "64", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "c_include_s2mm_dre": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "c_include_s2mm_sf": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "c_s2mm_burst_size": [ { "value": "16", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "c_addr_width": [ { "value": "40", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "c_single_interface": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "c_increase_throughput": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ]
+      },
+      "model_parameters": {
+        "C_S_AXI_LITE_ADDR_WIDTH": [ { "value": "10", "format": "long", "usage": "all" } ],
+        "C_S_AXI_LITE_DATA_WIDTH": [ { "value": "32", "format": "long", "usage": "all" } ],
+        "C_DLYTMR_RESOLUTION": [ { "value": "125", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PRMRY_IS_ACLK_ASYNC": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ENABLE_MULTI_CHANNEL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_NUM_MM2S_CHANNELS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_NUM_S2MM_CHANNELS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_INCLUDE_SG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_SG_INCLUDE_STSCNTRL_STRM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_SG_USE_STSAPP_LENGTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_SG_LENGTH_WIDTH": [ { "value": "26", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_M_AXI_SG_ADDR_WIDTH": [ { "value": "40", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_M_AXI_SG_DATA_WIDTH": [ { "value": "32", "format": "long", "usage": "all" } ],
+        "C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_S_AXIS_S2MM_STS_TDATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_MICRO_DMA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_INCLUDE_MM2S": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_INCLUDE_MM2S_SF": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_MM2S_BURST_SIZE": [ { "value": "16", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_M_AXI_MM2S_ADDR_WIDTH": [ { "value": "40", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_M_AXI_MM2S_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_M_AXIS_MM2S_TDATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_INCLUDE_MM2S_DRE": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_INCLUDE_S2MM": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_INCLUDE_S2MM_SF": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S2MM_BURST_SIZE": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_M_AXI_S2MM_ADDR_WIDTH": [ { "value": "40", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_M_AXI_S2MM_DATA_WIDTH": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXIS_S2MM_TDATA_WIDTH": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_INCLUDE_S2MM_DRE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_INCREASE_THROUGHPUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_FAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "zynq" } ],
+        "BASE_BOARD_PART": [ { "value": "xilinx.com:zc706:part0:1.4" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xc7z045" } ],
+        "NEXTGEN_VERSAL": [ { "value": "0" } ],
+        "PACKAGE": [ { "value": "ffg900" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Integrator" } ],
+        "IPREVISION": [ { "value": "32" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../../../project_fix_dac.gen/sources_1/bd/system_top/ip/system_top_axi_dma_1_0" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "../../ipshared" } ],
+        "SWVERSION": [ { "value": "2024.1" } ],
+        "SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "s_axi_lite_aclk": [ { "direction": "in", "driver_value": "0" } ],
+        "m_axi_s2mm_aclk": [ { "direction": "in", "driver_value": "0" } ],
+        "axi_resetn": [ { "direction": "in", "driver_value": "1" } ],
+        "s_axi_lite_awvalid": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axi_lite_awready": [ { "direction": "out" } ],
+        "s_axi_lite_awaddr": [ { "direction": "in", "size_left": "9", "size_right": "0", "driver_value": "0" } ],
+        "s_axi_lite_wvalid": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axi_lite_wready": [ { "direction": "out" } ],
+        "s_axi_lite_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
+        "s_axi_lite_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
+        "s_axi_lite_bvalid": [ { "direction": "out" } ],
+        "s_axi_lite_bready": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axi_lite_arvalid": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axi_lite_arready": [ { "direction": "out" } ],
+        "s_axi_lite_araddr": [ { "direction": "in", "size_left": "9", "size_right": "0", "driver_value": "0" } ],
+        "s_axi_lite_rvalid": [ { "direction": "out" } ],
+        "s_axi_lite_rready": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axi_lite_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
+        "s_axi_lite_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
+        "m_axi_s2mm_awaddr": [ { "direction": "out", "size_left": "39", "size_right": "0" } ],
+        "m_axi_s2mm_awlen": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
+        "m_axi_s2mm_awsize": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
+        "m_axi_s2mm_awburst": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
+        "m_axi_s2mm_awprot": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
+        "m_axi_s2mm_awcache": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
+        "m_axi_s2mm_awvalid": [ { "direction": "out" } ],
+        "m_axi_s2mm_awready": [ { "direction": "in", "driver_value": "0" } ],
+        "m_axi_s2mm_wdata": [ { "direction": "out", "size_left": "63", "size_right": "0" } ],
+        "m_axi_s2mm_wstrb": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
+        "m_axi_s2mm_wlast": [ { "direction": "out" } ],
+        "m_axi_s2mm_wvalid": [ { "direction": "out" } ],
+        "m_axi_s2mm_wready": [ { "direction": "in", "driver_value": "0" } ],
+        "m_axi_s2mm_bresp": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
+        "m_axi_s2mm_bvalid": [ { "direction": "in", "driver_value": "0" } ],
+        "m_axi_s2mm_bready": [ { "direction": "out" } ],
+        "s2mm_prmry_reset_out_n": [ { "direction": "out" } ],
+        "s_axis_s2mm_tdata": [ { "direction": "in", "size_left": "63", "size_right": "0", "driver_value": "0" } ],
+        "s_axis_s2mm_tkeep": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0xFF" } ],
+        "s_axis_s2mm_tvalid": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axis_s2mm_tready": [ { "direction": "out" } ],
+        "s_axis_s2mm_tlast": [ { "direction": "in", "driver_value": "0" } ],
+        "s2mm_introut": [ { "direction": "out" } ],
+        "axi_dma_tstvec": [ { "direction": "out", "size_left": "31", "size_right": "0" } ]
+      },
+      "interfaces": {
+        "S_AXI_LITE": {
+          "vlnv": "xilinx.com:interface:aximm:1.0",
+          "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
+          "mode": "slave",
+          "memory_map_ref": "S_AXI_LITE",
+          "parameters": {
+            "DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "ADDR_WIDTH": [ { "value": "10", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_PROT": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_WSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "MAX_BURST_LENGTH": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_top_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "ARADDR": [ { "physical_name": "s_axi_lite_araddr" } ],
+            "ARREADY": [ { "physical_name": "s_axi_lite_arready" } ],
+            "ARVALID": [ { "physical_name": "s_axi_lite_arvalid" } ],
+            "AWADDR": [ { "physical_name": "s_axi_lite_awaddr" } ],
+            "AWREADY": [ { "physical_name": "s_axi_lite_awready" } ],
+            "AWVALID": [ { "physical_name": "s_axi_lite_awvalid" } ],
+            "BREADY": [ { "physical_name": "s_axi_lite_bready" } ],
+            "BRESP": [ { "physical_name": "s_axi_lite_bresp" } ],
+            "BVALID": [ { "physical_name": "s_axi_lite_bvalid" } ],
+            "RDATA": [ { "physical_name": "s_axi_lite_rdata" } ],
+            "RREADY": [ { "physical_name": "s_axi_lite_rready" } ],
+            "RRESP": [ { "physical_name": "s_axi_lite_rresp" } ],
+            "RVALID": [ { "physical_name": "s_axi_lite_rvalid" } ],
+            "WDATA": [ { "physical_name": "s_axi_lite_wdata" } ],
+            "WREADY": [ { "physical_name": "s_axi_lite_wready" } ],
+            "WVALID": [ { "physical_name": "s_axi_lite_wvalid" } ]
+          }
+        },
+        "M_AXI_S2MM": {
+          "vlnv": "xilinx.com:interface:aximm:1.0",
+          "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
+          "mode": "master",
+          "address_space_ref": "Data_S2MM",
+          "parameters": {
+            "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
+            "NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
+            "DATA_WIDTH": [ { "value": "64", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PROTOCOL": [ { "value": "AXI4", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "200000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "ADDR_WIDTH": [ { "value": "40", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "AWUSER_WIDTH": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "WRITE_ONLY", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_PROT": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_CACHE": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_WSTRB": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_BRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_RRESP": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "MAX_BURST_LENGTH": [ { "value": "16", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_top_mig_7series_0_0_ui_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "AWADDR": [ { "physical_name": "m_axi_s2mm_awaddr" } ],
+            "AWBURST": [ { "physical_name": "m_axi_s2mm_awburst" } ],
+            "AWCACHE": [ { "physical_name": "m_axi_s2mm_awcache" } ],
+            "AWLEN": [ { "physical_name": "m_axi_s2mm_awlen" } ],
+            "AWPROT": [ { "physical_name": "m_axi_s2mm_awprot" } ],
+            "AWREADY": [ { "physical_name": "m_axi_s2mm_awready" } ],
+            "AWSIZE": [ { "physical_name": "m_axi_s2mm_awsize" } ],
+            "AWVALID": [ { "physical_name": "m_axi_s2mm_awvalid" } ],
+            "BREADY": [ { "physical_name": "m_axi_s2mm_bready" } ],
+            "BRESP": [ { "physical_name": "m_axi_s2mm_bresp" } ],
+            "BVALID": [ { "physical_name": "m_axi_s2mm_bvalid" } ],
+            "WDATA": [ { "physical_name": "m_axi_s2mm_wdata" } ],
+            "WLAST": [ { "physical_name": "m_axi_s2mm_wlast" } ],
+            "WREADY": [ { "physical_name": "m_axi_s2mm_wready" } ],
+            "WSTRB": [ { "physical_name": "m_axi_s2mm_wstrb" } ],
+            "WVALID": [ { "physical_name": "m_axi_s2mm_wvalid" } ]
+          }
+        },
+        "S_AXIS_S2MM": {
+          "vlnv": "xilinx.com:interface:axis:1.0",
+          "abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "TDATA_NUM_BYTES": [ { "value": "8", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TDEST_WIDTH": [ { "value": "0", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TID_WIDTH": [ { "value": "0", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TREADY": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TKEEP": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TLAST": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "200000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_top_mig_7series_0_0_ui_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "TDATA": [ { "physical_name": "s_axis_s2mm_tdata" } ],
+            "TKEEP": [ { "physical_name": "s_axis_s2mm_tkeep" } ],
+            "TLAST": [ { "physical_name": "s_axis_s2mm_tlast" } ],
+            "TREADY": [ { "physical_name": "s_axis_s2mm_tready" } ],
+            "TVALID": [ { "physical_name": "s_axis_s2mm_tvalid" } ]
+          }
+        },
+        "AXI_RESETN": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "axi_resetn" } ]
+          }
+        },
+        "MM2S_INTROUT": {
+          "vlnv": "xilinx.com:signal:interrupt:1.0",
+          "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "SENSITIVITY": [ { "value": "LEVEL_HIGH", "value_src": "constant", "usage": "all" } ],
+            "PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "S2MM_INTROUT": {
+          "vlnv": "xilinx.com:signal:interrupt:1.0",
+          "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "SENSITIVITY": [ { "value": "LEVEL_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "PortWidth": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "INTERRUPT": [ { "physical_name": "s2mm_introut" } ]
+          }
+        },
+        "M_AXI_SG_CLK": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "M_AXI_SG", "value_src": "constant", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "M_AXI_MM2S_CLK": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "M_AXI_MM2S:M_AXIS_MM2S:M_AXIS_CNTRL", "value_src": "constant", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "mm2s_prmry_reset_out_n:mm2s_cntrl_reset_out_n", "value_src": "constant", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "M_AXI_S2MM_CLK": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "M_AXI_S2MM:S_AXIS_S2MM:S_AXIS_STS", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "s2mm_prmry_reset_out_n:s2mm_sts_reset_out_n", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "200000000", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_top_mig_7series_0_0_ui_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "m_axi_s2mm_aclk" } ]
+          }
+        },
+        "S_AXI_LITE_ACLK": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "S_AXI_LITE:M_AXI", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "axi_resetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_top_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "s_axi_lite_aclk" } ]
+          }
+        },
+        "MM2S_PRMRY_RESET_OUT_N": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "S2MM_PRMRY_RESET_OUT_N": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "s2mm_prmry_reset_out_n" } ]
+          }
+        },
+        "MM2S_CNTRL_RESET_OUT_N": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "S2MM_STS_RESET_OUT_N": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        }
+      },
+      "address_spaces": {
+        "Data_S2MM": {
+          "range": "1099511627776",
+          "width": "40"
+        }
+      },
+      "memory_maps": {
+        "S_AXI_LITE": {
+          "display_name": "S_AXI_MEM",
+          "description": "Memory Map for S_AXI_LITE",
+          "address_blocks": {
+            "Reg": {
+              "base_address": "0",
+              "range": "4096",
+              "display_name": "Reg",
+              "description": "Register Block",
+              "usage": "register",
+              "access": "read-write",
+              "registers": {
+                "MM2S_DMACR": {
+                  "address_offset": "0x0",
+                  "size": 32,
+                  "display_name": "MM2S DMA Control Register",
+                  "description": "MM2S DMA Control Register",
+                  "is_volatile": true,
+                  "access": "read-write",
+                  "reset_value": "0x10002",
+                  "fields": {
+                    "RS": {
+                      "bit_offset": 0,
+                      "bit_width": 1,
+                      "display_name": "Run/Stop Control",
+                      "description": "Run / Stop control for controlling running and stopping of the DMA channel.\n  0 - Stop, DMA stops when current (if any) DMA operations are complete. For Scatter / Gather Mode pending commands/transfers are flushed or completed. \n  AXI4-Stream outs are potentially terminated early. Descriptors in the update queue are allowed to finish updating to remote memory before engine halt.\n  For Direct Register mode pending commands/transfers are flushed or completed. AXI4-Stream outs are potentially terminated.\n  The halted bit in the DMA Status register asserts to 1 when the DMA engine is halted. This bit is cleared by AXI DMA hardware when an error occurs. The CPU can also choose to clear this bit to stop DMA operations.\n  1 - Run, Start DMA operations. The halted bit in the DMA Status register deasserts to 0 when the DMA engine begins operations.\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    },
+                    "Reset": {
+                      "bit_offset": 2,
+                      "bit_width": 1,
+                      "display_name": "Soft Reset",
+                      "description": "Soft reset for resetting the AXI DMA core. Setting this bit to a 1 causes the AXI DMA to be reset. Reset is accomplished gracefully. Pending commands/transfers are flushed or completed.\nAXI4-Stream outs are potentially terminated early. Setting either MM2S_DMACR. Reset = 1 or S2MM_DMACR.Reset = 1 resets the entire AXI DMA engine. After completion of a soft reset, all registers and bits are in the Reset State.      0 - Normal operation.   1 - Reset in progress.\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    },
+                    "Keyhole": {
+                      "bit_offset": 3,
+                      "bit_width": 1,
+                      "display_name": "Keyhole Read",
+                      "description": "Keyhole Read. Setting this bit to 1 causes AXI DMA to initiate MM2S reads (AXI4read) in non-incrementing address mode (Fixed Address Burst transfer on AXI4). This bit can be updated when AXI DMA is in idle. When using keyhole operation the Max Burst Length should not exceed 16. This bit should not be set when DRE is enabled.\nThis bit is non functional when the multichannel feature is enabled or in Direct Register mode.\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    },
+                    "Cyclic_BD_Enable": {
+                      "bit_offset": 4,
+                      "bit_width": 1,
+                      "display_name": "Cyclic BD Enable",
+                      "description": "When set to 1, the DMA operates in Cyclic Buffer Descriptor (BD) mode without any user intervention. In this mode, the Scatter Gather module ignores the Completed bit of the BD. With this bit set, you can use the same BDs in cyclic manner without worrying about any stale descriptor errors.\nThis bit should be set/unset only when the DMA is idle or when not running. Updating this bit while the DMA is running can result in unexpected behavior.\nThis bit is non functional when DMA operates in multichannel mode.\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    },
+                    "IOC_IrqEn": {
+                      "bit_offset": 12,
+                      "bit_width": 1,
+                      "display_name": "Interrupt on Complete (IOC) Interrupt Enable",
+                      "description": "Interrupt on Complete (IOC) Interrupt Enable. When set to 1, allows DMASR.IOC_Irq to generate an interrupt out for descriptors with the IOC bit set.   0 - IOC Interrupt disabled      1 - IOC Interrupt enabled\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    },
+                    "Dly_IrqEn": {
+                      "bit_offset": 13,
+                      "bit_width": 1,
+                      "display_name": "Interrupt on Delay Timer Interrupt Enable",
+                      "description": "Interrupt on Delay Timer Interrupt Enable. When set to 1, allows DMASR.Dly_Irq to generate an interrupt out.      0 - Delay Interrupt disabled   1 - Delay Interrupt enabled Note: This field is ignored when AXI DMA is configured for Direct Register Mode.\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    },
+                    "Err_IrqEn": {
+                      "bit_offset": 14,
+                      "bit_width": 1,
+                      "display_name": "Interrupt on Error Interrupt Enable",
+                      "description": "Interrupt on Error Interrupt Enable.\n  0 - Error Interrupt disabled\n  1 - Error Interrupt enabled\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    },
+                    "IRQThreshold": {
+                      "bit_offset": 16,
+                      "bit_width": 8,
+                      "display_name": "Interrupt Threshold",
+                      "description": "Interrupt Threshold. This value is used for setting the interrupt threshold. When IOC interrupt events occur, an internal counter counts down from the Interrupt Threshold setting. When the count reaches zero, an interrupt out is generated by the DMA engine.   Note: The minimum setting for the threshold is 0x01. A write of 0x00 to this register has no effect.   Note: This field is ignored when AXI DMA is configured for Direct Register Mode.\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    },
+                    "IRQDelay": {
+                      "bit_offset": 24,
+                      "bit_width": 8,
+                      "display_name": "Interrupt Delay Time Out",
+                      "description": "Interrupt Delay Time Out. This value is used for setting the interrupt timeout value. The interrupt timeout mechanism causes the DMA engine to generate an interrupt after the delay time period has expired. Timer begins counting at the end of a packet and resets with receipt of a new packet or a timeout event occurs.\nNote: Setting this value to zero disables the delay timer interrupt.\nNote: This field is ignored when AXI DMA is configured for Direct Register Mode.\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    }
+                  }
+                },
+                "MM2S_DMASR": {
+                  "address_offset": "0x04",
+                  "size": 32,
+                  "display_name": "MM2S DMA Status Register",
+                  "description": "MM2S DMA Status Register",
+                  "is_volatile": true,
+                  "access": "read-write",
+                  "reset_value": "0x10000",
+                  "fields": {
+                    "Halted": {
+                      "bit_offset": 0,
+                      "bit_width": 1,
+                      "display_name": "DMA Channel Halted",
+                      "description": "DMA Channel Halted. Indicates the run/stop state of the DMA channel.      0 - DMA channel running.      1 - DMA channel halted.  For Scatter / Gather Mode this bit gets set when DMACR.RS = 0 and DMA and SG operations have halted. For Direct Register mode (C_INCLUDE_SG = 0) this bit gets set when DMACR.RS = 0 and DMA operations have halted. There can be a lag of time between when DMACR.RS = 0 and when DMASR.Halted = 1 Note: When halted (RS= 0 and Halted = 1), writing to CURDESC_PTR or TAILDESC_PTR pointer registers has no effect on DMA operations when in Scatter Gather Mode. For Direct Register Mode, writing to the LENGTH register has no effect on DMA operations.\n",
+                      "is_volatile": true,
+                      "access": "read-only"
+                    },
+                    "Idle": {
+                      "bit_offset": 1,
+                      "bit_width": 1,
+                      "display_name": "DMA Channel Idle",
+                      "description": "DMA Channel Idle. Indicates the state of AXI DMA operations.\nFor Scatter / Gather Mode when IDLE indicates the SG Engine has reached the tail pointer for the associated channel and all queued descriptors have been processed. Writing to the tail pointer register automatically restarts DMA operations.\nFor Direct Register Mode when IDLE indicates the current transfer has completed.      0 - Not Idle. For Scatter / Gather Mode, SG has not reached tail descriptor pointer and/or DMA operations in progress. For Direct Register Mode, transfer is not complete.      1 - Idle. For Scatter / Gather Mode, SG has reached tail descriptor pointer and DMA operation paused. for Direct Register Mode, DMA transfer has completed and controller is paused.  Note: This bit is 0 when channel is halted (DMASR.Halted=1). This bit is also 0 prior to initial transfer when AXI DMA configured for Direct Register Mode.\n",
+                      "is_volatile": true,
+                      "access": "read-only"
+                    },
+                    "SGIncld": {
+                      "bit_offset": 3,
+                      "bit_width": 1,
+                      "display_name": "SGIncld",
+                      "description": "1 - Scatter Gather Enabled\n0 - Scatter Gather not enabled\n",
+                      "is_volatile": true,
+                      "access": "read-only"
+                    },
+                    "DMAIntErr": {
+                      "bit_offset": 4,
+                      "bit_width": 1,
+                      "display_name": "DMA Internal Error",
+                      "description": "DMA Internal Error. Internal error occurs if the buffer length specified in the fetched descriptor is set to 0. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No DMA Internal Errors        1 - DMA Internal Error detected. DMA Engine halts\n",
+                      "is_volatile": true,
+                      "access": "read-only"
+                    },
+                    "DMASlvErr": {
+                      "bit_offset": 5,
+                      "bit_width": 1,
+                      "display_name": "DMA Slave Error",
+                      "description": "DMA Slave Error. This error occurs if the slave read from the Memory Map interface issues a Slave Error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No DMA Slave Errors.      1 - DMA Slave Error detected. DMA Engine halts\n",
+                      "is_volatile": true,
+                      "access": "read-only"
+                    },
+                    "DMADecErr": {
+                      "bit_offset": 6,
+                      "bit_width": 1,
+                      "display_name": "DMA Decode Error",
+                      "description": "DMA Decode Error. This error occurs if the address request points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No DMA Decode Errors.      1 - DMA Decode Error detected. DMA Engine halts.\n",
+                      "is_volatile": true,
+                      "access": "read-only"
+                    },
+                    "SGIntErr": {
+                      "bit_offset": 8,
+                      "bit_width": 1,
+                      "display_name": "Scatter Gather Internal Error",
+                      "description": "Scatter Gather Internal Error. This error occurs if a descriptor with the \"Complete bit\" already set is fetched. Refer to the Scatter Gather Descriptor section for more information.This indicates to the SG Engine that the descriptor is a stale descriptor. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No SG Internal Errors.      1 - SG Internal Error detected. DMA Engine halts.  Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode.\n",
+                      "is_volatile": true,
+                      "access": "read-only"
+                    },
+                    "SGSlvErr": {
+                      "bit_offset": 9,
+                      "bit_width": 1,
+                      "display_name": "Scatter Gather Slave Error",
+                      "description": "Scatter Gather Slave Error. This error occurs if the slave read from on the Memory Map interface issues a Slave error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No SG Slave Errors.      1 - SG Slave Error detected. DMA Engine halts.  Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode. \n",
+                      "is_volatile": true,
+                      "access": "read-only"
+                    },
+                    "SGDecErr": {
+                      "bit_offset": 10,
+                      "bit_width": 1,
+                      "display_name": "Scatter Gather Decode Error",
+                      "description": "Scatter Gather Decode Error. This error occurs if CURDESC_PTR and/or NXTDESC_PTR points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No SG Decode Errors.      1 - SG Decode Error detected. DMA Engine halts.  Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode. \n",
+                      "is_volatile": true,
+                      "access": "read-only"
+                    },
+                    "IOC_Irq": {
+                      "bit_offset": 12,
+                      "bit_width": 1,
+                      "display_name": "Interrupt on Complete",
+                      "description": "Interrupt on Complete. When set to 1 for Scatter/Gather Mode, indicates an interrupt event was generated on completion of a descriptor. This occurs for descriptors with the End of Frame (EOF) bit set. When set to 1 for Direct Register Mode, indicates an interrupt event was generated on completion of a transfer. If the corresponding bit is enabled in the MM2S_DMACR (IOC_IrqEn = 1) and if the interrupt threshold has been met, causes an interrupt out to be generated from the AXI DMA.      0 - No IOC Interrupt.      1 - IOC Interrupt detected.  Writing a 1 to this bit will clear it.\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    },
+                    "Dly_Irq": {
+                      "bit_offset": 13,
+                      "bit_width": 1,
+                      "display_name": "Interrupt on Delay",
+                      "description": "Interrupt on Delay. When set to 1, indicates an interrupt event was generated on delay timer time out. If the corresponding bit is enabled in the MM2S_DMACR (Dly_IrqEn = 1), an interrupt out is generated from the AXI DMA.      0 - No Delay Interrupt.      1 - Delay Interrupt detected. Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode. \n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    },
+                    "Err_Irq": {
+                      "bit_offset": 14,
+                      "bit_width": 1,
+                      "display_name": "Interrupt on Error",
+                      "description": "Interrupt on Error. When set to 1, indicates an interrupt event was generated on error. If the corresponding bit is enabled in the MM2S_DMACR (Err_IrqEn = 1), an interrupt out is generated from the AXI DMA.\nWriting a 1 to this bit will clear it.   \n0 - No error Interrupt.   \n1 - Error interrupt detected.\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    },
+                    "IRQThresholdSts": {
+                      "bit_offset": 16,
+                      "bit_width": 8,
+                      "display_name": "Interrupt Threshold Status",
+                      "description": "Interrupt Threshold Status. Indicates current interrupt threshold value.\nNote: Applicable only when Scatter Gather is enabled.\n",
+                      "is_volatile": true,
+                      "access": "read-only"
+                    },
+                    "IRQDelaySts": {
+                      "bit_offset": 24,
+                      "bit_width": 8,
+                      "display_name": "Interrupt Delay Time Status",
+                      "description": "Interrupt Delay Time Status. Indicates current interrupt delay time value.\nNote: Applicable only when Scatter Gather is enabled.\n",
+                      "is_volatile": true,
+                      "access": "read-only"
+                    }
+                  }
+                },
+                "MM2S_SA": {
+                  "address_offset": "0x18",
+                  "size": 32,
+                  "display_name": "MM2S Source Address Register",
+                  "description": "MM2S Source Address Register",
+                  "is_volatile": true,
+                  "access": "read-write",
+                  "reset_value": "0x0",
+                  "fields": {
+                    "Source_Address": {
+                      "bit_offset": 0,
+                      "bit_width": 32,
+                      "display_name": "Source Address",
+                      "description": "Indicates the source address AXI DMA reads from to transfer data to AXI4-Stream on the MM2S Channel.\nNote: If Data Realignment Engine is included, the Source Address can be at any byte offset. If Data Realignment Engine is not included, the Source Address must be MM2S Memory Map data width aligned.\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    }
+                  }
+                },
+                "MM2S_SA_MSB": {
+                  "address_offset": "0x1C",
+                  "size": 32,
+                  "display_name": "MM2S Source Address Register",
+                  "description": "MM2S Source Address Register",
+                  "is_volatile": true,
+                  "access": "read-write",
+                  "reset_value": "0x0",
+                  "fields": {
+                    "Source_Address": {
+                      "bit_offset": 0,
+                      "bit_width": 32,
+                      "display_name": "Source Address",
+                      "description": "Indicates the MSB 32 bits of the source address AXI DMA reads from to transfer data to AXI4-Stream on the MM2S Channel.\nNote: If Data Realignment Engine is included, the Source Address can be at any byte offset. If Data Realignment Engine is not included, the Source Address must be MM2S Memory Map data width aligned.\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    }
+                  }
+                },
+                "MM2S_LENGTH": {
+                  "address_offset": "0x28",
+                  "size": 32,
+                  "display_name": "MM2S DMA Transfer Length Register",
+                  "description": "MM2S DMA Transfer Length Register",
+                  "is_volatile": true,
+                  "access": "read-write",
+                  "reset_value": "0x0",
+                  "fields": {
+                    "Length": {
+                      "bit_offset": 0,
+                      "bit_width": 26,
+                      "display_name": "Length",
+                      "description": "Indicates the number of bytes to transfer for the MM2S channel. Writing a non-zero value to this register starts the MM2S transfer.\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    }
+                  }
+                },
+                "S2MM_DMACR": {
+                  "address_offset": "0x30",
+                  "size": 32,
+                  "display_name": "S2MM DMA Control Register",
+                  "description": "S2MM DMA Control Register",
+                  "is_volatile": true,
+                  "access": "read-write",
+                  "reset_value": "0x10002",
+                  "fields": {
+                    "RS": {
+                      "bit_offset": 0,
+                      "bit_width": 1,
+                      "display_name": "Run/Stop Control",
+                      "description": "Run / Stop control for controlling running and stopping of the DMA channel.\n  0 - Stop, DMA stops when current (if any) DMA operations are complete. For Scatter / Gather Mode pending commands/transfers are flushed or completed. \n  AXI4-Stream outs are potentially terminated early. Descriptors in the update queue are allowed to finish updating to remote memory before engine halt.\n  For Direct Register mode pending commands/transfers are flushed or completed. AXI4-Stream outs are potentially terminated. Data integrity on S2MM AXI4 cannot be guaranteed.\n  The halted bit in the DMA Status register asserts to 1 when the DMA engine is halted. This bit is cleared by AXI DMA hardware when an error occurs. The CPU can also choose to clear this bit to stop DMA operations.\n  1 - Run, Start DMA operations. The halted bit in the DMA Status register deasserts to 0 when the DMA engine begins operations.\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    },
+                    "Reset": {
+                      "bit_offset": 2,
+                      "bit_width": 1,
+                      "display_name": "Soft Reset",
+                      "description": "Soft reset for resetting the AXI DMA core. Setting this bit to a 1 causes the AXI DMA to be reset. Reset is accomplished gracefully. Pending commands/transfers are flushed or completed.\nAXI4-Stream outs are terminated early, if necessary with associated TLAST. Setting either MM2S_DMACR.Reset = 1 or S2MM_DMACR.Reset = 1 resets the entire AXI DMA engine. After completion of a soft reset, all registers and bits are in the Reset State.      0 - Reset not in progress. Normal operation.      1 - Reset in progress\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    },
+                    "Keyhole": {
+                      "bit_offset": 3,
+                      "bit_width": 1,
+                      "display_name": "Keyhole Write",
+                      "description": "Keyhole Write. Setting this bit to 1 causes AXI DMA to initiate S2MM writes (AXI4 Writes) in non-incrementing address mode (Fixed Address Burst transfer on AXI4). This bit can be modified when AXI DMA is in idle. When enabling Key hole operation the maximum burst length cannot be more than 16. This bit should not be set when DRE is enabled.\nThis bit is non functional when DMA is used in multichannel mode.\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    },
+                    "Cyclic_BD_Enable": {
+                      "bit_offset": 4,
+                      "bit_width": 1,
+                      "display_name": "Cyclic BD Enable",
+                      "description": "When set to 1, the DMA operates in Cyclic Buffer Descriptor (BD) mode without any user intervention. In this mode, the Scatter Gather module ignores the Completed bit of the BD. With this bit set, you can use the same BDs in cyclic manner without worrying about any stale descriptor errors.\nThis bit is non functional when DMA operates in Multichannel mode. or in Direct Register Mode\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    },
+                    "IOC_IrqEn": {
+                      "bit_offset": 12,
+                      "bit_width": 1,
+                      "display_name": "Interrupt on Complete (IOC) Interrupt Enable",
+                      "description": "Interrupt on Complete (IOC) Interrupt Enable. When set to 1, allows Interrupt On Complete events to generate an interrupt out for descriptors with the Complete bit set.      0 - IOC Interrupt disabled      1 - IOC Interrupt enabled\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    },
+                    "Dly_IrqEn": {
+                      "bit_offset": 13,
+                      "bit_width": 1,
+                      "display_name": "Interrupt on Delay Timer Interrupt Enable",
+                      "description": "Interrupt on Delay Timer Interrupt Enable. When set to 1, allows error events to generate an interrupt out.      0 - Delay Interrupt disabled      1 - Delay Interrupt enabled  Note: Applicable only when Scatter Gather is enabled.\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    },
+                    "Err_IrqEn": {
+                      "bit_offset": 14,
+                      "bit_width": 1,
+                      "display_name": "Interrupt on Error Interrupt Enable",
+                      "description": "Interrupt on Error Interrupt Enable. When set to 1, allows error events to generate an interrupt out.      0 - Error Interrupt disabled      1 - Error Interrupt enabled\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    },
+                    "IRQThreshold": {
+                      "bit_offset": 16,
+                      "bit_width": 8,
+                      "display_name": "Interrupt Threshold",
+                      "description": "Interrupt Threshold. This value is used for setting the interrupt threshold. When IOC interrupt events occur, an internal counter counts down from the Interrupt Threshold setting. When the count reaches zero, an interrupt out is generated by the DMA engine.\nNote: The minimum setting for the threshold is 0x01. A write of 0x00 to this register has no effect.\nNote: Applicable only when Scatter Gather is enabled.\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    },
+                    "IRQDelay": {
+                      "bit_offset": 24,
+                      "bit_width": 8,
+                      "display_name": "Interrupt Delay Time Out",
+                      "description": "Interrupt Delay Time Out. This value is used for setting the interrupt timeout value. The interrupt timeout mechanism causes the DMA engine to generate an interrupt after the delay time period has expired. Timer begins counting at the end of a packet and resets with receipt of a new packet or a timeout event occurs.\nNote: Setting this value to zero disables the delay timer interrupt.\nNote: Applicable only when Scatter Gather is enabled.\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    }
+                  }
+                },
+                "S2MM_DMASR": {
+                  "address_offset": "0x34",
+                  "size": 32,
+                  "display_name": "S2MM DMA Status Register",
+                  "description": "S2MM DMA Status Register",
+                  "is_volatile": true,
+                  "access": "read-write",
+                  "reset_value": "0x10000",
+                  "fields": {
+                    "Halted": {
+                      "bit_offset": 0,
+                      "bit_width": 1,
+                      "display_name": "DMA Channel Halted",
+                      "description": "DMA Channel Halted. Indicates the run/stop state of the DMA channel.      0 - DMA channel running.      1 - DMA channel halted.  For Scatter/Gather Mode this bit gets set when DMACR.RS = 0 and DMA and SG operations have halted. For Direct Register Mode this bit gets set when DMACR.RS = 0 and DMA operations have halted. There can be a lag of time between when DMACR.RS = 0 and when DMASR.Halted = 1 \nNote: When halted (RS= 0 and Halted = 1), writing to CURDESC_PTR or TAILDESC_PTR pointer registers has no effect on DMA operations when in Scatter Gather Mode. For Direct Register Mode, writing to the LENGTH register has no effect on DMA operations.\n",
+                      "is_volatile": true,
+                      "access": "read-only"
+                    },
+                    "Idle": {
+                      "bit_offset": 1,
+                      "bit_width": 1,
+                      "display_name": "DMA Channel Idle",
+                      "description": "DMA Channel Idle. Indicates the state of AXI DMA operations.\nFor Scatter / Gather Mode when IDLE indicates the SG Engine has reached the tail pointer for the associated channel and all queued descriptors have been processed. Writing to the tail pointer register automatically restarts DMA operations.\nFor Direct Register Mode when IDLE indicates the current transfer has completed.      0 - Not Idle.      1 - Idle.   Note: This bit is 0 when channel is halted (DMASR.Halted=1). This bit is also 0 prior to initial transfer when AXI DMA configured for Direct Register Mode.\n",
+                      "is_volatile": true,
+                      "access": "read-only"
+                    },
+                    "SGIncld": {
+                      "bit_offset": 3,
+                      "bit_width": 1,
+                      "display_name": "SGIncld",
+                      "description": "Scatter Gather Engine Included. DMASR.SGIncld = 1 indicates the Scatter Gather engine is included and the AXI DMA is configured for Scatter Gather mode. DMASR.SGIncld = 0 indicates the Scatter Gather engine is excluded and the AXI DMA is configured for Direct Register Mode.\n",
+                      "is_volatile": true,
+                      "access": "read-only"
+                    },
+                    "DMAIntErr": {
+                      "bit_offset": 4,
+                      "bit_width": 1,
+                      "display_name": "DMA Internal Error",
+                      "description": "DMA Internal Error. This error occurs if the buffer length specified in the fetched descriptor is set to 0. Also, when in Scatter Gather Mode and using the status app length field, this error occurs when the Status AXI4-Stream packet RxLength field does not match the S2MM packet being received by the S_AXIS_S2MM interface. When Scatter Gather is disabled, this error is flagged if any error occurs during Memory write or if the incoming packet is bigger than what is specified in the DMA length register.\nThis error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No DMA Internal Errors      1 - DMA Internal Error detected.\n",
+                      "is_volatile": true,
+                      "access": "read-only"
+                    },
+                    "DMASlvErr": {
+                      "bit_offset": 5,
+                      "bit_width": 1,
+                      "display_name": "DMA Slave Error",
+                      "description": "DMA Slave Error. This error occurs if the slave read from the Memory Map interface issues a Slave Error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No DMA Slave Errors.      1 - DMA Slave Error detected.\n",
+                      "is_volatile": true,
+                      "access": "read-only"
+                    },
+                    "DMADecErr": {
+                      "bit_offset": 6,
+                      "bit_width": 1,
+                      "display_name": "DMA Decode Error",
+                      "description": "DMA Decode Error. This error occurs if the address request points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.     0 - No DMA Decode Errors.   1 - DMA Decode Error detected.\n",
+                      "is_volatile": true,
+                      "access": "read-only"
+                    },
+                    "SGIntErr": {
+                      "bit_offset": 8,
+                      "bit_width": 1,
+                      "display_name": "Scatter Gather Internal Error",
+                      "description": "Scatter Gather Internal Error. This error occurs if a descriptor with the \"Complete bit\" already set is fetched. This indicates to the SG Engine that the descriptor is a tail descriptor. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No SG Internal Errors.      1 - SG Internal Error detected.  Note: Applicable only when Scatter Gather is enabled. \n",
+                      "is_volatile": true,
+                      "access": "read-only"
+                    },
+                    "SGSlvErr": {
+                      "bit_offset": 9,
+                      "bit_width": 1,
+                      "display_name": "Scatter Gather Slave Error",
+                      "description": "Scatter Gather Slave Error. This error occurs if the slave read from on the Memory Map interface issues a Slave error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No SG Slave Errors.      1 - SG Slave Error detected. DMA Engine halts. Note: Applicable only when Scatter Gather is enabled. \n",
+                      "is_volatile": true,
+                      "access": "read-only"
+                    },
+                    "SGDecErr": {
+                      "bit_offset": 10,
+                      "bit_width": 1,
+                      "display_name": "Scatter Gather Decode Error",
+                      "description": "Scatter Gather Decode Error. This error occurs if CURDESC_PTR and/or NXTDESC_PTR points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No SG Decode Errors.      1 - SG Decode Error detected. DMA Engine halts. Note: Applicable only when Scatter Gather is enabled. \n",
+                      "is_volatile": true,
+                      "access": "read-only"
+                    },
+                    "IOC_Irq": {
+                      "bit_offset": 12,
+                      "bit_width": 1,
+                      "display_name": "Interrupt on Complete",
+                      "description": "Interrupt on Complete. When set to 1 for Scatter/Gather Mode, indicates an interrupt event was generated on completion of a descriptor. This occurs for descriptors with the End of Frame (EOF) bit set. When set to 1 for Direct Register Mode, indicates an interrupt event was generated on completion of a transfer. If the corresponding bit in S2MM_DMACR is enabled (IOC_IrqEn = 1) and if the interrupt threshold has been met, causes an interrupt out to be generated from the AXI DMA.      0 - No IOC Interrupt.      1 - IOC Interrupt detected. Writing a 1 to this bit will clear it.\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    },
+                    "Dly_Irq": {
+                      "bit_offset": 13,
+                      "bit_width": 1,
+                      "display_name": "Interrupt on Delay",
+                      "description": "Interrupt on Delay. When set to 1, indicates an interrupt event was generated on delay timer time out. If the corresponding bit is enabled in the S2MM_DMACR (Dly_IrqEn = 1), an interrupt out is generated from the AXI DMA.      0 - No Delay Interrupt.      1 - Delay Interrupt detected.1 = IOC Interrupt detected. Writing a 1 to this bit will clear it. Note: Applicable only when Scatter Gather is enabled. \n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    },
+                    "Err_Irq": {
+                      "bit_offset": 14,
+                      "bit_width": 1,
+                      "display_name": "Interrupt on Error",
+                      "description": "Interrupt on Error. When set to 1, indicates an interrupt event was generated on error. If the corresponding bit is enabled in the S2MM_DMACR (Err_IrqEn = 1), an interrupt out is generated from the AXI DMA.\nWriting a 1 to this bit will clear it.      0 - No error Interrupt.      1 - Error interrupt detected.\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    },
+                    "IRQThresholdSts": {
+                      "bit_offset": 16,
+                      "bit_width": 8,
+                      "display_name": "Interrupt Threshold Status",
+                      "description": "Interrupt Threshold Status. Indicates current interrupt threshold value.\nNote: Applicable only when Scatter Gather is enabled.\n",
+                      "is_volatile": true,
+                      "access": "read-only"
+                    },
+                    "IRQDelaySts": {
+                      "bit_offset": 24,
+                      "bit_width": 8,
+                      "display_name": "Interrupt Delay Time Status",
+                      "description": "Interrupt Delay Time Status. Indicates current interrupt delay time value.\nNote: Applicable only when Scatter Gather is enabled.\n",
+                      "is_volatile": true,
+                      "access": "read-only"
+                    }
+                  }
+                },
+                "S2MM_DA": {
+                  "address_offset": "0x48",
+                  "size": 32,
+                  "display_name": "S2MM DMA Destination Address Register",
+                  "description": "S2MM DMA Destination Address Register",
+                  "is_volatile": true,
+                  "access": "read-write",
+                  "reset_value": "0x0",
+                  "fields": {
+                    "Destination_Address": {
+                      "bit_offset": 0,
+                      "bit_width": 32,
+                      "display_name": "Destination Address",
+                      "description": "Indicates the destination address the AXI DMA writes to transfer data from AXI4-Stream on S2MM Channel.\nNote: If Data Realignment Engine is included, the Destination Address can be at any byte offset. If Data Realignment Engine is not included, the Destination Address must be S2MM Memory Map data width aligned.\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    }
+                  }
+                },
+                "S2MM_DA_MSB": {
+                  "address_offset": "0x4C",
+                  "size": 32,
+                  "display_name": "S2MM Destination Address Register",
+                  "description": "S2MM Destination Address Register",
+                  "is_volatile": true,
+                  "access": "read-write",
+                  "reset_value": "0x0",
+                  "fields": {
+                    "Destination_Address": {
+                      "bit_offset": 0,
+                      "bit_width": 32,
+                      "display_name": "Destination Address",
+                      "description": "Indicates the MSB 32 bits of the Destination address AXI DMA writes to transfer data from AXI4-Stream on the S2MM Channel.\nNote: If Data Realignment Engine is included, the Destination Address can be at any byte offset. If Data Realignment Engine is not included, the Dstination Address must be S2MM Memory Map data width aligned.\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    }
+                  }
+                },
+                "S2MM_LENGTH": {
+                  "address_offset": "0x58",
+                  "size": 32,
+                  "display_name": "S2MM DMA Transfer Length Register",
+                  "description": "S2MM DMA Transfer Length Register",
+                  "is_volatile": true,
+                  "access": "read-write",
+                  "reset_value": "0x0",
+                  "fields": {
+                    "Length": {
+                      "bit_offset": 0,
+                      "bit_width": 26,
+                      "display_name": "Length",
+                      "description": "Indicates the length in bytes of the S2MM buffer available to write receive data from the S2MM channel. Writing a non-zero value to this register enables S2MM channel to receive packet data.\nAt the completion of the S2MM transfer, the number of actual bytes written on the S2MM AXI4 interface is updated to the S2MM_LENGTH register.\nNote: This value must be greater than or equal to the largest expected packet to be received on S2MM AXI4-Stream. Values smaller than the received packet result in undefined behavior. \n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    }
+                  }
+                }
+              }
+            }
+          }
+        }
+      }
+    }
+  }
+}

cx9261a_demo_cmos_20240829/project_fix_dac.srcs/sources_1/bd/system_top/ip/system_top_axi_dma_2_0/system_top_axi_dma_2_0.xci

@@ -0,0 +1,976 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "system_top_axi_dma_2_0",
+    "cell_name": "axi_dma_2",
+    "component_reference": "xilinx.com:ip:axi_dma:7.1",
+    "ip_revision": "32",
+    "gen_directory": "../../../../../../project_fix_dac.gen/sources_1/bd/system_top/ip/system_top_axi_dma_2_0",
+    "parameters": {
+      "component_parameters": {
+        "Component_Name": [ { "value": "system_top_axi_dma_2_0", "resolve_type": "user", "usage": "all" } ],
+        "c_include_sg": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "c_enable_multi_channel": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "c_num_mm2s_channels": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "c_num_s2mm_channels": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "c_sg_length_width": [ { "value": "26", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "c_dlytmr_resolution": [ { "value": "125", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "c_prmry_is_aclk_async": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "c_sg_include_stscntrl_strm": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "c_micro_dma": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "c_include_mm2s": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "c_m_axi_mm2s_data_width": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "c_m_axis_mm2s_tdata_width": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "c_include_mm2s_dre": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "c_include_mm2s_sf": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "c_mm2s_burst_size": [ { "value": "16", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "c_include_s2mm": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "c_sg_use_stsapp_length": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "c_m_axi_s2mm_data_width": [ { "value": "64", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "c_s_axis_s2mm_tdata_width": [ { "value": "64", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "c_include_s2mm_dre": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "c_include_s2mm_sf": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "c_s2mm_burst_size": [ { "value": "16", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "c_addr_width": [ { "value": "40", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "c_single_interface": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "c_increase_throughput": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ]
+      },
+      "model_parameters": {
+        "C_S_AXI_LITE_ADDR_WIDTH": [ { "value": "10", "format": "long", "usage": "all" } ],
+        "C_S_AXI_LITE_DATA_WIDTH": [ { "value": "32", "format": "long", "usage": "all" } ],
+        "C_DLYTMR_RESOLUTION": [ { "value": "125", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PRMRY_IS_ACLK_ASYNC": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ENABLE_MULTI_CHANNEL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_NUM_MM2S_CHANNELS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_NUM_S2MM_CHANNELS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_INCLUDE_SG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_SG_INCLUDE_STSCNTRL_STRM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_SG_USE_STSAPP_LENGTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_SG_LENGTH_WIDTH": [ { "value": "26", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_M_AXI_SG_ADDR_WIDTH": [ { "value": "40", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_M_AXI_SG_DATA_WIDTH": [ { "value": "32", "format": "long", "usage": "all" } ],
+        "C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_S_AXIS_S2MM_STS_TDATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_MICRO_DMA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_INCLUDE_MM2S": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_INCLUDE_MM2S_SF": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_MM2S_BURST_SIZE": [ { "value": "16", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_M_AXI_MM2S_ADDR_WIDTH": [ { "value": "40", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_M_AXI_MM2S_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_M_AXIS_MM2S_TDATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_INCLUDE_MM2S_DRE": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_INCLUDE_S2MM": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_INCLUDE_S2MM_SF": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S2MM_BURST_SIZE": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_M_AXI_S2MM_ADDR_WIDTH": [ { "value": "40", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_M_AXI_S2MM_DATA_WIDTH": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXIS_S2MM_TDATA_WIDTH": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_INCLUDE_S2MM_DRE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_INCREASE_THROUGHPUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_FAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "zynq" } ],
+        "BASE_BOARD_PART": [ { "value": "xilinx.com:zc706:part0:1.4" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xc7z045" } ],
+        "NEXTGEN_VERSAL": [ { "value": "0" } ],
+        "PACKAGE": [ { "value": "ffg900" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Integrator" } ],
+        "IPREVISION": [ { "value": "32" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../../../project_fix_dac.gen/sources_1/bd/system_top/ip/system_top_axi_dma_2_0" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "../../ipshared" } ],
+        "SWVERSION": [ { "value": "2024.1" } ],
+        "SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "s_axi_lite_aclk": [ { "direction": "in", "driver_value": "0" } ],
+        "m_axi_s2mm_aclk": [ { "direction": "in", "driver_value": "0" } ],
+        "axi_resetn": [ { "direction": "in", "driver_value": "1" } ],
+        "s_axi_lite_awvalid": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axi_lite_awready": [ { "direction": "out" } ],
+        "s_axi_lite_awaddr": [ { "direction": "in", "size_left": "9", "size_right": "0", "driver_value": "0" } ],
+        "s_axi_lite_wvalid": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axi_lite_wready": [ { "direction": "out" } ],
+        "s_axi_lite_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
+        "s_axi_lite_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
+        "s_axi_lite_bvalid": [ { "direction": "out" } ],
+        "s_axi_lite_bready": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axi_lite_arvalid": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axi_lite_arready": [ { "direction": "out" } ],
+        "s_axi_lite_araddr": [ { "direction": "in", "size_left": "9", "size_right": "0", "driver_value": "0" } ],
+        "s_axi_lite_rvalid": [ { "direction": "out" } ],
+        "s_axi_lite_rready": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axi_lite_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
+        "s_axi_lite_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
+        "m_axi_s2mm_awaddr": [ { "direction": "out", "size_left": "39", "size_right": "0" } ],
+        "m_axi_s2mm_awlen": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
+        "m_axi_s2mm_awsize": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
+        "m_axi_s2mm_awburst": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
+        "m_axi_s2mm_awprot": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
+        "m_axi_s2mm_awcache": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
+        "m_axi_s2mm_awvalid": [ { "direction": "out" } ],
+        "m_axi_s2mm_awready": [ { "direction": "in", "driver_value": "0" } ],
+        "m_axi_s2mm_wdata": [ { "direction": "out", "size_left": "63", "size_right": "0" } ],
+        "m_axi_s2mm_wstrb": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
+        "m_axi_s2mm_wlast": [ { "direction": "out" } ],
+        "m_axi_s2mm_wvalid": [ { "direction": "out" } ],
+        "m_axi_s2mm_wready": [ { "direction": "in", "driver_value": "0" } ],
+        "m_axi_s2mm_bresp": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
+        "m_axi_s2mm_bvalid": [ { "direction": "in", "driver_value": "0" } ],
+        "m_axi_s2mm_bready": [ { "direction": "out" } ],
+        "s2mm_prmry_reset_out_n": [ { "direction": "out" } ],
+        "s_axis_s2mm_tdata": [ { "direction": "in", "size_left": "63", "size_right": "0", "driver_value": "0" } ],
+        "s_axis_s2mm_tkeep": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0xFF" } ],
+        "s_axis_s2mm_tvalid": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axis_s2mm_tready": [ { "direction": "out" } ],
+        "s_axis_s2mm_tlast": [ { "direction": "in", "driver_value": "0" } ],
+        "s2mm_introut": [ { "direction": "out" } ],
+        "axi_dma_tstvec": [ { "direction": "out", "size_left": "31", "size_right": "0" } ]
+      },
+      "interfaces": {
+        "S_AXI_LITE": {
+          "vlnv": "xilinx.com:interface:aximm:1.0",
+          "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
+          "mode": "slave",
+          "memory_map_ref": "S_AXI_LITE",
+          "parameters": {
+            "DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "ADDR_WIDTH": [ { "value": "10", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_PROT": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_WSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "MAX_BURST_LENGTH": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_top_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "ARADDR": [ { "physical_name": "s_axi_lite_araddr" } ],
+            "ARREADY": [ { "physical_name": "s_axi_lite_arready" } ],
+            "ARVALID": [ { "physical_name": "s_axi_lite_arvalid" } ],
+            "AWADDR": [ { "physical_name": "s_axi_lite_awaddr" } ],
+            "AWREADY": [ { "physical_name": "s_axi_lite_awready" } ],
+            "AWVALID": [ { "physical_name": "s_axi_lite_awvalid" } ],
+            "BREADY": [ { "physical_name": "s_axi_lite_bready" } ],
+            "BRESP": [ { "physical_name": "s_axi_lite_bresp" } ],
+            "BVALID": [ { "physical_name": "s_axi_lite_bvalid" } ],
+            "RDATA": [ { "physical_name": "s_axi_lite_rdata" } ],
+            "RREADY": [ { "physical_name": "s_axi_lite_rready" } ],
+            "RRESP": [ { "physical_name": "s_axi_lite_rresp" } ],
+            "RVALID": [ { "physical_name": "s_axi_lite_rvalid" } ],
+            "WDATA": [ { "physical_name": "s_axi_lite_wdata" } ],
+            "WREADY": [ { "physical_name": "s_axi_lite_wready" } ],
+            "WVALID": [ { "physical_name": "s_axi_lite_wvalid" } ]
+          }
+        },
+        "M_AXI_S2MM": {
+          "vlnv": "xilinx.com:interface:aximm:1.0",
+          "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
+          "mode": "master",
+          "address_space_ref": "Data_S2MM",
+          "parameters": {
+            "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
+            "NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
+            "DATA_WIDTH": [ { "value": "64", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PROTOCOL": [ { "value": "AXI4", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "200000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "ADDR_WIDTH": [ { "value": "40", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "AWUSER_WIDTH": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "WRITE_ONLY", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_PROT": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_CACHE": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_WSTRB": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_BRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_RRESP": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "MAX_BURST_LENGTH": [ { "value": "16", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_top_mig_7series_0_0_ui_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "AWADDR": [ { "physical_name": "m_axi_s2mm_awaddr" } ],
+            "AWBURST": [ { "physical_name": "m_axi_s2mm_awburst" } ],
+            "AWCACHE": [ { "physical_name": "m_axi_s2mm_awcache" } ],
+            "AWLEN": [ { "physical_name": "m_axi_s2mm_awlen" } ],
+            "AWPROT": [ { "physical_name": "m_axi_s2mm_awprot" } ],
+            "AWREADY": [ { "physical_name": "m_axi_s2mm_awready" } ],
+            "AWSIZE": [ { "physical_name": "m_axi_s2mm_awsize" } ],
+            "AWVALID": [ { "physical_name": "m_axi_s2mm_awvalid" } ],
+            "BREADY": [ { "physical_name": "m_axi_s2mm_bready" } ],
+            "BRESP": [ { "physical_name": "m_axi_s2mm_bresp" } ],
+            "BVALID": [ { "physical_name": "m_axi_s2mm_bvalid" } ],
+            "WDATA": [ { "physical_name": "m_axi_s2mm_wdata" } ],
+            "WLAST": [ { "physical_name": "m_axi_s2mm_wlast" } ],
+            "WREADY": [ { "physical_name": "m_axi_s2mm_wready" } ],
+            "WSTRB": [ { "physical_name": "m_axi_s2mm_wstrb" } ],
+            "WVALID": [ { "physical_name": "m_axi_s2mm_wvalid" } ]
+          }
+        },
+        "S_AXIS_S2MM": {
+          "vlnv": "xilinx.com:interface:axis:1.0",
+          "abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "TDATA_NUM_BYTES": [ { "value": "8", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TDEST_WIDTH": [ { "value": "0", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TID_WIDTH": [ { "value": "0", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TREADY": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TKEEP": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TLAST": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "200000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_top_mig_7series_0_0_ui_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "TDATA": [ { "physical_name": "s_axis_s2mm_tdata" } ],
+            "TKEEP": [ { "physical_name": "s_axis_s2mm_tkeep" } ],
+            "TLAST": [ { "physical_name": "s_axis_s2mm_tlast" } ],
+            "TREADY": [ { "physical_name": "s_axis_s2mm_tready" } ],
+            "TVALID": [ { "physical_name": "s_axis_s2mm_tvalid" } ]
+          }
+        },
+        "AXI_RESETN": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "axi_resetn" } ]
+          }
+        },
+        "MM2S_INTROUT": {
+          "vlnv": "xilinx.com:signal:interrupt:1.0",
+          "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "SENSITIVITY": [ { "value": "LEVEL_HIGH", "value_src": "constant", "usage": "all" } ],
+            "PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "S2MM_INTROUT": {
+          "vlnv": "xilinx.com:signal:interrupt:1.0",
+          "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "SENSITIVITY": [ { "value": "LEVEL_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "PortWidth": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "INTERRUPT": [ { "physical_name": "s2mm_introut" } ]
+          }
+        },
+        "M_AXI_SG_CLK": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "M_AXI_SG", "value_src": "constant", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "M_AXI_MM2S_CLK": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "M_AXI_MM2S:M_AXIS_MM2S:M_AXIS_CNTRL", "value_src": "constant", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "mm2s_prmry_reset_out_n:mm2s_cntrl_reset_out_n", "value_src": "constant", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "M_AXI_S2MM_CLK": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "M_AXI_S2MM:S_AXIS_S2MM:S_AXIS_STS", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "s2mm_prmry_reset_out_n:s2mm_sts_reset_out_n", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "200000000", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_top_mig_7series_0_0_ui_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "m_axi_s2mm_aclk" } ]
+          }
+        },
+        "S_AXI_LITE_ACLK": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "S_AXI_LITE:M_AXI", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "axi_resetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_top_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "s_axi_lite_aclk" } ]
+          }
+        },
+        "MM2S_PRMRY_RESET_OUT_N": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "S2MM_PRMRY_RESET_OUT_N": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "s2mm_prmry_reset_out_n" } ]
+          }
+        },
+        "MM2S_CNTRL_RESET_OUT_N": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "S2MM_STS_RESET_OUT_N": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        }
+      },
+      "address_spaces": {
+        "Data_S2MM": {
+          "range": "1099511627776",
+          "width": "40"
+        }
+      },
+      "memory_maps": {
+        "S_AXI_LITE": {
+          "display_name": "S_AXI_MEM",
+          "description": "Memory Map for S_AXI_LITE",
+          "address_blocks": {
+            "Reg": {
+              "base_address": "0",
+              "range": "4096",
+              "display_name": "Reg",
+              "description": "Register Block",
+              "usage": "register",
+              "access": "read-write",
+              "registers": {
+                "MM2S_DMACR": {
+                  "address_offset": "0x0",
+                  "size": 32,
+                  "display_name": "MM2S DMA Control Register",
+                  "description": "MM2S DMA Control Register",
+                  "is_volatile": true,
+                  "access": "read-write",
+                  "reset_value": "0x10002",
+                  "fields": {
+                    "RS": {
+                      "bit_offset": 0,
+                      "bit_width": 1,
+                      "display_name": "Run/Stop Control",
+                      "description": "Run / Stop control for controlling running and stopping of the DMA channel.\n  0 - Stop, DMA stops when current (if any) DMA operations are complete. For Scatter / Gather Mode pending commands/transfers are flushed or completed. \n  AXI4-Stream outs are potentially terminated early. Descriptors in the update queue are allowed to finish updating to remote memory before engine halt.\n  For Direct Register mode pending commands/transfers are flushed or completed. AXI4-Stream outs are potentially terminated.\n  The halted bit in the DMA Status register asserts to 1 when the DMA engine is halted. This bit is cleared by AXI DMA hardware when an error occurs. The CPU can also choose to clear this bit to stop DMA operations.\n  1 - Run, Start DMA operations. The halted bit in the DMA Status register deasserts to 0 when the DMA engine begins operations.\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    },
+                    "Reset": {
+                      "bit_offset": 2,
+                      "bit_width": 1,
+                      "display_name": "Soft Reset",
+                      "description": "Soft reset for resetting the AXI DMA core. Setting this bit to a 1 causes the AXI DMA to be reset. Reset is accomplished gracefully. Pending commands/transfers are flushed or completed.\nAXI4-Stream outs are potentially terminated early. Setting either MM2S_DMACR. Reset = 1 or S2MM_DMACR.Reset = 1 resets the entire AXI DMA engine. After completion of a soft reset, all registers and bits are in the Reset State.      0 - Normal operation.   1 - Reset in progress.\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    },
+                    "Keyhole": {
+                      "bit_offset": 3,
+                      "bit_width": 1,
+                      "display_name": "Keyhole Read",
+                      "description": "Keyhole Read. Setting this bit to 1 causes AXI DMA to initiate MM2S reads (AXI4read) in non-incrementing address mode (Fixed Address Burst transfer on AXI4). This bit can be updated when AXI DMA is in idle. When using keyhole operation the Max Burst Length should not exceed 16. This bit should not be set when DRE is enabled.\nThis bit is non functional when the multichannel feature is enabled or in Direct Register mode.\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    },
+                    "Cyclic_BD_Enable": {
+                      "bit_offset": 4,
+                      "bit_width": 1,
+                      "display_name": "Cyclic BD Enable",
+                      "description": "When set to 1, the DMA operates in Cyclic Buffer Descriptor (BD) mode without any user intervention. In this mode, the Scatter Gather module ignores the Completed bit of the BD. With this bit set, you can use the same BDs in cyclic manner without worrying about any stale descriptor errors.\nThis bit should be set/unset only when the DMA is idle or when not running. Updating this bit while the DMA is running can result in unexpected behavior.\nThis bit is non functional when DMA operates in multichannel mode.\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    },
+                    "IOC_IrqEn": {
+                      "bit_offset": 12,
+                      "bit_width": 1,
+                      "display_name": "Interrupt on Complete (IOC) Interrupt Enable",
+                      "description": "Interrupt on Complete (IOC) Interrupt Enable. When set to 1, allows DMASR.IOC_Irq to generate an interrupt out for descriptors with the IOC bit set.   0 - IOC Interrupt disabled      1 - IOC Interrupt enabled\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    },
+                    "Dly_IrqEn": {
+                      "bit_offset": 13,
+                      "bit_width": 1,
+                      "display_name": "Interrupt on Delay Timer Interrupt Enable",
+                      "description": "Interrupt on Delay Timer Interrupt Enable. When set to 1, allows DMASR.Dly_Irq to generate an interrupt out.      0 - Delay Interrupt disabled   1 - Delay Interrupt enabled Note: This field is ignored when AXI DMA is configured for Direct Register Mode.\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    },
+                    "Err_IrqEn": {
+                      "bit_offset": 14,
+                      "bit_width": 1,
+                      "display_name": "Interrupt on Error Interrupt Enable",
+                      "description": "Interrupt on Error Interrupt Enable.\n  0 - Error Interrupt disabled\n  1 - Error Interrupt enabled\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    },
+                    "IRQThreshold": {
+                      "bit_offset": 16,
+                      "bit_width": 8,
+                      "display_name": "Interrupt Threshold",
+                      "description": "Interrupt Threshold. This value is used for setting the interrupt threshold. When IOC interrupt events occur, an internal counter counts down from the Interrupt Threshold setting. When the count reaches zero, an interrupt out is generated by the DMA engine.   Note: The minimum setting for the threshold is 0x01. A write of 0x00 to this register has no effect.   Note: This field is ignored when AXI DMA is configured for Direct Register Mode.\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    },
+                    "IRQDelay": {
+                      "bit_offset": 24,
+                      "bit_width": 8,
+                      "display_name": "Interrupt Delay Time Out",
+                      "description": "Interrupt Delay Time Out. This value is used for setting the interrupt timeout value. The interrupt timeout mechanism causes the DMA engine to generate an interrupt after the delay time period has expired. Timer begins counting at the end of a packet and resets with receipt of a new packet or a timeout event occurs.\nNote: Setting this value to zero disables the delay timer interrupt.\nNote: This field is ignored when AXI DMA is configured for Direct Register Mode.\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    }
+                  }
+                },
+                "MM2S_DMASR": {
+                  "address_offset": "0x04",
+                  "size": 32,
+                  "display_name": "MM2S DMA Status Register",
+                  "description": "MM2S DMA Status Register",
+                  "is_volatile": true,
+                  "access": "read-write",
+                  "reset_value": "0x10000",
+                  "fields": {
+                    "Halted": {
+                      "bit_offset": 0,
+                      "bit_width": 1,
+                      "display_name": "DMA Channel Halted",
+                      "description": "DMA Channel Halted. Indicates the run/stop state of the DMA channel.      0 - DMA channel running.      1 - DMA channel halted.  For Scatter / Gather Mode this bit gets set when DMACR.RS = 0 and DMA and SG operations have halted. For Direct Register mode (C_INCLUDE_SG = 0) this bit gets set when DMACR.RS = 0 and DMA operations have halted. There can be a lag of time between when DMACR.RS = 0 and when DMASR.Halted = 1 Note: When halted (RS= 0 and Halted = 1), writing to CURDESC_PTR or TAILDESC_PTR pointer registers has no effect on DMA operations when in Scatter Gather Mode. For Direct Register Mode, writing to the LENGTH register has no effect on DMA operations.\n",
+                      "is_volatile": true,
+                      "access": "read-only"
+                    },
+                    "Idle": {
+                      "bit_offset": 1,
+                      "bit_width": 1,
+                      "display_name": "DMA Channel Idle",
+                      "description": "DMA Channel Idle. Indicates the state of AXI DMA operations.\nFor Scatter / Gather Mode when IDLE indicates the SG Engine has reached the tail pointer for the associated channel and all queued descriptors have been processed. Writing to the tail pointer register automatically restarts DMA operations.\nFor Direct Register Mode when IDLE indicates the current transfer has completed.      0 - Not Idle. For Scatter / Gather Mode, SG has not reached tail descriptor pointer and/or DMA operations in progress. For Direct Register Mode, transfer is not complete.      1 - Idle. For Scatter / Gather Mode, SG has reached tail descriptor pointer and DMA operation paused. for Direct Register Mode, DMA transfer has completed and controller is paused.  Note: This bit is 0 when channel is halted (DMASR.Halted=1). This bit is also 0 prior to initial transfer when AXI DMA configured for Direct Register Mode.\n",
+                      "is_volatile": true,
+                      "access": "read-only"
+                    },
+                    "SGIncld": {
+                      "bit_offset": 3,
+                      "bit_width": 1,
+                      "display_name": "SGIncld",
+                      "description": "1 - Scatter Gather Enabled\n0 - Scatter Gather not enabled\n",
+                      "is_volatile": true,
+                      "access": "read-only"
+                    },
+                    "DMAIntErr": {
+                      "bit_offset": 4,
+                      "bit_width": 1,
+                      "display_name": "DMA Internal Error",
+                      "description": "DMA Internal Error. Internal error occurs if the buffer length specified in the fetched descriptor is set to 0. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No DMA Internal Errors        1 - DMA Internal Error detected. DMA Engine halts\n",
+                      "is_volatile": true,
+                      "access": "read-only"
+                    },
+                    "DMASlvErr": {
+                      "bit_offset": 5,
+                      "bit_width": 1,
+                      "display_name": "DMA Slave Error",
+                      "description": "DMA Slave Error. This error occurs if the slave read from the Memory Map interface issues a Slave Error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No DMA Slave Errors.      1 - DMA Slave Error detected. DMA Engine halts\n",
+                      "is_volatile": true,
+                      "access": "read-only"
+                    },
+                    "DMADecErr": {
+                      "bit_offset": 6,
+                      "bit_width": 1,
+                      "display_name": "DMA Decode Error",
+                      "description": "DMA Decode Error. This error occurs if the address request points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No DMA Decode Errors.      1 - DMA Decode Error detected. DMA Engine halts.\n",
+                      "is_volatile": true,
+                      "access": "read-only"
+                    },
+                    "SGIntErr": {
+                      "bit_offset": 8,
+                      "bit_width": 1,
+                      "display_name": "Scatter Gather Internal Error",
+                      "description": "Scatter Gather Internal Error. This error occurs if a descriptor with the \"Complete bit\" already set is fetched. Refer to the Scatter Gather Descriptor section for more information.This indicates to the SG Engine that the descriptor is a stale descriptor. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No SG Internal Errors.      1 - SG Internal Error detected. DMA Engine halts.  Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode.\n",
+                      "is_volatile": true,
+                      "access": "read-only"
+                    },
+                    "SGSlvErr": {
+                      "bit_offset": 9,
+                      "bit_width": 1,
+                      "display_name": "Scatter Gather Slave Error",
+                      "description": "Scatter Gather Slave Error. This error occurs if the slave read from on the Memory Map interface issues a Slave error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No SG Slave Errors.      1 - SG Slave Error detected. DMA Engine halts.  Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode. \n",
+                      "is_volatile": true,
+                      "access": "read-only"
+                    },
+                    "SGDecErr": {
+                      "bit_offset": 10,
+                      "bit_width": 1,
+                      "display_name": "Scatter Gather Decode Error",
+                      "description": "Scatter Gather Decode Error. This error occurs if CURDESC_PTR and/or NXTDESC_PTR points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No SG Decode Errors.      1 - SG Decode Error detected. DMA Engine halts.  Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode. \n",
+                      "is_volatile": true,
+                      "access": "read-only"
+                    },
+                    "IOC_Irq": {
+                      "bit_offset": 12,
+                      "bit_width": 1,
+                      "display_name": "Interrupt on Complete",
+                      "description": "Interrupt on Complete. When set to 1 for Scatter/Gather Mode, indicates an interrupt event was generated on completion of a descriptor. This occurs for descriptors with the End of Frame (EOF) bit set. When set to 1 for Direct Register Mode, indicates an interrupt event was generated on completion of a transfer. If the corresponding bit is enabled in the MM2S_DMACR (IOC_IrqEn = 1) and if the interrupt threshold has been met, causes an interrupt out to be generated from the AXI DMA.      0 - No IOC Interrupt.      1 - IOC Interrupt detected.  Writing a 1 to this bit will clear it.\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    },
+                    "Dly_Irq": {
+                      "bit_offset": 13,
+                      "bit_width": 1,
+                      "display_name": "Interrupt on Delay",
+                      "description": "Interrupt on Delay. When set to 1, indicates an interrupt event was generated on delay timer time out. If the corresponding bit is enabled in the MM2S_DMACR (Dly_IrqEn = 1), an interrupt out is generated from the AXI DMA.      0 - No Delay Interrupt.      1 - Delay Interrupt detected. Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode. \n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    },
+                    "Err_Irq": {
+                      "bit_offset": 14,
+                      "bit_width": 1,
+                      "display_name": "Interrupt on Error",
+                      "description": "Interrupt on Error. When set to 1, indicates an interrupt event was generated on error. If the corresponding bit is enabled in the MM2S_DMACR (Err_IrqEn = 1), an interrupt out is generated from the AXI DMA.\nWriting a 1 to this bit will clear it.   \n0 - No error Interrupt.   \n1 - Error interrupt detected.\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    },
+                    "IRQThresholdSts": {
+                      "bit_offset": 16,
+                      "bit_width": 8,
+                      "display_name": "Interrupt Threshold Status",
+                      "description": "Interrupt Threshold Status. Indicates current interrupt threshold value.\nNote: Applicable only when Scatter Gather is enabled.\n",
+                      "is_volatile": true,
+                      "access": "read-only"
+                    },
+                    "IRQDelaySts": {
+                      "bit_offset": 24,
+                      "bit_width": 8,
+                      "display_name": "Interrupt Delay Time Status",
+                      "description": "Interrupt Delay Time Status. Indicates current interrupt delay time value.\nNote: Applicable only when Scatter Gather is enabled.\n",
+                      "is_volatile": true,
+                      "access": "read-only"
+                    }
+                  }
+                },
+                "MM2S_SA": {
+                  "address_offset": "0x18",
+                  "size": 32,
+                  "display_name": "MM2S Source Address Register",
+                  "description": "MM2S Source Address Register",
+                  "is_volatile": true,
+                  "access": "read-write",
+                  "reset_value": "0x0",
+                  "fields": {
+                    "Source_Address": {
+                      "bit_offset": 0,
+                      "bit_width": 32,
+                      "display_name": "Source Address",
+                      "description": "Indicates the source address AXI DMA reads from to transfer data to AXI4-Stream on the MM2S Channel.\nNote: If Data Realignment Engine is included, the Source Address can be at any byte offset. If Data Realignment Engine is not included, the Source Address must be MM2S Memory Map data width aligned.\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    }
+                  }
+                },
+                "MM2S_SA_MSB": {
+                  "address_offset": "0x1C",
+                  "size": 32,
+                  "display_name": "MM2S Source Address Register",
+                  "description": "MM2S Source Address Register",
+                  "is_volatile": true,
+                  "access": "read-write",
+                  "reset_value": "0x0",
+                  "fields": {
+                    "Source_Address": {
+                      "bit_offset": 0,
+                      "bit_width": 32,
+                      "display_name": "Source Address",
+                      "description": "Indicates the MSB 32 bits of the source address AXI DMA reads from to transfer data to AXI4-Stream on the MM2S Channel.\nNote: If Data Realignment Engine is included, the Source Address can be at any byte offset. If Data Realignment Engine is not included, the Source Address must be MM2S Memory Map data width aligned.\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    }
+                  }
+                },
+                "MM2S_LENGTH": {
+                  "address_offset": "0x28",
+                  "size": 32,
+                  "display_name": "MM2S DMA Transfer Length Register",
+                  "description": "MM2S DMA Transfer Length Register",
+                  "is_volatile": true,
+                  "access": "read-write",
+                  "reset_value": "0x0",
+                  "fields": {
+                    "Length": {
+                      "bit_offset": 0,
+                      "bit_width": 26,
+                      "display_name": "Length",
+                      "description": "Indicates the number of bytes to transfer for the MM2S channel. Writing a non-zero value to this register starts the MM2S transfer.\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    }
+                  }
+                },
+                "S2MM_DMACR": {
+                  "address_offset": "0x30",
+                  "size": 32,
+                  "display_name": "S2MM DMA Control Register",
+                  "description": "S2MM DMA Control Register",
+                  "is_volatile": true,
+                  "access": "read-write",
+                  "reset_value": "0x10002",
+                  "fields": {
+                    "RS": {
+                      "bit_offset": 0,
+                      "bit_width": 1,
+                      "display_name": "Run/Stop Control",
+                      "description": "Run / Stop control for controlling running and stopping of the DMA channel.\n  0 - Stop, DMA stops when current (if any) DMA operations are complete. For Scatter / Gather Mode pending commands/transfers are flushed or completed. \n  AXI4-Stream outs are potentially terminated early. Descriptors in the update queue are allowed to finish updating to remote memory before engine halt.\n  For Direct Register mode pending commands/transfers are flushed or completed. AXI4-Stream outs are potentially terminated. Data integrity on S2MM AXI4 cannot be guaranteed.\n  The halted bit in the DMA Status register asserts to 1 when the DMA engine is halted. This bit is cleared by AXI DMA hardware when an error occurs. The CPU can also choose to clear this bit to stop DMA operations.\n  1 - Run, Start DMA operations. The halted bit in the DMA Status register deasserts to 0 when the DMA engine begins operations.\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    },
+                    "Reset": {
+                      "bit_offset": 2,
+                      "bit_width": 1,
+                      "display_name": "Soft Reset",
+                      "description": "Soft reset for resetting the AXI DMA core. Setting this bit to a 1 causes the AXI DMA to be reset. Reset is accomplished gracefully. Pending commands/transfers are flushed or completed.\nAXI4-Stream outs are terminated early, if necessary with associated TLAST. Setting either MM2S_DMACR.Reset = 1 or S2MM_DMACR.Reset = 1 resets the entire AXI DMA engine. After completion of a soft reset, all registers and bits are in the Reset State.      0 - Reset not in progress. Normal operation.      1 - Reset in progress\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    },
+                    "Keyhole": {
+                      "bit_offset": 3,
+                      "bit_width": 1,
+                      "display_name": "Keyhole Write",
+                      "description": "Keyhole Write. Setting this bit to 1 causes AXI DMA to initiate S2MM writes (AXI4 Writes) in non-incrementing address mode (Fixed Address Burst transfer on AXI4). This bit can be modified when AXI DMA is in idle. When enabling Key hole operation the maximum burst length cannot be more than 16. This bit should not be set when DRE is enabled.\nThis bit is non functional when DMA is used in multichannel mode.\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    },
+                    "Cyclic_BD_Enable": {
+                      "bit_offset": 4,
+                      "bit_width": 1,
+                      "display_name": "Cyclic BD Enable",
+                      "description": "When set to 1, the DMA operates in Cyclic Buffer Descriptor (BD) mode without any user intervention. In this mode, the Scatter Gather module ignores the Completed bit of the BD. With this bit set, you can use the same BDs in cyclic manner without worrying about any stale descriptor errors.\nThis bit is non functional when DMA operates in Multichannel mode. or in Direct Register Mode\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    },
+                    "IOC_IrqEn": {
+                      "bit_offset": 12,
+                      "bit_width": 1,
+                      "display_name": "Interrupt on Complete (IOC) Interrupt Enable",
+                      "description": "Interrupt on Complete (IOC) Interrupt Enable. When set to 1, allows Interrupt On Complete events to generate an interrupt out for descriptors with the Complete bit set.      0 - IOC Interrupt disabled      1 - IOC Interrupt enabled\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    },
+                    "Dly_IrqEn": {
+                      "bit_offset": 13,
+                      "bit_width": 1,
+                      "display_name": "Interrupt on Delay Timer Interrupt Enable",
+                      "description": "Interrupt on Delay Timer Interrupt Enable. When set to 1, allows error events to generate an interrupt out.      0 - Delay Interrupt disabled      1 - Delay Interrupt enabled  Note: Applicable only when Scatter Gather is enabled.\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    },
+                    "Err_IrqEn": {
+                      "bit_offset": 14,
+                      "bit_width": 1,
+                      "display_name": "Interrupt on Error Interrupt Enable",
+                      "description": "Interrupt on Error Interrupt Enable. When set to 1, allows error events to generate an interrupt out.      0 - Error Interrupt disabled      1 - Error Interrupt enabled\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    },
+                    "IRQThreshold": {
+                      "bit_offset": 16,
+                      "bit_width": 8,
+                      "display_name": "Interrupt Threshold",
+                      "description": "Interrupt Threshold. This value is used for setting the interrupt threshold. When IOC interrupt events occur, an internal counter counts down from the Interrupt Threshold setting. When the count reaches zero, an interrupt out is generated by the DMA engine.\nNote: The minimum setting for the threshold is 0x01. A write of 0x00 to this register has no effect.\nNote: Applicable only when Scatter Gather is enabled.\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    },
+                    "IRQDelay": {
+                      "bit_offset": 24,
+                      "bit_width": 8,
+                      "display_name": "Interrupt Delay Time Out",
+                      "description": "Interrupt Delay Time Out. This value is used for setting the interrupt timeout value. The interrupt timeout mechanism causes the DMA engine to generate an interrupt after the delay time period has expired. Timer begins counting at the end of a packet and resets with receipt of a new packet or a timeout event occurs.\nNote: Setting this value to zero disables the delay timer interrupt.\nNote: Applicable only when Scatter Gather is enabled.\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    }
+                  }
+                },
+                "S2MM_DMASR": {
+                  "address_offset": "0x34",
+                  "size": 32,
+                  "display_name": "S2MM DMA Status Register",
+                  "description": "S2MM DMA Status Register",
+                  "is_volatile": true,
+                  "access": "read-write",
+                  "reset_value": "0x10000",
+                  "fields": {
+                    "Halted": {
+                      "bit_offset": 0,
+                      "bit_width": 1,
+                      "display_name": "DMA Channel Halted",
+                      "description": "DMA Channel Halted. Indicates the run/stop state of the DMA channel.      0 - DMA channel running.      1 - DMA channel halted.  For Scatter/Gather Mode this bit gets set when DMACR.RS = 0 and DMA and SG operations have halted. For Direct Register Mode this bit gets set when DMACR.RS = 0 and DMA operations have halted. There can be a lag of time between when DMACR.RS = 0 and when DMASR.Halted = 1 \nNote: When halted (RS= 0 and Halted = 1), writing to CURDESC_PTR or TAILDESC_PTR pointer registers has no effect on DMA operations when in Scatter Gather Mode. For Direct Register Mode, writing to the LENGTH register has no effect on DMA operations.\n",
+                      "is_volatile": true,
+                      "access": "read-only"
+                    },
+                    "Idle": {
+                      "bit_offset": 1,
+                      "bit_width": 1,
+                      "display_name": "DMA Channel Idle",
+                      "description": "DMA Channel Idle. Indicates the state of AXI DMA operations.\nFor Scatter / Gather Mode when IDLE indicates the SG Engine has reached the tail pointer for the associated channel and all queued descriptors have been processed. Writing to the tail pointer register automatically restarts DMA operations.\nFor Direct Register Mode when IDLE indicates the current transfer has completed.      0 - Not Idle.      1 - Idle.   Note: This bit is 0 when channel is halted (DMASR.Halted=1). This bit is also 0 prior to initial transfer when AXI DMA configured for Direct Register Mode.\n",
+                      "is_volatile": true,
+                      "access": "read-only"
+                    },
+                    "SGIncld": {
+                      "bit_offset": 3,
+                      "bit_width": 1,
+                      "display_name": "SGIncld",
+                      "description": "Scatter Gather Engine Included. DMASR.SGIncld = 1 indicates the Scatter Gather engine is included and the AXI DMA is configured for Scatter Gather mode. DMASR.SGIncld = 0 indicates the Scatter Gather engine is excluded and the AXI DMA is configured for Direct Register Mode.\n",
+                      "is_volatile": true,
+                      "access": "read-only"
+                    },
+                    "DMAIntErr": {
+                      "bit_offset": 4,
+                      "bit_width": 1,
+                      "display_name": "DMA Internal Error",
+                      "description": "DMA Internal Error. This error occurs if the buffer length specified in the fetched descriptor is set to 0. Also, when in Scatter Gather Mode and using the status app length field, this error occurs when the Status AXI4-Stream packet RxLength field does not match the S2MM packet being received by the S_AXIS_S2MM interface. When Scatter Gather is disabled, this error is flagged if any error occurs during Memory write or if the incoming packet is bigger than what is specified in the DMA length register.\nThis error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No DMA Internal Errors      1 - DMA Internal Error detected.\n",
+                      "is_volatile": true,
+                      "access": "read-only"
+                    },
+                    "DMASlvErr": {
+                      "bit_offset": 5,
+                      "bit_width": 1,
+                      "display_name": "DMA Slave Error",
+                      "description": "DMA Slave Error. This error occurs if the slave read from the Memory Map interface issues a Slave Error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No DMA Slave Errors.      1 - DMA Slave Error detected.\n",
+                      "is_volatile": true,
+                      "access": "read-only"
+                    },
+                    "DMADecErr": {
+                      "bit_offset": 6,
+                      "bit_width": 1,
+                      "display_name": "DMA Decode Error",
+                      "description": "DMA Decode Error. This error occurs if the address request points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.     0 - No DMA Decode Errors.   1 - DMA Decode Error detected.\n",
+                      "is_volatile": true,
+                      "access": "read-only"
+                    },
+                    "SGIntErr": {
+                      "bit_offset": 8,
+                      "bit_width": 1,
+                      "display_name": "Scatter Gather Internal Error",
+                      "description": "Scatter Gather Internal Error. This error occurs if a descriptor with the \"Complete bit\" already set is fetched. This indicates to the SG Engine that the descriptor is a tail descriptor. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No SG Internal Errors.      1 - SG Internal Error detected.  Note: Applicable only when Scatter Gather is enabled. \n",
+                      "is_volatile": true,
+                      "access": "read-only"
+                    },
+                    "SGSlvErr": {
+                      "bit_offset": 9,
+                      "bit_width": 1,
+                      "display_name": "Scatter Gather Slave Error",
+                      "description": "Scatter Gather Slave Error. This error occurs if the slave read from on the Memory Map interface issues a Slave error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No SG Slave Errors.      1 - SG Slave Error detected. DMA Engine halts. Note: Applicable only when Scatter Gather is enabled. \n",
+                      "is_volatile": true,
+                      "access": "read-only"
+                    },
+                    "SGDecErr": {
+                      "bit_offset": 10,
+                      "bit_width": 1,
+                      "display_name": "Scatter Gather Decode Error",
+                      "description": "Scatter Gather Decode Error. This error occurs if CURDESC_PTR and/or NXTDESC_PTR points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No SG Decode Errors.      1 - SG Decode Error detected. DMA Engine halts. Note: Applicable only when Scatter Gather is enabled. \n",
+                      "is_volatile": true,
+                      "access": "read-only"
+                    },
+                    "IOC_Irq": {
+                      "bit_offset": 12,
+                      "bit_width": 1,
+                      "display_name": "Interrupt on Complete",
+                      "description": "Interrupt on Complete. When set to 1 for Scatter/Gather Mode, indicates an interrupt event was generated on completion of a descriptor. This occurs for descriptors with the End of Frame (EOF) bit set. When set to 1 for Direct Register Mode, indicates an interrupt event was generated on completion of a transfer. If the corresponding bit in S2MM_DMACR is enabled (IOC_IrqEn = 1) and if the interrupt threshold has been met, causes an interrupt out to be generated from the AXI DMA.      0 - No IOC Interrupt.      1 - IOC Interrupt detected. Writing a 1 to this bit will clear it.\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    },
+                    "Dly_Irq": {
+                      "bit_offset": 13,
+                      "bit_width": 1,
+                      "display_name": "Interrupt on Delay",
+                      "description": "Interrupt on Delay. When set to 1, indicates an interrupt event was generated on delay timer time out. If the corresponding bit is enabled in the S2MM_DMACR (Dly_IrqEn = 1), an interrupt out is generated from the AXI DMA.      0 - No Delay Interrupt.      1 - Delay Interrupt detected.1 = IOC Interrupt detected. Writing a 1 to this bit will clear it. Note: Applicable only when Scatter Gather is enabled. \n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    },
+                    "Err_Irq": {
+                      "bit_offset": 14,
+                      "bit_width": 1,
+                      "display_name": "Interrupt on Error",
+                      "description": "Interrupt on Error. When set to 1, indicates an interrupt event was generated on error. If the corresponding bit is enabled in the S2MM_DMACR (Err_IrqEn = 1), an interrupt out is generated from the AXI DMA.\nWriting a 1 to this bit will clear it.      0 - No error Interrupt.      1 - Error interrupt detected.\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    },
+                    "IRQThresholdSts": {
+                      "bit_offset": 16,
+                      "bit_width": 8,
+                      "display_name": "Interrupt Threshold Status",
+                      "description": "Interrupt Threshold Status. Indicates current interrupt threshold value.\nNote: Applicable only when Scatter Gather is enabled.\n",
+                      "is_volatile": true,
+                      "access": "read-only"
+                    },
+                    "IRQDelaySts": {
+                      "bit_offset": 24,
+                      "bit_width": 8,
+                      "display_name": "Interrupt Delay Time Status",
+                      "description": "Interrupt Delay Time Status. Indicates current interrupt delay time value.\nNote: Applicable only when Scatter Gather is enabled.\n",
+                      "is_volatile": true,
+                      "access": "read-only"
+                    }
+                  }
+                },
+                "S2MM_DA": {
+                  "address_offset": "0x48",
+                  "size": 32,
+                  "display_name": "S2MM DMA Destination Address Register",
+                  "description": "S2MM DMA Destination Address Register",
+                  "is_volatile": true,
+                  "access": "read-write",
+                  "reset_value": "0x0",
+                  "fields": {
+                    "Destination_Address": {
+                      "bit_offset": 0,
+                      "bit_width": 32,
+                      "display_name": "Destination Address",
+                      "description": "Indicates the destination address the AXI DMA writes to transfer data from AXI4-Stream on S2MM Channel.\nNote: If Data Realignment Engine is included, the Destination Address can be at any byte offset. If Data Realignment Engine is not included, the Destination Address must be S2MM Memory Map data width aligned.\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    }
+                  }
+                },
+                "S2MM_DA_MSB": {
+                  "address_offset": "0x4C",
+                  "size": 32,
+                  "display_name": "S2MM Destination Address Register",
+                  "description": "S2MM Destination Address Register",
+                  "is_volatile": true,
+                  "access": "read-write",
+                  "reset_value": "0x0",
+                  "fields": {
+                    "Destination_Address": {
+                      "bit_offset": 0,
+                      "bit_width": 32,
+                      "display_name": "Destination Address",
+                      "description": "Indicates the MSB 32 bits of the Destination address AXI DMA writes to transfer data from AXI4-Stream on the S2MM Channel.\nNote: If Data Realignment Engine is included, the Destination Address can be at any byte offset. If Data Realignment Engine is not included, the Dstination Address must be S2MM Memory Map data width aligned.\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    }
+                  }
+                },
+                "S2MM_LENGTH": {
+                  "address_offset": "0x58",
+                  "size": 32,
+                  "display_name": "S2MM DMA Transfer Length Register",
+                  "description": "S2MM DMA Transfer Length Register",
+                  "is_volatile": true,
+                  "access": "read-write",
+                  "reset_value": "0x0",
+                  "fields": {
+                    "Length": {
+                      "bit_offset": 0,
+                      "bit_width": 26,
+                      "display_name": "Length",
+                      "description": "Indicates the length in bytes of the S2MM buffer available to write receive data from the S2MM channel. Writing a non-zero value to this register enables S2MM channel to receive packet data.\nAt the completion of the S2MM transfer, the number of actual bytes written on the S2MM AXI4 interface is updated to the S2MM_LENGTH register.\nNote: This value must be greater than or equal to the largest expected packet to be received on S2MM AXI4-Stream. Values smaller than the received packet result in undefined behavior. \n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    }
+                  }
+                }
+              }
+            }
+          }
+        }
+      }
+    }
+  }
+}

cx9261a_demo_cmos_20240829/project_fix_dac.srcs/sources_1/bd/system_top/ip/system_top_axi_gpio_0_0/system_top_axi_gpio_0_0.xci

@@ -0,0 +1,380 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "system_top_axi_gpio_0_0",
+    "cell_name": "axi_gpio_0",
+    "component_reference": "xilinx.com:ip:axi_gpio:2.0",
+    "ip_revision": "33",
+    "gen_directory": "../../../../../../project_fix_dac.gen/sources_1/bd/system_top/ip/system_top_axi_gpio_0_0",
+    "parameters": {
+      "component_parameters": {
+        "C_TRI_DEFAULT": [ { "value": "0xFFFFFFFF", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
+        "C_GPIO_WIDTH": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_GPIO2_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_IS_DUAL": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_ALL_INPUTS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_TRI_DEFAULT_2": [ { "value": "0xFFFFFFFF", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
+        "C_DOUT_DEFAULT_2": [ { "value": "0x00000000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
+        "C_DOUT_DEFAULT": [ { "value": "0x00000000", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
+        "C_ALL_INPUTS_2": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_INTERRUPT_PRESENT": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Component_Name": [ { "value": "system_top_axi_gpio_0_0", "resolve_type": "user", "usage": "all" } ],
+        "USE_BOARD_FLOW": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "GPIO_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
+        "GPIO2_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
+        "C_ALL_OUTPUTS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_ALL_OUTPUTS_2": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ]
+      },
+      "model_parameters": {
+        "C_FAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ],
+        "C_S_AXI_ADDR_WIDTH": [ { "value": "9", "format": "long", "usage": "all" } ],
+        "C_S_AXI_DATA_WIDTH": [ { "value": "32", "format": "long", "usage": "all" } ],
+        "C_GPIO_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_GPIO2_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ALL_INPUTS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ALL_INPUTS_2": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ALL_OUTPUTS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ALL_OUTPUTS_2": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_INTERRUPT_PRESENT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DOUT_DEFAULT": [ { "value": "0x00000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
+        "C_TRI_DEFAULT": [ { "value": "0xFFFFFFFF", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
+        "C_IS_DUAL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DOUT_DEFAULT_2": [ { "value": "0x00000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
+        "C_TRI_DEFAULT_2": [ { "value": "0xFFFFFFFF", "resolve_type": "generated", "format": "bitString", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "zynq" } ],
+        "BASE_BOARD_PART": [ { "value": "xilinx.com:zc706:part0:1.4" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xc7z045" } ],
+        "NEXTGEN_VERSAL": [ { "value": "0" } ],
+        "PACKAGE": [ { "value": "ffg900" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Integrator" } ],
+        "IPREVISION": [ { "value": "33" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../../../project_fix_dac.gen/sources_1/bd/system_top/ip/system_top_axi_gpio_0_0" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "../../ipshared" } ],
+        "SWVERSION": [ { "value": "2024.1" } ],
+        "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "s_axi_aclk": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axi_aresetn": [ { "direction": "in", "driver_value": "1" } ],
+        "s_axi_awaddr": [ { "direction": "in", "size_left": "8", "size_right": "0", "driver_value": "0" } ],
+        "s_axi_awvalid": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axi_awready": [ { "direction": "out" } ],
+        "s_axi_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
+        "s_axi_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
+        "s_axi_wvalid": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axi_wready": [ { "direction": "out" } ],
+        "s_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
+        "s_axi_bvalid": [ { "direction": "out" } ],
+        "s_axi_bready": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axi_araddr": [ { "direction": "in", "size_left": "8", "size_right": "0", "driver_value": "0" } ],
+        "s_axi_arvalid": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axi_arready": [ { "direction": "out" } ],
+        "s_axi_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
+        "s_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
+        "s_axi_rvalid": [ { "direction": "out" } ],
+        "s_axi_rready": [ { "direction": "in", "driver_value": "0" } ],
+        "ip2intc_irpt": [ { "direction": "out" } ],
+        "gpio_io_i": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
+        "gpio_io_o": [ { "direction": "out", "size_left": "0", "size_right": "0" } ],
+        "gpio_io_t": [ { "direction": "out", "size_left": "0", "size_right": "0" } ]
+      },
+      "interfaces": {
+        "S_AXI": {
+          "vlnv": "xilinx.com:interface:aximm:1.0",
+          "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
+          "mode": "slave",
+          "memory_map_ref": "S_AXI",
+          "parameters": {
+            "DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "ADDR_WIDTH": [ { "value": "9", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_PROT": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "MAX_BURST_LENGTH": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_top_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "ARADDR": [ { "physical_name": "s_axi_araddr" } ],
+            "ARREADY": [ { "physical_name": "s_axi_arready" } ],
+            "ARVALID": [ { "physical_name": "s_axi_arvalid" } ],
+            "AWADDR": [ { "physical_name": "s_axi_awaddr" } ],
+            "AWREADY": [ { "physical_name": "s_axi_awready" } ],
+            "AWVALID": [ { "physical_name": "s_axi_awvalid" } ],
+            "BREADY": [ { "physical_name": "s_axi_bready" } ],
+            "BRESP": [ { "physical_name": "s_axi_bresp" } ],
+            "BVALID": [ { "physical_name": "s_axi_bvalid" } ],
+            "RDATA": [ { "physical_name": "s_axi_rdata" } ],
+            "RREADY": [ { "physical_name": "s_axi_rready" } ],
+            "RRESP": [ { "physical_name": "s_axi_rresp" } ],
+            "RVALID": [ { "physical_name": "s_axi_rvalid" } ],
+            "WDATA": [ { "physical_name": "s_axi_wdata" } ],
+            "WREADY": [ { "physical_name": "s_axi_wready" } ],
+            "WSTRB": [ { "physical_name": "s_axi_wstrb" } ],
+            "WVALID": [ { "physical_name": "s_axi_wvalid" } ]
+          }
+        },
+        "S_AXI_ACLK": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "S_AXI", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "s_axi_aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_top_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "s_axi_aclk" } ]
+          }
+        },
+        "S_AXI_ARESETN": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "s_axi_aresetn" } ]
+          }
+        },
+        "IP2INTC_IRQ": {
+          "vlnv": "xilinx.com:signal:interrupt:1.0",
+          "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "SENSITIVITY": [ { "value": "LEVEL_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "PortWidth": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "INTERRUPT": [ { "physical_name": "ip2intc_irpt" } ]
+          }
+        },
+        "GPIO": {
+          "vlnv": "xilinx.com:interface:gpio:1.0",
+          "abstraction_type": "xilinx.com:interface:gpio_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "BOARD.ASSOCIATED_PARAM": [ { "value": "GPIO_BOARD_INTERFACE", "value_src": "constant", "value_permission": "bd", "usage": "all" } ]
+          },
+          "port_maps": {
+            "TRI_I": [ { "physical_name": "gpio_io_i" } ],
+            "TRI_O": [ { "physical_name": "gpio_io_o" } ],
+            "TRI_T": [ { "physical_name": "gpio_io_t" } ]
+          }
+        }
+      },
+      "memory_maps": {
+        "S_AXI": {
+          "display_name": "S_AXI_MEM",
+          "description": "Memory Map for S_AXI",
+          "address_blocks": {
+            "Reg": {
+              "base_address": "0",
+              "range": "4096",
+              "display_name": "Reg",
+              "description": "Register Block",
+              "usage": "register",
+              "access": "read-write",
+              "registers": {
+                "GPIO_DATA": {
+                  "address_offset": "0x0",
+                  "size": 1,
+                  "display_name": "Channel_1_GPIO_DATA",
+                  "description": "Channel-1 AXI GPIO Data register",
+                  "is_volatile": true,
+                  "access": "read-write",
+                  "reset_value": "0x0",
+                  "fields": {
+                    "CH1_DATA": {
+                      "bit_offset": 0,
+                      "bit_width": 1,
+                      "display_name": "Channel_1_GPIO_DATA",
+                      "description": "AXI GPIO Data Register.\nFor each I/O bit programmed as input\n  R - Reads value on the input pin.\n  W - No effect.\nFor each I/O bit programmed as output\n  R - Reads value on GPIO_O pins\n  W - Writes value to the corresponding AXI GPIO \n      data register bit and output pin\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    }
+                  }
+                },
+                "GPIO_TRI": {
+                  "address_offset": "0x4",
+                  "size": 1,
+                  "display_name": "Channel_1_GPIO_TRI",
+                  "description": "Channel-1 AXI GPIO 3-State Control register",
+                  "is_volatile": true,
+                  "access": "read-write",
+                  "reset_value": "0x0",
+                  "fields": {
+                    "CH1_TRI": {
+                      "bit_offset": 0,
+                      "bit_width": 1,
+                      "display_name": "Channel_1_GPIO_DATA",
+                      "description": "AXI GPIO 3-State Control Register\nEach I/O pin of the AXI GPIO is individually programmable as an input or output   For each of the bits     0 - I/O pin configured as output     1 - I/O pin configured as input\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    }
+                  }
+                },
+                "GPIO2_DATA": {
+                  "address_offset": "0x8",
+                  "size": 32,
+                  "display_name": "Channel_2_GPIO_DATA",
+                  "description": "Channel-2 AXI GPIO Data register",
+                  "is_volatile": true,
+                  "access": "read-write",
+                  "reset_value": "0x0",
+                  "fields": {
+                    "CH2_DATA": {
+                      "bit_offset": 0,
+                      "bit_width": 32,
+                      "display_name": "Channel_2_GPIO_DATA",
+                      "description": "AXI GPIO Data Register.\nFor each I/O bit programmed as input\n  R - Reads value on the input pin.\n  W - No effect.\nFor each I/O bit programmed as output\n  R - Reads value on GPIO_O pins\n  W - Writes value to the corresponding AXI GPIO \n      data register bit and output pin\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    }
+                  }
+                },
+                "GPIO2_TRI": {
+                  "address_offset": "0xC",
+                  "size": 32,
+                  "display_name": "Channel_2_GPIO_TRI",
+                  "description": "Channel-2 AXI GPIO 3-State Control register",
+                  "is_volatile": true,
+                  "access": "read-write",
+                  "reset_value": "0x0",
+                  "fields": {
+                    "CH2_TRI": {
+                      "bit_offset": 0,
+                      "bit_width": 32,
+                      "display_name": "Channel_2_GPIO_DATA",
+                      "description": "AXI GPIO 3-State Control Register\nEach I/O pin of the AXI GPIO is individually programmable as an input or output   For each of the bits     0 - I/O pin configured as output     1 - I/O pin configured as input\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    }
+                  }
+                },
+                "GIER": {
+                  "address_offset": "0x11C",
+                  "size": 32,
+                  "display_name": "Global_Interrupt_Enable register",
+                  "description": "Global_Interrupt_Enable register",
+                  "is_volatile": true,
+                  "access": "read-write",
+                  "reset_value": "0x0",
+                  "fields": {
+                    "INT_EN": {
+                      "bit_offset": 31,
+                      "bit_width": 1,
+                      "display_name": "Global_Interrupt_Enable",
+                      "description": "Master enable for the device interrupt output\n  0 - Disabled\n  1 - Enabled\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    }
+                  }
+                },
+                "IP_IER": {
+                  "address_offset": "0x128",
+                  "size": 32,
+                  "display_name": "IP Interrupt Enable register",
+                  "description": "IP Interrupt Enable register",
+                  "is_volatile": true,
+                  "access": "read-write",
+                  "reset_value": "0x0",
+                  "fields": {
+                    "CH1_INT_EN": {
+                      "bit_offset": 0,
+                      "bit_width": 1,
+                      "display_name": "Channel_1_Interrupt_Enable",
+                      "description": "Enable Channel 1 Interrupt\n  0 - Disabled (masked)\n  1 - Enabled\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    },
+                    "CH2_INT_EN": {
+                      "bit_offset": 1,
+                      "bit_width": 1,
+                      "display_name": "Channel_2_Interrupt_Enable",
+                      "description": "Enable Channel 2 Interrupt\n  0 - Disabled (masked)\n  1 - Enabled\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    }
+                  }
+                },
+                "IP_ISR": {
+                  "address_offset": "0x120",
+                  "size": 32,
+                  "display_name": "IP Interrupt Status register",
+                  "description": "IP Interrupt Status register",
+                  "is_volatile": true,
+                  "access": "read-write",
+                  "reset_value": "0x0",
+                  "fields": {
+                    "CH1_INT_S": {
+                      "bit_offset": 0,
+                      "bit_width": 1,
+                      "display_name": "Channel_1_Interrupt_Status",
+                      "description": "Channel 1 Interrupt Status\n  0 - No Channel 1 input interrupt\n  1 - Channel 1 input interrupt\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    },
+                    "CH2_INT_S": {
+                      "bit_offset": 1,
+                      "bit_width": 1,
+                      "display_name": "Channel_2_Interrupt_Status",
+                      "description": "Channel 2 Interrupt Status\n  0 - No Channel 2 input interrupt\n  1 - Channel 2 input interrupt\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    }
+                  }
+                }
+              }
+            }
+          }
+        }
+      }
+    }
+  }
+}

cx9261a_demo_cmos_20240829/project_fix_dac.srcs/sources_1/bd/system_top/ip/system_top_axi_smc1_0/system_top_axi_smc1_0.xci

@@ -0,0 +1,537 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "system_top_axi_smc1_0",
+    "cell_name": "axi_smc1",
+    "component_reference": "xilinx.com:ip:smartconnect:1.0",
+    "ip_revision": "23",
+    "gen_directory": "../../../../../../project_fix_dac.gen/sources_1/bd/system_top/ip/system_top_axi_smc1_0",
+    "parameters": {
+      "component_parameters": {
+        "Component_Name": [ { "value": "system_top_axi_smc1_0", "resolve_type": "user", "usage": "all" } ],
+        "NUM_MI": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "NUM_SI": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "NUM_CLKS": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "HAS_ARESETN": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "ADVANCED_PROPERTIES": [ { "value": "0", "resolve_type": "user", "usage": "all" } ]
+      },
+      "model_parameters": {
+        "TLM_COMPONENT_NAME": [ { "value": "system_top_axi_smc1_0", "resolve_type": "generated", "usage": "simulation.tlm" } ],
+        "HAS_RESET": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "zynq" } ],
+        "BASE_BOARD_PART": [ { "value": "xilinx.com:zc706:part0:1.4" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xc7z045" } ],
+        "NEXTGEN_VERSAL": [ { "value": "0" } ],
+        "PACKAGE": [ { "value": "ffg900" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Integrator" } ],
+        "IPREVISION": [ { "value": "23" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../../../project_fix_dac.gen/sources_1/bd/system_top/ip/system_top_axi_smc1_0" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "../../ipshared" } ],
+        "SWVERSION": [ { "value": "2024.1" } ],
+        "SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "aclk": [ { "direction": "in" } ],
+        "aresetn": [ { "direction": "in", "driver_value": "1" } ],
+        "S00_AXI_awid": [ { "direction": "in", "size_left": "11", "size_right": "0", "driver_value": "0" } ],
+        "S00_AXI_awaddr": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
+        "S00_AXI_awlen": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
+        "S00_AXI_awsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "010" } ],
+        "S00_AXI_awburst": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "1" } ],
+        "S00_AXI_awlock": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
+        "S00_AXI_awcache": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "3" } ],
+        "S00_AXI_awprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
+        "S00_AXI_awqos": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
+        "S00_AXI_awvalid": [ { "direction": "in", "driver_value": "0" } ],
+        "S00_AXI_awready": [ { "direction": "out", "driver_value": "0" } ],
+        "S00_AXI_wid": [ { "direction": "in", "size_left": "11", "size_right": "0", "driver_value": "0" } ],
+        "S00_AXI_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
+        "S00_AXI_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "1" } ],
+        "S00_AXI_wlast": [ { "direction": "in", "driver_value": "0" } ],
+        "S00_AXI_wvalid": [ { "direction": "in", "driver_value": "0" } ],
+        "S00_AXI_wready": [ { "direction": "out", "driver_value": "0" } ],
+        "S00_AXI_bid": [ { "direction": "out", "size_left": "11", "size_right": "0", "driver_value": "0" } ],
+        "S00_AXI_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
+        "S00_AXI_bvalid": [ { "direction": "out", "driver_value": "0" } ],
+        "S00_AXI_bready": [ { "direction": "in", "driver_value": "0" } ],
+        "S00_AXI_arid": [ { "direction": "in", "size_left": "11", "size_right": "0", "driver_value": "0" } ],
+        "S00_AXI_araddr": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
+        "S00_AXI_arlen": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
+        "S00_AXI_arsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "010" } ],
+        "S00_AXI_arburst": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "1" } ],
+        "S00_AXI_arlock": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
+        "S00_AXI_arcache": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "3" } ],
+        "S00_AXI_arprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
+        "S00_AXI_arqos": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
+        "S00_AXI_arvalid": [ { "direction": "in", "driver_value": "0" } ],
+        "S00_AXI_arready": [ { "direction": "out", "driver_value": "0" } ],
+        "S00_AXI_rid": [ { "direction": "out", "size_left": "11", "size_right": "0", "driver_value": "0" } ],
+        "S00_AXI_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
+        "S00_AXI_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
+        "S00_AXI_rlast": [ { "direction": "out", "driver_value": "0" } ],
+        "S00_AXI_rvalid": [ { "direction": "out", "driver_value": "0" } ],
+        "S00_AXI_rready": [ { "direction": "in", "driver_value": "0" } ],
+        "S01_AXI_awaddr": [ { "direction": "in", "size_left": "39", "size_right": "0", "driver_value": "0" } ],
+        "S01_AXI_awlen": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
+        "S01_AXI_awsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "011" } ],
+        "S01_AXI_awburst": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "1" } ],
+        "S01_AXI_awlock": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
+        "S01_AXI_awcache": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "3" } ],
+        "S01_AXI_awprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
+        "S01_AXI_awqos": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
+        "S01_AXI_awvalid": [ { "direction": "in", "driver_value": "0" } ],
+        "S01_AXI_awready": [ { "direction": "out", "driver_value": "0" } ],
+        "S01_AXI_wdata": [ { "direction": "in", "size_left": "63", "size_right": "0", "driver_value": "0" } ],
+        "S01_AXI_wstrb": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "1" } ],
+        "S01_AXI_wlast": [ { "direction": "in", "driver_value": "0" } ],
+        "S01_AXI_wvalid": [ { "direction": "in", "driver_value": "0" } ],
+        "S01_AXI_wready": [ { "direction": "out", "driver_value": "0" } ],
+        "S01_AXI_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
+        "S01_AXI_bvalid": [ { "direction": "out", "driver_value": "0" } ],
+        "S01_AXI_bready": [ { "direction": "in", "driver_value": "0" } ],
+        "S02_AXI_awaddr": [ { "direction": "in", "size_left": "39", "size_right": "0", "driver_value": "0" } ],
+        "S02_AXI_awlen": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
+        "S02_AXI_awsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "011" } ],
+        "S02_AXI_awburst": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "1" } ],
+        "S02_AXI_awlock": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
+        "S02_AXI_awcache": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "3" } ],
+        "S02_AXI_awprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
+        "S02_AXI_awqos": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
+        "S02_AXI_awvalid": [ { "direction": "in", "driver_value": "0" } ],
+        "S02_AXI_awready": [ { "direction": "out", "driver_value": "0" } ],
+        "S02_AXI_wdata": [ { "direction": "in", "size_left": "63", "size_right": "0", "driver_value": "0" } ],
+        "S02_AXI_wstrb": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "1" } ],
+        "S02_AXI_wlast": [ { "direction": "in", "driver_value": "0" } ],
+        "S02_AXI_wvalid": [ { "direction": "in", "driver_value": "0" } ],
+        "S02_AXI_wready": [ { "direction": "out", "driver_value": "0" } ],
+        "S02_AXI_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
+        "S02_AXI_bvalid": [ { "direction": "out", "driver_value": "0" } ],
+        "S02_AXI_bready": [ { "direction": "in", "driver_value": "0" } ],
+        "S03_AXI_awaddr": [ { "direction": "in", "size_left": "39", "size_right": "0", "driver_value": "0" } ],
+        "S03_AXI_awlen": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
+        "S03_AXI_awsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "011" } ],
+        "S03_AXI_awburst": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "1" } ],
+        "S03_AXI_awlock": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
+        "S03_AXI_awcache": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "3" } ],
+        "S03_AXI_awprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
+        "S03_AXI_awqos": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
+        "S03_AXI_awvalid": [ { "direction": "in", "driver_value": "0" } ],
+        "S03_AXI_awready": [ { "direction": "out", "driver_value": "0" } ],
+        "S03_AXI_wdata": [ { "direction": "in", "size_left": "63", "size_right": "0", "driver_value": "0" } ],
+        "S03_AXI_wstrb": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "1" } ],
+        "S03_AXI_wlast": [ { "direction": "in", "driver_value": "0" } ],
+        "S03_AXI_wvalid": [ { "direction": "in", "driver_value": "0" } ],
+        "S03_AXI_wready": [ { "direction": "out", "driver_value": "0" } ],
+        "S03_AXI_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
+        "S03_AXI_bvalid": [ { "direction": "out", "driver_value": "0" } ],
+        "S03_AXI_bready": [ { "direction": "in", "driver_value": "0" } ],
+        "M00_AXI_awaddr": [ { "direction": "out", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
+        "M00_AXI_awlen": [ { "direction": "out", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
+        "M00_AXI_awsize": [ { "direction": "out", "size_left": "2", "size_right": "0", "driver_value": "110" } ],
+        "M00_AXI_awburst": [ { "direction": "out", "size_left": "1", "size_right": "0", "driver_value": "1" } ],
+        "M00_AXI_awlock": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
+        "M00_AXI_awcache": [ { "direction": "out", "size_left": "3", "size_right": "0", "driver_value": "3" } ],
+        "M00_AXI_awprot": [ { "direction": "out", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
+        "M00_AXI_awqos": [ { "direction": "out", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
+        "M00_AXI_awvalid": [ { "direction": "out", "driver_value": "0" } ],
+        "M00_AXI_awready": [ { "direction": "in", "driver_value": "0" } ],
+        "M00_AXI_wdata": [ { "direction": "out", "size_left": "511", "size_right": "0", "driver_value": "0" } ],
+        "M00_AXI_wstrb": [ { "direction": "out", "size_left": "63", "size_right": "0", "driver_value": "1" } ],
+        "M00_AXI_wlast": [ { "direction": "out", "driver_value": "0" } ],
+        "M00_AXI_wvalid": [ { "direction": "out", "driver_value": "0" } ],
+        "M00_AXI_wready": [ { "direction": "in", "driver_value": "0" } ],
+        "M00_AXI_bresp": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
+        "M00_AXI_bvalid": [ { "direction": "in", "driver_value": "0" } ],
+        "M00_AXI_bready": [ { "direction": "out", "driver_value": "0" } ],
+        "M00_AXI_araddr": [ { "direction": "out", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
+        "M00_AXI_arlen": [ { "direction": "out", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
+        "M00_AXI_arsize": [ { "direction": "out", "size_left": "2", "size_right": "0", "driver_value": "110" } ],
+        "M00_AXI_arburst": [ { "direction": "out", "size_left": "1", "size_right": "0", "driver_value": "1" } ],
+        "M00_AXI_arlock": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
+        "M00_AXI_arcache": [ { "direction": "out", "size_left": "3", "size_right": "0", "driver_value": "3" } ],
+        "M00_AXI_arprot": [ { "direction": "out", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
+        "M00_AXI_arqos": [ { "direction": "out", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
+        "M00_AXI_arvalid": [ { "direction": "out", "driver_value": "0" } ],
+        "M00_AXI_arready": [ { "direction": "in", "driver_value": "0" } ],
+        "M00_AXI_rdata": [ { "direction": "in", "size_left": "511", "size_right": "0", "driver_value": "0" } ],
+        "M00_AXI_rresp": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
+        "M00_AXI_rlast": [ { "direction": "in", "driver_value": "0" } ],
+        "M00_AXI_rvalid": [ { "direction": "in", "driver_value": "0" } ],
+        "M00_AXI_rready": [ { "direction": "out", "driver_value": "0" } ]
+      },
+      "interfaces": {
+        "CLK.aclk": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "FREQ_HZ": [ { "value": "200000000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "PHASE": [ { "value": "0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_top_mig_7series_0_0_ui_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
+            "ASSOCIATED_BUSIF": [ { "value": "M00_AXI:S00_AXI:S01_AXI:S02_AXI:S03_AXI", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
+            "ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ],
+            "ASSOCIATED_CLKEN": [ { "value": "m_sc_aclken", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "aclk" } ]
+          }
+        },
+        "RST.aresetn": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "aresetn" } ]
+          }
+        },
+        "S00_AXI": {
+          "vlnv": "xilinx.com:interface:aximm:1.0",
+          "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "DATA_WIDTH": [ { "value": "32", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "PROTOCOL": [ { "value": "AXI3", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "200000000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "ID_WIDTH": [ { "value": "12", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "ADDR_WIDTH": [ { "value": "32", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "WUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "RUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "BUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_BURST": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_LOCK": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_PROT": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_CACHE": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_QOS": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_WSTRB": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_BRESP": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_RRESP": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "MAX_BURST_LENGTH": [ { "value": "16", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "PHASE": [ { "value": "0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_top_mig_7series_0_0_ui_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
+            "NUM_READ_THREADS": [ { "value": "4", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "NUM_WRITE_THREADS": [ { "value": "4", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "AWID": [ { "physical_name": "S00_AXI_awid" } ],
+            "AWADDR": [ { "physical_name": "S00_AXI_awaddr" } ],
+            "AWLEN": [ { "physical_name": "S00_AXI_awlen" } ],
+            "AWSIZE": [ { "physical_name": "S00_AXI_awsize" } ],
+            "AWBURST": [ { "physical_name": "S00_AXI_awburst" } ],
+            "AWLOCK": [ { "physical_name": "S00_AXI_awlock" } ],
+            "AWCACHE": [ { "physical_name": "S00_AXI_awcache" } ],
+            "AWPROT": [ { "physical_name": "S00_AXI_awprot" } ],
+            "AWQOS": [ { "physical_name": "S00_AXI_awqos" } ],
+            "AWVALID": [ { "physical_name": "S00_AXI_awvalid" } ],
+            "AWREADY": [ { "physical_name": "S00_AXI_awready" } ],
+            "WID": [ { "physical_name": "S00_AXI_wid" } ],
+            "WDATA": [ { "physical_name": "S00_AXI_wdata" } ],
+            "WSTRB": [ { "physical_name": "S00_AXI_wstrb" } ],
+            "WLAST": [ { "physical_name": "S00_AXI_wlast" } ],
+            "WVALID": [ { "physical_name": "S00_AXI_wvalid" } ],
+            "WREADY": [ { "physical_name": "S00_AXI_wready" } ],
+            "BID": [ { "physical_name": "S00_AXI_bid" } ],
+            "BRESP": [ { "physical_name": "S00_AXI_bresp" } ],
+            "BVALID": [ { "physical_name": "S00_AXI_bvalid" } ],
+            "BREADY": [ { "physical_name": "S00_AXI_bready" } ],
+            "ARID": [ { "physical_name": "S00_AXI_arid" } ],
+            "ARADDR": [ { "physical_name": "S00_AXI_araddr" } ],
+            "ARLEN": [ { "physical_name": "S00_AXI_arlen" } ],
+            "ARSIZE": [ { "physical_name": "S00_AXI_arsize" } ],
+            "ARBURST": [ { "physical_name": "S00_AXI_arburst" } ],
+            "ARLOCK": [ { "physical_name": "S00_AXI_arlock" } ],
+            "ARCACHE": [ { "physical_name": "S00_AXI_arcache" } ],
+            "ARPROT": [ { "physical_name": "S00_AXI_arprot" } ],
+            "ARQOS": [ { "physical_name": "S00_AXI_arqos" } ],
+            "ARVALID": [ { "physical_name": "S00_AXI_arvalid" } ],
+            "ARREADY": [ { "physical_name": "S00_AXI_arready" } ],
+            "RID": [ { "physical_name": "S00_AXI_rid" } ],
+            "RDATA": [ { "physical_name": "S00_AXI_rdata" } ],
+            "RRESP": [ { "physical_name": "S00_AXI_rresp" } ],
+            "RLAST": [ { "physical_name": "S00_AXI_rlast" } ],
+            "RVALID": [ { "physical_name": "S00_AXI_rvalid" } ],
+            "RREADY": [ { "physical_name": "S00_AXI_rready" } ]
+          }
+        },
+        "S01_AXI": {
+          "vlnv": "xilinx.com:interface:aximm:1.0",
+          "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "DATA_WIDTH": [ { "value": "64", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "PROTOCOL": [ { "value": "AXI4", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "200000000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "ID_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "ADDR_WIDTH": [ { "value": "40", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "AWUSER_WIDTH": [ { "value": "0", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "WUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "RUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "BUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "WRITE_ONLY", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_BURST": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_LOCK": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_PROT": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_CACHE": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_QOS": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_WSTRB": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_BRESP": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_RRESP": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "MAX_BURST_LENGTH": [ { "value": "16", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "PHASE": [ { "value": "0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_top_mig_7series_0_0_ui_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
+            "NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "AWADDR": [ { "physical_name": "S01_AXI_awaddr" } ],
+            "AWLEN": [ { "physical_name": "S01_AXI_awlen" } ],
+            "AWSIZE": [ { "physical_name": "S01_AXI_awsize" } ],
+            "AWBURST": [ { "physical_name": "S01_AXI_awburst" } ],
+            "AWLOCK": [ { "physical_name": "S01_AXI_awlock" } ],
+            "AWCACHE": [ { "physical_name": "S01_AXI_awcache" } ],
+            "AWPROT": [ { "physical_name": "S01_AXI_awprot" } ],
+            "AWQOS": [ { "physical_name": "S01_AXI_awqos" } ],
+            "AWVALID": [ { "physical_name": "S01_AXI_awvalid" } ],
+            "AWREADY": [ { "physical_name": "S01_AXI_awready" } ],
+            "WDATA": [ { "physical_name": "S01_AXI_wdata" } ],
+            "WSTRB": [ { "physical_name": "S01_AXI_wstrb" } ],
+            "WLAST": [ { "physical_name": "S01_AXI_wlast" } ],
+            "WVALID": [ { "physical_name": "S01_AXI_wvalid" } ],
+            "WREADY": [ { "physical_name": "S01_AXI_wready" } ],
+            "BRESP": [ { "physical_name": "S01_AXI_bresp" } ],
+            "BVALID": [ { "physical_name": "S01_AXI_bvalid" } ],
+            "BREADY": [ { "physical_name": "S01_AXI_bready" } ]
+          }
+        },
+        "S02_AXI": {
+          "vlnv": "xilinx.com:interface:aximm:1.0",
+          "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "DATA_WIDTH": [ { "value": "64", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "PROTOCOL": [ { "value": "AXI4", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "200000000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "ID_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "ADDR_WIDTH": [ { "value": "40", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "AWUSER_WIDTH": [ { "value": "0", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "WUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "RUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "BUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "WRITE_ONLY", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_BURST": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_LOCK": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_PROT": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_CACHE": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_QOS": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_WSTRB": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_BRESP": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_RRESP": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "MAX_BURST_LENGTH": [ { "value": "16", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "PHASE": [ { "value": "0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_top_mig_7series_0_0_ui_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
+            "NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "AWADDR": [ { "physical_name": "S02_AXI_awaddr" } ],
+            "AWLEN": [ { "physical_name": "S02_AXI_awlen" } ],
+            "AWSIZE": [ { "physical_name": "S02_AXI_awsize" } ],
+            "AWBURST": [ { "physical_name": "S02_AXI_awburst" } ],
+            "AWLOCK": [ { "physical_name": "S02_AXI_awlock" } ],
+            "AWCACHE": [ { "physical_name": "S02_AXI_awcache" } ],
+            "AWPROT": [ { "physical_name": "S02_AXI_awprot" } ],
+            "AWQOS": [ { "physical_name": "S02_AXI_awqos" } ],
+            "AWVALID": [ { "physical_name": "S02_AXI_awvalid" } ],
+            "AWREADY": [ { "physical_name": "S02_AXI_awready" } ],
+            "WDATA": [ { "physical_name": "S02_AXI_wdata" } ],
+            "WSTRB": [ { "physical_name": "S02_AXI_wstrb" } ],
+            "WLAST": [ { "physical_name": "S02_AXI_wlast" } ],
+            "WVALID": [ { "physical_name": "S02_AXI_wvalid" } ],
+            "WREADY": [ { "physical_name": "S02_AXI_wready" } ],
+            "BRESP": [ { "physical_name": "S02_AXI_bresp" } ],
+            "BVALID": [ { "physical_name": "S02_AXI_bvalid" } ],
+            "BREADY": [ { "physical_name": "S02_AXI_bready" } ]
+          }
+        },
+        "S03_AXI": {
+          "vlnv": "xilinx.com:interface:aximm:1.0",
+          "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "DATA_WIDTH": [ { "value": "64", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "PROTOCOL": [ { "value": "AXI4", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "200000000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "ID_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "ADDR_WIDTH": [ { "value": "40", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "AWUSER_WIDTH": [ { "value": "0", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "WUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "RUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "BUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "WRITE_ONLY", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_BURST": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_LOCK": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_PROT": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_CACHE": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_QOS": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_WSTRB": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_BRESP": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_RRESP": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "MAX_BURST_LENGTH": [ { "value": "16", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "PHASE": [ { "value": "0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_top_mig_7series_0_0_ui_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
+            "NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "AWADDR": [ { "physical_name": "S03_AXI_awaddr" } ],
+            "AWLEN": [ { "physical_name": "S03_AXI_awlen" } ],
+            "AWSIZE": [ { "physical_name": "S03_AXI_awsize" } ],
+            "AWBURST": [ { "physical_name": "S03_AXI_awburst" } ],
+            "AWLOCK": [ { "physical_name": "S03_AXI_awlock" } ],
+            "AWCACHE": [ { "physical_name": "S03_AXI_awcache" } ],
+            "AWPROT": [ { "physical_name": "S03_AXI_awprot" } ],
+            "AWQOS": [ { "physical_name": "S03_AXI_awqos" } ],
+            "AWVALID": [ { "physical_name": "S03_AXI_awvalid" } ],
+            "AWREADY": [ { "physical_name": "S03_AXI_awready" } ],
+            "WDATA": [ { "physical_name": "S03_AXI_wdata" } ],
+            "WSTRB": [ { "physical_name": "S03_AXI_wstrb" } ],
+            "WLAST": [ { "physical_name": "S03_AXI_wlast" } ],
+            "WVALID": [ { "physical_name": "S03_AXI_wvalid" } ],
+            "WREADY": [ { "physical_name": "S03_AXI_wready" } ],
+            "BRESP": [ { "physical_name": "S03_AXI_bresp" } ],
+            "BVALID": [ { "physical_name": "S03_AXI_bvalid" } ],
+            "BREADY": [ { "physical_name": "S03_AXI_bready" } ]
+          }
+        },
+        "M00_AXI": {
+          "vlnv": "xilinx.com:interface:aximm:1.0",
+          "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "DATA_WIDTH": [ { "value": "512", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "PROTOCOL": [ { "value": "AXI4", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "200000000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "ID_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "ADDR_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "AWUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "ARUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "WUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "RUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "BUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_BURST": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_LOCK": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_PROT": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_CACHE": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_QOS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_WSTRB": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_BRESP": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_RRESP": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "MAX_BURST_LENGTH": [ { "value": "2", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "PHASE": [ { "value": "0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_top_mig_7series_0_0_ui_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
+            "NUM_READ_THREADS": [ { "value": "1", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "AWADDR": [ { "physical_name": "M00_AXI_awaddr" } ],
+            "AWLEN": [ { "physical_name": "M00_AXI_awlen" } ],
+            "AWSIZE": [ { "physical_name": "M00_AXI_awsize" } ],
+            "AWBURST": [ { "physical_name": "M00_AXI_awburst" } ],
+            "AWLOCK": [ { "physical_name": "M00_AXI_awlock" } ],
+            "AWCACHE": [ { "physical_name": "M00_AXI_awcache" } ],
+            "AWPROT": [ { "physical_name": "M00_AXI_awprot" } ],
+            "AWQOS": [ { "physical_name": "M00_AXI_awqos" } ],
+            "AWVALID": [ { "physical_name": "M00_AXI_awvalid" } ],
+            "AWREADY": [ { "physical_name": "M00_AXI_awready" } ],
+            "WDATA": [ { "physical_name": "M00_AXI_wdata" } ],
+            "WSTRB": [ { "physical_name": "M00_AXI_wstrb" } ],
+            "WLAST": [ { "physical_name": "M00_AXI_wlast" } ],
+            "WVALID": [ { "physical_name": "M00_AXI_wvalid" } ],
+            "WREADY": [ { "physical_name": "M00_AXI_wready" } ],
+            "BRESP": [ { "physical_name": "M00_AXI_bresp" } ],
+            "BVALID": [ { "physical_name": "M00_AXI_bvalid" } ],
+            "BREADY": [ { "physical_name": "M00_AXI_bready" } ],
+            "ARADDR": [ { "physical_name": "M00_AXI_araddr" } ],
+            "ARLEN": [ { "physical_name": "M00_AXI_arlen" } ],
+            "ARSIZE": [ { "physical_name": "M00_AXI_arsize" } ],
+            "ARBURST": [ { "physical_name": "M00_AXI_arburst" } ],
+            "ARLOCK": [ { "physical_name": "M00_AXI_arlock" } ],
+            "ARCACHE": [ { "physical_name": "M00_AXI_arcache" } ],
+            "ARPROT": [ { "physical_name": "M00_AXI_arprot" } ],
+            "ARQOS": [ { "physical_name": "M00_AXI_arqos" } ],
+            "ARVALID": [ { "physical_name": "M00_AXI_arvalid" } ],
+            "ARREADY": [ { "physical_name": "M00_AXI_arready" } ],
+            "RDATA": [ { "physical_name": "M00_AXI_rdata" } ],
+            "RRESP": [ { "physical_name": "M00_AXI_rresp" } ],
+            "RLAST": [ { "physical_name": "M00_AXI_rlast" } ],
+            "RVALID": [ { "physical_name": "M00_AXI_rvalid" } ],
+            "RREADY": [ { "physical_name": "M00_AXI_rready" } ]
+          }
+        }
+      }
+    }
+  }
+}

cx9261a_demo_cmos_20240829/project_fix_dac.srcs/sources_1/bd/system_top/ip/system_top_blk_mem_gen_0_0/system_top_blk_mem_gen_0_0.xci

@@ -0,0 +1,295 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "system_top_blk_mem_gen_0_0",
+    "cell_name": "blk_mem_gen_0",
+    "component_reference": "xilinx.com:ip:blk_mem_gen:8.4",
+    "ip_revision": "8",
+    "gen_directory": "../../../../../../project_fix_dac.gen/sources_1/bd/system_top/ip/system_top_blk_mem_gen_0_0",
+    "parameters": {
+      "component_parameters": {
+        "Component_Name": [ { "value": "system_top_blk_mem_gen_0_0", "resolve_type": "user", "usage": "all" } ],
+        "Interface_Type": [ { "value": "Native", "resolve_type": "user", "usage": "all" } ],
+        "AXI_Type": [ { "value": "AXI4_Full", "resolve_type": "user", "usage": "all" } ],
+        "AXI_Slave_Type": [ { "value": "Memory_Slave", "resolve_type": "user", "usage": "all" } ],
+        "Use_AXI_ID": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "AXI_ID_Width": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Memory_Type": [ { "value": "True_Dual_Port_RAM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "PRIM_type_to_Implement": [ { "value": "BRAM", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Enable_32bit_Address": [ { "value": "true", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "ecctype": [ { "value": "No_ECC", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "ECC": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "EN_SLEEP_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "EN_DEEPSLEEP_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "EN_SHUTDOWN_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "EN_ECC_PIPE": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "RD_ADDR_CHNG_A": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "RD_ADDR_CHNG_B": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Use_Error_Injection_Pins": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Error_Injection_Type": [ { "value": "Single_Bit_Error_Injection", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Use_Byte_Write_Enable": [ { "value": "true", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Byte_Size": [ { "value": "8", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Algorithm": [ { "value": "Minimum_Area", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Primitive": [ { "value": "8kx2", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Assume_Synchronous_Clk": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Write_Width_A": [ { "value": "32", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Write_Depth_A": [ { "value": "8192", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Read_Width_A": [ { "value": "32", "value_src": "propagated", "resolve_type": "user", "usage": "all" } ],
+        "Operating_Mode_A": [ { "value": "WRITE_FIRST", "resolve_type": "user", "usage": "all" } ],
+        "Enable_A": [ { "value": "Use_ENA_Pin", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Write_Width_B": [ { "value": "32", "value_src": "propagated", "resolve_type": "user", "usage": "all" } ],
+        "Read_Width_B": [ { "value": "32", "value_src": "propagated", "resolve_type": "user", "usage": "all" } ],
+        "Operating_Mode_B": [ { "value": "WRITE_FIRST", "resolve_type": "user", "usage": "all" } ],
+        "Enable_B": [ { "value": "Use_ENB_Pin", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Register_PortA_Output_of_Memory_Primitives": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Register_PortA_Output_of_Memory_Core": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Use_REGCEA_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Register_PortB_Output_of_Memory_Primitives": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Register_PortB_Output_of_Memory_Core": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Use_REGCEB_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "register_porta_input_of_softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "register_portb_output_of_softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Pipeline_Stages": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Load_Init_File": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Coe_File": [ { "value": "no_coe_file_loaded", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Fill_Remaining_Memory_Locations": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Remaining_Memory_Locations": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Use_RSTA_Pin": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Reset_Memory_Latch_A": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Reset_Priority_A": [ { "value": "CE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Output_Reset_Value_A": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
+        "Use_RSTB_Pin": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Reset_Memory_Latch_B": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Reset_Priority_B": [ { "value": "CE", "resolve_type": "user", "usage": "all" } ],
+        "Output_Reset_Value_B": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
+        "Reset_Type": [ { "value": "SYNC", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Additional_Inputs_for_Power_Estimation": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Port_A_Clock": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Port_A_Write_Rate": [ { "value": "50", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Port_B_Clock": [ { "value": "100", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Port_B_Write_Rate": [ { "value": "50", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Port_A_Enable_Rate": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Port_B_Enable_Rate": [ { "value": "100", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Collision_Warnings": [ { "value": "ALL", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Disable_Collision_Warnings": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Disable_Out_of_Range_Warnings": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "use_bram_block": [ { "value": "BRAM_Controller", "resolve_type": "user", "usage": "all" } ],
+        "MEM_FILE": [ { "value": "NONE", "value_src": "ip_propagated", "resolve_type": "user", "usage": "all" } ],
+        "CTRL_ECC_ALGO": [ { "value": "NONE", "value_src": "propagated", "resolve_type": "user", "usage": "all" } ],
+        "EN_SAFETY_CKT": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "READ_LATENCY_A": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "READ_LATENCY_B": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ]
+      },
+      "model_parameters": {
+        "C_FAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ],
+        "C_XDEVICEFAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ],
+        "C_ELABORATION_DIR": [ { "value": "./", "resolve_type": "generated", "usage": "all" } ],
+        "C_INTERFACE_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_SLAVE_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_BRAM_BLOCK": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ENABLE_32BIT_ADDRESS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CTRL_ECC_ALGO": [ { "value": "NONE", "resolve_type": "generated", "usage": "all" } ],
+        "C_HAS_AXI_ID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_ID_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MEM_TYPE": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_BYTE_SIZE": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ALGORITHM": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PRIM_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_LOAD_INIT_FILE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_INIT_FILE_NAME": [ { "value": "no_coe_file_loaded", "resolve_type": "generated", "usage": "all" } ],
+        "C_INIT_FILE": [ { "value": "NONE", "resolve_type": "generated", "usage": "all" } ],
+        "C_USE_DEFAULT_DATA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DEFAULT_DATA": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
+        "C_HAS_RSTA": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_RST_PRIORITY_A": [ { "value": "CE", "resolve_type": "generated", "usage": "all" } ],
+        "C_RSTRAM_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_INITA_VAL": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
+        "C_HAS_ENA": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_REGCEA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_BYTE_WEA": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WEA_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WRITE_MODE_A": [ { "value": "WRITE_FIRST", "resolve_type": "generated", "usage": "all" } ],
+        "C_WRITE_WIDTH_A": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_READ_WIDTH_A": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WRITE_DEPTH_A": [ { "value": "8192", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_READ_DEPTH_A": [ { "value": "8192", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ADDRA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_RSTB": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_RST_PRIORITY_B": [ { "value": "CE", "resolve_type": "generated", "usage": "all" } ],
+        "C_RSTRAM_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_INITB_VAL": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
+        "C_HAS_ENB": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_REGCEB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_BYTE_WEB": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WEB_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WRITE_MODE_B": [ { "value": "WRITE_FIRST", "resolve_type": "generated", "usage": "all" } ],
+        "C_WRITE_WIDTH_B": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_READ_WIDTH_B": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WRITE_DEPTH_B": [ { "value": "8192", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_READ_DEPTH_B": [ { "value": "8192", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ADDRB_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_MEM_OUTPUT_REGS_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_MEM_OUTPUT_REGS_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_MUX_OUTPUT_REGS_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_MUX_OUTPUT_REGS_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MUX_PIPELINE_STAGES": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_SOFTECC_INPUT_REGS_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_SOFTECC_OUTPUT_REGS_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_SOFTECC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_ECC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_EN_ECC_PIPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_READ_LATENCY_A": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_READ_LATENCY_B": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_INJECTERR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_SIM_COLLISION_CHECK": [ { "value": "ALL", "resolve_type": "generated", "usage": "all" } ],
+        "C_COMMON_CLK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DISABLE_WARN_BHV_COLL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_EN_SLEEP_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_URAM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_EN_RDADDRA_CHG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_EN_RDADDRB_CHG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_EN_DEEPSLEEP_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_EN_SHUTDOWN_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_EN_SAFETY_CKT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DISABLE_WARN_BHV_RANGE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_COUNT_36K_BRAM": [ { "value": "8", "resolve_type": "generated", "usage": "all" } ],
+        "C_COUNT_18K_BRAM": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
+        "C_EST_POWER_SUMMARY": [ { "value": "Estimated Power for IP     :     20.388 mW", "resolve_type": "generated", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "zynq" } ],
+        "BASE_BOARD_PART": [ { "value": "xilinx.com:zc706:part0:1.4" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xc7z045" } ],
+        "NEXTGEN_VERSAL": [ { "value": "0" } ],
+        "PACKAGE": [ { "value": "ffg900" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Integrator" } ],
+        "IPREVISION": [ { "value": "8" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../../../project_fix_dac.gen/sources_1/bd/system_top/ip/system_top_blk_mem_gen_0_0" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "../../ipshared" } ],
+        "SWVERSION": [ { "value": "2024.1" } ],
+        "SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "clka": [ { "direction": "in", "driver_value": "0" } ],
+        "rsta": [ { "direction": "in", "driver_value": "0" } ],
+        "ena": [ { "direction": "in", "driver_value": "0" } ],
+        "wea": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
+        "addra": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
+        "dina": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
+        "douta": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
+        "clkb": [ { "direction": "in", "driver_value": "0" } ],
+        "rstb": [ { "direction": "in", "driver_value": "0" } ],
+        "enb": [ { "direction": "in", "driver_value": "0" } ],
+        "web": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
+        "addrb": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
+        "dinb": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
+        "doutb": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
+        "rsta_busy": [ { "direction": "out" } ],
+        "rstb_busy": [ { "direction": "out" } ]
+      },
+      "interfaces": {
+        "CLK.ACLK": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "AXI_SLAVE_S_AXI:AXILite_SLAVE_S_AXI", "value_src": "constant", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "s_aresetn", "value_src": "constant", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "RST.ARESETN": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "BRAM_PORTA": {
+          "vlnv": "xilinx.com:interface:bram:1.0",
+          "abstraction_type": "xilinx.com:interface:bram_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "MEM_ADDRESS_MODE": [ { "value": "BYTE_ADDRESS", "value_permission": "bd", "resolve_type": "user", "usage": "all" } ],
+            "MEM_SIZE": [ { "value": "32768", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "MEM_WIDTH": [ { "value": "32", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "MEM_ECC": [ { "value": "NONE", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "MASTER_TYPE": [ { "value": "BRAM_CTRL", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "READ_LATENCY": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "ADDR": [ { "physical_name": "addra" } ],
+            "CLK": [ { "physical_name": "clka" } ],
+            "DIN": [ { "physical_name": "dina" } ],
+            "DOUT": [ { "physical_name": "douta" } ],
+            "EN": [ { "physical_name": "ena" } ],
+            "RST": [ { "physical_name": "rsta" } ],
+            "WE": [ { "physical_name": "wea" } ]
+          }
+        },
+        "BRAM_PORTB": {
+          "vlnv": "xilinx.com:interface:bram:1.0",
+          "abstraction_type": "xilinx.com:interface:bram_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "MEM_ADDRESS_MODE": [ { "value": "BYTE_ADDRESS", "value_permission": "bd", "resolve_type": "user", "usage": "all" } ],
+            "MEM_SIZE": [ { "value": "8192", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "MEM_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "MEM_ECC": [ { "value": "NONE", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "MASTER_TYPE": [ { "value": "BRAM_CTRL", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "READ_LATENCY": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "ADDR": [ { "physical_name": "addrb" } ],
+            "CLK": [ { "physical_name": "clkb" } ],
+            "DIN": [ { "physical_name": "dinb" } ],
+            "DOUT": [ { "physical_name": "doutb" } ],
+            "EN": [ { "physical_name": "enb" } ],
+            "RST": [ { "physical_name": "rstb" } ],
+            "WE": [ { "physical_name": "web" } ]
+          }
+        }
+      },
+      "memory_maps": {
+        "S_1": {
+          "address_blocks": {
+            "Mem0": {
+              "base_address": "0",
+              "range": "4096",
+              "usage": "memory",
+              "access": "read-write",
+              "parameters": {
+                "OFFSET_BASE_PARAM": [ { "value": "C_BASEADDR" } ],
+                "OFFSET_HIGH_PARAM": [ { "value": "C_HIGHADDR" } ]
+              }
+            }
+          }
+        }
+      }
+    }
+  }
+}

cx9261a_demo_cmos_20240829/project_fix_dac.srcs/sources_1/bd/system_top/ip/system_top_blk_mem_gen_1_0/system_top_blk_mem_gen_1_0.xci

@@ -0,0 +1,295 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "system_top_blk_mem_gen_1_0",
+    "cell_name": "blk_mem_gen_1",
+    "component_reference": "xilinx.com:ip:blk_mem_gen:8.4",
+    "ip_revision": "8",
+    "gen_directory": "../../../../../../project_fix_dac.gen/sources_1/bd/system_top/ip/system_top_blk_mem_gen_1_0",
+    "parameters": {
+      "component_parameters": {
+        "Component_Name": [ { "value": "system_top_blk_mem_gen_1_0", "resolve_type": "user", "usage": "all" } ],
+        "Interface_Type": [ { "value": "Native", "resolve_type": "user", "usage": "all" } ],
+        "AXI_Type": [ { "value": "AXI4_Full", "resolve_type": "user", "usage": "all" } ],
+        "AXI_Slave_Type": [ { "value": "Memory_Slave", "resolve_type": "user", "usage": "all" } ],
+        "Use_AXI_ID": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "AXI_ID_Width": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Memory_Type": [ { "value": "True_Dual_Port_RAM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "PRIM_type_to_Implement": [ { "value": "BRAM", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Enable_32bit_Address": [ { "value": "true", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "ecctype": [ { "value": "No_ECC", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "ECC": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "EN_SLEEP_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "EN_DEEPSLEEP_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "EN_SHUTDOWN_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "EN_ECC_PIPE": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "RD_ADDR_CHNG_A": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "RD_ADDR_CHNG_B": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Use_Error_Injection_Pins": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Error_Injection_Type": [ { "value": "Single_Bit_Error_Injection", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Use_Byte_Write_Enable": [ { "value": "true", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Byte_Size": [ { "value": "8", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Algorithm": [ { "value": "Minimum_Area", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Primitive": [ { "value": "8kx2", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Assume_Synchronous_Clk": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Write_Width_A": [ { "value": "32", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Write_Depth_A": [ { "value": "8192", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Read_Width_A": [ { "value": "32", "value_src": "propagated", "resolve_type": "user", "usage": "all" } ],
+        "Operating_Mode_A": [ { "value": "WRITE_FIRST", "resolve_type": "user", "usage": "all" } ],
+        "Enable_A": [ { "value": "Use_ENA_Pin", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Write_Width_B": [ { "value": "32", "value_src": "propagated", "resolve_type": "user", "usage": "all" } ],
+        "Read_Width_B": [ { "value": "32", "value_src": "propagated", "resolve_type": "user", "usage": "all" } ],
+        "Operating_Mode_B": [ { "value": "WRITE_FIRST", "resolve_type": "user", "usage": "all" } ],
+        "Enable_B": [ { "value": "Use_ENB_Pin", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Register_PortA_Output_of_Memory_Primitives": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Register_PortA_Output_of_Memory_Core": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Use_REGCEA_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Register_PortB_Output_of_Memory_Primitives": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Register_PortB_Output_of_Memory_Core": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Use_REGCEB_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "register_porta_input_of_softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "register_portb_output_of_softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Pipeline_Stages": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Load_Init_File": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Coe_File": [ { "value": "no_coe_file_loaded", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Fill_Remaining_Memory_Locations": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Remaining_Memory_Locations": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Use_RSTA_Pin": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Reset_Memory_Latch_A": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Reset_Priority_A": [ { "value": "CE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Output_Reset_Value_A": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
+        "Use_RSTB_Pin": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Reset_Memory_Latch_B": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Reset_Priority_B": [ { "value": "CE", "resolve_type": "user", "usage": "all" } ],
+        "Output_Reset_Value_B": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
+        "Reset_Type": [ { "value": "SYNC", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Additional_Inputs_for_Power_Estimation": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Port_A_Clock": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Port_A_Write_Rate": [ { "value": "50", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Port_B_Clock": [ { "value": "100", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Port_B_Write_Rate": [ { "value": "50", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Port_A_Enable_Rate": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Port_B_Enable_Rate": [ { "value": "100", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Collision_Warnings": [ { "value": "ALL", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Disable_Collision_Warnings": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Disable_Out_of_Range_Warnings": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "use_bram_block": [ { "value": "BRAM_Controller", "resolve_type": "user", "usage": "all" } ],
+        "MEM_FILE": [ { "value": "NONE", "value_src": "ip_propagated", "resolve_type": "user", "usage": "all" } ],
+        "CTRL_ECC_ALGO": [ { "value": "NONE", "value_src": "propagated", "resolve_type": "user", "usage": "all" } ],
+        "EN_SAFETY_CKT": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "READ_LATENCY_A": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "READ_LATENCY_B": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ]
+      },
+      "model_parameters": {
+        "C_FAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ],
+        "C_XDEVICEFAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ],
+        "C_ELABORATION_DIR": [ { "value": "./", "resolve_type": "generated", "usage": "all" } ],
+        "C_INTERFACE_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_SLAVE_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_BRAM_BLOCK": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ENABLE_32BIT_ADDRESS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CTRL_ECC_ALGO": [ { "value": "NONE", "resolve_type": "generated", "usage": "all" } ],
+        "C_HAS_AXI_ID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_ID_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MEM_TYPE": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_BYTE_SIZE": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ALGORITHM": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PRIM_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_LOAD_INIT_FILE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_INIT_FILE_NAME": [ { "value": "no_coe_file_loaded", "resolve_type": "generated", "usage": "all" } ],
+        "C_INIT_FILE": [ { "value": "NONE", "resolve_type": "generated", "usage": "all" } ],
+        "C_USE_DEFAULT_DATA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DEFAULT_DATA": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
+        "C_HAS_RSTA": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_RST_PRIORITY_A": [ { "value": "CE", "resolve_type": "generated", "usage": "all" } ],
+        "C_RSTRAM_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_INITA_VAL": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
+        "C_HAS_ENA": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_REGCEA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_BYTE_WEA": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WEA_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WRITE_MODE_A": [ { "value": "WRITE_FIRST", "resolve_type": "generated", "usage": "all" } ],
+        "C_WRITE_WIDTH_A": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_READ_WIDTH_A": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WRITE_DEPTH_A": [ { "value": "8192", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_READ_DEPTH_A": [ { "value": "8192", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ADDRA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_RSTB": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_RST_PRIORITY_B": [ { "value": "CE", "resolve_type": "generated", "usage": "all" } ],
+        "C_RSTRAM_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_INITB_VAL": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
+        "C_HAS_ENB": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_REGCEB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_BYTE_WEB": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WEB_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WRITE_MODE_B": [ { "value": "WRITE_FIRST", "resolve_type": "generated", "usage": "all" } ],
+        "C_WRITE_WIDTH_B": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_READ_WIDTH_B": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WRITE_DEPTH_B": [ { "value": "8192", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_READ_DEPTH_B": [ { "value": "8192", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ADDRB_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_MEM_OUTPUT_REGS_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_MEM_OUTPUT_REGS_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_MUX_OUTPUT_REGS_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_MUX_OUTPUT_REGS_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MUX_PIPELINE_STAGES": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_SOFTECC_INPUT_REGS_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_SOFTECC_OUTPUT_REGS_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_SOFTECC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_ECC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_EN_ECC_PIPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_READ_LATENCY_A": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_READ_LATENCY_B": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_INJECTERR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_SIM_COLLISION_CHECK": [ { "value": "ALL", "resolve_type": "generated", "usage": "all" } ],
+        "C_COMMON_CLK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DISABLE_WARN_BHV_COLL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_EN_SLEEP_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_URAM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_EN_RDADDRA_CHG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_EN_RDADDRB_CHG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_EN_DEEPSLEEP_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_EN_SHUTDOWN_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_EN_SAFETY_CKT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DISABLE_WARN_BHV_RANGE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_COUNT_36K_BRAM": [ { "value": "8", "resolve_type": "generated", "usage": "all" } ],
+        "C_COUNT_18K_BRAM": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
+        "C_EST_POWER_SUMMARY": [ { "value": "Estimated Power for IP     :     20.388 mW", "resolve_type": "generated", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "zynq" } ],
+        "BASE_BOARD_PART": [ { "value": "xilinx.com:zc706:part0:1.4" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xc7z045" } ],
+        "NEXTGEN_VERSAL": [ { "value": "0" } ],
+        "PACKAGE": [ { "value": "ffg900" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Integrator" } ],
+        "IPREVISION": [ { "value": "8" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../../../project_fix_dac.gen/sources_1/bd/system_top/ip/system_top_blk_mem_gen_1_0" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "../../ipshared" } ],
+        "SWVERSION": [ { "value": "2024.1" } ],
+        "SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "clka": [ { "direction": "in", "driver_value": "0" } ],
+        "rsta": [ { "direction": "in", "driver_value": "0" } ],
+        "ena": [ { "direction": "in", "driver_value": "0" } ],
+        "wea": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
+        "addra": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
+        "dina": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
+        "douta": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
+        "clkb": [ { "direction": "in", "driver_value": "0" } ],
+        "rstb": [ { "direction": "in", "driver_value": "0" } ],
+        "enb": [ { "direction": "in", "driver_value": "0" } ],
+        "web": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
+        "addrb": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
+        "dinb": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
+        "doutb": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
+        "rsta_busy": [ { "direction": "out" } ],
+        "rstb_busy": [ { "direction": "out" } ]
+      },
+      "interfaces": {
+        "CLK.ACLK": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "AXI_SLAVE_S_AXI:AXILite_SLAVE_S_AXI", "value_src": "constant", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "s_aresetn", "value_src": "constant", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "RST.ARESETN": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "BRAM_PORTA": {
+          "vlnv": "xilinx.com:interface:bram:1.0",
+          "abstraction_type": "xilinx.com:interface:bram_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "MEM_ADDRESS_MODE": [ { "value": "BYTE_ADDRESS", "value_permission": "bd", "resolve_type": "user", "usage": "all" } ],
+            "MEM_SIZE": [ { "value": "32768", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "MEM_WIDTH": [ { "value": "32", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "MEM_ECC": [ { "value": "NONE", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "MASTER_TYPE": [ { "value": "BRAM_CTRL", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "READ_LATENCY": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "ADDR": [ { "physical_name": "addra" } ],
+            "CLK": [ { "physical_name": "clka" } ],
+            "DIN": [ { "physical_name": "dina" } ],
+            "DOUT": [ { "physical_name": "douta" } ],
+            "EN": [ { "physical_name": "ena" } ],
+            "RST": [ { "physical_name": "rsta" } ],
+            "WE": [ { "physical_name": "wea" } ]
+          }
+        },
+        "BRAM_PORTB": {
+          "vlnv": "xilinx.com:interface:bram:1.0",
+          "abstraction_type": "xilinx.com:interface:bram_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "MEM_ADDRESS_MODE": [ { "value": "BYTE_ADDRESS", "value_permission": "bd", "resolve_type": "user", "usage": "all" } ],
+            "MEM_SIZE": [ { "value": "8192", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "MEM_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "MEM_ECC": [ { "value": "NONE", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "MASTER_TYPE": [ { "value": "BRAM_CTRL", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "READ_LATENCY": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "ADDR": [ { "physical_name": "addrb" } ],
+            "CLK": [ { "physical_name": "clkb" } ],
+            "DIN": [ { "physical_name": "dinb" } ],
+            "DOUT": [ { "physical_name": "doutb" } ],
+            "EN": [ { "physical_name": "enb" } ],
+            "RST": [ { "physical_name": "rstb" } ],
+            "WE": [ { "physical_name": "web" } ]
+          }
+        }
+      },
+      "memory_maps": {
+        "S_1": {
+          "address_blocks": {
+            "Mem0": {
+              "base_address": "0",
+              "range": "4096",
+              "usage": "memory",
+              "access": "read-write",
+              "parameters": {
+                "OFFSET_BASE_PARAM": [ { "value": "C_BASEADDR" } ],
+                "OFFSET_HIGH_PARAM": [ { "value": "C_HIGHADDR" } ]
+              }
+            }
+          }
+        }
+      }
+    }
+  }
+}

cx9261a_demo_cmos_20240829/project_fix_dac.srcs/sources_1/bd/system_top/ip/system_top_c_counter_binary_1_0/system_top_c_counter_binary_1_0.xci

@@ -0,0 +1,192 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "system_top_c_counter_binary_1_0",
+    "cell_name": "c_counter_binary_1",
+    "component_reference": "xilinx.com:ip:c_counter_binary:12.0",
+    "ip_revision": "19",
+    "gen_directory": "../../../../../../project_fix_dac.gen/sources_1/bd/system_top/ip/system_top_c_counter_binary_1_0",
+    "parameters": {
+      "component_parameters": {
+        "Component_Name": [ { "value": "system_top_c_counter_binary_1_0", "resolve_type": "user", "usage": "all" } ],
+        "Implementation": [ { "value": "Fabric", "resolve_type": "user", "usage": "all" } ],
+        "Output_Width": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Increment_Value": [ { "value": "4", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Restrict_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Final_Count_Value": [ { "value": "1", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Count_Mode": [ { "value": "UP", "resolve_type": "user", "usage": "all" } ],
+        "Sync_Threshold_Output": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Threshold_Value": [ { "value": "1", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "CE": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "SCLR": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "SSET": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "SINIT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "SINIT_Value": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "SyncCtrlPriority": [ { "value": "Reset_Overrides_Set", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Sync_CE_Priority": [ { "value": "Sync_Overrides_CE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "AINIT_Value": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
+        "Load": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Latency_Configuration": [ { "value": "Manual", "resolve_type": "user", "usage": "all" } ],
+        "Latency": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Fb_Latency_Configuration": [ { "value": "Manual", "resolve_type": "user", "usage": "all" } ],
+        "Fb_Latency": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Load_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ]
+      },
+      "model_parameters": {
+        "C_IMPLEMENTATION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_VERBOSITY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_XDEVICEFAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ],
+        "C_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_CE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_SCLR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_RESTRICT_COUNT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_COUNT_TO": [ { "value": "1", "resolve_type": "generated", "usage": "all" } ],
+        "C_COUNT_BY": [ { "value": "100", "resolve_type": "generated", "usage": "all" } ],
+        "C_COUNT_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_THRESH0_VALUE": [ { "value": "1", "resolve_type": "generated", "usage": "all" } ],
+        "C_CE_OVERRIDES_SYNC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_THRESH0": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_LOAD": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_LOAD_LOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_FB_LATENCY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AINIT_VAL": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
+        "C_SINIT_VAL": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
+        "C_SCLR_OVERRIDES_SSET": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_SSET": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_SINIT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "zynq" } ],
+        "BASE_BOARD_PART": [ { "value": "xilinx.com:zc706:part0:1.4" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xc7z045" } ],
+        "NEXTGEN_VERSAL": [ { "value": "0" } ],
+        "PACKAGE": [ { "value": "ffg900" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Integrator" } ],
+        "IPREVISION": [ { "value": "19" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../../../project_fix_dac.gen/sources_1/bd/system_top/ip/system_top_c_counter_binary_1_0" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "../../ipshared" } ],
+        "SWVERSION": [ { "value": "2024.1" } ],
+        "SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "CLK": [ { "direction": "in", "driver_value": "0x0" } ],
+        "CE": [ { "direction": "in", "driver_value": "0x1" } ],
+        "Q": [ { "direction": "out", "size_left": "31", "size_right": "0" } ]
+      },
+      "interfaces": {
+        "sset_intf": {
+          "vlnv": "xilinx.com:signal:data:1.0",
+          "abstraction_type": "xilinx.com:signal:data_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "clk_intf": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "q_intf:thresh0_intf:l_intf:load_intf:up_intf:sinit_intf:sset_intf", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "SCLR", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "ASSOCIATED_CLKEN": [ { "value": "CE", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "100000000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_top_data_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "CLK" } ]
+          }
+        },
+        "sclr_intf": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "ce_intf": {
+          "vlnv": "xilinx.com:signal:clockenable:1.0",
+          "abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ]
+          },
+          "port_maps": {
+            "CE": [ { "physical_name": "CE" } ]
+          }
+        },
+        "sinit_intf": {
+          "vlnv": "xilinx.com:signal:data:1.0",
+          "abstraction_type": "xilinx.com:signal:data_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "up_intf": {
+          "vlnv": "xilinx.com:signal:data:1.0",
+          "abstraction_type": "xilinx.com:signal:data_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "load_intf": {
+          "vlnv": "xilinx.com:signal:data:1.0",
+          "abstraction_type": "xilinx.com:signal:data_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "l_intf": {
+          "vlnv": "xilinx.com:signal:data:1.0",
+          "abstraction_type": "xilinx.com:signal:data_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "thresh0_intf": {
+          "vlnv": "xilinx.com:signal:data:1.0",
+          "abstraction_type": "xilinx.com:signal:data_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "q_intf": {
+          "vlnv": "xilinx.com:signal:data:1.0",
+          "abstraction_type": "xilinx.com:signal:data_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "LAYERED_METADATA": [ { "value": "xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value data} bitwidth {attribs {resolve_type generated dependency bitwidth format long minimum {} maximum {}} value 32} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} integer {signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value false}}}} DATA_WIDTH 32}", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "DATA": [ { "physical_name": "Q" } ]
+          }
+        }
+      }
+    }
+  }
+}

cx9261a_demo_cmos_20240829/project_fix_dac.srcs/sources_1/bd/system_top/ip/system_top_c_counter_binary_2_0/system_top_c_counter_binary_2_0.xci

@@ -0,0 +1,192 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "system_top_c_counter_binary_2_0",
+    "cell_name": "c_counter_binary_2",
+    "component_reference": "xilinx.com:ip:c_counter_binary:12.0",
+    "ip_revision": "19",
+    "gen_directory": "../../../../../../project_fix_dac.gen/sources_1/bd/system_top/ip/system_top_c_counter_binary_2_0",
+    "parameters": {
+      "component_parameters": {
+        "Component_Name": [ { "value": "system_top_c_counter_binary_2_0", "resolve_type": "user", "usage": "all" } ],
+        "Implementation": [ { "value": "Fabric", "resolve_type": "user", "usage": "all" } ],
+        "Output_Width": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Increment_Value": [ { "value": "4", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Restrict_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Final_Count_Value": [ { "value": "1", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Count_Mode": [ { "value": "UP", "resolve_type": "user", "usage": "all" } ],
+        "Sync_Threshold_Output": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Threshold_Value": [ { "value": "1", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "CE": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "SCLR": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "SSET": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "SINIT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "SINIT_Value": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "SyncCtrlPriority": [ { "value": "Reset_Overrides_Set", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Sync_CE_Priority": [ { "value": "Sync_Overrides_CE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "AINIT_Value": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
+        "Load": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Latency_Configuration": [ { "value": "Manual", "resolve_type": "user", "usage": "all" } ],
+        "Latency": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Fb_Latency_Configuration": [ { "value": "Manual", "resolve_type": "user", "usage": "all" } ],
+        "Fb_Latency": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Load_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ]
+      },
+      "model_parameters": {
+        "C_IMPLEMENTATION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_VERBOSITY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_XDEVICEFAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ],
+        "C_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_CE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_SCLR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_RESTRICT_COUNT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_COUNT_TO": [ { "value": "1", "resolve_type": "generated", "usage": "all" } ],
+        "C_COUNT_BY": [ { "value": "100", "resolve_type": "generated", "usage": "all" } ],
+        "C_COUNT_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_THRESH0_VALUE": [ { "value": "1", "resolve_type": "generated", "usage": "all" } ],
+        "C_CE_OVERRIDES_SYNC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_THRESH0": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_LOAD": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_LOAD_LOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_FB_LATENCY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AINIT_VAL": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
+        "C_SINIT_VAL": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
+        "C_SCLR_OVERRIDES_SSET": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_SSET": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_SINIT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "zynq" } ],
+        "BASE_BOARD_PART": [ { "value": "xilinx.com:zc706:part0:1.4" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xc7z045" } ],
+        "NEXTGEN_VERSAL": [ { "value": "0" } ],
+        "PACKAGE": [ { "value": "ffg900" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Integrator" } ],
+        "IPREVISION": [ { "value": "19" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../../../project_fix_dac.gen/sources_1/bd/system_top/ip/system_top_c_counter_binary_2_0" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "../../ipshared" } ],
+        "SWVERSION": [ { "value": "2024.1" } ],
+        "SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "CLK": [ { "direction": "in", "driver_value": "0x0" } ],
+        "CE": [ { "direction": "in", "driver_value": "0x1" } ],
+        "Q": [ { "direction": "out", "size_left": "31", "size_right": "0" } ]
+      },
+      "interfaces": {
+        "sset_intf": {
+          "vlnv": "xilinx.com:signal:data:1.0",
+          "abstraction_type": "xilinx.com:signal:data_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "clk_intf": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "q_intf:thresh0_intf:l_intf:load_intf:up_intf:sinit_intf:sset_intf", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "SCLR", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "ASSOCIATED_CLKEN": [ { "value": "CE", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "100000000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_top_data_clk_1", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "CLK" } ]
+          }
+        },
+        "sclr_intf": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "ce_intf": {
+          "vlnv": "xilinx.com:signal:clockenable:1.0",
+          "abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ]
+          },
+          "port_maps": {
+            "CE": [ { "physical_name": "CE" } ]
+          }
+        },
+        "sinit_intf": {
+          "vlnv": "xilinx.com:signal:data:1.0",
+          "abstraction_type": "xilinx.com:signal:data_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "up_intf": {
+          "vlnv": "xilinx.com:signal:data:1.0",
+          "abstraction_type": "xilinx.com:signal:data_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "load_intf": {
+          "vlnv": "xilinx.com:signal:data:1.0",
+          "abstraction_type": "xilinx.com:signal:data_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "l_intf": {
+          "vlnv": "xilinx.com:signal:data:1.0",
+          "abstraction_type": "xilinx.com:signal:data_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "thresh0_intf": {
+          "vlnv": "xilinx.com:signal:data:1.0",
+          "abstraction_type": "xilinx.com:signal:data_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "q_intf": {
+          "vlnv": "xilinx.com:signal:data:1.0",
+          "abstraction_type": "xilinx.com:signal:data_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "LAYERED_METADATA": [ { "value": "xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value data} bitwidth {attribs {resolve_type generated dependency bitwidth format long minimum {} maximum {}} value 32} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} integer {signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value false}}}} DATA_WIDTH 32}", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "DATA": [ { "physical_name": "Q" } ]
+          }
+        }
+      }
+    }
+  }
+}

cx9261a_demo_cmos_20240829/project_fix_dac.srcs/sources_1/bd/system_top/ip/system_top_fifo_generator_0_0/system_top_fifo_generator_0_0.xci

@@ -0,0 +1,533 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "system_top_fifo_generator_0_0",
+    "cell_name": "fifo_generator_0",
+    "component_reference": "xilinx.com:ip:fifo_generator:13.2",
+    "ip_revision": "10",
+    "gen_directory": "../../../../../../project_fix_dac.gen/sources_1/bd/system_top/ip/system_top_fifo_generator_0_0",
+    "parameters": {
+      "component_parameters": {
+        "Component_Name": [ { "value": "system_top_fifo_generator_0_0", "resolve_type": "user", "usage": "all" } ],
+        "Fifo_Implementation": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
+        "synchronization_stages": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "synchronization_stages_axi": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "INTERFACE_TYPE": [ { "value": "AXI_STREAM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Performance_Options": [ { "value": "Standard_FIFO", "resolve_type": "user", "usage": "all" } ],
+        "asymmetric_port_width": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Input_Data_Width": [ { "value": "18", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Input_Depth": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
+        "Output_Data_Width": [ { "value": "18", "resolve_type": "user", "usage": "all" } ],
+        "Output_Depth": [ { "value": "1024", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Enable_ECC": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Use_Embedded_Registers": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Reset_Pin": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Enable_Reset_Synchronization": [ { "value": "true", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Reset_Type": [ { "value": "Asynchronous_Reset", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Full_Flags_Reset_Value": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Use_Dout_Reset": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Dout_Reset_Value": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
+        "dynamic_power_saving": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Almost_Full_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Almost_Empty_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Valid_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Valid_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Underflow_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Underflow_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Write_Acknowledge_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Write_Acknowledge_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Overflow_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Overflow_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Inject_Sbit_Error": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Dbit_Error": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "ecc_pipeline_reg": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Use_Extra_Logic": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Data_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Data_Count_Width": [ { "value": "10", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Write_Data_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Write_Data_Count_Width": [ { "value": "10", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Read_Data_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Read_Data_Count_Width": [ { "value": "10", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Disable_Timing_Violations": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Read_Clock_Frequency": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Write_Clock_Frequency": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Programmable_Full_Type": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "usage": "all" } ],
+        "Full_Threshold_Assert_Value": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Full_Threshold_Negate_Value": [ { "value": "1021", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Programmable_Empty_Type": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "usage": "all" } ],
+        "Empty_Threshold_Assert_Value": [ { "value": "2", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Empty_Threshold_Negate_Value": [ { "value": "3", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "PROTOCOL": [ { "value": "AXI4", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Clock_Type_AXI": [ { "value": "Independent_Clock", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "HAS_ACLKEN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Clock_Enable_Type": [ { "value": "Slave_Interface_Clock_Enable", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "READ_WRITE_MODE": [ { "value": "READ_WRITE", "resolve_type": "user", "usage": "all" } ],
+        "ID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "ADDRESS_WIDTH": [ { "value": "32", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "DATA_WIDTH": [ { "value": "64", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "AWUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "WUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "BUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "ARUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "RUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "TDATA_NUM_BYTES": [ { "value": "8", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "TID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "TDEST_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "TUSER_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Enable_TREADY": [ { "value": "true", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Enable_TLAST": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "HAS_TSTRB": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "TSTRB_WIDTH": [ { "value": "8", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "HAS_TKEEP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "TKEEP_WIDTH": [ { "value": "8", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "wach_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Implementation_wach": [ { "value": "Independent_Clocks_Distributed_RAM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Application_Type_wach": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Enable_ECC_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Sbit_Error_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Dbit_Error_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Input_Depth_wach": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
+        "Enable_Data_Counts_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Programmable_Full_Type_wach": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Full_Threshold_Assert_Value_wach": [ { "value": "15", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Programmable_Empty_Type_wach": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Empty_Threshold_Assert_Value_wach": [ { "value": "13", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "wdch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Implementation_wdch": [ { "value": "Independent_Clocks_Block_RAM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Application_Type_wdch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Enable_ECC_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Sbit_Error_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Dbit_Error_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Input_Depth_wdch": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
+        "Enable_Data_Counts_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Programmable_Full_Type_wdch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Full_Threshold_Assert_Value_wdch": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Programmable_Empty_Type_wdch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Empty_Threshold_Assert_Value_wdch": [ { "value": "1021", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "wrch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Implementation_wrch": [ { "value": "Independent_Clocks_Distributed_RAM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Application_Type_wrch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Enable_ECC_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Sbit_Error_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Dbit_Error_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Input_Depth_wrch": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
+        "Enable_Data_Counts_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Programmable_Full_Type_wrch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Full_Threshold_Assert_Value_wrch": [ { "value": "15", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Programmable_Empty_Type_wrch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Empty_Threshold_Assert_Value_wrch": [ { "value": "13", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "rach_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Implementation_rach": [ { "value": "Independent_Clocks_Distributed_RAM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Application_Type_rach": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Enable_ECC_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Sbit_Error_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Dbit_Error_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Input_Depth_rach": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
+        "Enable_Data_Counts_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Programmable_Full_Type_rach": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Full_Threshold_Assert_Value_rach": [ { "value": "15", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Programmable_Empty_Type_rach": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Empty_Threshold_Assert_Value_rach": [ { "value": "13", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "rdch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Implementation_rdch": [ { "value": "Independent_Clocks_Block_RAM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Application_Type_rdch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Enable_ECC_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Sbit_Error_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Dbit_Error_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Input_Depth_rdch": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
+        "Enable_Data_Counts_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Programmable_Full_Type_rdch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Full_Threshold_Assert_Value_rdch": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Programmable_Empty_Type_rdch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Empty_Threshold_Assert_Value_rdch": [ { "value": "1021", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "axis_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Implementation_axis": [ { "value": "Independent_Clocks_Block_RAM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Application_Type_axis": [ { "value": "Data_FIFO", "resolve_type": "user", "usage": "all" } ],
+        "Enable_ECC_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Inject_Sbit_Error_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Dbit_Error_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Input_Depth_axis": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
+        "Enable_Data_Counts_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Programmable_Full_Type_axis": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "usage": "all" } ],
+        "Full_Threshold_Assert_Value_axis": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Programmable_Empty_Type_axis": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "usage": "all" } ],
+        "Empty_Threshold_Assert_Value_axis": [ { "value": "1021", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Register_Slice_Mode_wach": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
+        "Register_Slice_Mode_wdch": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
+        "Register_Slice_Mode_wrch": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
+        "Register_Slice_Mode_rach": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
+        "Register_Slice_Mode_rdch": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
+        "Register_Slice_Mode_axis": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
+        "Underflow_Flag_AXI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Underflow_Sense_AXI": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Overflow_Flag_AXI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Overflow_Sense_AXI": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Disable_Timing_Violations_AXI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Add_NGC_Constraint_AXI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Enable_Common_Underflow": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Enable_Common_Overflow": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "enable_read_pointer_increment_by2": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Use_Embedded_Registers_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "enable_low_latency": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "use_dout_register": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Master_interface_Clock_enable_memory_mapped": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Slave_interface_Clock_enable_memory_mapped": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Output_Register_Type": [ { "value": "Embedded_Reg", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Enable_Safety_Circuit": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Enable_ECC_Type": [ { "value": "Hard_ECC", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "C_SELECT_XPM": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ]
+      },
+      "model_parameters": {
+        "C_COMMON_CLOCK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_SELECT_XPM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_COUNT_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DATA_COUNT_WIDTH": [ { "value": "10", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DEFAULT_VALUE": [ { "value": "BlankString", "resolve_type": "generated", "usage": "all" } ],
+        "C_DIN_WIDTH": [ { "value": "18", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DOUT_RST_VAL": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
+        "C_DOUT_WIDTH": [ { "value": "18", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ENABLE_RLOCS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_FAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ],
+        "C_FULL_FLAGS_RST_VAL": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_ALMOST_EMPTY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_ALMOST_FULL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_BACKUP": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_DATA_COUNT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_INT_CLK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_MEMINIT_FILE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_OVERFLOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_RD_DATA_COUNT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_RD_RST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_RST": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_SRST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_UNDERFLOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_VALID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_WR_ACK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_WR_DATA_COUNT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_WR_RST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_IMPLEMENTATION_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_INIT_WR_PNTR_VAL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MEMORY_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MIF_FILE_NAME": [ { "value": "BlankString", "resolve_type": "generated", "usage": "all" } ],
+        "C_OPTIMIZATION_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_OVERFLOW_LOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PRELOAD_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PRELOAD_REGS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PRIM_FIFO_TYPE": [ { "value": "4kx4", "resolve_type": "generated", "usage": "all" } ],
+        "C_PROG_EMPTY_THRESH_ASSERT_VAL": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_EMPTY_THRESH_NEGATE_VAL": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_EMPTY_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_FULL_THRESH_ASSERT_VAL": [ { "value": "1022", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_FULL_THRESH_NEGATE_VAL": [ { "value": "1021", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_FULL_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_RD_DATA_COUNT_WIDTH": [ { "value": "10", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_RD_DEPTH": [ { "value": "1024", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_RD_FREQ": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_RD_PNTR_WIDTH": [ { "value": "10", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_UNDERFLOW_LOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_DOUT_RST": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_ECC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_EMBEDDED_REG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_PIPELINE_REG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_POWER_SAVING_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_FIFO16_FLAGS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_FWFT_DATA_COUNT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_VALID_LOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WR_ACK_LOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WR_DATA_COUNT_WIDTH": [ { "value": "10", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WR_DEPTH": [ { "value": "1024", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WR_FREQ": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WR_PNTR_WIDTH": [ { "value": "10", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WR_RESPONSE_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MSGON_VAL": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ENABLE_RST_SYNC": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_EN_SAFETY_CKT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ERROR_INJECTION_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_SYNCHRONIZER_STAGE": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_INTERFACE_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_AXI_WR_CHANNEL": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_AXI_RD_CHANNEL": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_SLAVE_CE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_MASTER_CE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ADD_NGC_CONSTRAINT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_COMMON_OVERFLOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_COMMON_UNDERFLOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_DEFAULT_SETTINGS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_ID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_DATA_WIDTH": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_LEN_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_LOCK_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_AXI_ID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_AXI_AWUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_AXI_WUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_AXI_BUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_AXI_ARUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_AXI_RUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_ARUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_AWUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_WUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_BUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_RUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_AXIS_TDATA": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_AXIS_TID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_AXIS_TDEST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_AXIS_TUSER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_AXIS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_AXIS_TLAST": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_AXIS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_AXIS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXIS_TDATA_WIDTH": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXIS_TID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXIS_TDEST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXIS_TUSER_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXIS_TSTRB_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXIS_TKEEP_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WACH_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WDCH_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WRCH_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_RACH_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_RDCH_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXIS_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_IMPLEMENTATION_TYPE_WACH": [ { "value": "12", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_IMPLEMENTATION_TYPE_WDCH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_IMPLEMENTATION_TYPE_WRCH": [ { "value": "12", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_IMPLEMENTATION_TYPE_RACH": [ { "value": "12", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_IMPLEMENTATION_TYPE_RDCH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_IMPLEMENTATION_TYPE_AXIS": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_APPLICATION_TYPE_WACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_APPLICATION_TYPE_WDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_APPLICATION_TYPE_WRCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_APPLICATION_TYPE_RACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_APPLICATION_TYPE_RDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_APPLICATION_TYPE_AXIS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PRIM_FIFO_TYPE_WACH": [ { "value": "512x36", "resolve_type": "generated", "usage": "all" } ],
+        "C_PRIM_FIFO_TYPE_WDCH": [ { "value": "1kx36", "resolve_type": "generated", "usage": "all" } ],
+        "C_PRIM_FIFO_TYPE_WRCH": [ { "value": "512x36", "resolve_type": "generated", "usage": "all" } ],
+        "C_PRIM_FIFO_TYPE_RACH": [ { "value": "512x36", "resolve_type": "generated", "usage": "all" } ],
+        "C_PRIM_FIFO_TYPE_RDCH": [ { "value": "1kx36", "resolve_type": "generated", "usage": "all" } ],
+        "C_PRIM_FIFO_TYPE_AXIS": [ { "value": "1kx36", "resolve_type": "generated", "usage": "all" } ],
+        "C_USE_ECC_WACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_ECC_WDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_ECC_WRCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_ECC_RACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_ECC_RDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_ECC_AXIS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ERROR_INJECTION_TYPE_WACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ERROR_INJECTION_TYPE_WDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ERROR_INJECTION_TYPE_WRCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ERROR_INJECTION_TYPE_RACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ERROR_INJECTION_TYPE_RDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ERROR_INJECTION_TYPE_AXIS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DIN_WIDTH_WACH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DIN_WIDTH_WDCH": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DIN_WIDTH_WRCH": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DIN_WIDTH_RACH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DIN_WIDTH_RDCH": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DIN_WIDTH_AXIS": [ { "value": "69", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WR_DEPTH_WACH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WR_DEPTH_WDCH": [ { "value": "1024", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WR_DEPTH_WRCH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WR_DEPTH_RACH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WR_DEPTH_RDCH": [ { "value": "1024", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WR_DEPTH_AXIS": [ { "value": "1024", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WR_PNTR_WIDTH_WACH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WR_PNTR_WIDTH_WDCH": [ { "value": "10", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WR_PNTR_WIDTH_WRCH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WR_PNTR_WIDTH_RACH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WR_PNTR_WIDTH_RDCH": [ { "value": "10", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WR_PNTR_WIDTH_AXIS": [ { "value": "10", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_DATA_COUNTS_WACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_DATA_COUNTS_WDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_DATA_COUNTS_WRCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_DATA_COUNTS_RACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_DATA_COUNTS_RDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_DATA_COUNTS_AXIS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_PROG_FLAGS_WACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_PROG_FLAGS_WDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_PROG_FLAGS_WRCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_PROG_FLAGS_RACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_PROG_FLAGS_RDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_PROG_FLAGS_AXIS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_FULL_TYPE_WACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_FULL_TYPE_WDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_FULL_TYPE_WRCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_FULL_TYPE_RACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_FULL_TYPE_RDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_FULL_TYPE_AXIS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_FULL_THRESH_ASSERT_VAL_WACH": [ { "value": "15", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_FULL_THRESH_ASSERT_VAL_WDCH": [ { "value": "1023", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_FULL_THRESH_ASSERT_VAL_WRCH": [ { "value": "15", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_FULL_THRESH_ASSERT_VAL_RACH": [ { "value": "15", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_FULL_THRESH_ASSERT_VAL_RDCH": [ { "value": "1023", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_FULL_THRESH_ASSERT_VAL_AXIS": [ { "value": "1023", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_EMPTY_TYPE_WACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_EMPTY_TYPE_WDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_EMPTY_TYPE_WRCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_EMPTY_TYPE_RACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_EMPTY_TYPE_RDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_EMPTY_TYPE_AXIS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH": [ { "value": "13", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH": [ { "value": "1021", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH": [ { "value": "13", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH": [ { "value": "13", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH": [ { "value": "1021", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS": [ { "value": "1021", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_REG_SLICE_MODE_WACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_REG_SLICE_MODE_WDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_REG_SLICE_MODE_WRCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_REG_SLICE_MODE_RACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_REG_SLICE_MODE_RDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_REG_SLICE_MODE_AXIS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "zynq" } ],
+        "BASE_BOARD_PART": [ { "value": "xilinx.com:zc706:part0:1.4" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xc7z045" } ],
+        "NEXTGEN_VERSAL": [ { "value": "0" } ],
+        "PACKAGE": [ { "value": "ffg900" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Integrator" } ],
+        "IPREVISION": [ { "value": "10" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../../../project_fix_dac.gen/sources_1/bd/system_top/ip/system_top_fifo_generator_0_0" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "../../ipshared" } ],
+        "SWVERSION": [ { "value": "2024.1" } ],
+        "SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "wr_rst_busy": [ { "direction": "out", "driver_value": "0" } ],
+        "rd_rst_busy": [ { "direction": "out", "driver_value": "0" } ],
+        "m_aclk": [ { "direction": "in", "driver_value": "0" } ],
+        "s_aclk": [ { "direction": "in", "driver_value": "0" } ],
+        "s_aresetn": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axis_tvalid": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axis_tready": [ { "direction": "out", "driver_value": "0x0" } ],
+        "s_axis_tdata": [ { "direction": "in", "size_left": "63", "size_right": "0", "driver_value": "0" } ],
+        "s_axis_tlast": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axis_tuser": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
+        "m_axis_tvalid": [ { "direction": "out", "driver_value": "0x0" } ],
+        "m_axis_tready": [ { "direction": "in", "driver_value": "0" } ],
+        "m_axis_tdata": [ { "direction": "out", "size_left": "63", "size_right": "0", "driver_value": "0" } ],
+        "m_axis_tlast": [ { "direction": "out", "driver_value": "0x0" } ],
+        "m_axis_tuser": [ { "direction": "out", "size_left": "3", "size_right": "0", "driver_value": "0" } ]
+      },
+      "interfaces": {
+        "M_AXIS": {
+          "vlnv": "xilinx.com:interface:axis:1.0",
+          "abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "TDATA_NUM_BYTES": [ { "value": "8", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TDEST_WIDTH": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TID_WIDTH": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TUSER_WIDTH": [ { "value": "4", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TREADY": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TSTRB": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TKEEP": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TLAST": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "200000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_top_mig_7series_0_0_ui_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "TDATA": [ { "physical_name": "m_axis_tdata" } ],
+            "TLAST": [ { "physical_name": "m_axis_tlast" } ],
+            "TREADY": [ { "physical_name": "m_axis_tready" } ],
+            "TUSER": [ { "physical_name": "m_axis_tuser" } ],
+            "TVALID": [ { "physical_name": "m_axis_tvalid" } ]
+          }
+        },
+        "S_AXIS": {
+          "vlnv": "xilinx.com:interface:axis:1.0",
+          "abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "TDATA_NUM_BYTES": [ { "value": "8", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TDEST_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TID_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TUSER_WIDTH": [ { "value": "4", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TREADY": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TSTRB": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TKEEP": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TLAST": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_top_data_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "TDATA": [ { "physical_name": "s_axis_tdata" } ],
+            "TLAST": [ { "physical_name": "s_axis_tlast" } ],
+            "TREADY": [ { "physical_name": "s_axis_tready" } ],
+            "TUSER": [ { "physical_name": "s_axis_tuser" } ],
+            "TVALID": [ { "physical_name": "s_axis_tvalid" } ]
+          }
+        },
+        "master_aclk": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "M_AXIS:M_AXI", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "200000000", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_top_mig_7series_0_0_ui_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "m_aclk" } ]
+          }
+        },
+        "slave_aclk": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "S_AXIS:S_AXI", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "s_aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_top_data_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "s_aclk" } ]
+          }
+        },
+        "slave_aresetn": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "s_aresetn" } ]
+          }
+        }
+      }
+    }
+  }
+}

cx9261a_demo_cmos_20240829/project_fix_dac.srcs/sources_1/bd/system_top/ip/system_top_fifo_generator_1_0/system_top_fifo_generator_1_0.xci

@@ -0,0 +1,533 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "system_top_fifo_generator_1_0",
+    "cell_name": "fifo_generator_1",
+    "component_reference": "xilinx.com:ip:fifo_generator:13.2",
+    "ip_revision": "10",
+    "gen_directory": "../../../../../../project_fix_dac.gen/sources_1/bd/system_top/ip/system_top_fifo_generator_1_0",
+    "parameters": {
+      "component_parameters": {
+        "Component_Name": [ { "value": "system_top_fifo_generator_1_0", "resolve_type": "user", "usage": "all" } ],
+        "Fifo_Implementation": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
+        "synchronization_stages": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "synchronization_stages_axi": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "INTERFACE_TYPE": [ { "value": "AXI_STREAM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Performance_Options": [ { "value": "Standard_FIFO", "resolve_type": "user", "usage": "all" } ],
+        "asymmetric_port_width": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Input_Data_Width": [ { "value": "18", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Input_Depth": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
+        "Output_Data_Width": [ { "value": "18", "resolve_type": "user", "usage": "all" } ],
+        "Output_Depth": [ { "value": "1024", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Enable_ECC": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Use_Embedded_Registers": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Reset_Pin": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Enable_Reset_Synchronization": [ { "value": "true", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Reset_Type": [ { "value": "Asynchronous_Reset", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Full_Flags_Reset_Value": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Use_Dout_Reset": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Dout_Reset_Value": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
+        "dynamic_power_saving": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Almost_Full_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Almost_Empty_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Valid_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Valid_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Underflow_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Underflow_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Write_Acknowledge_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Write_Acknowledge_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Overflow_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Overflow_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Inject_Sbit_Error": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Dbit_Error": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "ecc_pipeline_reg": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Use_Extra_Logic": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Data_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Data_Count_Width": [ { "value": "10", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Write_Data_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Write_Data_Count_Width": [ { "value": "10", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Read_Data_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Read_Data_Count_Width": [ { "value": "10", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Disable_Timing_Violations": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Read_Clock_Frequency": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Write_Clock_Frequency": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Programmable_Full_Type": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "usage": "all" } ],
+        "Full_Threshold_Assert_Value": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Full_Threshold_Negate_Value": [ { "value": "1021", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Programmable_Empty_Type": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "usage": "all" } ],
+        "Empty_Threshold_Assert_Value": [ { "value": "2", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Empty_Threshold_Negate_Value": [ { "value": "3", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "PROTOCOL": [ { "value": "AXI4", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Clock_Type_AXI": [ { "value": "Independent_Clock", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "HAS_ACLKEN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Clock_Enable_Type": [ { "value": "Slave_Interface_Clock_Enable", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "READ_WRITE_MODE": [ { "value": "READ_WRITE", "resolve_type": "user", "usage": "all" } ],
+        "ID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "ADDRESS_WIDTH": [ { "value": "32", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "DATA_WIDTH": [ { "value": "64", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "AWUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "WUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "BUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "ARUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "RUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "TDATA_NUM_BYTES": [ { "value": "8", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "TID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "TDEST_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "TUSER_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Enable_TREADY": [ { "value": "true", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Enable_TLAST": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "HAS_TSTRB": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "TSTRB_WIDTH": [ { "value": "8", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "HAS_TKEEP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "TKEEP_WIDTH": [ { "value": "8", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "wach_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Implementation_wach": [ { "value": "Independent_Clocks_Distributed_RAM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Application_Type_wach": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Enable_ECC_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Sbit_Error_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Dbit_Error_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Input_Depth_wach": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
+        "Enable_Data_Counts_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Programmable_Full_Type_wach": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Full_Threshold_Assert_Value_wach": [ { "value": "15", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Programmable_Empty_Type_wach": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Empty_Threshold_Assert_Value_wach": [ { "value": "13", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "wdch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Implementation_wdch": [ { "value": "Independent_Clocks_Block_RAM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Application_Type_wdch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Enable_ECC_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Sbit_Error_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Dbit_Error_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Input_Depth_wdch": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
+        "Enable_Data_Counts_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Programmable_Full_Type_wdch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Full_Threshold_Assert_Value_wdch": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Programmable_Empty_Type_wdch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Empty_Threshold_Assert_Value_wdch": [ { "value": "1021", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "wrch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Implementation_wrch": [ { "value": "Independent_Clocks_Distributed_RAM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Application_Type_wrch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Enable_ECC_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Sbit_Error_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Dbit_Error_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Input_Depth_wrch": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
+        "Enable_Data_Counts_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Programmable_Full_Type_wrch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Full_Threshold_Assert_Value_wrch": [ { "value": "15", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Programmable_Empty_Type_wrch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Empty_Threshold_Assert_Value_wrch": [ { "value": "13", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "rach_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Implementation_rach": [ { "value": "Independent_Clocks_Distributed_RAM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Application_Type_rach": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Enable_ECC_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Sbit_Error_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Dbit_Error_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Input_Depth_rach": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
+        "Enable_Data_Counts_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Programmable_Full_Type_rach": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Full_Threshold_Assert_Value_rach": [ { "value": "15", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Programmable_Empty_Type_rach": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Empty_Threshold_Assert_Value_rach": [ { "value": "13", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "rdch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Implementation_rdch": [ { "value": "Independent_Clocks_Block_RAM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Application_Type_rdch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Enable_ECC_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Sbit_Error_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Dbit_Error_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Input_Depth_rdch": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
+        "Enable_Data_Counts_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Programmable_Full_Type_rdch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Full_Threshold_Assert_Value_rdch": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Programmable_Empty_Type_rdch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Empty_Threshold_Assert_Value_rdch": [ { "value": "1021", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "axis_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Implementation_axis": [ { "value": "Independent_Clocks_Block_RAM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Application_Type_axis": [ { "value": "Data_FIFO", "resolve_type": "user", "usage": "all" } ],
+        "Enable_ECC_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Inject_Sbit_Error_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Dbit_Error_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Input_Depth_axis": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
+        "Enable_Data_Counts_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Programmable_Full_Type_axis": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "usage": "all" } ],
+        "Full_Threshold_Assert_Value_axis": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Programmable_Empty_Type_axis": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "usage": "all" } ],
+        "Empty_Threshold_Assert_Value_axis": [ { "value": "1021", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Register_Slice_Mode_wach": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
+        "Register_Slice_Mode_wdch": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
+        "Register_Slice_Mode_wrch": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
+        "Register_Slice_Mode_rach": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
+        "Register_Slice_Mode_rdch": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
+        "Register_Slice_Mode_axis": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
+        "Underflow_Flag_AXI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Underflow_Sense_AXI": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Overflow_Flag_AXI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Overflow_Sense_AXI": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Disable_Timing_Violations_AXI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Add_NGC_Constraint_AXI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Enable_Common_Underflow": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Enable_Common_Overflow": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "enable_read_pointer_increment_by2": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Use_Embedded_Registers_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "enable_low_latency": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "use_dout_register": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Master_interface_Clock_enable_memory_mapped": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Slave_interface_Clock_enable_memory_mapped": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Output_Register_Type": [ { "value": "Embedded_Reg", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Enable_Safety_Circuit": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Enable_ECC_Type": [ { "value": "Hard_ECC", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "C_SELECT_XPM": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ]
+      },
+      "model_parameters": {
+        "C_COMMON_CLOCK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_SELECT_XPM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_COUNT_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DATA_COUNT_WIDTH": [ { "value": "10", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DEFAULT_VALUE": [ { "value": "BlankString", "resolve_type": "generated", "usage": "all" } ],
+        "C_DIN_WIDTH": [ { "value": "18", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DOUT_RST_VAL": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
+        "C_DOUT_WIDTH": [ { "value": "18", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ENABLE_RLOCS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_FAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ],
+        "C_FULL_FLAGS_RST_VAL": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_ALMOST_EMPTY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_ALMOST_FULL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_BACKUP": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_DATA_COUNT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_INT_CLK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_MEMINIT_FILE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_OVERFLOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_RD_DATA_COUNT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_RD_RST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_RST": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_SRST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_UNDERFLOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_VALID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_WR_ACK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_WR_DATA_COUNT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_WR_RST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_IMPLEMENTATION_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_INIT_WR_PNTR_VAL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MEMORY_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MIF_FILE_NAME": [ { "value": "BlankString", "resolve_type": "generated", "usage": "all" } ],
+        "C_OPTIMIZATION_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_OVERFLOW_LOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PRELOAD_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PRELOAD_REGS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PRIM_FIFO_TYPE": [ { "value": "4kx4", "resolve_type": "generated", "usage": "all" } ],
+        "C_PROG_EMPTY_THRESH_ASSERT_VAL": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_EMPTY_THRESH_NEGATE_VAL": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_EMPTY_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_FULL_THRESH_ASSERT_VAL": [ { "value": "1022", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_FULL_THRESH_NEGATE_VAL": [ { "value": "1021", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_FULL_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_RD_DATA_COUNT_WIDTH": [ { "value": "10", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_RD_DEPTH": [ { "value": "1024", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_RD_FREQ": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_RD_PNTR_WIDTH": [ { "value": "10", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_UNDERFLOW_LOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_DOUT_RST": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_ECC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_EMBEDDED_REG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_PIPELINE_REG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_POWER_SAVING_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_FIFO16_FLAGS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_FWFT_DATA_COUNT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_VALID_LOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WR_ACK_LOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WR_DATA_COUNT_WIDTH": [ { "value": "10", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WR_DEPTH": [ { "value": "1024", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WR_FREQ": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WR_PNTR_WIDTH": [ { "value": "10", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WR_RESPONSE_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MSGON_VAL": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ENABLE_RST_SYNC": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_EN_SAFETY_CKT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ERROR_INJECTION_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_SYNCHRONIZER_STAGE": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_INTERFACE_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_AXI_WR_CHANNEL": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_AXI_RD_CHANNEL": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_SLAVE_CE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_MASTER_CE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ADD_NGC_CONSTRAINT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_COMMON_OVERFLOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_COMMON_UNDERFLOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_DEFAULT_SETTINGS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_ID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_DATA_WIDTH": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_LEN_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_LOCK_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_AXI_ID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_AXI_AWUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_AXI_WUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_AXI_BUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_AXI_ARUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_AXI_RUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_ARUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_AWUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_WUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_BUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_RUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_AXIS_TDATA": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_AXIS_TID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_AXIS_TDEST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_AXIS_TUSER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_AXIS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_AXIS_TLAST": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_AXIS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_AXIS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXIS_TDATA_WIDTH": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXIS_TID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXIS_TDEST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXIS_TUSER_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXIS_TSTRB_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXIS_TKEEP_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WACH_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WDCH_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WRCH_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_RACH_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_RDCH_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXIS_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_IMPLEMENTATION_TYPE_WACH": [ { "value": "12", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_IMPLEMENTATION_TYPE_WDCH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_IMPLEMENTATION_TYPE_WRCH": [ { "value": "12", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_IMPLEMENTATION_TYPE_RACH": [ { "value": "12", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_IMPLEMENTATION_TYPE_RDCH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_IMPLEMENTATION_TYPE_AXIS": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_APPLICATION_TYPE_WACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_APPLICATION_TYPE_WDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_APPLICATION_TYPE_WRCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_APPLICATION_TYPE_RACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_APPLICATION_TYPE_RDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_APPLICATION_TYPE_AXIS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PRIM_FIFO_TYPE_WACH": [ { "value": "512x36", "resolve_type": "generated", "usage": "all" } ],
+        "C_PRIM_FIFO_TYPE_WDCH": [ { "value": "1kx36", "resolve_type": "generated", "usage": "all" } ],
+        "C_PRIM_FIFO_TYPE_WRCH": [ { "value": "512x36", "resolve_type": "generated", "usage": "all" } ],
+        "C_PRIM_FIFO_TYPE_RACH": [ { "value": "512x36", "resolve_type": "generated", "usage": "all" } ],
+        "C_PRIM_FIFO_TYPE_RDCH": [ { "value": "1kx36", "resolve_type": "generated", "usage": "all" } ],
+        "C_PRIM_FIFO_TYPE_AXIS": [ { "value": "1kx36", "resolve_type": "generated", "usage": "all" } ],
+        "C_USE_ECC_WACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_ECC_WDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_ECC_WRCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_ECC_RACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_ECC_RDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_ECC_AXIS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ERROR_INJECTION_TYPE_WACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ERROR_INJECTION_TYPE_WDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ERROR_INJECTION_TYPE_WRCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ERROR_INJECTION_TYPE_RACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ERROR_INJECTION_TYPE_RDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ERROR_INJECTION_TYPE_AXIS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DIN_WIDTH_WACH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DIN_WIDTH_WDCH": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DIN_WIDTH_WRCH": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DIN_WIDTH_RACH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DIN_WIDTH_RDCH": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DIN_WIDTH_AXIS": [ { "value": "69", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WR_DEPTH_WACH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WR_DEPTH_WDCH": [ { "value": "1024", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WR_DEPTH_WRCH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WR_DEPTH_RACH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WR_DEPTH_RDCH": [ { "value": "1024", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WR_DEPTH_AXIS": [ { "value": "1024", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WR_PNTR_WIDTH_WACH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WR_PNTR_WIDTH_WDCH": [ { "value": "10", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WR_PNTR_WIDTH_WRCH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WR_PNTR_WIDTH_RACH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WR_PNTR_WIDTH_RDCH": [ { "value": "10", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WR_PNTR_WIDTH_AXIS": [ { "value": "10", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_DATA_COUNTS_WACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_DATA_COUNTS_WDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_DATA_COUNTS_WRCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_DATA_COUNTS_RACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_DATA_COUNTS_RDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_DATA_COUNTS_AXIS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_PROG_FLAGS_WACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_PROG_FLAGS_WDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_PROG_FLAGS_WRCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_PROG_FLAGS_RACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_PROG_FLAGS_RDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_PROG_FLAGS_AXIS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_FULL_TYPE_WACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_FULL_TYPE_WDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_FULL_TYPE_WRCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_FULL_TYPE_RACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_FULL_TYPE_RDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_FULL_TYPE_AXIS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_FULL_THRESH_ASSERT_VAL_WACH": [ { "value": "15", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_FULL_THRESH_ASSERT_VAL_WDCH": [ { "value": "1023", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_FULL_THRESH_ASSERT_VAL_WRCH": [ { "value": "15", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_FULL_THRESH_ASSERT_VAL_RACH": [ { "value": "15", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_FULL_THRESH_ASSERT_VAL_RDCH": [ { "value": "1023", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_FULL_THRESH_ASSERT_VAL_AXIS": [ { "value": "1023", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_EMPTY_TYPE_WACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_EMPTY_TYPE_WDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_EMPTY_TYPE_WRCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_EMPTY_TYPE_RACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_EMPTY_TYPE_RDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_EMPTY_TYPE_AXIS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH": [ { "value": "13", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH": [ { "value": "1021", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH": [ { "value": "13", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH": [ { "value": "13", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH": [ { "value": "1021", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS": [ { "value": "1021", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_REG_SLICE_MODE_WACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_REG_SLICE_MODE_WDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_REG_SLICE_MODE_WRCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_REG_SLICE_MODE_RACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_REG_SLICE_MODE_RDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_REG_SLICE_MODE_AXIS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "zynq" } ],
+        "BASE_BOARD_PART": [ { "value": "xilinx.com:zc706:part0:1.4" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xc7z045" } ],
+        "NEXTGEN_VERSAL": [ { "value": "0" } ],
+        "PACKAGE": [ { "value": "ffg900" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Integrator" } ],
+        "IPREVISION": [ { "value": "10" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../../../project_fix_dac.gen/sources_1/bd/system_top/ip/system_top_fifo_generator_1_0" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "../../ipshared" } ],
+        "SWVERSION": [ { "value": "2024.1" } ],
+        "SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "wr_rst_busy": [ { "direction": "out", "driver_value": "0" } ],
+        "rd_rst_busy": [ { "direction": "out", "driver_value": "0" } ],
+        "m_aclk": [ { "direction": "in", "driver_value": "0" } ],
+        "s_aclk": [ { "direction": "in", "driver_value": "0" } ],
+        "s_aresetn": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axis_tvalid": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axis_tready": [ { "direction": "out", "driver_value": "0x0" } ],
+        "s_axis_tdata": [ { "direction": "in", "size_left": "63", "size_right": "0", "driver_value": "0" } ],
+        "s_axis_tlast": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axis_tuser": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
+        "m_axis_tvalid": [ { "direction": "out", "driver_value": "0x0" } ],
+        "m_axis_tready": [ { "direction": "in", "driver_value": "0" } ],
+        "m_axis_tdata": [ { "direction": "out", "size_left": "63", "size_right": "0", "driver_value": "0" } ],
+        "m_axis_tlast": [ { "direction": "out", "driver_value": "0x0" } ],
+        "m_axis_tuser": [ { "direction": "out", "size_left": "3", "size_right": "0", "driver_value": "0" } ]
+      },
+      "interfaces": {
+        "M_AXIS": {
+          "vlnv": "xilinx.com:interface:axis:1.0",
+          "abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "TDATA_NUM_BYTES": [ { "value": "8", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TDEST_WIDTH": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TID_WIDTH": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TUSER_WIDTH": [ { "value": "4", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TREADY": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TSTRB": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TKEEP": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TLAST": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "200000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_top_mig_7series_0_0_ui_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "TDATA": [ { "physical_name": "m_axis_tdata" } ],
+            "TLAST": [ { "physical_name": "m_axis_tlast" } ],
+            "TREADY": [ { "physical_name": "m_axis_tready" } ],
+            "TUSER": [ { "physical_name": "m_axis_tuser" } ],
+            "TVALID": [ { "physical_name": "m_axis_tvalid" } ]
+          }
+        },
+        "S_AXIS": {
+          "vlnv": "xilinx.com:interface:axis:1.0",
+          "abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "TDATA_NUM_BYTES": [ { "value": "8", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TDEST_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TID_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TUSER_WIDTH": [ { "value": "4", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TREADY": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TSTRB": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TKEEP": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TLAST": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_top_data_clk_1", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "TDATA": [ { "physical_name": "s_axis_tdata" } ],
+            "TLAST": [ { "physical_name": "s_axis_tlast" } ],
+            "TREADY": [ { "physical_name": "s_axis_tready" } ],
+            "TUSER": [ { "physical_name": "s_axis_tuser" } ],
+            "TVALID": [ { "physical_name": "s_axis_tvalid" } ]
+          }
+        },
+        "master_aclk": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "M_AXIS:M_AXI", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "200000000", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_top_mig_7series_0_0_ui_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "m_aclk" } ]
+          }
+        },
+        "slave_aclk": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "S_AXIS:S_AXI", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "s_aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_top_data_clk_1", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "s_aclk" } ]
+          }
+        },
+        "slave_aresetn": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "s_aresetn" } ]
+          }
+        }
+      }
+    }
+  }
+}

cx9261a_demo_cmos_20240829/project_fix_dac.srcs/sources_1/bd/system_top/ip/system_top_fifo_generator_2_0/system_top_fifo_generator_2_0.xci

@@ -0,0 +1,533 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "system_top_fifo_generator_2_0",
+    "cell_name": "fifo_generator_2",
+    "component_reference": "xilinx.com:ip:fifo_generator:13.2",
+    "ip_revision": "10",
+    "gen_directory": "../../../../../../project_fix_dac.gen/sources_1/bd/system_top/ip/system_top_fifo_generator_2_0",
+    "parameters": {
+      "component_parameters": {
+        "Component_Name": [ { "value": "system_top_fifo_generator_2_0", "resolve_type": "user", "usage": "all" } ],
+        "Fifo_Implementation": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
+        "synchronization_stages": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "synchronization_stages_axi": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "INTERFACE_TYPE": [ { "value": "AXI_STREAM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Performance_Options": [ { "value": "Standard_FIFO", "resolve_type": "user", "usage": "all" } ],
+        "asymmetric_port_width": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Input_Data_Width": [ { "value": "18", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Input_Depth": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
+        "Output_Data_Width": [ { "value": "18", "resolve_type": "user", "usage": "all" } ],
+        "Output_Depth": [ { "value": "1024", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Enable_ECC": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Use_Embedded_Registers": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Reset_Pin": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Enable_Reset_Synchronization": [ { "value": "true", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Reset_Type": [ { "value": "Asynchronous_Reset", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Full_Flags_Reset_Value": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Use_Dout_Reset": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Dout_Reset_Value": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
+        "dynamic_power_saving": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Almost_Full_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Almost_Empty_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Valid_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Valid_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Underflow_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Underflow_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Write_Acknowledge_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Write_Acknowledge_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Overflow_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Overflow_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Inject_Sbit_Error": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Dbit_Error": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "ecc_pipeline_reg": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Use_Extra_Logic": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Data_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Data_Count_Width": [ { "value": "10", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Write_Data_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Write_Data_Count_Width": [ { "value": "10", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Read_Data_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Read_Data_Count_Width": [ { "value": "10", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Disable_Timing_Violations": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Read_Clock_Frequency": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Write_Clock_Frequency": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Programmable_Full_Type": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "usage": "all" } ],
+        "Full_Threshold_Assert_Value": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Full_Threshold_Negate_Value": [ { "value": "1021", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Programmable_Empty_Type": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "usage": "all" } ],
+        "Empty_Threshold_Assert_Value": [ { "value": "2", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Empty_Threshold_Negate_Value": [ { "value": "3", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "PROTOCOL": [ { "value": "AXI4", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Clock_Type_AXI": [ { "value": "Independent_Clock", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "HAS_ACLKEN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Clock_Enable_Type": [ { "value": "Slave_Interface_Clock_Enable", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "READ_WRITE_MODE": [ { "value": "READ_WRITE", "resolve_type": "user", "usage": "all" } ],
+        "ID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "ADDRESS_WIDTH": [ { "value": "32", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "DATA_WIDTH": [ { "value": "64", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "AWUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "WUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "BUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "ARUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "RUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "TDATA_NUM_BYTES": [ { "value": "8", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "TID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "TDEST_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "TUSER_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Enable_TREADY": [ { "value": "true", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Enable_TLAST": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "HAS_TSTRB": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "TSTRB_WIDTH": [ { "value": "8", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "HAS_TKEEP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "TKEEP_WIDTH": [ { "value": "8", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "wach_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Implementation_wach": [ { "value": "Independent_Clocks_Distributed_RAM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Application_Type_wach": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Enable_ECC_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Sbit_Error_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Dbit_Error_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Input_Depth_wach": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
+        "Enable_Data_Counts_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Programmable_Full_Type_wach": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Full_Threshold_Assert_Value_wach": [ { "value": "15", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Programmable_Empty_Type_wach": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Empty_Threshold_Assert_Value_wach": [ { "value": "13", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "wdch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Implementation_wdch": [ { "value": "Independent_Clocks_Block_RAM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Application_Type_wdch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Enable_ECC_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Sbit_Error_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Dbit_Error_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Input_Depth_wdch": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
+        "Enable_Data_Counts_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Programmable_Full_Type_wdch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Full_Threshold_Assert_Value_wdch": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Programmable_Empty_Type_wdch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Empty_Threshold_Assert_Value_wdch": [ { "value": "1021", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "wrch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Implementation_wrch": [ { "value": "Independent_Clocks_Distributed_RAM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Application_Type_wrch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Enable_ECC_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Sbit_Error_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Dbit_Error_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Input_Depth_wrch": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
+        "Enable_Data_Counts_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Programmable_Full_Type_wrch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Full_Threshold_Assert_Value_wrch": [ { "value": "15", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Programmable_Empty_Type_wrch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Empty_Threshold_Assert_Value_wrch": [ { "value": "13", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "rach_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Implementation_rach": [ { "value": "Independent_Clocks_Distributed_RAM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Application_Type_rach": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Enable_ECC_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Sbit_Error_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Dbit_Error_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Input_Depth_rach": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
+        "Enable_Data_Counts_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Programmable_Full_Type_rach": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Full_Threshold_Assert_Value_rach": [ { "value": "15", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Programmable_Empty_Type_rach": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Empty_Threshold_Assert_Value_rach": [ { "value": "13", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "rdch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Implementation_rdch": [ { "value": "Independent_Clocks_Block_RAM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Application_Type_rdch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Enable_ECC_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Sbit_Error_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Dbit_Error_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Input_Depth_rdch": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
+        "Enable_Data_Counts_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Programmable_Full_Type_rdch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Full_Threshold_Assert_Value_rdch": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Programmable_Empty_Type_rdch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Empty_Threshold_Assert_Value_rdch": [ { "value": "1021", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "axis_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Implementation_axis": [ { "value": "Independent_Clocks_Block_RAM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Application_Type_axis": [ { "value": "Data_FIFO", "resolve_type": "user", "usage": "all" } ],
+        "Enable_ECC_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Inject_Sbit_Error_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Dbit_Error_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Input_Depth_axis": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
+        "Enable_Data_Counts_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Programmable_Full_Type_axis": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "usage": "all" } ],
+        "Full_Threshold_Assert_Value_axis": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Programmable_Empty_Type_axis": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "usage": "all" } ],
+        "Empty_Threshold_Assert_Value_axis": [ { "value": "1021", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Register_Slice_Mode_wach": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
+        "Register_Slice_Mode_wdch": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
+        "Register_Slice_Mode_wrch": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
+        "Register_Slice_Mode_rach": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
+        "Register_Slice_Mode_rdch": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
+        "Register_Slice_Mode_axis": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
+        "Underflow_Flag_AXI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Underflow_Sense_AXI": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Overflow_Flag_AXI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Overflow_Sense_AXI": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Disable_Timing_Violations_AXI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Add_NGC_Constraint_AXI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Enable_Common_Underflow": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Enable_Common_Overflow": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "enable_read_pointer_increment_by2": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Use_Embedded_Registers_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "enable_low_latency": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "use_dout_register": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Master_interface_Clock_enable_memory_mapped": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Slave_interface_Clock_enable_memory_mapped": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Output_Register_Type": [ { "value": "Embedded_Reg", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Enable_Safety_Circuit": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Enable_ECC_Type": [ { "value": "Hard_ECC", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "C_SELECT_XPM": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ]
+      },
+      "model_parameters": {
+        "C_COMMON_CLOCK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_SELECT_XPM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_COUNT_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DATA_COUNT_WIDTH": [ { "value": "10", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DEFAULT_VALUE": [ { "value": "BlankString", "resolve_type": "generated", "usage": "all" } ],
+        "C_DIN_WIDTH": [ { "value": "18", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DOUT_RST_VAL": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
+        "C_DOUT_WIDTH": [ { "value": "18", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ENABLE_RLOCS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_FAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ],
+        "C_FULL_FLAGS_RST_VAL": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_ALMOST_EMPTY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_ALMOST_FULL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_BACKUP": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_DATA_COUNT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_INT_CLK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_MEMINIT_FILE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_OVERFLOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_RD_DATA_COUNT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_RD_RST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_RST": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_SRST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_UNDERFLOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_VALID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_WR_ACK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_WR_DATA_COUNT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_WR_RST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_IMPLEMENTATION_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_INIT_WR_PNTR_VAL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MEMORY_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MIF_FILE_NAME": [ { "value": "BlankString", "resolve_type": "generated", "usage": "all" } ],
+        "C_OPTIMIZATION_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_OVERFLOW_LOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PRELOAD_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PRELOAD_REGS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PRIM_FIFO_TYPE": [ { "value": "4kx4", "resolve_type": "generated", "usage": "all" } ],
+        "C_PROG_EMPTY_THRESH_ASSERT_VAL": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_EMPTY_THRESH_NEGATE_VAL": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_EMPTY_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_FULL_THRESH_ASSERT_VAL": [ { "value": "1022", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_FULL_THRESH_NEGATE_VAL": [ { "value": "1021", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_FULL_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_RD_DATA_COUNT_WIDTH": [ { "value": "10", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_RD_DEPTH": [ { "value": "1024", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_RD_FREQ": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_RD_PNTR_WIDTH": [ { "value": "10", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_UNDERFLOW_LOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_DOUT_RST": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_ECC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_EMBEDDED_REG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_PIPELINE_REG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_POWER_SAVING_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_FIFO16_FLAGS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_FWFT_DATA_COUNT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_VALID_LOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WR_ACK_LOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WR_DATA_COUNT_WIDTH": [ { "value": "10", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WR_DEPTH": [ { "value": "1024", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WR_FREQ": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WR_PNTR_WIDTH": [ { "value": "10", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WR_RESPONSE_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MSGON_VAL": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ENABLE_RST_SYNC": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_EN_SAFETY_CKT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ERROR_INJECTION_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_SYNCHRONIZER_STAGE": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_INTERFACE_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_AXI_WR_CHANNEL": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_AXI_RD_CHANNEL": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_SLAVE_CE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_MASTER_CE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ADD_NGC_CONSTRAINT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_COMMON_OVERFLOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_COMMON_UNDERFLOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_DEFAULT_SETTINGS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_ID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_DATA_WIDTH": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_LEN_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_LOCK_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_AXI_ID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_AXI_AWUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_AXI_WUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_AXI_BUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_AXI_ARUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_AXI_RUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_ARUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_AWUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_WUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_BUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_RUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_AXIS_TDATA": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_AXIS_TID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_AXIS_TDEST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_AXIS_TUSER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_AXIS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_AXIS_TLAST": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_AXIS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_AXIS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXIS_TDATA_WIDTH": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXIS_TID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXIS_TDEST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXIS_TUSER_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXIS_TSTRB_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXIS_TKEEP_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WACH_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WDCH_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WRCH_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_RACH_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_RDCH_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXIS_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_IMPLEMENTATION_TYPE_WACH": [ { "value": "12", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_IMPLEMENTATION_TYPE_WDCH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_IMPLEMENTATION_TYPE_WRCH": [ { "value": "12", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_IMPLEMENTATION_TYPE_RACH": [ { "value": "12", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_IMPLEMENTATION_TYPE_RDCH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_IMPLEMENTATION_TYPE_AXIS": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_APPLICATION_TYPE_WACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_APPLICATION_TYPE_WDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_APPLICATION_TYPE_WRCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_APPLICATION_TYPE_RACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_APPLICATION_TYPE_RDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_APPLICATION_TYPE_AXIS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PRIM_FIFO_TYPE_WACH": [ { "value": "512x36", "resolve_type": "generated", "usage": "all" } ],
+        "C_PRIM_FIFO_TYPE_WDCH": [ { "value": "1kx36", "resolve_type": "generated", "usage": "all" } ],
+        "C_PRIM_FIFO_TYPE_WRCH": [ { "value": "512x36", "resolve_type": "generated", "usage": "all" } ],
+        "C_PRIM_FIFO_TYPE_RACH": [ { "value": "512x36", "resolve_type": "generated", "usage": "all" } ],
+        "C_PRIM_FIFO_TYPE_RDCH": [ { "value": "1kx36", "resolve_type": "generated", "usage": "all" } ],
+        "C_PRIM_FIFO_TYPE_AXIS": [ { "value": "1kx36", "resolve_type": "generated", "usage": "all" } ],
+        "C_USE_ECC_WACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_ECC_WDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_ECC_WRCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_ECC_RACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_ECC_RDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_ECC_AXIS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ERROR_INJECTION_TYPE_WACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ERROR_INJECTION_TYPE_WDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ERROR_INJECTION_TYPE_WRCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ERROR_INJECTION_TYPE_RACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ERROR_INJECTION_TYPE_RDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ERROR_INJECTION_TYPE_AXIS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DIN_WIDTH_WACH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DIN_WIDTH_WDCH": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DIN_WIDTH_WRCH": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DIN_WIDTH_RACH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DIN_WIDTH_RDCH": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DIN_WIDTH_AXIS": [ { "value": "69", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WR_DEPTH_WACH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WR_DEPTH_WDCH": [ { "value": "1024", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WR_DEPTH_WRCH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WR_DEPTH_RACH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WR_DEPTH_RDCH": [ { "value": "1024", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WR_DEPTH_AXIS": [ { "value": "1024", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WR_PNTR_WIDTH_WACH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WR_PNTR_WIDTH_WDCH": [ { "value": "10", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WR_PNTR_WIDTH_WRCH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WR_PNTR_WIDTH_RACH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WR_PNTR_WIDTH_RDCH": [ { "value": "10", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WR_PNTR_WIDTH_AXIS": [ { "value": "10", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_DATA_COUNTS_WACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_DATA_COUNTS_WDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_DATA_COUNTS_WRCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_DATA_COUNTS_RACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_DATA_COUNTS_RDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_DATA_COUNTS_AXIS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_PROG_FLAGS_WACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_PROG_FLAGS_WDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_PROG_FLAGS_WRCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_PROG_FLAGS_RACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_PROG_FLAGS_RDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_PROG_FLAGS_AXIS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_FULL_TYPE_WACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_FULL_TYPE_WDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_FULL_TYPE_WRCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_FULL_TYPE_RACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_FULL_TYPE_RDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_FULL_TYPE_AXIS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_FULL_THRESH_ASSERT_VAL_WACH": [ { "value": "15", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_FULL_THRESH_ASSERT_VAL_WDCH": [ { "value": "1023", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_FULL_THRESH_ASSERT_VAL_WRCH": [ { "value": "15", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_FULL_THRESH_ASSERT_VAL_RACH": [ { "value": "15", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_FULL_THRESH_ASSERT_VAL_RDCH": [ { "value": "1023", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_FULL_THRESH_ASSERT_VAL_AXIS": [ { "value": "1023", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_EMPTY_TYPE_WACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_EMPTY_TYPE_WDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_EMPTY_TYPE_WRCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_EMPTY_TYPE_RACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_EMPTY_TYPE_RDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_EMPTY_TYPE_AXIS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH": [ { "value": "13", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH": [ { "value": "1021", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH": [ { "value": "13", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH": [ { "value": "13", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH": [ { "value": "1021", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS": [ { "value": "1021", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_REG_SLICE_MODE_WACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_REG_SLICE_MODE_WDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_REG_SLICE_MODE_WRCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_REG_SLICE_MODE_RACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_REG_SLICE_MODE_RDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_REG_SLICE_MODE_AXIS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "zynq" } ],
+        "BASE_BOARD_PART": [ { "value": "xilinx.com:zc706:part0:1.4" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xc7z045" } ],
+        "NEXTGEN_VERSAL": [ { "value": "0" } ],
+        "PACKAGE": [ { "value": "ffg900" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Integrator" } ],
+        "IPREVISION": [ { "value": "10" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../../../project_fix_dac.gen/sources_1/bd/system_top/ip/system_top_fifo_generator_2_0" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "../../ipshared" } ],
+        "SWVERSION": [ { "value": "2024.1" } ],
+        "SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "wr_rst_busy": [ { "direction": "out", "driver_value": "0" } ],
+        "rd_rst_busy": [ { "direction": "out", "driver_value": "0" } ],
+        "m_aclk": [ { "direction": "in", "driver_value": "0" } ],
+        "s_aclk": [ { "direction": "in", "driver_value": "0" } ],
+        "s_aresetn": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axis_tvalid": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axis_tready": [ { "direction": "out", "driver_value": "0x0" } ],
+        "s_axis_tdata": [ { "direction": "in", "size_left": "63", "size_right": "0", "driver_value": "0" } ],
+        "s_axis_tlast": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axis_tuser": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
+        "m_axis_tvalid": [ { "direction": "out", "driver_value": "0x0" } ],
+        "m_axis_tready": [ { "direction": "in", "driver_value": "0" } ],
+        "m_axis_tdata": [ { "direction": "out", "size_left": "63", "size_right": "0", "driver_value": "0" } ],
+        "m_axis_tlast": [ { "direction": "out", "driver_value": "0x0" } ],
+        "m_axis_tuser": [ { "direction": "out", "size_left": "3", "size_right": "0", "driver_value": "0" } ]
+      },
+      "interfaces": {
+        "M_AXIS": {
+          "vlnv": "xilinx.com:interface:axis:1.0",
+          "abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "TDATA_NUM_BYTES": [ { "value": "8", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TDEST_WIDTH": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TID_WIDTH": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TUSER_WIDTH": [ { "value": "4", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TREADY": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TSTRB": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TKEEP": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TLAST": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "200000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_top_mig_7series_0_0_ui_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "TDATA": [ { "physical_name": "m_axis_tdata" } ],
+            "TLAST": [ { "physical_name": "m_axis_tlast" } ],
+            "TREADY": [ { "physical_name": "m_axis_tready" } ],
+            "TUSER": [ { "physical_name": "m_axis_tuser" } ],
+            "TVALID": [ { "physical_name": "m_axis_tvalid" } ]
+          }
+        },
+        "S_AXIS": {
+          "vlnv": "xilinx.com:interface:axis:1.0",
+          "abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "TDATA_NUM_BYTES": [ { "value": "8", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TDEST_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TID_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TUSER_WIDTH": [ { "value": "4", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TREADY": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TSTRB": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TKEEP": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TLAST": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_top_data_clk_2", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "TDATA": [ { "physical_name": "s_axis_tdata" } ],
+            "TLAST": [ { "physical_name": "s_axis_tlast" } ],
+            "TREADY": [ { "physical_name": "s_axis_tready" } ],
+            "TUSER": [ { "physical_name": "s_axis_tuser" } ],
+            "TVALID": [ { "physical_name": "s_axis_tvalid" } ]
+          }
+        },
+        "master_aclk": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "M_AXIS:M_AXI", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "200000000", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_top_mig_7series_0_0_ui_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "m_aclk" } ]
+          }
+        },
+        "slave_aclk": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "S_AXIS:S_AXI", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "s_aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_top_data_clk_2", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "s_aclk" } ]
+          }
+        },
+        "slave_aresetn": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "s_aresetn" } ]
+          }
+        }
+      }
+    }
+  }
+}

cx9261a_demo_cmos_20240829/project_fix_dac.srcs/sources_1/bd/system_top/ip/system_top_mig_7series_0_0/board.prj

@@ -0,0 +1,203 @@
+<?xml version='1.0' encoding='UTF-8'?>
+<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->
+<Project NoOfControllers="1" >
+    <ModuleName>design_1_mig_7series_1_0</ModuleName>
+    <dci_inouts_inputs>1</dci_inouts_inputs>
+    <dci_inputs>1</dci_inputs>
+    <Debug_En>OFF</Debug_En>
+    <DataDepth_En>1024</DataDepth_En>
+    <LowPower_En>ON</LowPower_En>
+    <XADC_En>Enabled</XADC_En>
+    <TargetFPGA>xc7z045-ffg900/-2</TargetFPGA>
+    <Version>1.9</Version>
+    <SystemClock>Differential</SystemClock>
+    <ReferenceClock>Use System Clock</ReferenceClock>
+    <SysResetPolarity>ACTIVE HIGH</SysResetPolarity>
+    <BankSelectionFlag>FALSE</BankSelectionFlag>
+    <InternalVref>0</InternalVref>
+    <dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs>
+    <dci_cascade>1</dci_cascade>
+    <Controller number="0" >
+        <MemoryDevice>DDR3_SDRAM/SODIMMs/MT8JTF12864HZ-1G6</MemoryDevice>
+        <TimePeriod>1250</TimePeriod>
+        <VccAuxIO>1.8V</VccAuxIO>
+        <PHYRatio>4:1</PHYRatio>
+        <InputClkFreq>200</InputClkFreq>
+        <UIExtraClocks>1</UIExtraClocks>
+        <MMCMClkOut0> 8.000</MMCMClkOut0>
+        <MMCMClkOut1>1</MMCMClkOut1>
+        <MMCMClkOut2>1</MMCMClkOut2>
+        <MMCMClkOut3>1</MMCMClkOut3>
+        <MMCMClkOut4>1</MMCMClkOut4>
+        <DataWidth>64</DataWidth>
+        <DeepMemory>1</DeepMemory>
+        <DataMask>1</DataMask>
+        <ECC>Disabled</ECC>
+        <Ordering>Normal</Ordering>
+        <CustomPart>FALSE</CustomPart>
+        <NewPartName></NewPartName>
+        <RowAddress>14</RowAddress>
+        <ColAddress>10</ColAddress>
+        <BankAddress>3</BankAddress>
+        <MemoryVoltage>1.5V</MemoryVoltage>
+        <UserMemoryAddressMap>BANK_ROW_COLUMN</UserMemoryAddressMap>
+        <PinSelection>
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="E10" SLEW="FAST" name="ddr3_addr[0]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="D6" SLEW="FAST" name="ddr3_addr[10]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="B7" SLEW="FAST" name="ddr3_addr[11]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="H12" SLEW="FAST" name="ddr3_addr[12]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="A10" SLEW="FAST" name="ddr3_addr[13]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="B9" SLEW="FAST" name="ddr3_addr[1]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="E11" SLEW="FAST" name="ddr3_addr[2]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="A9" SLEW="FAST" name="ddr3_addr[3]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="D11" SLEW="FAST" name="ddr3_addr[4]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="B6" SLEW="FAST" name="ddr3_addr[5]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="F9" SLEW="FAST" name="ddr3_addr[6]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="E8" SLEW="FAST" name="ddr3_addr[7]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="B10" SLEW="FAST" name="ddr3_addr[8]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="J8" SLEW="FAST" name="ddr3_addr[9]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="F8" SLEW="FAST" name="ddr3_ba[0]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="H7" SLEW="FAST" name="ddr3_ba[1]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="A7" SLEW="FAST" name="ddr3_ba[2]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="E7" SLEW="FAST" name="ddr3_cas_n" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15" PADName="F10" SLEW="FAST" name="ddr3_ck_n[0]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15" PADName="G10" SLEW="FAST" name="ddr3_ck_p[0]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="D10" SLEW="FAST" name="ddr3_cke[0]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="J11" SLEW="FAST" name="ddr3_cs_n[0]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="J3" SLEW="FAST" name="ddr3_dm[0]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="F2" SLEW="FAST" name="ddr3_dm[1]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="E1" SLEW="FAST" name="ddr3_dm[2]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="C2" SLEW="FAST" name="ddr3_dm[3]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="L12" SLEW="FAST" name="ddr3_dm[4]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="G14" SLEW="FAST" name="ddr3_dm[5]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="C16" SLEW="FAST" name="ddr3_dm[6]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="C11" SLEW="FAST" name="ddr3_dm[7]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="L1" SLEW="FAST" name="ddr3_dq[0]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="H6" SLEW="FAST" name="ddr3_dq[10]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="H3" SLEW="FAST" name="ddr3_dq[11]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="G1" SLEW="FAST" name="ddr3_dq[12]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="H2" SLEW="FAST" name="ddr3_dq[13]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="G5" SLEW="FAST" name="ddr3_dq[14]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="G4" SLEW="FAST" name="ddr3_dq[15]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="E2" SLEW="FAST" name="ddr3_dq[16]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="E3" SLEW="FAST" name="ddr3_dq[17]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="D4" SLEW="FAST" name="ddr3_dq[18]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="E5" SLEW="FAST" name="ddr3_dq[19]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="L2" SLEW="FAST" name="ddr3_dq[1]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="F4" SLEW="FAST" name="ddr3_dq[20]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="F3" SLEW="FAST" name="ddr3_dq[21]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="D1" SLEW="FAST" name="ddr3_dq[22]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="D3" SLEW="FAST" name="ddr3_dq[23]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="A2" SLEW="FAST" name="ddr3_dq[24]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="B2" SLEW="FAST" name="ddr3_dq[25]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="B4" SLEW="FAST" name="ddr3_dq[26]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="B5" SLEW="FAST" name="ddr3_dq[27]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="A3" SLEW="FAST" name="ddr3_dq[28]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="B1" SLEW="FAST" name="ddr3_dq[29]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="K5" SLEW="FAST" name="ddr3_dq[2]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="C1" SLEW="FAST" name="ddr3_dq[30]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="C4" SLEW="FAST" name="ddr3_dq[31]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="K10" SLEW="FAST" name="ddr3_dq[32]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="L9" SLEW="FAST" name="ddr3_dq[33]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="K12" SLEW="FAST" name="ddr3_dq[34]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="J9" SLEW="FAST" name="ddr3_dq[35]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="K11" SLEW="FAST" name="ddr3_dq[36]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="L10" SLEW="FAST" name="ddr3_dq[37]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="J10" SLEW="FAST" name="ddr3_dq[38]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="L7" SLEW="FAST" name="ddr3_dq[39]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="J4" SLEW="FAST" name="ddr3_dq[3]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="F14" SLEW="FAST" name="ddr3_dq[40]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="F15" SLEW="FAST" name="ddr3_dq[41]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="F13" SLEW="FAST" name="ddr3_dq[42]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="G16" SLEW="FAST" name="ddr3_dq[43]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="G15" SLEW="FAST" name="ddr3_dq[44]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="E12" SLEW="FAST" name="ddr3_dq[45]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="D13" SLEW="FAST" name="ddr3_dq[46]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="E13" SLEW="FAST" name="ddr3_dq[47]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="D15" SLEW="FAST" name="ddr3_dq[48]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="E15" SLEW="FAST" name="ddr3_dq[49]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="K1" SLEW="FAST" name="ddr3_dq[4]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="D16" SLEW="FAST" name="ddr3_dq[50]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="E16" SLEW="FAST" name="ddr3_dq[51]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="C17" SLEW="FAST" name="ddr3_dq[52]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="B16" SLEW="FAST" name="ddr3_dq[53]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="D14" SLEW="FAST" name="ddr3_dq[54]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="B17" SLEW="FAST" name="ddr3_dq[55]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="B12" SLEW="FAST" name="ddr3_dq[56]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="C12" SLEW="FAST" name="ddr3_dq[57]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="A12" SLEW="FAST" name="ddr3_dq[58]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="A14" SLEW="FAST" name="ddr3_dq[59]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="L3" SLEW="FAST" name="ddr3_dq[5]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="A13" SLEW="FAST" name="ddr3_dq[60]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="B11" SLEW="FAST" name="ddr3_dq[61]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="C14" SLEW="FAST" name="ddr3_dq[62]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="B14" SLEW="FAST" name="ddr3_dq[63]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="J5" SLEW="FAST" name="ddr3_dq[6]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="K6" SLEW="FAST" name="ddr3_dq[7]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="G6" SLEW="FAST" name="ddr3_dq[8]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="H4" SLEW="FAST" name="ddr3_dq[9]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="K2" SLEW="FAST" name="ddr3_dqs_n[0]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="H1" SLEW="FAST" name="ddr3_dqs_n[1]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="D5" SLEW="FAST" name="ddr3_dqs_n[2]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="A4" SLEW="FAST" name="ddr3_dqs_n[3]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="K8" SLEW="FAST" name="ddr3_dqs_n[4]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="F12" SLEW="FAST" name="ddr3_dqs_n[5]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="E17" SLEW="FAST" name="ddr3_dqs_n[6]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="A15" SLEW="FAST" name="ddr3_dqs_n[7]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="K3" SLEW="FAST" name="ddr3_dqs_p[0]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="J1" SLEW="FAST" name="ddr3_dqs_p[1]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="E6" SLEW="FAST" name="ddr3_dqs_p[2]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="A5" SLEW="FAST" name="ddr3_dqs_p[3]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="L8" SLEW="FAST" name="ddr3_dqs_p[4]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="G12" SLEW="FAST" name="ddr3_dqs_p[5]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="F17" SLEW="FAST" name="ddr3_dqs_p[6]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="B15" SLEW="FAST" name="ddr3_dqs_p[7]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="G7" SLEW="FAST" name="ddr3_odt[0]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="H11" SLEW="FAST" name="ddr3_ras_n" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="LVCMOS15" PADName="G17" SLEW="FAST" name="ddr3_reset_n" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="F7" SLEW="FAST" name="ddr3_we_n" IN_TERM="" />
+            <Pin VCCAUX_IO="DONTCARE" IOSTANDARD="DIFF_SSTL15" PADName="G9" SLEW="" name="sys_clk_n" IN_TERM="" />
+            <Pin VCCAUX_IO="DONTCARE" IOSTANDARD="DIFF_SSTL15" PADName="H9" SLEW="" name="sys_clk_p" IN_TERM="" />
+        </PinSelection>
+        <System_Clock>
+            <Pin PADName="H9/G9(CC_P/N)" Bank="34" name="sys_clk_p/n" />
+        </System_Clock>
+        <System_Control>
+            <Pin PADName="No connect" Bank="Select Bank" name="sys_rst" />
+            <Pin PADName="No connect" Bank="Select Bank" name="init_calib_complete" />
+            <Pin PADName="No connect" Bank="Select Bank" name="tg_compare_error" />
+        </System_Control>
+        <TimingParameters>
+            <Parameters twtr="7.5" trrd="6" trefi="7.8" tfaw="30" trtp="7.5" tcke="5" trfc="110" trp="13.125" tras="35" trcd="13.125" />
+        </TimingParameters>
+        <mrBurstLength name="Burst Length" >8 - Fixed</mrBurstLength>
+        <mrBurstType name="Read Burst Type and Length" >Sequential</mrBurstType>
+        <mrCasLatency name="CAS Latency" >6</mrCasLatency>
+        <mrMode name="Mode" >Normal</mrMode>
+        <mrDllReset name="DLL Reset" >No</mrDllReset>
+        <mrPdMode name="DLL control for precharge PD" >Slow Exit</mrPdMode>
+        <emrDllEnable name="DLL Enable" >Enable</emrDllEnable>
+        <emrOutputDriveStrength name="Output Driver Impedance Control" >RZQ/7</emrOutputDriveStrength>
+        <emrMirrorSelection name="Address Mirroring" >Disable</emrMirrorSelection>
+        <emrCSSelection name="Controller Chip Select Pin" >Enable</emrCSSelection>
+        <emrRTT name="RTT (nominal) - On Die Termination (ODT)" >RZQ/6</emrRTT>
+        <emrPosted name="Additive Latency (AL)" >0</emrPosted>
+        <emrOCD name="Write Leveling Enable" >Disabled</emrOCD>
+        <emrDQS name="TDQS enable" >Enabled</emrDQS>
+        <emrRDQS name="Qoff" >Output Buffer Enabled</emrRDQS>
+        <mr2PartialArraySelfRefresh name="Partial-Array Self Refresh" >Full Array</mr2PartialArraySelfRefresh>
+        <mr2CasWriteLatency name="CAS write latency" >5</mr2CasWriteLatency>
+        <mr2AutoSelfRefresh name="Auto Self Refresh" >Enabled</mr2AutoSelfRefresh>
+        <mr2SelfRefreshTempRange name="High Temparature Self Refresh Rate" >Normal</mr2SelfRefreshTempRange>
+        <mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)" >Dynamic ODT off</mr2RTTWR>
+        <PortInterface>AXI</PortInterface>
+        <AXIParameters>
+            <C0_C_RD_WR_ARB_ALGORITHM>RD_PRI_REG</C0_C_RD_WR_ARB_ALGORITHM>
+            <C0_S_AXI_ADDR_WIDTH>32</C0_S_AXI_ADDR_WIDTH>
+            <C0_S_AXI_DATA_WIDTH>512</C0_S_AXI_DATA_WIDTH>
+            <C0_S_AXI_ID_WIDTH>2</C0_S_AXI_ID_WIDTH>
+            <C0_S_AXI_SUPPORTS_NARROW_BURST>0</C0_S_AXI_SUPPORTS_NARROW_BURST>
+        </AXIParameters>
+    </Controller>
+
+</Project>

cx9261a_demo_cmos_20240829/project_fix_dac.srcs/sources_1/bd/system_top/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0.veo

@@ -0,0 +1,160 @@
+//*****************************************************************************␍␍
+// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.␍␍
+//␍␍
+// This file contains confidential and proprietary information␍␍
+// of Xilinx, Inc. and is protected under U.S. and␍␍
+// international copyright and other intellectual property␍␍
+// laws.␍␍
+//␍␍
+// DISCLAIMER␍␍
+// This disclaimer is not a license and does not grant any␍␍
+// rights to the materials distributed herewith. Except as␍␍
+// otherwise provided in a valid license issued to you by␍␍
+// Xilinx, and to the maximum extent permitted by applicable␍␍
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND␍␍
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES␍␍
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING␍␍
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-␍␍
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and␍␍
+// (2) Xilinx shall not be liable (whether in contract or tort,␍␍
+// including negligence, or under any other theory of␍␍
+// liability) for any loss or damage of any kind or nature␍␍
+// related to, arising under or in connection with these␍␍
+// materials, including for any direct, or any indirect,␍␍
+// special, incidental, or consequential loss or damage␍␍
+// (including loss of data, profits, goodwill, or any type of␍␍
+// loss or damage suffered as a result of any action brought␍␍
+// by a third party) even if such damage or loss was␍␍
+// reasonably foreseeable or Xilinx had been advised of the␍␍
+// possibility of the same.␍␍
+//␍␍
+// CRITICAL APPLICATIONS␍␍
+// Xilinx products are not designed or intended to be fail-␍␍
+// safe, or for use in any application requiring fail-safe␍␍
+// performance, such as life-support or safety devices or␍␍
+// systems, Class III medical devices, nuclear facilities,␍␍
+// applications related to the deployment of airbags, or any␍␍
+// other applications that could lead to death, personal␍␍
+// injury, or severe property or environmental damage␍␍
+// (individually and collectively, "Critical␍␍
+// Applications"). Customer assumes the sole risk and␍␍
+// liability of any use of Xilinx products in Critical␍␍
+// Applications, subject only to applicable laws and␍␍
+// regulations governing limitations on product liability.␍␍
+//␍␍
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS␍␍
+// PART OF THIS FILE AT ALL TIMES.␍␍
+//␍␍
+//*****************************************************************************␍␍
+//   ____  ____␍␍
+//  /   /\/   /␍␍
+// /___/  \  /   Vendor             : Xilinx␍␍
+// \   \   \/    Version            : 4.2␍␍
+//  \   \        Application        : MIG␍␍
+//  /   /        Filename           : system_top_mig_7series_0_0.veo␍␍
+// /___/   /\    Date Last Modified : $Date: 2011/06/02 08:34:47 $␍␍
+// \   \  /  \   Date Created       : Tue Sept 21 2010␍␍
+//  \___\/\___\␍␍
+//␍␍
+// Device           : 7 Series␍␍
+// Design Name      : DDR3 SDRAM␍␍
+// Purpose          : Template file containing code that can be used as a model␍␍
+//                    for instantiating a CORE Generator module in a HDL design.␍␍
+// Revision History :␍␍
+//*****************************************************************************␍␍
+␍␍
+// The following must be inserted into your Verilog file for this␍␍
+// core to be instantiated. Change the instance name and port connections␍␍
+// (in parentheses) to your own signal names.␍␍
+␍␍
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG␍␍
+␍␍
+  system_top_mig_7series_0_0 u_system_top_mig_7series_0_0 (␍␍
+␍␍
+    // Memory interface ports␍␍
+    .ddr3_addr                      (ddr3_addr),  // output [13:0]		ddr3_addr␍␍
+    .ddr3_ba                        (ddr3_ba),  // output [2:0]		ddr3_ba␍␍
+    .ddr3_cas_n                     (ddr3_cas_n),  // output			ddr3_cas_n␍␍
+    .ddr3_ck_n                      (ddr3_ck_n),  // output [0:0]		ddr3_ck_n␍␍
+    .ddr3_ck_p                      (ddr3_ck_p),  // output [0:0]		ddr3_ck_p␍␍
+    .ddr3_cke                       (ddr3_cke),  // output [0:0]		ddr3_cke␍␍
+    .ddr3_ras_n                     (ddr3_ras_n),  // output			ddr3_ras_n␍␍
+    .ddr3_reset_n                   (ddr3_reset_n),  // output			ddr3_reset_n␍␍
+    .ddr3_we_n                      (ddr3_we_n),  // output			ddr3_we_n␍␍
+    .ddr3_dq                        (ddr3_dq),  // inout [63:0]		ddr3_dq␍␍
+    .ddr3_dqs_n                     (ddr3_dqs_n),  // inout [7:0]		ddr3_dqs_n␍␍
+    .ddr3_dqs_p                     (ddr3_dqs_p),  // inout [7:0]		ddr3_dqs_p␍␍
+    .init_calib_complete            (init_calib_complete),  // output			init_calib_complete␍␍
+      ␍␍
+	.ddr3_cs_n                      (ddr3_cs_n),  // output [0:0]		ddr3_cs_n␍␍
+    .ddr3_dm                        (ddr3_dm),  // output [7:0]		ddr3_dm␍␍
+    .ddr3_odt                       (ddr3_odt),  // output [0:0]		ddr3_odt␍␍
+    // Application interface ports␍␍
+    .ui_clk                         (ui_clk),  // output			ui_clk␍␍
+    .ui_clk_sync_rst                (ui_clk_sync_rst),  // output			ui_clk_sync_rst␍␍
+    .ui_addn_clk_0                  (ui_addn_clk_0),  // output			ui_addn_clk_0␍␍
+    .ui_addn_clk_1                  (ui_addn_clk_1),  // output			ui_addn_clk_1␍␍
+    .ui_addn_clk_2                  (ui_addn_clk_2),  // output			ui_addn_clk_2␍␍
+    .ui_addn_clk_3                  (ui_addn_clk_3),  // output			ui_addn_clk_3␍␍
+    .ui_addn_clk_4                  (ui_addn_clk_4),  // output			ui_addn_clk_4␍␍
+    .mmcm_locked                    (mmcm_locked),  // output			mmcm_locked␍␍
+    .aresetn                        (aresetn),  // input			aresetn␍␍
+    .app_sr_active                  (app_sr_active),  // output			app_sr_active␍␍
+    .app_ref_ack                    (app_ref_ack),  // output			app_ref_ack␍␍
+    .app_zq_ack                     (app_zq_ack),  // output			app_zq_ack␍␍
+    // Slave Interface Write Address Ports␍␍
+    .s_axi_awid                     (s_axi_awid),  // input [1:0]			s_axi_awid␍␍
+    .s_axi_awaddr                   (s_axi_awaddr),  // input [31:0]			s_axi_awaddr␍␍
+    .s_axi_awlen                    (s_axi_awlen),  // input [7:0]			s_axi_awlen␍␍
+    .s_axi_awsize                   (s_axi_awsize),  // input [2:0]			s_axi_awsize␍␍
+    .s_axi_awburst                  (s_axi_awburst),  // input [1:0]			s_axi_awburst␍␍
+    .s_axi_awlock                   (s_axi_awlock),  // input [0:0]			s_axi_awlock␍␍
+    .s_axi_awcache                  (s_axi_awcache),  // input [3:0]			s_axi_awcache␍␍
+    .s_axi_awprot                   (s_axi_awprot),  // input [2:0]			s_axi_awprot␍␍
+    .s_axi_awqos                    (s_axi_awqos),  // input [3:0]			s_axi_awqos␍␍
+    .s_axi_awvalid                  (s_axi_awvalid),  // input			s_axi_awvalid␍␍
+    .s_axi_awready                  (s_axi_awready),  // output			s_axi_awready␍␍
+    // Slave Interface Write Data Ports␍␍
+    .s_axi_wdata                    (s_axi_wdata),  // input [511:0]			s_axi_wdata␍␍
+    .s_axi_wstrb                    (s_axi_wstrb),  // input [63:0]			s_axi_wstrb␍␍
+    .s_axi_wlast                    (s_axi_wlast),  // input			s_axi_wlast␍␍
+    .s_axi_wvalid                   (s_axi_wvalid),  // input			s_axi_wvalid␍␍
+    .s_axi_wready                   (s_axi_wready),  // output			s_axi_wready␍␍
+    // Slave Interface Write Response Ports␍␍
+    .s_axi_bid                      (s_axi_bid),  // output [1:0]			s_axi_bid␍␍
+    .s_axi_bresp                    (s_axi_bresp),  // output [1:0]			s_axi_bresp␍␍
+    .s_axi_bvalid                   (s_axi_bvalid),  // output			s_axi_bvalid␍␍
+    .s_axi_bready                   (s_axi_bready),  // input			s_axi_bready␍␍
+    // Slave Interface Read Address Ports␍␍
+    .s_axi_arid                     (s_axi_arid),  // input [1:0]			s_axi_arid␍␍
+    .s_axi_araddr                   (s_axi_araddr),  // input [31:0]			s_axi_araddr␍␍
+    .s_axi_arlen                    (s_axi_arlen),  // input [7:0]			s_axi_arlen␍␍
+    .s_axi_arsize                   (s_axi_arsize),  // input [2:0]			s_axi_arsize␍␍
+    .s_axi_arburst                  (s_axi_arburst),  // input [1:0]			s_axi_arburst␍␍
+    .s_axi_arlock                   (s_axi_arlock),  // input [0:0]			s_axi_arlock␍␍
+    .s_axi_arcache                  (s_axi_arcache),  // input [3:0]			s_axi_arcache␍␍
+    .s_axi_arprot                   (s_axi_arprot),  // input [2:0]			s_axi_arprot␍␍
+    .s_axi_arqos                    (s_axi_arqos),  // input [3:0]			s_axi_arqos␍␍
+    .s_axi_arvalid                  (s_axi_arvalid),  // input			s_axi_arvalid␍␍
+    .s_axi_arready                  (s_axi_arready),  // output			s_axi_arready␍␍
+    // Slave Interface Read Data Ports␍␍
+    .s_axi_rid                      (s_axi_rid),  // output [1:0]			s_axi_rid␍␍
+    .s_axi_rdata                    (s_axi_rdata),  // output [511:0]			s_axi_rdata␍␍
+    .s_axi_rresp                    (s_axi_rresp),  // output [1:0]			s_axi_rresp␍␍
+    .s_axi_rlast                    (s_axi_rlast),  // output			s_axi_rlast␍␍
+    .s_axi_rvalid                   (s_axi_rvalid),  // output			s_axi_rvalid␍␍
+    .s_axi_rready                   (s_axi_rready),  // input			s_axi_rready␍␍
+    // System Clock Ports␍␍
+    .sys_clk_p                       (sys_clk_p),  // input				sys_clk_p␍␍
+    .sys_clk_n                       (sys_clk_n),  // input				sys_clk_n␍␍
+    .sys_rst                        (sys_rst) // input sys_rst␍␍
+    );␍␍
+␍␍
+// INST_TAG_END ------ End INSTANTIATION Template ---------␍␍
+␍␍
+// You must compile the wrapper file system_top_mig_7series_0_0.v when simulating␍␍
+// the core, system_top_mig_7series_0_0. When compiling the wrapper file, be sure to␍␍
+// reference the XilinxCoreLib Verilog simulation library. For detailed␍␍
+// instructions, please refer to the "CORE Generator Help".␍␍
+␍␍
+␍

cx9261a_demo_cmos_20240829/project_fix_dac.srcs/sources_1/bd/system_top/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/datasheet.txt

@@ -0,0 +1,133 @@
+␍
+␍
+Vivado Project Options:␍
+   Target Device                   : xc7z045-ffg900␍
+   Speed Grade                     : -2␍
+   HDL                             : verilog␍
+   Synthesis Tool                  : VIVADO␍
+␍
+MIG Output Options:␍
+   Module Name                     : system_top_mig_7series_0_0␍
+   No of Controllers               : 1␍
+   Selected Compatible Device(s)   : --␍
+␍
+FPGA Options:␍
+   System Clock Type               : Differential␍
+   Reference Clock Type            : Use System Clock␍
+   Debug Port                      : OFF␍
+   Internal Vref                   : disabled␍
+   IO Power Reduction              : ON␍
+   XADC instantiation in MIG       : Enabled␍
+␍
+Extended FPGA Options:␍
+   DCI for DQ,DQS/DQS#,DM          : enabled␍
+   Internal Termination (HR Banks) : 50 Ohms␍
+    ␍
+␍
+/*******************************************************/␍
+␍
+/*                  Controller 0                       */␍
+␍
+/*******************************************************/␍
+␍
+Controller Options :␍
+␍
+   Memory                        : DDR3_SDRAM␍
+␍
+   Interface                     : AXI␍
+␍
+   Design Clock Frequency        : 1250 ps (  0.00 MHz)␍
+␍
+   Phy to Controller Clock Ratio : 4:1␍
+␍
+   Input Clock Period            : 5000 ps␍
+␍
+   CLKFBOUT_MULT (PLL)           : 8␍
+␍
+   DIVCLK_DIVIDE (PLL)           : 1␍
+␍
+   VCC_AUX IO                    : 1.8V␍
+␍
+   Memory Type                   : SODIMMs␍
+␍
+   Memory Part                   : MT8JTF12864HZ-1G6␍
+␍
+   Equivalent Part(s)            : --␍
+␍
+   Data Width                    : 64␍
+␍
+   ECC                           : Disabled␍
+␍
+   Data Mask                     : enabled␍
+␍
+   ORDERING                      : Normal␍
+␍
+␍
+␍
+AXI Parameters :␍
+␍
+   Data Width                    : 512␍
+␍
+   Arbitration Scheme            : RD_PRI_REG␍
+␍
+   Narrow Burst Support          : 0␍
+␍
+   ID Width                      : 2␍
+␍
+␍
+␍
+Memory Options:␍
+␍
+   Burst Length (MR0[1:0])          : 8 - Fixed␍
+␍
+   Read Burst Type (MR0[3])         : Sequential␍
+␍
+   CAS Latency (MR0[6:4])           : 11␍
+␍
+   Output Drive Strength (MR1[5,1]) : RZQ/7␍
+␍
+   Controller CS option             : Enable␍
+␍
+   Rtt_NOM - ODT (MR1[9,6,2])       : RZQ/6␍
+␍
+   Rtt_WR - Dynamic ODT (MR2[10:9]) : Dynamic ODT off␍
+␍
+   Memory Address Mapping           : BANK_ROW_COLUMN␍
+␍
+␍
+␍
+␍
+Bank Selections:␍
+	Bank: 33␍
+		Byte Group T0:	DQ[0-7]␍
+		Byte Group T1:	DQ[8-15]␍
+		Byte Group T2:	DQ[16-23]␍
+		Byte Group T3:	DQ[24-31]␍
+	Bank: 34␍
+		Byte Group T0:	Address/Ctrl-2␍
+		Byte Group T1:	Address/Ctrl-0␍
+		Byte Group T2:	Address/Ctrl-1␍
+		Byte Group T3:	DQ[32-39]␍
+	Bank: 35␍
+		Byte Group T1:	DQ[40-47]␍
+		Byte Group T2:	DQ[48-55]␍
+		Byte Group T3:	DQ[56-63]␍
+␍
+␍
+System_Clock: ␍
+	SignalName: sys_clk_p/n␍
+		PadLocation: H9/G9(CC_P/N)  Bank: 34␍
+␍
+System_Control: ␍
+	SignalName: sys_rst␍
+		PadLocation: No connect  Bank: Select Bank␍
+	SignalName: init_calib_complete␍
+		PadLocation: No connect  Bank: Select Bank␍
+	SignalName: tg_compare_error␍
+		PadLocation: No connect  Bank: Select Bank␍
+␍
+␍
+␍
+␍
+␍
+    ␍

cx9261a_demo_cmos_20240829/project_fix_dac.srcs/sources_1/bd/system_top/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/docs/phy_only_support_readme.txt

@@ -0,0 +1,12 @@
+This file includes the information about the PHY layer support:
+
+   - Folder "<component name>/user_design/rtl/phy" includes the PHY layer
+     RTL modules.
+   - The top-level PHY module to be instantiated is ddr_phy_top (ddr_phy_top.v)
+   - PHY modules can be used in any environment by taking the RTL modules
+     listed in "phy" folder and PHY layer needs to be connected to
+     the memory controller.
+   - Refer to User Guide (UG586) section "Physical Layer Interface (Non-Memory
+     Controller Design)" for more details on PHY interface signaling,
+     parameter(s) and timing information.
+

cx9261a_demo_cmos_20240829/project_fix_dac.srcs/sources_1/bd/system_top/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/example_design/par/example_top.xdc

@@ -0,0 +1,28 @@
+##################################################################################################␍
+## ␍
+##  Xilinx, Inc. 2010            www.xilinx.com ␍
+##  Tue Apr 23 16:23:00 2024
+␍
+##  Generated by MIG Version 4.2␍
+##  ␍
+##################################################################################################␍
+##  File name :       example_top.xdc␍
+##  Details :     Constraints file␍
+##                    FPGA Family:       ZYNQ␍
+##                    FPGA Part:         XC7Z045-FFG900␍
+##                    Speedgrade:        -2␍
+##                    Design Entry:      VERILOG␍
+##                    Frequency:         800 MHz␍
+##                    Time Period:       1250 ps␍
+##################################################################################################␍
+␍
+##################################################################################################␍
+## Controller 0␍
+## Memory Device: DDR3_SDRAM->SODIMMs->MT8JTF12864HZ-1G6␍
+## Data Width: 64␍
+## Time Period: 1250␍
+## Data Mask: 1␍
+##################################################################################################␍
+############## NET - IOSTANDARD ##################␍
+␍
+␍

cx9261a_demo_cmos_20240829/project_fix_dac.srcs/sources_1/bd/system_top/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/example_design/par/readme.txt

@@ -0,0 +1,18 @@
+Files in PAR folder :␍
+␍
+* "example_top.xdc" file is the constraint file for the design. This is used␍
+  by Vivado. It has clock constraints, location constraints, IO standards ␍
+  and false path/SLICE constraints if any.␍
+␍
+* LTX/probe file is required when programming BIT file to FPGA as it contains␍
+  the information of debug signals like signal name and position with respect␍
+  to ILA/VIO core. The probe file (debug_nets.ltx) is auto generated by ␍
+  vivado tool and is found in <project_name>.runs/impl_1/debug_nets.ltx␍
+␍
+compatible_ucf folder:␍
+␍
+* MIG outputs this folder only when Pin Compatible FPGAs are checked in GUI␍
+  (Pin Compatible FPGAs page in GUI). It generates the XDC files for all␍
+  the Compatible FPGAs selected in GUI. If you want to switch to any of the␍
+  Compatible FPGAs follow the steps mentioned below.␍
+␍

cx9261a_demo_cmos_20240829/project_fix_dac.srcs/sources_1/bd/system_top/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/example_design/rtl/example_top.v

@@ -0,0 +1,735 @@
+//*****************************************************************************␍␍
+// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.␍␍
+//␍␍
+// This file contains confidential and proprietary information␍␍
+// of Xilinx, Inc. and is protected under U.S. and␍␍
+// international copyright and other intellectual property␍␍
+// laws.␍␍
+//␍␍
+// DISCLAIMER␍␍
+// This disclaimer is not a license and does not grant any␍␍
+// rights to the materials distributed herewith. Except as␍␍
+// otherwise provided in a valid license issued to you by␍␍
+// Xilinx, and to the maximum extent permitted by applicable␍␍
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND␍␍
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES␍␍
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING␍␍
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-␍␍
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and␍␍
+// (2) Xilinx shall not be liable (whether in contract or tort,␍␍
+// including negligence, or under any other theory of␍␍
+// liability) for any loss or damage of any kind or nature␍␍
+// related to, arising under or in connection with these␍␍
+// materials, including for any direct, or any indirect,␍␍
+// special, incidental, or consequential loss or damage␍␍
+// (including loss of data, profits, goodwill, or any type of␍␍
+// loss or damage suffered as a result of any action brought␍␍
+// by a third party) even if such damage or loss was␍␍
+// reasonably foreseeable or Xilinx had been advised of the␍␍
+// possibility of the same.␍␍
+//␍␍
+// CRITICAL APPLICATIONS␍␍
+// Xilinx products are not designed or intended to be fail-␍␍
+// safe, or for use in any application requiring fail-safe␍␍
+// performance, such as life-support or safety devices or␍␍
+// systems, Class III medical devices, nuclear facilities,␍␍
+// applications related to the deployment of airbags, or any␍␍
+// other applications that could lead to death, personal␍␍
+// injury, or severe property or environmental damage␍␍
+// (individually and collectively, "Critical␍␍
+// Applications"). Customer assumes the sole risk and␍␍
+// liability of any use of Xilinx products in Critical␍␍
+// Applications, subject only to applicable laws and␍␍
+// regulations governing limitations on product liability.␍␍
+//␍␍
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS␍␍
+// PART OF THIS FILE AT ALL TIMES.␍␍
+//␍␍
+//*****************************************************************************␍␍
+//   ____  ____␍␍
+//  /   /\/   /␍␍
+// /___/  \  /    Vendor             : Xilinx␍␍
+// \   \   \/     Version            : 4.2␍␍
+//  \   \         Application        : MIG␍␍
+//  /   /         Filename           : example_top.v␍␍
+// /___/   /\     Date Last Modified : $Date: 2011/06/02 08:35:03 $␍␍
+// \   \  /  \    Date Created       : Tue Sept 21 2010␍␍
+//  \___\/\___\␍␍
+//␍␍
+// Device           : 7 Series␍␍
+// Design Name      : DDR3 SDRAM␍␍
+// Purpose          :␍␍
+//   Top-level  module. This module serves as an example,␍␍
+//   and allows the user to synthesize a self-contained design,␍␍
+//   which they can be used to test their hardware.␍␍
+//   In addition to the memory controller, the module instantiates:␍␍
+//     1. Synthesizable testbench - used to model user's backend logic␍␍
+//        and generate different traffic patterns␍␍
+// Reference        :␍␍
+// Revision History :␍␍
+//*****************************************************************************␍␍
+␍␍
+//`define SKIP_CALIB␍␍
+`timescale 1ps/1ps␍␍
+␍␍
+module example_top #␍␍
+  (␍␍
+␍␍
+   //***************************************************************************␍␍
+   // Traffic Gen related parameters␍␍
+   //***************************************************************************␍␍
+   parameter BEGIN_ADDRESS         = 32'h00000000,␍␍
+   parameter END_ADDRESS           = 32'h00ffffff,␍␍
+   parameter PRBS_EADDR_MASK_POS   = 32'hff000000,␍␍
+   parameter ENFORCE_RD_WR         = 0,␍␍
+   parameter ENFORCE_RD_WR_CMD     = 8'h11,␍␍
+   parameter ENFORCE_RD_WR_PATTERN = 3'b000,␍␍
+   parameter C_EN_WRAP_TRANS       = 0,␍␍
+   parameter C_AXI_NBURST_TEST     = 0,␍␍
+␍␍
+   //***************************************************************************␍␍
+   // The following parameters refer to width of various ports␍␍
+   //***************************************************************************␍␍
+   parameter CK_WIDTH              = 1,␍␍
+                                     // # of CK/CK# outputs to memory.␍␍
+   parameter nCS_PER_RANK          = 1,␍␍
+                                     // # of unique CS outputs per rank for phy␍␍
+   parameter CKE_WIDTH             = 1,␍␍
+                                     // # of CKE outputs to memory.␍␍
+   parameter DM_WIDTH              = 8,␍␍
+                                     // # of DM (data mask)␍␍
+   parameter ODT_WIDTH             = 1,␍␍
+                                     // # of ODT outputs to memory.␍␍
+   parameter BANK_WIDTH            = 3,␍␍
+                                     // # of memory Bank Address bits.␍␍
+   parameter COL_WIDTH             = 10,␍␍
+                                     // # of memory Column Address bits.␍␍
+   parameter CS_WIDTH              = 1,␍␍
+                                     // # of unique CS outputs to memory.␍␍
+   parameter DQ_WIDTH              = 64,␍␍
+                                     // # of DQ (data)␍␍
+   parameter DQS_WIDTH             = 8,␍␍
+   parameter DQS_CNT_WIDTH         = 3,␍␍
+                                     // = ceil(log2(DQS_WIDTH))␍␍
+   parameter DRAM_WIDTH            = 8,␍␍
+                                     // # of DQ per DQS␍␍
+   parameter ECC                   = "OFF",␍␍
+   parameter ECC_TEST              = "OFF",␍␍
+   //parameter nBANK_MACHS           = 4,␍␍
+   parameter nBANK_MACHS           = 4,␍␍
+   parameter RANKS                 = 1,␍␍
+                                     // # of Ranks.␍␍
+   parameter ROW_WIDTH             = 14,␍␍
+                                     // # of memory Row Address bits.␍␍
+   parameter ADDR_WIDTH            = 28,␍␍
+                                     // # = RANK_WIDTH + BANK_WIDTH␍␍
+                                     //     + ROW_WIDTH + COL_WIDTH;␍␍
+                                     // Chip Select is always tied to low for␍␍
+                                     // single rank devices␍␍
+␍␍
+   //***************************************************************************␍␍
+   // The following parameters are mode register settings␍␍
+   //***************************************************************************␍␍
+   parameter BURST_MODE            = "8",␍␍
+                                     // DDR3 SDRAM:␍␍
+                                     // Burst Length (Mode Register 0).␍␍
+                                     // # = "8", "4", "OTF".␍␍
+                                     // DDR2 SDRAM:␍␍
+                                     // Burst Length (Mode Register).␍␍
+                                     // # = "8", "4".␍␍
+␍␍
+   ␍␍
+   //***************************************************************************␍␍
+   // The following parameters are multiplier and divisor factors for PLLE2.␍␍
+   // Based on the selected design frequency these parameters vary.␍␍
+   //***************************************************************************␍␍
+   parameter CLKIN_PERIOD          = 5000,␍␍
+                                     // Input Clock Period␍␍
+   parameter CLKFBOUT_MULT         = 8,␍␍
+                                     // write PLL VCO multiplier␍␍
+   parameter DIVCLK_DIVIDE         = 1,␍␍
+                                     // write PLL VCO divisor␍␍
+   parameter CLKOUT0_PHASE         = 337.5,␍␍
+                                     // Phase for PLL output clock (CLKOUT0)␍␍
+   parameter CLKOUT0_DIVIDE        = 2,␍␍
+                                     // VCO output divisor for PLL output clock (CLKOUT0)␍␍
+   parameter CLKOUT1_DIVIDE        = 2,␍␍
+                                     // VCO output divisor for PLL output clock (CLKOUT1)␍␍
+   parameter CLKOUT2_DIVIDE        = 32,␍␍
+                                     // VCO output divisor for PLL output clock (CLKOUT2)␍␍
+   parameter CLKOUT3_DIVIDE        = 8,␍␍
+                                     // VCO output divisor for PLL output clock (CLKOUT3)␍␍
+   parameter MMCM_VCO              = 800,␍␍
+                                     // Max Freq (MHz) of MMCM VCO␍␍
+   parameter MMCM_MULT_F           = 4,␍␍
+                                     // write MMCM VCO multiplier␍␍
+   parameter MMCM_DIVCLK_DIVIDE    = 1,␍␍
+                                     // write MMCM VCO divisor␍␍
+   parameter MMCM_CLKOUT0_EN       = "TRUE",␍␍
+                                     // "TRUE" - MMCM output clock (CLKOUT0) is enabled␍␍
+                                     // "FALSE" - MMCM output clock (CLKOUT0) is disabled␍␍
+   parameter MMCM_CLKOUT1_EN       = "FALSE",␍␍
+                                     // "TRUE" - MMCM output clock (CLKOUT1) is enabled␍␍
+                                     // "FALSE" - MMCM output clock (CLKOUT1) is disabled␍␍
+   parameter MMCM_CLKOUT2_EN       = "FALSE",␍␍
+                                     // "TRUE" - MMCM output clock (CLKOUT2) is enabled␍␍
+                                     // "FALSE" - MMCM output clock (CLKOUT2) is disabled␍␍
+   parameter MMCM_CLKOUT3_EN       = "FALSE",␍␍
+                                     // "TRUE" - MMCM output clock (CLKOUT3) is enabled␍␍
+                                     // "FALSE" - MMCM output clock (CLKOUT3) is disabled␍␍
+   parameter MMCM_CLKOUT4_EN       = "FALSE",␍␍
+                                     // "TRUE" - MMCM output clock (CLKOUT4) is enabled␍␍
+                                     // "FALSE" - MMCM output clock (CLKOUT4) is disabled␍␍
+   parameter MMCM_CLKOUT0_DIVIDE   = 8,␍␍
+                                     // VCO output divisor for MMCM output clock (CLKOUT0)␍␍
+   parameter MMCM_CLKOUT1_DIVIDE   = 1,␍␍
+                                     // VCO output divisor for MMCM output clock (CLKOUT1)␍␍
+   parameter MMCM_CLKOUT2_DIVIDE   = 1,␍␍
+                                     // VCO output divisor for MMCM output clock (CLKOUT2)␍␍
+   parameter MMCM_CLKOUT3_DIVIDE   = 1,␍␍
+                                     // VCO output divisor for MMCM output clock (CLKOUT3)␍␍
+   parameter MMCM_CLKOUT4_DIVIDE   = 1,␍␍
+                                     // VCO output divisor for MMCM output clock (CLKOUT4)␍␍
+␍␍
+␍␍
+   //***************************************************************************␍␍
+   // Simulation parameters␍␍
+   //***************************************************************************␍␍
+   parameter SIMULATION            = "FALSE",␍␍
+                                     // Should be TRUE during design simulations and␍␍
+                                     // FALSE during implementations␍␍
+␍␍
+   //***************************************************************************␍␍
+   // IODELAY and PHY related parameters␍␍
+   //***************************************************************************␍␍
+   parameter TCQ                   = 100,␍␍
+   ␍␍
+   parameter DRAM_TYPE             = "DDR3",␍␍
+␍␍
+   ␍␍
+   //***************************************************************************␍␍
+   // System clock frequency parameters␍␍
+   //***************************************************************************␍␍
+   parameter nCK_PER_CLK           = 4,␍␍
+                                     // # of memory CKs per fabric CLK␍␍
+␍␍
+   ␍␍
+   //***************************************************************************␍␍
+   // AXI4 Shim parameters␍␍
+   //***************************************************************************␍␍
+   parameter C_S_AXI_ID_WIDTH              = 2,␍␍
+                                             // Width of all master and slave ID signals.␍␍
+                                             // # = >= 1.␍␍
+   parameter C_S_AXI_ADDR_WIDTH            = 32,␍␍
+                                             // Width of S_AXI_AWADDR, S_AXI_ARADDR, M_AXI_AWADDR and␍␍
+                                             // M_AXI_ARADDR for all SI/MI slots.␍␍
+                                             // # = 32.␍␍
+   parameter C_S_AXI_DATA_WIDTH            = 512,␍␍
+                                             // Width of WDATA and RDATA on SI slot.␍␍
+                                             // Must be <= APP_DATA_WIDTH.␍␍
+                                             // # = 32, 64, 128, 256.␍␍
+   parameter C_S_AXI_SUPPORTS_NARROW_BURST = 0,␍␍
+                                             // Indicates whether to instatiate upsizer␍␍
+                                             // Range: 0, 1␍␍
+      ␍␍
+␍␍
+   //***************************************************************************␍␍
+   // Debug parameters␍␍
+   //***************************************************************************␍␍
+   parameter DEBUG_PORT            = "OFF",␍␍
+                                     // # = "ON" Enable debug signals/controls.␍␍
+                                     //   = "OFF" Disable debug signals/controls.␍␍
+      ␍␍
+   parameter RST_ACT_LOW           = 0␍␍
+                                     // =1 for active low reset,␍␍
+                                     // =0 for active high.␍␍
+   )␍␍
+  (␍␍
+␍␍
+   // Inouts␍␍
+   inout [63:0]                         ddr3_dq,␍␍
+   inout [7:0]                        ddr3_dqs_n,␍␍
+   inout [7:0]                        ddr3_dqs_p,␍␍
+␍␍
+   // Outputs␍␍
+   output [13:0]                       ddr3_addr,␍␍
+   output [2:0]                      ddr3_ba,␍␍
+   output                                       ddr3_ras_n,␍␍
+   output                                       ddr3_cas_n,␍␍
+   output                                       ddr3_we_n,␍␍
+   output                                       ddr3_reset_n,␍␍
+   output [0:0]                        ddr3_ck_p,␍␍
+   output [0:0]                        ddr3_ck_n,␍␍
+   output [0:0]                       ddr3_cke,␍␍
+   ␍␍
+   output [0:0]           ddr3_cs_n,␍␍
+   ␍␍
+   output [7:0]                        ddr3_dm,␍␍
+   ␍␍
+   output [0:0]                       ddr3_odt,␍␍
+   ␍␍
+␍␍
+   // Inputs␍␍
+   ␍␍
+   // Differential system clocks␍␍
+   input                                        sys_clk_p,␍␍
+   input                                        sys_clk_n,␍␍
+   ␍␍
+␍␍
+   output                                       tg_compare_error,␍␍
+   output                                       init_calib_complete,␍␍
+   ␍␍
+      ␍␍
+␍␍
+   // System reset - Default polarity of sys_rst pin is Active Low.␍␍
+   // System reset polarity will change based on the option ␍␍
+   // selected in GUI.␍␍
+   input                                        sys_rst␍␍
+   );␍␍
+␍␍
+function integer clogb2 (input integer size);␍␍
+    begin␍␍
+      size = size - 1;␍␍
+      for (clogb2=1; size>1; clogb2=clogb2+1)␍␍
+        size = size >> 1;␍␍
+    end␍␍
+  endfunction // clogb2␍␍
+␍␍
+  function integer STR_TO_INT;␍␍
+    input [7:0] in;␍␍
+    begin␍␍
+      if(in == "8")␍␍
+        STR_TO_INT = 8;␍␍
+      else if(in == "4")␍␍
+        STR_TO_INT = 4;␍␍
+      else␍␍
+        STR_TO_INT = 0;␍␍
+    end␍␍
+  endfunction␍␍
+␍␍
+␍␍
+  localparam DATA_WIDTH            = 64;␍␍
+  localparam RANK_WIDTH = clogb2(RANKS);␍␍
+  localparam PAYLOAD_WIDTH         = (ECC_TEST == "OFF") ? DATA_WIDTH : DQ_WIDTH;␍␍
+  localparam BURST_LENGTH          = STR_TO_INT(BURST_MODE);␍␍
+  localparam APP_DATA_WIDTH        = 2 * nCK_PER_CLK * PAYLOAD_WIDTH;␍␍
+  localparam APP_MASK_WIDTH        = APP_DATA_WIDTH / 8;␍␍
+␍␍
+  //***************************************************************************␍␍
+  // Traffic Gen related parameters (derived)␍␍
+  //***************************************************************************␍␍
+  localparam  TG_ADDR_WIDTH = ((CS_WIDTH == 1) ? 0 : RANK_WIDTH)␍␍
+                                 + BANK_WIDTH + ROW_WIDTH + COL_WIDTH;␍␍
+  localparam MASK_SIZE             = DATA_WIDTH/8;␍␍
+  localparam DBG_WR_STS_WIDTH      = 40;␍␍
+  localparam DBG_RD_STS_WIDTH      = 40;␍␍
+      ␍␍
+␍␍
+  // Wire declarations␍␍
+      ␍␍
+  wire                              clk;␍␍
+  wire                              rst;␍␍
+  wire                              ui_addn_clk_0;␍␍
+  wire                              ui_addn_clk_1;␍␍
+  wire                              ui_addn_clk_2;␍␍
+  wire                              ui_addn_clk_3;␍␍
+  wire                              ui_addn_clk_4;␍␍
+  wire                              mmcm_locked;␍␍
+  reg                               aresetn;␍␍
+  wire                              app_sr_active;␍␍
+  wire                              app_ref_ack;␍␍
+  wire                              app_zq_ack;␍␍
+  wire                              app_rd_data_valid;␍␍
+  wire [APP_DATA_WIDTH-1:0]         app_rd_data;␍␍
+␍␍
+  wire                              mem_pattern_init_done;␍␍
+␍␍
+  wire                              cmd_err;␍␍
+  wire                              data_msmatch_err;␍␍
+  wire                              write_err;␍␍
+  wire                              read_err;␍␍
+  wire                              test_cmptd;␍␍
+  wire                              write_cmptd;␍␍
+  wire                              read_cmptd;␍␍
+  wire                              cmptd_one_wr_rd;␍␍
+␍␍
+  // Slave Interface Write Address Ports␍␍
+  wire [C_S_AXI_ID_WIDTH-1:0]       s_axi_awid;␍␍
+  wire [C_S_AXI_ADDR_WIDTH-1:0]     s_axi_awaddr;␍␍
+  wire [7:0]                        s_axi_awlen;␍␍
+  wire [2:0]                        s_axi_awsize;␍␍
+  wire [1:0]                        s_axi_awburst;␍␍
+  wire [0:0]                        s_axi_awlock;␍␍
+  wire [3:0]                        s_axi_awcache;␍␍
+  wire [2:0]                        s_axi_awprot;␍␍
+  wire                              s_axi_awvalid;␍␍
+  wire                              s_axi_awready;␍␍
+   // Slave Interface Write Data Ports␍␍
+  wire [C_S_AXI_DATA_WIDTH-1:0]     s_axi_wdata;␍␍
+  wire [(C_S_AXI_DATA_WIDTH/8)-1:0]   s_axi_wstrb;␍␍
+  wire                              s_axi_wlast;␍␍
+  wire                              s_axi_wvalid;␍␍
+  wire                              s_axi_wready;␍␍
+   // Slave Interface Write Response Ports␍␍
+  wire                              s_axi_bready;␍␍
+  wire [C_S_AXI_ID_WIDTH-1:0]       s_axi_bid;␍␍
+  wire [1:0]                        s_axi_bresp;␍␍
+  wire                              s_axi_bvalid;␍␍
+   // Slave Interface Read Address Ports␍␍
+  wire [C_S_AXI_ID_WIDTH-1:0]       s_axi_arid;␍␍
+  wire [C_S_AXI_ADDR_WIDTH-1:0]     s_axi_araddr;␍␍
+  wire [7:0]                        s_axi_arlen;␍␍
+  wire [2:0]                        s_axi_arsize;␍␍
+  wire [1:0]                        s_axi_arburst;␍␍
+  wire [0:0]                        s_axi_arlock;␍␍
+  wire [3:0]                        s_axi_arcache;␍␍
+  wire [2:0]                        s_axi_arprot;␍␍
+  wire                              s_axi_arvalid;␍␍
+  wire                              s_axi_arready;␍␍
+   // Slave Interface Read Data Ports␍␍
+  wire                              s_axi_rready;␍␍
+  wire [C_S_AXI_ID_WIDTH-1:0]       s_axi_rid;␍␍
+  wire [C_S_AXI_DATA_WIDTH-1:0]     s_axi_rdata;␍␍
+  wire [1:0]                        s_axi_rresp;␍␍
+  wire                              s_axi_rlast;␍␍
+  wire                              s_axi_rvalid;␍␍
+␍␍
+  wire                              cmp_data_valid;␍␍
+  wire [C_S_AXI_DATA_WIDTH-1:0]      cmp_data;     // Compare data␍␍
+  wire [C_S_AXI_DATA_WIDTH-1:0]      rdata_cmp;      // Read data␍␍
+␍␍
+  wire                              dbg_wr_sts_vld;␍␍
+  wire [DBG_WR_STS_WIDTH-1:0]       dbg_wr_sts;␍␍
+  wire                              dbg_rd_sts_vld;␍␍
+  wire [DBG_RD_STS_WIDTH-1:0]       dbg_rd_sts;␍␍
+  wire [11:0]                           device_temp;␍␍
+  ␍␍
+`ifdef SKIP_CALIB␍␍
+  // skip calibration wires␍␍
+  wire                          calib_tap_req;␍␍
+  reg                           calib_tap_load;␍␍
+  reg [6:0]                     calib_tap_addr;␍␍
+  reg [7:0]                     calib_tap_val;␍␍
+  reg                           calib_tap_load_done;␍␍
+`endif␍␍
+      ␍␍
+  ␍␍
+␍␍
+//***************************************************************************␍␍
+␍␍
+␍␍
+␍␍
+  assign tg_compare_error = cmd_err | data_msmatch_err | write_err | read_err;␍␍
+      ␍␍
+      ␍␍
+␍␍
+␍␍
+      ␍␍
+// Start of User Design top instance␍␍
+//***************************************************************************␍␍
+// The User design is instantiated below. The memory interface ports are␍␍
+// connected to the top-level and the application interface ports are␍␍
+// connected to the traffic generator module. This provides a reference␍␍
+// for connecting the memory controller to system.␍␍
+//***************************************************************************␍␍
+␍␍
+  system_top_mig_7series_0_0 u_system_top_mig_7series_0_0␍␍
+      (␍␍
+       ␍␍
+       ␍␍
+// Memory interface ports␍␍
+       .ddr3_addr                      (ddr3_addr),␍␍
+       .ddr3_ba                        (ddr3_ba),␍␍
+       .ddr3_cas_n                     (ddr3_cas_n),␍␍
+       .ddr3_ck_n                      (ddr3_ck_n),␍␍
+       .ddr3_ck_p                      (ddr3_ck_p),␍␍
+       .ddr3_cke                       (ddr3_cke),␍␍
+       .ddr3_ras_n                     (ddr3_ras_n),␍␍
+       .ddr3_we_n                      (ddr3_we_n),␍␍
+       .ddr3_dq                        (ddr3_dq),␍␍
+       .ddr3_dqs_n                     (ddr3_dqs_n),␍␍
+       .ddr3_dqs_p                     (ddr3_dqs_p),␍␍
+       .ddr3_reset_n                   (ddr3_reset_n),␍␍
+       .init_calib_complete            (init_calib_complete),␍␍
+      ␍␍
+       .ddr3_cs_n                      (ddr3_cs_n),␍␍
+       .ddr3_dm                        (ddr3_dm),␍␍
+       .ddr3_odt                       (ddr3_odt),␍␍
+// Application interface ports␍␍
+       .ui_clk                         (clk),␍␍
+       .ui_clk_sync_rst                (rst),␍␍
+␍␍
+       .ui_addn_clk_0                  (ui_addn_clk_0),␍␍
+       .ui_addn_clk_1                  (ui_addn_clk_1),␍␍
+       .ui_addn_clk_2                  (ui_addn_clk_2),␍␍
+       .ui_addn_clk_3                  (ui_addn_clk_3),␍␍
+       .ui_addn_clk_4                  (ui_addn_clk_4),␍␍
+       .mmcm_locked                    (mmcm_locked),␍␍
+       .aresetn                        (aresetn),␍␍
+       .app_sr_active                  (app_sr_active),␍␍
+       .app_ref_ack                    (app_ref_ack),␍␍
+       .app_zq_ack                     (app_zq_ack),␍␍
+␍␍
+// Slave Interface Write Address Ports␍␍
+       .s_axi_awid                     (s_axi_awid),␍␍
+       .s_axi_awaddr                   (s_axi_awaddr),␍␍
+       .s_axi_awlen                    (s_axi_awlen),␍␍
+       .s_axi_awsize                   (s_axi_awsize),␍␍
+       .s_axi_awburst                  (s_axi_awburst),␍␍
+       .s_axi_awlock                   (s_axi_awlock),␍␍
+       .s_axi_awcache                  (s_axi_awcache),␍␍
+       .s_axi_awprot                   (s_axi_awprot),␍␍
+       .s_axi_awqos                    (4'h0),␍␍
+       .s_axi_awvalid                  (s_axi_awvalid),␍␍
+       .s_axi_awready                  (s_axi_awready),␍␍
+// Slave Interface Write Data Ports␍␍
+       .s_axi_wdata                    (s_axi_wdata),␍␍
+       .s_axi_wstrb                    (s_axi_wstrb),␍␍
+       .s_axi_wlast                    (s_axi_wlast),␍␍
+       .s_axi_wvalid                   (s_axi_wvalid),␍␍
+       .s_axi_wready                   (s_axi_wready),␍␍
+// Slave Interface Write Response Ports␍␍
+       .s_axi_bid                      (s_axi_bid),␍␍
+       .s_axi_bresp                    (s_axi_bresp),␍␍
+       .s_axi_bvalid                   (s_axi_bvalid),␍␍
+       .s_axi_bready                   (s_axi_bready),␍␍
+// Slave Interface Read Address Ports␍␍
+       .s_axi_arid                     (s_axi_arid),␍␍
+       .s_axi_araddr                   (s_axi_araddr),␍␍
+       .s_axi_arlen                    (s_axi_arlen),␍␍
+       .s_axi_arsize                   (s_axi_arsize),␍␍
+       .s_axi_arburst                  (s_axi_arburst),␍␍
+       .s_axi_arlock                   (s_axi_arlock),␍␍
+       .s_axi_arcache                  (s_axi_arcache),␍␍
+       .s_axi_arprot                   (s_axi_arprot),␍␍
+       .s_axi_arqos                    (4'h0),␍␍
+       .s_axi_arvalid                  (s_axi_arvalid),␍␍
+       .s_axi_arready                  (s_axi_arready),␍␍
+// Slave Interface Read Data Ports␍␍
+       .s_axi_rid                      (s_axi_rid),␍␍
+       .s_axi_rdata                    (s_axi_rdata),␍␍
+       .s_axi_rresp                    (s_axi_rresp),␍␍
+       .s_axi_rlast                    (s_axi_rlast),␍␍
+       .s_axi_rvalid                   (s_axi_rvalid),␍␍
+       .s_axi_rready                   (s_axi_rready),␍␍
+␍␍
+      ␍␍
+       ␍␍
+// System Clock Ports␍␍
+       .sys_clk_p                       (sys_clk_p),␍␍
+       .sys_clk_n                       (sys_clk_n),␍␍
+       .device_temp            (device_temp),␍␍
+       `ifdef SKIP_CALIB␍␍
+       .calib_tap_req                    (calib_tap_req),␍␍
+       .calib_tap_load                   (calib_tap_load),␍␍
+       .calib_tap_addr                   (calib_tap_addr),␍␍
+       .calib_tap_val                    (calib_tap_val),␍␍
+       .calib_tap_load_done              (calib_tap_load_done),␍␍
+       `endif␍␍
+      ␍␍
+       .sys_rst                        (sys_rst)␍␍
+       );␍␍
+// End of User Design top instance␍␍
+␍␍
+␍␍
+//***************************************************************************␍␍
+// The traffic generation module instantiated below drives traffic (patterns)␍␍
+// on the application interface of the memory controller␍␍
+//***************************************************************************␍␍
+␍␍
+   always @(posedge clk) begin␍␍
+     aresetn <= ~rst;␍␍
+   end␍␍
+␍␍
+   mig_7series_v4_2_axi4_tg #(␍␍
+␍␍
+     .C_AXI_ID_WIDTH                   (C_S_AXI_ID_WIDTH),␍␍
+     .C_AXI_ADDR_WIDTH                 (C_S_AXI_ADDR_WIDTH),␍␍
+     .C_AXI_DATA_WIDTH                 (C_S_AXI_DATA_WIDTH),␍␍
+     .C_AXI_NBURST_SUPPORT             (C_AXI_NBURST_TEST),␍␍
+     .C_EN_WRAP_TRANS                  (C_EN_WRAP_TRANS),␍␍
+     .C_BEGIN_ADDRESS                  (BEGIN_ADDRESS),␍␍
+     .C_END_ADDRESS                    (END_ADDRESS),␍␍
+     .PRBS_EADDR_MASK_POS              (PRBS_EADDR_MASK_POS),␍␍
+     .DBG_WR_STS_WIDTH                 (DBG_WR_STS_WIDTH),␍␍
+     .DBG_RD_STS_WIDTH                 (DBG_RD_STS_WIDTH),␍␍
+     .ENFORCE_RD_WR                    (ENFORCE_RD_WR),␍␍
+     .ENFORCE_RD_WR_CMD                (ENFORCE_RD_WR_CMD),␍␍
+     .EN_UPSIZER                       (C_S_AXI_SUPPORTS_NARROW_BURST),␍␍
+     .ENFORCE_RD_WR_PATTERN            (ENFORCE_RD_WR_PATTERN)␍␍
+␍␍
+   ) u_axi4_tg_inst␍␍
+   (␍␍
+     .aclk                             (clk),␍␍
+     .aresetn                          (aresetn),␍␍
+␍␍
+// Input control signals␍␍
+     .init_cmptd                       (init_calib_complete),␍␍
+     .init_test                        (1'b0),␍␍
+     .wdog_mask                        (~init_calib_complete),␍␍
+     .wrap_en                          (1'b0),␍␍
+␍␍
+// AXI write address channel signals␍␍
+     .axi_wready                       (s_axi_awready),␍␍
+     .axi_wid                          (s_axi_awid),␍␍
+     .axi_waddr                        (s_axi_awaddr),␍␍
+     .axi_wlen                         (s_axi_awlen),␍␍
+     .axi_wsize                        (s_axi_awsize),␍␍
+     .axi_wburst                       (s_axi_awburst),␍␍
+     .axi_wlock                        (s_axi_awlock),␍␍
+     .axi_wcache                       (s_axi_awcache),␍␍
+     .axi_wprot                        (s_axi_awprot),␍␍
+     .axi_wvalid                       (s_axi_awvalid),␍␍
+␍␍
+// AXI write data channel signals␍␍
+     .axi_wd_wready                    (s_axi_wready),␍␍
+     .axi_wd_wid                       (s_axi_wid),␍␍
+     .axi_wd_data                      (s_axi_wdata),␍␍
+     .axi_wd_strb                      (s_axi_wstrb),␍␍
+     .axi_wd_last                      (s_axi_wlast),␍␍
+     .axi_wd_valid                     (s_axi_wvalid),␍␍
+␍␍
+// AXI write response channel signals␍␍
+     .axi_wd_bid                       (s_axi_bid),␍␍
+     .axi_wd_bresp                     (s_axi_bresp),␍␍
+     .axi_wd_bvalid                    (s_axi_bvalid),␍␍
+     .axi_wd_bready                    (s_axi_bready),␍␍
+␍␍
+// AXI read address channel signals␍␍
+     .axi_rready                       (s_axi_arready),␍␍
+     .axi_rid                          (s_axi_arid),␍␍
+     .axi_raddr                        (s_axi_araddr),␍␍
+     .axi_rlen                         (s_axi_arlen),␍␍
+     .axi_rsize                        (s_axi_arsize),␍␍
+     .axi_rburst                       (s_axi_arburst),␍␍
+     .axi_rlock                        (s_axi_arlock),␍␍
+     .axi_rcache                       (s_axi_arcache),␍␍
+     .axi_rprot                        (s_axi_arprot),␍␍
+     .axi_rvalid                       (s_axi_arvalid),␍␍
+␍␍
+// AXI read data channel signals␍␍
+     .axi_rd_bid                       (s_axi_rid),␍␍
+     .axi_rd_rresp                     (s_axi_rresp),␍␍
+     .axi_rd_rvalid                    (s_axi_rvalid),␍␍
+     .axi_rd_data                      (s_axi_rdata),␍␍
+     .axi_rd_last                      (s_axi_rlast),␍␍
+     .axi_rd_rready                    (s_axi_rready),␍␍
+␍␍
+// Error status signals␍␍
+     .cmd_err                          (cmd_err),␍␍
+     .data_msmatch_err                 (data_msmatch_err),␍␍
+     .write_err                        (write_err),␍␍
+     .read_err                         (read_err),␍␍
+     .test_cmptd                       (test_cmptd),␍␍
+     .write_cmptd                      (write_cmptd),␍␍
+     .read_cmptd                       (read_cmptd),␍␍
+     .cmptd_one_wr_rd                  (cmptd_one_wr_rd),␍␍
+␍␍
+// Debug status signals␍␍
+     .cmp_data_en                      (cmp_data_valid),␍␍
+     .cmp_data_o                       (cmp_data),␍␍
+     .rdata_cmp                        (rdata_cmp),␍␍
+     .dbg_wr_sts_vld                   (dbg_wr_sts_vld),␍␍
+     .dbg_wr_sts                       (dbg_wr_sts),␍␍
+     .dbg_rd_sts_vld                   (dbg_rd_sts_vld),␍␍
+     .dbg_rd_sts                       (dbg_rd_sts)␍␍
+);␍␍
+␍␍
+      ␍␍
+␍␍
+␍␍
+   //*****************************************************************␍␍
+   // Default values are assigned to the debug inputs␍␍
+   //*****************************************************************␍␍
+   assign dbg_sel_pi_incdec       = 'b0;␍␍
+   assign dbg_sel_po_incdec       = 'b0;␍␍
+   assign dbg_pi_f_inc            = 'b0;␍␍
+   assign dbg_pi_f_dec            = 'b0;␍␍
+   assign dbg_po_f_inc            = 'b0;␍␍
+   assign dbg_po_f_dec            = 'b0;␍␍
+   assign dbg_po_f_stg23_sel      = 'b0;␍␍
+   assign po_win_tg_rst           = 'b0;␍␍
+   assign vio_tg_rst              = 'b0;␍␍
+`ifdef SKIP_CALIB␍␍
+  //***************************************************************************␍␍
+  // Skip calib test logic␍␍
+  //***************************************************************************␍␍
+␍␍
+  reg[3*DQS_WIDTH-1:0]        po_coarse_tap;␍␍
+  reg[6*DQS_WIDTH-1:0]        po_stg3_taps;␍␍
+  reg[6*DQS_WIDTH-1:0]        po_stg2_taps;␍␍
+  reg[6*DQS_WIDTH-1:0]        pi_stg2_taps;␍␍
+  reg[5*DQS_WIDTH-1:0]        idelay_taps;␍␍
+  reg[11:0]                   cal_device_temp;␍␍
+␍␍
+␍␍
+  always @(posedge clk) begin␍␍
+    // tap values from golden run (factory)␍␍
+    po_coarse_tap   <= #TCQ 'h2;␍␍
+    po_stg3_taps    <= #TCQ 'h0D;␍␍
+    po_stg2_taps    <= #TCQ 'h1D;␍␍
+    pi_stg2_taps    <= #TCQ 'h1E;␍␍
+    idelay_taps     <= #TCQ 'h08;␍␍
+        cal_device_temp <= #TCQ 'h000;␍␍
+  end␍␍
+␍␍
+  always @(posedge clk) begin␍␍
+    if (rst)␍␍
+      calib_tap_load <= #TCQ 1'b0;␍␍
+    else if (calib_tap_req)␍␍
+      calib_tap_load <= #TCQ 1'b1;␍␍
+  end␍␍
+␍␍
+  always @(posedge clk) begin␍␍
+    if (rst) begin␍␍
+      calib_tap_addr      <= #TCQ 'd0;␍␍
+      calib_tap_val       <= #TCQ po_coarse_tap[3*calib_tap_addr[6:3]+:3]; //'d1;␍␍
+      calib_tap_load_done <= #TCQ 1'b0;␍␍
+    end else if (calib_tap_load) begin␍␍
+      case (calib_tap_addr[2:0])␍␍
+        3'b000: begin␍␍
+          calib_tap_addr[2:0] <= #TCQ 3'b001;␍␍
+          calib_tap_val       <= #TCQ po_stg3_taps[6*calib_tap_addr[6:3]+:6]; //'d19;␍␍
+        end␍␍
+        3'b001: begin␍␍
+          calib_tap_addr[2:0] <= #TCQ 3'b010;␍␍
+          calib_tap_val       <= #TCQ po_stg2_taps[6*calib_tap_addr[6:3]+:6]; //'d45;␍␍
+        end␍␍
+        3'b010: begin␍␍
+          calib_tap_addr[2:0] <= #TCQ 3'b011;␍␍
+          calib_tap_val       <= #TCQ pi_stg2_taps[6*calib_tap_addr[6:3]+:6]; //'d20;␍␍
+        end␍␍
+        3'b011: begin␍␍
+          calib_tap_addr[2:0] <= #TCQ 3'b100;␍␍
+          calib_tap_val       <= #TCQ idelay_taps[5*calib_tap_addr[6:3]+:5]; //'d1;␍␍
+        end␍␍
+        3'b100: begin␍␍
+          if (calib_tap_addr[6:3] < DQS_WIDTH-1) begin␍␍
+            calib_tap_addr[2:0] <= #TCQ 3'b000;␍␍
+            calib_tap_val       <= #TCQ po_coarse_tap[3*(calib_tap_addr[6:3]+1)+:3]; //'d1;␍␍
+            calib_tap_addr[6:3] <= #TCQ calib_tap_addr[6:3] + 1;␍␍
+          end else begin␍␍
+            calib_tap_addr[2:0] <= #TCQ 3'b110;␍␍
+            calib_tap_val       <= #TCQ cal_device_temp[7:0];␍␍
+            calib_tap_addr[6:3] <= #TCQ 4'b1111;␍␍
+          end␍␍
+        end␍␍
+        3'b110: begin␍␍
+            calib_tap_addr[2:0] <= #TCQ 3'b111;␍␍
+            calib_tap_val       <= #TCQ {4'h0,cal_device_temp[11:8]};␍␍
+            calib_tap_addr[6:3] <= #TCQ 4'b1111;␍␍
+        end␍␍
+        3'b111: begin␍␍
+            calib_tap_load_done <= #TCQ 1'b1;␍␍
+        end␍␍
+      endcase␍␍
+    end␍␍
+  end␍␍
+␍␍
+␍␍
+//****************skip calib test logic end**********************************␍␍
+`endif    ␍␍
+␍␍
+endmodule␍␍
+␍␍
+␍

cx9261a_demo_cmos_20240829/project_fix_dac.srcs/sources_1/bd/system_top/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/example_design/rtl/traffic_gen/mig_7series_v4_2_axi4_tg.v

@@ -0,0 +1,413 @@
+//*****************************************************************************
+// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//*****************************************************************************
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /    Vendor: Xilinx
+// \   \   \/     Version: 3.6
+//  \   \         Application: MIG
+//  /   /         Filename: axi4_wrapper.v
+// /___/   /\     Date Last Modified: $Date: 2011/06/02 08:37:18 $
+// \   \  /  \    Date Created: Sept 16, 2009
+//  \___\/\___\
+//
+//Device: Virtex-6, Spartan-6 and 7series
+//Design Name: DDR3 SDRAM
+//Purpose:
+//   This module is wrapper for converting the reads and writes to transactions
+//   that follow the AXI protocol.
+//
+//Reference:
+//Revision History:
+//*****************************************************************************
+`timescale 1ps/1ps
+
+module mig_7series_v4_2_axi4_tg #(
+    
+     parameter C_AXI_ID_WIDTH           = 4, // The AXI id width used for read and write
+                                             // This is an integer between 1-16
+     parameter C_AXI_ADDR_WIDTH         = 32, // This is AXI address width for all 
+                                              // SI and MI slots
+     parameter C_AXI_DATA_WIDTH         = 32, // Width of the AXI write and read data
+  
+     parameter C_AXI_NBURST_SUPPORT     = 0, // Support for narrow burst transfers
+                                             // 1-supported, 0-not supported 
+     parameter C_EN_WRAP_TRANS          = 0, // Set 1 to enable wrap transactions
+
+     parameter C_BEGIN_ADDRESS          = 0, // Start address of the address map
+  
+     parameter C_END_ADDRESS            = 32'hFFFF_FFFF, // End address of the address map
+     
+     parameter PRBS_EADDR_MASK_POS      = 32'hFFFFD000,
+
+     parameter PRBS_SADDR_MASK_POS      = 32'h00002000,
+
+     parameter DBG_WR_STS_WIDTH         = 40,
+
+     parameter DBG_RD_STS_WIDTH         = 40,
+  
+     parameter ENFORCE_RD_WR            = 0,
+
+     parameter ENFORCE_RD_WR_CMD        = 8'h11,
+
+     parameter EN_UPSIZER               = 0,
+
+     parameter ENFORCE_RD_WR_PATTERN    = 3'b000
+  
+)
+(
+   input                               aclk,    // AXI input clock
+   input                               aresetn, // Active low AXI reset signal
+
+// Input control signals
+   input                               init_cmptd, // Initialization completed
+   input                               init_test,  // Initialize the test
+   input                               wdog_mask,  // Mask the watchdog timeouts
+   input                               wrap_en,    // Enable wrap transactions
+
+// AXI write address channel signals
+   input                               axi_wready, // Indicates slave is ready to accept a 
+   output [C_AXI_ID_WIDTH-1:0]         axi_wid,    // Write ID
+   output [C_AXI_ADDR_WIDTH-1:0]       axi_waddr,  // Write address
+   output [7:0]                        axi_wlen,   // Write Burst Length
+   output [2:0]                        axi_wsize,  // Write Burst size
+   output [1:0]                        axi_wburst, // Write Burst type
+   output [1:0]                        axi_wlock,  // Write lock type
+   output [3:0]                        axi_wcache, // Write Cache type
+   output [2:0]                        axi_wprot,  // Write Protection type
+   output                              axi_wvalid, // Write address valid
+  
+// AXI write data channel signals
+   input                               axi_wd_wready,  // Write data ready
+   output [C_AXI_ID_WIDTH-1:0]         axi_wd_wid,     // Write ID tag
+   output [C_AXI_DATA_WIDTH-1:0]       axi_wd_data,    // Write data
+   output [C_AXI_DATA_WIDTH/8-1:0]     axi_wd_strb,    // Write strobes
+   output                              axi_wd_last,    // Last write transaction   
+   output                              axi_wd_valid,   // Write valid
+  
+// AXI write response channel signals
+   input  [C_AXI_ID_WIDTH-1:0]         axi_wd_bid,     // Response ID
+   input  [1:0]                        axi_wd_bresp,   // Write response
+   input                               axi_wd_bvalid,  // Write reponse valid
+   output                              axi_wd_bready,  // Response ready
+  
+// AXI read address channel signals
+   input                               axi_rready,     // Read address ready
+   output [C_AXI_ID_WIDTH-1:0]         axi_rid,        // Read ID
+   output [C_AXI_ADDR_WIDTH-1:0]       axi_raddr,      // Read address
+   output [7:0]                        axi_rlen,       // Read Burst Length
+   output [2:0]                        axi_rsize,      // Read Burst size
+   output [1:0]                        axi_rburst,     // Read Burst type
+   output [1:0]                        axi_rlock,      // Read lock type
+   output [3:0]                        axi_rcache,     // Read Cache type
+   output [2:0]                        axi_rprot,      // Read Protection type
+   output                              axi_rvalid,     // Read address valid
+  
+// AXI read data channel signals   
+   input  [C_AXI_ID_WIDTH-1:0]         axi_rd_bid,     // Response ID
+   input  [1:0]                        axi_rd_rresp,   // Read response
+   input                               axi_rd_rvalid,  // Read reponse valid
+   input  [C_AXI_DATA_WIDTH-1:0]       axi_rd_data,    // Read data
+   input                               axi_rd_last,    // Read last
+   output                              axi_rd_rready,  // Read Response ready
+
+// Error status signals
+   output                              cmd_err,      // Error during command phase
+   output                              data_msmatch_err, // Data mismatch
+   output                              write_err,    // Write error occured
+   output                              read_err,     // Read error occured
+   output                              test_cmptd,   // Data pattern test completed
+   output                              write_cmptd,  // Write test completed
+   output                              read_cmptd,   // Read test completed
+   output reg                          cmptd_one_wr_rd, // Completed atleast one write
+                                                        // and read
+
+// Debug status signals
+   output                              cmp_data_en,
+   output [C_AXI_DATA_WIDTH-1:0]       cmp_data_o,     // Compare data 
+   output [C_AXI_DATA_WIDTH-1:0]       rdata_cmp,      // Read data 
+   output                              dbg_wr_sts_vld, // Write debug status valid,
+   output [DBG_WR_STS_WIDTH-1:0]       dbg_wr_sts,     // Write status
+   output                              dbg_rd_sts_vld, // Read debug status valid
+   output [DBG_RD_STS_WIDTH-1:0]       dbg_rd_sts      // Read status
+);
+
+//*****************************************************************************
+// Parameter declarations
+//*****************************************************************************
+
+  localparam CTL_SIG_WIDTH             = 3;  // Control signal width
+  localparam RD_STS_WIDTH              = 16; // Read port status signal width
+  localparam WDG_TIMER_WIDTH           = 11;
+  localparam WR_STS_WIDTH              = 16; // Write port status signal width
+
+//*****************************************************************************
+// Internal register and wire declarations
+//*****************************************************************************
+
+  wire                                 cmd_en;
+  wire [2:0]                           cmd;
+  wire [7:0]                           blen;
+  wire [31:0]                          addr;
+  wire [CTL_SIG_WIDTH-1:0]             ctl;
+  wire                                 cmd_ack;
+
+// User interface write ports
+  wire                                 wrdata_vld;
+  wire [C_AXI_DATA_WIDTH-1:0]          wrdata;
+  wire [C_AXI_DATA_WIDTH/8-1:0]        wrdata_bvld;
+  wire                                 wrdata_cmptd;
+  wire                                 wrdata_rdy;
+  wire                                 wrdata_sts_vld;
+  wire [WR_STS_WIDTH-1:0]              wrdata_sts;
+
+// User interface read ports
+  wire                                 rddata_rdy;
+  wire                                 rddata_vld;
+  wire [C_AXI_DATA_WIDTH-1:0]          rddata;
+  wire [C_AXI_DATA_WIDTH/8-1:0]        rddata_bvld;
+  wire                                 rddata_cmptd;
+  wire [RD_STS_WIDTH-1:0]              rddata_sts;
+  reg                                  cmptd_one_wr;
+  reg                                  cmptd_one_rd;
+
+//*****************************************************************************
+// AXI4 wrapper instance
+//*****************************************************************************
+
+  mig_7series_v4_2_axi4_wrapper #
+    (
+    
+     .C_AXI_ID_WIDTH                   (C_AXI_ID_WIDTH),
+     .C_AXI_ADDR_WIDTH                 (C_AXI_ADDR_WIDTH),
+     .C_AXI_DATA_WIDTH                 (C_AXI_DATA_WIDTH),
+     .C_AXI_NBURST_SUPPORT             (C_AXI_NBURST_SUPPORT),
+     .C_BEGIN_ADDRESS                  (C_BEGIN_ADDRESS),
+     .C_END_ADDRESS                    (C_END_ADDRESS),
+     .CTL_SIG_WIDTH                    (CTL_SIG_WIDTH),
+     .WR_STS_WIDTH                     (WR_STS_WIDTH),
+     .RD_STS_WIDTH                     (RD_STS_WIDTH),
+     .EN_UPSIZER                       (EN_UPSIZER),
+     .WDG_TIMER_WIDTH                  (WDG_TIMER_WIDTH)
+  
+  ) axi4_wrapper_inst
+  (
+     .aclk                             (aclk),
+     .aresetn                          (aresetn),
+     
+// User interface command port
+     .cmd_en                           (cmd_en),
+     .cmd                              (cmd),
+     .blen                             (blen),
+     .addr                             (addr),
+     .ctl                              (ctl),
+     .wdog_mask                        (wdog_mask),
+     .cmd_ack                          (cmd_ack),
+  
+// User interface write ports
+     .wrdata_vld                       (wrdata_vld),
+     .wrdata                           (wrdata),
+     .wrdata_bvld                      (wrdata_bvld),
+     .wrdata_cmptd                     (wrdata_cmptd),
+     .wrdata_rdy                       (wrdata_rdy),
+     .wrdata_sts_vld                   (wrdata_sts_vld),
+     .wrdata_sts                       (wrdata_sts),
+  
+// User interface read ports
+     .rddata_rdy                       (rddata_rdy),
+     .rddata_vld                       (rddata_vld),
+     .rddata                           (rddata),
+     .rddata_bvld                      (rddata_bvld),
+     .rddata_cmptd                     (rddata_cmptd),
+     .rddata_sts                       (rddata_sts),
+  
+// AXI write address channel signals
+     .axi_wready                       (axi_wready),
+     .axi_wid                          (axi_wid),
+     .axi_waddr                        (axi_waddr),
+     .axi_wlen                         (axi_wlen),
+     .axi_wsize                        (axi_wsize),
+     .axi_wburst                       (axi_wburst),
+     .axi_wlock                        (axi_wlock),
+     .axi_wcache                       (axi_wcache),
+     .axi_wprot                        (axi_wprot),
+     .axi_wvalid                       (axi_wvalid),
+  
+// AXI write data channel signals
+     .axi_wd_wready                    (axi_wd_wready),
+     .axi_wd_wid                       (axi_wd_wid),
+     .axi_wd_data                      (axi_wd_data),
+     .axi_wd_strb                      (axi_wd_strb),
+     .axi_wd_last                      (axi_wd_last),
+     .axi_wd_valid                     (axi_wd_valid),
+  
+// AXI write response channel signals
+     .axi_wd_bid                       (axi_wd_bid),
+     .axi_wd_bresp                     (axi_wd_bresp),
+     .axi_wd_bvalid                    (axi_wd_bvalid),
+     .axi_wd_bready                    (axi_wd_bready),
+  
+// AXI read address channel signals
+     .axi_rready                       (axi_rready),
+     .axi_rid                          (axi_rid),
+     .axi_raddr                        (axi_raddr),
+     .axi_rlen                         (axi_rlen),
+     .axi_rsize                        (axi_rsize),
+     .axi_rburst                       (axi_rburst),
+     .axi_rlock                        (axi_rlock),
+     .axi_rcache                       (axi_rcache),
+     .axi_rprot                        (axi_rprot),
+     .axi_rvalid                       (axi_rvalid),
+  
+// AXI read data channel signals   
+     .axi_rd_bid                       (axi_rd_bid),
+     .axi_rd_rresp                     (axi_rd_rresp),
+     .axi_rd_rvalid                    (axi_rd_rvalid),
+     .axi_rd_data                      (axi_rd_data),
+     .axi_rd_last                      (axi_rd_last),
+     .axi_rd_rready                    (axi_rd_rready)
+  );
+
+//*****************************************************************************
+// Traffic Generator instance
+//*****************************************************************************
+
+  mig_7series_v4_2_tg #
+    (
+  
+    .C_AXI_ADDR_WIDTH                  (C_AXI_ADDR_WIDTH),
+    .C_AXI_DATA_WIDTH                  (C_AXI_DATA_WIDTH),
+    .C_AXI_NBURST_SUPPORT              (C_AXI_NBURST_SUPPORT),
+    .C_BEGIN_ADDRESS                   (C_BEGIN_ADDRESS),
+    .C_END_ADDRESS                     (C_END_ADDRESS),
+    .C_EN_WRAP_TRANS                   (C_EN_WRAP_TRANS),
+    .CTL_SIG_WIDTH                     (CTL_SIG_WIDTH),
+    .WR_STS_WIDTH                      (WR_STS_WIDTH),
+    .RD_STS_WIDTH                      (RD_STS_WIDTH),
+    .DBG_WR_STS_WIDTH                  (DBG_WR_STS_WIDTH),
+    .DBG_RD_STS_WIDTH                  (DBG_RD_STS_WIDTH),
+    .ENFORCE_RD_WR                     (ENFORCE_RD_WR),
+    .ENFORCE_RD_WR_CMD                 (ENFORCE_RD_WR_CMD),
+    .PRBS_EADDR_MASK_POS               (PRBS_EADDR_MASK_POS),
+    .PRBS_SADDR_MASK_POS               (PRBS_SADDR_MASK_POS),
+    .ENFORCE_RD_WR_PATTERN             (ENFORCE_RD_WR_PATTERN)
+
+  ) traffic_gen_inst
+  (
+    .clk                               (aclk),
+    .resetn                            (aresetn),
+
+// Input start signals
+    .init_cmptd                        (init_cmptd),
+    .init_test                         (init_test),
+    .wrap_en                           (wrap_en),
+
+// Control ports
+    .cmd_ack                           (cmd_ack),
+    .cmd_en                            (cmd_en),
+    .cmd                               (cmd),
+    .blen                              (blen),
+    .addr                              (addr),
+    .ctl                               (ctl),
+
+// Write port
+    .wdata_rdy                         (wrdata_rdy),
+    .wdata_vld                         (wrdata_vld),
+    .wdata_cmptd                       (wrdata_cmptd),
+    .wdata                             (wrdata),
+    .wdata_bvld                        (wrdata_bvld),
+    .wdata_sts_vld                     (wrdata_sts_vld),
+    .wdata_sts                         (wrdata_sts),
+
+// Read Port
+    .rdata_vld                         (rddata_vld),
+    .rdata                             (rddata),
+    .rdata_bvld                        (rddata_bvld),
+    .rdata_cmptd                       (rddata_cmptd),
+    .rdata_sts                         (rddata_sts),
+    .rdata_rdy                         (rddata_rdy),
+
+// Error status signals
+    .cmd_err                           (cmd_err),
+    .data_msmatch_err                  (data_msmatch_err),
+    .write_err                         (write_err),
+    .read_err                          (read_err),
+    .test_cmptd                        (test_cmptd),
+    .write_cmptd                       (write_cmptd),
+    .read_cmptd                        (read_cmptd),
+
+// Debug status signals
+    .cmp_data_en                       (cmp_data_en),
+    .rdata_cmp                         (rdata_cmp),
+    .dbg_wr_sts_vld                    (dbg_wr_sts_vld),
+    .dbg_wr_sts                        (dbg_wr_sts),
+    .dbg_rd_sts_vld                    (dbg_rd_sts_vld),
+    .dbg_rd_sts                        (dbg_rd_sts)
+  );
+
+  assign cmp_data_o = wrdata;
+
+  always @(posedge aclk)
+    if (!aresetn) 
+      cmptd_one_wr <= 1'b0;
+    else if (write_cmptd)
+      cmptd_one_wr <= 1'b1;
+
+  always @(posedge aclk)
+    if (!aresetn) 
+      cmptd_one_rd <= 1'b0;
+    else if (read_cmptd)
+      cmptd_one_rd <= 1'b1;
+
+  always @(posedge aclk)
+    if (!aresetn) 
+      cmptd_one_wr_rd <= 1'b0;
+    else if (cmptd_one_wr & cmptd_one_rd)
+      cmptd_one_wr_rd <= 1'b1;
+
+endmodule

cx9261a_demo_cmos_20240829/project_fix_dac.srcs/sources_1/bd/system_top/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/example_design/rtl/traffic_gen/mig_7series_v4_2_axi4_wrapper.v

@@ -0,0 +1,869 @@
+//*****************************************************************************
+// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//*****************************************************************************
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /    Vendor: Xilinx
+// \   \   \/     Version: 3.6
+//  \   \         Application: MIG
+//  /   /         Filename: axi4_wrapper.v
+// /___/   /\     Date Last Modified: $Date: 2011/06/02 08:37:18 $
+// \   \  /  \    Date Created: Sept 16, 2009
+//  \___\/\___\
+//
+//Device: Virtex-6, Spartan-6 and 7series
+//Design Name: DDR3 SDRAM
+//Purpose:
+//   This module is wrapper for converting the reads and writes to transactions
+//   that follow the AXI4 protocol.
+//
+//Reference:
+//Revision History:
+//*****************************************************************************
+`timescale 1ps/1ps
+
+module mig_7series_v4_2_axi4_wrapper #(
+  
+   parameter C_AXI_ID_WIDTH       = 4, // The AXI id width used for read and write
+                                       // This is an integer between 1-16
+   parameter C_AXI_ADDR_WIDTH     = 32, // This is AXI address width for all 
+                                        // SI and MI slots
+   parameter C_AXI_DATA_WIDTH     = 32, // Width of the AXI write and read data
+
+   parameter C_AXI_NBURST_SUPPORT = 0, // Support for narrow burst transfers
+                                       // 1-supported, 0-not supported 
+   parameter C_BEGIN_ADDRESS      = 0, // Start address of the address map
+
+   parameter C_END_ADDRESS        = 32'hFFFF_FFFF, // End address of the address map
+
+   parameter CTL_SIG_WIDTH        = 2, // Control signal width
+
+   parameter WR_STS_WIDTH         = 16, // Write port status signal width
+
+   parameter RD_STS_WIDTH         = 16,  // Read port status signal width
+
+   parameter EN_UPSIZER           = 0, // There is no upsizer code
+ 
+   parameter WDG_TIMER_WIDTH      = 9
+
+)
+(
+   input                               aclk, // AXI input clock
+   input                               aresetn, // Active low AXI reset signal
+   
+// User interface command port
+
+   input                               cmd_en, // Asserted to indicate a valid command
+                                               // and address
+   input [2:0]                         cmd,    // Write or read command
+                                               // 000 - READ with INCR bursts
+                                               // 001 - READ with WRAP bursts
+                                               // 01x - Reserved
+                                               // 100 - WRITE with INCR bursts
+                                               // 101 - WRITE with WRAP bursts
+   input [7:0]                         blen,   // Burst length calculated as blen+1
+   input [31:0]                        addr,   // Address for the read or the write
+                                               // transaction
+   input [CTL_SIG_WIDTH-1:0]           ctl,    // control command for read or write
+                                               // transaction 
+   input                               wdog_mask, // Mask the watchdog timeouts
+   output                              cmd_ack,// Indicates the command has been accepted
+
+// User interface write ports
+
+   input                               wrdata_vld,  // Asserted to indicate a valid write
+                                                    // data
+   input [C_AXI_DATA_WIDTH-1:0]        wrdata,      // Write data
+   input [C_AXI_DATA_WIDTH/8-1:0]      wrdata_bvld, // Byte valids for the write data
+   input                               wrdata_cmptd,// Last data to be transferred
+   output reg                          wrdata_rdy,  // Indicates that the write data is
+                                                    // ready to be accepted
+   output reg                          wrdata_sts_vld, // Indicates a write status after
+                                                       // completion of a write transfer                               
+   output [WR_STS_WIDTH-1:0]           wrdata_sts,     // Status of the write transaction
+
+// User interface read ports
+
+   input                               rddata_rdy,   // Data ready to be accepted
+   output reg                          rddata_vld,   // Indicates a valid read data available
+   output reg [C_AXI_DATA_WIDTH-1:0]   rddata,       // Read data
+   output [C_AXI_DATA_WIDTH/8-1:0]     rddata_bvld,  // Byte valids for read data 
+   output reg                          rddata_cmptd, // Indicates last data present and 
+                                                     // valid status
+   output [RD_STS_WIDTH-1:0]           rddata_sts,   // Status of the read transaction
+
+// AXI write address channel signals
+
+   input                               axi_wready, // Indicates slave is ready to accept a 
+                                                   // write address
+   output [C_AXI_ID_WIDTH-1:0]         axi_wid,    // Write ID
+   output [C_AXI_ADDR_WIDTH-1:0]       axi_waddr,  // Write address
+   output [7:0]                        axi_wlen,   // Write Burst Length
+   output [2:0]                        axi_wsize,  // Write Burst size
+   output [1:0]                        axi_wburst, // Write Burst type
+   output [1:0]                        axi_wlock,  // Write lock type
+   output [3:0]                        axi_wcache, // Write Cache type
+   output [2:0]                        axi_wprot,  // Write Protection type
+   output reg                          axi_wvalid, // Write address valid
+
+// AXI write data channel signals
+
+   input                               axi_wd_wready,  // Write data ready
+   output [C_AXI_ID_WIDTH-1:0]         axi_wd_wid,     // Write ID tag
+   output reg [C_AXI_DATA_WIDTH-1:0]   axi_wd_data,    // Write data
+   output reg [C_AXI_DATA_WIDTH/8-1:0] axi_wd_strb,    // Write strobes
+   output reg                          axi_wd_last,    // Last write transaction   
+   output                              axi_wd_valid,   // Write valid
+
+// AXI write response channel signals
+   input  [C_AXI_ID_WIDTH-1:0]         axi_wd_bid,     // Response ID
+   input  [1:0]                        axi_wd_bresp,   // Write response
+   input                               axi_wd_bvalid,  // Write reponse valid
+   output reg                          axi_wd_bready,  // Response ready
+
+// AXI read address channel signals
+   input                               axi_rready,     // Read address ready
+   output [C_AXI_ID_WIDTH-1:0]         axi_rid,        // Read ID
+   output [C_AXI_ADDR_WIDTH-1:0]       axi_raddr,      // Read address
+   output [7:0]                        axi_rlen,       // Read Burst Length
+   output [2:0]                        axi_rsize,      // Read Burst size
+   output [1:0]                        axi_rburst,     // Read Burst type
+   output [1:0]                        axi_rlock,      // Read lock type
+   output [3:0]                        axi_rcache,     // Read Cache type
+   output [2:0]                        axi_rprot,      // Read Protection type
+   output reg                          axi_rvalid,     // Read address valid
+
+// AXI read data channel signals   
+   input  [C_AXI_ID_WIDTH-1:0]         axi_rd_bid,     // Response ID
+   input  [1:0]                        axi_rd_rresp,   // Read response
+   input                               axi_rd_rvalid,  // Read reponse valid
+   input  [C_AXI_DATA_WIDTH-1:0]       axi_rd_data,    // Read data
+   input                               axi_rd_last,    // Read last
+   output reg                          axi_rd_rready   // Read Response ready
+);
+  
+//*****************************************************************************
+// Internal parameter declarations
+//*****************************************************************************
+ 
+  parameter [8:0]                      AXI_WRIDLE    = 9'd0,
+                                       AXI_WRCTL     = 9'd1,
+                                       AXI_WRRDY     = 9'd2,
+                                       AXI_WRDAT     = 9'd3,
+                                       AXI_WRDAT_WT  = 9'd4,
+                                       AXI_WRDAT_LST = 9'd5,
+                                       AXI_WRDAT_DMY = 9'd6,
+                                       AXI_WRRESP_WT = 9'd7,
+                                       AXI_WRTO      = 9'd8;
+
+  parameter [5:0]                      AXI_RDIDLE    = 6'd0,
+                                       AXI_RDCTL     = 6'd1,
+                                       AXI_RDDAT     = 6'd2,
+                                       AXI_RDDAT_LST = 6'd3,
+                                       AXI_RDDAT_WT  = 6'd4,
+                                       AXI_RDTO      = 6'd5;
+
+//*****************************************************************************
+// Internal register and wire declarations
+//*****************************************************************************
+  
+  reg                                  wrap_w;
+  reg [7:0]                            blen_w;
+  reg [7:0]                            blen_w_minus_1;
+  reg [C_AXI_ADDR_WIDTH-1:0]           addr_w;
+  reg [CTL_SIG_WIDTH-1:0]              ctl_w;
+  reg                                  wrap_r;
+  reg [7:0]                            blen_r;
+  reg [C_AXI_ADDR_WIDTH-1:0]           addr_r;
+  reg [CTL_SIG_WIDTH-1:0]              ctl_r;
+  reg [8:0]                            wstate;
+  reg [8:0]                            next_wstate;
+  reg                                  wr_cmd_start;
+  reg [WDG_TIMER_WIDTH-1:0]            wr_wdog_cntr;
+  reg                                  wrdata_vld_r;
+  reg                                  wrdata_cmptd_r;
+  reg [7:0]                            wr_len_cntr;
+  reg [7:0]                            rd_len_cntr;
+  reg [7:0]                            blen_cntr;
+  reg [3:0]                            wr_cntr;
+  reg [C_AXI_DATA_WIDTH-1:0]           wrdata_r1;
+  reg [C_AXI_DATA_WIDTH-1:0]           wrdata_r2;
+  reg                                  wrdata_mux_ctrl;
+  reg [2:0]                            wrdata_fsm_sts;
+  reg [3:0]                            brespid_r;
+  reg [1:0]                            bresp_r;
+
+  reg [5:0]                            rstate;
+  reg [5:0]                            next_rstate;
+  reg [WDG_TIMER_WIDTH-1:0]            rd_wdog_cntr;
+  reg                                  rd_cmd_start;
+  reg                                  rlast;
+  reg [3:0]                            rd_cntr;
+  reg                                  rddata_ppld;
+  reg [C_AXI_DATA_WIDTH-1:0]           rddata_p1;
+  reg                                  err_resp;
+  reg [1:0]                            rddata_fsm_sts;
+  reg                                  rrid_err;
+  reg                                  pending_one_trans;
+  reg                                  axi_wready_l;
+
+  wire                                 wr_cmd_timeout;
+  wire                                 wr_done;
+  wire                                 wr_last;
+
+  wire                                 rd_cmd_timeout;
+
+//*****************************************************************************
+// Address and control register logic
+//*****************************************************************************
+
+  always @(posedge aclk) begin
+    if (!aresetn) begin
+      wrap_w <= 1'b0; 
+      blen_w <= 8'h0;
+      blen_w_minus_1 <= 8'h0;
+      addr_w <= {C_AXI_ADDR_WIDTH{1'b0}};
+      ctl_w  <= {CTL_SIG_WIDTH{1'b0}};
+    end
+    else if (wstate[AXI_WRIDLE] & next_wstate[AXI_WRIDLE] & 
+        cmd_en & cmd[2]) begin
+      wrap_w <= cmd[0]; 
+      blen_w <= blen;
+      blen_w_minus_1 <= blen - 8'h01;
+      addr_w <= addr;
+      ctl_w  <= ctl;
+    end
+  end 
+
+  always @(posedge aclk) begin
+    if (!aresetn) begin
+      wrap_r <= 1'b0; 
+      blen_r <= 8'h0;
+      addr_r <= {C_AXI_ADDR_WIDTH{1'b0}};
+      ctl_r  <= {CTL_SIG_WIDTH{1'b0}};
+    end
+    else if (rstate[AXI_RDIDLE] & next_rstate[AXI_RDIDLE] & 
+        cmd_en & !cmd[2]) begin
+      wrap_r <= cmd[0]; 
+      blen_r <= blen;
+      addr_r <= addr;
+      ctl_r  <= ctl;
+    end
+  end 
+
+  assign cmd_ack = (wstate[AXI_WRIDLE] & next_wstate[AXI_WRCTL]) |
+                   (rstate[AXI_RDIDLE] & next_rstate[AXI_RDCTL]);
+  
+//*****************************************************************************
+// Write data state machine control signals
+//*****************************************************************************
+
+  always @(posedge aclk)
+    if (!aresetn)
+      wr_cmd_start <= 1'b0;
+    else if (cmd_en & cmd[2] & wstate[AXI_WRIDLE])
+      wr_cmd_start <= 1'b1;
+    else if (wstate[AXI_WRCTL])
+      wr_cmd_start <= 1'b0;
+      
+  always @(posedge aclk)
+    if (wstate[AXI_WRIDLE] | 
+        (axi_wd_wready & (wstate[AXI_WRDAT] | wstate[AXI_WRDAT_WT] | wstate[AXI_WRDAT_LST] | wstate[AXI_WRDAT_DMY])) |
+        (axi_wd_bvalid & wstate[AXI_WRRESP_WT])) 
+      wr_wdog_cntr <= 'h0;
+    else if (!wstate[AXI_WRTO] & !wdog_mask)
+      wr_wdog_cntr <= wr_wdog_cntr + 'h1;
+
+  always @(posedge aclk)
+    wrdata_vld_r <= wrdata_vld;
+
+  always @(posedge aclk)
+    if (wstate[AXI_WRIDLE])    
+      wrdata_cmptd_r <= 1'b0;
+    else if (wrdata_cmptd & wrdata_vld)
+      wrdata_cmptd_r <= 1'b1;
+
+  always @(posedge aclk)
+    if (wstate[AXI_WRIDLE])    
+      blen_cntr <= 8'h0; 
+    else if (wrdata_vld & wrdata_rdy)
+      blen_cntr <= blen_cntr + 8'h01; 
+
+  always @(posedge aclk)
+    if (wstate[AXI_WRIDLE])    
+      pending_one_trans <= 1'b0; 
+    else if (next_wstate[AXI_WRDAT] & wstate[AXI_WRDAT_WT])
+      pending_one_trans <= 1'b0; 
+    else if (wstate[AXI_WRDAT] & next_wstate[AXI_WRDAT_WT] & wr_last & !axi_wd_wready)
+      pending_one_trans <= 1'b1; 
+
+  always @(posedge aclk)
+    if (wstate[AXI_WRIDLE])    
+      wr_len_cntr <= 8'h0; 
+    else if ((wstate[AXI_WRDAT_DMY] | wstate[AXI_WRDAT] | wstate[AXI_WRDAT_WT]) & 
+             axi_wd_valid & axi_wd_wready)             
+      wr_len_cntr <= wr_len_cntr + 8'h01;
+
+  always @(posedge aclk)
+    if (wstate[AXI_WRIDLE])    
+      axi_wready_l <= 1'b0; 
+    else if (axi_wready)
+      axi_wready_l <= 1'b1; 
+
+  assign wr_cmd_timeout = wr_wdog_cntr[WDG_TIMER_WIDTH-1] & !wdog_mask; 
+  assign wr_last        = (wr_len_cntr >= blen_w_minus_1);
+  assign wr_done        = (blen_cntr >= blen_w);
+
+//*****************************************************************************
+// Write data state machine
+//*****************************************************************************
+
+  always @(posedge aclk) begin
+    if (!aresetn)
+      wstate <= 9'h1;
+    else 
+      wstate <= next_wstate;
+  end
+
+  always @(*) begin
+    next_wstate = 9'h0;
+    case (1'b1)
+      wstate[AXI_WRIDLE]: begin // 9'h001
+        if (wr_cmd_start)
+          next_wstate[AXI_WRCTL] = 1'b1;
+        else
+          next_wstate[AXI_WRIDLE] = 1'b1;
+      end
+      wstate[AXI_WRCTL]: begin // 9'h002
+        if (wr_cmd_timeout)
+          next_wstate[AXI_WRTO] = 1'b1;
+        else if (axi_wvalid)
+          next_wstate[AXI_WRRDY] = 1'b1;
+        else
+          next_wstate[AXI_WRCTL] = 1'b1;
+      end 
+      wstate[AXI_WRRDY]: begin // 9'h004
+        if (wrdata_cmptd_r & wrdata_rdy)
+          next_wstate[AXI_WRDAT_LST] = 1'b1;
+        else if (wrdata_vld_r & wrdata_rdy)
+          next_wstate[AXI_WRDAT] = 1'b1;
+        else
+          next_wstate[AXI_WRRDY] = 1'b1;
+      end
+      wstate[AXI_WRDAT]: begin // 9'h008
+        if (wr_cmd_timeout)
+          next_wstate[AXI_WRTO] = 1'b1;
+        else if (axi_wd_wready & wrdata_cmptd_r & (wr_last | ~(|blen_w)))
+          next_wstate[AXI_WRDAT_LST] = 1'b1;
+        else if (axi_wd_wready & wrdata_cmptd_r & !wr_done & 
+                 (wr_len_cntr != 8'h00))
+          next_wstate[AXI_WRDAT_DMY] = 1'b1;
+        else if (!axi_wd_wready)
+          next_wstate[AXI_WRDAT_WT] = 1'b1;
+        else
+          next_wstate[AXI_WRDAT] = 1'b1;
+      end
+      wstate[AXI_WRDAT_WT]: begin // 9'h010
+        if (wr_cmd_timeout)
+          next_wstate[AXI_WRTO] = 1'b1;
+        else if (axi_wd_wready) begin
+          if (pending_one_trans & wrdata_cmptd_r & (wr_last | ~(|blen_w)))
+            next_wstate[AXI_WRDAT_LST] = 1'b1;
+          else if (!pending_one_trans & wrdata_cmptd_r & !wr_done & 
+                   (wr_len_cntr != 8'h00))
+            next_wstate[AXI_WRDAT_DMY] = 1'b1;
+          else
+            next_wstate[AXI_WRDAT] = 1'b1;
+        end
+        else
+          next_wstate[AXI_WRDAT_WT] = 1'b1;
+      end
+      wstate[AXI_WRDAT_LST]: begin // 9'h020
+        if (wr_cmd_timeout)
+          next_wstate[AXI_WRTO] = 1'b1;
+        else if (axi_wd_valid & axi_wd_wready)
+          next_wstate[AXI_WRRESP_WT] = 1'b1;
+        else
+          next_wstate[AXI_WRDAT_LST] = 1'b1;
+      end
+      wstate[AXI_WRDAT_DMY]: begin // 9'h040
+        if (wr_cmd_timeout)
+          next_wstate[AXI_WRTO] = 1'b1;
+        else if (wrdata_cmptd_r & wr_last)
+          next_wstate[AXI_WRDAT_LST] = 1'b1;
+        else if (!wr_last & !axi_wd_wready)
+          next_wstate[AXI_WRDAT_WT] = 1'b1;  
+        else
+          next_wstate[AXI_WRDAT_DMY] = 1'b1;  
+      end
+      wstate[AXI_WRRESP_WT]: begin // 9'h080
+        if (wr_cmd_timeout)
+          next_wstate[AXI_WRTO] = 1'b1;
+        else if (axi_wd_bvalid & 
+                 (EN_UPSIZER == 1 || (EN_UPSIZER == 0 & axi_wready_l)))
+          next_wstate[AXI_WRIDLE] = 1'b1;
+        else
+          next_wstate[AXI_WRRESP_WT] = 1'b1;
+      end
+      wstate[AXI_WRTO]: begin // 9'h100
+        next_wstate[AXI_WRIDLE] = 1'b1;
+      end
+    endcase
+  end
+
+//*****************************************************************************
+// Write channel control signals
+//*****************************************************************************
+
+  always @(posedge aclk)
+    if (!aresetn)
+      wr_cntr <= 4'h0;
+    else if (wstate[AXI_WRRESP_WT] & next_wstate[AXI_WRIDLE])
+      wr_cntr <= wr_cntr + 4'h1;
+
+  always @(posedge aclk)
+    if (!aresetn)
+      axi_wvalid <= 1'b0;
+    else if ((wstate[AXI_WRCTL] & next_wstate[AXI_WRRDY] & axi_wready) ||
+             (axi_wready & !wstate[AXI_WRCTL]))
+      axi_wvalid <= 1'b0;
+    else if (wstate[AXI_WRCTL])
+      axi_wvalid <= 1'b1;
+
+  assign awid = wr_cntr;
+  
+  assign axi_waddr = addr_w;
+  assign axi_wid   = wr_cntr;
+  assign axi_wlen  = blen_w;
+  assign axi_wburst = {1'b0, wrap_w} + 2'b01;
+  assign axi_wsize = ctl_w[2:0];
+
+// Not supported and hence assigned zeros
+  assign axi_wlock = 2'b0;
+  assign axi_wcache = 4'b0;
+  assign axi_wprot = 3'b0;
+
+//*****************************************************************************
+// Write channel data signals
+//*****************************************************************************
+
+  always @(posedge aclk) begin
+    if (wstate[AXI_WRIDLE]) begin
+      wrdata_r1 <= 'h0;
+      wrdata_r2 <= 'h0; 
+    end
+    else if (wrdata_rdy & wrdata_vld & (wstate[AXI_WRDAT] | wstate[AXI_WRRDY] | 
+             wstate[AXI_WRDAT_LST])) begin
+      wrdata_r1 <= wrdata;
+      wrdata_r2 <= wrdata_r1; 
+    end 
+  end
+  
+  always @(posedge aclk)
+    if (!aresetn)
+      wrdata_rdy <= 1'b0;
+    else if (wstate[AXI_WRDAT_LST] | (wstate[AXI_WRDAT] & next_wstate[AXI_WRDAT_WT]))
+      wrdata_rdy <= 1'b0;
+    else if (wstate[AXI_WRDAT] | 
+             (wstate[AXI_WRCTL] & next_wstate[AXI_WRRDY]) |
+             (wstate[AXI_WRDAT_WT] & next_wstate[AXI_WRDAT])) 
+      wrdata_rdy <= 1'b1;
+
+  always @(posedge aclk)
+    if (!aresetn)
+      wrdata_sts_vld <= 1'b0;
+    else if (wstate[AXI_WRIDLE])
+      wrdata_sts_vld <= 1'b0;
+    else if ((wstate[AXI_WRRESP_WT] | wstate[AXI_WRTO]) & next_wstate[AXI_WRIDLE])
+      wrdata_sts_vld <= 1'b1;
+
+  always @(posedge aclk)
+    if (!aresetn)
+      wrdata_mux_ctrl <= 1'b0;
+    else if ((wstate[AXI_WRDAT_WT] & (next_wstate[AXI_WRDAT] | next_wstate[AXI_WRDAT_LST])) |
+             wstate[AXI_WRIDLE])
+      wrdata_mux_ctrl <= 1'b0;
+    else if (wstate[AXI_WRDAT] & next_wstate[AXI_WRDAT_WT] & !pending_one_trans)
+      wrdata_mux_ctrl <= 1'b1;
+
+  always @(posedge aclk)
+    if (!aresetn)
+      axi_wd_last <= 1'b0;
+    else if (wstate[AXI_WRDAT_LST] & next_wstate[AXI_WRRESP_WT])
+      axi_wd_last <= 1'b0;
+    else if ((wstate[AXI_WRDAT] | wstate[AXI_WRDAT_DMY] | wstate[AXI_WRRDY] | wstate[AXI_WRDAT_WT]) & 
+             next_wstate[AXI_WRDAT_LST])
+      axi_wd_last <= 1'b1;
+
+  generate 
+    begin: data_axi_wr
+      if (C_AXI_NBURST_SUPPORT != 1) begin
+        
+        always @(posedge aclk)
+          if (wstate[AXI_WRIDLE])
+            axi_wd_data <= 'h0;
+          else if (axi_wd_wready & (wstate[AXI_WRDAT] | wstate[AXI_WRDAT_WT]) & wrdata_mux_ctrl &
+                   ~next_wstate[AXI_WRDAT_LST])
+            axi_wd_data <= wrdata_r2;
+          else if ((axi_wd_wready & (wstate[AXI_WRDAT] | 
+                                    (wstate[AXI_WRDAT_WT] & next_wstate[AXI_WRDAT_LST]) | 
+                                    (wstate[AXI_WRDAT_LST] & !next_wstate[AXI_WRRESP_WT]))) |
+                                    (wstate[AXI_WRRDY] & next_wstate[AXI_WRDAT]))
+            axi_wd_data <= wrdata_r1;
+
+        always @(posedge aclk)
+          if (wstate[AXI_WRIDLE])
+            axi_wd_strb <= {(C_AXI_DATA_WIDTH/8){1'b0}};
+          else if ((axi_wd_wready & (wstate[AXI_WRDAT] | 
+                                    (next_wstate[AXI_WRDAT_LST] & (wstate[AXI_WRRDY] | wstate[AXI_WRDAT])) |
+                                    ((wstate[AXI_WRRDY] | wstate[AXI_WRDAT_WT]) & 
+                                     next_wstate[AXI_WRDAT]))) | 
+                   (next_wstate[AXI_WRDAT_LST] & !axi_wd_wready & 
+                    (wstate[AXI_WRDAT] | wstate[AXI_WRDAT_LST] | 
+                     wstate[AXI_WRDAT_DMY] | wstate[AXI_WRDAT_WT])) |
+                   (wstate[AXI_WRRDY] & next_wstate[AXI_WRDAT]) | 
+                   ((wstate[AXI_WRDAT] | wstate[AXI_WRDAT_DMY]) & next_wstate[AXI_WRDAT_WT]) | 
+                   (wstate[AXI_WRDAT_WT])) 
+            axi_wd_strb <= {(C_AXI_DATA_WIDTH/8){1'b1}};
+          else
+            axi_wd_strb <= {(C_AXI_DATA_WIDTH/8){1'b0}};
+
+      end
+    end
+  endgenerate
+
+  assign axi_wd_wid = wr_cntr;
+  assign axi_wd_valid = wstate[AXI_WRDAT] | wstate[AXI_WRDAT_LST] | 
+                        wstate[AXI_WRDAT_DMY] | wstate[AXI_WRDAT_WT];
+
+//*****************************************************************************
+// Write response and status signals
+//*****************************************************************************
+
+  always @(posedge aclk)
+    if (!aresetn)
+      axi_wd_bready <= 1'b0;
+    else if (next_wstate[AXI_WRIDLE] & wstate[AXI_WRRESP_WT])
+      axi_wd_bready <= 1'b0;
+    else if (wstate[AXI_WRRESP_WT])
+      axi_wd_bready <= 1'b1;
+
+  always @(posedge aclk)
+    if (wstate[AXI_WRIDLE]) 
+      wrdata_fsm_sts <= 3'b000;  
+    else begin
+      if (next_wstate[AXI_WRTO]) begin
+        if (wstate[AXI_WRDAT])
+          wrdata_fsm_sts <= 3'b001;
+        else if (wstate[AXI_WRDAT_WT])
+          wrdata_fsm_sts <= 3'b010;
+        else if (wstate[AXI_WRDAT_DMY])
+          wrdata_fsm_sts <= 3'b011;
+        else if (wstate[AXI_WRRESP_WT])
+          wrdata_fsm_sts <= 3'b100;
+      end
+    end
+
+  always @(posedge aclk)
+    if (wstate[AXI_WRIDLE]) begin 
+      brespid_r <= 4'h0;  
+      bresp_r   <= 2'b00;
+    end
+    else if (wstate[AXI_WRRESP_WT] & axi_wd_bvalid) begin
+      brespid_r <= axi_wd_bid;  
+      bresp_r   <= axi_wd_bresp;
+    end
+
+  assign wrdata_sts = {{{WR_STS_WIDTH-8}{1'b0}},wrdata_fsm_sts,brespid_r[3:0],bresp_r}; 
+
+//*****************************************************************************
+// Read data state machine control signals
+//*****************************************************************************
+
+  always @(posedge aclk)
+    if (rstate[AXI_RDIDLE] | axi_rready | axi_rd_rvalid) 
+      rd_wdog_cntr <= 'h0;
+    else if (!rstate[AXI_RDTO])
+      rd_wdog_cntr <= rd_wdog_cntr + 'h1;
+
+  always @(posedge aclk)
+    if (!aresetn)
+      rd_cmd_start <= 1'b0;
+    else if (cmd_en & !cmd[2] & rstate[AXI_RDIDLE])
+      rd_cmd_start <= 1'b1;
+    else if (rstate[AXI_RDCTL])
+      rd_cmd_start <= 1'b0;
+      
+  always @(posedge aclk)
+    if (rstate[AXI_RDIDLE])
+      rlast <= 1'b0;
+    else if (axi_rd_last & axi_rd_rvalid)
+      rlast <= 1'b1; 
+
+  assign rd_cmd_timeout = rd_wdog_cntr[WDG_TIMER_WIDTH-1] & !wdog_mask; 
+
+//*****************************************************************************
+// Read data state machine
+//*****************************************************************************
+
+  always @(posedge aclk) begin
+    if (!aresetn)
+      rstate <= 6'h1;
+    else 
+      rstate <= next_rstate;
+  end
+
+  always @(*) begin
+    next_rstate = 6'h0;
+    case (1'b1)
+      rstate[AXI_RDIDLE]: begin // 6'h01
+        if (rd_cmd_start)
+          next_rstate[AXI_RDCTL] = 1'b1;
+        else
+          next_rstate[AXI_RDIDLE] = 1'b1;
+      end
+      rstate[AXI_RDCTL]: begin // 6'h02
+        if (rd_cmd_timeout)
+          next_rstate[AXI_RDTO] = 1'b1;
+        else if (axi_rready & axi_rvalid) begin
+          if (rddata_rdy)
+            next_rstate[AXI_RDDAT] = 1'b1;
+          else
+            next_rstate[AXI_RDDAT_WT] = 1'b1;
+        end 
+        else
+          next_rstate[AXI_RDCTL] = 1'b1;
+      end
+      rstate[AXI_RDDAT]: begin // 6'h04
+        if (rd_cmd_timeout)
+          next_rstate[AXI_RDTO] = 1'b1;
+        else if (rddata_rdy) begin
+          if (rlast)
+            next_rstate[AXI_RDDAT_LST] = 1'b1;
+          else
+            next_rstate[AXI_RDDAT] = 1'b1;
+        end
+        else
+          next_rstate[AXI_RDDAT_WT] = 1'b1;
+      end
+      rstate[AXI_RDDAT_LST]: begin // 6'h08
+        if (rddata_cmptd & rddata_vld & rddata_rdy)
+          next_rstate[AXI_RDIDLE] = 1'b1;
+        else      
+          next_rstate[AXI_RDDAT_LST] = 1'b1;
+      end
+      rstate[AXI_RDDAT_WT]: begin // 6'h10
+        if (rddata_rdy) begin
+          if (rlast)
+            next_rstate[AXI_RDDAT_LST] = 1'b1;
+          else
+            next_rstate[AXI_RDDAT] = 1'b1;
+        end
+        else
+          next_rstate[AXI_RDDAT_WT] = 1'b1;
+      end
+      rstate[AXI_RDTO]: begin // 6'h20
+        next_rstate[AXI_RDIDLE] = 1'b1;
+      end
+    endcase
+  end
+
+//*****************************************************************************
+// Read Address control signals
+//*****************************************************************************
+
+  always @(posedge aclk)
+    if (!aresetn)
+      rd_cntr <= 4'h0;
+    else if (rstate[AXI_RDDAT_LST] & next_rstate[AXI_RDIDLE])
+      rd_cntr <= rd_cntr + 4'h1;
+
+  always @(posedge aclk)
+    if (!aresetn)
+      axi_rvalid <= 1'b0;
+    else if (rstate[AXI_RDCTL] & next_rstate[AXI_RDDAT])
+      axi_rvalid <= 1'b0;
+    else if (rstate[AXI_RDCTL])     
+      axi_rvalid <= 1'b1;
+
+  assign axi_rid = rd_cntr; 
+
+  generate 
+    begin: addr_axi_rd
+      if (C_AXI_DATA_WIDTH == 256)
+        assign axi_raddr = {addr_r[C_AXI_ADDR_WIDTH-1:5], 5'b0};
+      else if (C_AXI_DATA_WIDTH == 128)
+        assign axi_raddr = {addr_r[C_AXI_ADDR_WIDTH-1:4], 4'b0};
+      else if (C_AXI_DATA_WIDTH == 64)
+        assign axi_raddr = {addr_r[C_AXI_ADDR_WIDTH-1:3], 3'b0};
+      else
+        assign axi_raddr = {addr_r[C_AXI_ADDR_WIDTH-1:2], 2'b0};
+    end
+  endgenerate
+
+  assign axi_rlen = blen_r;
+  assign axi_rburst = {1'b0, wrap_r} + 2'b01;
+  assign axi_rsize = ctl_r[2:0];
+
+// Not supported and hence assigned zeros
+  assign axi_rlock = 2'b0;
+  assign axi_rcache = 4'b0;
+  assign axi_rprot = 3'b0; 
+
+//*****************************************************************************
+// Read channel data signals
+//*****************************************************************************
+
+  always @(posedge aclk)
+    if (!aresetn)
+      rddata_vld <= 1'b0;
+    else if ((rddata_vld & !axi_rd_rvalid & rstate[AXI_RDDAT]) |
+             (rddata_rdy & rstate[AXI_RDDAT_LST]) | 
+             (rstate[AXI_RDDAT_WT] & next_rstate[AXI_RDDAT] & rddata_ppld) | 
+             (rddata_rdy & axi_rd_rvalid & axi_rd_last) |
+             rstate[AXI_RDIDLE])
+      rddata_vld <= 1'b0;
+    else if ((rstate[AXI_RDDAT] & axi_rd_rvalid & !axi_rd_last) |
+             ((rstate[AXI_RDDAT] | rstate[AXI_RDDAT_WT]) & next_rstate[AXI_RDDAT_LST] & rlast) |
+             (rstate[AXI_RDDAT_LST] & axi_rd_rvalid & axi_rd_last & axi_rd_rready) | 
+             rstate[AXI_RDTO])
+      rddata_vld <= 1'b1;
+
+  always @(posedge aclk)
+    if (!aresetn)
+      rddata_ppld <= 1'b0;
+    else if (rddata_vld & rddata_rdy)
+      rddata_ppld <= 1'b0;
+    else if (!rddata_vld & axi_rd_rvalid & axi_rd_rready & rstate[AXI_RDDAT_WT])
+      rddata_ppld <= 1'b1;
+
+  always @(posedge aclk)
+    if (!aresetn)
+      axi_rd_rready <= 1'b0;
+    else if (rstate[AXI_RDIDLE] |
+             (rstate[AXI_RDDAT] & next_rstate[AXI_RDDAT_WT]) |
+             (rstate[AXI_RDDAT_WT] & !next_rstate[AXI_RDDAT] & rddata_ppld) |
+             (next_rstate[AXI_RDDAT_LST] & (rstate[AXI_RDDAT] | rstate[AXI_RDDAT_WT])))
+      axi_rd_rready <= 1'b0;
+    else if ((next_rstate[AXI_RDDAT] & (rstate[AXI_RDCTL] | rstate[AXI_RDDAT_WT])) |
+             (next_rstate[AXI_RDDAT_LST] & rstate[AXI_RDDAT_WT] & rddata_ppld) |
+             (rstate[AXI_RDDAT_WT] & !rddata_ppld) |
+             (rstate[AXI_RDDAT_LST] & axi_rd_rvalid & axi_rd_last))
+      axi_rd_rready <= 1'b1;
+
+  always @(posedge aclk)
+    if (axi_rd_rvalid)
+      rddata_p1 <= axi_rd_data;
+
+  generate 
+    begin: data_axi_rd
+      if (C_AXI_NBURST_SUPPORT == 1) begin
+      end
+      else begin
+        
+        always @(posedge aclk)
+          if (axi_rd_rvalid & !rddata_ppld)
+            rddata <= axi_rd_data;
+          else if (rddata_rdy & rddata_vld & rddata_ppld)
+            rddata <= rddata_p1;
+
+        assign rddata_bvld = {{C_AXI_DATA_WIDTH/32}{4'hF}};
+
+      end
+    end
+  endgenerate
+
+  always @(posedge aclk)
+    if (!aresetn)
+      rddata_cmptd <= 1'b0;
+    else if ((next_rstate[AXI_RDIDLE] & rstate[AXI_RDDAT_LST]) |
+             rstate[AXI_RDIDLE])
+      rddata_cmptd <= 1'b0;
+    else if (((rstate[AXI_RDDAT] | rstate[AXI_RDDAT_WT]) & next_rstate[AXI_RDDAT_LST] & rlast) |
+             (rstate[AXI_RDDAT_LST] & axi_rd_rvalid & axi_rd_last & axi_rd_rready) | 
+             rstate[AXI_RDTO])
+      rddata_cmptd <= 1'b1;
+
+  always @(posedge aclk)
+    if (rstate[AXI_RDIDLE])
+      err_resp <= 1'b0;
+    else if (axi_rd_rvalid & axi_rd_rresp[1])
+      err_resp <= 1'b1;
+
+  always @(posedge aclk)
+    if (rstate[AXI_RDIDLE] & next_rstate[AXI_RDCTL])
+      rddata_fsm_sts <= 2'b00;
+    else if (rstate[AXI_RDCTL] & next_rstate[AXI_RDTO])
+      rddata_fsm_sts <= 2'b01;
+    else if (rstate[AXI_RDDAT] & next_rstate[AXI_RDTO])
+      rddata_fsm_sts <= 2'b10;
+  
+  always @(posedge aclk)
+    if (rstate[AXI_RDIDLE] & next_rstate[AXI_RDCTL])
+      rrid_err <= 1'b0;
+    else if (axi_rd_rvalid & axi_rd_bid != rd_cntr)
+      rrid_err <= 1'b1;
+
+  always @(posedge aclk)
+    if (rstate[AXI_RDIDLE])    
+      rd_len_cntr <= 8'h0; 
+    else if (axi_rd_rvalid & axi_rd_rready)
+      rd_len_cntr <= rd_len_cntr + 8'h01;
+
+  assign rddata_sts = {{(RD_STS_WIDTH-12){1'b0}},rd_len_cntr,rddata_fsm_sts,rrid_err,err_resp}; 
+
+// synthesis translate_off
+  always @(posedge aclk) begin
+    if (rd_cmd_timeout)
+      $display ("ERR: Read timeout occured at time %t", $time);
+    if (wr_cmd_timeout)
+      $display ("ERR: Write timeout occured at time %t", $time);
+  end
+// synthesis translate_on
+
+endmodule

cx9261a_demo_cmos_20240829/project_fix_dac.srcs/sources_1/bd/system_top/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/example_design/rtl/traffic_gen/mig_7series_v4_2_cmd_prbs_gen_axi.v

@@ -0,0 +1,250 @@
+//*****************************************************************************
+// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//*****************************************************************************
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /    Vendor: Xilinx
+// \   \   \/     Version: %version
+//  \   \         Application: MIG
+//  /   /         Filename: cmd_prbs_gen.v
+// /___/   /\     Date Last Modified:
+// \   \  /  \    Date Created:
+//  \___\/\___\
+//
+//Device: Spartan6
+//Design Name: DDR/DDR2/DDR3/LPDDR
+//Purpose:  This moduel use LFSR to generate random address, isntructions
+//          or burst_length.
+//Reference:
+//Revision History:     1.1 Added condition to zero out the LSB address bits according to
+//                      DWIDTH and FAMILY. 7/9/2009       
+//
+//*****************************************************************************
+
+`timescale 1ps/1ps
+
+module mig_7series_v4_2_cmd_prbs_gen_axi #
+  (
+   parameter TCQ                 = 100,
+   parameter FAMILY              = "SPARTAN6",
+   parameter ADDR_WIDTH          = 29,
+   parameter DWIDTH              = 32,
+   parameter PRBS_CMD            = "ADDRESS", // "INSTR", "BLEN","ADDRESS"
+   parameter PRBS_WIDTH          = 64,        //   64,15,20
+   parameter SEED_WIDTH          = 32,        //   32,15,4
+
+   parameter PRBS_EADDR_MASK_POS = 32'hFFFFD000,
+   parameter PRBS_SADDR_MASK_POS = 32'h00002000,
+   parameter PRBS_EADDR          = 32'h00002000,
+   parameter PRBS_SADDR          = 32'h00002000
+   )
+  (
+   input                         clk_i,
+   input                         prbs_seed_init,  // when high the prbs_x_seed will be loaded
+   input                         clk_en,
+   input [SEED_WIDTH-1:0]        prbs_seed_i,
+   output[SEED_WIDTH-1:0]        prbs_o           // generated address
+  );
+
+  wire[ADDR_WIDTH - 1:0]         ZEROS;
+  reg [SEED_WIDTH - 1:0]         prbs;
+  reg [PRBS_WIDTH :1]            lfsr_q;
+
+assign ZEROS = 'b0;
+//
+//**************************************************************
+//####################################################################################################################
+//                                                                                                                   #
+//                                                                                                                   #
+// 64 taps: [64,63,61,60]: {{8'b01011000}, {56'b0}}                                                                  #
+//  upper 32 bits are loadable                                                                                       #
+//                                                                                                                   #
+//
+//
+//     ........................................................................................
+//         ^                  ^                      ^             ^                          |
+//         |   ____           |  ___     ___         | ___         |  ___     ___     ___     |
+//         |   |   |   |---|<-  |   |   |   | |---|<- |   |  |---|<- |   |...|   |   |   |    |  The first 32 bits are parallel loadable.
+//         ----|64 |<--|xor|<-- |63 |-->|62 |-|xor|<--|61 |<-|xor|<--|60 |...|33 |<--|1|<<--
+//             |___|    ---     |___|   |___|  ---    |___|   ---    |___|...|___|   |___|
+//
+//
+//                                           <<-- shifting  --
+//#####################################################################################################################
+
+// use SRLC32E for lower 32 stages and 32 registers for upper 32 stages.
+// we need to provide 30 bits addres. SRLC32 has only one bit output.
+// address seed will be loaded to upper 32 bits.
+//
+//  parallel load and serial shift out to  LFSR  during INIT time
+
+generate
+  if(PRBS_CMD == "ADDRESS" && PRBS_WIDTH == 64) begin :gen64_taps
+    always @ (posedge clk_i) begin
+      if(prbs_seed_init) begin//reset it to a known good state to prevent it locks up
+        lfsr_q <= #TCQ {31'b0,prbs_seed_i};
+      end else if(clk_en) begin
+        lfsr_q[64] <= #TCQ lfsr_q[64] ^ lfsr_q[63];
+        lfsr_q[63] <= #TCQ lfsr_q[62];
+        lfsr_q[62] <= #TCQ lfsr_q[64] ^ lfsr_q[61];
+        lfsr_q[61] <= #TCQ lfsr_q[64] ^ lfsr_q[60];
+        lfsr_q[60:2] <= #TCQ lfsr_q[59:1];
+        lfsr_q[1] <= #TCQ lfsr_q[64];
+      end
+    end
+
+    always @(lfsr_q[32:1]) begin
+      prbs = lfsr_q[32:1];
+    end
+  end
+endgenerate
+
+function integer logb2;
+  input [31:0] in;
+  integer i;
+  begin
+    i = in;
+      for(logb2=1; i>0; logb2=logb2+1)
+        i = i >> 1;
+  end
+endfunction
+
+generate
+  if(PRBS_CMD == "ADDRESS" && PRBS_WIDTH == 32) begin :gen32_taps
+    always @ (posedge clk_i) begin
+      if(prbs_seed_init) begin //reset it to a known good state to prevent it locks up
+        lfsr_q <= #TCQ {prbs_seed_i};
+      end else if(clk_en) begin
+        lfsr_q[32:9] <= #TCQ lfsr_q[31:8];
+        lfsr_q[8]    <= #TCQ lfsr_q[32] ^ lfsr_q[7];
+        lfsr_q[7]    <= #TCQ lfsr_q[32] ^ lfsr_q[6];
+        lfsr_q[6:4]  <= #TCQ lfsr_q[5:3];
+
+        lfsr_q[3]    <= #TCQ lfsr_q[32] ^ lfsr_q[2];
+        lfsr_q[2]    <= #TCQ lfsr_q[1] ;
+        lfsr_q[1]    <= #TCQ lfsr_q[32];
+      end
+    end
+
+    integer i;
+    always @(lfsr_q[32:1]) begin
+    
+     if (FAMILY == "SPARTAN6" ) begin  // for 32 bits
+    
+      for(i = logb2(DWIDTH) + 1; i <= SEED_WIDTH - 1; i = i + 1)
+
+       if(PRBS_SADDR_MASK_POS[i] == 1)
+          prbs[i] = PRBS_SADDR[i] | lfsr_q[i+1];
+       else if(PRBS_EADDR_MASK_POS[i] == 1)
+          prbs[i] = PRBS_EADDR[i] & lfsr_q[i+1];
+       else
+          prbs[i] =  lfsr_q[i+1];
+          
+       prbs[logb2(DWIDTH )  :0] = {logb2(DWIDTH ) + 1{1'b0}};         
+
+      end
+    else begin
+     for(i = logb2(DWIDTH)-4; i <= SEED_WIDTH - 1; i = i + 1)
+       if(PRBS_SADDR_MASK_POS[i] == 1)
+          prbs[i] = PRBS_SADDR[i] | lfsr_q[i+1];
+       else if(PRBS_EADDR_MASK_POS[i] == 1)
+          prbs[i] = PRBS_EADDR[i] & lfsr_q[i+1];
+       else
+          prbs[i] =  lfsr_q[i+1];
+     prbs[logb2(DWIDTH)-5:0] = {logb2(DWIDTH) - 4{1'b0}};
+
+    end  
+ 
+  end  
+end endgenerate
+
+//////////////////////////////////////////////////////////////////////////
+//####################################################################################################################
+//                                                                                                                   #
+//                                                                                                                   #
+// 15 taps: [15,14]:                                                                                                 #
+//                                                                                         #
+//                                                                                                                   #
+//
+//
+//         .............................................................
+//         ^                  ^              .                           ^
+//         |   ____           |  ___     ___     ___     ___     ___     |
+//         |   |   |   |---|<-  |   |   |   |   |   |...|   |   |   |    |
+//         ----|15 |<--|xor|<-- |14 |<--|13 |<--|12 |...|2  |<--|1  |<<--
+//             |___|    ---     |___|   |___|   |___|...|___|   |___|
+//
+//
+//                                           <<-- shifting  --
+//#####################################################################################################################
+
+generate
+  if(PRBS_CMD == "INSTR" | PRBS_CMD == "BLEN") begin :gen20_taps
+    always @(posedge clk_i) begin
+      if(prbs_seed_init) begin//reset it to a known good state to prevent it locks up
+        lfsr_q <= #TCQ {5'b0,prbs_seed_i[14:0]};
+      end else if(clk_en) begin
+        lfsr_q[20]   <= #TCQ lfsr_q[19];
+        lfsr_q[19]   <= #TCQ lfsr_q[18];
+
+        lfsr_q[18]   <= #TCQ lfsr_q[20] ^lfsr_q[17];
+
+        lfsr_q[17:2] <= #TCQ lfsr_q[16:1];
+        lfsr_q[1]    <= #TCQ lfsr_q[20];
+      end
+    end
+
+    always @ (lfsr_q) begin
+      prbs = lfsr_q[32:1];
+    end
+  end
+endgenerate
+
+assign prbs_o = prbs;
+
+endmodule

cx9261a_demo_cmos_20240829/project_fix_dac.srcs/sources_1/bd/system_top/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/example_design/rtl/traffic_gen/mig_7series_v4_2_data_gen_chk.v

@@ -0,0 +1,193 @@
+//*****************************************************************************
+// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//*****************************************************************************
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /    Vendor: Xilinx
+// \   \   \/     Version: %version
+//  \   \         Application: MIG
+//  /   /         Filename: data_gen_chk.v
+// /___/   /\     Date Last Modified: $Date: 2011/06/02 08:37:19 $
+// \   \  /  \    Date Created: Fri Sep 01 2006
+//  \___\/\___\
+//
+//Device: Virtex6/Spartan6/7series
+//Design Name: DDR/DDR2/DDR3/LPDDR 
+//Purpose:  This module is used LFSR to generate random data for memory 
+//          data write or memory data read comparison. This always 
+//          generates 32-bit data only. This also checks the received 
+//          data
+//Reference:
+//Revision History:
+//*****************************************************************************
+`timescale 1ps/1ps
+
+module mig_7series_v4_2_data_gen_chk # (
+
+  parameter C_AXI_DATA_WIDTH     = 32 // Width of the AXI write and read data
+  
+  ) 
+  (
+   input                          clk,
+   input                          data_en,
+   input [2:0]                    data_pattern,
+   input                          pattern_init,    // when high the patterns are initialized
+   input [31:0]                   prbs_seed_i,
+   input [C_AXI_DATA_WIDTH-1:0]   rdata,
+   input [C_AXI_DATA_WIDTH/8-1:0] rdata_bvld,
+   input                          rdata_vld,
+   input                          wrd_cntr_rst,
+   output                         msmatch_err,     // Indicates there is a mismatch error
+   output reg [7:0]               wrd_cntr,        // Word count output
+   output reg [31:0]              data_o           // generated data
+  );
+  
+  reg [31:0]                      prbs;  
+  reg [32:1]                      lfsr_q;
+  reg [31:0]                      walk0;
+  reg [31:0]                      walk1;
+  reg [C_AXI_DATA_WIDTH/32-1:0]   msmatch_err_sig;
+
+//*****************************************************************************
+// Data generate segment
+//*****************************************************************************
+
+  always @ (posedge clk) begin
+    if (pattern_init) begin
+      lfsr_q <= {prbs_seed_i + 32'h55555555};
+    end
+    else if (data_en) begin
+      lfsr_q[32:9] <= lfsr_q[31:8];
+      lfsr_q[8]    <= lfsr_q[32] ^ lfsr_q[7];
+      lfsr_q[7]    <= lfsr_q[32] ^ lfsr_q[6];
+      lfsr_q[6:4]  <= lfsr_q[5:3];
+      
+      lfsr_q[3]    <= lfsr_q[32] ^ lfsr_q[2];
+      lfsr_q[2]    <= lfsr_q[1] ;
+      lfsr_q[1]    <= lfsr_q[32];
+    end
+  end
+  
+  always @(posedge clk)
+    if (pattern_init)
+      walk0 <= 32'hFFFF_FFFE;
+    else if (data_en)
+      walk0 <= {walk0[30:0],walk0[31]};
+  
+  always @(posedge clk)
+    if (pattern_init)
+      walk1 <= 32'h0000_0001;
+    else if (data_en)
+      walk1 <= {walk1[30:0],walk1[31]};
+  
+  always @(*) begin
+    prbs = lfsr_q[32:1];
+  end
+  
+  always @(*) begin
+    case (data_pattern)
+      3'b001: data_o = prbs; // PRBS pattern
+      3'b010: data_o = walk0; // Walking zeros
+      3'b011: data_o = walk1; // Walking ones
+      3'b100: data_o = 32'hFFFF_FFFF; // All ones
+      3'b101: data_o = 32'h0000_0000; // All zeros
+      default: data_o = 32'h5A5A_A5A5;
+    endcase
+  end
+
+//*****************************************************************************
+// Data check segment
+//*****************************************************************************
+
+  always @(posedge clk)
+    if (wrd_cntr_rst)
+      wrd_cntr <= 8'h00;
+    else if (rdata_vld)
+      wrd_cntr <= wrd_cntr + 8'h01;
+  
+  genvar i;
+  generate 
+    begin: data_check
+      for (i = 0; i <= (C_AXI_DATA_WIDTH/32-1); i=i+1) begin: gen_data_check
+        always @(posedge clk)
+          if (wrd_cntr_rst)
+            msmatch_err_sig[i] <= 1'b0;
+          else if (rdata_vld & 
+                   ((rdata[((i*32)+7):i*32] != data_o[7:0] & rdata_bvld[(i*4)]) |
+                    (rdata[((i*32)+15):((i*32)+8)] != data_o[15:8] & rdata_bvld[(i*4)+1]) |
+                    (rdata[((i*32)+23):((i*32)+16)] != data_o[23:16] & rdata_bvld[(i*4)+2]) |
+                    (rdata[((i*32)+31):((i*32)+24)] != data_o[31:24] & rdata_bvld[(i*4)+3])))
+            msmatch_err_sig[i] <= 1'b1;
+          else
+            msmatch_err_sig[i] <= 1'b0;
+      end
+    end
+  endgenerate
+
+  assign msmatch_err = |msmatch_err_sig;
+
+// synthesis translate_off
+//*****************************************************************************
+// Simulation debug signals and messages
+//*****************************************************************************
+ 
+  always @(posedge clk) begin
+    if (rdata_vld & ({{C_AXI_DATA_WIDTH/32}{data_o}} !== rdata)) begin
+      $display ("[ERROR] : Written data and read data does not match");
+      $display ("Data written : %h", {{C_AXI_DATA_WIDTH/32}{data_o}});
+      $display ("Data read    : %h", rdata);
+      $display ("Word number  : %h", wrd_cntr);
+      $display ("Simulation time : %t", $time);
+    end 
+  end
+
+// synthesis translate_on
+
+endmodule
+   
+         

cx9261a_demo_cmos_20240829/project_fix_dac.srcs/sources_1/bd/system_top/ip/system_top_mig_7series_0_0/system_top_mig_7series_0_0/example_design/rtl/traffic_gen/mig_7series_v4_2_tg.v

@@ -0,0 +1,780 @@
+//*****************************************************************************
+// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//*****************************************************************************
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /    Vendor: Xilinx
+// \   \   \/     Version: 3.6
+//  \   \         Application: MIG
+//  /   /         Filename: tg.v
+// /___/   /\     Date Last Modified: $Date: 2011/06/02 08:37:24 $
+// \   \  /  \    Date Created: Sept 16, 2009
+//  \___\/\___\
+//
+//Device: Virtex-6, Spartan-6 and 7series
+//Design Name: DDR3 SDRAM
+//Purpose:
+//   This module generates and checks the AXI traffic 
+//
+//Reference:
+//Revision History:
+//*****************************************************************************
+`timescale 1ps/1ps
+
+module mig_7series_v4_2_tg #(
+  
+   parameter C_AXI_ADDR_WIDTH     = 32, // This is AXI address width for all 
+                                        // SI and MI slots
+   parameter C_AXI_DATA_WIDTH     = 32, // Width of the AXI write and read data
+
+   parameter C_AXI_NBURST_SUPPORT = 0, // Support for narrow burst transfers
+                                       // 1-supported, 0-not supported 
+   parameter C_BEGIN_ADDRESS      = 32'h0, // Start address of the address map
+
+   parameter C_END_ADDRESS        = 32'h0000_00FF, // End address of the address map
+ 
+   parameter C_EN_WRAP_TRANS      = 0, // Should be set to 1 for wrap transactions
+
+   parameter CTL_SIG_WIDTH        = 3,  // Control signal width
+
+   parameter WR_STS_WIDTH         = 16, // Write port status signal width
+
+   parameter RD_STS_WIDTH         = 16, // Read port status signal width
+ 
+   parameter DBG_WR_STS_WIDTH     = 40,
+
+   parameter DBG_RD_STS_WIDTH     = 40,
+
+   parameter ENFORCE_RD_WR        = 0,
+
+   parameter ENFORCE_RD_WR_CMD    = 8'h11,
+
+   parameter PRBS_EADDR_MASK_POS  = 32'hFFFFD000,
+
+   parameter PRBS_SADDR_MASK_POS  = 32'h00002000,
+
+   parameter ENFORCE_RD_WR_PATTERN = 3'b000
+
+)
+(
+   input                      clk,          // input clock
+   input                      resetn,       // Active low reset signal
+
+// Input start signals
+   input                      init_cmptd,   // Initialization completed
+   input                      init_test,    // Initialize the test
+   input                      wrap_en,      // Enable wrap transactions
+
+// Control ports
+   input                      cmd_ack,      // Command has been accepted
+   output reg                 cmd_en,       // Command enable
+   output [2:0]               cmd,          // Command
+   output reg [7:0]           blen,         // Length of the burst
+   output reg [31:0]          addr,         // output address
+   output [CTL_SIG_WIDTH-1:0] ctl,          // Control signal
+
+// Write port
+   input                      wdata_rdy,    // Write data ready to be accepted
+   output                     wdata_vld,    // Write data valid
+   output reg                 wdata_cmptd,  // Write data completed
+   output [C_AXI_DATA_WIDTH-1:0] wdata,     // Write data 
+   output [C_AXI_DATA_WIDTH/8-1:0] wdata_bvld, // Byte valids
+   input                      wdata_sts_vld, // Status valid
+   input [WR_STS_WIDTH-1:0]   wdata_sts,     // Write status 
+
+// Read Port
+   input                      rdata_vld,    // Read data valid 
+   input [C_AXI_DATA_WIDTH-1:0] rdata,      // Write data 
+   input [C_AXI_DATA_WIDTH/8-1:0] rdata_bvld, // Byte valids
+   input                      rdata_cmptd,  // Read data completed
+   input [RD_STS_WIDTH-1:0]   rdata_sts,    // Read status
+   output                     rdata_rdy,    // Read data ready
+
+// Error status signals
+   output reg                 cmd_err,      // Error during command phase
+   output reg                 data_msmatch_err, // Data mismatch
+   output reg                 write_err,    // Write error occured
+   output reg                 read_err,     // Read error occured
+   output                     test_cmptd,   // Completed testing with all patterns
+   output                     write_cmptd,  // Completed write operation
+   output                     read_cmptd,   // Completed write operation
+
+// Debug status signals
+   output                     cmp_data_en,
+   output [C_AXI_DATA_WIDTH-1:0] rdata_cmp,   // read data 
+   output reg                 dbg_wr_sts_vld, // Write debug status valid,
+   output [DBG_WR_STS_WIDTH-1:0] dbg_wr_sts,  // Write status
+   output reg                 dbg_rd_sts_vld, // Read debug status valid
+   output [DBG_RD_STS_WIDTH-1:0] dbg_rd_sts   // Read status
+);   
+
+//*****************************************************************************
+// Internal parameter declarations
+//*****************************************************************************
+
+  parameter [8:0]             TG_IDLE       = 8'd0,
+                              TG_GEN_PRBS   = 8'd1,
+                              TG_WR_CMD     = 8'd2,
+                              TG_WR_DATA    = 8'd3,
+                              TG_WR_DONE    = 8'd4,
+                              TG_RD_CMD     = 8'd5,
+                              TG_RD_DATA    = 8'd6,
+                              TG_UPDT_CNTR  = 8'd7;
+
+//*****************************************************************************
+// Internal wire and reg declarations
+//*****************************************************************************
+
+  wire [2:0]                       data_pattern;
+  wire                             dgen_en;
+  wire                             dgen_init;
+  wire [31:0]                      prbs_seed;
+  wire                             msmatch_err;
+  wire [31:0]                      prbs_data;
+  wire [31:0]                      prbs_blen;             
+  wire [7:0]                       prbs_blen_mdfy;             
+  wire [31:0]                      prbs_addr;             
+  wire [31:0]                      prbs_addr_mdfy;
+  wire                             cmd_gen_csr_sig;
+  wire                             rdata_sig_vld;
+  wire                             wdata_sig_vld;
+  reg  [7:0]                       rd_mismatch_wrd_cntr_r;
+  wire [7:0]                       rd_wrd_cntr;
+  reg  [7:0]                       wr_wrd_cntr;
+  reg  [7:0]                       rd_wrd_cntr_r;
+  reg  [7:0]                       wr_wrd_cntr_r;
+  wire                             wrd_cntr_rst;
+  wire                             w_burst_4;
+  wire                             w_burst_8;
+  wire                             w_burst_16;
+  
+  reg  [7:0]                       tg_state;
+  reg  [7:0]                       next_tg_state;
+  reg  [2:0]                       shft_cntr;
+  reg  [2:0]                       seed_cntr;
+  reg                              cmd_vld;
+  reg  [7:0]                       blen_cntr;
+  reg                              wr_proc;
+  reg                              curr_wr_ptr;
+  reg                              curr_rd_ptr;
+  reg  [31:0]                      curr_addr1;             
+  reg  [31:0]                      curr_addr2;             
+  reg  [7:0]                       curr_blen1;             
+  reg  [7:0]                       curr_blen2;             
+  reg                              cmd_wr_en;
+  reg                              cmd_wr_en_r;
+  reg                              cmd_rd_en;
+  reg  [7:0]                       cmd_gen_csr;
+  reg                              cmd_err_dbg;
+  reg                              data_msmatch_err_dbg;
+  reg                              write_err_dbg;
+  reg                              read_err_dbg;
+  reg  [WR_STS_WIDTH-1:0]          wdata_sts_r; // Write status registered 
+  reg  [RD_STS_WIDTH-1:0]          rdata_sts_r; // Read status registered
+  
+//*****************************************************************************
+// FSM Control Block
+//*****************************************************************************
+
+  always @(posedge clk) begin
+    if (!resetn | init_test)
+      tg_state <= 8'h1;
+    else 
+      tg_state <= next_tg_state;
+  end
+
+  always @(*) begin
+    next_tg_state = 8'h0;
+    case (1'b1)
+      tg_state[TG_IDLE]: begin // 8'h01
+        if (init_cmptd) 
+          next_tg_state[TG_GEN_PRBS] = 1'b1;
+        else
+          next_tg_state[TG_IDLE] = 1'b1;
+      end
+      tg_state[TG_GEN_PRBS]: begin // 8'h02
+        if (cmd_vld) begin
+          if (cmd_gen_csr_sig)
+            next_tg_state[TG_WR_CMD] = 1'b1;
+          else
+            next_tg_state[TG_RD_CMD] = 1'b1;
+        end else
+          next_tg_state[TG_GEN_PRBS] = 1'b1;
+      end
+      tg_state[TG_WR_CMD]: begin // 8'h04
+        if (wdata_sts_vld) begin
+          if (&shft_cntr)
+            next_tg_state[TG_UPDT_CNTR] = 1'b1;
+          else
+            next_tg_state[TG_GEN_PRBS] = 1'b1;
+        end
+        else if (wdata_rdy)
+          next_tg_state[TG_WR_DATA] = 1'b1;
+        else
+          next_tg_state[TG_WR_CMD] = 1'b1;
+      end
+      tg_state[TG_WR_DATA]: begin // 8'h08
+        if (wdata_sts_vld) begin
+          if (&shft_cntr)
+            next_tg_state[TG_UPDT_CNTR] = 1'b1;
+          else
+            next_tg_state[TG_GEN_PRBS] = 1'b1;
+        end
+        else if (blen_cntr == 8'h0 & wdata_rdy)
+          next_tg_state[TG_WR_DONE] = 1'b1;
+        else
+          next_tg_state[TG_WR_DATA] = 1'b1;
+      end
+      tg_state[TG_WR_DONE]: begin // 8'h10
+        if (wdata_sts_vld) begin
+          if (&shft_cntr)
+            next_tg_state[TG_UPDT_CNTR] = 1'b1;
+          else
+            next_tg_state[TG_GEN_PRBS] = 1'b1;
+        end
+        else
+          next_tg_state[TG_WR_DONE] = 1'b1;
+      end
+      tg_state[TG_RD_CMD]: begin // 8'h20
+        if (rdata_cmptd) begin
+          if (&shft_cntr)
+            next_tg_state[TG_UPDT_CNTR] = 1'b1;
+          else
+            next_tg_state[TG_GEN_PRBS] = 1'b1;
+        end
+        else if (cmd_ack)
+          next_tg_state[TG_RD_DATA] = 1'b1;
+        else
+          next_tg_state[TG_RD_CMD] = 1'b1;
+      end
+      tg_state[TG_RD_DATA]: begin // 8'h040
+        if (rdata_cmptd & rdata_vld & rdata_rdy) begin
+          if (&shft_cntr)
+            next_tg_state[TG_UPDT_CNTR] = 1'b1;
+          else
+            next_tg_state[TG_GEN_PRBS] = 1'b1;
+        end
+        else
+          next_tg_state[TG_RD_DATA] = 1'b1;
+      end
+      tg_state[TG_UPDT_CNTR]: begin // 8'h80
+        if (&seed_cntr)
+          next_tg_state[TG_IDLE] = 1'b1;
+        else
+          next_tg_state[TG_GEN_PRBS] = 1'b1;
+      end
+    endcase
+  end
+
+//*****************************************************************************
+// Control Signals
+//*****************************************************************************
+
+  always @(posedge clk) begin
+    if (!resetn)
+      cmd_wr_en <= 1'b0;
+    else if (next_tg_state[TG_WR_CMD] & tg_state[TG_GEN_PRBS])
+      cmd_wr_en <= 1'b1;
+    else 
+      cmd_wr_en <= 1'b0;
+  end
+
+  always @(posedge clk) begin
+    if (!resetn)
+      cmd_rd_en <= 1'b0;
+    else if (next_tg_state[TG_RD_CMD] & tg_state[TG_GEN_PRBS])
+      cmd_rd_en <= 1'b1;
+    else 
+      cmd_rd_en <= 1'b0;
+  end
+
+  always @(posedge clk) begin
+    if (tg_state[TG_IDLE] | tg_state[TG_UPDT_CNTR])
+      curr_wr_ptr <= 1'b0;
+    else if (cmd_wr_en)    
+      curr_wr_ptr <= ~curr_wr_ptr;
+  end
+
+  always @(posedge clk) begin
+    if (tg_state[TG_IDLE] | tg_state[TG_UPDT_CNTR])
+      curr_rd_ptr <= 1'b0;
+    else if (cmd_rd_en)    
+      curr_rd_ptr <= ~curr_rd_ptr;
+  end
+
+  always @(posedge clk) begin
+    if (!resetn)
+      cmd_vld <= 1'b0;
+    else if (tg_state[TG_WR_CMD] | tg_state[TG_RD_CMD])
+      cmd_vld <= 1'b0;
+    else if (tg_state[TG_GEN_PRBS])
+      cmd_vld <= 1'b1;
+  end
+
+  always @(posedge clk) begin
+    if (tg_state[TG_IDLE])
+      wr_proc <= 1'b0;
+    else if (cmd_wr_en)
+      wr_proc <= 1'b1;
+    else if (cmd_rd_en)
+      wr_proc <= 1'b0;
+  end     
+
+  always @(posedge clk) begin
+    if (tg_state[TG_IDLE] | tg_state[TG_UPDT_CNTR])
+      shft_cntr <= 3'b000;
+    else if (tg_state[TG_GEN_PRBS] & (next_tg_state[TG_WR_CMD] | 
+                                      next_tg_state[TG_RD_CMD]))
+      shft_cntr <= shft_cntr + 3'b001;
+  end
+
+  always @(posedge clk)
+    cmd_wr_en_r <= cmd_wr_en;
+
+  assign prbs_seed = {{10{seed_cntr}}, 2'b10};
+  assign dgen_init = next_tg_state[TG_GEN_PRBS] & !tg_state[TG_GEN_PRBS];
+  assign agen_init = next_tg_state[TG_GEN_PRBS] & (tg_state[TG_IDLE] | tg_state[TG_UPDT_CNTR]);
+  assign cgen_init = next_tg_state[TG_GEN_PRBS] & (tg_state[TG_IDLE] | tg_state[TG_UPDT_CNTR]);
+  assign data_pattern = (ENFORCE_RD_WR == 1) ? ENFORCE_RD_WR_PATTERN :
+                                               seed_cntr;
+  assign dgen_en   = wr_proc ? (tg_state[TG_WR_DATA] & wdata_rdy) :
+                               (tg_state[TG_RD_DATA] & rdata_vld) ;
+  assign wrd_cntr_rst = tg_state[TG_GEN_PRBS] | tg_state[TG_IDLE];
+
+//*****************************************************************************
+// Data Generation, FIFO, Checker and Data Sizer block
+//*****************************************************************************
+
+  mig_7series_v4_2_data_gen_chk #
+    (
+   
+    .C_AXI_DATA_WIDTH       (C_AXI_DATA_WIDTH)
+    
+    ) data_gen_chk_inst
+    (
+     .clk                   (clk),
+     .data_en               (dgen_en),
+     .data_pattern          (data_pattern),
+     .pattern_init          (dgen_init),   
+     .prbs_seed_i           (prbs_seed),
+     .rdata                 (rdata),
+     .rdata_bvld            (rdata_bvld),
+     .rdata_vld             (rdata_sig_vld),
+     .msmatch_err           (msmatch_err),   
+     .wrd_cntr_rst          (wrd_cntr_rst),
+     .wrd_cntr              (rd_wrd_cntr),
+     .data_o                (prbs_data)       
+    );
+
+  assign rdata_rdy = tg_state[TG_RD_DATA];
+
+  assign rdata_sig_vld = wr_proc ? 1'b0 : (rdata_vld & tg_state[TG_RD_DATA]);
+  assign wdata_sig_vld = wr_proc ? (wdata_vld & tg_state[TG_WR_DATA]) : 1'b0;
+
+
+//*****************************************************************************
+// Command generation
+//*****************************************************************************
+
+  always @(posedge clk) begin
+    if (tg_state[TG_IDLE])
+      seed_cntr <= 3'b000;
+    else if (next_tg_state[TG_UPDT_CNTR] & 
+             (tg_state[TG_WR_DATA] | tg_state[TG_WR_DONE] |
+              tg_state[TG_WR_CMD] | tg_state[TG_RD_CMD] | 
+              tg_state[TG_RD_DATA] ))
+      seed_cntr <= seed_cntr + 3'b001;
+  end
+
+  always @(posedge clk) begin
+    if (tg_state[TG_IDLE] | tg_state[TG_UPDT_CNTR]) begin
+      if (ENFORCE_RD_WR == 1)
+        cmd_gen_csr <= ENFORCE_RD_WR_CMD;
+      else
+        cmd_gen_csr <= {seed_cntr, 1'b1, seed_cntr, 1'b1};
+    end
+    else if (next_tg_state[TG_GEN_PRBS] & 
+             (tg_state[TG_WR_CMD] | tg_state[TG_WR_DATA] |
+              tg_state[TG_RD_DATA] | tg_state[TG_RD_CMD] | 
+              tg_state[TG_WR_DONE]))      
+      cmd_gen_csr <= cmd_gen_csr >> 1;
+  end
+
+  assign cmd_gen_csr_sig = cmd_gen_csr[0];
+
+//*****************************************************************************
+// Burst Length generation PRBS
+//*****************************************************************************
+
+  mig_7series_v4_2_cmd_prbs_gen_axi #
+    (
+     .PRBS_CMD            ("BLEN"),
+     .PRBS_WIDTH          (32),        //   64,15,20
+     .SEED_WIDTH          (32),        //   32,15,4
+     .ADDR_WIDTH          (C_AXI_ADDR_WIDTH) 
+     ) blen_gen_inst
+    (
+     .clk_i                 (clk),
+     .prbs_seed_init        (cgen_init),  
+     .clk_en                (cmd_wr_en_r),
+     .prbs_seed_i           (prbs_seed),
+     .prbs_o                (prbs_blen)
+    );
+
+  assign w_burst_4      = (|prbs_blen[7:2]);
+  assign w_burst_8      = (|prbs_blen[7:3]);
+  assign w_burst_16     = (|prbs_blen[7:4]);
+  assign prbs_blen_mdfy = (C_EN_WRAP_TRANS == 1 && wrap_en) ? {4'h0, w_burst_16, w_burst_8, 
+                                                    w_burst_4, 1'b1} : prbs_blen[7:0];
+
+  always @(posedge clk) begin
+    if (tg_state[TG_IDLE]) begin
+      curr_blen1 <= 8'h0;
+      curr_blen2 <= 8'h0;
+    end
+    else if (cmd_wr_en) begin
+      if (curr_wr_ptr)
+        curr_blen2 <= prbs_blen_mdfy;
+      else
+        curr_blen1 <= prbs_blen_mdfy;
+    end
+  end
+
+  always @(posedge clk) begin
+    if (tg_state[TG_IDLE] | (next_tg_state[TG_GEN_PRBS] & !tg_state[TG_GEN_PRBS])) 
+      blen_cntr <= 8'h00;
+    else if (tg_state[TG_GEN_PRBS] & next_tg_state[TG_GEN_PRBS])
+      blen_cntr <= prbs_blen_mdfy;
+    else if (tg_state[TG_WR_DATA] & wdata_rdy & (blen_cntr != 8'h00))
+      blen_cntr <= blen_cntr - 8'h01;
+  end
+
+//*****************************************************************************
+// Address generation PRBS
+//*****************************************************************************
+
+  mig_7series_v4_2_cmd_prbs_gen_axi #
+    (
+     .FAMILY              ("VIRTEX7"),
+     .ADDR_WIDTH          (C_AXI_ADDR_WIDTH),
+     .PRBS_CMD            ("ADDRESS"), // "INSTR", "BLEN","ADDRESS"
+     .PRBS_WIDTH          (32),        //   64,15,20
+     .SEED_WIDTH          (32),        //   32,15,4
+     .PRBS_EADDR_MASK_POS (PRBS_EADDR_MASK_POS),
+     .PRBS_SADDR_MASK_POS (PRBS_SADDR_MASK_POS),
+     .PRBS_EADDR          (C_END_ADDRESS),
+     .PRBS_SADDR          (C_BEGIN_ADDRESS)
+    ) addr_gen_inst
+    (
+     .clk_i                 (clk),
+     .prbs_seed_init        (agen_init),  
+     .clk_en                (cmd_wr_en_r),
+     .prbs_seed_i           (prbs_seed),
+     .prbs_o                (prbs_addr)
+    );
+ 
+  generate 
+    begin: addr_axi_wr
+      if (C_AXI_DATA_WIDTH == 256)
+        assign prbs_addr_mdfy = prbs_addr[31:0] & 32'hffff_ffe0;
+      else if (C_AXI_DATA_WIDTH == 128)
+        assign prbs_addr_mdfy = prbs_addr[31:0] & 32'hffff_fff0;
+      else if (C_AXI_DATA_WIDTH == 64)
+        assign prbs_addr_mdfy = prbs_addr[31:0] & 32'hffff_fff8;
+      else
+        assign prbs_addr_mdfy = prbs_addr[31:0] & 32'hffff_fffc;
+    end
+  endgenerate
+ 
+  always @(posedge clk) begin
+    if (tg_state[TG_IDLE]) begin
+      curr_addr1 <= 32'h0;
+      curr_addr2 <= 32'h0;
+    end
+    else if (cmd_wr_en) begin
+      if (curr_wr_ptr)
+        curr_addr2 <= prbs_addr_mdfy;
+      else
+        curr_addr1 <= prbs_addr_mdfy;
+    end
+  end
+
+//*****************************************************************************
+// Control Output Signals
+//*****************************************************************************
+
+  always @(posedge clk) begin
+    if (!resetn)
+      cmd_en <= 1'b0;
+    else if (tg_state[TG_WR_CMD] | tg_state[TG_RD_CMD])
+      cmd_en <= 1'b1;
+    else if (tg_state[TG_WR_DATA] | tg_state[TG_RD_DATA])
+      cmd_en <= 1'b0;
+  end
+
+  assign cmd = {cmd_gen_csr_sig, 1'b0, wrap_en};
+
+  always @(posedge clk) begin
+    if (tg_state[TG_IDLE]) begin
+      blen <= 8'h0;
+      addr <= 32'h0;
+    end
+    else if (cmd_gen_csr_sig & tg_state[TG_GEN_PRBS]) begin
+      blen <= prbs_blen_mdfy;
+      addr <= prbs_addr_mdfy;
+    end
+    else if (tg_state[TG_GEN_PRBS]) begin
+      case ({curr_wr_ptr, curr_rd_ptr})
+        2'b01: begin
+          blen <= curr_blen2;
+          addr <= curr_addr2;
+        end 
+        default : begin 
+          blen <= curr_blen1;
+          addr <= curr_addr1;
+        end
+      endcase
+    end
+  end
+
+  generate 
+    begin: cntrl_sig
+      if (C_AXI_NBURST_SUPPORT == 1) begin
+      end
+      else begin
+        if (C_AXI_DATA_WIDTH == 1024) 
+          assign ctl[2:0] = 3'b111;
+        else if (C_AXI_DATA_WIDTH == 512) 
+          assign ctl[2:0] = 3'b110;
+        else if (C_AXI_DATA_WIDTH == 256) 
+          assign ctl[2:0] = 3'b101;
+        else if (C_AXI_DATA_WIDTH == 128) 
+          assign ctl[2:0] = 3'b100;
+        else if (C_AXI_DATA_WIDTH == 64) 
+          assign ctl[2:0] = 3'b011;
+        else
+          assign ctl[2:0] = 3'b010;
+      end
+    end
+  endgenerate
+
+//*****************************************************************************
+// Write Output Signals
+//*****************************************************************************
+
+  always @(posedge clk) begin
+    if (!resetn)
+      wdata_cmptd <= 1'b0;
+    else if (tg_state[TG_WR_DONE])
+      wdata_cmptd <= 1'b0;
+    else if ((tg_state[TG_WR_DATA] & wdata_rdy & blen_cntr == 8'h01) |
+             (next_tg_state[TG_WR_DATA] & tg_state[TG_WR_CMD] & blen_cntr == 8'h00))
+      wdata_cmptd <= 1'b1;
+  end
+
+  assign wdata_vld = tg_state[TG_WR_DATA];
+  assign wdata = {{C_AXI_DATA_WIDTH/32}{prbs_data}};
+
+  generate 
+    begin: data_sig
+      if (C_AXI_NBURST_SUPPORT == 1) begin
+      end
+      else begin
+        assign wdata_bvld = {{C_AXI_DATA_WIDTH/32}{4'hF}};
+      end
+    end
+  endgenerate
+
+//*****************************************************************************
+// Status and Debug Signals
+//*****************************************************************************
+
+  always @(posedge clk) begin
+    if (!resetn) begin
+      cmd_err_dbg <= 1'b0;
+      data_msmatch_err_dbg <= 1'b0;
+      write_err_dbg <= 1'b0;
+      read_err_dbg <= 1'b0;
+    end
+    else if (tg_state[TG_IDLE] & next_tg_state[TG_GEN_PRBS]) begin
+      cmd_err_dbg <= 1'b0;
+      data_msmatch_err_dbg <= 1'b0;
+      write_err_dbg <= 1'b0;
+      read_err_dbg <= 1'b0;
+    end
+    else begin
+      if ((next_tg_state[TG_GEN_PRBS] | next_tg_state[TG_UPDT_CNTR]) &
+          (tg_state[TG_RD_CMD] | tg_state[TG_WR_CMD])) 
+        cmd_err_dbg <= 1'b0;
+      if (msmatch_err & tg_state[TG_RD_DATA])
+        data_msmatch_err_dbg <= 1'b1;
+      if ((next_tg_state[TG_GEN_PRBS] | next_tg_state[TG_UPDT_CNTR]) &
+          tg_state[TG_WR_DATA]) 
+        write_err_dbg <= 1'b1;
+      if (rdata_cmptd & rdata_vld & rdata_rdy)    
+        read_err_dbg <= (rdata_sts[3:2] == 2'b01);
+    end
+  end
+
+  always @(posedge clk) begin
+    if (!resetn) begin
+      cmd_err <= 1'b0;
+      data_msmatch_err <= 1'b0;
+      write_err <= 1'b0;
+      read_err <= 1'b0;
+    end
+    else begin
+      if (cmd_err_dbg)
+        cmd_err <= 1'b1;
+      if (data_msmatch_err_dbg)  
+        data_msmatch_err <= 1'b1;
+      if (write_err_dbg) 
+        write_err <= 1'b1;
+      if (read_err_dbg)
+        read_err <= 1'b1;
+    end
+  end
+
+  always @(posedge clk) begin
+    if (!resetn) begin
+      dbg_wr_sts_vld <= 1'b0;
+      dbg_rd_sts_vld <= 1'b0;
+    end
+    else if (tg_state[TG_GEN_PRBS]) begin
+      dbg_wr_sts_vld <= 1'b0;
+      dbg_rd_sts_vld <= 1'b0;
+    end
+    else begin
+      if (wdata_sts_vld)
+        dbg_wr_sts_vld <= 1'b1;
+      if (rdata_cmptd & rdata_vld & rdata_rdy)
+        dbg_rd_sts_vld <= 1'b1;
+    end
+  end 
+
+  always @(posedge clk) begin
+    if (tg_state[TG_GEN_PRBS] | tg_state[TG_IDLE]) begin
+      wdata_sts_r <= {WR_STS_WIDTH{1'b0}};
+      rdata_sts_r <= {RD_STS_WIDTH{1'b0}};
+    end
+    else begin
+      if (wdata_sts_vld)
+        wdata_sts_r <= wdata_sts;
+      if (rdata_cmptd & rdata_vld & rdata_rdy)
+        rdata_sts_r <= rdata_sts;
+    end
+  end      
+
+  //*****************************************************************************
+  // Data count generation incremented for each burst to indicate activity
+  //*****************************************************************************
+
+  // Write count within a burst
+  always @(posedge clk)
+    if (wrd_cntr_rst)
+      wr_wrd_cntr <= 8'h00;
+    else if (wdata_sig_vld)
+      wr_wrd_cntr <= wr_wrd_cntr + 8'h01;
+
+  // Read count within a burst is implemented inside the data_gen_chk module
+
+  // Storing last burst count for read and write
+  always @(posedge clk)
+    if (!resetn)
+      wr_wrd_cntr_r <= 8'h00;
+    else if (dbg_wr_sts_vld)
+      wr_wrd_cntr_r <= wr_wrd_cntr;
+
+  always @(posedge clk)
+    if (!resetn)
+      rd_wrd_cntr_r <= 8'h00;
+    else if (dbg_rd_sts_vld)
+      rd_wrd_cntr_r <= rd_wrd_cntr;
+
+  // Computing the word count at which first data mismatch occured
+  always @(posedge clk)
+    if (wrd_cntr_rst)
+      rd_mismatch_wrd_cntr_r <= 8'h00;
+    else if (~data_msmatch_err_dbg)
+      rd_mismatch_wrd_cntr_r <= rd_wrd_cntr - 1;
+  
+  assign dbg_wr_sts = {rd_wrd_cntr_r, 11'h0, data_pattern, write_err_dbg, cmd_err_dbg, wdata_sts_r};
+  assign dbg_rd_sts = {wr_wrd_cntr_r, 2'b00, data_pattern, rd_mismatch_wrd_cntr_r, data_msmatch_err_dbg, read_err_dbg, cmd_err_dbg, rdata_sts_r}; 
+  assign test_cmptd = tg_state[TG_UPDT_CNTR] & next_tg_state[TG_IDLE];
+  assign write_cmptd = (tg_state[TG_WR_DATA] | tg_state[TG_WR_DONE]) & 
+                       (next_tg_state[TG_GEN_PRBS] | next_tg_state[TG_UPDT_CNTR]);
+  assign read_cmptd = tg_state[TG_RD_DATA] & (next_tg_state[TG_GEN_PRBS] | next_tg_state[TG_UPDT_CNTR]);
+  assign cmp_data_en = dgen_en & tg_state[TG_RD_DATA];
+  assign rdata_cmp  = rdata;
+
+// synthesis translate_off
+//*****************************************************************************
+// Simulation debug signals and messages
+//*****************************************************************************
+ 
+  
+  always @(*) begin
+    if (test_cmptd) begin
+      $display ("[INFO] : All tests have been completed");
+      if (cmd_err)
+        $display ("[ERROR] Command error has occured");
+      if (data_msmatch_err)
+        $display ("[ERROR] Data mismatch error occured");
+      if (write_err)
+        $display ("[ERROR] Timeout occured during write transaction");
+      if (read_err)
+        $display ("[ERROR] Timeout occured during read transaction");
+      if (!cmd_err & !data_msmatch_err & !write_err & !read_err)
+        $display ("[INFO] : Tests PASSED");
+      $finish;
+    end 
+  end  
+
+// synthesis translate_on
+
+endmodule