josh/brd_cx9261a
1
0
Fork 0
Code Issues 1 Pull Requests Actions Packages Projects Releases 2 Wiki Activity

initial commit for zc706_cx9261a_demo

Browse Source
This commit is contained in:
josh
2024-10-31 00:22:43 +08:00
commit 3192c53706
160 changed files with 104017 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/common/ad_rst.v
+77
View File
@@ -0,0 +1,77 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_rst (
// clock reset
input rst_async,
input clk,
output rstn,
output reg rst);
// internal registers
reg rst_async_d1 = 1'd1;
reg rst_async_d2 = 1'd1;
reg rst_sync = 1'd1;
reg rst_sync_d = 1'd1;
// simple reset synchronizer
always @(posedge clk or posedge rst_async) begin
if (rst_async) begin
rst_async_d1 <= 1'b1;
rst_async_d2 <= 1'b1;
rst_sync <= 1'b1;
end else begin
rst_async_d1 <= 1'b0;
rst_async_d2 <= rst_async_d1;
rst_sync <= rst_async_d2;
end
end
// two-stage synchronizer to prevent metastability on the falling edge
always @(posedge clk) begin
rst_sync_d <= rst_sync;
rst <= rst_sync_d;
end
assign rstn = ~rst;
endmodule
// ***************************************************************************
// ***************************************************************************
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/common/up_axi.v
+239
View File
@@ -0,0 +1,239 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module up_axi #(
parameter AXI_ADDRESS_WIDTH = 16) (
// reset and clocks
input up_rstn,
input up_clk,
// axi4 interface
input up_axi_awvalid,
input [(AXI_ADDRESS_WIDTH-1):0] up_axi_awaddr,
output up_axi_awready,
input up_axi_wvalid,
input [31:0] up_axi_wdata,
input [ 3:0] up_axi_wstrb,
output up_axi_wready,
output up_axi_bvalid,
output [ 1:0] up_axi_bresp,
input up_axi_bready,
input up_axi_arvalid,
input [(AXI_ADDRESS_WIDTH-1):0] up_axi_araddr,
output up_axi_arready,
output up_axi_rvalid,
output [ 1:0] up_axi_rresp,
output [31:0] up_axi_rdata,
input up_axi_rready,
// pcore interface
output up_wreq,
output [(AXI_ADDRESS_WIDTH-3):0] up_waddr,
output [31:0] up_wdata,
input up_wack,
output up_rreq,
output [(AXI_ADDRESS_WIDTH-3):0] up_raddr,
input [31:0] up_rdata,
input up_rack);
// internal registers
reg up_axi_awready_int = 'd0;
reg up_axi_wready_int = 'd0;
reg up_axi_bvalid_int = 'd0;
reg up_wack_d = 'd0;
reg up_wsel = 'd0;
reg up_wreq_int = 'd0;
reg [(AXI_ADDRESS_WIDTH-3):0] up_waddr_int = 'd0;
reg [31:0] up_wdata_int = 'd0;
reg [ 4:0] up_wcount = 'd0;
reg up_axi_arready_int = 'd0;
reg up_axi_rvalid_int = 'd0;
reg [31:0] up_axi_rdata_int = 'd0;
reg up_rack_d = 'd0;
reg [31:0] up_rdata_d = 'd0;
reg up_rsel = 'd0;
reg up_rreq_int = 'd0;
reg [(AXI_ADDRESS_WIDTH-3):0] up_raddr_int = 'd0;
reg [ 4:0] up_rcount = 'd0;
// internal signals
wire up_wack_s;
wire up_rack_s;
wire [31:0] up_rdata_s;
// write channel interface
assign up_axi_awready = up_axi_awready_int;
assign up_axi_wready = up_axi_wready_int;
assign up_axi_bvalid = up_axi_bvalid_int;
assign up_axi_bresp = 2'd0;
always @(posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_axi_awready_int <= 'd0;
up_axi_wready_int <= 'd0;
up_axi_bvalid_int <= 'd0;
end else begin
if (up_axi_awready_int == 1'b1) begin
up_axi_awready_int <= 1'b0;
end else if (up_wack_s == 1'b1) begin
up_axi_awready_int <= 1'b1;
end
if (up_axi_wready_int == 1'b1) begin
up_axi_wready_int <= 1'b0;
end else if (up_wack_s == 1'b1) begin
up_axi_wready_int <= 1'b1;
end
if ((up_axi_bready == 1'b1) && (up_axi_bvalid_int == 1'b1)) begin
up_axi_bvalid_int <= 1'b0;
end else if (up_wack_d == 1'b1) begin
up_axi_bvalid_int <= 1'b1;
end
end
end
assign up_wreq = up_wreq_int;
assign up_waddr = up_waddr_int;
assign up_wdata = up_wdata_int;
assign up_wack_s = (up_wcount == 5'h1f) ? 1'b1 : (up_wcount[4] & up_wack);
always @(posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_wack_d <= 'd0;
up_wsel <= 'd0;
up_wreq_int <= 'd0;
up_waddr_int <= 'd0;
up_wdata_int <= 'd0;
up_wcount <= 'd0;
end else begin
up_wack_d <= up_wack_s;
if (up_wsel == 1'b1) begin
if ((up_axi_bready == 1'b1) && (up_axi_bvalid_int == 1'b1)) begin
up_wsel <= 1'b0;
end
up_wreq_int <= 1'b0;
end else begin
up_wsel <= up_axi_awvalid & up_axi_wvalid;
up_wreq_int <= up_axi_awvalid & up_axi_wvalid;
up_waddr_int <= up_axi_awaddr[(AXI_ADDRESS_WIDTH-1):2];
up_wdata_int <= up_axi_wdata;
end
if (up_wack_s == 1'b1) begin
up_wcount <= 5'h00;
end else if (up_wcount[4] == 1'b1) begin
up_wcount <= up_wcount + 1'b1;
end else if (up_wreq_int == 1'b1) begin
up_wcount <= 5'h10;
end
end
end
// read channel interface
assign up_axi_arready = up_axi_arready_int;
assign up_axi_rvalid = up_axi_rvalid_int;
assign up_axi_rdata = up_axi_rdata_int;
assign up_axi_rresp = 2'd0;
always @(posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_axi_arready_int <= 'd0;
up_axi_rvalid_int <= 'd0;
up_axi_rdata_int <= 'd0;
end else begin
if (up_axi_arready_int == 1'b1) begin
up_axi_arready_int <= 1'b0;
end else if (up_rack_s == 1'b1) begin
up_axi_arready_int <= 1'b1;
end
if ((up_axi_rready == 1'b1) && (up_axi_rvalid_int == 1'b1)) begin
up_axi_rvalid_int <= 1'b0;
up_axi_rdata_int <= 32'd0;
end else if (up_rack_d == 1'b1) begin
up_axi_rvalid_int <= 1'b1;
up_axi_rdata_int <= up_rdata_d;
end
end
end
assign up_rreq = up_rreq_int;
assign up_raddr = up_raddr_int;
assign up_rack_s = (up_rcount == 5'h1f) ? 1'b1 : (up_rcount[4] & up_rack);
assign up_rdata_s = (up_rcount == 5'h1f) ? {2{16'hdead}} : up_rdata;
always @(posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_rack_d <= 'd0;
up_rdata_d <= 'd0;
up_rsel <= 'd0;
up_rreq_int <= 'd0;
up_raddr_int <= 'd0;
up_rcount <= 'd0;
end else begin
up_rack_d <= up_rack_s;
up_rdata_d <= up_rdata_s;
if (up_rsel == 1'b1) begin
if ((up_axi_rready == 1'b1) && (up_axi_rvalid_int == 1'b1)) begin
up_rsel <= 1'b0;
end
up_rreq_int <= 1'b0;
end else begin
up_rsel <= up_axi_arvalid;
up_rreq_int <= up_axi_arvalid;
up_raddr_int <= up_axi_araddr[(AXI_ADDRESS_WIDTH-1):2];
end
if (up_rack_s == 1'b1) begin
up_rcount <= 5'h00;
end else if (up_rcount[4] == 1'b1) begin
up_rcount <= up_rcount + 1'b1;
end else if (up_rreq_int == 1'b1) begin
up_rcount <= 5'h10;
end
end
end
endmodule
// ***************************************************************************
// ***************************************************************************
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_auto_pc_0/system_bd_auto_pc_0.xci
+302
View File
@@ -0,0 +1,302 @@
{
"schema": "xilinx.com:schema:json_instance:1.0",
"ip_inst": {
"xci_name": "system_bd_auto_pc_0",
"cell_name": "axi_interconnect_0/s00_couplers/auto_pc",
"component_reference": "xilinx.com:ip:axi_protocol_converter:2.1",
"ip_revision": "31",
"gen_directory": "../../../../../../zc706_cx9261a_demo.gen/sources_1/bd/system_bd/ip/system_bd_auto_pc_0",
"parameters": {
"component_parameters": {
"SI_PROTOCOL": [ { "value": "AXI3", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
"MI_PROTOCOL": [ { "value": "AXI4LITE", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
"TRANSLATION_MODE": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
"ADDR_WIDTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"DATA_WIDTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"ID_WIDTH": [ { "value": "12", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"AWUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"ARUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"RUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"WUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"BUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Component_Name": [ { "value": "system_bd_auto_pc_0", "resolve_type": "user", "usage": "all" } ]
},
"model_parameters": {
"C_FAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ],
"C_M_AXI_PROTOCOL": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_S_AXI_PROTOCOL": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_IGNORE_ID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXI_ID_WIDTH": [ { "value": "12", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXI_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXI_SUPPORTS_WRITE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXI_SUPPORTS_READ": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXI_SUPPORTS_USER_SIGNALS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXI_AWUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXI_ARUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXI_WUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXI_RUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXI_BUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_TRANSLATION_MODE": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ]
},
"project_parameters": {
"ARCHITECTURE": [ { "value": "zynq" } ],
"BASE_BOARD_PART": [ { "value": "xilinx.com:zc706:part0:1.4" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xc7z045" } ],
"NEXTGEN_VERSAL": [ { "value": "0" } ],
"PACKAGE": [ { "value": "ffg900" } ],
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "" } ]
},
"runtime_parameters": {
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
"IPREVISION": [ { "value": "31" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "../../../../../../zc706_cx9261a_demo.gen/sources_1/bd/system_bd/ip/system_bd_auto_pc_0" } ],
"SELECTEDSIMMODEL": [ { "value": "rtl" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2024.1" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
}
},
"boundary": {
"ports": {
"aclk": [ { "direction": "in" } ],
"aresetn": [ { "direction": "in" } ],
"s_axi_awid": [ { "direction": "in", "size_left": "11", "size_right": "0", "driver_value": "0x000" } ],
"s_axi_awaddr": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0x00000000" } ],
"s_axi_awlen": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
"s_axi_awsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ],
"s_axi_awburst": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x1" } ],
"s_axi_awlock": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ],
"s_axi_awcache": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
"s_axi_awprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ],
"s_axi_awqos": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
"s_axi_awvalid": [ { "direction": "in", "driver_value": "0x0" } ],
"s_axi_awready": [ { "direction": "out" } ],
"s_axi_wid": [ { "direction": "in", "size_left": "11", "size_right": "0", "driver_value": "0x000" } ],
"s_axi_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0x00000000" } ],
"s_axi_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0xF" } ],
"s_axi_wlast": [ { "direction": "in", "driver_value": "0x1" } ],
"s_axi_wvalid": [ { "direction": "in", "driver_value": "0x0" } ],
"s_axi_wready": [ { "direction": "out" } ],
"s_axi_bid": [ { "direction": "out", "size_left": "11", "size_right": "0" } ],
"s_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
"s_axi_bvalid": [ { "direction": "out" } ],
"s_axi_bready": [ { "direction": "in", "driver_value": "0x0" } ],
"s_axi_arid": [ { "direction": "in", "size_left": "11", "size_right": "0", "driver_value": "0x000" } ],
"s_axi_araddr": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0x00000000" } ],
"s_axi_arlen": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
"s_axi_arsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ],
"s_axi_arburst": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x1" } ],
"s_axi_arlock": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ],
"s_axi_arcache": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
"s_axi_arprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ],
"s_axi_arqos": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
"s_axi_arvalid": [ { "direction": "in", "driver_value": "0x0" } ],
"s_axi_arready": [ { "direction": "out" } ],
"s_axi_rid": [ { "direction": "out", "size_left": "11", "size_right": "0" } ],
"s_axi_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
"s_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
"s_axi_rlast": [ { "direction": "out" } ],
"s_axi_rvalid": [ { "direction": "out" } ],
"s_axi_rready": [ { "direction": "in", "driver_value": "0x0" } ],
"m_axi_awaddr": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
"m_axi_awprot": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
"m_axi_awvalid": [ { "direction": "out" } ],
"m_axi_awready": [ { "direction": "in", "driver_value": "0x0" } ],
"m_axi_wdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
"m_axi_wstrb": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
"m_axi_wvalid": [ { "direction": "out" } ],
"m_axi_wready": [ { "direction": "in", "driver_value": "0x0" } ],
"m_axi_bresp": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ],
"m_axi_bvalid": [ { "direction": "in", "driver_value": "0x0" } ],
"m_axi_bready": [ { "direction": "out" } ],
"m_axi_araddr": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
"m_axi_arprot": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
"m_axi_arvalid": [ { "direction": "out" } ],
"m_axi_arready": [ { "direction": "in", "driver_value": "0x0" } ],
"m_axi_rdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0x00000000" } ],
"m_axi_rresp": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ],
"m_axi_rvalid": [ { "direction": "in", "driver_value": "0x0" } ],
"m_axi_rready": [ { "direction": "out" } ]
},
"interfaces": {
"S_AXI": {
"vlnv": "xilinx.com:interface:aximm:1.0",
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
"mode": "slave",
"parameters": {
"DATA_WIDTH": [ { "value": "32", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"PROTOCOL": [ { "value": "AXI3", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "5e+07", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"ID_WIDTH": [ { "value": "12", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"ADDR_WIDTH": [ { "value": "32", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_BURST": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_LOCK": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_PROT": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_CACHE": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_QOS": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_REGION": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_WSTRB": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_BRESP": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_RRESP": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"MAX_BURST_LENGTH": [ { "value": "16", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_READ_THREADS": [ { "value": "4", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_WRITE_THREADS": [ { "value": "4", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"AWID": [ { "physical_name": "s_axi_awid" } ],
"AWADDR": [ { "physical_name": "s_axi_awaddr" } ],
"AWLEN": [ { "physical_name": "s_axi_awlen" } ],
"AWSIZE": [ { "physical_name": "s_axi_awsize" } ],
"AWBURST": [ { "physical_name": "s_axi_awburst" } ],
"AWLOCK": [ { "physical_name": "s_axi_awlock" } ],
"AWCACHE": [ { "physical_name": "s_axi_awcache" } ],
"AWPROT": [ { "physical_name": "s_axi_awprot" } ],
"AWQOS": [ { "physical_name": "s_axi_awqos" } ],
"AWVALID": [ { "physical_name": "s_axi_awvalid" } ],
"AWREADY": [ { "physical_name": "s_axi_awready" } ],
"WID": [ { "physical_name": "s_axi_wid" } ],
"WDATA": [ { "physical_name": "s_axi_wdata" } ],
"WSTRB": [ { "physical_name": "s_axi_wstrb" } ],
"WLAST": [ { "physical_name": "s_axi_wlast" } ],
"WVALID": [ { "physical_name": "s_axi_wvalid" } ],
"WREADY": [ { "physical_name": "s_axi_wready" } ],
"BID": [ { "physical_name": "s_axi_bid" } ],
"BRESP": [ { "physical_name": "s_axi_bresp" } ],
"BVALID": [ { "physical_name": "s_axi_bvalid" } ],
"BREADY": [ { "physical_name": "s_axi_bready" } ],
"ARID": [ { "physical_name": "s_axi_arid" } ],
"ARADDR": [ { "physical_name": "s_axi_araddr" } ],
"ARLEN": [ { "physical_name": "s_axi_arlen" } ],
"ARSIZE": [ { "physical_name": "s_axi_arsize" } ],
"ARBURST": [ { "physical_name": "s_axi_arburst" } ],
"ARLOCK": [ { "physical_name": "s_axi_arlock" } ],
"ARCACHE": [ { "physical_name": "s_axi_arcache" } ],
"ARPROT": [ { "physical_name": "s_axi_arprot" } ],
"ARQOS": [ { "physical_name": "s_axi_arqos" } ],
"ARVALID": [ { "physical_name": "s_axi_arvalid" } ],
"ARREADY": [ { "physical_name": "s_axi_arready" } ],
"RID": [ { "physical_name": "s_axi_rid" } ],
"RDATA": [ { "physical_name": "s_axi_rdata" } ],
"RRESP": [ { "physical_name": "s_axi_rresp" } ],
"RLAST": [ { "physical_name": "s_axi_rlast" } ],
"RVALID": [ { "physical_name": "s_axi_rvalid" } ],
"RREADY": [ { "physical_name": "s_axi_rready" } ]
}
},
"M_AXI": {
"vlnv": "xilinx.com:interface:aximm:1.0",
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
"mode": "master",
"parameters": {
"DATA_WIDTH": [ { "value": "32", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "5e+07", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"ID_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"ADDR_WIDTH": [ { "value": "32", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_BURST": [ { "value": "0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_LOCK": [ { "value": "0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_PROT": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_CACHE": [ { "value": "0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_QOS": [ { "value": "0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_REGION": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_WSTRB": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_BRESP": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_RRESP": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"MAX_BURST_LENGTH": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_READ_THREADS": [ { "value": "4", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_WRITE_THREADS": [ { "value": "4", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"AWADDR": [ { "physical_name": "m_axi_awaddr" } ],
"AWPROT": [ { "physical_name": "m_axi_awprot" } ],
"AWVALID": [ { "physical_name": "m_axi_awvalid" } ],
"AWREADY": [ { "physical_name": "m_axi_awready" } ],
"WDATA": [ { "physical_name": "m_axi_wdata" } ],
"WSTRB": [ { "physical_name": "m_axi_wstrb" } ],
"WVALID": [ { "physical_name": "m_axi_wvalid" } ],
"WREADY": [ { "physical_name": "m_axi_wready" } ],
"BRESP": [ { "physical_name": "m_axi_bresp" } ],
"BVALID": [ { "physical_name": "m_axi_bvalid" } ],
"BREADY": [ { "physical_name": "m_axi_bready" } ],
"ARADDR": [ { "physical_name": "m_axi_araddr" } ],
"ARPROT": [ { "physical_name": "m_axi_arprot" } ],
"ARVALID": [ { "physical_name": "m_axi_arvalid" } ],
"ARREADY": [ { "physical_name": "m_axi_arready" } ],
"RDATA": [ { "physical_name": "m_axi_rdata" } ],
"RRESP": [ { "physical_name": "m_axi_rresp" } ],
"RVALID": [ { "physical_name": "m_axi_rvalid" } ],
"RREADY": [ { "physical_name": "m_axi_rready" } ]
}
},
"CLK": {
"vlnv": "xilinx.com:signal:clock:1.0",
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
"mode": "slave",
"parameters": {
"ASSOCIATED_BUSIF": [ { "value": "S_AXI:M_AXI", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
"ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
"FREQ_HZ": [ { "value": "5e+07", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"CLK": [ { "physical_name": "aclk" } ]
}
},
"RST": {
"vlnv": "xilinx.com:signal:reset:1.0",
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
"mode": "slave",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
"TYPE": [ { "value": "INTERCONNECT", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"RST": [ { "physical_name": "aresetn" } ]
}
}
}
}
}
}
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_axi_interconnect_0_0/system_bd_axi_interconnect_0_0.xci
+353
View File
@@ -0,0 +1,353 @@
{
"schema": "xilinx.com:schema:json_instance:1.0",
"ip_inst": {
"xci_name": "system_bd_axi_interconnect_0_0",
"cell_name": "axi_interconnect_0",
"component_reference": "xilinx.com:ip:axi_interconnect:2.1",
"ip_revision": "32",
"gen_directory": "../../../../../../zc706_cx9261a_demo.gen/sources_1/bd/system_bd/ip/system_bd_axi_interconnect_0_0",
"parameters": {
"component_parameters": {
"NUM_SI": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"NUM_MI": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"STRATEGY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"ENABLE_ADVANCED_OPTIONS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"ENABLE_PROTOCOL_CHECKERS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"XBAR_DATA_WIDTH": [ { "value": "32", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"PCHK_WAITS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"PCHK_MAX_RD_BURSTS": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
"PCHK_MAX_WR_BURSTS": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
"SYNCHRONIZATION_STAGES": [ { "value": "3", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M00_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M01_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M02_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M03_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M04_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M05_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M06_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M07_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M08_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M09_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M10_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M11_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M12_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M13_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M14_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M15_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M16_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M17_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M18_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M19_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M20_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M21_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M22_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M23_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M24_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M25_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M26_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M27_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M28_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M29_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M30_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M31_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M32_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M33_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M34_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M35_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M36_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M37_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M38_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M39_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M40_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M41_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M42_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M43_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M44_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M45_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M46_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M47_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M48_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M49_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M50_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M51_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M52_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M53_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M54_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M55_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M56_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M57_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M58_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M59_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M60_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M61_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M62_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M63_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M00_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M01_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M02_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M03_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M04_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M05_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M06_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M07_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M08_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M09_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M10_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M11_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M12_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M13_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M14_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M15_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M16_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M17_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M18_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M19_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M20_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M21_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M22_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M23_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M24_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M25_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M26_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M27_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M28_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M29_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M30_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M31_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M32_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M33_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M34_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M35_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M36_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M37_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M38_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M39_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M40_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M41_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M42_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M43_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M44_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M45_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M46_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M47_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M48_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M49_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M50_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M51_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M52_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M53_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M54_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M55_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M56_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M57_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M58_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M59_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M60_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M61_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M62_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M63_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"S00_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"S01_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"S02_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"S03_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"S04_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"S05_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"S06_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"S07_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"S08_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"S09_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"S10_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"S11_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"S12_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"S13_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"S14_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"S15_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"S00_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"S01_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"S02_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"S03_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"S04_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"S05_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"S06_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"S07_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"S08_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"S09_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"S10_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"S11_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"S12_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"S13_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"S14_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"S15_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M00_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M01_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M02_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M03_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M04_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M05_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M06_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M07_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M08_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M09_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M10_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M11_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M12_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M13_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M14_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M15_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M16_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M17_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M18_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M19_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M20_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M21_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M22_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M23_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M24_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M25_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M26_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M27_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M28_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M29_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M30_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M31_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M32_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M33_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M34_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M35_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M36_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M37_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M38_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M39_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M40_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M41_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M42_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M43_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M44_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M45_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M46_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M47_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M48_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M49_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M50_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M51_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M52_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M53_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M54_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M55_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M56_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M57_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M58_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M59_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M60_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M61_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M62_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M63_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M00_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M01_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M02_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M03_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M04_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M05_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M06_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M07_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M08_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M09_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M10_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M11_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M12_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M13_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M14_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M15_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M16_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M17_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M18_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M19_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M20_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M21_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M22_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M23_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M24_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M25_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M26_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M27_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M28_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M29_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M30_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M31_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M32_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M33_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M34_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M35_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M36_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M37_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M38_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M39_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M40_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M41_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M42_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M43_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M44_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M45_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M46_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M47_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M48_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M49_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M50_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M51_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M52_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M53_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M54_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M55_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M56_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M57_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M58_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M59_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M60_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M61_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M62_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M63_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"S00_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"S01_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"S02_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"S03_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"S04_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"S05_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"S06_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"S07_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"S08_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"S09_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"S10_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"S11_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"S12_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"S13_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"S14_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"S15_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Component_Name": [ { "value": "system_bd_axi_interconnect_0_0", "resolve_type": "user", "usage": "all" } ]
},
"project_parameters": {
"ARCHITECTURE": [ { "value": "zynq" } ],
"BASE_BOARD_PART": [ { "value": "xilinx.com:zc706:part0:1.4" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xc7z045" } ],
"NEXTGEN_VERSAL": [ { "value": "0" } ],
"PACKAGE": [ { "value": "ffg900" } ],
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "" } ]
},
"runtime_parameters": {
"IPCONTEXT": [ { "value": "IP_Integrator_AppCore" } ],
"IPREVISION": [ { "value": "32" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "../../../../../../zc706_cx9261a_demo.gen/sources_1/bd/system_bd/ip/system_bd_axi_interconnect_0_0" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2024.1" } ],
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
}
}
}
}
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/sim/system_bd_axi_spi_engine_0_0.v
+245
View File
@@ -0,0 +1,245 @@
// (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: analog.com:user:axi_spi_engine:1.0
// IP Revision: 1
`timescale 1ns/1ps
(* IP_DEFINITION_SOURCE = "package_project" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module system_bd_axi_spi_engine_0_0 (
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awready,
s_axi_awprot,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arready,
s_axi_arprot,
s_axi_rvalid,
s_axi_rready,
s_axi_rresp,
s_axi_rdata,
irq,
spi_clk,
spi_resetn,
cmd_ready,
cmd_valid,
cmd_data,
sdo_data_ready,
sdo_data_valid,
sdo_data,
sdi_data_ready,
sdi_data_valid,
sdi_data,
sync_ready,
sync_valid,
sync_data
);
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi_aclk, ASSOCIATED_BUSIF s_axi, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0, XIL_INTERFACENAME spi_engine_offload_ctrl0_s_axi_signal_clock, ASSOCIATED_BUSIF spi_engine_offload_ctrl0:s_axi, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 s_axi_aclk CLK, xilinx.com:signal:clock:1.0 spi_engine_offload_ctrl0_s_axi_signal_clock CLK" *)
input wire s_axi_aclk;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0, XIL_INTERFACENAME spi_engine_offload_ctrl0_s_axi_signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 s_axi_aresetn RST, xilinx.com:signal:reset:1.0 spi_engine_offload_ctrl0_s_axi_signal_reset RST" *)
input wire s_axi_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWADDR" *)
input wire [15 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARADDR" *)
input wire [15 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 50000000, ID_WIDTH 0, ADDR_WIDTH 16, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREAD\
S 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RDATA" *)
output wire [31 : 0] s_axi_rdata;
output wire irq;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME spi_engine_ctrl_signal_clock, ASSOCIATED_BUSIF spi_engine_ctrl, ASSOCIATED_RESET spi_resetn, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 spi_engine_ctrl_signal_clock CLK" *)
input wire spi_clk;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME spi_engine_ctrl_signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 spi_engine_ctrl_signal_reset RST" *)
output wire spi_resetn;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl CMD_READY" *)
input wire cmd_ready;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl CMD_VALID" *)
output wire cmd_valid;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl CMD_DATA" *)
output wire [15 : 0] cmd_data;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDO_READY" *)
input wire sdo_data_ready;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDO_VALID" *)
output wire sdo_data_valid;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDO_DATA" *)
output wire [7 : 0] sdo_data;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDI_READY" *)
output wire sdi_data_ready;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDI_VALID" *)
input wire sdi_data_valid;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDI_DATA" *)
input wire [7 : 0] sdi_data;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SYNC_READY" *)
output wire sync_ready;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SYNC_VALID" *)
input wire sync_valid;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SYNC_DATA" *)
input wire [7 : 0] sync_data;
axi_spi_engine #(
.CMD_FIFO_ADDRESS_WIDTH(4),
.SYNC_FIFO_ADDRESS_WIDTH(4),
.SDO_FIFO_ADDRESS_WIDTH(5),
.SDI_FIFO_ADDRESS_WIDTH(5),
.MM_IF_TYPE(0),
.ASYNC_SPI_CLK(1'B0),
.NUM_OFFLOAD(0),
.OFFLOAD0_CMD_MEM_ADDRESS_WIDTH(4),
.OFFLOAD0_SDO_MEM_ADDRESS_WIDTH(4),
.ID(0),
.DATA_WIDTH(8),
.NUM_OF_SDI(1)
) inst (
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awready(s_axi_awready),
.s_axi_awprot(s_axi_awprot),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wready(s_axi_wready),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bresp(s_axi_bresp),
.s_axi_bready(s_axi_bready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arready(s_axi_arready),
.s_axi_arprot(s_axi_arprot),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_rdata(s_axi_rdata),
.up_clk(1'B0),
.up_rstn(1'B0),
.up_wreq(1'B0),
.up_waddr(14'B0),
.up_wdata(32'B0),
.up_wack(),
.up_rreq(1'B0),
.up_raddr(14'B0),
.up_rdata(),
.up_rack(),
.irq(irq),
.spi_clk(spi_clk),
.spi_resetn(spi_resetn),
.cmd_ready(cmd_ready),
.cmd_valid(cmd_valid),
.cmd_data(cmd_data),
.sdo_data_ready(sdo_data_ready),
.sdo_data_valid(sdo_data_valid),
.sdo_data(sdo_data),
.sdi_data_ready(sdi_data_ready),
.sdi_data_valid(sdi_data_valid),
.sdi_data(sdi_data),
.sync_ready(sync_ready),
.sync_valid(sync_valid),
.sync_data(sync_data),
.offload0_cmd_wr_en(),
.offload0_cmd_wr_data(),
.offload0_sdo_wr_en(),
.offload0_sdo_wr_data(),
.offload0_mem_reset(),
.offload0_enable(),
.offload0_enabled(1'B0),
.offload_sync_ready(),
.offload_sync_valid(1'B0),
.offload_sync_data(8'B0)
);
endmodule
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/synth/system_bd_axi_spi_engine_0_0.v
+245
View File
@@ -0,0 +1,245 @@
// (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: analog.com:user:axi_spi_engine:1.0
// IP Revision: 1
(* X_CORE_INFO = "axi_spi_engine,Vivado 2019.1.3" *)
(* CHECK_LICENSE_TYPE = "system_bd_axi_spi_engine_0_0,axi_spi_engine,{}" *)
(* IP_DEFINITION_SOURCE = "package_project" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module system_bd_axi_spi_engine_0_0 (
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awready,
s_axi_awprot,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arready,
s_axi_arprot,
s_axi_rvalid,
s_axi_rready,
s_axi_rresp,
s_axi_rdata,
irq,
spi_clk,
spi_resetn,
cmd_ready,
cmd_valid,
cmd_data,
sdo_data_ready,
sdo_data_valid,
sdo_data,
sdi_data_ready,
sdi_data_valid,
sdi_data,
sync_ready,
sync_valid,
sync_data
);
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi_aclk, ASSOCIATED_BUSIF s_axi, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0, XIL_INTERFACENAME spi_engine_offload_ctrl0_s_axi_signal_clock, ASSOCIATED_BUSIF spi_engine_offload_ctrl0:s_axi, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 s_axi_aclk CLK, xilinx.com:signal:clock:1.0 spi_engine_offload_ctrl0_s_axi_signal_clock CLK" *)
input wire s_axi_aclk;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0, XIL_INTERFACENAME spi_engine_offload_ctrl0_s_axi_signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 s_axi_aresetn RST, xilinx.com:signal:reset:1.0 spi_engine_offload_ctrl0_s_axi_signal_reset RST" *)
input wire s_axi_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWADDR" *)
input wire [15 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARADDR" *)
input wire [15 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 50000000, ID_WIDTH 0, ADDR_WIDTH 16, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREAD\
S 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RDATA" *)
output wire [31 : 0] s_axi_rdata;
output wire irq;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME spi_engine_ctrl_signal_clock, ASSOCIATED_BUSIF spi_engine_ctrl, ASSOCIATED_RESET spi_resetn, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 spi_engine_ctrl_signal_clock CLK" *)
input wire spi_clk;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME spi_engine_ctrl_signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 spi_engine_ctrl_signal_reset RST" *)
output wire spi_resetn;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl CMD_READY" *)
input wire cmd_ready;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl CMD_VALID" *)
output wire cmd_valid;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl CMD_DATA" *)
output wire [15 : 0] cmd_data;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDO_READY" *)
input wire sdo_data_ready;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDO_VALID" *)
output wire sdo_data_valid;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDO_DATA" *)
output wire [7 : 0] sdo_data;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDI_READY" *)
output wire sdi_data_ready;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDI_VALID" *)
input wire sdi_data_valid;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDI_DATA" *)
input wire [7 : 0] sdi_data;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SYNC_READY" *)
output wire sync_ready;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SYNC_VALID" *)
input wire sync_valid;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SYNC_DATA" *)
input wire [7 : 0] sync_data;
axi_spi_engine #(
.CMD_FIFO_ADDRESS_WIDTH(4),
.SYNC_FIFO_ADDRESS_WIDTH(4),
.SDO_FIFO_ADDRESS_WIDTH(5),
.SDI_FIFO_ADDRESS_WIDTH(5),
.MM_IF_TYPE(0),
.ASYNC_SPI_CLK(1'B0),
.NUM_OFFLOAD(0),
.OFFLOAD0_CMD_MEM_ADDRESS_WIDTH(4),
.OFFLOAD0_SDO_MEM_ADDRESS_WIDTH(4),
.ID(0),
.DATA_WIDTH(8),
.NUM_OF_SDI(1)
) inst (
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awready(s_axi_awready),
.s_axi_awprot(s_axi_awprot),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wready(s_axi_wready),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bresp(s_axi_bresp),
.s_axi_bready(s_axi_bready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arready(s_axi_arready),
.s_axi_arprot(s_axi_arprot),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_rdata(s_axi_rdata),
.up_clk(1'B0),
.up_rstn(1'B0),
.up_wreq(1'B0),
.up_waddr(14'B0),
.up_wdata(32'B0),
.up_wack(),
.up_rreq(1'B0),
.up_raddr(14'B0),
.up_rdata(),
.up_rack(),
.irq(irq),
.spi_clk(spi_clk),
.spi_resetn(spi_resetn),
.cmd_ready(cmd_ready),
.cmd_valid(cmd_valid),
.cmd_data(cmd_data),
.sdo_data_ready(sdo_data_ready),
.sdo_data_valid(sdo_data_valid),
.sdo_data(sdo_data),
.sdi_data_ready(sdi_data_ready),
.sdi_data_valid(sdi_data_valid),
.sdi_data(sdi_data),
.sync_ready(sync_ready),
.sync_valid(sync_valid),
.sync_data(sync_data),
.offload0_cmd_wr_en(),
.offload0_cmd_wr_data(),
.offload0_sdo_wr_en(),
.offload0_sdo_wr_data(),
.offload0_mem_reset(),
.offload0_enable(),
.offload0_enabled(1'B0),
.offload_sync_ready(),
.offload_sync_valid(1'B0),
.offload_sync_data(8'B0)
);
endmodule
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0.dcp
LFS
BIN
View File
Binary file not shown.
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0.xci
+287
View File
@@ -0,0 +1,287 @@
{
"schema": "xilinx.com:schema:json_instance:1.0",
"ip_inst": {
"xci_name": "system_bd_axi_spi_engine_0_0",
"cell_name": "axi_spi_engine/axi_spi_engine",
"component_reference": "analog.com:user:axi_spi_engine:1.0",
"ip_revision": "1",
"gen_directory": ".",
"parameters": {
"component_parameters": {
"CMD_FIFO_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
"SYNC_FIFO_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
"SDO_FIFO_ADDRESS_WIDTH": [ { "value": "5", "resolve_type": "user", "format": "long", "usage": "all" } ],
"SDI_FIFO_ADDRESS_WIDTH": [ { "value": "5", "resolve_type": "user", "format": "long", "usage": "all" } ],
"MM_IF_TYPE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"ASYNC_SPI_CLK": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"NUM_OFFLOAD": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"OFFLOAD0_CMD_MEM_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"OFFLOAD0_SDO_MEM_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"ID": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"DATA_WIDTH": [ { "value": "8", "resolve_type": "user", "format": "long", "usage": "all" } ],
"NUM_OF_SDI": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Component_Name": [ { "value": "system_bd_axi_spi_engine_0_0", "resolve_type": "user", "usage": "all" } ]
},
"model_parameters": {
"CMD_FIFO_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"SYNC_FIFO_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"SDO_FIFO_ADDRESS_WIDTH": [ { "value": "5", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"SDI_FIFO_ADDRESS_WIDTH": [ { "value": "5", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"MM_IF_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"ASYNC_SPI_CLK": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
"NUM_OFFLOAD": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"OFFLOAD0_CMD_MEM_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"OFFLOAD0_SDO_MEM_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"ID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"DATA_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"NUM_OF_SDI": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ]
},
"project_parameters": {
"ARCHITECTURE": [ { "value": "zynq" } ],
"BASE_BOARD_PART": [ { "value": "xilinx.com:zc706:part0:1.4" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xc7z045" } ],
"NEXTGEN_VERSAL": [ { "value": "0" } ],
"PACKAGE": [ { "value": "ffg900" } ],
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "" } ]
},
"runtime_parameters": {
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
"IPREVISION": [ { "value": "1" } ],
"LOCKEDBYUSER": [ { "value": "TRUE" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "." } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2019.1.3" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
}
},
"boundary": {
"ports": {
"s_axi_aclk": [ { "direction": "in", "driver_value": "0" } ],
"s_axi_aresetn": [ { "direction": "in", "driver_value": "0" } ],
"s_axi_awvalid": [ { "direction": "in", "driver_value": "0" } ],
"s_axi_awaddr": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
"s_axi_awready": [ { "direction": "out", "driver_value": "0" } ],
"s_axi_awprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
"s_axi_wvalid": [ { "direction": "in", "driver_value": "0" } ],
"s_axi_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
"s_axi_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
"s_axi_wready": [ { "direction": "out", "driver_value": "0" } ],
"s_axi_bvalid": [ { "direction": "out", "driver_value": "0" } ],
"s_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
"s_axi_bready": [ { "direction": "in", "driver_value": "0" } ],
"s_axi_arvalid": [ { "direction": "in", "driver_value": "0" } ],
"s_axi_araddr": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
"s_axi_arready": [ { "direction": "out", "driver_value": "0" } ],
"s_axi_arprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
"s_axi_rvalid": [ { "direction": "out", "driver_value": "0" } ],
"s_axi_rready": [ { "direction": "in", "driver_value": "0" } ],
"s_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
"s_axi_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
"irq": [ { "direction": "out" } ],
"spi_clk": [ { "direction": "in" } ],
"spi_resetn": [ { "direction": "out" } ],
"cmd_ready": [ { "direction": "in" } ],
"cmd_valid": [ { "direction": "out" } ],
"cmd_data": [ { "direction": "out", "size_left": "15", "size_right": "0" } ],
"sdo_data_ready": [ { "direction": "in", "driver_value": "0" } ],
"sdo_data_valid": [ { "direction": "out" } ],
"sdo_data": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
"sdi_data_ready": [ { "direction": "out" } ],
"sdi_data_valid": [ { "direction": "in", "driver_value": "0" } ],
"sdi_data": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
"sync_ready": [ { "direction": "out" } ],
"sync_valid": [ { "direction": "in" } ],
"sync_data": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ]
},
"interfaces": {
"s_axi": {
"vlnv": "xilinx.com:interface:aximm:1.0",
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
"mode": "slave",
"memory_map_ref": "s_axi",
"parameters": {
"DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
"FREQ_HZ": [ { "value": "50000000", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"ADDR_WIDTH": [ { "value": "16", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"HAS_PROT": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"HAS_WSTRB": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"HAS_BRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"HAS_RRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"NUM_READ_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"MAX_BURST_LENGTH": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_static_object": false } ],
"NUM_READ_THREADS": [ { "value": "1", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"NUM_WRITE_THREADS": [ { "value": "1", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"RUSER_BITS_PER_BYTE": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"WUSER_BITS_PER_BYTE": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
},
"port_maps": {
"AWADDR": [ { "physical_name": "s_axi_awaddr" } ],
"AWPROT": [ { "physical_name": "s_axi_awprot" } ],
"AWVALID": [ { "physical_name": "s_axi_awvalid" } ],
"AWREADY": [ { "physical_name": "s_axi_awready" } ],
"WDATA": [ { "physical_name": "s_axi_wdata" } ],
"WSTRB": [ { "physical_name": "s_axi_wstrb" } ],
"WVALID": [ { "physical_name": "s_axi_wvalid" } ],
"WREADY": [ { "physical_name": "s_axi_wready" } ],
"BRESP": [ { "physical_name": "s_axi_bresp" } ],
"BVALID": [ { "physical_name": "s_axi_bvalid" } ],
"BREADY": [ { "physical_name": "s_axi_bready" } ],
"ARADDR": [ { "physical_name": "s_axi_araddr" } ],
"ARPROT": [ { "physical_name": "s_axi_arprot" } ],
"ARVALID": [ { "physical_name": "s_axi_arvalid" } ],
"ARREADY": [ { "physical_name": "s_axi_arready" } ],
"RDATA": [ { "physical_name": "s_axi_rdata" } ],
"RRESP": [ { "physical_name": "s_axi_rresp" } ],
"RVALID": [ { "physical_name": "s_axi_rvalid" } ],
"RREADY": [ { "physical_name": "s_axi_rready" } ]
}
},
"s_axi_aclk": {
"vlnv": "xilinx.com:signal:clock:1.0",
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
"mode": "slave",
"parameters": {
"ASSOCIATED_BUSIF": [ { "value": "s_axi", "value_src": "constant", "usage": "all" } ],
"ASSOCIATED_RESET": [ { "value": "s_axi_aresetn", "value_src": "constant", "usage": "all" } ],
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"CLK": [ { "physical_name": "s_axi_aclk" } ]
}
},
"s_axi_aresetn": {
"vlnv": "xilinx.com:signal:reset:1.0",
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
"mode": "slave",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
},
"port_maps": {
"RST": [ { "physical_name": "s_axi_aresetn" } ]
}
},
"spi_engine_ctrl": {
"vlnv": "analog.com:interface:spi_engine_ctrl:1.0",
"abstraction_type": "analog.com:interface:spi_engine_ctrl_rtl:1.0",
"mode": "master",
"port_maps": {
"CMD_READY": [ { "physical_name": "cmd_ready" } ],
"CMD_VALID": [ { "physical_name": "cmd_valid" } ],
"CMD_DATA": [ { "physical_name": "cmd_data" } ],
"SDO_READY": [ { "physical_name": "sdo_data_ready" } ],
"SDO_VALID": [ { "physical_name": "sdo_data_valid" } ],
"SDO_DATA": [ { "physical_name": "sdo_data" } ],
"SDI_READY": [ { "physical_name": "sdi_data_ready" } ],
"SDI_VALID": [ { "physical_name": "sdi_data_valid" } ],
"SDI_DATA": [ { "physical_name": "sdi_data" } ],
"SYNC_READY": [ { "physical_name": "sync_ready" } ],
"SYNC_VALID": [ { "physical_name": "sync_valid" } ],
"SYNC_DATA": [ { "physical_name": "sync_data" } ]
}
},
"spi_engine_ctrl_signal_clock": {
"vlnv": "xilinx.com:signal:clock:1.0",
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
"mode": "slave",
"parameters": {
"ASSOCIATED_BUSIF": [ { "value": "spi_engine_ctrl", "value_src": "constant", "usage": "all" } ],
"ASSOCIATED_RESET": [ { "value": "spi_resetn", "value_src": "constant", "usage": "all" } ],
"FREQ_HZ": [ { "value": "50000000", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"CLK": [ { "physical_name": "spi_clk" } ]
}
},
"spi_engine_ctrl_signal_reset": {
"vlnv": "xilinx.com:signal:reset:1.0",
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
"mode": "master",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
},
"port_maps": {
"RST": [ { "physical_name": "spi_resetn" } ]
}
},
"spi_engine_offload_ctrl0_s_axi_signal_clock": {
"vlnv": "xilinx.com:signal:clock:1.0",
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
"mode": "slave",
"parameters": {
"ASSOCIATED_BUSIF": [ { "value": "spi_engine_offload_ctrl0:s_axi", "value_src": "constant", "usage": "all" } ],
"ASSOCIATED_RESET": [ { "value": "s_axi_aresetn", "value_src": "constant", "usage": "all" } ],
"FREQ_HZ": [ { "value": "50000000", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"CLK": [ { "physical_name": "s_axi_aclk" } ]
}
},
"spi_engine_offload_ctrl0_s_axi_signal_reset": {
"vlnv": "xilinx.com:signal:reset:1.0",
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
"mode": "slave",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
},
"port_maps": {
"RST": [ { "physical_name": "s_axi_aresetn" } ]
}
}
},
"memory_maps": {
"s_axi": {
"address_blocks": {
"axi_lite": {
"base_address": "0",
"range": "65536"
}
}
}
}
}
}
}
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0.xml
+2744
View File
File diff suppressed because it is too large Load Diff
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0_constr.xdc
+1
View File
@@ -0,0 +1 @@
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0_sim_netlist.v
+6411
View File
File diff suppressed because it is too large Load Diff
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0_sim_netlist.vhdl
+7953
View File
File diff suppressed because it is too large Load Diff
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0_stub.v
+60
View File
@@ -0,0 +1,60 @@
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
// Date : Sun Sep 29 16:31:49 2024
// Host : gatsby-dev running 64-bit Red Hat Enterprise Linux release 8.10 (Ootpa)
// Command : write_verilog -force -mode synth_stub
// /home/josh/Workspace/CX9261A/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0_stub.v
// Design : system_bd_axi_spi_engine_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z045ffg900-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_spi_engine,Vivado 2019.1.3" *)
module system_bd_axi_spi_engine_0_0(s_axi_aclk, s_axi_aresetn, s_axi_awvalid,
s_axi_awaddr, s_axi_awready, s_axi_awprot, s_axi_wvalid, s_axi_wdata, s_axi_wstrb,
s_axi_wready, s_axi_bvalid, s_axi_bresp, s_axi_bready, s_axi_arvalid, s_axi_araddr,
s_axi_arready, s_axi_arprot, s_axi_rvalid, s_axi_rready, s_axi_rresp, s_axi_rdata, irq,
spi_clk, spi_resetn, cmd_ready, cmd_valid, cmd_data, sdo_data_ready, sdo_data_valid, sdo_data,
sdi_data_ready, sdi_data_valid, sdi_data, sync_ready, sync_valid, sync_data)
/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,s_axi_awvalid,s_axi_awaddr[15:0],s_axi_awready,s_axi_awprot[2:0],s_axi_wvalid,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wready,s_axi_bvalid,s_axi_bresp[1:0],s_axi_bready,s_axi_arvalid,s_axi_araddr[15:0],s_axi_arready,s_axi_arprot[2:0],s_axi_rvalid,s_axi_rready,s_axi_rresp[1:0],s_axi_rdata[31:0],irq,spi_clk,spi_resetn,cmd_ready,cmd_valid,cmd_data[15:0],sdo_data_ready,sdo_data_valid,sdo_data[7:0],sdi_data_ready,sdi_data_valid,sdi_data[7:0],sync_ready,sync_valid,sync_data[7:0]" */;
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [15:0]s_axi_awaddr;
output s_axi_awready;
input [2:0]s_axi_awprot;
input s_axi_wvalid;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [1:0]s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [15:0]s_axi_araddr;
output s_axi_arready;
input [2:0]s_axi_arprot;
output s_axi_rvalid;
input s_axi_rready;
output [1:0]s_axi_rresp;
output [31:0]s_axi_rdata;
output irq;
input spi_clk;
output spi_resetn;
input cmd_ready;
output cmd_valid;
output [15:0]cmd_data;
input sdo_data_ready;
output sdo_data_valid;
output [7:0]sdo_data;
output sdi_data_ready;
input sdi_data_valid;
input [7:0]sdi_data;
output sync_ready;
input sync_valid;
input [7:0]sync_data;
endmodule
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0_stub.vhdl
+65
View File
@@ -0,0 +1,65 @@
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
-- Date : Sun Sep 29 16:31:49 2024
-- Host : gatsby-dev running 64-bit Red Hat Enterprise Linux release 8.10 (Ootpa)
-- Command : write_vhdl -force -mode synth_stub
-- /home/josh/Workspace/CX9261A/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0_stub.vhdl
-- Design : system_bd_axi_spi_engine_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z045ffg900-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_bd_axi_spi_engine_0_0 is
Port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_awready : out STD_LOGIC;
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wready : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bready : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_arready : out STD_LOGIC;
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
irq : out STD_LOGIC;
spi_clk : in STD_LOGIC;
spi_resetn : out STD_LOGIC;
cmd_ready : in STD_LOGIC;
cmd_valid : out STD_LOGIC;
cmd_data : out STD_LOGIC_VECTOR ( 15 downto 0 );
sdo_data_ready : in STD_LOGIC;
sdo_data_valid : out STD_LOGIC;
sdo_data : out STD_LOGIC_VECTOR ( 7 downto 0 );
sdi_data_ready : out STD_LOGIC;
sdi_data_valid : in STD_LOGIC;
sdi_data : in STD_LOGIC_VECTOR ( 7 downto 0 );
sync_ready : out STD_LOGIC;
sync_valid : in STD_LOGIC;
sync_data : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
end system_bd_axi_spi_engine_0_0;
architecture stub of system_bd_axi_spi_engine_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "s_axi_aclk,s_axi_aresetn,s_axi_awvalid,s_axi_awaddr[15:0],s_axi_awready,s_axi_awprot[2:0],s_axi_wvalid,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wready,s_axi_bvalid,s_axi_bresp[1:0],s_axi_bready,s_axi_arvalid,s_axi_araddr[15:0],s_axi_arready,s_axi_arprot[2:0],s_axi_rvalid,s_axi_rready,s_axi_rresp[1:0],s_axi_rdata[31:0],irq,spi_clk,spi_resetn,cmd_ready,cmd_valid,cmd_data[15:0],sdo_data_ready,sdo_data_valid,sdo_data[7:0],sdi_data_ready,sdi_data_valid,sdi_data[7:0],sync_ready,sync_valid,sync_data[7:0]";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "axi_spi_engine,Vivado 2019.1.3";
begin
end;
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_processing_system7_0_0/ps7_parameters.xml
+643
View File
@@ -0,0 +1,643 @@
<?xml version="1.0" encoding="UTF-8" ?>
<!DOCTYPE designInfo PUBLIC "designInfo" "designInfo.dtd" >
<designInfo version="1.0" >
<MODULE IP_TYPE="SOC" MOD_CLASS="CONFIGURABLE" MODTYPE="processing_system7" >
<PARAMETERS >
<PARAMETER NAME="PCW_APU_CLK_RATIO_ENABLE" VALUE="6:2:1" />
<PARAMETER NAME="PCW_APU_PERIPHERAL_FREQMHZ" VALUE="667.000000" />
<PARAMETER NAME="PCW_ARMPLL_CTRL_FBDIV" VALUE="40" />
<PARAMETER NAME="PCW_CAN0_CAN0_IO" VALUE="" />
<PARAMETER NAME="PCW_CAN0_GRP_CLK_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_CAN0_GRP_CLK_IO" VALUE="" />
<PARAMETER NAME="PCW_CAN0_PERIPHERAL_CLKSRC" VALUE="External" />
<PARAMETER NAME="PCW_CAN0_PERIPHERAL_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_CAN0_PERIPHERAL_FREQMHZ" VALUE="" />
<PARAMETER NAME="PCW_CAN1_CAN1_IO" VALUE="" />
<PARAMETER NAME="PCW_CAN1_GRP_CLK_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_CAN1_GRP_CLK_IO" VALUE="" />
<PARAMETER NAME="PCW_CAN1_PERIPHERAL_CLKSRC" VALUE="External" />
<PARAMETER NAME="PCW_CAN1_PERIPHERAL_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_CAN1_PERIPHERAL_FREQMHZ" VALUE="" />
<PARAMETER NAME="PCW_CAN_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
<PARAMETER NAME="PCW_CAN_PERIPHERAL_DIVISOR0" VALUE="1" />
<PARAMETER NAME="PCW_CAN_PERIPHERAL_DIVISOR1" VALUE="1" />
<PARAMETER NAME="PCW_CAN_PERIPHERAL_FREQMHZ" VALUE="100" />
<PARAMETER NAME="PCW_CPU_CPU_PLL_FREQMHZ" VALUE="1333.333" />
<PARAMETER NAME="PCW_CPU_PERIPHERAL_CLKSRC" VALUE="ARM PLL" />
<PARAMETER NAME="PCW_CPU_PERIPHERAL_DIVISOR0" VALUE="2" />
<PARAMETER NAME="PCW_CRYSTAL_PERIPHERAL_FREQMHZ" VALUE="33.333333" />
<PARAMETER NAME="PCW_DCI_PERIPHERAL_CLKSRC" VALUE="DDR PLL" />
<PARAMETER NAME="PCW_DCI_PERIPHERAL_DIVISOR0" VALUE="15" />
<PARAMETER NAME="PCW_DCI_PERIPHERAL_DIVISOR1" VALUE="7" />
<PARAMETER NAME="PCW_DCI_PERIPHERAL_FREQMHZ" VALUE="10.159" />
<PARAMETER NAME="PCW_DDRPLL_CTRL_FBDIV" VALUE="32" />
<PARAMETER NAME="PCW_DDR_DDR_PLL_FREQMHZ" VALUE="1066.667" />
<PARAMETER NAME="PCW_DDR_HPRLPR_QUEUE_PARTITION" VALUE="HPR(0)/LPR(32)" />
<PARAMETER NAME="PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL" VALUE="15" />
<PARAMETER NAME="PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL" VALUE="2" />
<PARAMETER NAME="PCW_DDR_PERIPHERAL_CLKSRC" VALUE="DDR PLL" />
<PARAMETER NAME="PCW_DDR_PERIPHERAL_DIVISOR0" VALUE="2" />
<PARAMETER NAME="PCW_DDR_PORT0_HPR_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_DDR_PORT1_HPR_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_DDR_PORT2_HPR_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_DDR_PORT3_HPR_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_0" VALUE="" />
<PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_1" VALUE="" />
<PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_2" VALUE="" />
<PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_3" VALUE="" />
<PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_0" VALUE="" />
<PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_1" VALUE="" />
<PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_2" VALUE="" />
<PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_3" VALUE="" />
<PARAMETER NAME="PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL" VALUE="2" />
<PARAMETER NAME="PCW_DUAL_PARALLEL_QSPI_DATA_MODE" VALUE="x8" />
<PARAMETER NAME="PCW_DUAL_STACK_QSPI_DATA_MODE" VALUE="" />
<PARAMETER NAME="PCW_ENET0_ENET0_IO" VALUE="MIO 16 .. 27" />
<PARAMETER NAME="PCW_ENET0_GRP_MDIO_ENABLE" VALUE="1" />
<PARAMETER NAME="PCW_ENET0_GRP_MDIO_IO" VALUE="MIO 52 .. 53" />
<PARAMETER NAME="PCW_ENET0_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
<PARAMETER NAME="PCW_ENET0_PERIPHERAL_DIVISOR0" VALUE="8" />
<PARAMETER NAME="PCW_ENET0_PERIPHERAL_DIVISOR1" VALUE="5" />
<PARAMETER NAME="PCW_ENET0_PERIPHERAL_ENABLE" VALUE="1" />
<PARAMETER NAME="PCW_ENET0_PERIPHERAL_FREQMHZ" VALUE="100 Mbps" />
<PARAMETER NAME="PCW_ENET0_RESET_ENABLE" VALUE="1" />
<PARAMETER NAME="PCW_ENET0_RESET_IO" VALUE="MIO 47" />
<PARAMETER NAME="PCW_ENET1_ENET1_IO" VALUE="" />
<PARAMETER NAME="PCW_ENET1_GRP_MDIO_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_ENET1_GRP_MDIO_IO" VALUE="" />
<PARAMETER NAME="PCW_ENET1_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
<PARAMETER NAME="PCW_ENET1_PERIPHERAL_DIVISOR0" VALUE="1" />
<PARAMETER NAME="PCW_ENET1_PERIPHERAL_DIVISOR1" VALUE="1" />
<PARAMETER NAME="PCW_ENET1_PERIPHERAL_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_ENET1_PERIPHERAL_FREQMHZ" VALUE="1000 Mbps" />
<PARAMETER NAME="PCW_ENET1_RESET_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_ENET1_RESET_IO" VALUE="" />
<PARAMETER NAME="PCW_ENET_RESET_ENABLE" VALUE="1" />
<PARAMETER NAME="PCW_ENET_RESET_POLARITY" VALUE="Active Low" />
<PARAMETER NAME="PCW_ENET_RESET_SELECT" VALUE="Share reset pin" />
<PARAMETER NAME="PCW_EN_4K_TIMER" VALUE="0" />
<PARAMETER NAME="PCW_EN_CLK0_PORT" VALUE="1" />
<PARAMETER NAME="PCW_EN_CLK1_PORT" VALUE="1" />
<PARAMETER NAME="PCW_EN_CLK2_PORT" VALUE="0" />
<PARAMETER NAME="PCW_EN_CLK3_PORT" VALUE="0" />
<PARAMETER NAME="PCW_FCLK0_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
<PARAMETER NAME="PCW_FCLK0_PERIPHERAL_DIVISOR0" VALUE="5" />
<PARAMETER NAME="PCW_FCLK0_PERIPHERAL_DIVISOR1" VALUE="4" />
<PARAMETER NAME="PCW_FCLK1_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
<PARAMETER NAME="PCW_FCLK1_PERIPHERAL_DIVISOR0" VALUE="5" />
<PARAMETER NAME="PCW_FCLK1_PERIPHERAL_DIVISOR1" VALUE="1" />
<PARAMETER NAME="PCW_FCLK2_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
<PARAMETER NAME="PCW_FCLK2_PERIPHERAL_DIVISOR0" VALUE="1" />
<PARAMETER NAME="PCW_FCLK2_PERIPHERAL_DIVISOR1" VALUE="1" />
<PARAMETER NAME="PCW_FCLK3_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
<PARAMETER NAME="PCW_FCLK3_PERIPHERAL_DIVISOR0" VALUE="1" />
<PARAMETER NAME="PCW_FCLK3_PERIPHERAL_DIVISOR1" VALUE="1" />
<PARAMETER NAME="PCW_FCLK_CLK0_BUF" VALUE="TRUE" />
<PARAMETER NAME="PCW_FCLK_CLK1_BUF" VALUE="TRUE" />
<PARAMETER NAME="PCW_FCLK_CLK2_BUF" VALUE="FALSE" />
<PARAMETER NAME="PCW_FCLK_CLK3_BUF" VALUE="FALSE" />
<PARAMETER NAME="PCW_FPGA0_PERIPHERAL_FREQMHZ" VALUE="50" />
<PARAMETER NAME="PCW_FPGA1_PERIPHERAL_FREQMHZ" VALUE="200" />
<PARAMETER NAME="PCW_FPGA2_PERIPHERAL_FREQMHZ" VALUE="50" />
<PARAMETER NAME="PCW_FPGA3_PERIPHERAL_FREQMHZ" VALUE="50" />
<PARAMETER NAME="PCW_FTM_CTI_IN0" VALUE="" />
<PARAMETER NAME="PCW_FTM_CTI_IN1" VALUE="" />
<PARAMETER NAME="PCW_FTM_CTI_IN2" VALUE="" />
<PARAMETER NAME="PCW_FTM_CTI_IN3" VALUE="" />
<PARAMETER NAME="PCW_FTM_CTI_OUT0" VALUE="" />
<PARAMETER NAME="PCW_FTM_CTI_OUT1" VALUE="" />
<PARAMETER NAME="PCW_FTM_CTI_OUT2" VALUE="" />
<PARAMETER NAME="PCW_FTM_CTI_OUT3" VALUE="" />
<PARAMETER NAME="PCW_GPIO_EMIO_GPIO_ENABLE" VALUE="1" />
<PARAMETER NAME="PCW_GPIO_EMIO_GPIO_IO" VALUE="32" />
<PARAMETER NAME="PCW_GPIO_MIO_GPIO_ENABLE" VALUE="1" />
<PARAMETER NAME="PCW_GPIO_MIO_GPIO_IO" VALUE="MIO" />
<PARAMETER NAME="PCW_GPIO_PERIPHERAL_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_I2C0_GRP_INT_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_I2C0_GRP_INT_IO" VALUE="" />
<PARAMETER NAME="PCW_I2C0_I2C0_IO" VALUE="MIO 50 .. 51" />
<PARAMETER NAME="PCW_I2C0_PERIPHERAL_ENABLE" VALUE="1" />
<PARAMETER NAME="PCW_I2C0_RESET_ENABLE" VALUE="1" />
<PARAMETER NAME="PCW_I2C0_RESET_IO" VALUE="MIO 46" />
<PARAMETER NAME="PCW_I2C1_GRP_INT_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_I2C1_GRP_INT_IO" VALUE="" />
<PARAMETER NAME="PCW_I2C1_I2C1_IO" VALUE="" />
<PARAMETER NAME="PCW_I2C1_PERIPHERAL_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_I2C1_RESET_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_I2C1_RESET_IO" VALUE="" />
<PARAMETER NAME="PCW_I2C_RESET_ENABLE" VALUE="1" />
<PARAMETER NAME="PCW_I2C_RESET_POLARITY" VALUE="Active Low" />
<PARAMETER NAME="PCW_I2C_RESET_SELECT" VALUE="Share reset pin" />
<PARAMETER NAME="PCW_IOPLL_CTRL_FBDIV" VALUE="30" />
<PARAMETER NAME="PCW_IO_IO_PLL_FREQMHZ" VALUE="1000.000" />
<PARAMETER NAME="PCW_IRQ_F2P_MODE" VALUE="DIRECT" />
<PARAMETER NAME="PCW_MIO_0_DIRECTION" VALUE="out" />
<PARAMETER NAME="PCW_MIO_0_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_0_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_0_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_10_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_10_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_10_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_10_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_11_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_11_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_11_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_11_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_12_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_12_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_12_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_12_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_13_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_13_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_13_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_13_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_14_DIRECTION" VALUE="in" />
<PARAMETER NAME="PCW_MIO_14_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_14_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_14_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_15_DIRECTION" VALUE="in" />
<PARAMETER NAME="PCW_MIO_15_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_15_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_15_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_16_DIRECTION" VALUE="out" />
<PARAMETER NAME="PCW_MIO_16_IOTYPE" VALUE="HSTL 1.8V" />
<PARAMETER NAME="PCW_MIO_16_PULLUP" VALUE="disabled" />
<PARAMETER NAME="PCW_MIO_16_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_17_DIRECTION" VALUE="out" />
<PARAMETER NAME="PCW_MIO_17_IOTYPE" VALUE="HSTL 1.8V" />
<PARAMETER NAME="PCW_MIO_17_PULLUP" VALUE="disabled" />
<PARAMETER NAME="PCW_MIO_17_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_18_DIRECTION" VALUE="out" />
<PARAMETER NAME="PCW_MIO_18_IOTYPE" VALUE="HSTL 1.8V" />
<PARAMETER NAME="PCW_MIO_18_PULLUP" VALUE="disabled" />
<PARAMETER NAME="PCW_MIO_18_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_19_DIRECTION" VALUE="out" />
<PARAMETER NAME="PCW_MIO_19_IOTYPE" VALUE="HSTL 1.8V" />
<PARAMETER NAME="PCW_MIO_19_PULLUP" VALUE="disabled" />
<PARAMETER NAME="PCW_MIO_19_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_1_DIRECTION" VALUE="out" />
<PARAMETER NAME="PCW_MIO_1_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_1_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_1_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_20_DIRECTION" VALUE="out" />
<PARAMETER NAME="PCW_MIO_20_IOTYPE" VALUE="HSTL 1.8V" />
<PARAMETER NAME="PCW_MIO_20_PULLUP" VALUE="disabled" />
<PARAMETER NAME="PCW_MIO_20_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_21_DIRECTION" VALUE="out" />
<PARAMETER NAME="PCW_MIO_21_IOTYPE" VALUE="HSTL 1.8V" />
<PARAMETER NAME="PCW_MIO_21_PULLUP" VALUE="disabled" />
<PARAMETER NAME="PCW_MIO_21_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_22_DIRECTION" VALUE="in" />
<PARAMETER NAME="PCW_MIO_22_IOTYPE" VALUE="HSTL 1.8V" />
<PARAMETER NAME="PCW_MIO_22_PULLUP" VALUE="disabled" />
<PARAMETER NAME="PCW_MIO_22_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_23_DIRECTION" VALUE="in" />
<PARAMETER NAME="PCW_MIO_23_IOTYPE" VALUE="HSTL 1.8V" />
<PARAMETER NAME="PCW_MIO_23_PULLUP" VALUE="disabled" />
<PARAMETER NAME="PCW_MIO_23_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_24_DIRECTION" VALUE="in" />
<PARAMETER NAME="PCW_MIO_24_IOTYPE" VALUE="HSTL 1.8V" />
<PARAMETER NAME="PCW_MIO_24_PULLUP" VALUE="disabled" />
<PARAMETER NAME="PCW_MIO_24_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_25_DIRECTION" VALUE="in" />
<PARAMETER NAME="PCW_MIO_25_IOTYPE" VALUE="HSTL 1.8V" />
<PARAMETER NAME="PCW_MIO_25_PULLUP" VALUE="disabled" />
<PARAMETER NAME="PCW_MIO_25_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_26_DIRECTION" VALUE="in" />
<PARAMETER NAME="PCW_MIO_26_IOTYPE" VALUE="HSTL 1.8V" />
<PARAMETER NAME="PCW_MIO_26_PULLUP" VALUE="disabled" />
<PARAMETER NAME="PCW_MIO_26_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_27_DIRECTION" VALUE="in" />
<PARAMETER NAME="PCW_MIO_27_IOTYPE" VALUE="HSTL 1.8V" />
<PARAMETER NAME="PCW_MIO_27_PULLUP" VALUE="disabled" />
<PARAMETER NAME="PCW_MIO_27_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_28_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_28_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_28_PULLUP" VALUE="disabled" />
<PARAMETER NAME="PCW_MIO_28_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_29_DIRECTION" VALUE="in" />
<PARAMETER NAME="PCW_MIO_29_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_29_PULLUP" VALUE="disabled" />
<PARAMETER NAME="PCW_MIO_29_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_2_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_2_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_2_PULLUP" VALUE="disabled" />
<PARAMETER NAME="PCW_MIO_2_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_30_DIRECTION" VALUE="out" />
<PARAMETER NAME="PCW_MIO_30_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_30_PULLUP" VALUE="disabled" />
<PARAMETER NAME="PCW_MIO_30_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_31_DIRECTION" VALUE="in" />
<PARAMETER NAME="PCW_MIO_31_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_31_PULLUP" VALUE="disabled" />
<PARAMETER NAME="PCW_MIO_31_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_32_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_32_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_32_PULLUP" VALUE="disabled" />
<PARAMETER NAME="PCW_MIO_32_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_33_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_33_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_33_PULLUP" VALUE="disabled" />
<PARAMETER NAME="PCW_MIO_33_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_34_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_34_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_34_PULLUP" VALUE="disabled" />
<PARAMETER NAME="PCW_MIO_34_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_35_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_35_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_35_PULLUP" VALUE="disabled" />
<PARAMETER NAME="PCW_MIO_35_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_36_DIRECTION" VALUE="in" />
<PARAMETER NAME="PCW_MIO_36_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_36_PULLUP" VALUE="disabled" />
<PARAMETER NAME="PCW_MIO_36_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_37_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_37_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_37_PULLUP" VALUE="disabled" />
<PARAMETER NAME="PCW_MIO_37_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_38_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_38_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_38_PULLUP" VALUE="disabled" />
<PARAMETER NAME="PCW_MIO_38_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_39_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_39_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_39_PULLUP" VALUE="disabled" />
<PARAMETER NAME="PCW_MIO_39_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_3_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_3_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_3_PULLUP" VALUE="disabled" />
<PARAMETER NAME="PCW_MIO_3_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_40_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_40_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_40_PULLUP" VALUE="disabled" />
<PARAMETER NAME="PCW_MIO_40_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_41_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_41_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_41_PULLUP" VALUE="disabled" />
<PARAMETER NAME="PCW_MIO_41_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_42_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_42_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_42_PULLUP" VALUE="disabled" />
<PARAMETER NAME="PCW_MIO_42_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_43_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_43_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_43_PULLUP" VALUE="disabled" />
<PARAMETER NAME="PCW_MIO_43_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_44_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_44_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_44_PULLUP" VALUE="disabled" />
<PARAMETER NAME="PCW_MIO_44_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_45_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_45_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_45_PULLUP" VALUE="disabled" />
<PARAMETER NAME="PCW_MIO_45_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_46_DIRECTION" VALUE="out" />
<PARAMETER NAME="PCW_MIO_46_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_46_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_46_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_47_DIRECTION" VALUE="out" />
<PARAMETER NAME="PCW_MIO_47_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_47_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_47_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_48_DIRECTION" VALUE="out" />
<PARAMETER NAME="PCW_MIO_48_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_48_PULLUP" VALUE="disabled" />
<PARAMETER NAME="PCW_MIO_48_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_49_DIRECTION" VALUE="in" />
<PARAMETER NAME="PCW_MIO_49_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_49_PULLUP" VALUE="disabled" />
<PARAMETER NAME="PCW_MIO_49_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_4_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_4_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_4_PULLUP" VALUE="disabled" />
<PARAMETER NAME="PCW_MIO_4_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_50_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_50_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_50_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_50_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_51_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_51_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_51_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_51_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_52_DIRECTION" VALUE="out" />
<PARAMETER NAME="PCW_MIO_52_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_52_PULLUP" VALUE="disabled" />
<PARAMETER NAME="PCW_MIO_52_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_53_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_53_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_53_PULLUP" VALUE="disabled" />
<PARAMETER NAME="PCW_MIO_53_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_5_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_5_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_5_PULLUP" VALUE="disabled" />
<PARAMETER NAME="PCW_MIO_5_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_6_DIRECTION" VALUE="out" />
<PARAMETER NAME="PCW_MIO_6_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_6_PULLUP" VALUE="disabled" />
<PARAMETER NAME="PCW_MIO_6_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_7_DIRECTION" VALUE="out" />
<PARAMETER NAME="PCW_MIO_7_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_7_PULLUP" VALUE="disabled" />
<PARAMETER NAME="PCW_MIO_7_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_8_DIRECTION" VALUE="out" />
<PARAMETER NAME="PCW_MIO_8_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_8_PULLUP" VALUE="disabled" />
<PARAMETER NAME="PCW_MIO_8_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_9_DIRECTION" VALUE="out" />
<PARAMETER NAME="PCW_MIO_9_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_9_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_9_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_NAND_CYCLES_T_AR" VALUE="1" />
<PARAMETER NAME="PCW_NAND_CYCLES_T_CLR" VALUE="1" />
<PARAMETER NAME="PCW_NAND_CYCLES_T_RC" VALUE="11" />
<PARAMETER NAME="PCW_NAND_CYCLES_T_REA" VALUE="1" />
<PARAMETER NAME="PCW_NAND_CYCLES_T_RR" VALUE="1" />
<PARAMETER NAME="PCW_NAND_CYCLES_T_WC" VALUE="11" />
<PARAMETER NAME="PCW_NAND_CYCLES_T_WP" VALUE="1" />
<PARAMETER NAME="PCW_NAND_GRP_D8_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_NAND_GRP_D8_IO" VALUE="" />
<PARAMETER NAME="PCW_NAND_NAND_IO" VALUE="" />
<PARAMETER NAME="PCW_NAND_PERIPHERAL_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_NOR_CS0_T_CEOE" VALUE="1" />
<PARAMETER NAME="PCW_NOR_CS0_T_PC" VALUE="1" />
<PARAMETER NAME="PCW_NOR_CS0_T_RC" VALUE="11" />
<PARAMETER NAME="PCW_NOR_CS0_T_TR" VALUE="1" />
<PARAMETER NAME="PCW_NOR_CS0_T_WC" VALUE="11" />
<PARAMETER NAME="PCW_NOR_CS0_T_WP" VALUE="1" />
<PARAMETER NAME="PCW_NOR_CS0_WE_TIME" VALUE="0" />
<PARAMETER NAME="PCW_NOR_CS1_T_CEOE" VALUE="1" />
<PARAMETER NAME="PCW_NOR_CS1_T_PC" VALUE="1" />
<PARAMETER NAME="PCW_NOR_CS1_T_RC" VALUE="11" />
<PARAMETER NAME="PCW_NOR_CS1_T_TR" VALUE="1" />
<PARAMETER NAME="PCW_NOR_CS1_T_WC" VALUE="11" />
<PARAMETER NAME="PCW_NOR_CS1_T_WP" VALUE="1" />
<PARAMETER NAME="PCW_NOR_CS1_WE_TIME" VALUE="0" />
<PARAMETER NAME="PCW_NOR_GRP_A25_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_NOR_GRP_A25_IO" VALUE="" />
<PARAMETER NAME="PCW_NOR_GRP_CS0_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_NOR_GRP_CS0_IO" VALUE="" />
<PARAMETER NAME="PCW_NOR_GRP_CS1_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_NOR_GRP_CS1_IO" VALUE="" />
<PARAMETER NAME="PCW_NOR_GRP_SRAM_CS0_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_NOR_GRP_SRAM_CS0_IO" VALUE="" />
<PARAMETER NAME="PCW_NOR_GRP_SRAM_CS1_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_NOR_GRP_SRAM_CS1_IO" VALUE="" />
<PARAMETER NAME="PCW_NOR_GRP_SRAM_INT_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_NOR_GRP_SRAM_INT_IO" VALUE="" />
<PARAMETER NAME="PCW_NOR_NOR_IO" VALUE="" />
<PARAMETER NAME="PCW_NOR_PERIPHERAL_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_NOR_SRAM_CS0_T_CEOE" VALUE="1" />
<PARAMETER NAME="PCW_NOR_SRAM_CS0_T_PC" VALUE="1" />
<PARAMETER NAME="PCW_NOR_SRAM_CS0_T_RC" VALUE="11" />
<PARAMETER NAME="PCW_NOR_SRAM_CS0_T_TR" VALUE="1" />
<PARAMETER NAME="PCW_NOR_SRAM_CS0_T_WC" VALUE="11" />
<PARAMETER NAME="PCW_NOR_SRAM_CS0_T_WP" VALUE="1" />
<PARAMETER NAME="PCW_NOR_SRAM_CS0_WE_TIME" VALUE="0" />
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_CEOE" VALUE="1" />
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_PC" VALUE="1" />
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_RC" VALUE="11" />
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_TR" VALUE="1" />
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_WC" VALUE="11" />
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_WP" VALUE="1" />
<PARAMETER NAME="PCW_NOR_SRAM_CS1_WE_TIME" VALUE="0" />
<PARAMETER NAME="PCW_OVERRIDE_BASIC_CLOCK" VALUE="0" />
<PARAMETER NAME="PCW_PCAP_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
<PARAMETER NAME="PCW_PCAP_PERIPHERAL_DIVISOR0" VALUE="5" />
<PARAMETER NAME="PCW_PCAP_PERIPHERAL_FREQMHZ" VALUE="200" />
<PARAMETER NAME="PCW_PJTAG_PERIPHERAL_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_PJTAG_PJTAG_IO" VALUE="" />
<PARAMETER NAME="PCW_PLL_BYPASSMODE_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_PRESET_BANK0_VOLTAGE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_PRESET_BANK1_VOLTAGE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_QSPI_GRP_FBCLK_ENABLE" VALUE="1" />
<PARAMETER NAME="PCW_QSPI_GRP_FBCLK_IO" VALUE="MIO 8" />
<PARAMETER NAME="PCW_QSPI_GRP_IO1_ENABLE" VALUE="1" />
<PARAMETER NAME="PCW_QSPI_GRP_IO1_IO" VALUE="MIO 0 9 .. 13" />
<PARAMETER NAME="PCW_QSPI_GRP_SINGLE_SS_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_QSPI_GRP_SINGLE_SS_IO" VALUE="" />
<PARAMETER NAME="PCW_QSPI_GRP_SS1_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_QSPI_GRP_SS1_IO" VALUE="" />
<PARAMETER NAME="PCW_QSPI_INTERNAL_HIGHADDRESS" VALUE="0xFDFFFFFF" />
<PARAMETER NAME="PCW_QSPI_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
<PARAMETER NAME="PCW_QSPI_PERIPHERAL_DIVISOR0" VALUE="5" />
<PARAMETER NAME="PCW_QSPI_PERIPHERAL_ENABLE" VALUE="1" />
<PARAMETER NAME="PCW_QSPI_PERIPHERAL_FREQMHZ" VALUE="200" />
<PARAMETER NAME="PCW_QSPI_QSPI_IO" VALUE="MIO 1 .. 6" />
<PARAMETER NAME="PCW_SD0_GRP_CD_ENABLE" VALUE="1" />
<PARAMETER NAME="PCW_SD0_GRP_CD_IO" VALUE="MIO 14" />
<PARAMETER NAME="PCW_SD0_GRP_POW_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_SD0_GRP_POW_IO" VALUE="" />
<PARAMETER NAME="PCW_SD0_GRP_WP_ENABLE" VALUE="1" />
<PARAMETER NAME="PCW_SD0_GRP_WP_IO" VALUE="MIO 15" />
<PARAMETER NAME="PCW_SD0_PERIPHERAL_ENABLE" VALUE="1" />
<PARAMETER NAME="PCW_SD0_SD0_IO" VALUE="MIO 40 .. 45" />
<PARAMETER NAME="PCW_SD1_GRP_CD_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_SD1_GRP_CD_IO" VALUE="" />
<PARAMETER NAME="PCW_SD1_GRP_POW_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_SD1_GRP_POW_IO" VALUE="" />
<PARAMETER NAME="PCW_SD1_GRP_WP_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_SD1_GRP_WP_IO" VALUE="" />
<PARAMETER NAME="PCW_SD1_PERIPHERAL_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_SD1_SD1_IO" VALUE="" />
<PARAMETER NAME="PCW_SDIO_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
<PARAMETER NAME="PCW_SDIO_PERIPHERAL_DIVISOR0" VALUE="20" />
<PARAMETER NAME="PCW_SDIO_PERIPHERAL_FREQMHZ" VALUE="50" />
<PARAMETER NAME="PCW_SINGLE_QSPI_DATA_MODE" VALUE="" />
<PARAMETER NAME="PCW_SMC_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
<PARAMETER NAME="PCW_SMC_PERIPHERAL_DIVISOR0" VALUE="1" />
<PARAMETER NAME="PCW_SMC_PERIPHERAL_FREQMHZ" VALUE="100" />
<PARAMETER NAME="PCW_SPI0_GRP_SS0_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_SPI0_GRP_SS0_IO" VALUE="" />
<PARAMETER NAME="PCW_SPI0_GRP_SS1_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_SPI0_GRP_SS1_IO" VALUE="" />
<PARAMETER NAME="PCW_SPI0_GRP_SS2_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_SPI0_GRP_SS2_IO" VALUE="" />
<PARAMETER NAME="PCW_SPI0_PERIPHERAL_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_SPI0_SPI0_IO" VALUE="" />
<PARAMETER NAME="PCW_SPI1_GRP_SS0_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_SPI1_GRP_SS0_IO" VALUE="" />
<PARAMETER NAME="PCW_SPI1_GRP_SS1_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_SPI1_GRP_SS1_IO" VALUE="" />
<PARAMETER NAME="PCW_SPI1_GRP_SS2_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_SPI1_GRP_SS2_IO" VALUE="" />
<PARAMETER NAME="PCW_SPI1_PERIPHERAL_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_SPI1_SPI1_IO" VALUE="" />
<PARAMETER NAME="PCW_SPI_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
<PARAMETER NAME="PCW_SPI_PERIPHERAL_DIVISOR0" VALUE="1" />
<PARAMETER NAME="PCW_SPI_PERIPHERAL_FREQMHZ" VALUE="166.666666" />
<PARAMETER NAME="PCW_S_AXI_HP0_DATA_WIDTH" VALUE="64" />
<PARAMETER NAME="PCW_S_AXI_HP1_DATA_WIDTH" VALUE="64" />
<PARAMETER NAME="PCW_S_AXI_HP2_DATA_WIDTH" VALUE="64" />
<PARAMETER NAME="PCW_S_AXI_HP3_DATA_WIDTH" VALUE="64" />
<PARAMETER NAME="PCW_TPIU_PERIPHERAL_CLKSRC" VALUE="External" />
<PARAMETER NAME="PCW_TPIU_PERIPHERAL_DIVISOR0" VALUE="1" />
<PARAMETER NAME="PCW_TPIU_PERIPHERAL_FREQMHZ" VALUE="200" />
<PARAMETER NAME="PCW_TRACE_GRP_16BIT_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_TRACE_GRP_16BIT_IO" VALUE="" />
<PARAMETER NAME="PCW_TRACE_GRP_2BIT_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_TRACE_GRP_2BIT_IO" VALUE="" />
<PARAMETER NAME="PCW_TRACE_GRP_32BIT_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_TRACE_GRP_32BIT_IO" VALUE="" />
<PARAMETER NAME="PCW_TRACE_GRP_4BIT_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_TRACE_GRP_4BIT_IO" VALUE="" />
<PARAMETER NAME="PCW_TRACE_GRP_8BIT_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_TRACE_GRP_8BIT_IO" VALUE="" />
<PARAMETER NAME="PCW_TRACE_INTERNAL_WIDTH" VALUE="2" />
<PARAMETER NAME="PCW_TRACE_PERIPHERAL_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_TRACE_TRACE_IO" VALUE="" />
<PARAMETER NAME="PCW_TTC0_CLK0_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
<PARAMETER NAME="PCW_TTC0_CLK0_PERIPHERAL_DIVISOR0" VALUE="1" />
<PARAMETER NAME="PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
<PARAMETER NAME="PCW_TTC0_CLK1_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
<PARAMETER NAME="PCW_TTC0_CLK1_PERIPHERAL_DIVISOR0" VALUE="1" />
<PARAMETER NAME="PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
<PARAMETER NAME="PCW_TTC0_CLK2_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
<PARAMETER NAME="PCW_TTC0_CLK2_PERIPHERAL_DIVISOR0" VALUE="1" />
<PARAMETER NAME="PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
<PARAMETER NAME="PCW_TTC0_PERIPHERAL_ENABLE" VALUE="1" />
<PARAMETER NAME="PCW_TTC0_TTC0_IO" VALUE="EMIO" />
<PARAMETER NAME="PCW_TTC1_CLK0_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
<PARAMETER NAME="PCW_TTC1_CLK0_PERIPHERAL_DIVISOR0" VALUE="1" />
<PARAMETER NAME="PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
<PARAMETER NAME="PCW_TTC1_CLK1_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
<PARAMETER NAME="PCW_TTC1_CLK1_PERIPHERAL_DIVISOR0" VALUE="1" />
<PARAMETER NAME="PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
<PARAMETER NAME="PCW_TTC1_CLK2_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
<PARAMETER NAME="PCW_TTC1_CLK2_PERIPHERAL_DIVISOR0" VALUE="1" />
<PARAMETER NAME="PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
<PARAMETER NAME="PCW_TTC1_PERIPHERAL_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_TTC1_TTC1_IO" VALUE="" />
<PARAMETER NAME="PCW_TTC_PERIPHERAL_FREQMHZ" VALUE="50" />
<PARAMETER NAME="PCW_UART0_BAUD_RATE" VALUE="115200" />
<PARAMETER NAME="PCW_UART0_GRP_FULL_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_UART0_GRP_FULL_IO" VALUE="" />
<PARAMETER NAME="PCW_UART0_PERIPHERAL_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_UART0_UART0_IO" VALUE="" />
<PARAMETER NAME="PCW_UART1_BAUD_RATE" VALUE="115200" />
<PARAMETER NAME="PCW_UART1_GRP_FULL_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_UART1_GRP_FULL_IO" VALUE="" />
<PARAMETER NAME="PCW_UART1_PERIPHERAL_ENABLE" VALUE="1" />
<PARAMETER NAME="PCW_UART1_UART1_IO" VALUE="MIO 48 .. 49" />
<PARAMETER NAME="PCW_UART_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
<PARAMETER NAME="PCW_UART_PERIPHERAL_DIVISOR0" VALUE="20" />
<PARAMETER NAME="PCW_UART_PERIPHERAL_FREQMHZ" VALUE="50" />
<PARAMETER NAME="PCW_UIPARAM_DDR_ADV_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_AL" VALUE="0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_BANK_ADDR_COUNT" VALUE="3" />
<PARAMETER NAME="PCW_UIPARAM_DDR_BL" VALUE="8" />
<PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY0" VALUE="0.521" />
<PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY1" VALUE="0.636" />
<PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY2" VALUE="0.54" />
<PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY3" VALUE="0.621" />
<PARAMETER NAME="PCW_UIPARAM_DDR_BUS_WIDTH" VALUE="32 Bit" />
<PARAMETER NAME="PCW_UIPARAM_DDR_CL" VALUE="7" />
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM" VALUE="0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH" VALUE="92.3275" />
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY" VALUE="160" />
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM" VALUE="0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH" VALUE="92.3275" />
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY" VALUE="160" />
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM" VALUE="0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH" VALUE="92.3275" />
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY" VALUE="160" />
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM" VALUE="0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH" VALUE="92.3275" />
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY" VALUE="160" />
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_STOP_EN" VALUE="0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_COL_ADDR_COUNT" VALUE="10" />
<PARAMETER NAME="PCW_UIPARAM_DDR_CWL" VALUE="6" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DEVICE_CAPACITY" VALUE="2048 MBits" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_0_LENGTH_MM" VALUE="0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH" VALUE="108.9255" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY" VALUE="160" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_1_LENGTH_MM" VALUE="0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH" VALUE="131.286" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY" VALUE="160" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_2_LENGTH_MM" VALUE="0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH" VALUE="131.83" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY" VALUE="160" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_3_LENGTH_MM" VALUE="0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH" VALUE="108.5285" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY" VALUE="160" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0" VALUE="0.226" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1" VALUE="0.278" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2" VALUE="0.184" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3" VALUE="0.309" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_0_LENGTH_MM" VALUE="0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH" VALUE="107.643" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY" VALUE="160" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_1_LENGTH_MM" VALUE="0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH" VALUE="132.917" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY" VALUE="160" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_2_LENGTH_MM" VALUE="0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH" VALUE="129.6135" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY" VALUE="160" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_3_LENGTH_MM" VALUE="0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH" VALUE="108.6395" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY" VALUE="160" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DRAM_WIDTH" VALUE="8 Bits" />
<PARAMETER NAME="PCW_UIPARAM_DDR_ECC" VALUE="Disabled" />
<PARAMETER NAME="PCW_UIPARAM_DDR_ENABLE" VALUE="1" />
<PARAMETER NAME="PCW_UIPARAM_DDR_FREQ_MHZ" VALUE="533.333313" />
<PARAMETER NAME="PCW_UIPARAM_DDR_HIGH_TEMP" VALUE="Normal (0-85)" />
<PARAMETER NAME="PCW_UIPARAM_DDR_MEMORY_TYPE" VALUE="DDR 3" />
<PARAMETER NAME="PCW_UIPARAM_DDR_PARTNO" VALUE="Custom" />
<PARAMETER NAME="PCW_UIPARAM_DDR_ROW_ADDR_COUNT" VALUE="15" />
<PARAMETER NAME="PCW_UIPARAM_DDR_SPEED_BIN" VALUE="DDR3_1066F" />
<PARAMETER NAME="PCW_UIPARAM_DDR_TRAIN_DATA_EYE" VALUE="1" />
<PARAMETER NAME="PCW_UIPARAM_DDR_TRAIN_READ_GATE" VALUE="1" />
<PARAMETER NAME="PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL" VALUE="1" />
<PARAMETER NAME="PCW_UIPARAM_DDR_T_FAW" VALUE="30.0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_T_RAS_MIN" VALUE="36.0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_T_RC" VALUE="49.5" />
<PARAMETER NAME="PCW_UIPARAM_DDR_T_RCD" VALUE="7" />
<PARAMETER NAME="PCW_UIPARAM_DDR_T_RP" VALUE="7" />
<PARAMETER NAME="PCW_UIPARAM_DDR_USE_INTERNAL_VREF" VALUE="1" />
<PARAMETER NAME="PCW_USB0_PERIPHERAL_ENABLE" VALUE="1" />
<PARAMETER NAME="PCW_USB0_PERIPHERAL_FREQMHZ" VALUE="60" />
<PARAMETER NAME="PCW_USB0_RESET_ENABLE" VALUE="1" />
<PARAMETER NAME="PCW_USB0_RESET_IO" VALUE="MIO 7" />
<PARAMETER NAME="PCW_USB0_USB0_IO" VALUE="MIO 28 .. 39" />
<PARAMETER NAME="PCW_USB1_PERIPHERAL_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_USB1_PERIPHERAL_FREQMHZ" VALUE="60" />
<PARAMETER NAME="PCW_USB1_RESET_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_USB1_RESET_IO" VALUE="" />
<PARAMETER NAME="PCW_USB1_USB1_IO" VALUE="" />
<PARAMETER NAME="PCW_USB_RESET_ENABLE" VALUE="1" />
<PARAMETER NAME="PCW_USB_RESET_POLARITY" VALUE="Active Low" />
<PARAMETER NAME="PCW_USB_RESET_SELECT" VALUE="Share reset pin" />
<PARAMETER NAME="PCW_USE_AXI_NONSECURE" VALUE="0" />
<PARAMETER NAME="PCW_USE_CROSS_TRIGGER" VALUE="0" />
<PARAMETER NAME="PCW_USE_M_AXI_GP0" VALUE="1" />
<PARAMETER NAME="PCW_USE_M_AXI_GP1" VALUE="0" />
<PARAMETER NAME="PCW_USE_S_AXI_ACP" VALUE="0" />
<PARAMETER NAME="PCW_USE_S_AXI_GP0" VALUE="0" />
<PARAMETER NAME="PCW_USE_S_AXI_GP1" VALUE="0" />
<PARAMETER NAME="PCW_USE_S_AXI_HP0" VALUE="0" />
<PARAMETER NAME="PCW_USE_S_AXI_HP1" VALUE="0" />
<PARAMETER NAME="PCW_USE_S_AXI_HP2" VALUE="0" />
<PARAMETER NAME="PCW_USE_S_AXI_HP3" VALUE="0" />
<PARAMETER NAME="PCW_WDT_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
<PARAMETER NAME="PCW_WDT_PERIPHERAL_DIVISOR0" VALUE="1" />
<PARAMETER NAME="PCW_WDT_PERIPHERAL_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_WDT_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
<PARAMETER NAME="PCW_WDT_WDT_IO" VALUE="" />
</PARAMETERS>
<BUSINTERFACES >
<BUSINTERFACE NAME="M_AXI_GP0" TYPE="MASTER" WIDTH="32" PARAMTOENABLE="PCW_USE_M_AXI_GP0" VALUE="1" />
<BUSINTERFACE NAME="M_AXI_GP1" TYPE="MASTER" WIDTH="32" PARAMTOENABLE="PCW_USE_M_AXI_GP1" VALUE="0" />
<BUSINTERFACE NAME="S_AXI_GP0" TYPE="TARGET" WIDTH="32" PARAMTOENABLE="PCW_USE_S_AXI_GP0" VALUE="0" />
<BUSINTERFACE NAME="S_AXI_GP0" TYPE="TARGET" WIDTH="32" PARAMTOENABLE="PCW_USE_S_AXI_GP1" VALUE="0" />
<BUSINTERFACE NAME="S_AXI_HP0" TYPE="TARGET" WIDTH="64" PARAMTOENABLE="PCW_USE_S_AXI_HP0" VALUE="0" />
<BUSINTERFACE NAME="S_AXI_HP1" TYPE="TARGET" WIDTH="64" PARAMTOENABLE="PCW_USE_S_AXI_HP1" VALUE="0" />
<BUSINTERFACE NAME="S_AXI_HP2" TYPE="TARGET" WIDTH="64" PARAMTOENABLE="PCW_USE_S_AXI_HP2" VALUE="0" />
<BUSINTERFACE NAME="S_AXI_HP3" TYPE="TARGET" WIDTH="64" PARAMTOENABLE="PCW_USE_S_AXI_HP1" VALUE="0" />
</BUSINTERFACES>
<CLOCKOUTS >
<CLOCKOUT NAME="FCLK_CLK0" FREQUENCY="50.000000" />
<CLOCKOUT NAME="FCLK_CLK1" FREQUENCY="200.000000" />
<CLOCKOUT NAME="FCLK_CLK2" FREQUENCY="10.000000" />
<CLOCKOUT NAME="FCLK_CLK3" FREQUENCY="10.000000" />
</CLOCKOUTS>
</MODULE>
</designInfo>
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_processing_system7_0_0/system_bd_processing_system7_0_0.xci
+1318
View File
File diff suppressed because it is too large Load Diff
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_rst_ps7_50M_0/system_bd_rst_ps7_50M_0.xci
+196
View File
@@ -0,0 +1,196 @@
{
"schema": "xilinx.com:schema:json_instance:1.0",
"ip_inst": {
"xci_name": "system_bd_rst_ps7_50M_0",
"cell_name": "rst_ps7_50M",
"component_reference": "xilinx.com:ip:proc_sys_reset:5.0",
"ip_revision": "15",
"gen_directory": "../../../../../../zc706_cx9261a_demo.gen/sources_1/bd/system_bd/ip/system_bd_rst_ps7_50M_0",
"parameters": {
"component_parameters": {
"C_NUM_PERP_ARESETN": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"C_NUM_INTERCONNECT_ARESETN": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"C_NUM_PERP_RST": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"C_NUM_BUS_RST": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"C_AUX_RESET_HIGH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"C_EXT_RESET_HIGH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
"C_AUX_RST_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
"C_EXT_RST_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Component_Name": [ { "value": "system_bd_rst_ps7_50M_0", "resolve_type": "user", "usage": "all" } ],
"USE_BOARD_FLOW": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"RESET_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ]
},
"model_parameters": {
"C_FAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ],
"C_EXT_RST_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AUX_RST_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_EXT_RESET_HIGH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AUX_RESET_HIGH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_NUM_BUS_RST": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_NUM_PERP_RST": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_NUM_INTERCONNECT_ARESETN": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_NUM_PERP_ARESETN": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ]
},
"project_parameters": {
"ARCHITECTURE": [ { "value": "zynq" } ],
"BASE_BOARD_PART": [ { "value": "xilinx.com:zc706:part0:1.4" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xc7z045" } ],
"NEXTGEN_VERSAL": [ { "value": "0" } ],
"PACKAGE": [ { "value": "ffg900" } ],
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "" } ]
},
"runtime_parameters": {
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
"IPREVISION": [ { "value": "15" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "../../../../../../zc706_cx9261a_demo.gen/sources_1/bd/system_bd/ip/system_bd_rst_ps7_50M_0" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2024.1" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
}
},
"boundary": {
"ports": {
"slowest_sync_clk": [ { "direction": "in" } ],
"ext_reset_in": [ { "direction": "in" } ],
"aux_reset_in": [ { "direction": "in", "driver_value": "1" } ],
"mb_debug_sys_rst": [ { "direction": "in", "driver_value": "0" } ],
"dcm_locked": [ { "direction": "in", "driver_value": "0x1" } ],
"mb_reset": [ { "direction": "out", "driver_value": "0x0" } ],
"bus_struct_reset": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"peripheral_reset": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"interconnect_aresetn": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "1" } ],
"peripheral_aresetn": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "1" } ]
},
"interfaces": {
"clock": {
"vlnv": "xilinx.com:signal:clock:1.0",
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
"mode": "slave",
"parameters": {
"ASSOCIATED_RESET": [ { "value": "mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
"FREQ_HZ": [ { "value": "5e+07", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"CLK": [ { "physical_name": "slowest_sync_clk" } ]
}
},
"ext_reset": {
"vlnv": "xilinx.com:signal:reset:1.0",
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
"mode": "slave",
"parameters": {
"BOARD.ASSOCIATED_PARAM": [ { "value": "RESET_BOARD_INTERFACE", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
"POLARITY": [ { "value": "ACTIVE_LOW", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"RST": [ { "physical_name": "ext_reset_in" } ]
}
},
"aux_reset": {
"vlnv": "xilinx.com:signal:reset:1.0",
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
"mode": "slave",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"RST": [ { "physical_name": "aux_reset_in" } ]
}
},
"dbg_reset": {
"vlnv": "xilinx.com:signal:reset:1.0",
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
"mode": "slave",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"RST": [ { "physical_name": "mb_debug_sys_rst" } ]
}
},
"mb_rst": {
"vlnv": "xilinx.com:signal:reset:1.0",
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
"mode": "master",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
"TYPE": [ { "value": "PROCESSOR", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"RST": [ { "physical_name": "mb_reset" } ]
}
},
"bus_struct_reset": {
"vlnv": "xilinx.com:signal:reset:1.0",
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
"mode": "master",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
"TYPE": [ { "value": "INTERCONNECT", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"RST": [ { "physical_name": "bus_struct_reset" } ]
}
},
"interconnect_low_rst": {
"vlnv": "xilinx.com:signal:reset:1.0",
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
"mode": "master",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
"TYPE": [ { "value": "INTERCONNECT", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"RST": [ { "physical_name": "interconnect_aresetn" } ]
}
},
"peripheral_high_rst": {
"vlnv": "xilinx.com:signal:reset:1.0",
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
"mode": "master",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
"TYPE": [ { "value": "PERIPHERAL", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"RST": [ { "physical_name": "peripheral_reset" } ]
}
},
"peripheral_low_rst": {
"vlnv": "xilinx.com:signal:reset:1.0",
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
"mode": "master",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
"TYPE": [ { "value": "PERIPHERAL", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"RST": [ { "physical_name": "peripheral_aresetn" } ]
}
}
}
}
}
}
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_spi_engine_execution_0_1/system_bd_spi_engine_execution_0_1.xci
+176
View File
@@ -0,0 +1,176 @@
{
"schema": "xilinx.com:schema:json_instance:1.0",
"ip_inst": {
"xci_name": "system_bd_spi_engine_execution_0_1",
"cell_name": "spi_engine_execution",
"component_reference": "analog.com:user:spi_engine_execution:1.0",
"ip_revision": "1",
"gen_directory": "../../../../../../zc706_cx9261a_demo.gen/sources_1/bd/system_bd/ip/system_bd_spi_engine_execution_0_1",
"parameters": {
"component_parameters": {
"NUM_OF_CS": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"DEFAULT_SPI_CFG": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"DEFAULT_CLK_DIV": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"DATA_WIDTH": [ { "value": "8", "resolve_type": "user", "format": "long", "usage": "all" } ],
"NUM_OF_SDI": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"SDO_DEFAULT": [ { "value": "\"0\"", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
"ECHO_SCLK": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"SDI_DELAY": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Component_Name": [ { "value": "system_bd_spi_engine_execution_0_1", "resolve_type": "user", "usage": "all" } ]
},
"model_parameters": {
"NUM_OF_CS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"DEFAULT_SPI_CFG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"DEFAULT_CLK_DIV": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"DATA_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"NUM_OF_SDI": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"SDO_DEFAULT": [ { "value": "\"0\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
"ECHO_SCLK": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
"SDI_DELAY": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ]
},
"project_parameters": {
"ARCHITECTURE": [ { "value": "zynq" } ],
"BASE_BOARD_PART": [ { "value": "xilinx.com:zc706:part0:1.4" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xc7z045" } ],
"NEXTGEN_VERSAL": [ { "value": "0" } ],
"PACKAGE": [ { "value": "ffg900" } ],
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "" } ]
},
"runtime_parameters": {
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
"IPREVISION": [ { "value": "1" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "../../../../../../zc706_cx9261a_demo.gen/sources_1/bd/system_bd/ip/system_bd_spi_engine_execution_0_1" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2024.1" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
}
},
"boundary": {
"ports": {
"clk": [ { "direction": "in" } ],
"resetn": [ { "direction": "in" } ],
"active": [ { "direction": "out" } ],
"cmd_ready": [ { "direction": "out" } ],
"cmd_valid": [ { "direction": "in" } ],
"cmd": [ { "direction": "in", "size_left": "15", "size_right": "0" } ],
"sdo_data_valid": [ { "direction": "in", "driver_value": "0" } ],
"sdo_data_ready": [ { "direction": "out" } ],
"sdo_data": [ { "direction": "in", "size_left": "7", "size_right": "0" } ],
"sdi_data_ready": [ { "direction": "in", "driver_value": "0" } ],
"sdi_data_valid": [ { "direction": "out" } ],
"sdi_data": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
"sync_ready": [ { "direction": "in" } ],
"sync_valid": [ { "direction": "out" } ],
"sync": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
"sclk": [ { "direction": "out" } ],
"sdo": [ { "direction": "out" } ],
"sdo_t": [ { "direction": "out" } ],
"sdi": [ { "direction": "in", "size_left": "0", "size_right": "0" } ],
"cs": [ { "direction": "out", "size_left": "0", "size_right": "0" } ],
"three_wire": [ { "direction": "out" } ]
},
"interfaces": {
"ctrl": {
"vlnv": "analog.com:interface:spi_engine_ctrl:1.0",
"abstraction_type": "analog.com:interface:spi_engine_ctrl_rtl:1.0",
"mode": "slave",
"port_maps": {
"cmd_ready": [ { "physical_name": "cmd_ready" } ],
"cmd_valid": [ { "physical_name": "cmd_valid" } ],
"cmd_data": [ { "physical_name": "cmd" } ],
"sdo_ready": [ { "physical_name": "sdo_data_ready" } ],
"sdo_valid": [ { "physical_name": "sdo_data_valid" } ],
"sdo_data": [ { "physical_name": "sdo_data" } ],
"sdi_ready": [ { "physical_name": "sdi_data_ready" } ],
"sdi_valid": [ { "physical_name": "sdi_data_valid" } ],
"sdi_data": [ { "physical_name": "sdi_data" } ],
"sync_ready": [ { "physical_name": "sync_ready" } ],
"sync_valid": [ { "physical_name": "sync_valid" } ],
"sync_data": [ { "physical_name": "sync" } ]
}
},
"ctrl_signal_clock": {
"vlnv": "xilinx.com:signal:clock:1.0",
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
"mode": "slave",
"parameters": {
"ASSOCIATED_BUSIF": [ { "value": "ctrl", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
"ASSOCIATED_RESET": [ { "value": "resetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"CLK": [ { "physical_name": "clk" } ]
}
},
"ctrl_signal_reset": {
"vlnv": "xilinx.com:signal:reset:1.0",
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
"mode": "slave",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"RST": [ { "physical_name": "resetn" } ]
}
},
"spi": {
"vlnv": "analog.com:interface:spi_engine:1.0",
"abstraction_type": "analog.com:interface:spi_engine_rtl:1.0",
"mode": "master",
"port_maps": {
"sclk": [ { "physical_name": "sclk" } ],
"sdi": [ { "physical_name": "sdi" } ],
"sdo": [ { "physical_name": "sdo" } ],
"sdo_t": [ { "physical_name": "sdo_t" } ],
"three_wire": [ { "physical_name": "three_wire" } ],
"cs": [ { "physical_name": "cs" } ]
}
},
"spi_signal_clock": {
"vlnv": "xilinx.com:signal:clock:1.0",
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
"mode": "slave",
"parameters": {
"ASSOCIATED_BUSIF": [ { "value": "spi", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
"ASSOCIATED_RESET": [ { "value": "resetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
"FREQ_HZ": [ { "value": "5e+07", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"CLK": [ { "physical_name": "clk" } ]
}
},
"spi_signal_reset": {
"vlnv": "xilinx.com:signal:reset:1.0",
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
"mode": "slave",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"RST": [ { "physical_name": "resetn" } ]
}
}
}
}
}
}
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_xadc_wiz_0_0/system_bd_xadc_wiz_0_0.xci
+419
View File
@@ -0,0 +1,419 @@
{
"schema": "xilinx.com:schema:json_instance:1.0",
"ip_inst": {
"xci_name": "system_bd_xadc_wiz_0_0",
"cell_name": "system_management",
"component_reference": "xilinx.com:ip:xadc_wiz:3.3",
"ip_revision": "10",
"gen_directory": "../../../../../../zc706_cx9261a_demo.gen/sources_1/bd/system_bd/ip/system_bd_xadc_wiz_0_0",
"parameters": {
"component_parameters": {
"Component_Name": [ { "value": "system_bd_xadc_wiz_0_0", "resolve_type": "user", "usage": "all" } ],
"INTERFACE_SELECTION": [ { "value": "Enable_AXI", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"SIM_FILE_SEL": [ { "value": "Default", "resolve_type": "user", "usage": "all" } ],
"SIM_FILE_REL_PATH": [ { "value": "./", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"NUM_WAVE": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"SIM_FILE_NAME": [ { "value": "design", "resolve_type": "user", "usage": "all" } ],
"WAVEFORM_TYPE": [ { "value": "CONSTANT", "resolve_type": "user", "usage": "all" } ],
"STIMULUS_FREQ": [ { "value": "1.0", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ],
"TIMING_MODE": [ { "value": "Continuous", "resolve_type": "user", "usage": "all" } ],
"STARTUP_CHANNEL_SELECTION": [ { "value": "single_channel", "resolve_type": "user", "usage": "all" } ],
"XADC_STARUP_SELECTION": [ { "value": "single_channel", "resolve_type": "user", "usage": "all" } ],
"ENABLE_DCLK": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"INCREASE_ACQUISITION_TIME": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"DCLK_FREQUENCY": [ { "value": "100", "resolve_type": "user", "format": "float", "usage": "all" } ],
"ADC_CONVERSION_RATE": [ { "value": "1000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"SEQUENCER_MODE": [ { "value": "Off", "resolve_type": "user", "usage": "all" } ],
"ENABLE_CALIBRATION_AVERAGING": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"ENABLE_DRP": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"ENABLE_RESET": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"ENABLE_CONVST": [ { "value": "true", "resolve_type": "user", "usage": "all" } ],
"ENABLE_CONVSTCLK": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"ENABLE_CHANNEL": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"ENABLE_EOC": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"ENABLE_EOS": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"ENABLE_BUSY": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"ENABLE_JTAGLOCKED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"ENABLE_JTAGMODIFIED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"ENABLE_JTAGBUSY": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"OT_ALARM": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"USER_TEMP_ALARM": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"VCCINT_ALARM": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"VCCAUX_ALARM": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"ENABLE_VBRAM_ALARM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"TEMPERATURE_ALARM_TRIGGER": [ { "value": "85.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"TEMPERATURE_ALARM_RESET": [ { "value": "60.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"TEMPERATURE_ALARM_OT_TRIGGER": [ { "value": "125.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"TEMPERATURE_ALARM_OT_RESET": [ { "value": "70.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"VCCINT_ALARM_LOWER": [ { "value": "0.97", "resolve_type": "user", "format": "float", "usage": "all" } ],
"VCCINT_ALARM_UPPER": [ { "value": "1.03", "resolve_type": "user", "format": "float", "usage": "all" } ],
"VCCAUX_ALARM_LOWER": [ { "value": "1.75", "resolve_type": "user", "format": "float", "usage": "all" } ],
"VCCAUX_ALARM_UPPER": [ { "value": "1.89", "resolve_type": "user", "format": "float", "usage": "all" } ],
"VBRAM_ALARM_LOWER": [ { "value": "0.95", "resolve_type": "user", "format": "float", "usage": "all" } ],
"VBRAM_ALARM_UPPER": [ { "value": "1.05", "resolve_type": "user", "format": "float", "usage": "all" } ],
"ENABLE_VCCPINT_ALARM": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"ENABLE_VCCPAUX_ALARM": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"ENABLE_VCCDDRO_ALARM": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"VCCDDRO_VOLT": [ { "value": "1_2", "resolve_type": "user", "usage": "all" } ],
"VCCPINT_ALARM_LOWER": [ { "value": "0.95", "resolve_type": "user", "format": "float", "usage": "all" } ],
"VCCPINT_ALARM_UPPER": [ { "value": "1.00", "resolve_type": "user", "format": "float", "usage": "all" } ],
"VCCPAUX_ALARM_LOWER": [ { "value": "1.71", "resolve_type": "user", "format": "float", "usage": "all" } ],
"VCCPAUX_ALARM_UPPER": [ { "value": "1.8", "resolve_type": "user", "format": "float", "usage": "all" } ],
"VCCDDRO_ALARM_LOWER": [ { "value": "1.2", "resolve_type": "user", "format": "float", "usage": "all" } ],
"VCCDDRO_ALARM_UPPER": [ { "value": "1.25", "resolve_type": "user", "format": "float", "usage": "all" } ],
"SINGLE_CHANNEL_SELECTION": [ { "value": "TEMPERATURE", "resolve_type": "user", "usage": "all" } ],
"SINGLE_CHANNEL_ENABLE_CALIBRATION": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"BIPOLAR_OPERATION": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"SINGLE_CHANNEL_ACQUISITION_TIME": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CHANNEL_AVERAGING": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
"ADC_OFFSET_CALIBRATION": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"ADC_OFFSET_AND_GAIN_CALIBRATION": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"SENSOR_OFFSET_CALIBRATION": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"SENSOR_OFFSET_AND_GAIN_CALIBRATION": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"ENABLE_EXTERNAL_MUX": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"EXTERNAL_MUX_CHANNEL": [ { "value": "VP_VN", "resolve_type": "user", "usage": "all" } ],
"EXTERNAL_MUXADDR_ENABLE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CHANNEL_ENABLE_CALIBRATION": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CHANNEL_ENABLE_TEMPERATURE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CHANNEL_ENABLE_VCCINT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CHANNEL_ENABLE_VCCAUX": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CHANNEL_ENABLE_VP_VN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CHANNEL_ENABLE_VREFP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CHANNEL_ENABLE_VREFN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CHANNEL_ENABLE_VBRAM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"AVERAGE_ENABLE_VBRAM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CHANNEL_ENABLE_VCCPINT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"AVERAGE_ENABLE_VCCPINT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CHANNEL_ENABLE_VCCPAUX": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"AVERAGE_ENABLE_VCCPAUX": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CHANNEL_ENABLE_VCCDDRO": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"AVERAGE_ENABLE_VCCDDRO": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CHANNEL_ENABLE_VAUXP0_VAUXN0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CHANNEL_ENABLE_VAUXP1_VAUXN1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CHANNEL_ENABLE_VAUXP2_VAUXN2": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CHANNEL_ENABLE_VAUXP3_VAUXN3": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CHANNEL_ENABLE_VAUXP4_VAUXN4": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CHANNEL_ENABLE_VAUXP5_VAUXN5": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CHANNEL_ENABLE_VAUXP6_VAUXN6": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CHANNEL_ENABLE_VAUXP7_VAUXN7": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CHANNEL_ENABLE_VAUXP8_VAUXN8": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CHANNEL_ENABLE_VAUXP9_VAUXN9": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CHANNEL_ENABLE_VAUXP10_VAUXN10": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CHANNEL_ENABLE_VAUXP11_VAUXN11": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CHANNEL_ENABLE_VAUXP12_VAUXN12": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CHANNEL_ENABLE_VAUXP13_VAUXN13": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CHANNEL_ENABLE_VAUXP14_VAUXN14": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CHANNEL_ENABLE_VAUXP15_VAUXN15": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"AVERAGE_ENABLE_VP_VN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"AVERAGE_ENABLE_VAUXP0_VAUXN0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"AVERAGE_ENABLE_VAUXP1_VAUXN1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"AVERAGE_ENABLE_VAUXP2_VAUXN2": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"AVERAGE_ENABLE_VAUXP3_VAUXN3": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"AVERAGE_ENABLE_VAUXP4_VAUXN4": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"AVERAGE_ENABLE_VAUXP5_VAUXN5": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"AVERAGE_ENABLE_VAUXP6_VAUXN6": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"AVERAGE_ENABLE_VAUXP7_VAUXN7": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"AVERAGE_ENABLE_VAUXP8_VAUXN8": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"AVERAGE_ENABLE_VAUXP9_VAUXN9": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"AVERAGE_ENABLE_VAUXP10_VAUXN10": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"AVERAGE_ENABLE_VAUXP11_VAUXN11": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"AVERAGE_ENABLE_VAUXP12_VAUXN12": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"AVERAGE_ENABLE_VAUXP13_VAUXN13": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"AVERAGE_ENABLE_VAUXP14_VAUXN14": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"AVERAGE_ENABLE_VAUXP15_VAUXN15": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"AVERAGE_ENABLE_TEMPERATURE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"AVERAGE_ENABLE_VCCINT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"AVERAGE_ENABLE_VCCAUX": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"BIPOLAR_VP_VN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"BIPOLAR_VAUXP0_VAUXN0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"BIPOLAR_VAUXP1_VAUXN1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"BIPOLAR_VAUXP2_VAUXN2": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"BIPOLAR_VAUXP3_VAUXN3": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"BIPOLAR_VAUXP4_VAUXN4": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"BIPOLAR_VAUXP5_VAUXN5": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"BIPOLAR_VAUXP6_VAUXN6": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"BIPOLAR_VAUXP7_VAUXN7": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"BIPOLAR_VAUXP8_VAUXN8": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"BIPOLAR_VAUXP9_VAUXN9": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"BIPOLAR_VAUXP10_VAUXN10": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"BIPOLAR_VAUXP11_VAUXN11": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"BIPOLAR_VAUXP12_VAUXN12": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"BIPOLAR_VAUXP13_VAUXN13": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"BIPOLAR_VAUXP14_VAUXN14": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"BIPOLAR_VAUXP15_VAUXN15": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"ACQUISITION_TIME_VP_VN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"ACQUISITION_TIME_VAUXP0_VAUXN0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"ACQUISITION_TIME_VAUXP1_VAUXN1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"ACQUISITION_TIME_VAUXP2_VAUXN2": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"ACQUISITION_TIME_VAUXP3_VAUXN3": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"ACQUISITION_TIME_VAUXP4_VAUXN4": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"ACQUISITION_TIME_VAUXP5_VAUXN5": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"ACQUISITION_TIME_VAUXP6_VAUXN6": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"ACQUISITION_TIME_VAUXP7_VAUXN7": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"ACQUISITION_TIME_VAUXP8_VAUXN8": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"ACQUISITION_TIME_VAUXP9_VAUXN9": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"ACQUISITION_TIME_VAUXP10_VAUXN10": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"ACQUISITION_TIME_VAUXP11_VAUXN11": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"ACQUISITION_TIME_VAUXP12_VAUXN12": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"ACQUISITION_TIME_VAUXP13_VAUXN13": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"ACQUISITION_TIME_VAUXP14_VAUXN14": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"ACQUISITION_TIME_VAUXP15_VAUXN15": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"ADDR_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
"DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
"ENABLE_JTAG_ARBITER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"ACQUISITION_TIME": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
"ENABLE_TEMP_BUS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"ENABLE_AXI4STREAM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"FIFO_DEPTH": [ { "value": "7", "resolve_type": "user", "format": "long", "usage": "all" } ],
"POWER_DOWN_ADCA": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"POWER_DOWN_ADCB": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ]
},
"model_parameters": {
"c_component_name": [ { "value": "system_bd_xadc_wiz_0_0", "resolve_type": "generated", "usage": "all" } ],
"C_SIM_FILE_SEL": [ { "value": "Default", "resolve_type": "generated", "usage": "all" } ],
"C_SIM_FILE_REL_PATH": [ { "value": "./", "resolve_type": "generated", "usage": "all" } ],
"C_SIM_FILE_NAME": [ { "value": "design", "resolve_type": "generated", "usage": "all" } ],
"C_HAS_DCLK": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_DRP": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_RESET": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_CONVST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_CONVSTCLK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_VP": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_VN": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_CHANNEL": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_EOC": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_EOS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_BUSY": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_JTAGLOCKED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_JTAGMODIFIED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_JTAGBUSY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_EXTERNAL_MUX": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_EXTERNAL_MUX_CHANNEL": [ { "value": "VP_VN", "resolve_type": "generated", "usage": "all" } ],
"C_EXTERNAL_MUXADDR_ENABLE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_DCLK_FREQUENCY": [ { "value": "100", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_SAMPLING_RATE": [ { "value": "961538.4615384615", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_HAS_OT_ALARM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_USER_TEMP_ALARM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_VCCINT_ALARM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_VCCAUX_ALARM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_VBRAM_ALARM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_VCCPINT_ALARM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_VCCPAUX_ALARM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_VCCDDRO_ALARM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_CONFIGURATION_R0": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_CONFIGURATION_R1": [ { "value": "12719", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_CONFIGURATION_R2": [ { "value": "1024", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_ALARM_LIMIT_R0": [ { "value": "46573", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_ALARM_LIMIT_R1": [ { "value": "22500", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_ALARM_LIMIT_R2": [ { "value": "41287", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_ALARM_LIMIT_R3": [ { "value": "51763", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_ALARM_LIMIT_R4": [ { "value": "43322", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_ALARM_LIMIT_R5": [ { "value": "21190", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_ALARM_LIMIT_R6": [ { "value": "38229", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_ALARM_LIMIT_R7": [ { "value": "44622", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_ALARM_LIMIT_R8": [ { "value": "22937", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_ALARM_LIMIT_R9": [ { "value": "20753", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_ALARM_LIMIT_R10": [ { "value": "21845", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_ALARM_LIMIT_R11": [ { "value": "20753", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_ALARM_LIMIT_R12": [ { "value": "39321", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_ALARM_LIMIT_R13": [ { "value": "37355", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_ALARM_LIMIT_R14": [ { "value": "27306", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_ALARM_LIMIT_R15": [ { "value": "26214", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_SEQUENCE_R0": [ { "value": "256", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_SEQUENCE_R1": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_SEQUENCE_R2": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_SEQUENCE_R3": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_SEQUENCE_R4": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_SEQUENCE_R5": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_SEQUENCE_R6": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_SEQUENCE_R7": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_VAUX0": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_VAUX1": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_VAUX2": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_VAUX3": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_VAUX4": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_VAUX5": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_VAUX6": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_VAUX7": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_VAUX8": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_VAUX9": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_VAUX10": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_VAUX11": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_VAUX12": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_VAUX13": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_VAUX14": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_VAUX15": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_AXI": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_AXI4STREAM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_TEMP_BUS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_FIFO_DEPTH": [ { "value": "7", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_INCLUDE_INTR": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ]
},
"project_parameters": {
"ARCHITECTURE": [ { "value": "zynq" } ],
"BASE_BOARD_PART": [ { "value": "xilinx.com:zc706:part0:1.4" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xc7z045" } ],
"NEXTGEN_VERSAL": [ { "value": "0" } ],
"PACKAGE": [ { "value": "ffg900" } ],
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "" } ]
},
"runtime_parameters": {
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
"IPREVISION": [ { "value": "10" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "../../../../../../zc706_cx9261a_demo.gen/sources_1/bd/system_bd/ip/system_bd_xadc_wiz_0_0" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2024.1" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
}
},
"boundary": {
"ports": {
"s_axi_aclk": [ { "direction": "in", "driver_value": "0" } ],
"s_axi_aresetn": [ { "direction": "in", "driver_value": "0" } ],
"s_axi_awaddr": [ { "direction": "in", "size_left": "10", "size_right": "0", "driver_value": "0" } ],
"s_axi_awvalid": [ { "direction": "in", "driver_value": "0" } ],
"s_axi_awready": [ { "direction": "out" } ],
"s_axi_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
"s_axi_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
"s_axi_wvalid": [ { "direction": "in", "driver_value": "0" } ],
"s_axi_wready": [ { "direction": "out" } ],
"s_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
"s_axi_bvalid": [ { "direction": "out" } ],
"s_axi_bready": [ { "direction": "in", "driver_value": "0" } ],
"s_axi_araddr": [ { "direction": "in", "size_left": "10", "size_right": "0", "driver_value": "0" } ],
"s_axi_arvalid": [ { "direction": "in", "driver_value": "0" } ],
"s_axi_arready": [ { "direction": "out" } ],
"s_axi_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
"s_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
"s_axi_rvalid": [ { "direction": "out" } ],
"s_axi_rready": [ { "direction": "in", "driver_value": "0" } ],
"ip2intc_irpt": [ { "direction": "out" } ],
"vp_in": [ { "direction": "in", "driver_value": "0" } ],
"vn_in": [ { "direction": "in", "driver_value": "0" } ],
"channel_out": [ { "direction": "out", "size_left": "4", "size_right": "0" } ],
"eoc_out": [ { "direction": "out" } ],
"alarm_out": [ { "direction": "out" } ],
"eos_out": [ { "direction": "out" } ],
"busy_out": [ { "direction": "out" } ]
},
"interfaces": {
"s_axi_lite": {
"vlnv": "xilinx.com:interface:aximm:1.0",
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
"mode": "slave",
"parameters": {
"DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "5e+07", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ADDR_WIDTH": [ { "value": "11", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_PROT": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_WSTRB": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_BRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_RRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_READ_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"MAX_BURST_LENGTH": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"ARADDR": [ { "physical_name": "s_axi_araddr" } ],
"ARREADY": [ { "physical_name": "s_axi_arready" } ],
"ARVALID": [ { "physical_name": "s_axi_arvalid" } ],
"AWADDR": [ { "physical_name": "s_axi_awaddr" } ],
"AWREADY": [ { "physical_name": "s_axi_awready" } ],
"AWVALID": [ { "physical_name": "s_axi_awvalid" } ],
"BREADY": [ { "physical_name": "s_axi_bready" } ],
"BRESP": [ { "physical_name": "s_axi_bresp" } ],
"BVALID": [ { "physical_name": "s_axi_bvalid" } ],
"RDATA": [ { "physical_name": "s_axi_rdata" } ],
"RREADY": [ { "physical_name": "s_axi_rready" } ],
"RRESP": [ { "physical_name": "s_axi_rresp" } ],
"RVALID": [ { "physical_name": "s_axi_rvalid" } ],
"WDATA": [ { "physical_name": "s_axi_wdata" } ],
"WREADY": [ { "physical_name": "s_axi_wready" } ],
"WSTRB": [ { "physical_name": "s_axi_wstrb" } ],
"WVALID": [ { "physical_name": "s_axi_wvalid" } ]
}
},
"s_axi_aclk": {
"vlnv": "xilinx.com:signal:clock:1.0",
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
"mode": "slave",
"parameters": {
"ASSOCIATED_BUSIF": [ { "value": "s_axi_lite:M_AXIS", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
"ASSOCIATED_RESET": [ { "value": "s_axi_aresetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
"FREQ_HZ": [ { "value": "5e+07", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"CLK": [ { "physical_name": "s_axi_aclk" } ]
}
},
"s_axi_aresetn": {
"vlnv": "xilinx.com:signal:reset:1.0",
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
"mode": "slave",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"RST": [ { "physical_name": "s_axi_aresetn" } ]
}
},
"intr": {
"vlnv": "xilinx.com:signal:interrupt:1.0",
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
"mode": "master",
"parameters": {
"SENSITIVITY": [ { "value": "LEVEL_HIGH", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
"PortWidth": [ { "value": "1", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"INTERRUPT": [ { "physical_name": "ip2intc_irpt" } ]
}
},
"Vp_Vn": {
"vlnv": "xilinx.com:interface:diff_analog_io:1.0",
"abstraction_type": "xilinx.com:interface:diff_analog_io_rtl:1.0",
"mode": "slave",
"port_maps": {
"V_N": [ { "physical_name": "vn_in" } ],
"V_P": [ { "physical_name": "vp_in" } ]
}
}
}
}
}
}
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_xbar_0/system_bd_xbar_0.xci
+1523
View File
File diff suppressed because it is too large Load Diff
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_xlconcat_0_0/system_bd_xlconcat_0_0.xci
+308
View File
@@ -0,0 +1,308 @@
{
"schema": "xilinx.com:schema:json_instance:1.0",
"ip_inst": {
"xci_name": "system_bd_xlconcat_0_0",
"cell_name": "xlconcat_irq",
"component_reference": "xilinx.com:ip:xlconcat:2.1",
"ip_revision": "6",
"gen_directory": "../../../../../../zc706_cx9261a_demo.gen/sources_1/bd/system_bd/ip/system_bd_xlconcat_0_0",
"parameters": {
"component_parameters": {
"Component_Name": [ { "value": "system_bd_xlconcat_0_0", "resolve_type": "user", "usage": "all" } ],
"NUM_PORTS": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN0_WIDTH": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN1_WIDTH": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN2_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN3_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN4_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN5_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN6_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN7_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN8_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN9_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN10_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN11_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN12_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN13_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN14_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN15_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN16_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN17_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN18_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN19_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN20_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN21_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN22_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN23_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN24_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN25_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN26_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN27_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN28_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN29_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN30_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN31_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN32_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN33_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN34_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN35_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN36_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN37_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN38_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN39_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN40_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN41_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN42_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN43_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN44_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN45_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN46_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN47_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN48_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN49_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN50_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN51_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN52_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN53_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN54_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN55_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN56_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN57_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN58_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN59_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN60_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN61_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN62_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN63_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN64_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN65_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN66_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN67_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN68_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN69_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN70_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN71_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN72_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN73_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN74_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN75_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN76_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN77_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN78_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN79_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN80_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN81_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN82_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN83_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN84_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN85_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN86_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN87_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN88_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN89_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN90_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN91_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN92_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN93_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN94_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN95_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN96_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN97_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN98_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN99_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN100_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN101_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN102_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN103_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN104_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN105_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN106_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN107_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN108_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN109_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN110_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN111_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN112_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN113_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN114_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN115_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN116_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN117_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN118_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN119_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN120_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN121_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN122_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN123_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN124_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN125_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN126_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IN127_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"dout_width": [ { "value": "2", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ]
},
"model_parameters": {
"IN0_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN1_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN2_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN3_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN4_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN5_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN6_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN7_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN8_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN9_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN10_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN11_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN12_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN13_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN14_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN15_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN16_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN17_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN18_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN19_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN20_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN21_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN22_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN23_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN24_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN25_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN26_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN27_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN28_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN29_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN30_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN31_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN32_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN33_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN34_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN35_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN36_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN37_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN38_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN39_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN40_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN41_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN42_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN43_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN44_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN45_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN46_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN47_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN48_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN49_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN50_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN51_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN52_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN53_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN54_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN55_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN56_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN57_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN58_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN59_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN60_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN61_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN62_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN63_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN64_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN65_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN66_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN67_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN68_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN69_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN70_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN71_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN72_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN73_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN74_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN75_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN76_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN77_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN78_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN79_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN80_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN81_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN82_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN83_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN84_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN85_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN86_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN87_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN88_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN89_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN90_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN91_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN92_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN93_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN94_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN95_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN96_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN97_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN98_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN99_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN100_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN101_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN102_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN103_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN104_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN105_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN106_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN107_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN108_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN109_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN110_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN111_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN112_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN113_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN114_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN115_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN116_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN117_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN118_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN119_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN120_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN121_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN122_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN123_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN124_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN125_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN126_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IN127_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"dout_width": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"NUM_PORTS": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ]
},
"project_parameters": {
"ARCHITECTURE": [ { "value": "zynq" } ],
"BASE_BOARD_PART": [ { "value": "xilinx.com:zc706:part0:1.4" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xc7z045" } ],
"NEXTGEN_VERSAL": [ { "value": "0" } ],
"PACKAGE": [ { "value": "ffg900" } ],
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "" } ]
},
"runtime_parameters": {
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
"IPREVISION": [ { "value": "6" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "../../../../../../zc706_cx9261a_demo.gen/sources_1/bd/system_bd/ip/system_bd_xlconcat_0_0" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2024.1" } ],
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
}
},
"boundary": {
"ports": {
"In0": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"In1": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"dout": [ { "direction": "out", "size_left": "1", "size_right": "0" } ]
}
}
}
}
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ipshared/1cb1/axi_spi_engine.v
+625
View File
@@ -0,0 +1,625 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_spi_engine #(
parameter CMD_FIFO_ADDRESS_WIDTH = 4,
parameter SYNC_FIFO_ADDRESS_WIDTH = 4,
parameter SDO_FIFO_ADDRESS_WIDTH = 5,
parameter SDI_FIFO_ADDRESS_WIDTH = 5,
parameter MM_IF_TYPE = 0,
parameter ASYNC_SPI_CLK = 0,
parameter NUM_OFFLOAD = 0,
parameter OFFLOAD0_CMD_MEM_ADDRESS_WIDTH = 4,
parameter OFFLOAD0_SDO_MEM_ADDRESS_WIDTH = 4,
parameter ID = 0,
parameter [15:0] DATA_WIDTH = 8,
parameter [ 7:0] NUM_OF_SDI = 1 ) (
// Slave AXI interface
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [15:0] s_axi_awaddr,
output s_axi_awready,
input [2:0] s_axi_awprot,
input s_axi_wvalid,
input [31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [15:0] s_axi_araddr,
output s_axi_arready,
input [2:0] s_axi_arprot,
output s_axi_rvalid,
input s_axi_rready,
output [ 1:0] s_axi_rresp,
output [31:0] s_axi_rdata,
// up interface
input up_clk,
input up_rstn,
input up_wreq,
input [13:0] up_waddr,
input [31:0] up_wdata,
output up_wack,
input up_rreq,
input [13:0] up_raddr,
output [31:0] up_rdata,
output up_rack,
output reg irq,
// SPI signals
input spi_clk,
output spi_resetn,
input cmd_ready,
output cmd_valid,
output [15:0] cmd_data,
input sdo_data_ready,
output sdo_data_valid,
output [(DATA_WIDTH-1):0] sdo_data,
output sdi_data_ready,
input sdi_data_valid,
input [(NUM_OF_SDI * DATA_WIDTH-1):0] sdi_data,
output sync_ready,
input sync_valid,
input [7:0] sync_data,
// Offload ctrl signals
output offload0_cmd_wr_en,
output [15:0] offload0_cmd_wr_data,
output offload0_sdo_wr_en,
output [(DATA_WIDTH-1):0] offload0_sdo_wr_data,
output offload0_mem_reset,
output offload0_enable,
input offload0_enabled,
output offload_sync_ready,
input offload_sync_valid,
input [7:0] offload_sync_data);
localparam PCORE_VERSION = 'h010071;
localparam S_AXI = 0;
localparam UP_FIFO = 1;
wire clk;
wire rstn;
wire [CMD_FIFO_ADDRESS_WIDTH:0] cmd_fifo_room;
wire cmd_fifo_almost_empty;
wire [15:0] cmd_fifo_in_data;
wire cmd_fifo_in_ready;
wire cmd_fifo_in_valid;
wire [SDO_FIFO_ADDRESS_WIDTH:0] sdo_fifo_room;
wire sdo_fifo_almost_empty;
wire [(DATA_WIDTH-1):0] sdo_fifo_in_data;
wire sdo_fifo_in_ready;
wire sdo_fifo_in_valid;
wire sdi_fifo_out_data_msb_s;
wire [SDI_FIFO_ADDRESS_WIDTH:0] sdi_fifo_level;
wire sdi_fifo_almost_full;
wire [(NUM_OF_SDI * DATA_WIDTH-1):0] sdi_fifo_out_data;
wire sdi_fifo_out_ready;
wire sdi_fifo_out_valid;
wire [7:0] sync_fifo_data;
wire sync_fifo_valid;
wire [7:0] offload_sync_fifo_data;
wire offload_sync_fifo_valid;
reg up_sw_reset = 1'b1;
wire up_sw_resetn = ~up_sw_reset;
reg [31:0] up_rdata_ff = 'd0;
reg up_wack_ff = 1'b0;
reg up_rack_ff = 1'b0;
wire up_wreq_s;
wire up_rreq_s;
wire [31:0] up_wdata_s;
wire [13:0] up_waddr_s;
wire [13:0] up_raddr_s;
// Scratch register
reg [31:0] up_scratch = 'h00;
reg [7:0] sync_id = 'h00;
reg sync_id_pending = 1'b0;
reg [7:0] offload_sync_id = 'h00;
reg offload_sync_id_pending = 1'b0;
generate if (MM_IF_TYPE == S_AXI) begin
// assign clock and reset
assign clk = s_axi_aclk;
assign rstn = s_axi_aresetn;
// interface wrapper
up_axi #(
.AXI_ADDRESS_WIDTH (16)
) i_up_axi (
.up_rstn(rstn),
.up_clk(clk),
.up_axi_awvalid(s_axi_awvalid),
.up_axi_awaddr(s_axi_awaddr),
.up_axi_awready(s_axi_awready),
.up_axi_wvalid(s_axi_wvalid),
.up_axi_wdata(s_axi_wdata),
.up_axi_wstrb(s_axi_wstrb),
.up_axi_wready(s_axi_wready),
.up_axi_bvalid(s_axi_bvalid),
.up_axi_bresp(s_axi_bresp),
.up_axi_bready(s_axi_bready),
.up_axi_arvalid(s_axi_arvalid),
.up_axi_araddr(s_axi_araddr),
.up_axi_arready(s_axi_arready),
.up_axi_rvalid(s_axi_rvalid),
.up_axi_rresp(s_axi_rresp),
.up_axi_rdata(s_axi_rdata),
.up_axi_rready(s_axi_rready),
.up_wreq(up_wreq_s),
.up_waddr(up_waddr_s),
.up_wdata(up_wdata_s),
.up_wack(up_wack_ff),
.up_rreq(up_rreq_s),
.up_raddr(up_raddr_s),
.up_rdata(up_rdata_ff),
.up_rack(up_rack_ff)
);
assign up_rdata = 32'b0;
assign up_rack = 1'b0;
assign up_wack = 1'b0;
end
endgenerate
generate if (MM_IF_TYPE == UP_FIFO) begin
// assign clock and reset
assign clk = up_clk;
assign rstn = up_rstn;
assign up_wreq_s = up_wreq;
assign up_waddr_s = up_waddr;
assign up_wdata_s = up_wdata;
assign up_wack = up_wack_ff;
assign up_rreq_s = up_rreq;
assign up_raddr_s = up_raddr;
assign up_rdata = up_rdata_ff;
assign up_rack = up_rack_ff;
end
endgenerate
// IRQ handling
reg [3:0] up_irq_mask = 'h0;
wire [3:0] up_irq_source;
wire [3:0] up_irq_pending;
assign up_irq_source = {
offload_sync_id_pending,
sync_id_pending,
sdi_fifo_almost_full,
sdo_fifo_almost_empty,
cmd_fifo_almost_empty
};
assign up_irq_pending = up_irq_mask & up_irq_source;
always @(posedge clk) begin
if (rstn == 1'b0)
irq <= 1'b0;
else
irq <= |up_irq_pending;
end
always @(posedge clk) begin
if (rstn == 1'b0) begin
up_wack_ff <= 1'b0;
up_scratch <= 'h00;
up_sw_reset <= 1'b1;
end else begin
up_wack_ff <= up_wreq_s;
if (up_wreq_s) begin
case (up_waddr_s)
8'h02: up_scratch <= up_wdata_s;
8'h10: up_sw_reset <= up_wdata_s;
endcase
end
end
end
reg offload0_enable_reg;
reg offload0_mem_reset_reg;
wire offload0_enabled_s;
// the software reset should reset all the registers
always @(posedge clk) begin
if (up_sw_resetn == 1'b0) begin
up_irq_mask <= 'h00;
offload0_enable_reg <= 1'b0;
offload0_mem_reset_reg <= 1'b0;
end else begin
if (up_wreq_s) begin
case (up_waddr_s)
8'h20: up_irq_mask <= up_wdata_s;
8'h40: offload0_enable_reg <= up_wdata_s[0];
8'h42: offload0_mem_reset_reg <= up_wdata_s[0];
endcase
end
end
end
always @(posedge clk) begin
if (rstn == 1'b0) begin
up_rack_ff <= 'd0;
end else begin
up_rack_ff <= up_rreq_s;
end
end
generate
if (NUM_OF_SDI > 1) begin
// Only the first two SDI data can be recovered through AXI regmap
assign sdi_fifo_out_data_msb_s = sdi_fifo_out_data[DATA_WIDTH+:DATA_WIDTH];
end else begin
assign sdi_fifo_out_data_msb_s = sdi_fifo_out_data;
end
endgenerate
always @(posedge clk) begin
case (up_raddr_s)
8'h00: up_rdata_ff <= PCORE_VERSION;
8'h01: up_rdata_ff <= ID;
8'h02: up_rdata_ff <= up_scratch;
8'h03: up_rdata_ff <= {8'b0, NUM_OF_SDI, DATA_WIDTH};
8'h10: up_rdata_ff <= up_sw_reset;
8'h20: up_rdata_ff <= up_irq_mask;
8'h21: up_rdata_ff <= up_irq_pending;
8'h22: up_rdata_ff <= up_irq_source;
8'h30: up_rdata_ff <= sync_id;
8'h31: up_rdata_ff <= offload_sync_id;
8'h34: up_rdata_ff <= cmd_fifo_room;
8'h35: up_rdata_ff <= sdo_fifo_room;
8'h36: up_rdata_ff <= sdi_fifo_level;
8'h3a: up_rdata_ff <= sdi_fifo_out_data[DATA_WIDTH-1:0];
8'h3b: up_rdata_ff <= sdi_fifo_out_data_msb_s; /* store SDI's 32 bits MSB, if exists */
8'h3c: up_rdata_ff <= sdi_fifo_out_data; /* PEEK register */
8'h40: up_rdata_ff <= {offload0_enable_reg};
8'h41: up_rdata_ff <= {offload0_enabled_s};
default: up_rdata_ff <= 'h00;
endcase
end
always @(posedge clk) begin
if (up_sw_resetn == 1'b0) begin
sync_id <= 'h00;
sync_id_pending <= 1'b0;
end else begin
if (sync_fifo_valid == 1'b1) begin
sync_id <= sync_fifo_data;
sync_id_pending <= 1'b1;
end else if (up_wreq_s == 1'b1 && up_waddr_s == 8'h21 && up_wdata_s[3] == 1'b1) begin
sync_id_pending <= 1'b0;
end
end
end
always @(posedge clk) begin
if (up_sw_resetn == 1'b0) begin
offload_sync_id <= 'h00;
offload_sync_id_pending <= 1'b0;
end else begin
if (offload_sync_fifo_valid == 1'b1) begin
offload_sync_id <= offload_sync_fifo_data;
offload_sync_id_pending <= 1'b1;
end else if (up_wreq_s == 1'b1 && up_waddr_s == 8'h21 && up_wdata_s[3] == 1'b1) begin
offload_sync_id_pending <= 1'b0;
end
end
end
generate if (ASYNC_SPI_CLK) begin
wire spi_reset;
ad_rst i_spi_resetn (
.rst_async(up_sw_reset),
.clk(spi_clk),
.rst(spi_reset),
.rstn()
);
assign spi_resetn = ~spi_reset;
end else begin
assign spi_resetn = ~up_sw_reset;
end
endgenerate
/* Evaluates to true if FIFO level/room is 3/4 or above */
`define axi_spi_engine_check_watermark(x, n) \
(x[n] == 1'b1 || x[n-1:n-2] == 2'b11)
assign cmd_fifo_in_valid = up_wreq_s == 1'b1 && up_waddr_s == 8'h38;
assign cmd_fifo_in_data = up_wdata_s[15:0];
assign cmd_fifo_almost_empty =
`axi_spi_engine_check_watermark(cmd_fifo_room, CMD_FIFO_ADDRESS_WIDTH);
util_axis_fifo #(
.DATA_WIDTH(16),
.ASYNC_CLK(ASYNC_SPI_CLK),
.ADDRESS_WIDTH(CMD_FIFO_ADDRESS_WIDTH),
.S_AXIS_REGISTERED(0)
) i_cmd_fifo (
.s_axis_aclk(clk),
.s_axis_aresetn(up_sw_resetn),
.s_axis_ready(cmd_fifo_in_ready),
.s_axis_valid(cmd_fifo_in_valid),
.s_axis_data(cmd_fifo_in_data),
.s_axis_room(cmd_fifo_room),
.s_axis_empty(),
.m_axis_aclk(spi_clk),
.m_axis_aresetn(spi_resetn),
.m_axis_ready(cmd_ready),
.m_axis_valid(cmd_valid),
.m_axis_data(cmd_data),
.m_axis_level()
);
assign sdo_fifo_in_valid = up_wreq_s == 1'b1 && up_waddr_s == 8'h39;
assign sdo_fifo_in_data = up_wdata_s[(DATA_WIDTH-1):0];
assign sdo_fifo_almost_empty =
`axi_spi_engine_check_watermark(sdo_fifo_room, SDO_FIFO_ADDRESS_WIDTH);
util_axis_fifo #(
.DATA_WIDTH(DATA_WIDTH),
.ASYNC_CLK(ASYNC_SPI_CLK),
.ADDRESS_WIDTH(SDO_FIFO_ADDRESS_WIDTH),
.S_AXIS_REGISTERED(0)
) i_sdo_fifo (
.s_axis_aclk(clk),
.s_axis_aresetn(up_sw_resetn),
.s_axis_ready(sdo_fifo_in_ready),
.s_axis_valid(sdo_fifo_in_valid),
.s_axis_data(sdo_fifo_in_data),
.s_axis_room(sdo_fifo_room),
.s_axis_empty(),
.m_axis_aclk(spi_clk),
.m_axis_aresetn(spi_resetn),
.m_axis_ready(sdo_data_ready),
.m_axis_valid(sdo_data_valid),
.m_axis_data(sdo_data),
.m_axis_level()
);
assign sdi_fifo_out_ready = up_rreq_s == 1'b1 && up_raddr_s == 8'h3a;
assign sdi_fifo_almost_full =
`axi_spi_engine_check_watermark(sdi_fifo_level, SDI_FIFO_ADDRESS_WIDTH);
util_axis_fifo #(
.DATA_WIDTH(NUM_OF_SDI * DATA_WIDTH),
.ASYNC_CLK(ASYNC_SPI_CLK),
.ADDRESS_WIDTH(SDI_FIFO_ADDRESS_WIDTH),
.S_AXIS_REGISTERED(0)
) i_sdi_fifo (
.s_axis_aclk(spi_clk),
.s_axis_aresetn(spi_resetn),
.s_axis_ready(sdi_data_ready),
.s_axis_valid(sdi_data_valid),
.s_axis_data(sdi_data),
.s_axis_room(),
.s_axis_empty(),
.m_axis_aclk(clk),
.m_axis_aresetn(up_sw_resetn),
.m_axis_ready(sdi_fifo_out_ready),
.m_axis_valid(sdi_fifo_out_valid),
.m_axis_data(sdi_fifo_out_data),
.m_axis_level(sdi_fifo_level)
);
generate if (ASYNC_SPI_CLK) begin
// synchronization FIFO for the SYNC interface
util_axis_fifo #(
.DATA_WIDTH(8),
.ASYNC_CLK(ASYNC_SPI_CLK),
.ADDRESS_WIDTH(SYNC_FIFO_ADDRESS_WIDTH),
.S_AXIS_REGISTERED(0)
) i_sync_fifo (
.s_axis_aclk(spi_clk),
.s_axis_aresetn(spi_resetn),
.s_axis_ready(sync_ready),
.s_axis_valid(sync_valid),
.s_axis_data(sync_data),
.s_axis_room(),
.s_axis_empty(),
.m_axis_aclk(clk),
.m_axis_aresetn(up_sw_resetn),
.m_axis_ready(1'b1),
.m_axis_valid(sync_fifo_valid),
.m_axis_data(sync_fifo_data),
.m_axis_level()
);
// synchronization FIFO for the offload command interface
wire up_offload0_cmd_wr_en_s;
wire [15:0] up_offload0_cmd_wr_data_s;
util_axis_fifo #(
.DATA_WIDTH(16),
.ASYNC_CLK(ASYNC_SPI_CLK),
.ADDRESS_WIDTH(SYNC_FIFO_ADDRESS_WIDTH),
.S_AXIS_REGISTERED(0)
) i_offload_cmd_fifo (
.s_axis_aclk(clk),
.s_axis_aresetn(up_sw_resetn),
.s_axis_ready(),
.s_axis_valid(up_offload0_cmd_wr_en_s),
.s_axis_data(up_offload0_cmd_wr_data_s),
.s_axis_room(),
.s_axis_empty(),
.m_axis_aclk(spi_clk),
.m_axis_aresetn(spi_resetn),
.m_axis_ready(1'b1),
.m_axis_valid(offload0_cmd_wr_en),
.m_axis_data(offload0_cmd_wr_data),
.m_axis_level()
);
assign up_offload0_cmd_wr_en_s = up_wreq_s == 1'b1 && up_waddr_s == 8'h44;
assign up_offload0_cmd_wr_data_s = up_wdata_s[15:0];
// synchronization FIFO for the offload SDO interface
wire up_offload0_sdo_wr_en_s;
wire [DATA_WIDTH-1:0] up_offload0_sdo_wr_data_s;
util_axis_fifo #(
.DATA_WIDTH(DATA_WIDTH),
.ASYNC_CLK(ASYNC_SPI_CLK),
.ADDRESS_WIDTH(SYNC_FIFO_ADDRESS_WIDTH),
.S_AXIS_REGISTERED(0)
) i_offload_sdo_fifo (
.s_axis_aclk(clk),
.s_axis_aresetn(up_sw_resetn),
.s_axis_ready(),
.s_axis_valid(up_offload0_sdo_wr_en_s),
.s_axis_data(up_offload0_sdo_wr_data_s),
.s_axis_room(),
.s_axis_empty(),
.m_axis_aclk(spi_clk),
.m_axis_aresetn(spi_resetn),
.m_axis_ready(1'b1),
.m_axis_valid(offload0_sdo_wr_en),
.m_axis_data(offload0_sdo_wr_data),
.m_axis_level()
);
assign up_offload0_sdo_wr_en_s = up_wreq_s == 1'b1 && up_waddr_s == 8'h45;
assign up_offload0_sdo_wr_data_s = up_wdata_s[DATA_WIDTH-1:0];
// synchronization FIFO for the Offload SYNC interface
util_axis_fifo #(
.DATA_WIDTH(8),
.ASYNC_CLK(ASYNC_SPI_CLK),
.ADDRESS_WIDTH(SYNC_FIFO_ADDRESS_WIDTH),
.S_AXIS_REGISTERED(0)
) i_offload_sync_fifo (
.s_axis_aclk(spi_clk),
.s_axis_aresetn(spi_resetn),
.s_axis_ready(offload_sync_ready),
.s_axis_valid(offload_sync_valid),
.s_axis_data(offload_sync_data),
.s_axis_room(),
.s_axis_empty(),
.m_axis_aclk(clk),
.m_axis_aresetn(up_sw_resetn),
.m_axis_ready(1'b1),
.m_axis_valid(offload_sync_fifo_valid),
.m_axis_data(offload_sync_fifo_data),
.m_axis_level()
);
end else begin /* ASYNC_SPI_CLK == 0 */
assign sync_fifo_valid = sync_valid;
assign sync_fifo_data = sync_data;
assign sync_ready = 1'b1;
assign offload0_cmd_wr_en = up_wreq_s == 1'b1 && up_waddr_s == 8'h44;
assign offload0_cmd_wr_data = up_wdata_s[15:0];
assign offload0_sdo_wr_en = up_wreq_s == 1'b1 && up_waddr_s == 8'h45;
assign offload0_sdo_wr_data = up_wdata_s[DATA_WIDTH-1:0];
assign offload_sync_fifo_valid = offload_sync_valid;
assign offload_sync_fifo_data = offload_sync_data;
assign offload_sync_ready = 1'b1;
end
endgenerate
sync_bits #(
.NUM_OF_BITS (1),
.ASYNC_CLK (ASYNC_SPI_CLK)
) i_offload_enable_sync (
.in_bits (offload0_enable_reg),
.out_resetn (spi_resetn),
.out_clk (spi_clk),
.out_bits (offload0_enable));
sync_bits #(
.NUM_OF_BITS (1),
.ASYNC_CLK (ASYNC_SPI_CLK)
) i_offload_enabled_sync (
.in_bits (offload0_enabled),
.out_resetn (up_sw_resetn),
.out_clk (clk),
.out_bits (offload0_enabled_s));
sync_bits #(
.NUM_OF_BITS (1),
.ASYNC_CLK (ASYNC_SPI_CLK)
) i_offload_mem_reset_sync (
.in_bits (offload0_mem_reset_reg),
.out_resetn (spi_resetn),
.out_clk (spi_clk),
.out_bits (offload0_mem_reset));
endmodule
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ipshared/802c/spi_engine_execution.v
+456
View File
@@ -0,0 +1,456 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module spi_engine_execution #(
parameter NUM_OF_CS = 1,
parameter DEFAULT_SPI_CFG = 0,
parameter DEFAULT_CLK_DIV = 0,
parameter DATA_WIDTH = 8, // Valid data widths values are 8/16/24/32
parameter NUM_OF_SDI = 1,
parameter [0:0] SDO_DEFAULT = 1'b0,
parameter [1:0] SDI_DELAY = 2'b00) (
input clk,
input resetn,
output reg active,
output cmd_ready,
input cmd_valid,
input [15:0] cmd,
input sdo_data_valid,
output reg sdo_data_ready,
input [(DATA_WIDTH-1):0] sdo_data,
input sdi_data_ready,
output reg sdi_data_valid,
output [(NUM_OF_SDI * DATA_WIDTH)-1:0] sdi_data,
input sync_ready,
output reg sync_valid,
output [7:0] sync,
output reg sclk,
output reg sdo,
output reg sdo_t,
input [NUM_OF_SDI-1:0] sdi,
output reg [NUM_OF_CS-1:0] cs,
output reg three_wire
);
localparam CMD_TRANSFER = 2'b00;
localparam CMD_CHIPSELECT = 2'b01;
localparam CMD_WRITE = 2'b10;
localparam CMD_MISC = 2'b11;
localparam MISC_SYNC = 1'b0;
localparam MISC_SLEEP = 1'b1;
localparam REG_CLK_DIV = 2'b00;
localparam REG_CONFIG = 2'b01;
localparam REG_WORD_LENGTH = 2'b10;
localparam BIT_COUNTER_WIDTH = DATA_WIDTH > 16 ? 5 :
DATA_WIDTH > 8 ? 4 : 3;
localparam BIT_COUNTER_CARRY = 2** (BIT_COUNTER_WIDTH + 1);
localparam BIT_COUNTER_CLEAR = {{8{1'b1}}, {BIT_COUNTER_WIDTH{1'b0}}, 1'b1};
reg sclk_int = 1'b0;
wire sdo_int_s;
reg sdo_t_int = 1'b0;
reg idle;
reg [7:0] clk_div_counter = 'h00;
reg [7:0] clk_div_counter_next = 'h00;
reg clk_div_last;
reg [(BIT_COUNTER_WIDTH+8):0] counter = 'h00;
wire [7:0] sleep_counter = counter[(BIT_COUNTER_WIDTH+8):(BIT_COUNTER_WIDTH+1)];
wire [1:0] cs_sleep_counter = counter[(BIT_COUNTER_WIDTH+2):(BIT_COUNTER_WIDTH+1)];
wire [2:0] cs_sleep_counter2 = counter[(BIT_COUNTER_WIDTH+3):(BIT_COUNTER_WIDTH+1)];
wire [(BIT_COUNTER_WIDTH-1):0] bit_counter = counter[BIT_COUNTER_WIDTH:1];
wire [7:0] transfer_counter = counter[(BIT_COUNTER_WIDTH+8):(BIT_COUNTER_WIDTH+1)];
wire ntx_rx = counter[0];
reg trigger = 1'b0;
reg trigger_next = 1'b0;
reg wait_for_io = 1'b0;
reg transfer_active = 1'b0;
wire last_bit;
wire first_bit;
reg last_transfer;
reg [7:0] word_length = DATA_WIDTH;
reg [7:0] left_aligned = 8'b0;
wire end_of_word;
reg [7:0] sdi_counter = 8'b0;
assign first_bit = ((bit_counter == 'h0) || (bit_counter == word_length));
assign last_bit = bit_counter == word_length - 1;
assign end_of_word = last_bit == 1'b1 && ntx_rx == 1'b1 && clk_div_last == 1'b1;
reg [15:0] cmd_d1;
reg cpha = DEFAULT_SPI_CFG[0];
reg cpol = DEFAULT_SPI_CFG[1];
reg [7:0] clk_div = DEFAULT_CLK_DIV;
reg sdo_enabled = 1'b0;
reg sdi_enabled = 1'b0;
reg [(DATA_WIDTH-1):0] data_sdo_shift = 'h0;
reg [SDI_DELAY+1:0] trigger_rx_d = {(SDI_DELAY+2){1'b0}};
wire [1:0] inst = cmd[13:12];
wire [1:0] inst_d1 = cmd_d1[13:12];
wire exec_cmd = cmd_ready && cmd_valid;
wire exec_transfer_cmd = exec_cmd && inst == CMD_TRANSFER;
wire exec_write_cmd = exec_cmd && inst == CMD_WRITE;
wire exec_chipselect_cmd = exec_cmd && inst == CMD_CHIPSELECT;
wire exec_misc_cmd = exec_cmd && inst == CMD_MISC;
wire exec_sync_cmd = exec_misc_cmd && cmd[8] == MISC_SYNC;
wire trigger_tx;
wire trigger_rx;
wire sleep_counter_compare;
wire cs_sleep_counter_compare;
wire cs_sleep_counter_compare2;
wire io_ready1;
wire io_ready2;
wire trigger_rx_s;
wire last_sdi_bit;
assign cmd_ready = idle;
always @(posedge clk) begin
if (exec_transfer_cmd) begin
sdo_enabled <= cmd[8];
sdi_enabled <= cmd[9];
end
end
always @(posedge clk) begin
if (cmd_ready & cmd_valid)
cmd_d1 <= cmd;
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
active <= 1'b0;
end else begin
if (exec_cmd == 1'b1)
active <= 1'b1;
else if (sync_ready == 1'b1 && sync_valid == 1'b1)
active <= 1'b0;
end
end
// Load the interface configurations from the 'Configuration Write'
// instruction
always @(posedge clk) begin
if (resetn == 1'b0) begin
cpha <= DEFAULT_SPI_CFG[0];
cpol <= DEFAULT_SPI_CFG[1];
three_wire <= DEFAULT_SPI_CFG[2];
clk_div <= DEFAULT_CLK_DIV;
word_length <= DATA_WIDTH;
left_aligned <= 8'b0;
end else if (exec_write_cmd == 1'b1) begin
if (cmd[9:8] == REG_CONFIG) begin
cpha <= cmd[0];
cpol <= cmd[1];
three_wire <= cmd[2];
end else if (cmd[9:8] == REG_CLK_DIV) begin
clk_div <= cmd[7:0];
end else if (cmd[9:8] == REG_WORD_LENGTH) begin
// the max value of this reg must be DATA_WIDTH
word_length <= cmd[7:0];
left_aligned <= DATA_WIDTH - cmd[7:0];
end
end
end
always @(posedge clk) begin
if ((clk_div_last == 1'b0 && idle == 1'b0 && wait_for_io == 1'b0 &&
clk_div_counter == 'h01) || clk_div == 'h00)
clk_div_last <= 1'b1;
else
clk_div_last <= 1'b0;
end
always @(posedge clk) begin
if (clk_div_last == 1'b1 || idle == 1'b1 || wait_for_io == 1'b1) begin
clk_div_counter <= clk_div;
trigger <= 1'b1;
end else begin
clk_div_counter <= clk_div_counter - 1'b1;
trigger <= 1'b0;
end
end
assign trigger_tx = trigger == 1'b1 && ntx_rx == 1'b0;
assign trigger_rx = trigger == 1'b1 && ntx_rx == 1'b1;
assign sleep_counter_compare = sleep_counter == cmd_d1[7:0] && clk_div_last == 1'b1;
assign cs_sleep_counter_compare = cs_sleep_counter == cmd_d1[9:8] && clk_div_last == 1'b1;
assign cs_sleep_counter_compare2 = cs_sleep_counter2 == {cmd_d1[9:8],1'b1} && clk_div_last == 1'b1;
always @(posedge clk) begin
if (idle == 1'b1) begin
counter <= 'h00;
end else if (clk_div_last == 1'b1 && wait_for_io == 1'b0) begin
if (bit_counter == word_length) begin
counter <= (counter & BIT_COUNTER_CLEAR) + (transfer_active ? 'h1 : 'h10) + BIT_COUNTER_CARRY;
end else begin
counter <= counter + (transfer_active ? 'h1 : 'h10);
end
end
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
idle <= 1'b1;
end else begin
if (exec_transfer_cmd || exec_chipselect_cmd || exec_misc_cmd) begin
idle <= 1'b0;
end else begin
case (inst_d1)
CMD_TRANSFER: begin
if (transfer_active == 1'b0 && wait_for_io == 1'b0)
idle <= 1'b1;
end
CMD_CHIPSELECT: begin
if (cs_sleep_counter_compare2)
idle <= 1'b1;
end
CMD_MISC: begin
case (cmd_d1[8])
MISC_SLEEP: begin
if (sleep_counter_compare)
idle <= 1'b1;
end
MISC_SYNC: begin
if (sync_ready)
idle <= 1'b1;
end
endcase
end
endcase
end
end
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
cs <= 'hff;
end else if (inst_d1 == CMD_CHIPSELECT && cs_sleep_counter_compare == 1'b1) begin
cs <= cmd_d1[NUM_OF_CS-1:0];
end
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
sync_valid <= 1'b0;
end else begin
if (exec_sync_cmd == 1'b1) begin
sync_valid <= 1'b1;
end else if (sync_ready == 1'b1) begin
sync_valid <= 1'b0;
end
end
end
assign sync = cmd_d1[7:0];
always @(posedge clk) begin
if (resetn == 1'b0)
sdo_data_ready <= 1'b0;
else if (sdo_enabled == 1'b1 && first_bit == 1'b1 && trigger_tx == 1'b1 && transfer_active == 1'b1)
sdo_data_ready <= 1'b1;
else if (sdo_data_valid == 1'b1)
sdo_data_ready <= 1'b0;
end
always @(posedge clk) begin
if (resetn == 1'b0)
sdi_data_valid <= 1'b0;
else if (sdi_enabled == 1'b1 && last_sdi_bit == 1'b1 && trigger_rx_s == 1'b1)
sdi_data_valid <= 1'b1;
else if (sdi_data_ready == 1'b1)
sdi_data_valid <= 1'b0;
end
assign io_ready1 = (sdi_data_valid == 1'b0 || sdi_data_ready == 1'b1) &&
(sdo_enabled == 1'b0 || last_transfer == 1'b1 || sdo_data_valid == 1'b1);
assign io_ready2 = (sdi_enabled == 1'b0 || sdi_data_ready == 1'b1) &&
(sdo_enabled == 1'b0 || last_transfer == 1'b1 || sdo_data_valid == 1'b1);
always @(posedge clk) begin
if (idle == 1'b1) begin
last_transfer <= 1'b0;
end else if (trigger_tx == 1'b1 && transfer_active == 1'b1) begin
if (transfer_counter == cmd_d1[7:0])
last_transfer <= 1'b1;
else
last_transfer <= 1'b0;
end
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
transfer_active <= 1'b0;
wait_for_io <= 1'b0;
end else begin
if (exec_transfer_cmd == 1'b1) begin
wait_for_io <= 1'b1;
transfer_active <= 1'b0;
end else if (wait_for_io == 1'b1 && io_ready1 == 1'b1) begin
wait_for_io <= 1'b0;
if (last_transfer == 1'b0)
transfer_active <= 1'b1;
else
transfer_active <= 1'b0;
end else if (transfer_active == 1'b1 && end_of_word == 1'b1) begin
if (last_transfer == 1'b1 || io_ready2 == 1'b0)
transfer_active <= 1'b0;
if (io_ready2 == 1'b0)
wait_for_io <= 1'b1;
end
end
end
always @(posedge clk) begin
if (transfer_active == 1'b1 || wait_for_io == 1'b1)
begin
sdo_t_int <= ~sdo_enabled;
end else begin
sdo_t_int <= 1'b1;
end
end
// Load the SDO parallel data into the SDO shift register. In case of a custom
// data width, additional bit shifting must done at load.
always @(posedge clk) begin
if ((inst_d1 == CMD_TRANSFER) && (!sdo_enabled)) begin
data_sdo_shift <= {DATA_WIDTH{SDO_DEFAULT}};
end else if (transfer_active == 1'b1 && trigger_tx == 1'b1) begin
if (first_bit == 1'b1)
data_sdo_shift <= sdo_data << left_aligned;
else
data_sdo_shift <= {data_sdo_shift[(DATA_WIDTH-2):0], 1'b0};
end
end
assign sdo_int_s = data_sdo_shift[DATA_WIDTH-1];
// In case of an interface with high clock rate (SCLK > 50MHz), the latch of
// the SDI line can be delayed with 1, 2 or 3 SPI core clock cycle.
// Taking the fact that in high SCLK frequencies the pre-scaler most likely will
// be set to 0, to reduce the core clock's speed, this delay will mean that SDI will
// be latched at one of the next consecutive SCLK edge.
always @(posedge clk) begin
trigger_rx_d <= {trigger_rx_d, trigger_rx};
end
assign trigger_rx_s = trigger_rx_d[SDI_DELAY+1];
// Load the serial data into SDI shift register(s), then link it to the output
// register of the module
wire cs_active_s = (inst_d1 == CMD_CHIPSELECT) & ~(&cmd_d1[NUM_OF_CS-1:0]);
genvar i;
generate
for (i=0; i<NUM_OF_SDI; i=i+1) begin: g_sdi_shift_reg
reg [DATA_WIDTH-1:0] data_sdi_shift;
always @(posedge clk) begin
if (cs_active_s) begin
data_sdi_shift <= 0;
end else begin
if (trigger_rx_s == 1'b1) begin
data_sdi_shift <= {data_sdi_shift, sdi[i]};
end
end
end
assign sdi_data[i*DATA_WIDTH+:DATA_WIDTH] = data_sdi_shift;
end
endgenerate
assign last_sdi_bit = (sdi_counter == word_length-1);
always @(posedge clk) begin
if (resetn == 1'b0) begin
sdi_counter <= 8'b0;
end else begin
if (trigger_rx_s == 1'b1) begin
sdi_counter <= last_sdi_bit ? 8'b0 : sdi_counter + 1'b1;
end
end
end
always @(posedge clk) begin
if (transfer_active == 1'b1) begin
sclk_int <= cpol ^ cpha ^ ntx_rx;
end else begin
sclk_int <= cpol;
end
end
// Additional register stage to improve timing
always @(posedge clk) begin
sclk <= sclk_int;
sdo <= sdo_int_s;
sdo_t <= sdo_t_int;
end
endmodule
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ipshared/cb53/sync_bits.v
+79
View File
@@ -0,0 +1,79 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
/*
* Helper module for synchronizing bit signals from one clock domain to another.
* It uses the standard approach of 2 FF in series.
* Note, that while the module allows to synchronize multiple bits at once it is
* only able to synchronize multi-bit signals where at max one bit changes per
* clock cycle (e.g. a gray counter).
*/
`timescale 1ns/100ps
module sync_bits #(
// Number of bits to synchronize
parameter NUM_OF_BITS = 1,
// Whether input and output clocks are asynchronous, if 0 the synchronizer will
// be bypassed and the output signal equals the input signal.
parameter ASYNC_CLK = 1)(
input [NUM_OF_BITS-1:0] in_bits,
input out_resetn,
input out_clk,
output [NUM_OF_BITS-1:0] out_bits);
generate if (ASYNC_CLK == 1) begin
reg [NUM_OF_BITS-1:0] cdc_sync_stage1 = 'h0;
reg [NUM_OF_BITS-1:0] cdc_sync_stage2 = 'h0;
always @(posedge out_clk)
begin
if (out_resetn == 1'b0) begin
cdc_sync_stage1 <= 'b0;
cdc_sync_stage2 <= 'b0;
end else begin
cdc_sync_stage1 <= in_bits;
cdc_sync_stage2 <= cdc_sync_stage1;
end
end
assign out_bits = cdc_sync_stage2;
end else begin
assign out_bits = in_bits;
end endgenerate
endmodule
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ipshared/cb53/sync_data.v
+97
View File
@@ -0,0 +1,97 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module sync_data #(
parameter NUM_OF_BITS = 1,
parameter ASYNC_CLK = 1
) (
input in_clk,
input [NUM_OF_BITS-1:0] in_data,
input out_clk,
output reg [NUM_OF_BITS-1:0] out_data
);
generate
if (ASYNC_CLK == 1) begin
wire out_toggle;
wire in_toggle;
reg out_toggle_d1 = 1'b0;
reg in_toggle_d1 = 1'b0;
reg [NUM_OF_BITS-1:0] cdc_hold;
sync_bits i_sync_out (
.in_bits(in_toggle_d1),
.out_clk(out_clk),
.out_resetn(1'b1),
.out_bits(out_toggle)
);
sync_bits i_sync_in (
.in_bits(out_toggle_d1),
.out_clk(in_clk),
.out_resetn(1'b1),
.out_bits(in_toggle)
);
wire in_load = in_toggle == in_toggle_d1;
wire out_load = out_toggle ^ out_toggle_d1;
always @(posedge in_clk) begin
if (in_load == 1'b1) begin
cdc_hold <= in_data;
in_toggle_d1 <= ~in_toggle_d1;
end
end
always @(posedge out_clk) begin
if (out_load == 1'b1) begin
out_data <= cdc_hold;
end
out_toggle_d1 <= out_toggle;
end
end else begin
always @(*) begin
out_data <= in_data;
end
end
endgenerate
endmodule
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ipshared/cb53/sync_event.v
+120
View File
@@ -0,0 +1,120 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module sync_event #(
parameter NUM_OF_EVENTS = 1,
parameter ASYNC_CLK = 1
) (
input in_clk,
input [NUM_OF_EVENTS-1:0] in_event,
input out_clk,
output reg [NUM_OF_EVENTS-1:0] out_event
);
generate
if (ASYNC_CLK == 1) begin
wire out_toggle;
wire in_toggle;
reg out_toggle_d1 = 1'b0;
reg in_toggle_d1 = 1'b0;
sync_bits i_sync_out (
.in_bits(in_toggle_d1),
.out_clk(out_clk),
.out_resetn(1'b1),
.out_bits(out_toggle)
);
sync_bits i_sync_in (
.in_bits(out_toggle_d1),
.out_clk(in_clk),
.out_resetn(1'b1),
.out_bits(in_toggle)
);
wire in_ready = in_toggle == in_toggle_d1;
wire load_out = out_toggle ^ out_toggle_d1;
reg [NUM_OF_EVENTS-1:0] in_event_sticky = 'h00;
wire [NUM_OF_EVENTS-1:0] pending_events = in_event_sticky | in_event;
wire [NUM_OF_EVENTS-1:0] out_event_s;
always @(posedge in_clk) begin
if (in_ready == 1'b1) begin
in_event_sticky <= {NUM_OF_EVENTS{1'b0}};
if (|pending_events == 1'b1) begin
in_toggle_d1 <= ~in_toggle_d1;
end
end else begin
in_event_sticky <= pending_events;
end
end
if (NUM_OF_EVENTS > 1) begin
reg [NUM_OF_EVENTS-1:0] cdc_hold = 'h00;
always @(posedge in_clk) begin
if (in_ready == 1'b1) begin
cdc_hold <= pending_events;
end
end
assign out_event_s = cdc_hold;
end else begin
// When there is only one event, we know that it is set.
assign out_event_s = 1'b1;
end
always @(posedge out_clk) begin
if (load_out == 1'b1) begin
out_event <= out_event_s;
end else begin
out_event <= {NUM_OF_EVENTS{1'b0}};
end
out_toggle_d1 <= out_toggle;
end
end else begin
always @(*) begin
out_event <= in_event;
end
end
endgenerate
endmodule
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ipshared/cb53/sync_gray.v
+115
View File
@@ -0,0 +1,115 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
/*
* Helper module for synchronizing a counter from one clock domain to another
* using gray code. To work correctly the counter must not change its value by
* more than one in one clock cycle in the source domain. I.e. the value may
* change by either -1, 0 or +1.
*/
`timescale 1ns/100ps
module sync_gray #(
// Bit-width of the counter
parameter DATA_WIDTH = 1,
// Whether the input and output clock are asynchronous, if set to 0 the
// synchronizer will be bypassed and out_count will be in_count.
parameter ASYNC_CLK = 1)(
input in_clk,
input in_resetn,
input [DATA_WIDTH-1:0] in_count,
input out_resetn,
input out_clk,
output [DATA_WIDTH-1:0] out_count);
generate if (ASYNC_CLK == 1) begin
reg [DATA_WIDTH-1:0] cdc_sync_stage0 = 'h0;
reg [DATA_WIDTH-1:0] cdc_sync_stage1 = 'h0;
reg [DATA_WIDTH-1:0] cdc_sync_stage2 = 'h0;
reg [DATA_WIDTH-1:0] out_count_m = 'h0;
function [DATA_WIDTH-1:0] g2b;
input [DATA_WIDTH-1:0] g;
reg [DATA_WIDTH-1:0] b;
integer i;
begin
b[DATA_WIDTH-1] = g[DATA_WIDTH-1];
for (i = DATA_WIDTH - 2; i >= 0; i = i - 1)
b[i] = b[i + 1] ^ g[i];
g2b = b;
end
endfunction
function [DATA_WIDTH-1:0] b2g;
input [DATA_WIDTH-1:0] b;
reg [DATA_WIDTH-1:0] g;
integer i;
begin
g[DATA_WIDTH-1] = b[DATA_WIDTH-1];
for (i = DATA_WIDTH - 2; i >= 0; i = i -1)
g[i] = b[i + 1] ^ b[i];
b2g = g;
end
endfunction
always @(posedge in_clk) begin
if (in_resetn == 1'b0) begin
cdc_sync_stage0 <= 'h00;
end else begin
cdc_sync_stage0 <= b2g(in_count);
end
end
always @(posedge out_clk) begin
if (out_resetn == 1'b0) begin
cdc_sync_stage1 <= 'h00;
cdc_sync_stage2 <= 'h00;
out_count_m <= 'h00;
end else begin
cdc_sync_stage1 <= cdc_sync_stage0;
cdc_sync_stage2 <= cdc_sync_stage1;
out_count_m <= g2b(cdc_sync_stage2);
end
end
assign out_count = out_count_m;
end else begin
assign out_count = in_count;
end endgenerate
endmodule
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ipshared/cf62/address_gray_pipelined.v
+152
View File
@@ -0,0 +1,152 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module fifo_address_gray_pipelined #(
parameter ADDRESS_WIDTH = 4
) (
input m_axis_aclk,
input m_axis_aresetn,
input m_axis_ready,
output reg m_axis_valid,
output [ADDRESS_WIDTH-1:0] m_axis_raddr,
output reg [ADDRESS_WIDTH:0] m_axis_level,
input s_axis_aclk,
input s_axis_aresetn,
output reg s_axis_ready,
input s_axis_valid,
output reg s_axis_empty,
output [ADDRESS_WIDTH-1:0] s_axis_waddr,
output reg [ADDRESS_WIDTH:0] s_axis_room
);
localparam MAX_ROOM = {1'b1,{ADDRESS_WIDTH{1'b0}}};
reg [ADDRESS_WIDTH:0] _s_axis_waddr = 'h00;
reg [ADDRESS_WIDTH:0] _s_axis_waddr_next;
wire [ADDRESS_WIDTH:0] _s_axis_raddr;
reg [ADDRESS_WIDTH:0] _m_axis_raddr = 'h00;
reg [ADDRESS_WIDTH:0] _m_axis_raddr_next;
wire [ADDRESS_WIDTH:0] _m_axis_waddr;
assign s_axis_waddr = _s_axis_waddr[ADDRESS_WIDTH-1:0];
assign m_axis_raddr = _m_axis_raddr[ADDRESS_WIDTH-1:0];
always @(*)
begin
if (s_axis_ready && s_axis_valid)
_s_axis_waddr_next <= _s_axis_waddr + 1'b1;
else
_s_axis_waddr_next <= _s_axis_waddr;
end
always @(posedge s_axis_aclk)
begin
if (s_axis_aresetn == 1'b0) begin
_s_axis_waddr <= 'h00;
end else begin
_s_axis_waddr <= _s_axis_waddr_next;
end
end
always @(*)
begin
if (m_axis_ready && m_axis_valid)
_m_axis_raddr_next <= _m_axis_raddr + 1'b1;
else
_m_axis_raddr_next <= _m_axis_raddr;
end
always @(posedge m_axis_aclk)
begin
if (m_axis_aresetn == 1'b0) begin
_m_axis_raddr <= 'h00;
end else begin
_m_axis_raddr <= _m_axis_raddr_next;
end
end
sync_gray #(
.DATA_WIDTH(ADDRESS_WIDTH + 1)
) i_waddr_sync (
.in_clk(s_axis_aclk),
.in_resetn(s_axis_aresetn),
.out_clk(m_axis_aclk),
.out_resetn(m_axis_aresetn),
.in_count(_s_axis_waddr),
.out_count(_m_axis_waddr)
);
sync_gray #(
.DATA_WIDTH(ADDRESS_WIDTH + 1)
) i_raddr_sync (
.in_clk(m_axis_aclk),
.in_resetn(m_axis_aresetn),
.out_clk(s_axis_aclk),
.out_resetn(s_axis_aresetn),
.in_count(_m_axis_raddr),
.out_count(_s_axis_raddr)
);
always @(posedge s_axis_aclk)
begin
if (s_axis_aresetn == 1'b0) begin
s_axis_ready <= 1'b1;
s_axis_empty <= 1'b1;
s_axis_room <= MAX_ROOM;
end else begin
s_axis_ready <= (_s_axis_raddr[ADDRESS_WIDTH] == _s_axis_waddr_next[ADDRESS_WIDTH] ||
_s_axis_raddr[ADDRESS_WIDTH-1:0] != _s_axis_waddr_next[ADDRESS_WIDTH-1:0]);
s_axis_empty <= _s_axis_raddr == _s_axis_waddr_next;
s_axis_room <= _s_axis_raddr - _s_axis_waddr_next + MAX_ROOM;
end
end
always @(posedge m_axis_aclk)
begin
if (m_axis_aresetn == 1'b0) begin
m_axis_valid <= 1'b0;
m_axis_level <= 'h00;
end else begin
m_axis_valid <= _m_axis_waddr != _m_axis_raddr_next;
m_axis_level <= _m_axis_waddr - _m_axis_raddr_next;
end
end
endmodule
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ipshared/cf62/address_sync.v
+109
View File
@@ -0,0 +1,109 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module fifo_address_sync #(
parameter ADDRESS_WIDTH = 4
) (
input clk,
input resetn,
input m_axis_ready,
output reg m_axis_valid,
output reg [ADDRESS_WIDTH-1:0] m_axis_raddr,
output [ADDRESS_WIDTH:0] m_axis_level,
output reg s_axis_ready,
input s_axis_valid,
output reg s_axis_empty,
output reg [ADDRESS_WIDTH-1:0] s_axis_waddr,
output [ADDRESS_WIDTH:0] s_axis_room
);
localparam MAX_ROOM = {1'b1,{ADDRESS_WIDTH{1'b0}}};
reg [ADDRESS_WIDTH:0] room = MAX_ROOM;
reg [ADDRESS_WIDTH:0] level = 'h00;
reg [ADDRESS_WIDTH:0] level_next;
assign s_axis_room = room;
assign m_axis_level = level;
wire read = m_axis_ready & m_axis_valid;
wire write = s_axis_ready & s_axis_valid;
always @(posedge clk)
begin
if (resetn == 1'b0) begin
s_axis_waddr <= 'h00;
m_axis_raddr <= 'h00;
end else begin
if (write)
s_axis_waddr <= s_axis_waddr + 1'b1;
if (read)
m_axis_raddr <= m_axis_raddr + 1'b1;
end
end
always @(*)
begin
if (read & ~write)
level_next <= level - 1'b1;
else if (~read & write)
level_next <= level + 1'b1;
else
level_next <= level;
end
always @(posedge clk)
begin
if (resetn == 1'b0) begin
m_axis_valid <= 1'b0;
s_axis_ready <= 1'b0;
level <= 'h00;
room <= MAX_ROOM;
s_axis_empty <= 'h00;
end else begin
level <= level_next;
room <= MAX_ROOM - level_next;
m_axis_valid <= level_next != 0;
s_axis_ready <= level_next != MAX_ROOM;
s_axis_empty <= level_next == 0;
end
end
endmodule
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ipshared/cf62/util_axis_fifo.v
+248
View File
@@ -0,0 +1,248 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module util_axis_fifo #(
parameter DATA_WIDTH = 64,
parameter ASYNC_CLK = 1,
parameter ADDRESS_WIDTH = 4,
parameter S_AXIS_REGISTERED = 1
) (
input m_axis_aclk,
input m_axis_aresetn,
input m_axis_ready,
output m_axis_valid,
output [DATA_WIDTH-1:0] m_axis_data,
output [ADDRESS_WIDTH:0] m_axis_level,
input s_axis_aclk,
input s_axis_aresetn,
output s_axis_ready,
input s_axis_valid,
input [DATA_WIDTH-1:0] s_axis_data,
output s_axis_empty,
output [ADDRESS_WIDTH:0] s_axis_room
);
generate if (ADDRESS_WIDTH == 0) begin
reg [DATA_WIDTH-1:0] cdc_sync_fifo_ram;
reg s_axis_waddr = 1'b0;
reg m_axis_raddr = 1'b0;
wire m_axis_waddr;
wire s_axis_raddr;
sync_bits #(
.NUM_OF_BITS(1),
.ASYNC_CLK(ASYNC_CLK)
) i_waddr_sync (
.out_clk(m_axis_aclk),
.out_resetn(m_axis_aresetn),
.in_bits(s_axis_waddr),
.out_bits(m_axis_waddr)
);
sync_bits #(
.NUM_OF_BITS(1),
.ASYNC_CLK(ASYNC_CLK)
) i_raddr_sync (
.out_clk(s_axis_aclk),
.out_resetn(s_axis_aresetn),
.in_bits(m_axis_raddr),
.out_bits(s_axis_raddr)
);
assign m_axis_valid = m_axis_raddr != m_axis_waddr;
assign m_axis_level = m_axis_valid;
assign s_axis_ready = s_axis_raddr == s_axis_waddr;
assign s_axis_empty = s_axis_ready;
assign s_axis_room = s_axis_ready;
always @(posedge s_axis_aclk) begin
if (s_axis_ready == 1'b1 && s_axis_valid == 1'b1)
cdc_sync_fifo_ram <= s_axis_data;
end
always @(posedge s_axis_aclk) begin
if (s_axis_aresetn == 1'b0) begin
s_axis_waddr <= 1'b0;
end else begin
if (s_axis_ready & s_axis_valid) begin
s_axis_waddr <= s_axis_waddr + 1'b1;
end
end
end
always @(posedge m_axis_aclk) begin
if (m_axis_aresetn == 1'b0) begin
m_axis_raddr <= 1'b0;
end else begin
if (m_axis_valid & m_axis_ready)
m_axis_raddr <= m_axis_raddr + 1'b1;
end
end
assign m_axis_data = cdc_sync_fifo_ram;
end else begin
reg [DATA_WIDTH-1:0] ram[0:2**ADDRESS_WIDTH-1];
wire [ADDRESS_WIDTH-1:0] s_axis_waddr;
wire [ADDRESS_WIDTH-1:0] m_axis_raddr;
wire _m_axis_ready;
wire _m_axis_valid;
wire [ADDRESS_WIDTH:0] _m_axis_level;
wire s_mem_write;
wire m_mem_read;
reg valid;
always @(posedge m_axis_aclk) begin
if (m_axis_aresetn == 1'b0) begin
valid <= 1'b0;
end else begin
if (_m_axis_valid)
valid <= 1'b1;
else if (m_axis_ready)
valid <= 1'b0;
end
end
assign s_mem_write = s_axis_ready & s_axis_valid;
assign m_mem_read = (~valid || m_axis_ready) && _m_axis_valid;
if (ASYNC_CLK == 1) begin
// The assumption is that in this mode the S_AXIS_REGISTERED is 1
fifo_address_gray_pipelined #(
.ADDRESS_WIDTH(ADDRESS_WIDTH)
) i_address_gray (
.m_axis_aclk(m_axis_aclk),
.m_axis_aresetn(m_axis_aresetn),
.m_axis_ready(_m_axis_ready),
.m_axis_valid(_m_axis_valid),
.m_axis_raddr(m_axis_raddr),
.m_axis_level(_m_axis_level),
.s_axis_aclk(s_axis_aclk),
.s_axis_aresetn(s_axis_aresetn),
.s_axis_ready(s_axis_ready),
.s_axis_valid(s_axis_valid),
.s_axis_empty(s_axis_empty),
.s_axis_waddr(s_axis_waddr),
.s_axis_room(s_axis_room)
);
// When the clocks are asynchronous instantiate a block RAM
// regardless of the requested size to make sure we threat the
// clock crossing correctly
ad_mem #(
.DATA_WIDTH (DATA_WIDTH),
.ADDRESS_WIDTH (ADDRESS_WIDTH))
i_mem (
.clka(s_axis_aclk),
.wea(s_mem_write),
.addra(s_axis_waddr),
.dina(s_axis_data),
.clkb(m_axis_aclk),
.reb(m_mem_read),
.addrb(m_axis_raddr),
.doutb(m_axis_data)
);
assign _m_axis_ready = ~valid || m_axis_ready;
assign m_axis_valid = valid;
// the util_axis_fifo is functioning in 'first write fall through' mode,
// which means that we need to assure that the value of the level reflects
// the actual FIFO level plus the available data, which sits on the bus
assign m_axis_level = (m_axis_valid) ? _m_axis_level + 1'b1 : _m_axis_level;
end else begin
fifo_address_sync #(
.ADDRESS_WIDTH(ADDRESS_WIDTH)
) i_address_sync (
.clk(m_axis_aclk),
.resetn(m_axis_aresetn),
.m_axis_ready(_m_axis_ready),
.m_axis_valid(_m_axis_valid),
.m_axis_raddr(m_axis_raddr),
.m_axis_level(m_axis_level),
.s_axis_ready(s_axis_ready),
.s_axis_valid(s_axis_valid),
.s_axis_empty(s_axis_empty),
.s_axis_waddr(s_axis_waddr),
.s_axis_room(s_axis_room)
);
// When the clocks are synchronous use behavioral modeling for the SDP RAM
// Let the synthesizer decide what to infer (distributed or block RAM)
always @(posedge s_axis_aclk) begin
if (s_mem_write)
ram[s_axis_waddr] <= s_axis_data;
end
if (S_AXIS_REGISTERED == 1) begin
reg [DATA_WIDTH-1:0] data;
always @(posedge m_axis_aclk) begin
if (m_mem_read)
data <= ram[m_axis_raddr];
end
assign _m_axis_ready = ~valid || m_axis_ready;
assign m_axis_data = data;
assign m_axis_valid = valid;
end else begin
assign _m_axis_ready = m_axis_ready;
assign m_axis_valid = _m_axis_valid;
assign m_axis_data = ram[m_axis_raddr];
end
end
end endgenerate
endmodule
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ipshared/common/ad_mem.v
+71
View File
@@ -0,0 +1,71 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_mem #(
parameter DATA_WIDTH = 16,
parameter ADDRESS_WIDTH = 5) (
input clka,
input wea,
input [(ADDRESS_WIDTH-1):0] addra,
input [(DATA_WIDTH-1):0] dina,
input clkb,
input reb,
input [(ADDRESS_WIDTH-1):0] addrb,
output reg [(DATA_WIDTH-1):0] doutb);
(* ram_style = "block" *)
reg [(DATA_WIDTH-1):0] m_ram[0:((2**ADDRESS_WIDTH)-1)];
always @(posedge clka) begin
if (wea == 1'b1) begin
m_ram[addra] <= dina;
end
end
always @(posedge clkb) begin
if (reb == 1'b1) begin
doutb <= m_ram[addrb];
end
end
endmodule
// ***************************************************************************
// ***************************************************************************
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/system_bd.bd
+2038
View File
File diff suppressed because it is too large Load Diff
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/system_bd.bda
+249
View File
@@ -0,0 +1,249 @@
{
"graphjs": {
"version": "1.0",
"keys": [
{
"abrv": "VH",
"name": "vert_hid",
"type": "int",
"for": "node"
},
{
"abrv": "VM",
"name": "vert_name",
"type": "string",
"for": "node"
},
{
"abrv": "VT",
"name": "vert_type",
"type": "string",
"for": "node"
},
{
"abrv": "BA",
"name": "base_addr",
"type": "string",
"for": "node"
},
{
"abrv": "HA",
"name": "high_addr",
"type": "string",
"for": "node"
},
{
"abrv": "BP",
"name": "base_param",
"type": "string",
"for": "node"
},
{
"abrv": "HP",
"name": "high_param",
"type": "string",
"for": "node"
},
{
"abrv": "MA",
"name": "master_addrspace",
"type": "string",
"for": "node"
},
{
"abrv": "MX",
"name": "master_instance",
"type": "string",
"for": "node"
},
{
"abrv": "MI",
"name": "master_interface",
"type": "string",
"for": "node"
},
{
"abrv": "MS",
"name": "master_segment",
"type": "string",
"for": "node"
},
{
"abrv": "MV",
"name": "master_vlnv",
"type": "string",
"for": "node"
},
{
"abrv": "SX",
"name": "slave_instance",
"type": "string",
"for": "node"
},
{
"abrv": "SI",
"name": "slave_interface",
"type": "string",
"for": "node"
},
{
"abrv": "MM",
"name": "slave_memmap",
"type": "string",
"for": "node"
},
{
"abrv": "SS",
"name": "slave_segment",
"type": "string",
"for": "node"
},
{
"abrv": "SV",
"name": "slave_vlnv",
"type": "string",
"for": "node"
},
{
"abrv": "TM",
"name": "memory_type",
"type": "string",
"for": "node"
},
{
"abrv": "TU",
"name": "usage_type",
"type": "string",
"for": "node"
},
{
"abrv": "LT",
"name": "lock_type",
"type": "string",
"for": "node"
},
{
"abrv": "BT",
"name": "boot_type",
"type": "string",
"for": "node"
},
{
"abrv": "EH",
"name": "edge_hid",
"type": "int",
"for": "edge"
}
],
"vertice_type_order": [
{
"abrv": "BC",
"desc": "Block Container"
},
{
"abrv": "PR",
"desc": "Parital Reference"
},
{
"abrv": "VR",
"desc": "Variant"
},
{
"abrv": "PM",
"desc": "Variant Permutations"
},
{
"abrv": "CX",
"desc": "Boundary Connection"
},
{
"abrv": "AC",
"desc": "Assignment Coordinate"
},
{
"abrv": "ACE",
"desc": "Excluded Assign Coordinate"
},
{
"abrv": "APX",
"desc": "Boundary Aperture"
},
{
"abrv": "CIP",
"desc": "High level Processing System"
}
],
"vertices": {
"V0": {
"VM": "system_bd",
"VT": "BC"
},
"V1": {
"VH": "2",
"VM": "system_bd",
"VT": "VR"
},
"V2": {
"VH": "2",
"VT": "PM",
"TU": "active"
},
"V3": {
"VT": "AC",
"BA": "0x43C00000",
"HA": "0x43C0FFFF",
"BP": "C_BASEADDR",
"HP": "C_HIGHADDR",
"MA": "Data",
"MX": "/processing_system7",
"MI": "M_AXI_GP0",
"MS": "SEG_axi_spi_engine_axi_lite",
"MV": "xilinx.com:ip:processing_system7:5.5",
"SX": "/axi_spi_engine/axi_spi_engine",
"SI": "s_axi",
"SS": "axi_lite",
"SV": "analog.com:user:axi_spi_engine:1.0",
"TM": "both",
"TU": "register"
},
"V4": {
"VT": "AC",
"BA": "0x43C10000",
"HA": "0x43C1FFFF",
"BP": "C_BASEADDR",
"HP": "C_HIGHADDR",
"MA": "Data",
"MX": "/processing_system7",
"MI": "M_AXI_GP0",
"MS": "SEG_system_management_Reg",
"MV": "xilinx.com:ip:processing_system7:5.5",
"SX": "/system_management",
"SI": "s_axi_lite",
"SS": "Reg",
"SV": "xilinx.com:ip:xadc_wiz:3.3",
"TM": "both",
"TU": "register"
}
},
"edges": [
{
"src": "V0",
"trg": "V1"
},
{
"src": "V1",
"trg": "V2"
},
{
"src": "V3",
"trg": "V2",
"EH": "2"
},
{
"src": "V4",
"trg": "V2",
"EH": "2"
}
]
}
}
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ui/bd_c6d0cb12.ui
+48
View File
@@ -0,0 +1,48 @@
{
"ActiveEmotionalView":"Default View",
"Default View_ScaleFactor":"0.798638",
"Default View_TopLeft":"-533,0",
"ExpandedHierarchyInLayout":"",
"guistr":"# # String gsaved with Nlview 7.7.1 2023-07-26 3bc4126617 VDI=43 GEI=38 GUI=JA:21.0 TLS
# -string -flagsOSRD
preplace port ddr -pg 1 -lvl 3 -x 930 -y 150 -defaultsOSRD
preplace port fixed_io -pg 1 -lvl 3 -x 930 -y 170 -defaultsOSRD
preplace port Vp_Vn -pg 1 -lvl 0 -x 0 -y 590 -defaultsOSRD
preplace port port-id_spi_active -pg 1 -lvl 3 -x 930 -y 70 -defaultsOSRD
preplace port port-id_ps_clk_200M -pg 1 -lvl 3 -x 930 -y 190 -defaultsOSRD
preplace port spi -pg 1 -lvl 3 -x 930 -y 930 -defaultsOSRD
preplace portBus gpio_i -pg 1 -lvl 3 -x 930 -y 90 -defaultsOSRD -right
preplace portBus gpio_o -pg 1 -lvl 3 -x 930 -y 110 -defaultsOSRD
preplace portBus gpio_t -pg 1 -lvl 3 -x 930 -y 130 -defaultsOSRD
preplace inst processing_system7 -pg 1 -lvl 1 -x 260 -y 200 -defaultsOSRD
preplace inst axi_spi_engine -pg 1 -lvl 1 -x 260 -y 950 -defaultsOSRD
preplace inst rst_ps7_50M -pg 1 -lvl 2 -x 710 -y 270 -defaultsOSRD
preplace inst axi_interconnect_0 -pg 1 -lvl 1 -x 260 -y 740 -defaultsOSRD
preplace inst xlconcat_irq -pg 1 -lvl 2 -x 710 -y 420 -defaultsOSRD -orient R180
preplace inst system_management -pg 1 -lvl 2 -x 710 -y 600 -defaultsOSRD
preplace netloc processing_system7_FCLK_CLK0 1 0 2 20 10 510
preplace netloc processing_system7_FCLK_RESET0_N 1 1 1 500 250n
preplace netloc rst_ps7_50M_peripheral_aresetn 1 0 3 40 580 530J 490 910
preplace netloc xlconcat_irq_dout 1 0 2 50 420 N
preplace netloc processing_system7_FCLK_CLK1 1 1 2 480J 140 910J
preplace netloc GPIO_I_0_1 1 1 2 N 90 N
preplace netloc processing_system7_GPIO_O 1 1 2 NJ 110 NJ
preplace netloc processing_system7_GPIO_T 1 1 2 NJ 130 NJ
preplace netloc system_management_ip2intc_irpt 1 2 1 900 410n
preplace netloc axi_spi_engine_active 1 1 2 490J 70 N
preplace netloc axi_spi_engine_irq 1 1 2 N 970 890
preplace netloc processing_system7_DDR 1 1 2 NJ 150 N
preplace netloc processing_system7_M_AXI_GP0 1 0 2 30 390 470
preplace netloc axi_interconnect_0_M00_AXI 1 0 2 50 600 470
preplace netloc processing_system7_FIXED_IO 1 1 2 NJ 170 N
preplace netloc axi_interconnect_0_M01_AXI 1 1 1 520 570n
preplace netloc Vp_Vn_0_1 1 0 2 NJ 590 NJ
preplace netloc axi_spi_engine_spi 1 1 2 NJ 930 NJ
levelinfo -pg 1 0 260 710 930
pagesize -pg 1 -db -bbox -sgen -100 0 1070 1030
"
}
{
"da_axi4_cnt":"3",
"da_ps7_cnt":"1"
}
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ui/bd_e4e34314.ui
+24
View File
@@ -0,0 +1,24 @@
{
"ActiveEmotionalView":"Default View",
"Default View_ScaleFactor":"1.0",
"Default View_TopLeft":"-438,-327",
"ExpandedHierarchyInLayout":"",
"guistr":"# # String gsaved with Nlview 7.7.1 2023-07-26 3bc4126617 VDI=43 GEI=38 GUI=JA:21.0 TLS
# -string -flagsOSRD
preplace port s_axi -pg 1 -lvl 0 -x -10 -y 60 -defaultsOSRD
preplace port spi_0 -pg 1 -lvl 3 -x 1040 -y 90 -defaultsOSRD
preplace port port-id_s_axi_aclk -pg 1 -lvl 0 -x -10 -y 80 -defaultsOSRD
preplace port port-id_s_axi_aresetn -pg 1 -lvl 0 -x -10 -y 100 -defaultsOSRD
preplace port port-id_spi_clk -pg 1 -lvl 0 -x -10 -y 120 -defaultsOSRD
preplace inst axi_spi_engine -pg 1 -lvl 1 -x 640 -y 90 -defaultsOSRD
preplace inst spi_engine_execution_0 -pg 1 -lvl 2 -x 890 -y 100 -defaultsOSRD
preplace netloc s_axi_aclk_0_1 1 0 1 N 80
preplace netloc s_axi_aresetn_0_1 1 0 1 N 100
preplace netloc spi_clk_0_1 1 0 1 N 120
preplace netloc Conn1 1 0 1 N 60
preplace netloc Conn2 1 2 1 N 90
levelinfo -pg 1 -10 640 890 1040
pagesize -pg 1 -db -bbox -sgen -160 -480 1140 330
"
}
0
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/xilinx/common/ad_rst_constr.xdc
+9
View File
@@ -0,0 +1,9 @@
# the "-quiet" option is added for the axi_spi_engine ip where the ad_rst.v
# module is not always inferred and this causes critical warnings
set_property -quiet ASYNC_REG TRUE [get_cells -hierarchical -filter {name =~ *rst_async_d*_reg}]
set_property -quiet ASYNC_REG TRUE [get_cells -hierarchical -filter {name =~ *rst_sync_reg}]
set_false_path -quiet -to [get_pins -hierarchical *rst_sync_reg/PRE]
set_false_path -quiet -to [get_pins -hierarchical *rst_async_d1_reg/PRE]
set_false_path -quiet -to [get_pins -hierarchical *rst_async_d2_reg/PRE]
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/ip/cmpy_18x8/cmpy_18x8.xci
+213
View File
@@ -0,0 +1,213 @@
{
"schema": "xilinx.com:schema:json_instance:1.0",
"ip_inst": {
"xci_name": "cmpy_18x8",
"component_reference": "xilinx.com:ip:cmpy:6.0",
"ip_revision": "24",
"gen_directory": "../../../../zc706_cx9261a_demo.gen/sources_1/ip/cmpy_18x8",
"parameters": {
"component_parameters": {
"Component_Name": [ { "value": "cmpy_18x8", "resolve_type": "user", "usage": "all" } ],
"APortWidth": [ { "value": "18", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HasATLAST": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"HasATUSER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"ATUSERWidth": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"BPortWidth": [ { "value": "8", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HasBTLAST": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"HasBTUSER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"BTUSERWidth": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"MultType": [ { "value": "Use_LUTs", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"OptimizeGoal": [ { "value": "Resources", "resolve_type": "user", "usage": "all" } ],
"FlowControl": [ { "value": "NonBlocking", "resolve_type": "user", "usage": "all" } ],
"RoundMode": [ { "value": "Truncate", "resolve_type": "user", "usage": "all" } ],
"OutputWidth": [ { "value": "27", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HasCTRLTLAST": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"HasCTRLTUSER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CTRLTUSERWidth": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"OutTLASTBehv": [ { "value": "Null", "resolve_type": "user", "usage": "all" } ],
"LatencyConfig": [ { "value": "Automatic", "resolve_type": "user", "usage": "all" } ],
"MinimumLatency": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"ACLKEN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"ARESETN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ]
},
"model_parameters": {
"C_VERBOSITY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_XDEVICEFAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ],
"C_XDEVICE": [ { "value": "xc7z045", "resolve_type": "generated", "usage": "all" } ],
"C_A_WIDTH": [ { "value": "18", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_B_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_OUT_WIDTH": [ { "value": "27", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_LATENCY": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_MULT_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_OPTIMIZE_GOAL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"HAS_NEGATE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"SINGLE_OUTPUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"ROUND": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"USE_DSP_CASCADES": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_THROTTLE_SCHEME": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_ACLKEN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_ARESETN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_S_AXIS_A_TUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_S_AXIS_A_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_S_AXIS_B_TUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_S_AXIS_B_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_S_AXIS_CTRL_TUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_S_AXIS_CTRL_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_TLAST_RESOLUTION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_S_AXIS_A_TDATA_WIDTH": [ { "value": "48", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_S_AXIS_A_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_S_AXIS_B_TDATA_WIDTH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_S_AXIS_B_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_S_AXIS_CTRL_TDATA_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_S_AXIS_CTRL_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_M_AXIS_DOUT_TDATA_WIDTH": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_M_AXIS_DOUT_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ]
},
"project_parameters": {
"ARCHITECTURE": [ { "value": "zynq" } ],
"BASE_BOARD_PART": [ { "value": "xilinx.com:zc706:part0:1.4" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xc7z045" } ],
"NEXTGEN_VERSAL": [ { "value": "0" } ],
"PACKAGE": [ { "value": "ffg900" } ],
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "" } ]
},
"runtime_parameters": {
"IPCONTEXT": [ { "value": "IP_Flow" } ],
"IPREVISION": [ { "value": "24" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "../../../../zc706_cx9261a_demo.gen/sources_1/ip/cmpy_18x8" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "." } ],
"SWVERSION": [ { "value": "2024.1" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
}
},
"boundary": {
"ports": {
"aclk": [ { "direction": "in", "driver_value": "0x0" } ],
"s_axis_a_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
"s_axis_a_tdata": [ { "direction": "in", "size_left": "47", "size_right": "0", "driver_value": "0" } ],
"s_axis_b_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
"s_axis_b_tdata": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
"m_axis_dout_tvalid": [ { "direction": "out", "driver_value": "0x0" } ],
"m_axis_dout_tdata": [ { "direction": "out", "size_left": "63", "size_right": "0", "driver_value": "0" } ]
},
"interfaces": {
"M_AXIS_DOUT": {
"vlnv": "xilinx.com:interface:axis:1.0",
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
"mode": "master",
"parameters": {
"TDATA_NUM_BYTES": [ { "value": "8", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"TDATA": [ { "physical_name": "m_axis_dout_tdata" } ],
"TVALID": [ { "physical_name": "m_axis_dout_tvalid" } ]
}
},
"aclk_intf": {
"vlnv": "xilinx.com:signal:clock:1.0",
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
"mode": "slave",
"parameters": {
"ASSOCIATED_BUSIF": [ { "value": "S_AXIS_CTRL:S_AXIS_B:S_AXIS_A:M_AXIS_DOUT", "value_src": "constant", "usage": "all" } ],
"ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "usage": "all" } ],
"ASSOCIATED_CLKEN": [ { "value": "aclken", "value_src": "constant", "usage": "all" } ],
"FREQ_HZ": [ { "value": "10000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"CLK": [ { "physical_name": "aclk" } ]
}
},
"aresetn_intf": {
"vlnv": "xilinx.com:signal:reset:1.0",
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
"mode": "slave",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
}
},
"aclken_intf": {
"vlnv": "xilinx.com:signal:clockenable:1.0",
"abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0",
"mode": "slave",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ]
}
},
"S_AXIS_A": {
"vlnv": "xilinx.com:interface:axis:1.0",
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
"mode": "slave",
"parameters": {
"TDATA_NUM_BYTES": [ { "value": "6", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"TDATA": [ { "physical_name": "s_axis_a_tdata" } ],
"TVALID": [ { "physical_name": "s_axis_a_tvalid" } ]
}
},
"S_AXIS_B": {
"vlnv": "xilinx.com:interface:axis:1.0",
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
"mode": "slave",
"parameters": {
"TDATA_NUM_BYTES": [ { "value": "2", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"TDATA": [ { "physical_name": "s_axis_b_tdata" } ],
"TVALID": [ { "physical_name": "s_axis_b_tvalid" } ]
}
}
}
}
}
}
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/ip/coe/hrc_64_12_025.coe
+771
View File
@@ -0,0 +1,771 @@
RADIX = 10;
COEFDATA =
-47,
-30,
-13,
4,
21,
38,
56,
73,
89,
106,
122,
138,
153,
168,
182,
196,
209,
221,
232,
243,
252,
261,
268,
275,
281,
285,
289,
291,
292,
292,
291,
288,
285,
280,
274,
267,
259,
249,
239,
228,
215,
202,
187,
172,
156,
139,
122,
104,
85,
66,
46,
26,
5,
-15,
-36,
-56,
-77,
-98,
-118,
-138,
-158,
-177,
-195,
-213,
-231,
-247,
-263,
-277,
-291,
-303,
-314,
-325,
-333,
-341,
-347,
-351,
-354,
-356,
-356,
-354,
-351,
-346,
-340,
-332,
-322,
-311,
-298,
-284,
-268,
-250,
-231,
-211,
-189,
-166,
-142,
-117,
-90,
-63,
-35,
-6,
24,
54,
85,
116,
147,
179,
210,
242,
273,
304,
334,
363,
392,
420,
447,
473,
497,
520,
542,
562,
580,
596,
611,
623,
633,
641,
647,
650,
650,
649,
644,
637,
627,
615,
600,
582,
562,
538,
513,
484,
453,
419,
383,
345,
304,
261,
216,
169,
119,
69,
16,
-38,
-93,
-150,
-207,
-265,
-324,
-383,
-443,
-502,
-562,
-621,
-679,
-736,
-793,
-848,
-902,
-954,
-1004,
-1052,
-1097,
-1140,
-1181,
-1218,
-1252,
-1283,
-1310,
-1333,
-1353,
-1369,
-1380,
-1387,
-1389,
-1387,
-1381,
-1369,
-1353,
-1332,
-1306,
-1274,
-1238,
-1197,
-1151,
-1100,
-1044,
-983,
-918,
-848,
-773,
-694,
-611,
-524,
-432,
-337,
-239,
-137,
-33,
74,
184,
296,
410,
525,
642,
759,
877,
995,
1113,
1230,
1346,
1461,
1575,
1686,
1794,
1900,
2002,
2101,
2195,
2285,
2371,
2451,
2525,
2593,
2655,
2711,
2759,
2800,
2833,
2859,
2876,
2885,
2886,
2877,
2860,
2833,
2798,
2752,
2698,
2633,
2559,
2476,
2382,
2280,
2168,
2046,
1915,
1775,
1627,
1469,
1304,
1130,
948,
759,
563,
360,
151,
-64,
-284,
-509,
-739,
-972,
-1208,
-1447,
-1687,
-1929,
-2172,
-2414,
-2656,
-2896,
-3133,
-3368,
-3600,
-3826,
-4048,
-4263,
-4472,
-4673,
-4866,
-5050,
-5224,
-5387,
-5539,
-5679,
-5807,
-5920,
-6020,
-6104,
-6173,
-6226,
-6262,
-6281,
-6282,
-6264,
-6228,
-6171,
-6096,
-5999,
-5882,
-5745,
-5585,
-5405,
-5203,
-4978,
-4732,
-4464,
-4174,
-3861,
-3527,
-3170,
-2792,
-2392,
-1971,
-1529,
-1066,
-582,
-79,
444,
985,
1545,
2123,
2717,
3328,
3955,
4597,
5253,
5921,
6603,
7295,
7998,
8711,
9432,
10160,
10895,
11635,
12379,
13126,
13875,
14624,
15374,
16121,
16866,
17607,
18342,
19071,
19793,
20505,
21208,
21900,
22579,
23245,
23896,
24532,
25151,
25752,
26334,
26896,
27438,
27957,
28455,
28928,
29377,
29801,
30200,
30571,
30915,
31232,
31520,
31779,
32009,
32209,
32379,
32518,
32627,
32704,
32751,
32767,
32751,
32704,
32627,
32518,
32379,
32209,
32009,
31779,
31520,
31232,
30915,
30571,
30200,
29801,
29377,
28928,
28455,
27957,
27438,
26896,
26334,
25752,
25151,
24532,
23896,
23245,
22579,
21900,
21208,
20505,
19793,
19071,
18342,
17607,
16866,
16121,
15374,
14624,
13875,
13126,
12379,
11635,
10895,
10160,
9432,
8711,
7998,
7295,
6603,
5921,
5253,
4597,
3955,
3328,
2717,
2123,
1545,
985,
444,
-79,
-582,
-1066,
-1529,
-1971,
-2392,
-2792,
-3170,
-3527,
-3861,
-4174,
-4464,
-4732,
-4978,
-5203,
-5405,
-5585,
-5745,
-5882,
-5999,
-6096,
-6171,
-6228,
-6264,
-6282,
-6281,
-6262,
-6226,
-6173,
-6104,
-6020,
-5920,
-5807,
-5679,
-5539,
-5387,
-5224,
-5050,
-4866,
-4673,
-4472,
-4263,
-4048,
-3826,
-3600,
-3368,
-3133,
-2896,
-2656,
-2414,
-2172,
-1929,
-1687,
-1447,
-1208,
-972,
-739,
-509,
-284,
-64,
151,
360,
563,
759,
948,
1130,
1304,
1469,
1627,
1775,
1915,
2046,
2168,
2280,
2382,
2476,
2559,
2633,
2698,
2752,
2798,
2833,
2860,
2877,
2886,
2885,
2876,
2859,
2833,
2800,
2759,
2711,
2655,
2593,
2525,
2451,
2371,
2285,
2195,
2101,
2002,
1900,
1794,
1686,
1575,
1461,
1346,
1230,
1113,
995,
877,
759,
642,
525,
410,
296,
184,
74,
-33,
-137,
-239,
-337,
-432,
-524,
-611,
-694,
-773,
-848,
-918,
-983,
-1044,
-1100,
-1151,
-1197,
-1238,
-1274,
-1306,
-1332,
-1353,
-1369,
-1381,
-1387,
-1389,
-1387,
-1380,
-1369,
-1353,
-1333,
-1310,
-1283,
-1252,
-1218,
-1181,
-1140,
-1097,
-1052,
-1004,
-954,
-902,
-848,
-793,
-736,
-679,
-621,
-562,
-502,
-443,
-383,
-324,
-265,
-207,
-150,
-93,
-38,
16,
69,
119,
169,
216,
261,
304,
345,
383,
419,
453,
484,
513,
538,
562,
582,
600,
615,
627,
637,
644,
649,
650,
650,
647,
641,
633,
623,
611,
596,
580,
562,
542,
520,
497,
473,
447,
420,
392,
363,
334,
304,
273,
242,
210,
179,
147,
116,
85,
54,
24,
-6,
-35,
-63,
-90,
-117,
-142,
-166,
-189,
-211,
-231,
-250,
-268,
-284,
-298,
-311,
-322,
-332,
-340,
-346,
-351,
-354,
-356,
-356,
-354,
-351,
-347,
-341,
-333,
-325,
-314,
-303,
-291,
-277,
-263,
-247,
-231,
-213,
-195,
-177,
-158,
-138,
-118,
-98,
-77,
-56,
-36,
-15,
5,
26,
46,
66,
85,
104,
122,
139,
156,
172,
187,
202,
215,
228,
239,
249,
259,
267,
274,
280,
285,
288,
291,
292,
292,
291,
289,
285,
281,
275,
268,
261,
252,
243,
232,
221,
209,
196,
182,
168,
153,
138,
122,
106,
89,
73,
56,
38,
21,
4,
-13,
-30,
-47;
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/ip/coe/sweep_freq.coe
+258
View File
@@ -0,0 +1,258 @@
MEMORY_INITIALIZATION_RADIX = 10;
MEMORY_INITIALIZATION_VECTOR =
-2147483647,
-2130640638,
-2113797629,
-2096954620,
-2080111611,
-2063268602,
-2046425593,
-2029582584,
-2012739575,
-1995896566,
-1979053557,
-1962210548,
-1945367539,
-1928524530,
-1911681521,
-1894838512,
-1877995503,
-1861152494,
-1844309485,
-1827466476,
-1810623467,
-1793780458,
-1776937449,
-1760094440,
-1743251431,
-1726408422,
-1709565413,
-1692722404,
-1675879395,
-1659036386,
-1642193377,
-1625350368,
-1608507359,
-1591664350,
-1574821341,
-1557978332,
-1541135323,
-1524292314,
-1507449305,
-1490606296,
-1473763287,
-1456920278,
-1440077269,
-1423234260,
-1406391251,
-1389548242,
-1372705233,
-1355862224,
-1339019215,
-1322176206,
-1305333197,
-1288490188,
-1271647179,
-1254804170,
-1237961161,
-1221118152,
-1204275143,
-1187432134,
-1170589125,
-1153746116,
-1136903107,
-1120060098,
-1103217089,
-1086374080,
-1069531071,
-1052688062,
-1035845053,
-1019002044,
-1002159035,
-985316026,
-968473017,
-951630008,
-934786999,
-917943990,
-901100981,
-884257972,
-867414963,
-850571954,
-833728945,
-816885936,
-800042927,
-783199918,
-766356909,
-749513900,
-732670891,
-715827882,
-698984873,
-682141864,
-665298855,
-648455846,
-631612837,
-614769828,
-597926819,
-581083810,
-564240801,
-547397792,
-530554783,
-513711774,
-496868765,
-480025756,
-463182747,
-446339738,
-429496729,
-412653720,
-395810711,
-378967702,
-362124693,
-345281684,
-328438675,
-311595666,
-294752657,
-277909648,
-261066639,
-244223630,
-227380621,
-210537612,
-193694603,
-176851594,
-160008585,
-143165576,
-126322567,
-109479558,
-92636549,
-75793540,
-58950531,
-42107522,
-25264513,
-8421504,
8421504,
25264513,
42107522,
58950531,
75793540,
92636549,
109479558,
126322567,
143165576,
160008585,
176851594,
193694603,
210537612,
227380621,
244223630,
261066639,
277909648,
294752657,
311595666,
328438675,
345281684,
362124693,
378967702,
395810711,
412653720,
429496729,
446339738,
463182747,
480025756,
496868765,
513711774,
530554783,
547397792,
564240801,
581083810,
597926819,
614769828,
631612837,
648455846,
665298855,
682141864,
698984873,
715827882,
732670891,
749513900,
766356909,
783199918,
800042927,
816885936,
833728945,
850571954,
867414963,
884257972,
901100981,
917943990,
934786999,
951630008,
968473017,
985316026,
1002159035,
1019002044,
1035845053,
1052688062,
1069531071,
1086374080,
1103217089,
1120060098,
1136903107,
1153746116,
1170589125,
1187432134,
1204275143,
1221118152,
1237961161,
1254804170,
1271647179,
1288490188,
1305333197,
1322176206,
1339019215,
1355862224,
1372705233,
1389548242,
1406391251,
1423234260,
1440077269,
1456920278,
1473763287,
1490606296,
1507449305,
1524292314,
1541135323,
1557978332,
1574821341,
1591664350,
1608507359,
1625350368,
1642193377,
1659036386,
1675879395,
1692722404,
1709565413,
1726408422,
1743251431,
1760094440,
1776937449,
1793780458,
1810623467,
1827466476,
1844309485,
1861152494,
1877995503,
1894838512,
1911681521,
1928524530,
1945367539,
1962210548,
1979053557,
1995896566,
2012739575,
2029582584,
2046425593,
2063268602,
2080111611,
2096954620,
2113797629,
2130640638,
2147483647;
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/ip/dds_32b_8b/dds_32b_8b.xci
+358
View File
@@ -0,0 +1,358 @@
{
"schema": "xilinx.com:schema:json_instance:1.0",
"ip_inst": {
"xci_name": "dds_32b_8b",
"component_reference": "xilinx.com:ip:dds_compiler:6.0",
"ip_revision": "25",
"gen_directory": "../../../../zc706_cx9261a_demo.gen/sources_1/ip/dds_32b_8b",
"parameters": {
"component_parameters": {
"Component_Name": [ { "value": "dds_32b_8b", "resolve_type": "user", "usage": "all" } ],
"PartsPresent": [ { "value": "Phase_Generator_and_SIN_COS_LUT", "resolve_type": "user", "usage": "all" } ],
"DDS_Clock_Rate": [ { "value": "48", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"Channels": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
"Mode_of_Operation": [ { "value": "Standard", "resolve_type": "user", "usage": "all" } ],
"Modulus": [ { "value": "9", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Output_Type": [ { "value": "Integer", "resolve_type": "user", "usage": "all" } ],
"Parameter_Entry": [ { "value": "Hardware_Parameters", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"Spurious_Free_Dynamic_Range": [ { "value": "45", "resolve_type": "user", "format": "float", "usage": "all" } ],
"Frequency_Resolution": [ { "value": "0.4", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"Noise_Shaping": [ { "value": "None", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"Phase_Width": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Output_Width": [ { "value": "8", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Phase_Increment": [ { "value": "Programmable", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"Resync": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Phase_offset": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
"Output_Selection": [ { "value": "Sine_and_Cosine", "resolve_type": "user", "usage": "all" } ],
"Negative_Sine": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Negative_Cosine": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Amplitude_Mode": [ { "value": "Full_Range", "resolve_type": "user", "usage": "all" } ],
"Memory_Type": [ { "value": "Auto", "resolve_type": "user", "usage": "all" } ],
"Optimization_Goal": [ { "value": "Auto", "resolve_type": "user", "usage": "all" } ],
"DSP48_Use": [ { "value": "Minimal", "resolve_type": "user", "usage": "all" } ],
"Has_Phase_Out": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"DATA_Has_TLAST": [ { "value": "Not_Required", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"Has_TREADY": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"S_PHASE_Has_TUSER": [ { "value": "Not_Required", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"S_PHASE_TUSER_Width": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M_DATA_Has_TUSER": [ { "value": "Not_Required", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"M_PHASE_Has_TUSER": [ { "value": "Not_Required", "resolve_type": "user", "usage": "all" } ],
"S_CONFIG_Sync_Mode": [ { "value": "On_Vector", "resolve_type": "user", "usage": "all" } ],
"OUTPUT_FORM": [ { "value": "Twos_Complement", "resolve_type": "user", "usage": "all" } ],
"Latency_Configuration": [ { "value": "Auto", "resolve_type": "user", "usage": "all" } ],
"Latency": [ { "value": "3", "resolve_type": "user", "usage": "all" } ],
"Has_ARESETn": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Has_ACLKEN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Output_Frequency1": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PINC1": [ { "value": "1101101001110100", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"Phase_Offset_Angles1": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"POFF1": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
"Output_Frequency2": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PINC2": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
"Phase_Offset_Angles2": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"POFF2": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
"Output_Frequency3": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PINC3": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
"Phase_Offset_Angles3": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"POFF3": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
"Output_Frequency4": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PINC4": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
"Phase_Offset_Angles4": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"POFF4": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
"Output_Frequency5": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PINC5": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
"Phase_Offset_Angles5": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"POFF5": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
"Output_Frequency6": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PINC6": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
"Phase_Offset_Angles6": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"POFF6": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
"Output_Frequency7": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PINC7": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
"Phase_Offset_Angles7": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"POFF7": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
"Output_Frequency8": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PINC8": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
"Phase_Offset_Angles8": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"POFF8": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
"Output_Frequency9": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PINC9": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
"Phase_Offset_Angles9": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"POFF9": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
"Output_Frequency10": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PINC10": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
"Phase_Offset_Angles10": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"POFF10": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
"Output_Frequency11": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PINC11": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
"Phase_Offset_Angles11": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"POFF11": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
"Output_Frequency12": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PINC12": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
"Phase_Offset_Angles12": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"POFF12": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
"Output_Frequency13": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PINC13": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
"Phase_Offset_Angles13": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"POFF13": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
"Output_Frequency14": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PINC14": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
"Phase_Offset_Angles14": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"POFF14": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
"Output_Frequency15": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PINC15": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
"Phase_Offset_Angles15": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"POFF15": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
"Output_Frequency16": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PINC16": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
"Phase_Offset_Angles16": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"POFF16": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
"POR_mode": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"GUI_Behaviour": [ { "value": "Coregen", "resolve_type": "user", "usage": "all" } ],
"explicit_period": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"period": [ { "value": "1", "resolve_type": "user", "format": "float", "usage": "all" } ]
},
"model_parameters": {
"C_XDEVICEFAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ],
"C_MODE_OF_OPERATION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_MODULUS": [ { "value": "9", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_ACCUMULATOR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_CHANNELS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_PHASE_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_PHASEGEN": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_SINCOS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_LATENCY": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_MEM_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_NEGATIVE_COSINE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_NEGATIVE_SINE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_NOISE_SHAPING": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_OUTPUTS_REQUIRED": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_OUTPUT_FORM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_OUTPUT_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_OUTPUT_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_PHASE_ANGLE_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_PHASE_INCREMENT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_PHASE_INCREMENT_VALUE": [ { "value": "1101101001110100,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0", "resolve_type": "generated", "usage": "all" } ],
"C_RESYNC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_PHASE_OFFSET": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_PHASE_OFFSET_VALUE": [ { "value": "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0", "resolve_type": "generated", "usage": "all" } ],
"C_OPTIMISE_GOAL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_USE_DSP48": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_POR_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AMPLITUDE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_ACLKEN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_ARESETN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_TREADY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_S_PHASE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_S_PHASE_TDATA_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_S_PHASE_HAS_TUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_S_PHASE_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_S_CONFIG": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_S_CONFIG_SYNC_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_S_CONFIG_TDATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_M_DATA": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_M_DATA_TDATA_WIDTH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_M_DATA_HAS_TUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_M_DATA_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_M_PHASE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_M_PHASE_TDATA_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_M_PHASE_HAS_TUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_M_PHASE_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_DEBUG_INTERFACE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_CHAN_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ]
},
"project_parameters": {
"ARCHITECTURE": [ { "value": "zynq" } ],
"BASE_BOARD_PART": [ { "value": "xilinx.com:zc706:part0:1.4" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xc7z045" } ],
"NEXTGEN_VERSAL": [ { "value": "0" } ],
"PACKAGE": [ { "value": "ffg900" } ],
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "" } ]
},
"runtime_parameters": {
"IPCONTEXT": [ { "value": "IP_Flow" } ],
"IPREVISION": [ { "value": "25" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "../../../../zc706_cx9261a_demo.gen/sources_1/ip/dds_32b_8b" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "." } ],
"SWVERSION": [ { "value": "2024.1" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
}
},
"boundary": {
"ports": {
"aclk": [ { "direction": "in", "driver_value": "0x0" } ],
"s_axis_config_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
"s_axis_config_tdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
"m_axis_data_tvalid": [ { "direction": "out", "driver_value": "0x0" } ],
"m_axis_data_tdata": [ { "direction": "out", "size_left": "15", "size_right": "0", "driver_value": "0" } ]
},
"interfaces": {
"event_pinc_invalid_intf": {
"vlnv": "xilinx.com:signal:interrupt:1.0",
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
"mode": "master",
"parameters": {
"SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
"PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
}
},
"event_poff_invalid_intf": {
"vlnv": "xilinx.com:signal:interrupt:1.0",
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
"mode": "master",
"parameters": {
"SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
"PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
}
},
"event_phase_in_invalid_intf": {
"vlnv": "xilinx.com:signal:interrupt:1.0",
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
"mode": "master",
"parameters": {
"SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
"PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
}
},
"event_s_phase_tlast_missing_intf": {
"vlnv": "xilinx.com:signal:interrupt:1.0",
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
"mode": "master",
"parameters": {
"SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
"PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
}
},
"event_s_phase_tlast_unexpected_intf": {
"vlnv": "xilinx.com:signal:interrupt:1.0",
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
"mode": "master",
"parameters": {
"SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
"PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
}
},
"event_s_phase_chanid_incorrect_intf": {
"vlnv": "xilinx.com:signal:interrupt:1.0",
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
"mode": "master",
"parameters": {
"SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
"PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
}
},
"event_s_config_tlast_missing_intf": {
"vlnv": "xilinx.com:signal:interrupt:1.0",
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
"mode": "master",
"parameters": {
"SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
"PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
}
},
"event_s_config_tlast_unexpected_intf": {
"vlnv": "xilinx.com:signal:interrupt:1.0",
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
"mode": "master",
"parameters": {
"SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
"PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
}
},
"aclk_intf": {
"vlnv": "xilinx.com:signal:clock:1.0",
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
"mode": "slave",
"parameters": {
"ASSOCIATED_BUSIF": [ { "value": "M_AXIS_PHASE:S_AXIS_CONFIG:M_AXIS_DATA:S_AXIS_PHASE", "value_src": "constant", "usage": "all" } ],
"ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "usage": "all" } ],
"ASSOCIATED_CLKEN": [ { "value": "aclken", "value_src": "constant", "usage": "all" } ],
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"CLK": [ { "physical_name": "aclk" } ]
}
},
"aresetn_intf": {
"vlnv": "xilinx.com:signal:reset:1.0",
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
"mode": "slave",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
}
},
"aclken_intf": {
"vlnv": "xilinx.com:signal:clockenable:1.0",
"abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0",
"mode": "slave",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ]
}
},
"M_AXIS_DATA": {
"vlnv": "xilinx.com:interface:axis:1.0",
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
"mode": "master",
"parameters": {
"TDATA_NUM_BYTES": [ { "value": "2", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"TDATA": [ { "physical_name": "m_axis_data_tdata" } ],
"TVALID": [ { "physical_name": "m_axis_data_tvalid" } ]
}
},
"S_AXIS_CONFIG": {
"vlnv": "xilinx.com:interface:axis:1.0",
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
"mode": "slave",
"parameters": {
"TDATA_NUM_BYTES": [ { "value": "4", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"TDATA": [ { "physical_name": "s_axis_config_tdata" } ],
"TVALID": [ { "physical_name": "s_axis_config_tvalid" } ]
}
}
}
}
}
}
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/ip/hop_rom/hop_rom.xci
+254
View File
@@ -0,0 +1,254 @@
{
"schema": "xilinx.com:schema:json_instance:1.0",
"ip_inst": {
"xci_name": "hop_rom",
"component_reference": "xilinx.com:ip:blk_mem_gen:8.4",
"ip_revision": "8",
"gen_directory": "../../../../zc706_cx9261a_demo.gen/sources_1/ip/hop_rom",
"parameters": {
"component_parameters": {
"Component_Name": [ { "value": "hop_rom", "resolve_type": "user", "usage": "all" } ],
"Interface_Type": [ { "value": "Native", "resolve_type": "user", "usage": "all" } ],
"AXI_Type": [ { "value": "AXI4_Full", "resolve_type": "user", "usage": "all" } ],
"AXI_Slave_Type": [ { "value": "Memory_Slave", "resolve_type": "user", "usage": "all" } ],
"Use_AXI_ID": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"AXI_ID_Width": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"Memory_Type": [ { "value": "Single_Port_ROM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"PRIM_type_to_Implement": [ { "value": "BRAM", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Enable_32bit_Address": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"ecctype": [ { "value": "No_ECC", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"ECC": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"EN_SLEEP_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"EN_DEEPSLEEP_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"EN_SHUTDOWN_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"EN_ECC_PIPE": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RD_ADDR_CHNG_A": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RD_ADDR_CHNG_B": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Use_Error_Injection_Pins": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Error_Injection_Type": [ { "value": "Single_Bit_Error_Injection", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Use_Byte_Write_Enable": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Byte_Size": [ { "value": "9", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Algorithm": [ { "value": "Minimum_Area", "resolve_type": "user", "usage": "all" } ],
"Primitive": [ { "value": "8kx2", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Assume_Synchronous_Clk": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Write_Width_A": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Write_Depth_A": [ { "value": "256", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Read_Width_A": [ { "value": "32", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Operating_Mode_A": [ { "value": "WRITE_FIRST", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Enable_A": [ { "value": "Always_Enabled", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"Write_Width_B": [ { "value": "32", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Read_Width_B": [ { "value": "32", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Operating_Mode_B": [ { "value": "WRITE_FIRST", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Enable_B": [ { "value": "Always_Enabled", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Register_PortA_Output_of_Memory_Primitives": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Register_PortA_Output_of_Memory_Core": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Use_REGCEA_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Register_PortB_Output_of_Memory_Primitives": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Register_PortB_Output_of_Memory_Core": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Use_REGCEB_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"register_porta_input_of_softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"register_portb_output_of_softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Pipeline_Stages": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Load_Init_File": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Coe_File": [ { "value": "../coe/sweep_freq.coe", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"Fill_Remaining_Memory_Locations": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Remaining_Memory_Locations": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Use_RSTA_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Reset_Memory_Latch_A": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Reset_Priority_A": [ { "value": "CE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Output_Reset_Value_A": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Use_RSTB_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Reset_Memory_Latch_B": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Reset_Priority_B": [ { "value": "CE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Output_Reset_Value_B": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Reset_Type": [ { "value": "SYNC", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Additional_Inputs_for_Power_Estimation": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Port_A_Clock": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Port_A_Write_Rate": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Port_B_Clock": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Port_B_Write_Rate": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Port_A_Enable_Rate": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Port_B_Enable_Rate": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Collision_Warnings": [ { "value": "ALL", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Disable_Collision_Warnings": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Disable_Out_of_Range_Warnings": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"use_bram_block": [ { "value": "Stand_Alone", "resolve_type": "user", "usage": "all" } ],
"MEM_FILE": [ { "value": "no_mem_loaded", "resolve_type": "user", "usage": "all" } ],
"CTRL_ECC_ALGO": [ { "value": "NONE", "resolve_type": "user", "usage": "all" } ],
"EN_SAFETY_CKT": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"READ_LATENCY_A": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"READ_LATENCY_B": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ]
},
"model_parameters": {
"C_FAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ],
"C_XDEVICEFAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ],
"C_ELABORATION_DIR": [ { "value": "./", "resolve_type": "generated", "usage": "all" } ],
"C_INTERFACE_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXI_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXI_SLAVE_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_USE_BRAM_BLOCK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_ENABLE_32BIT_ADDRESS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_CTRL_ECC_ALGO": [ { "value": "NONE", "resolve_type": "generated", "usage": "all" } ],
"C_HAS_AXI_ID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXI_ID_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_MEM_TYPE": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_BYTE_SIZE": [ { "value": "9", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_ALGORITHM": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_PRIM_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_LOAD_INIT_FILE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_INIT_FILE_NAME": [ { "value": "hop_rom.mif", "resolve_type": "generated", "usage": "all" } ],
"C_INIT_FILE": [ { "value": "hop_rom.mem", "resolve_type": "generated", "usage": "all" } ],
"C_USE_DEFAULT_DATA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_DEFAULT_DATA": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
"C_HAS_RSTA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_RST_PRIORITY_A": [ { "value": "CE", "resolve_type": "generated", "usage": "all" } ],
"C_RSTRAM_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_INITA_VAL": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
"C_HAS_ENA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_REGCEA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_USE_BYTE_WEA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_WEA_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_WRITE_MODE_A": [ { "value": "WRITE_FIRST", "resolve_type": "generated", "usage": "all" } ],
"C_WRITE_WIDTH_A": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_READ_WIDTH_A": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_WRITE_DEPTH_A": [ { "value": "256", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_READ_DEPTH_A": [ { "value": "256", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_ADDRA_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_RSTB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_RST_PRIORITY_B": [ { "value": "CE", "resolve_type": "generated", "usage": "all" } ],
"C_RSTRAM_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_INITB_VAL": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
"C_HAS_ENB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_REGCEB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_USE_BYTE_WEB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_WEB_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_WRITE_MODE_B": [ { "value": "WRITE_FIRST", "resolve_type": "generated", "usage": "all" } ],
"C_WRITE_WIDTH_B": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_READ_WIDTH_B": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_WRITE_DEPTH_B": [ { "value": "256", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_READ_DEPTH_B": [ { "value": "256", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_ADDRB_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_MEM_OUTPUT_REGS_A": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_MEM_OUTPUT_REGS_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_MUX_OUTPUT_REGS_A": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_MUX_OUTPUT_REGS_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_MUX_PIPELINE_STAGES": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_SOFTECC_INPUT_REGS_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_SOFTECC_OUTPUT_REGS_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_USE_SOFTECC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_USE_ECC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_EN_ECC_PIPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_READ_LATENCY_A": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_READ_LATENCY_B": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_INJECTERR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_SIM_COLLISION_CHECK": [ { "value": "ALL", "resolve_type": "generated", "usage": "all" } ],
"C_COMMON_CLK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_DISABLE_WARN_BHV_COLL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_EN_SLEEP_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_USE_URAM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_EN_RDADDRA_CHG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_EN_RDADDRB_CHG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_EN_DEEPSLEEP_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_EN_SHUTDOWN_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_EN_SAFETY_CKT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_DISABLE_WARN_BHV_RANGE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_COUNT_36K_BRAM": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
"C_COUNT_18K_BRAM": [ { "value": "1", "resolve_type": "generated", "usage": "all" } ],
"C_EST_POWER_SUMMARY": [ { "value": "Estimated Power for IP : 3.375199 mW", "resolve_type": "generated", "usage": "all" } ]
},
"project_parameters": {
"ARCHITECTURE": [ { "value": "zynq" } ],
"BASE_BOARD_PART": [ { "value": "xilinx.com:zc706:part0:1.4" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xc7z045" } ],
"NEXTGEN_VERSAL": [ { "value": "0" } ],
"PACKAGE": [ { "value": "ffg900" } ],
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "" } ]
},
"runtime_parameters": {
"IPCONTEXT": [ { "value": "IP_Flow" } ],
"IPREVISION": [ { "value": "8" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "../../../../zc706_cx9261a_demo.gen/sources_1/ip/hop_rom" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "." } ],
"SWVERSION": [ { "value": "2024.1" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
}
},
"boundary": {
"ports": {
"clka": [ { "direction": "in", "driver_value": "0" } ],
"addra": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
"douta": [ { "direction": "out", "size_left": "31", "size_right": "0" } ]
},
"interfaces": {
"CLK.ACLK": {
"vlnv": "xilinx.com:signal:clock:1.0",
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
"mode": "slave",
"parameters": {
"ASSOCIATED_BUSIF": [ { "value": "AXI_SLAVE_S_AXI:AXILite_SLAVE_S_AXI", "value_src": "constant", "usage": "all" } ],
"ASSOCIATED_RESET": [ { "value": "s_aresetn", "value_src": "constant", "usage": "all" } ],
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
}
},
"RST.ARESETN": {
"vlnv": "xilinx.com:signal:reset:1.0",
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
"mode": "slave",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
}
},
"BRAM_PORTA": {
"vlnv": "xilinx.com:interface:bram:1.0",
"abstraction_type": "xilinx.com:interface:bram_rtl:1.0",
"mode": "slave",
"parameters": {
"MEM_ADDRESS_MODE": [ { "value": "BYTE_ADDRESS", "resolve_type": "user", "usage": "all" } ],
"MEM_SIZE": [ { "value": "8192", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"MEM_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"MEM_ECC": [ { "value": "NONE", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"MASTER_TYPE": [ { "value": "OTHER", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"READ_WRITE_MODE": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"READ_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"ADDR": [ { "physical_name": "addra" } ],
"CLK": [ { "physical_name": "clka" } ],
"DOUT": [ { "physical_name": "douta" } ]
}
}
},
"memory_maps": {
"S_1": {
"address_blocks": {
"Mem0": {
"base_address": "0",
"range": "4096",
"usage": "memory",
"access": "read-write",
"parameters": {
"OFFSET_BASE_PARAM": [ { "value": "C_BASEADDR" } ],
"OFFSET_HIGH_PARAM": [ { "value": "C_HIGHADDR" } ]
}
}
}
}
}
}
}
}
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/ip/hrc_64_12_025/hrc_64_12_025.xci
+350
View File
@@ -0,0 +1,350 @@
{
"schema": "xilinx.com:schema:json_instance:1.0",
"ip_inst": {
"xci_name": "hrc_64_12_025",
"component_reference": "xilinx.com:ip:fir_compiler:7.2",
"ip_revision": "22",
"gen_directory": "../../../../zc706_cx9261a_demo.gen/sources_1/ip/hrc_64_12_025",
"parameters": {
"component_parameters": {
"Component_Name": [ { "value": "hrc_64_12_025", "resolve_type": "user", "usage": "all" } ],
"GUI_Behaviour": [ { "value": "Coregen", "resolve_type": "user", "usage": "all" } ],
"CoefficientSource": [ { "value": "COE_File", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"CoefficientVector": [ { "value": "6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6", "resolve_type": "user", "usage": "all" } ],
"Coefficient_File": [ { "value": "../coe/hrc_64_12_025.coe", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"Coefficient_Sets": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Coefficient_Reload": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Filter_Type": [ { "value": "Interpolation", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"Rate_Change_Type": [ { "value": "Integer", "resolve_type": "user", "usage": "all" } ],
"Interpolation_Rate": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Decimation_Rate": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Zero_Pack_Factor": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Channel_Sequence": [ { "value": "Basic", "resolve_type": "user", "usage": "all" } ],
"Number_Channels": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Select_Pattern": [ { "value": "All", "resolve_type": "user", "usage": "all" } ],
"Pattern_List": [ { "value": "P4-0,P4-1,P4-2,P4-3,P4-4", "resolve_type": "user", "usage": "all" } ],
"Number_Paths": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"RateSpecification": [ { "value": "Input_Sample_Period", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"HardwareOversamplingRate": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"SamplePeriod": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"Sample_Frequency": [ { "value": "0.001", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"Clock_Frequency": [ { "value": "300.0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"Coefficient_Sign": [ { "value": "Signed", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"Quantization": [ { "value": "Integer_Coefficients", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"Coefficient_Width": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"BestPrecision": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Coefficient_Fractional_Bits": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Coefficient_Structure": [ { "value": "Inferred", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"Data_Sign": [ { "value": "Signed", "resolve_type": "user", "usage": "all" } ],
"Data_Width": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Data_Fractional_Bits": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Output_Rounding_Mode": [ { "value": "Full_Precision", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"Output_Width": [ { "value": "18", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Filter_Architecture": [ { "value": "Systolic_Multiply_Accumulate", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"Optimization_Goal": [ { "value": "Area", "resolve_type": "user", "usage": "all" } ],
"Optimization_Selection": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
"Data_Path_Fanout": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Pre_Adder_Pipeline": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Coefficient_Fanout": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Control_Path_Fanout": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Control_Column_Fanout": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Control_Broadcast_Fanout": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Control_LUT_Pipeline": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"No_BRAM_Read_First_Mode": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Optimal_Column_Lengths": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Data_Path_Broadcast": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Disable_Half_Band_Centre_Tap": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"No_SRL_Attributes": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Other": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Optimization_List": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
"Data_Buffer_Type": [ { "value": "Automatic", "resolve_type": "user", "usage": "all" } ],
"Coefficient_Buffer_Type": [ { "value": "Automatic", "resolve_type": "user", "usage": "all" } ],
"Input_Buffer_Type": [ { "value": "Automatic", "resolve_type": "user", "usage": "all" } ],
"Output_Buffer_Type": [ { "value": "Automatic", "resolve_type": "user", "usage": "all" } ],
"Preference_For_Other_Storage": [ { "value": "Automatic", "resolve_type": "user", "usage": "all" } ],
"Multi_Column_Support": [ { "value": "Automatic", "resolve_type": "user", "usage": "all" } ],
"Inter_Column_Pipe_Length": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
"ColumnConfig": [ { "value": "7", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"DATA_Has_TLAST": [ { "value": "Not_Required", "resolve_type": "user", "usage": "all" } ],
"M_DATA_Has_TREADY": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"S_DATA_Has_FIFO": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"S_DATA_Has_TUSER": [ { "value": "Not_Required", "resolve_type": "user", "usage": "all" } ],
"M_DATA_Has_TUSER": [ { "value": "Not_Required", "resolve_type": "user", "usage": "all" } ],
"DATA_TUSER_Width": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"S_CONFIG_Sync_Mode": [ { "value": "On_Vector", "resolve_type": "user", "usage": "all" } ],
"S_CONFIG_Method": [ { "value": "Single", "resolve_type": "user", "usage": "all" } ],
"Num_Reload_Slots": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Has_ACLKEN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Has_ARESETn": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Reset_Data_Vector": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Blank_Output": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Gen_MIF_from_Spec": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Gen_MIF_from_COE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Reload_File": [ { "value": "no_coe_file_loaded", "resolve_type": "user", "usage": "all" } ],
"Gen_MIF_Files": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"DisplayReloadOrder": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Passband_Min": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"Passband_Max": [ { "value": "0.5", "resolve_type": "user", "format": "float", "usage": "all" } ],
"Stopband_Min": [ { "value": "0.5", "resolve_type": "user", "format": "float", "usage": "all" } ],
"Stopband_Max": [ { "value": "1.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"Filter_Selection": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ]
},
"model_parameters": {
"C_XDEVICEFAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ],
"C_ELABORATION_DIR": [ { "value": "./", "resolve_type": "generated", "usage": "all" } ],
"C_COMPONENT_NAME": [ { "value": "hrc_64_12_025", "resolve_type": "generated", "usage": "all" } ],
"C_COEF_FILE": [ { "value": "hrc_64_12_025.mif", "resolve_type": "generated", "usage": "all" } ],
"C_COEF_FILE_LINES": [ { "value": "448", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_FILTER_TYPE": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_INTERP_RATE": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_DECIM_RATE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_ZERO_PACKING_FACTOR": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_SYMMETRY": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_NUM_FILTS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_NUM_TAPS": [ { "value": "769", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_NUM_CHANNELS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_CHANNEL_PATTERN": [ { "value": "fixed", "resolve_type": "generated", "usage": "all" } ],
"C_ROUND_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_COEF_RELOAD": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_NUM_RELOAD_SLOTS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_COL_MODE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_COL_PIPE_LEN": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_COL_CONFIG": [ { "value": "7", "resolve_type": "generated", "usage": "all" } ],
"C_OPTIMIZATION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_DATA_PATH_WIDTHS": [ { "value": "2", "resolve_type": "generated", "usage": "all" } ],
"C_DATA_IP_PATH_WIDTHS": [ { "value": "2", "resolve_type": "generated", "usage": "all" } ],
"C_DATA_PX_PATH_WIDTHS": [ { "value": "2", "resolve_type": "generated", "usage": "all" } ],
"C_DATA_WIDTH": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_COEF_PATH_WIDTHS": [ { "value": "17", "resolve_type": "generated", "usage": "all" } ],
"C_COEF_WIDTH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_DATA_PATH_SRC": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
"C_COEF_PATH_SRC": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
"C_PX_PATH_SRC": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
"C_DATA_PATH_SIGN": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
"C_COEF_PATH_SIGN": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
"C_ACCUM_PATH_WIDTHS": [ { "value": "19", "resolve_type": "generated", "usage": "all" } ],
"C_OUTPUT_WIDTH": [ { "value": "18", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_OUTPUT_PATH_WIDTHS": [ { "value": "18", "resolve_type": "generated", "usage": "all" } ],
"C_ACCUM_OP_PATH_WIDTHS": [ { "value": "18", "resolve_type": "generated", "usage": "all" } ],
"C_EXT_MULT_CNFG": [ { "value": "none", "resolve_type": "generated", "usage": "all" } ],
"C_DATA_PATH_PSAMP_SRC": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
"C_OP_PATH_PSAMP_SRC": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
"C_NUM_MADDS": [ { "value": "7", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_OPT_MADDS": [ { "value": "none", "resolve_type": "generated", "usage": "all" } ],
"C_OVERSAMPLING_RATE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_INPUT_RATE": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_OUTPUT_RATE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_DATA_MEMTYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_COEF_MEMTYPE": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_IPBUFF_MEMTYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_OPBUFF_MEMTYPE": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_DATAPATH_MEMTYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_MEM_ARRANGEMENT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_DATA_MEM_PACKING": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_COEF_MEM_PACKING": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_FILTS_PACKED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_LATENCY": [ { "value": "17", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_ARESETn": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_ACLKEN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_DATA_HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_S_DATA_HAS_FIFO": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_S_DATA_HAS_TUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_S_DATA_TDATA_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_S_DATA_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_M_DATA_HAS_TREADY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_M_DATA_HAS_TUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_M_DATA_TDATA_WIDTH": [ { "value": "24", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_M_DATA_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_CONFIG_CHANNEL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_CONFIG_SYNC_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_CONFIG_PACKET_SIZE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_CONFIG_TDATA_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_RELOAD_TDATA_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ]
},
"project_parameters": {
"ARCHITECTURE": [ { "value": "zynq" } ],
"BASE_BOARD_PART": [ { "value": "xilinx.com:zc706:part0:1.4" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xc7z045" } ],
"NEXTGEN_VERSAL": [ { "value": "0" } ],
"PACKAGE": [ { "value": "ffg900" } ],
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "" } ]
},
"runtime_parameters": {
"IPCONTEXT": [ { "value": "IP_Flow" } ],
"IPREVISION": [ { "value": "22" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "../../../../zc706_cx9261a_demo.gen/sources_1/ip/hrc_64_12_025" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "." } ],
"SWVERSION": [ { "value": "2024.1" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
}
},
"boundary": {
"ports": {
"aclk": [ { "direction": "in" } ],
"s_axis_data_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
"s_axis_data_tready": [ { "direction": "out", "driver_value": "0x1" } ],
"s_axis_data_tdata": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
"m_axis_data_tvalid": [ { "direction": "out", "driver_value": "0x0" } ],
"m_axis_data_tdata": [ { "direction": "out", "size_left": "23", "size_right": "0", "driver_value": "0" } ]
},
"interfaces": {
"event_s_data_tlast_missing_intf": {
"vlnv": "xilinx.com:signal:interrupt:1.0",
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
"mode": "master",
"parameters": {
"SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
"PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
}
},
"event_s_data_tlast_unexpected_intf": {
"vlnv": "xilinx.com:signal:interrupt:1.0",
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
"mode": "master",
"parameters": {
"SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
"PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
}
},
"event_s_data_chanid_incorrect_intf": {
"vlnv": "xilinx.com:signal:interrupt:1.0",
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
"mode": "master",
"parameters": {
"SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
"PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
}
},
"event_s_config_tlast_missing_intf": {
"vlnv": "xilinx.com:signal:interrupt:1.0",
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
"mode": "master",
"parameters": {
"SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
"PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
}
},
"event_s_config_tlast_unexpected_intf": {
"vlnv": "xilinx.com:signal:interrupt:1.0",
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
"mode": "master",
"parameters": {
"SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
"PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
}
},
"event_s_reload_tlast_missing_intf": {
"vlnv": "xilinx.com:signal:interrupt:1.0",
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
"mode": "master",
"parameters": {
"SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
"PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
}
},
"event_s_reload_tlast_unexpected_intf": {
"vlnv": "xilinx.com:signal:interrupt:1.0",
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
"mode": "master",
"parameters": {
"SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
"PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
}
},
"aclk_intf": {
"vlnv": "xilinx.com:signal:clock:1.0",
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
"mode": "slave",
"parameters": {
"ASSOCIATED_BUSIF": [ { "value": "S_AXIS_CONFIG:M_AXIS_DATA:S_AXIS_DATA:S_AXIS_RELOAD", "value_src": "constant", "usage": "all" } ],
"ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "usage": "all" } ],
"ASSOCIATED_CLKEN": [ { "value": "aclken", "value_src": "constant", "usage": "all" } ],
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"CLK": [ { "physical_name": "aclk" } ]
}
},
"aresetn_intf": {
"vlnv": "xilinx.com:signal:reset:1.0",
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
"mode": "slave",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
}
},
"aclken_intf": {
"vlnv": "xilinx.com:signal:clockenable:1.0",
"abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0",
"mode": "slave",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ]
}
},
"S_AXIS_DATA": {
"vlnv": "xilinx.com:interface:axis:1.0",
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
"mode": "slave",
"parameters": {
"TDATA_NUM_BYTES": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"TDATA": [ { "physical_name": "s_axis_data_tdata" } ],
"TREADY": [ { "physical_name": "s_axis_data_tready" } ],
"TVALID": [ { "physical_name": "s_axis_data_tvalid" } ]
}
},
"M_AXIS_DATA": {
"vlnv": "xilinx.com:interface:axis:1.0",
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
"mode": "master",
"parameters": {
"TDATA_NUM_BYTES": [ { "value": "3", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"TDATA": [ { "physical_name": "m_axis_data_tdata" } ],
"TVALID": [ { "physical_name": "m_axis_data_tvalid" } ]
}
}
}
}
}
}
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/ip/ila_cx9261a/ila_cx9261a.xci
+6316
View File
File diff suppressed because it is too large Load Diff
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/ip/ila_trx/ila_trx.xci
+6305
View File
File diff suppressed because it is too large Load Diff
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/ip/ila_trx_fb/ila_trx_fb.xci
+6301
View File
File diff suppressed because it is too large Load Diff
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/ip/vio_hop/vio_hop.xci
+1630
View File
File diff suppressed because it is too large Load Diff
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/ip/vio_manual_ctrl/vio_manual_ctrl.xci
+1632
View File
File diff suppressed because it is too large Load Diff
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/ip/vio_mclk_delay/vio_mclk_delay.xci
+1633
View File
File diff suppressed because it is too large Load Diff
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/ip/vio_mode_sel/vio_mode_sel.xci
+1628
View File
File diff suppressed because it is too large Load Diff
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/new/cx9261a_if.v
+133
View File
@@ -0,0 +1,133 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2023/11/06 10:15:51
// Design Name: syb
// Module Name: cx9261a_if
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module cx9261a_if (
//rst & interface mode selection
input rst,
input sp_dp_sel,
input tr_sel,
input tdd_fdd_sel,
input r1t1_r2t2_sel,
//cx9261a rx-tx data
output data_clk,
output data_clk2,
output data_clk3,
output data_valid,
output data_valid2,
output data_valid3,
output [15:0] rx1_i_data,
output [15:0] rx1_q_data,
output [15:0] rx2_i_data,
output [15:0] rx2_q_data,
output [15:0] rx3_i_data,
output [15:0] rx3_q_data,
input [15:0] tx1_i_data,
input [15:0] tx1_q_data,
input [15:0] tx2_i_data,
input [15:0] tx2_q_data,
output tx_data_ready,
output tx_data_ready2,
input power_on_flag,
//cx9261a if
input RX1_FRAME_N,
input RX2_FRAME_P,
input RX3_FRAME ,
input RX1_MCLK_IN_N,
input RX2_MCLK_IN_P,
input RX3_MCLK_IN,
output TX1_FCLK_IN_N,
output TX2_FCLK_IN_P,
output TX1_FRAME_IN_N,
output TX2_FRAME_IN_P,
inout [ 7:0] RX1_FDD_DATA_IO,
inout [ 7:0] RX2_FDD_DATA_IO,
inout [ 7:0] TX1_FDD_DATA_IO,
inout [ 7:0] TX2_FDD_DATA_IO,
inout [ 7:0] RX3_FDD_DATA_IO,
inout [ 7:0] TX3_FDD_DATA_IO
);
// cmos port TRX1 TRX2
cx9261a_if_cmos_port u_cx9261a_if_cmos_port(
.rst(rst),
.sp_dp_sel(sp_dp_sel),
.tr_sel(tr_sel),
.tdd_fdd_sel(tdd_fdd_sel),
.r1t1_r2t2_sel(r1t1_r2t2_sel),
.data_clk1(data_clk),
.data_clk2(data_clk2),
.rx1_data_valid(data_valid),
.rx2_data_valid(data_valid2),
.rx1_i_data(rx1_i_data),
.rx1_q_data(rx1_q_data),
.rx2_i_data(rx2_i_data),
.rx2_q_data(rx2_q_data),
.tx_data_valid( power_on_flag ),
.tx1_i_data( tx1_i_data ),
.tx1_q_data( tx1_q_data ),
.tx2_i_data( tx2_i_data ),
.tx2_q_data( tx2_q_data ),
.tx1_data_ready( tx_data_ready ),
.tx2_data_ready( tx_data_ready2 ),
.RX1_FRAME_N( RX1_FRAME_N ),
.RX1_MCLK_IN_N( RX1_MCLK_IN_N ),
.RX2_FRAME_P( RX2_FRAME_P ),
.RX2_MCLK_IN_P( RX2_MCLK_IN_P ),
.TX1_FCLK_IN_N( TX1_FCLK_IN_N ),
.TX1_FRAME_IN_N( TX1_FRAME_IN_N ),
.TX2_FCLK_IN_P( TX2_FCLK_IN_P ),
.TX2_FRAME_IN_P( TX2_FRAME_IN_P ),
.RX1_DATA_IO( RX1_FDD_DATA_IO ),
.TX1_DATA_IO( TX1_FDD_DATA_IO ),
.RX2_DATA_IO( RX2_FDD_DATA_IO ),
.TX2_DATA_IO( TX2_FDD_DATA_IO )
);
// cmos port RX3
cx9261a_if_cmos_singleport u_cx9261a_if_cmos_RX3(
.rst(rst),
.tr_sel(1'b1),
.tdd_fdd_sel(tdd_fdd_sel),
.r1t1_r2t2_sel(1'b0),
.data_clk(data_clk3),
.data_valid(data_valid3),
.rx_i_data(rx3_i_data),
.rx_q_data(rx3_q_data),
.rx2_i_data(),
.rx2_q_data(),
.tx_data_valid( 1'b1 ),
.tx_i_data('b0 ),
.tx_q_data('b0 ),
.tx2_i_data('b0 ),
.tx2_q_data('b0 ),
.tx_data_ready( ),
.RX_FRAME_IN(RX3_FRAME ),
.RX_MCLK_IN(RX3_MCLK_IN ),
.TX_FCLK_IN( ),
.TX_FRAME_IN( ),
.RX_FDD_DATA_IO( RX3_FDD_DATA_IO ),
.TX_FDD_DATA_IO( TX3_FDD_DATA_IO )
);
endmodule
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/new/cx9261a_if_cmos_port.v
+1069
View File
File diff suppressed because it is too large Load Diff
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/new/cx9261a_if_cmos_singleport.v
+492
View File
@@ -0,0 +1,492 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2022/04/29 10:25:59
// Design Name:
// Module Name: cx9261a_if_cmos
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module cx9261a_if_cmos_singleport(
input wire rst,
output data_clk,
input wire tr_sel,
input wire tdd_fdd_sel,
input wire r1t1_r2t2_sel,
output reg data_valid,
output reg [15:0] rx_i_data,
output reg [15:0] rx_q_data,
output reg [15:0] rx2_i_data,
output reg [15:0] rx2_q_data,
input tx_data_valid,
input wire [15:0] tx_i_data,
input wire [15:0] tx_q_data,
input wire [15:0] tx2_i_data,
input wire [15:0] tx2_q_data,
output reg tx_data_ready,
input wire RX_FRAME_IN,
input wire RX_MCLK_IN,
output wire TX_FCLK_IN,
output wire TX_FRAME_IN,
inout wire [7:0] RX_FDD_DATA_IO,
inout wire [7:0] TX_FDD_DATA_IO
);
localparam TDD_MODE = 1'b1 ,
FDD_MODE = 1'b0 ,
R1T1_MODE = 1'b0,
R2T2_MODE = 1'b1;
wire mclk_g;
wire R;
wire T;
wire RX_FRAME_pos;
wire RX_FRAME_neg;
wire [7:0]TX_FDD_DATA_pos;
wire [7:0]TX_FDD_DATA_neg;
wire [7:0]RX_FDD_DATA_pos;
wire [7:0]RX_FDD_DATA_neg;
wire [7:0] RX_FDD_DATA;
wire [7:0] TX_FDD_DATA;
wire [7:0] RX_FDD_DATA_O;
wire [7:0] TX_FDD_DATA_O;
reg [7:0]TX_FDD_DATA_pos_o;
reg [7:0]TX_FDD_DATA_neg_o;
reg [7:0]RX_FDD_DATA_pos_o;
reg [7:0]RX_FDD_DATA_neg_o;
BUFG MCLK_BUFG(.I(RX_MCLK_IN),.O(mclk_g));
assign data_clk = mclk_g;
assign T = tr_sel;
//***************************************************CDC**************************************************************//
xpm_cdc_async_rst #(
.DEST_SYNC_FF(4), // DECIMAL; range: 2-10
.INIT_SYNC_FF(0), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values
.RST_ACTIVE_HIGH(1) // DECIMAL; 0=active low reset, 1=active high reset
)
xpm_cdc_async_rst_inst (
.dest_arst(R), // 1-bit output: src_arst asynchronous reset signal synchronized to destination
// clock domain. This output is registered. NOTE: Signal asserts asynchronously
// but deasserts synchronously to dest_clk. Width of the reset signal is at least
// (DEST_SYNC_FF*dest_clk) period.
.dest_clk(mclk_g), // 1-bit input: Destination clock.
.src_arst(rst) // 1-bit input: Source asynchronous reset signal.
);
//***************************************************CDC**************************************************************//
//***************************************************IOBUF**************************************************************//
IOBUF #(
.DRIVE(12), // Specify the output drive strength
.IBUF_LOW_PWR("TRUE"), // Low Power - "TRUE", High Performance = "FALSE"
.IOSTANDARD("DEFAULT"), // Specify the I/O standard
.SLEW("SLOW") // Specify the output slew rate
) IOBUF_RX_FDD_DATA[7:0] (
.O(RX_FDD_DATA), // Buffer output
.IO(RX_FDD_DATA_IO), // Buffer inout port (connect directly to top-level port)
.I(RX_FDD_DATA_O), // Buffer input
.T(tdd_fdd_sel?T:1'b1) // 3-state enable input, high=input, low=output
);
IOBUF #(
.DRIVE(12), // Specify the output drive strength
.IBUF_LOW_PWR("TRUE"), // Low Power - "TRUE", High Performance = "FALSE"
.IOSTANDARD("DEFAULT"), // Specify the I/O standard
.SLEW("SLOW") // Specify the output slew rate
) IOBUF_TX_FDD_DATA[7:0] (
.O(TX_FDD_DATA), // Buffer output
.IO(TX_FDD_DATA_IO), // Buffer inout port (connect directly to top-level port)
.I(TX_FDD_DATA_O), // Buffer input
.T(tdd_fdd_sel?T:1'b0) // 3-state enable input, high=input, low=output
);
//***************************************************IOBUF**************************************************************//
//***************************************************IDDR**************************************************************//
IDDR #(
.DDR_CLK_EDGE("SAME_EDGE_PIPELINED"), // "OPPOSITE_EDGE", "SAME_EDGE"
// or "SAME_EDGE_PIPELINED"
.INIT_Q1(1'b0), // Initial value of Q1: 1'b0 or 1'b1
.INIT_Q2(1'b0), // Initial value of Q2: 1'b0 or 1'b1
.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC"
) IDDR_TX[7:0] (
.Q1(TX_FDD_DATA_pos), // 1-bit output for positive edge of clock
.Q2(TX_FDD_DATA_neg), // 1-bit output for negative edge of clock
.C(mclk_g), // 1-bit clock input
.CE(1'b1), // 1-bit clock enable input
.D(TX_FDD_DATA), // 1-bit DDR data input
.R(R), // 1-bit reset
.S(1'b0) // 1-bit set
);
IDDR #(
.DDR_CLK_EDGE("SAME_EDGE_PIPELINED"), // "OPPOSITE_EDGE", "SAME_EDGE"
// or "SAME_EDGE_PIPELINED"
.INIT_Q1(1'b0), // Initial value of Q1: 1'b0 or 1'b1
.INIT_Q2(1'b0), // Initial value of Q2: 1'b0 or 1'b1
.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC"
) IDDR_RX[7:0] (
.Q1(RX_FDD_DATA_pos), // 1-bit output for positive edge of clock
.Q2(RX_FDD_DATA_neg), // 1-bit output for negative edge of clock
.C(mclk_g), // 1-bit clock input
.CE(1'b1), // 1-bit clock enable input
.D(RX_FDD_DATA), // 1-bit DDR data input
.R(R), // 1-bit reset
.S(1'b0) // 1-bit set
);
IDDR #(
.DDR_CLK_EDGE("SAME_EDGE_PIPELINED"), // "OPPOSITE_EDGE", "SAME_EDGE"
// or "SAME_EDGE_PIPELINED"
.INIT_Q1(1'b0), // Initial value of Q1: 1'b0 or 1'b1
.INIT_Q2(1'b0), // Initial value of Q2: 1'b0 or 1'b1
.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC"
) IDDR_rx_FRAME (
.Q1(RX_FRAME_pos), // 1-bit output for positive edge of clock
.Q2(RX_FRAME_neg), // 1-bit output for negative edge of clock
.C(mclk_g), // 1-bit clock input
.CE(1'b1), // 1-bit clock enable input
.D(RX_FRAME_IN), // 1-bit DDR data input
.R(R), // 1-bit reset
.S(1'b0) // 1-bit set
);
//***************************************************IDDR**************************************************************//
//***************************************************DATA**************************************************************//
wire [1:0] RX_FRAME;
reg [3:0] RX_FRAME_BUFF;
reg [15:0] RX_I_DATA_BUFF;
reg [15:0] RX_Q_DATA_BUFF;
reg [15:0] RX2_I_DATA_BUFF;
reg [15:0] RX2_Q_DATA_BUFF;
assign RX_FRAME = {RX_FRAME_pos,RX_FRAME_neg};
always @(posedge mclk_g)
if(R)begin
RX_FRAME_BUFF<=0;
end
else begin//1100,0011...
RX_FRAME_BUFF <= {RX_FRAME_BUFF[1:0],RX_FRAME} ;
end
always @(posedge mclk_g)
if(R)begin
RX_I_DATA_BUFF<=0;
RX_Q_DATA_BUFF<=0;
RX2_I_DATA_BUFF<=0;
RX2_Q_DATA_BUFF<=0;
end
else begin
if(r1t1_r2t2_sel == R2T2_MODE)begin
if(RX_FRAME == 2'b11)begin//normal case
RX2_I_DATA_BUFF<= {RX_FDD_DATA_pos,TX_FDD_DATA_pos};
RX2_Q_DATA_BUFF<= {RX_FDD_DATA_neg,TX_FDD_DATA_neg};
end
else if(RX_FRAME == 2'b00)begin
RX_I_DATA_BUFF<= {RX_FDD_DATA_pos,TX_FDD_DATA_pos};
RX_Q_DATA_BUFF<= {RX_FDD_DATA_neg,TX_FDD_DATA_neg};
end
else begin
RX_I_DATA_BUFF<=0;
RX_Q_DATA_BUFF<=0;
end
end
else
if(tdd_fdd_sel == TDD_MODE)
if(RX_FRAME == 2'b10)begin//normal case
RX_I_DATA_BUFF<= {RX_FDD_DATA_pos,TX_FDD_DATA_pos};
RX_Q_DATA_BUFF<= {RX_FDD_DATA_neg,TX_FDD_DATA_neg};
end
else if(RX_FRAME == 2'b01)begin//invert case
RX_Q_DATA_BUFF<= {RX_FDD_DATA_pos,TX_FDD_DATA_pos};
RX_I_DATA_BUFF<= {RX_FDD_DATA_neg,TX_FDD_DATA_neg};
end
else begin
RX_I_DATA_BUFF<=0;
RX_Q_DATA_BUFF<=0;
end
else begin //(tdd_fdd_sel == FDD_MODE)
if(RX_FRAME == 2'b11)begin//
RX_I_DATA_BUFF<= {RX_FDD_DATA_pos,RX_FDD_DATA_neg};
end
else if(RX_FRAME == 2'b00)begin
RX_Q_DATA_BUFF<= {RX_FDD_DATA_pos,RX_FDD_DATA_neg};
end
else begin
RX_I_DATA_BUFF<=0;
RX_Q_DATA_BUFF<=0;
end
end
end
always @(posedge mclk_g)
if(R)begin
rx_i_data<=0;
rx_q_data<=0;
rx2_i_data<=0;
rx2_q_data<=0;
data_valid<=1'b0;
end
else begin
if(r1t1_r2t2_sel == R2T2_MODE)begin
if(RX_FRAME_BUFF == 4'b1100)begin
rx_i_data<=RX_I_DATA_BUFF;
rx_q_data<=RX_Q_DATA_BUFF;
rx2_i_data<=RX2_I_DATA_BUFF;
rx2_q_data<=RX2_Q_DATA_BUFF;
data_valid<=1'b1;
end
else begin
rx_i_data<=rx_i_data;
rx_q_data<=rx_q_data;
data_valid<=1'b0;
end
end
else
if( tdd_fdd_sel == TDD_MODE )
if(RX_FRAME_BUFF == 4'b1010)begin
rx_i_data<=RX_I_DATA_BUFF;
rx_q_data<=RX_Q_DATA_BUFF;
data_valid<=1'b1;
end
else begin
rx_i_data<=rx_i_data;
rx_q_data<=rx_q_data;
data_valid<=1'b0;
end
else begin//(tdd_fdd_sel == FDD_MODE)
if(RX_FRAME_BUFF == 4'b1100)begin
rx_i_data<=RX_I_DATA_BUFF;
rx_q_data<=RX_Q_DATA_BUFF;
data_valid<=1'b1;
end
else begin
rx_i_data<=rx_i_data;
rx_q_data<=rx_q_data;
data_valid<=1'b0;
end
end
end
//***************************************************DATA**************************************************************//
//***************************************************TX DATA**************************************************************//
reg [15:0] TX_I_DATA_BUFF;
reg [15:0] TX_Q_DATA_BUFF;
reg [15:0] TX2_I_DATA_BUFF;
reg [15:0] TX2_Q_DATA_BUFF;
always @(posedge mclk_g)
if(R)begin
TX_I_DATA_BUFF<=0;
TX_Q_DATA_BUFF<=0;
TX2_I_DATA_BUFF<=0;
TX2_Q_DATA_BUFF<=0;
tx_data_ready = 1'b0;
end
else begin
if(r1t1_r2t2_sel == R2T2_MODE)begin
if(tx_data_valid & tx_data_ready)begin
TX_I_DATA_BUFF <= tx_i_data;
TX_Q_DATA_BUFF <= tx_q_data;
TX2_I_DATA_BUFF <= tx2_i_data;
TX2_Q_DATA_BUFF <= tx2_q_data;
tx_data_ready <= 1'b0;
end
else if(tx_data_ready == 1'b0) begin
TX_I_DATA_BUFF <= TX_I_DATA_BUFF;
TX_Q_DATA_BUFF <= TX_Q_DATA_BUFF;
TX2_I_DATA_BUFF <= TX2_I_DATA_BUFF;
TX2_Q_DATA_BUFF <= TX2_Q_DATA_BUFF;
tx_data_ready<=1'b1;
end
else begin
TX_I_DATA_BUFF <= TX_I_DATA_BUFF;
TX_Q_DATA_BUFF <= TX_Q_DATA_BUFF;
TX2_I_DATA_BUFF <= TX2_I_DATA_BUFF;
TX2_Q_DATA_BUFF <= TX2_Q_DATA_BUFF;
tx_data_ready<=tx_data_ready;
end
end
else
if( tdd_fdd_sel == TDD_MODE )
if(tx_data_valid & tx_data_ready)begin
TX_I_DATA_BUFF <= tx_i_data;
TX_Q_DATA_BUFF <= tx_q_data;
tx_data_ready <= 1'b1;
end
else if(tx_data_ready == 1'b0) begin
TX_I_DATA_BUFF <= tx_i_data;
TX_Q_DATA_BUFF <= tx_q_data;
tx_data_ready<=1'b1;
end
else begin
TX_I_DATA_BUFF <= TX_I_DATA_BUFF;
TX_Q_DATA_BUFF <= TX_Q_DATA_BUFF;
tx_data_ready<=tx_data_ready;
end
else begin//(tdd_fdd_sel == FDD_MODE)
if(tx_data_valid & tx_data_ready)begin
TX_I_DATA_BUFF <= tx_i_data;
TX_Q_DATA_BUFF <= tx_q_data;
tx_data_ready <= 1'b0;
end
else if(tx_data_ready == 1'b0) begin
TX_I_DATA_BUFF <= TX_I_DATA_BUFF;
TX_Q_DATA_BUFF <= TX_Q_DATA_BUFF;
tx_data_ready<=1'b1;
end
else begin
TX_I_DATA_BUFF <= TX_I_DATA_BUFF;
TX_Q_DATA_BUFF <= TX_Q_DATA_BUFF;
tx_data_ready<=tx_data_ready;
end
end
end
reg tx_frame_pos;
reg tx_frame_neg;
always @(posedge mclk_g)
if(R)begin
RX_FDD_DATA_pos_o<=0;
TX_FDD_DATA_pos_o<=0;
RX_FDD_DATA_neg_o<=0;
TX_FDD_DATA_neg_o<=0;
tx_frame_pos<= 1'b0;
end
else begin
if(r1t1_r2t2_sel == R2T2_MODE)begin
if(tx_data_ready==0)begin
RX_FDD_DATA_pos_o<=TX2_I_DATA_BUFF[15:8];
TX_FDD_DATA_pos_o<=TX2_I_DATA_BUFF[7:0];
RX_FDD_DATA_neg_o<=TX2_Q_DATA_BUFF[15:8];
TX_FDD_DATA_neg_o<=TX2_Q_DATA_BUFF[7:0];
tx_frame_pos<= 1'b1;
tx_frame_neg<= 1'b1;
end
else begin
RX_FDD_DATA_pos_o<=TX_I_DATA_BUFF[15:8];
TX_FDD_DATA_pos_o<=TX_I_DATA_BUFF[7:0];
RX_FDD_DATA_neg_o<=TX_Q_DATA_BUFF[15:8];
TX_FDD_DATA_neg_o<=TX_Q_DATA_BUFF[7:0];
tx_frame_pos<= 1'b0;
tx_frame_neg<= 1'b0;
end
end
else
if( tdd_fdd_sel == TDD_MODE )
if(tx_data_ready==1)begin
RX_FDD_DATA_pos_o<=TX_I_DATA_BUFF[15:8];
TX_FDD_DATA_pos_o<=TX_I_DATA_BUFF[7:0];
RX_FDD_DATA_neg_o<=TX_Q_DATA_BUFF[15:8];
TX_FDD_DATA_neg_o<=TX_Q_DATA_BUFF[7:0];
tx_frame_pos<= 1'b1;
tx_frame_neg<= 1'b0;
end
else begin
RX_FDD_DATA_pos_o<=8'd0;
TX_FDD_DATA_pos_o<=8'd0;
RX_FDD_DATA_neg_o<=8'd0;
TX_FDD_DATA_neg_o<=8'd0;
tx_frame_pos<= 1'b1;
tx_frame_neg<= 1'b0;
end
else//(tdd_fdd_sel == FDD_MODE)
if(tx_data_ready==0)begin
TX_FDD_DATA_pos_o<=TX_I_DATA_BUFF[15:8];
TX_FDD_DATA_neg_o<=TX_I_DATA_BUFF[7:0];
tx_frame_pos<= 1'b1;
tx_frame_neg<= 1'b1;
end
else begin
TX_FDD_DATA_pos_o<=TX_Q_DATA_BUFF[15:8];
TX_FDD_DATA_neg_o<=TX_Q_DATA_BUFF[7:0];
tx_frame_pos<= 1'b0;
tx_frame_neg<= 1'b0;
end
end
//***************************************************TX DATA**************************************************************//
//***************************************************ODDR**************************************************************//
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE"
.INIT(1'b0), // Initial value of Q: 1'b0 or 1'b1
.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC"
) ODDR_TX1[7:0] (
.Q(TX_FDD_DATA_O), // 1-bit DDR output
.C(mclk_g), // 1-bit clock input
.CE(1'b1), // 1-bit clock enable input
.D1(TX_FDD_DATA_pos_o), // 1-bit data input (positive edge)
.D2(TX_FDD_DATA_neg_o), // 1-bit data input (negative edge)
.R(R), // 1-bit reset
.S(1'b0) // 1-bit set
);
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE"
.INIT(1'b0), // Initial value of Q: 1'b0 or 1'b1
.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC"
) ODDR_RX1[7:0] (
.Q(RX_FDD_DATA_O), // 1-bit DDR output
.C(mclk_g), // 1-bit clock input
.CE(1'b1), // 1-bit clock enable input
.D1(RX_FDD_DATA_pos_o), // 1-bit data input (positive edge)
.D2(RX_FDD_DATA_neg_o), // 1-bit data input (negative edge)
.R(R), // 1-bit reset
.S(1'b0) // 1-bit set
);
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE"
.INIT(1'b0), // Initial value of Q: 1'b0 or 1'b1
.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC"
) ODDR_TX_FRAME (
.Q(TX_FRAME_IN), // 1-bit DDR output
.C(mclk_g), // 1-bit clock input
.CE(1'b1), // 1-bit clock enable input
.D1(tx_frame_pos), // 1-bit data input (positive edge)
.D2(tx_frame_neg), // 1-bit data input (negative edge)
.R(R), // 1-bit reset
.S(1'b0) // 1-bit set
);
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE"
.INIT(1'b0), // Initial value of Q: 1'b0 or 1'b1
.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC"
) ODDR_TX_FCLK (
.Q(TX_FCLK_IN), // 1-bit DDR output
.C(mclk_g), // 1-bit clock input
.CE(1'b1), // 1-bit clock enable input
.D1(1'b1), // 1-bit data input (positive edge)
.D2(1'b0), // 1-bit data input (negative edge)
.R(R), // 1-bit reset
.S(1'b0) // 1-bit set
);
//***************************************************ODDR**************************************************************//
endmodule
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/new/mclk_delay.v
+222
View File
@@ -0,0 +1,222 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2024/02/04 10:28:47
// Design Name:
// Module Name: mclk_delay
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module mclk_delay(
input wire RX2_MCLK_IN_P,
input wire RX1_MCLK_IN_N,
input wire RX3_MCLK_IN,
input wire rst,
output wire MCLK1,
output wire MCLK2,
output wire MCLK3,
(* MARK_DEBUG="true" *)input wire MCLK_DELAY_CTRL0,
(* MARK_DEBUG="true" *)input wire MCLK_DELAY_CTRL1,
(* MARK_DEBUG="true" *)input wire MCLK_DELAY_CTRL2,
input wire CX3E04_CLK_P,
input wire CX3E04_CLK_N,
input wire CX3E04_SYNC_P,
input wire CX3E04_SYNC_N,
inout wire FREF_DIV_MODE,
input wire ui_clk,
input wire sma_clk,
input wire OSC_OUT
);
//Debug Signal
wire cx3e04_sync;
reg r_cx3e04_sync;
wire cx3e04_clk;
//wire s_mclk;
//wire RX_MCLK;
//wire locked;
wire [4:0] MCLK_DELAY_SETVALUE0;
wire [4:0] MCLK_DELAY_SETVALUE1;
wire [4:0] MCLK_DELAY_SETVALUE2;
wire [4:0] MCLK_DELAY_CURVALUE0;
wire [4:0] MCLK_DELAY_CURVALUE1;
wire [4:0] MCLK_DELAY_CURVALUE2;
wire ld;
wire ce;
wire inv;
reg r_MCLK_DELAY_CTRL0;
reg r_MCLK_DELAY_CTRL0_DFF;
reg r_MCLK_DELAY_CTRL1;
reg r_MCLK_DELAY_CTRL1_DFF;
reg r_MCLK_DELAY_CTRL2;
//--------------------time of power_on to stable_rtx--------------------//
/*
FREF_DIV_MODE=0；f(OSC_OUT)= f(CX9261A_ref)
FREF_DIV_MODE=1；f(OSC_OUT)= f(CX9261A_ref)/2
*/
//IOBUF OSC_OUT_DIV(
// .I ( 1'b0 ),//IOBUF output
// .IO ( FREF_DIV_MODE ),//IOBUF inout
// .O (),//IOBUF input
// .T ( 1'b0 ) //IOBUF input high=fpga rx, low= fpga tx
//);
IBUFDS #(
.DIFF_TERM ("FALSE"), // Differential Termination
.IBUF_LOW_PWR("TRUE" ), // Low power="TRUE", Highest performance="FALSE"
.IOSTANDARD ("DEFAULT") // Specify the input I/O standard
) IBUFDS_sync (
.O(cx3e04_sync), // Buffer output
.I (CX3E04_SYNC_P), // Diff_p buffer input (connect directly to top-level port)
.IB(CX3E04_SYNC_N) // Diff_n buffer input (connect directly to top-level port)
);
IBUFDS #(
.DIFF_TERM ("FALSE"), // Differential Termination
.IBUF_LOW_PWR("TRUE" ), // Low power="TRUE", Highest performance="FALSE"
.IOSTANDARD ("DEFAULT") // Specify the input I/O standard
) IBUFDS_clk (
.O(cx3e04_clk), // Buffer output
.I (CX3E04_CLK_P), // Diff_p buffer input (connect directly to top-level port)
.IB(CX3E04_CLK_N) // Diff_n buffer input (connect directly to top-level port)
);
always @(posedge cx3e04_clk)begin
r_cx3e04_sync <= cx3e04_sync;
end
//---------------------sync/clk---------------------//
vio_mclk_delay mclk_delay (
.clk(ui_clk), // input wire clk
.probe_in0(MCLK_DELAY_CURVALUE0), // output wire [0 : 0] probe_out0
.probe_in1(MCLK_DELAY_CURVALUE1), // output wire [0 : 0] probe_out0
.probe_in2(MCLK_DELAY_CURVALUE2), // output wire [0 : 0] probe_out0
.probe_out0(MCLK_DELAY_SETVALUE0), // output wire [0 : 0] probe_out1
.probe_out1(MCLK_DELAY_SETVALUE1), // output wire [0 : 0] probe_out1
.probe_out2(MCLK_DELAY_SETVALUE2) // output wire [0 : 0] probe_out1
);
//确定延迟后，将IDELAY_TYPE改为FIXED,确认后延迟写入IDELAY_VALUE，其他不变
(* IODELAY_GROUP = "IDELAY_CTRL_RX12" *)
IDELAYE2 #(
.CINVCTRL_SEL("FALSE"), // Enable dynamic clock inversion (FALSE, TRUE)
.DELAY_SRC("IDATAIN"), // Delay input (IDATAIN, DATAIN)
.HIGH_PERFORMANCE_MODE("TRUE"), // Reduced jitter ("TRUE"), Reduced power ("FALSE")
.IDELAY_TYPE("VAR_LOAD"), // FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
.IDELAY_VALUE(0), // Input delay tap setting (0-31)
.PIPE_SEL("FALSE"), // Select pipelined mode, FALSE, TRUE
.REFCLK_FREQUENCY(200.0), // IDELAYCTRL clock input frequency in MHz (190.0-210.0, 290.0-310.0).
.SIGNAL_PATTERN("CLOCK") // DATA, CLOCK input signal
)
IDELAYE2_RX1 (
.CNTVALUEOUT(MCLK_DELAY_CURVALUE0), // 5-bit output: Counter value output
.DATAOUT(MCLK1), // 1-bit output: Delayed data output
.C(ui_clk), // 1-bit input: Clock input
.CE(ce), // 1-bit input: Active high enable increment/decrement input
.CINVCTRL(1'b0), // 1-bit input: Dynamic clock inversion input
.CNTVALUEIN(MCLK_DELAY_SETVALUE0), // 5-bit input: Counter value input
.DATAIN(1'b0), // 1-bit input: Internal delay data input
.IDATAIN(RX1_MCLK_IN_N), // 1-bit input: Data input from the I/O
.INC(r_MCLK_DELAY_CTRL2), // 1-bit input: Increment / Decrement tap delay input
.LD(ld), // 1-bit input: Load IDELAY_VALUE input
.LDPIPEEN(1'b0), // 1-bit input: Enable PIPELINE register to load data input
.REGRST(rst) // 1-bit input: Active-high reset tap-delay input
);
(* IODELAY_GROUP = "IDELAY_CTRL_RX12" *)
IDELAYE2 #(
.CINVCTRL_SEL("FALSE"), // Enable dynamic clock inversion (FALSE, TRUE)
.DELAY_SRC("IDATAIN"), // Delay input (IDATAIN, DATAIN)
.HIGH_PERFORMANCE_MODE("TRUE"), // Reduced jitter ("TRUE"), Reduced power ("FALSE")
.IDELAY_TYPE("VAR_LOAD"), // FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
.IDELAY_VALUE(0), // Input delay tap setting (0-31)
.PIPE_SEL("FALSE"), // Select pipelined mode, FALSE, TRUE
.REFCLK_FREQUENCY(200.0), // IDELAYCTRL clock input frequency in MHz (190.0-210.0, 290.0-310.0).
.SIGNAL_PATTERN("CLOCK") // DATA, CLOCK input signal
)
IDELAYE2_RX2 (
.CNTVALUEOUT(MCLK_DELAY_CURVALUE1), // 5-bit output: Counter value output
.DATAOUT(MCLK2), // 1-bit output: Delayed data output
.C(ui_clk), // 1-bit input: Clock input
.CE(ce), // 1-bit input: Active high enable increment/decrement input
.CINVCTRL(1'b0), // 1-bit input: Dynamic clock inversion input
.CNTVALUEIN(MCLK_DELAY_SETVALUE1), // 5-bit input: Counter value input
.DATAIN(1'b0), // 1-bit input: Internal delay data input
.IDATAIN(RX2_MCLK_IN_P), // 1-bit input: Data input from the I/O
.INC(r_MCLK_DELAY_CTRL2), // 1-bit input: Increment / Decrement tap delay input
.LD(ld), // 1-bit input: Load IDELAY_VALUE input
.LDPIPEEN(1'b0), // 1-bit input: Enable PIPELINE register to load data input
.REGRST(rst) // 1-bit input: Active-high reset tap-delay input
);
(* IODELAY_GROUP = "IDELAY_CTRL_RX12" *) // Specifies group name for associated IDELAYs/ODELAYs and IDELAYCTRL
IDELAYCTRL IDELAYCTRL_RX12 (
.RDY(), // 1-bit output: Ready output
.REFCLK(ui_clk), // 1-bit input: Reference clock input
.RST(rst) // 1-bit input: Active high reset input
);
(* IODELAY_GROUP = "IDELAY_CTRL_RX3" *)
IDELAYE2 #(
.CINVCTRL_SEL("FALSE"), // Enable dynamic clock inversion (FALSE, TRUE)
.DELAY_SRC("IDATAIN"), // Delay input (IDATAIN, DATAIN)
.HIGH_PERFORMANCE_MODE("TRUE"), // Reduced jitter ("TRUE"), Reduced power ("FALSE")
.IDELAY_TYPE("VAR_LOAD"), // FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
.IDELAY_VALUE(0), // Input delay tap setting (0-31)
.PIPE_SEL("FALSE"), // Select pipelined mode, FALSE, TRUE
.REFCLK_FREQUENCY(200.0), // IDELAYCTRL clock input frequency in MHz (190.0-210.0, 290.0-310.0).
.SIGNAL_PATTERN("CLOCK") // DATA, CLOCK input signal
)
IDELAYE2_RXFB (
.CNTVALUEOUT(MCLK_DELAY_CURVALUE2), // 5-bit output: Counter value output
.DATAOUT(MCLK3), // 1-bit output: Delayed data output
.C(ui_clk), // 1-bit input: Clock input
.CE(ce), // 1-bit input: Active high enable increment/decrement input
.CINVCTRL(1'b0), // 1-bit input: Dynamic clock inversion input
.CNTVALUEIN(MCLK_DELAY_SETVALUE2), // 5-bit input: Counter value input
.DATAIN(1'b0), // 1-bit input: Internal delay data input
.IDATAIN(RX3_MCLK_IN), // 1-bit input: Data input from the I/O
.INC(r_MCLK_DELAY_CTRL2), // 1-bit input: Increment / Decrement tap delay input
.LD(ld), // 1-bit input: Load IDELAY_VALUE input
.LDPIPEEN(1'b0), // 1-bit input: Enable PIPELINE register to load data input
.REGRST(rst) // 1-bit input: Active-high reset tap-delay input
);
(* IODELAY_GROUP = "IDELAY_CTRL_RX3" *) // Specifies group name for associated IDELAYs/ODELAYs and IDELAYCTRL
IDELAYCTRL IDELAYCTRL_RX3 (
.RDY(), // 1-bit output: Ready output
.REFCLK(ui_clk), // 1-bit input: Reference clock input
.RST(rst) // 1-bit input: Active high reset input
);
always @(posedge ui_clk)begin
r_MCLK_DELAY_CTRL0 <= MCLK_DELAY_CTRL0 ;
r_MCLK_DELAY_CTRL0_DFF <= r_MCLK_DELAY_CTRL0 ;
r_MCLK_DELAY_CTRL1 <= MCLK_DELAY_CTRL1 ;
r_MCLK_DELAY_CTRL1_DFF <= r_MCLK_DELAY_CTRL1 ;
r_MCLK_DELAY_CTRL2 <= MCLK_DELAY_CTRL2 ;
end
assign ld = ~r_MCLK_DELAY_CTRL0_DFF & r_MCLK_DELAY_CTRL0;
assign ce = ~r_MCLK_DELAY_CTRL1_DFF & r_MCLK_DELAY_CTRL1;
endmodule
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/new/system_top.v
+435
View File
@@ -0,0 +1,435 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 09/23/2024 04:37:39 PM
// Design Name:
// Module Name: system_top
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module system_top
(
// *************************************************************************
// *************************** CX9261A Interface ***************************
// *************************************************************************
input cx9261a_osc_out ,
output cx9261a_nrst ,
output cx9261a_spi_sclk ,
output cx9261a_spi_csb ,
input cx9261a_spi_miso ,
output cx9261a_spi_mosi ,
output cx9261a_txnrx_trx1 ,
output cx9261a_txnrx_trx2 ,
output cx9261a_txnrx_rxfb ,
output cx9261a_enable_trx1 ,
output cx9261a_enable_trx2 ,
output cx9261a_enable_rxfb ,
output cx9261a_tx1_fclk ,
output cx9261a_tx2_fclk ,
input cx9261a_rx1_mclk ,
input cx9261a_rx2_mclk ,
input cx9261a_rxfb_mclk ,
output cx9261a_tx1_frame ,
output cx9261a_tx2_frame ,
input cx9261a_rx1_frame ,
input cx9261a_rx2_frame ,
input cx9261a_rxfb_frame ,
inout [ 7:0] cx9261a_rxfb_rx_data,
inout [ 7:0] cx9261a_rxfb_tx_data,
inout [ 7:0] cx9261a_rx1_fdd_data,
inout [ 7:0] cx9261a_rx2_fdd_data,
inout [ 7:0] cx9261a_tx1_fdd_data,
inout [ 7:0] cx9261a_tx2_fdd_data,
// *************************************************************************
// ******************* DDR and Fixed-io (Do NOT Modify) ********************
// *************************************************************************
// ddr
inout [14:0] ddr_addr ,
inout [ 2:0] ddr_ba ,
inout ddr_cas_n ,
inout ddr_ck_n ,
inout ddr_ck_p ,
inout ddr_cke ,
inout ddr_cs_n ,
inout [ 3:0] ddr_dm ,
inout [31:0] ddr_dq ,
inout [ 3:0] ddr_dqs_n ,
inout [ 3:0] ddr_dqs_p ,
inout ddr_odt ,
inout ddr_ras_n ,
inout ddr_reset_n ,
inout ddr_we_n ,
// fixed-io
inout fixed_io_ddr_vrn ,
inout fixed_io_ddr_vrp ,
inout [53:0] fixed_io_mio ,
inout fixed_io_ps_clk ,
inout fixed_io_ps_porb ,
inout fixed_io_ps_srstb ,
// system monitor
input sysmon_vn ,
input sysmon_vp
);
////////////////////////////////////////////////////////////////////////////////
//////////////////////////// Block Design Interface ////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// gpio
wire [31:0] gpio_i;
wire [31:0] gpio_o;
wire [31:0] gpio_t;
// cx9261a
wire cx9261a_pl_rst;
wire cx9261a_tr_sel;
wire cx9261a_tdd_fdd_sel;
wire cx9261a_r1t1_r2t2_sel;
wire cx9261a_sp_dp_sel;
wire cx9261a_mclk_delay_ctrl0;
wire cx9261a_mclk_delay_ctrl1;
wire cx9261a_mclk_delay_ctrl2;
wire hop_flag; // transition indicates hop switch
assign cx9261a_nrst = gpio_o[ 0]; // cx9261a active-low reset
assign cx9261a_txnrx_trx1 = gpio_o[ 1]; // \------ Pin Control Map --------
assign cx9261a_txnrx_trx2 = gpio_o[ 2]; // \ ENABLE/TXNRX Status
assign cx9261a_txnrx_rxfb = gpio_o[ 3]; // \ 00 ALERT Mode
assign cx9261a_enable_trx1 = gpio_o[ 4]; // \ 10 TDD Rx Mode
assign cx9261a_enable_trx2 = gpio_o[ 5]; // \ 11 TDD Tx Mode
assign cx9261a_enable_rxfb = gpio_o[ 6]; // \ 10 FDD Mode
assign cx9261a_pl_rst = gpio_o[ 7]; // cx9261a pl logic active-high reset
assign cx9261a_tr_sel = gpio_o[ 8]; // 0: rx, 1: tx
assign cx9261a_tdd_fdd_sel = gpio_o[ 9]; // 0: fdd, 1: tdd
assign cx9261a_r1t1_r2t2_sel = gpio_o[10]; // 0: 1t1r, 1: 2t2r
assign cx9261a_sp_dp_sel = gpio_o[11]; // 0: dial port, 1: single port
assign cx9261a_mclk_delay_ctrl0 = gpio_o[12];
assign cx9261a_mclk_delay_ctrl1 = gpio_o[13];
assign cx9261a_mclk_delay_ctrl2 = gpio_o[14];
assign gpio_i[15] = hop_flag;
assign gpio_i[31:16] = gpio_o[31:16];
// spi interface
wire spi_sclk ;
wire spi_cs ;
wire spi_sdi ;
wire spi_sdo ;
wire spi_sdo_t ;
wire spi_three_wire;
wire spi_active ;
// cx9261 - three-wire spi or four-wire spi
assign cx9261a_spi_sclk = spi_sclk;
assign cx9261a_spi_csb = spi_cs;
assign cx9261a_spi_mosi = spi_sdo_t ? 1'bz : spi_sdo;
assign spi_sdi = spi_three_wire ? cx9261a_spi_mosi : cx9261a_spi_miso;
// ps clock
wire ps_clk_200M;
system_bd_wrapper system_bd
(
// ddr
.ddr_addr (ddr_addr ), // inout [14:0]ddr_addr
.ddr_ba (ddr_ba ), // inout [2:0]ddr_ba
.ddr_cas_n (ddr_cas_n ), // inout ddr_cas_n
.ddr_ck_n (ddr_ck_n ), // inout ddr_ck_n
.ddr_ck_p (ddr_ck_p ), // inout ddr_ck_p
.ddr_cke (ddr_cke ), // inout ddr_cke
.ddr_cs_n (ddr_cs_n ), // inout ddr_cs_n
.ddr_dm (ddr_dm ), // inout [3:0]ddr_dm
.ddr_dq (ddr_dq ), // inout [31:0]ddr_dq
.ddr_dqs_n (ddr_dqs_n ), // inout [3:0]ddr_dqs_n
.ddr_dqs_p (ddr_dqs_p ), // inout [3:0]ddr_dqs_p
.ddr_odt (ddr_odt ), // inout ddr_odt
.ddr_ras_n (ddr_ras_n ), // inout ddr_ras_n
.ddr_reset_n (ddr_reset_n ), // inout ddr_reset_n
.ddr_we_n (ddr_we_n ), // inout ddr_we_n
// fixed-io
.fixed_io_ddr_vrn (fixed_io_ddr_vrn ), // inout fixed_io_ddr_vrn
.fixed_io_ddr_vrp (fixed_io_ddr_vrp ), // inout fixed_io_ddr_vrp
.fixed_io_mio (fixed_io_mio ), // inout [53:0]fixed_io_mio
.fixed_io_ps_clk (fixed_io_ps_clk ), // inout fixed_io_ps_clk
.fixed_io_ps_porb (fixed_io_ps_porb ), // inout fixed_io_ps_porb
.fixed_io_ps_srstb (fixed_io_ps_srstb ), // inout fixed_io_ps_srstb
// system moniotr
.Vp_Vn_v_n (sysmon_vn ), // input Vp_Vn_v_n
.Vp_Vn_v_p (sysmon_vp ), // input Vp_Vn_v_p
// gpio, for control signals
.gpio_i (gpio_i ), // input [31:0]gpio_i
.gpio_o (gpio_o ), // output [31:0]gpio_o
.gpio_t (gpio_t ), // output [31:0]gpio_t
// spi interface
.spi_sclk (spi_sclk ), // output spi_sclk
.spi_cs (spi_cs ), // output [0:0]spi_cs
.spi_sdi (spi_sdi ), // input [0:0]spi_sdi
.spi_sdo (spi_sdo ), // output spi_sdo
.spi_sdo_t (spi_sdo_t ), // output spi_sdo_t
.spi_three_wire (spi_three_wire ), // output spi_three_wire
.spi_active (spi_active ), // output spi_active
// ps clock
.ps_clk_200M (ps_clk_200M ) // output ps_clk_200M
);
////////////////////////////////////////////////////////////////////////////////
////////////////////////////// CX9261A Interface ///////////////////////////////
////////////////////////////////////////////////////////////////////////////////
wire data_clk;
wire data_valid;
wire data_clk2;
wire data_valid2;
wire data_clk3;
wire data_valid3;
wire [15:0] rx1_data_i;
wire [15:0] rx1_data_q;
wire [15:0] rx2_data_i;
wire [15:0] rx2_data_q;
wire [15:0] rx3_data_i;
wire [15:0] rx3_data_q;
wire [15:0] tx1_data_i;
wire [15:0] tx1_data_q;
wire [15:0] tx2_data_i;
wire [15:0] tx2_data_q;
wire tx_data_ready;
wire tx_data_ready2;
wire cx9261a_mclk1;
wire cx9261a_mclk2;
wire cx9261a_mclk3;
mclk_delay u_mclk_delay
(
.RX1_MCLK_IN_N (cx9261a_rx1_mclk ), // input wire RX2_MCLK_IN_P
.RX2_MCLK_IN_P (cx9261a_rx2_mclk ), // input wire RX1_MCLK_IN_N
.RX3_MCLK_IN (cx9261a_rxfb_mclk ), // input wire RX3_MCLK_IN
.rst (cx9261a_pl_rst ), // input wire rst
.MCLK1 (cx9261a_mclk1 ), // output wire MCLK1
.MCLK2 (cx9261a_mclk2 ), // output wire MCLK2
.MCLK3 (cx9261a_mclk3 ), // output wire MCLK3
.MCLK_DELAY_CTRL0 (cx9261a_mclk_delay_ctrl0 ), // input wire MCLK_DELAY_CTRL0
.MCLK_DELAY_CTRL1 (cx9261a_mclk_delay_ctrl1 ), // input wire MCLK_DELAY_CTRL1
.MCLK_DELAY_CTRL2 (cx9261a_mclk_delay_ctrl2 ), // input wire MCLK_DELAY_CTRL2
.CX3E04_CLK_P (1'b0 ), // input wire CX3E04_CLK_P
.CX3E04_CLK_N (1'b0 ), // input wire CX3E04_CLK_N
.CX3E04_SYNC_P (1'b0 ), // input wire CX3E04_SYNC_P
.CX3E04_SYNC_N (1'b0 ), // input wire CX3E04_SYNC_N
.ui_clk (ps_clk_200M ), // inout wire FREF_DIV_MODE
.sma_clk (1'b0 ), // input wire ui_clk
.FREF_DIV_MODE (1'b0 ), // input wire sma_clk
.OSC_OUT (1'b0 ) // input wire OSC_OUT
);
cx9261a_if cx9261a_if_cmos
(
//复位和驱动接口模式选择
.rst (cx9261a_pl_rst ), // PS GPIO控制 模块复位，高有效。
.sp_dp_sel (cx9261a_sp_dp_sel ), // PS GPIO控制 singleport:1;dualport:0 保持芯片接口模式配置一致;
.tr_sel (cx9261a_tr_sel ), // PS GPIO控制 rx:1; tx:0 保持芯片接口模式配置一致;
.tdd_fdd_sel (cx9261a_tdd_fdd_sel ), // PS GPIO控制 tdd:1; fdd:0 保持芯片接口模式配置一致;
.r1t1_r2t2_sel (cx9261a_r1t1_r2t2_sel ), // PS GPIO控制 r2t2:1; r1t1:0 保持芯片接口模式配置一致;
//基带数据接口
.data_clk (data_clk ), // f(data_clk) = f(RX1_MCLK_IN_N);
.data_valid (data_valid ), // 任一接口模式下，data_valid可使rx1_i/q_data数据速率和ADC1采样率（无抽取）保持一致
.data_clk2 (data_clk2 ), // f(data_clk2) = f(RX2_MCLK_IN_P);
.data_valid2 (data_valid2 ), // 任一接口模式下，data_valid2可使rx2_i/q_data数据速率和ADC2采样率（无抽取）保持一致
.data_clk3 (data_clk3 ), // f(data_clk3) = f(RXFB_MCLK_IN);
.data_valid3 (data_valid3 ), // 任一接口模式下，data_valid3可使rx3_i/q_data数据速率和ADC3采样率（无抽取）保持一致
.rx1_i_data (rx1_data_i ), // \----------------------------------------------------------------------------------------
.rx1_q_data (rx1_data_q ), // \eg.：fadc = 64MSPS,fdac = 256MSPS,dac采样率固定是dac采样率的4倍。
.rx2_i_data (rx2_data_i ), // \发射数字插值倍数保持是接收数字抽取倍数4倍,则基带接收数据速率等于发射数据速率。
.rx2_q_data (rx2_data_q ), // \在FDD/singleport/r1t1、TDD/singleport/r2t2、FDD/dualport/r2t2三种数据接口模式下，
.rx3_i_data (rx3_data_i ), // \数据随路时钟MCLK fmclk = 2 * fadc，其余接口模式 fmclk = 2 * fadc。
.rx3_q_data (rx3_data_q ), // \rx1/2/3_i/q_data数据 和 tx1/2_i/q_data数据 对应处于 data_clk/2/3（速率等于MCLK）时钟域
.tx1_i_data (tx1_data_i ), // \为了保证基带接收数据速率等于发射数据速率,在上述三种三种数据接口模式下
.tx1_q_data (tx1_data_q ), // \data_valid/2/3实际是data_clk/2的两分频，其余接口模式 tx_data_ready常高;
.tx2_i_data (tx2_data_i ), // \tx_data_ready实际是data_clk/2的两分频，其余接口模式 tx_data_ready常高。
.tx2_q_data (tx2_data_q ), // \----------------------------------------------------------------------------------------
.tx_data_ready (tx_data_ready ), // 任一接口模式下，tx_data_ready可使tx1_i/q_data数据速率（4倍插值后）和DAC1采样率保持一致
.tx_data_ready2 (tx_data_ready2 ), // 任一接口模式下，tx_data_ready2可使tx2_i/q_data数据速率（4倍插值后）和DAC2采样率保持一致
//芯片数据接口 \----------------------------------------------------------------------------------------
.RX1_FRAME_N (cx9261a_rx1_frame ), // \争对客户板上数据时序异常情况，可通过IDELAYE2原语对RX1_MCLK_IN_N进行延时调节，其输出为MCLK1；
.RX1_MCLK_IN_N (cx9261a_mclk1 ), // \RX2_MCLK_IN_P延时调节，其输出为MCLK2；RXFB_MCLK_IN延时调节，其输出为MCLK3。
.RX2_FRAME_P (cx9261a_rx2_frame ), // \若无数据时序异常情况，可分别将MCLK1/2/3换成RX1_MCLK_IN_N/RX2_MCLK_IN_P/RXFB_MCLK_IN；
.RX2_MCLK_IN_P (cx9261a_mclk2 ), // \数据接口调试过程，信号推荐按无数据时序异常情况连接，若出现异常，
.RX3_FRAME (cx9261a_rxfb_frame ), // \先调节芯片内部mclk延迟寄存器（0x783/0x782/0x784），延时不够，再通过IDELAYE2原语调整时序
.RX3_MCLK_IN (cx9261a_mclk3 ), // \----------------------------------------------------------------------------------------
.TX1_FCLK_IN_N (cx9261a_tx1_fclk ), // f(TX1_FCLK_IN_N) = f(RX1_MCLK_IN_N)
.TX2_FCLK_IN_P (cx9261a_tx2_fclk ), // f(TX2_FCLK_IN_P) = f(RX2_MCLK_IN_P)
.TX1_FRAME_IN_N (cx9261a_tx1_frame ),
.TX2_FRAME_IN_P (cx9261a_tx2_frame ),
.RX1_FDD_DATA_IO (cx9261a_rx1_fdd_data ), // \----------------------------------------------------------------------------------------
.RX2_FDD_DATA_IO (cx9261a_rx2_fdd_data ), // \
.TX1_FDD_DATA_IO (cx9261a_tx1_fdd_data ), // \针对驱动模块的接口时序设计与芯片数据手册里标准接口时序不一致的问题。
.TX2_FDD_DATA_IO (cx9261a_tx2_fdd_data ), // \该模块按照MCLK/FCLK和RX_FRAME/TX_FRAME对齐去设计，便于代码实现，微调了芯片内部mclk延迟，
.RX3_FDD_DATA_IO (cx9261a_rxfb_rx_data ), // \实现了芯片标准接口时序的数据接收和发送
.TX3_FDD_DATA_IO (cx9261a_rxfb_tx_data ), // \----------------------------------------------------------------------------------------
//调试接口
.power_on_flag ( 1'b1 )
);
// <--------------------------------------------------------------------------->
// <--------------------- insert transmitter logic below ---------------------->
// <--------------------------------------------------------------------------->
wire [ 1:0] waveform_sel_1;
wire sweep_on_1 ;
wire [31:0] freq_set_1 ;
wire [ 1:0] iq_sel_1 ;
wire [ 3:0] bb_rshift_1 ;
tx_qpsk #(
.BIT_DATA (1024'b0000000100100010000011001001101000010010101000011110101110101101101100000000110000011011001100001010110101110001101111110001000111100111101101101000000010100001011010101000111110111100100101100000100110010001010001101101110000001111000111011111110010000110001011011101000011010101100111100101101100100000100010010011000000101100010100111011001110001011111101010001011101101011000011001101101010000011101001111010011010100100111000001111100111001101111010001010101101111100001001110100011101011111011010010000100001010010101100011100111111101100001000110100111001001111000011011101100011000111101111101001001010000001101000110010111010010110100010001011001101001010010001100001110110111100000101110010101110011101110111001100111010101110111101100101000100110110001000011100101111100101001100110010101010011111100110001101011110011010110100110001001011100001011110101010101111111101000001010100101111000101011110111010100110111001000111000111111111100000001110000111111011100010011111000110011111010110010110010010010000000001),
.BIT_DATA_LEN (1024),
.CLK_FREQ (48000000),
.DATA_WIDTH (16)
) u_tx1_qpsk
(
.clk (data_clk ), // input clk
.rst (1'b0 ), // input rst
.tx_data_i (tx1_data_i ), // output [11:0] tx_data_i
.tx_data_q (tx1_data_q ), // output [11:0] tx_data_q
// debug ports
.waveform_sel (waveform_sel_1[1:0]), // input [ 1:0] waveform_sel
.sweep_on (sweep_on_1 ), // input sweep_on
.freq_set (freq_set_1 ), // input [31:0] freq_set
.iq_sel (iq_sel_1 ), // input [ 1:0] iq_sel
.bb_rshift (bb_rshift_1 ) // input [ 3:0] bb_rshift
);
wire [ 1:0] waveform_sel_2;
wire sweep_on_2 ;
wire [31:0] freq_set_2 ;
wire [ 1:0] iq_sel_2 ;
wire [ 3:0] bb_rshift_2 ;
tx_qpsk #(
.BIT_DATA (1024'b0000000100100010000011001001101000010010101000011110101110101101101100000000110000011011001100001010110101110001101111110001000111100111101101101000000010100001011010101000111110111100100101100000100110010001010001101101110000001111000111011111110010000110001011011101000011010101100111100101101100100000100010010011000000101100010100111011001110001011111101010001011101101011000011001101101010000011101001111010011010100100111000001111100111001101111010001010101101111100001001110100011101011111011010010000100001010010101100011100111111101100001000110100111001001111000011011101100011000111101111101001001010000001101000110010111010010110100010001011001101001010010001100001110110111100000101110010101110011101110111001100111010101110111101100101000100110110001000011100101111100101001100110010101010011111100110001101011110011010110100110001001011100001011110101010101111111101000001010100101111000101011110111010100110111001000111000111111111100000001110000111111011100010011111000110011111010110010110010010010000000001),
.BIT_DATA_LEN (1024),
.CLK_FREQ (48000000),
.DATA_WIDTH (16)
) u_tx2_qpsk
(
.clk (data_clk2 ), // input clk
.rst (1'b0 ), // input rst
.tx_data_i (tx2_data_i ), // output [11:0] tx_data_i
.tx_data_q (tx2_data_q ), // output [11:0] tx_data_q
// debug ports
.waveform_sel (waveform_sel_2[1:0]), // input [ 1:0] waveform_sel
.sweep_on (sweep_on_2 ), // input sweep_on
.freq_set (freq_set_2 ), // input [31:0] freq_set
.iq_sel (iq_sel_2 ), // input [ 1:0] iq_sel
.bb_rshift (bb_rshift_2 ) // input [ 3:0] bb_rshift
);
////////////////////////////////////////////////////////////////////////////////
////////////////////////////// Simple Hop Control //////////////////////////////
////////////////////////////////////////////////////////////////////////////////
wire hop_en; // 1: hop enable; 0: hop disable
wire hop_trig; // vio control, switching hop_trig causes hop_flag to flip
wire [31:0] hop_inter; // hop interval
reg [31:0] hop_cnt = 'b0;
reg hop_flag_buf = 'b0;
reg hop_trig_d = 'b0;
assign hop_flag = hop_flag_buf;
always @(posedge data_clk) begin
hop_trig_d <= hop_trig;
if (hop_en) begin
hop_cnt <= (hop_cnt == hop_inter) ? 'b0 : hop_cnt + 1'b1;
hop_flag_buf <= (hop_cnt == hop_inter) ? ~hop_flag_buf : hop_flag_buf;
end
else begin
hop_cnt <= 'b0;
hop_flag_buf <= (hop_trig_d & ~hop_trig) ? ~hop_flag_buf : hop_flag_buf;
end
end
////////////////////////////////////////////////////////////////////////////////
//////////////////////////////// ILAs and VIOs /////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
vio_hop u_vio_hop (
.clk (data_clk ), // input wire clk
.probe_out0 (hop_inter ), // output wire [31 : 0] probe_out0
.probe_out1 (hop_en ), // output wire [0 : 0] probe_out1
.probe_out2 (hop_trig ) // output wire [0 : 0] probe_out2
);
ila_trx u_ila_trx1
(
.clk (data_clk ), // input wire clk
.probe0 (data_valid ), // input wire [0:0] probe0
.probe1 (rx1_data_i ), // input wire [11:0] probe1
.probe2 (rx1_data_q ), // input wire [11:0] probe2
.probe3 (tx_data_ready ), // input wire [0:0] probe3
.probe4 (tx1_data_i ), // input wire [11:0] probe4
.probe5 (tx1_data_q ), // input wire [11:0] probe5
.probe6 (hop_flag ) // input wire [0:0] probe6
);
ila_trx u_ila_trx2
(
.clk (data_clk2 ), // input wire clk
.probe0 (data_valid2 ), // input wire [0:0] probe0
.probe1 (rx2_data_i ), // input wire [11:0] probe1
.probe2 (rx2_data_q ), // input wire [11:0] probe2
.probe3 (tx_data_ready2 ), // input wire [0:0] probe3
.probe4 (tx2_data_i ), // input wire [11:0] probe4
.probe5 (tx2_data_q ), // input wire [11:0] probe5
.probe6 (hop_flag ) // input wire [0:0] probe6
);
ila_trx_fb u_ila_rx_fb
(
.clk (data_clk3 ), // input wire clk
.probe0 (data_valid3), // input wire [0:0] probe0
.probe1 (rx3_data_i ), // input wire [11:0] probe1
.probe2 (rx3_data_q ) // input wire [11:0] probe2
);
vio_manual_ctrl u_vio_manual_ctrl_1
(
.clk (data_clk ), // input wire clk
.probe_out0 (waveform_sel_1 ), // output wire [1 : 0] probe_out0
.probe_out1 (sweep_on_1 ), // output wire [0 : 0] probe_out1
.probe_out2 (freq_set_1 ), // output wire [31 : 0] probe_out2
.probe_out3 (iq_sel_1 ), // output wire [1 : 0] probe_out3
.probe_out4 (bb_rshift_1 ) // output wire [3 : 0] probe_out4
);
vio_manual_ctrl u_vio_manual_ctrl_2
(
.clk (data_clk2 ), // input wire clk
.probe_out0 (waveform_sel_2 ), // output wire [1 : 0] probe_out0
.probe_out1 (sweep_on_2 ), // output wire [0 : 0] probe_out1
.probe_out2 (freq_set_2 ), // output wire [31 : 0] probe_out2
.probe_out3 (iq_sel_2 ), // output wire [1 : 0] probe_out3
.probe_out4 (bb_rshift_2 ) // output wire [3 : 0] probe_out4
);
endmodule
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/new/tx_qpsk.v
+539
View File
@@ -0,0 +1,539 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
// _ _ ____
// | | ___ ___| |__ / ___| __ _ ___
// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
// \___/ \___/|___/_| |_| \____|\__,_|\___/
//
// Create Date: 2022/03/23 20:17:56
// Last Modified Date: 2023/03/10 15:41
// Design Name:
// Module Name: tx_qpsk
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// 20230228-1541 - 修改不扫频、无基带频偏时 [baseband_i/q] 的数据输出，原来从
// 乘法器引出，会导致频率为 0 时输出数据错误，现在直接从基带数据引出。
// 20230310-1542 - 增加输入参数，发送数据更改为直接由参数输入，发送方波改为 8
// 倍过采样，发送双音信号中 1MHz 信号的频率控制字可以根据参数中的时钟频率计
// 算得出。
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module tx_qpsk
#(
parameter DATA_WIDTH = 12, // need to be <= 16
parameter BIT_DATA = 128'b00000011000010100011110010001011001110101001111101000011100010010011011010110111101100011010010111011100110010101011111110000001, // inverse pseudorandom bit sequence, [0,flip(PRSB7)]
parameter BIT_DATA_LEN = 128,
parameter SQUARE_INTERP = 8,
parameter CLK_FREQ = 245760000 // in Hertz
)
(
input clk ,
input rst ,
output [DATA_WIDTH-1:0] tx_data_i ,
output [DATA_WIDTH-1:0] tx_data_q ,
// debug ports
input [ 1:0] waveform_sel ,
input sweep_on ,
input [31:0] freq_set ,
input [ 1:0] iq_sel ,
input [ 3:0] bb_rshift
);
localparam RCOS_INTERP = 64;
localparam INTERP = (RCOS_INTERP > SQUARE_INTERP) ? RCOS_INTERP : SQUARE_INTERP;
localparam FREQ_WORD_1M = 64'd2**64'd32*64'd1000000/CLK_FREQ;
////////////////////////////////////////////////////////////////////////////////
///////////////////////////////// Data Counter /////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// symbol & interpolation counter
reg [$clog2(INTERP*BIT_DATA_LEN)-1 : 0] cnt = 'b0;
always @(posedge clk) begin
if (rst) begin
cnt <= 'b0;
end
else begin
cnt <= (cnt == INTERP*BIT_DATA_LEN - 1) ? 'b0 : cnt + 16'b1;
end
end
////////////////////////////////////////////////////////////////////////////////
////////////////////// Root-Rasied Cosine Shaping Filter ///////////////////////
////////////////////////////////////////////////////////////////////////////////
// address
reg [$clog2(BIT_DATA_LEN)-1 : 0] hrc_data_addr_i = 'b0;
reg [$clog2(BIT_DATA_LEN)-1 : 0] hrc_data_addr_q = 'b1;
always @(posedge clk) begin
if (rst) begin
hrc_data_addr_i <= 'b0;
hrc_data_addr_q <= 'b1;
end
else begin
hrc_data_addr_i <= {cnt[$clog2(RCOS_INTERP) +: ($clog2(BIT_DATA_LEN)-1)],1'b0};
hrc_data_addr_q <= {cnt[$clog2(RCOS_INTERP) +: ($clog2(BIT_DATA_LEN)-1)],1'b1};
end
end
// bit data
reg hrc_data_i = 'b0;
reg hrc_data_q = 'b0;
always @(posedge clk) begin
if (rst) begin
hrc_data_i <= 'b0;
hrc_data_q <= 'b0;
end
else begin
hrc_data_i <= BIT_DATA[hrc_data_addr_i];
hrc_data_q <= BIT_DATA[hrc_data_addr_q];
end
end
// polarization
wire [ 7:0] hrc_data_polar_i;
wire [ 7:0] hrc_data_polar_q;
assign hrc_data_polar_i = {{7{hrc_data_i}},1'b1};
assign hrc_data_polar_q = {{7{hrc_data_q}},1'b1};
// root raised cosine shaping-filter
wire [23:0] hrc_wave_i;
wire [23:0] hrc_wave_q;
hrc_64_12_025 u_hrc_i (
.aclk (clk ), // input wire aclk
.s_axis_data_tvalid (~rst ), // input wire s_axis_data_tvalid
.s_axis_data_tready ( ), // output wire s_axis_data_tready
.s_axis_data_tdata (hrc_data_polar_i ), // input wire [7 : 0] s_axis_data_tdata
.m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid
.m_axis_data_tdata (hrc_wave_i ) // output wire [23 : 0] m_axis_data_tdata
);
hrc_64_12_025 u_hrc_q (
.aclk (clk ), // input wire aclk
.s_axis_data_tvalid (~rst ), // input wire s_axis_data_tvalid
.s_axis_data_tready ( ), // output wire s_axis_data_tready
.s_axis_data_tdata (hrc_data_polar_q ), // input wire [7 : 0] s_axis_data_tdata
.m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid
.m_axis_data_tdata (hrc_wave_q ) // output wire [23 : 0] m_axis_data_tdata
);
////////////////////////////////////////////////////////////////////////////////
//////////////////////////// Square Shaping Filter /////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// address
reg [$clog2(BIT_DATA_LEN)-1 : 0] hsq_data_addr = 'b0;
always @(posedge clk) begin
if (rst) begin
hsq_data_addr <= 'b0;
end
else
hsq_data_addr <= {cnt[$clog2(SQUARE_INTERP) +: $clog2(BIT_DATA_LEN)]};
end
// bit data
reg hsq_data = 'b0;
always @(posedge clk) begin
if (rst) begin
hsq_data <= 'b0;
end
else begin
hsq_data <= BIT_DATA[hsq_data_addr];
end
end
// square shaping-filter
reg [17:0] hsq_wave_i ='b0;
reg [17:0] hsq_wave_q ='b0;
always @(posedge clk) begin
if (rst) begin
hsq_wave_i <= 'b0;
hsq_wave_q <= 'b0;
end
else begin
hsq_wave_i <= hsq_data ? 18'b01_1111_1111_1111_1111 : 18'b10_0000_0000_0000_0001;
hsq_wave_q <= hsq_data ? 18'b10_0000_0000_0000_0001 : 18'b01_1111_1111_1111_1111;
end
end
////////////////////////////////////////////////////////////////////////////////
/////////////////////////////// Two Tone Siganl ////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// cosine wave with freq of 1 MHz
wire signed [7:0] cos_1m;
wire signed [7:0] sin_1m;
dds_32b_8b u_dds_1m
(
.aclk (clk ), // input wire aclk
.s_axis_config_tvalid (1'b1 ), // input wire s_axis_config_tvalid
.s_axis_config_tdata (FREQ_WORD_1M[31:0] ), // input wire [31 : 0] s_axis_config_tdata
.m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid
.m_axis_data_tdata ({sin_1m,cos_1m} ) // output wire [15 : 0] m_axis_data_tdata
);
// two-tone signal
reg signed [16:0] two_tone_wave_i = 'b0;
reg signed [16:0] two_tone_wave_q = 'b0;
always @(posedge clk) begin
if (rst) begin
two_tone_wave_i <= 'b0;
two_tone_wave_q <= 'b0;
end
else begin
two_tone_wave_i <= 17'b0_0111_1111_1111_1111 + {cos_1m[7],cos_1m,8'd0};
two_tone_wave_q <= 17'b0 + {sin_1m[7],sin_1m,8'd0};
end
end
////////////////////////////////////////////////////////////////////////////////
///////////////////// Waveform Selection & Hopping Control /////////////////////
////////////////////////////////////////////////////////////////////////////////
// baseband signal select
reg [17:0] baseband_sel_i = 'b0;
reg [17:0] baseband_sel_q = 'b0;
always @(posedge clk) begin
if (rst) begin
baseband_sel_i <= 'b0;
baseband_sel_q <= 'b0;
end
else begin
case (waveform_sel[1:0])
2'd0: begin
baseband_sel_i <= {hrc_wave_i[16:0],1'b0};
baseband_sel_q <= {hrc_wave_q[16:0],1'b0};
end
2'd1: begin
baseband_sel_i <= hsq_wave_i[17:0];
baseband_sel_q <= hsq_wave_q[17:0];
end
2'd2: begin
baseband_sel_i <= 18'b01_1111_1111_1111_1111;
baseband_sel_q <= 18'b0;
end
2'd3: begin
baseband_sel_i <= {two_tone_wave_i[16:0],1'b0};
baseband_sel_q <= {two_tone_wave_q[16:0],1'b0};
end
default: begin
baseband_sel_i <= {hrc_wave_i[16:0],1'b0};
baseband_sel_q <= {hrc_wave_q[16:0],1'b0};
end
endcase
end
end
// hopping control, 3750hop/s
reg [23:0] sweep_rom_addr = 'b0;
wire [31:0] freq_sweep;
always @(posedge clk) begin
if (rst) begin
sweep_rom_addr <= 'b0;
end
else if (sweep_on) begin
sweep_rom_addr <= sweep_rom_addr + 24'b1;
end
else begin
sweep_rom_addr <= 'b0;
end
end
hop_rom u_sweep_rom
(
.clka (clk ), // input wire clka
.addra (sweep_rom_addr[23:16] ), // input wire [7 : 0] addra
.douta (freq_sweep ) // output wire [31 : 0] douta
);
// choose the actual frequency word
reg [31:0] freq_word = 'b0;
always @(posedge clk) begin
if (rst) begin
freq_word <= 'b0;
end
else if (sweep_on) begin
// frequency sweep
freq_word <= freq_sweep;
end
else begin
// normal operation
freq_word <= freq_set;
end
end
// baseband frequency shift carrier generation
wire [ 7:0] cos_dds;
wire [ 7:0] sin_dds;
reg [ 7:0] cos = 'b0;
reg [ 7:0] sin = 'b0;
dds_32b_8b u_dds_bb_shift (
.aclk (clk ), // input wire aclk
.s_axis_config_tvalid (~rst ), // input wire s_axis_config_tvalid
.s_axis_config_tdata (freq_word ), // input wire [31 : 0] s_axis_config_tdata
.m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid
.m_axis_data_tdata ({sin_dds,cos_dds}) // output wire [31 : 0] m_axis_data_tdata
);
always @(posedge clk) begin
if (rst) begin
cos <= 'b0;
sin <= 'b0;
end
else if (freq_word == 'b0) begin
// to make sure the carriers stay at the right position when freq = 0
cos <= 8'b0111_1111;
sin <= 8'b0111_1111;
end
else begin
cos <= cos_dds;
sin <= sin_dds;
end
end
// baseband frequency shift modulation
wire [47:0] mod_cmpy_a;
wire [15:0] mod_cmpy_b;
wire [63:0] mod_cmpy_out;
wire [26:0] baseband_mult_i;
wire [26:0] baseband_mult_q;
assign mod_cmpy_a = {6'b0,baseband_sel_q,6'b0,baseband_sel_i};
assign mod_cmpy_b = {-sin,cos};
assign baseband_mult_i = mod_cmpy_out[58:32];
assign baseband_mult_q = mod_cmpy_out[26: 0];
cmpy_18x8 u_cmpy_18x8
(
.aclk (clk ), // input wire aclk
.s_axis_a_tvalid (1'b1 ), // input wire s_axis_a_tvalid
.s_axis_a_tdata (mod_cmpy_a ), // input wire [47 : 0] s_axis_a_tdata
.s_axis_b_tvalid (1'b1 ), // input wire s_axis_b_tvalid
.s_axis_b_tdata (mod_cmpy_b ), // input wire [15 : 0] s_axis_b_tdata
.m_axis_dout_tvalid ( ), // output wire m_axis_dout_tvalid
.m_axis_dout_tdata (mod_cmpy_out ) // output wire [63 : 0] m_axis_dout_tdata
);
// truncate to 16-bit
reg signed [15:0] baseband_i = 'b0;
reg signed [15:0] baseband_q = 'b0;
always @(posedge clk) begin
if (rst) begin
baseband_i <= 'b0;
baseband_q <= 'b0;
end
else begin
case (waveform_sel[1:0])
2'd0: begin
// scale rasied-cosine-shaped bpsk signal by 1.125 or 1.625
baseband_i <= (sweep_on == 0 && freq_set == 0) ? (baseband_sel_i[17 -: 16] + {{3{baseband_sel_i[17]}},baseband_sel_i[17 -: 13]}) : (baseband_mult_i[25:10] + {baseband_mult_i[25],baseband_mult_i[25:11]} + {{3{baseband_mult_i[25]}},baseband_mult_i[25:13]});
baseband_q <= (sweep_on == 0 && freq_set == 0) ? (baseband_sel_q[17 -: 16] + {{3{baseband_sel_q[17]}},baseband_sel_q[17 -: 13]}) : (baseband_mult_q[25:10] + {baseband_mult_q[25],baseband_mult_q[25:11]} + {{3{baseband_mult_q[25]}},baseband_mult_q[25:13]});
end
2'd1: begin
baseband_i <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_i[17 -: 16] : (baseband_mult_i[25:10] + {{2{baseband_mult_i[25]}},baseband_mult_i[25:12]});
baseband_q <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_q[17 -: 16] : (baseband_mult_q[25:10] + {{2{baseband_mult_q[25]}},baseband_mult_q[25:12]});
end
2'd2: begin
baseband_i <= baseband_mult_i[24:9];
baseband_q <= baseband_mult_q[24:9];
end
2'd3: begin
baseband_i <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_i[17 -: 16] : baseband_mult_i[24:9];
baseband_q <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_q[17 -: 16] : baseband_mult_q[24:9];
end
default: begin
// scale rasied-cosine-shaped bpsk signal by 1.125
baseband_i <= baseband_mult_i[25:10] + {{3{baseband_mult_i[25]}},baseband_mult_i[25:13]};
baseband_q <= baseband_mult_q[25:10] + {{3{baseband_mult_q[25]}},baseband_mult_q[25:13]};
end
endcase
end
end
// iq selection & baseband right shift
reg signed [15:0] baseband_data_i = 'b0;
reg signed [15:0] baseband_data_q = 'b0;
always @(posedge clk) begin
if (rst) begin
baseband_data_i <= 'b0;
baseband_data_q <= 'b0;
end
else begin
// inphase selection
if (iq_sel[1]) begin
baseband_data_i <= baseband_i >>> bb_rshift;
end
else begin
baseband_data_i <= 'b0;
end
// quadrature selection
if (iq_sel[0]) begin
baseband_data_q <= baseband_q >>> bb_rshift;
end
else begin
baseband_data_q <= 'b0;
end
end
end
// output data to ports
assign tx_data_i = baseband_data_i[15 -: DATA_WIDTH];
assign tx_data_q = baseband_data_q[15 -: DATA_WIDTH];
endmodule
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2020/12/08 12:43:46
// Design Name:
// Module Name: tb_tx_qpsk
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
// module tb_tx_qpsk;
// reg clk = 1'b0 ;
// reg rst = 1'b1 ;
// reg tx_on = 1'b1 ;
// reg [31:0] freq_set ;
// reg [ 1:0] waveform_sel = 2'b00;
// reg [ 1:0] iq_sel = 2'b11 ;
// wire [11:0] tx_data_i ;
// wire [11:0] tx_data_q ;
// reg [ 3:0] bb_rshift = 5'b0 ;
// tx_qpsk u_tx_qpsk
// (
// .clk (clk ),
// .rst (rst ),
// .tx_data_i (tx_data_i ),
// .tx_data_q (tx_data_q ),
// .waveform_sel (waveform_sel ),
// .sweep_on (1'b0 ),
// // .freq_set (32'd447392426 ),
// .freq_set (32'd0 ),
// .iq_sel (iq_sel ),
// .bb_rshift (bb_rshift )
// );
// initial begin
// #102
// rst = 1'b0;
// // freq_set = 32'd873813333;
// // waveform_sel = 2'b00;
// // bb_rshift = 5'd0;
// // #5000
// // bb_rshift = 5'd1;
// // #5000
// // bb_rshift = 5'd2;
// // #5000
// // bb_rshift = 5'd3;
// // #5000
// // bb_rshift = 5'd4;
// // #5000
// // bb_rshift = 5'd5;
// // #5000
// // bb_rshift = 5'd6;
// // #5000
// // bb_rshift = 5'd7;
// // #5000
// // bb_rshift = 5'd8;
// // #5000
// // bb_rshift = 5'd9;
// // #5000
// // bb_rshift = 5'd14;
// // #5000
// // bb_rshift = 5'd15;
// // #5000
// // bb_rshift = 5'd16;
// // freq_set = 32'd0;
// // func_sel = 3'b010;
// // #7777
// // freq_set = 32'd536870912;
// // func_sel = 3'b100;
// // #7777
// // freq_set = 32'd0;
// // func_sel = 3'b100;
// // #7777
// // freq_set = 32'd536870912;
// // func_sel = 3'b010;
// // #7777
// // freq_set = 32'd0;
// // func_sel = 3'b010;
// // freq_set = 32'd536870912;
// // iq_sel = 2'b00;
// // #7777
// // freq_set = 32'd536870912;
// // iq_sel = 2'b01;
// // #7777
// // freq_set = 32'd536870912;
// // iq_sel = 2'b10;
// // #7777
// // freq_set = 32'd536870912;
// // iq_sel = 2'b11;
// end
// always #5 clk = ~clk;
// // integer i;
// // integer w_file;
// // initial begin
// // w_file = $fopen("D:\\qpsk_josh.txt","w");
// // for (i = 0; i <= 35000; i = i + 1) begin
// // wait(clk);
// // #10;
// // $fdisplay(w_file,"%d %d",$signed(tx_data_i),
// // $signed(tx_data_q));
// // if (i == 35000) begin
// // $fclose(w_file);
// // $stop;
// // end
// // end
// // end
// endmodule