diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..41e2a60 --- /dev/null +++ b/.gitignore @@ -0,0 +1,20 @@ +# System generated files +# -- macOS +.DS_Store +.AppleDouble +.LSOverride +._* + +# -- Windows +Thumbs.db +ehthumbs.db +Desktop.ini + +# -- Linux +*~ + +# IDEs and editors' files +*.idea +*.vscode +*.sublime-workspace +*.sublime-project diff --git a/zc706_cx9261a_demo/system_top.xsa b/zc706_cx9261a_demo/system_top.xsa index 1a183e8..264b22d 100644 --- a/zc706_cx9261a_demo/system_top.xsa +++ b/zc706_cx9261a_demo/system_top.xsa @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:f0327732a24e8557e109ed84b77cfbd8fc15f6fe9adb6de05ba0b18f516267c2 -size 1506467 +oid sha256:d20bd5c1b8c2195a86ec9e827776b0d84627c4e71d494517a506f2a46ba2c74e +size 1404321 diff --git a/zc706_cx9261a_demo/vitis_classic_autobuild/config.json b/zc706_cx9261a_demo/vitis_classic_autobuild/config.json index 04b1c48..464c897 100644 --- a/zc706_cx9261a_demo/vitis_classic_autobuild/config.json +++ b/zc706_cx9261a_demo/vitis_classic_autobuild/config.json @@ -1,8 +1,8 @@ { "project_name": "zc706_cx9261a", - "version": "0.0.1", + "version": "0.0.2", "hw_design": "../system_top.xsa", - "hw_version": "zc706_cx9261a_demo-HW-0.0.1", + "hw_version": "zc706_cx9261a_demo-HW-0.0.2", "apps": { "zc706_cx9261a_app": { "sources": ["source_zc706_cx9261a/"], diff --git a/zc706_cx9261a_demo/vitis_classic_autobuild/source_zc706_cx9261a/config/app_config.h b/zc706_cx9261a_demo/vitis_classic_autobuild/source_zc706_cx9261a/config/app_config.h index 58767c5..597388f 100644 --- a/zc706_cx9261a_demo/vitis_classic_autobuild/source_zc706_cx9261a/config/app_config.h +++ b/zc706_cx9261a_demo/vitis_classic_autobuild/source_zc706_cx9261a/config/app_config.h @@ -48,7 +48,8 @@ #else // Zynq-7000 #define CPU_CLK_HZ XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ #define APP_TIMER_CLK_HZ (CPU_CLK_HZ / 2) -#define FCLK_CLK0_HZ 100000000 +#define FCLK_CLK0_HZ 50000000 +#define FCLK_CLK1_HZ 200000000 #endif /********* Zynq Platform Configs **********/ // APP Timer (for logging) @@ -121,7 +122,7 @@ // #define HAVE_DEBUG_MESSAGES /* For Debug purposes only */ // -- AD9361 SPI Engine Configuration #define AD9361_SPI_DEVICE_ID 0 -#define AD9361_SPI_ENGINE_REF_CLK FCLK_CLK0_HZ +#define AD9361_SPI_ENGINE_REF_CLK FCLK_CLK1_HZ #define AD9361_SPI_ENGINE_MAX_SPEED 5000000 #define AD9361_SPI_ENGINE_BASEADDR XPAR_AXI_SPI_ENGINE_AXI_SPI_ENGINE_BASEADDR #define AD9361_SPI_ENGINE_DATA_WIDTH 8 @@ -209,8 +210,8 @@ typedef enum #define CX9261A_HOP_FLAG (CX9261A_GPIO_OFFSET+15) // -- CX9261A SPI Engine Configuration #define CX9261A_SPI_DEVICE_ID 0 -#define CX9261A_SPI_ENGINE_REF_CLK FCLK_CLK0_HZ -#define CX9261A_SPI_ENGINE_MAX_SPEED 5000000 +#define CX9261A_SPI_ENGINE_REF_CLK FCLK_CLK1_HZ +#define CX9261A_SPI_ENGINE_MAX_SPEED 50000000 #define CX9261A_SPI_ENGINE_BASEADDR XPAR_AXI_SPI_ENGINE_AXI_SPI_ENGINE_BASEADDR #define CX9261A_SPI_ENGINE_DATA_WIDTH 8 #define CX9261A_SPI_ENGINE_CS_DELAY 3 @@ -227,7 +228,7 @@ typedef enum #define HMC7044_GPIO_3 (HMC7044_GPIO_OFFSET + 5) // -- HMC7044 SPI Engine Configuration #define HMC7044_SPI_DEVICE_ID 0 -#define HMC7044_SPI_ENGINE_REF_CLK FCLK_CLK0_HZ +#define HMC7044_SPI_ENGINE_REF_CLK FCLK_CLK1_HZ #define HMC7044_SPI_ENGINE_MAX_SPEED 5000000 #define HMC7044_SPI_ENGINE_BASEADDR XPAR_AXI_SPI_ENGINE_AXI_SPI_ENGINE_BASEADDR #define HMC7044_SPI_ENGINE_DATA_WIDTH 8 @@ -243,7 +244,7 @@ typedef enum #define AD9528_STATUS_1 (AD9528_GPIO_OFFSET+3) // -- AD9528 SPI Engine Configuration #define AD9528_SPI_DEVICE_ID 0 -#define AD9528_SPI_ENGINE_REF_CLK FCLK_CLK0_HZ +#define AD9528_SPI_ENGINE_REF_CLK FCLK_CLK1_HZ #define AD9528_SPI_ENGINE_MAX_SPEED 5000000 #define AD9528_SPI_ENGINE_BASEADDR XPAR_AXI_SPI_ENGINE_AXI_SPI_ENGINE_BASEADDR #define AD9528_SPI_ENGINE_DATA_WIDTH 8 @@ -255,7 +256,7 @@ typedef enum #define LMK04828_GPIO_OFFSET 54 // -- LMK04828 SPI Engine Configuration #define LMK04828_SPI_DEVICE_ID 0 -#define LMK04828_SPI_ENGINE_REF_CLK FCLK_CLK0_HZ +#define LMK04828_SPI_ENGINE_REF_CLK FCLK_CLK1_HZ #define LMK04828_SPI_ENGINE_MAX_SPEED 5000000 #define LMK04828_SPI_ENGINE_BASEADDR XPAR_AXI_SPI_ENGINE_AXI_SPI_ENGINE_BASEADDR #define LMK04828_SPI_ENGINE_DATA_WIDTH 8 @@ -267,7 +268,7 @@ typedef enum #define LMX2594_ADC_GPIO_OFFSET 54 // -- LMX2594_ADC SPI Engine Configuration #define LMX2594_ADC_SPI_DEVICE_ID 0 -#define LMX2594_ADC_SPI_ENGINE_REF_CLK FCLK_CLK0_HZ +#define LMX2594_ADC_SPI_ENGINE_REF_CLK FCLK_CLK1_HZ #define LMX2594_ADC_SPI_ENGINE_MAX_SPEED 5000000 #define LMX2594_ADC_SPI_ENGINE_BASEADDR XPAR_AXI_SPI_ENGINE_AXI_SPI_ENGINE_BASEADDR #define LMX2594_ADC_SPI_ENGINE_DATA_WIDTH 8 @@ -279,7 +280,7 @@ typedef enum #define LMX2594_DAC_GPIO_OFFSET 54 // -- LMX2594_DAC SPI Engine Configuration #define LMX2594_DAC_SPI_DEVICE_ID 0 -#define LMX2594_DAC_SPI_ENGINE_REF_CLK FCLK_CLK0_HZ +#define LMX2594_DAC_SPI_ENGINE_REF_CLK FCLK_CLK1_HZ #define LMX2594_DAC_SPI_ENGINE_MAX_SPEED 5000000 #define LMX2594_DAC_SPI_ENGINE_BASEADDR XPAR_AXI_SPI_ENGINE_AXI_SPI_ENGINE_BASEADDR #define LMX2594_DAC_SPI_ENGINE_DATA_WIDTH 8 @@ -292,7 +293,7 @@ typedef enum #define AD9653_POWR_DOWN (AD9653_GPIO_OFFSET+0) // -- AD9653 SPI Engine Configuration #define AD9653_SPI_DEVICE_ID 0 -#define AD9653_SPI_ENGINE_REF_CLK FCLK_CLK0_HZ +#define AD9653_SPI_ENGINE_REF_CLK FCLK_CLK1_HZ #define AD9653_SPI_ENGINE_MAX_SPEED 5000000 #define AD9653_SPI_ENGINE_BASEADDR XPAR_AXI_SPI_ENGINE_AXI_SPI_ENGINE_BASEADDR #define AD9653_SPI_ENGINE_DATA_WIDTH 8 @@ -304,7 +305,7 @@ typedef enum #define AD9694_GPIO_OFFSET 54 // -- AD9694 SPI Engine Configuration #define AD9694_SPI_DEVICE_ID 0 -#define AD9694_SPI_ENGINE_REF_CLK FCLK_CLK0_HZ +#define AD9694_SPI_ENGINE_REF_CLK FCLK_CLK1_HZ #define AD9694_SPI_ENGINE_MAX_SPEED 5000000 #define AD9694_SPI_ENGINE_BASEADDR XPAR_AXI_SPI_ENGINE_AXI_SPI_ENGINE_BASEADDR #define AD9694_SPI_ENGINE_DATA_WIDTH 8 diff --git a/zc706_cx9261a_demo/vitis_classic_autobuild/source_zc706_cx9261a/dev_profile/cx9261a_profile.c b/zc706_cx9261a_demo/vitis_classic_autobuild/source_zc706_cx9261a/dev_profile/cx9261a_profile.c index 3005573..86cd668 100644 --- a/zc706_cx9261a_demo/vitis_classic_autobuild/source_zc706_cx9261a/dev_profile/cx9261a_profile.c +++ b/zc706_cx9261a_demo/vitis_classic_autobuild/source_zc706_cx9261a/dev_profile/cx9261a_profile.c @@ -180,7 +180,7 @@ CX9261A_CX9261AConfiguration cx9261a_configuration = { .tx1Source = CX9261A_LOSRC_Pll1, .tx2Source = CX9261A_LOSRC_Pll2}, // 本振频率 注意：使用的所有PLL，频率必须设为正数 - .pllFreq = {.pll1Freq = 121.88, + .pllFreq = {.pll1Freq = 500, .pll2Freq = 5000, .pll3Freq = 800, .pll4Freq = 900, @@ -215,7 +215,7 @@ CX9261A_CX9261AConfiguration cx9261a_configuration = { .rx3CalibPll = CX9261A_LOSRC_Pll5, .tx1CalibPll = 0, .tx2CalibPll = 0, - .rxMethod = CX9261A_CALM_Tracking, + .rxMethod = CX9261A_CALM_TST, .txMethod = CX9261A_CALM_Bisec, .f0 = 4, // .rxMultiPoints = {2200, 2400, 2600, 2800, 3000, 3200, 3400, diff --git a/zc706_cx9261a_demo/vitis_classic_autobuild/source_zc706_cx9261a/drivers/rf-transceiver/cx9261a/cx9261a_riscv_bin.c b/zc706_cx9261a_demo/vitis_classic_autobuild/source_zc706_cx9261a/drivers/rf-transceiver/cx9261a/cx9261a_riscv_bin.c new file mode 100644 index 0000000..56a9573 --- /dev/null +++ b/zc706_cx9261a_demo/vitis_classic_autobuild/source_zc706_cx9261a/drivers/rf-transceiver/cx9261a/cx9261a_riscv_bin.c @@ -0,0 +1,5137 @@ +// Generated C code array +// Date: 2024-11-01 11:05:40 +// Source file: MultiPointsCalib_v1.8.bin + +#include +#include "cx9261adriver_c.h" + +uint32_t CX9261A_RiscvBinLen = 61516; +uint8_t *CX9261A_RiscvBin = (uint8_t[]){ + 0x6F, 0x00, 0xC0, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xA0, 0x82, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x42, 0x83, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xE0, 0x80, 0x00, 0x80, 0x14, 0x81, 0x00, 0x80, + 0x48, 0x81, 0x00, 0x80, 0x7C, 0x81, 0x00, 0x80, 0xE0, 0x81, 0x00, 0x80, + 0x40, 0x82, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x38, 0x83, 0x00, 0x80, 0x3A, 0x83, 0x00, 0x80, + 0x3C, 0x83, 0x00, 0x80, 0x3E, 0x83, 0x00, 0x80, 0x40, 0x83, 0x00, 0x80, + 0x00, 0x00, 0x00, 0x00, 0x44, 0x83, 0x00, 0x80, 0x46, 0x83, 0x00, 0x80, + 0x48, 0x83, 0x00, 0x80, 0x4A, 0x83, 0x00, 0x80, 0xAA, 0x82, 0x00, 0x80, + 0x73, 0x70, 0x04, 0x30, 0x93, 0x02, 0x00, 0x20, 0x73, 0xA0, 0x02, 0x7D, + 0x97, 0x02, 0x00, 0x00, 0x93, 0x82, 0x82, 0xF2, 0x73, 0x90, 0x72, 0x30, + 0x97, 0x82, 0x00, 0x00, 0x93, 0x82, 0x82, 0x31, 0x73, 0x90, 0xC2, 0x7E, + 0x73, 0xE0, 0xC0, 0x7E, 0x97, 0x82, 0x00, 0x00, 0x93, 0x82, 0xC2, 0x28, + 0x73, 0x90, 0x52, 0x30, 0x97, 0x11, 0x00, 0x10, 0x93, 0x81, 0x81, 0xF8, + 0x17, 0x01, 0x01, 0x10, 0x13, 0x01, 0x81, 0xEF, 0x17, 0x05, 0x00, 0x00, + 0x13, 0x05, 0x85, 0x0B, 0x97, 0x05, 0x00, 0x00, 0x93, 0x85, 0x05, 0x0B, + 0x63, 0x00, 0xB5, 0x02, 0x17, 0xE6, 0x00, 0x00, 0x13, 0x06, 0x06, 0x69, + 0x63, 0xFA, 0xC5, 0x00, 0x83, 0x22, 0x05, 0x00, 0x23, 0xA0, 0x55, 0x00, + 0x11, 0x05, 0x91, 0x05, 0xE3, 0xEA, 0xC5, 0xFE, 0x17, 0xE5, 0x00, 0x00, + 0x13, 0x05, 0x45, 0x67, 0x97, 0x05, 0x00, 0x10, 0x93, 0x85, 0x85, 0xEB, + 0x17, 0x06, 0x00, 0x10, 0x13, 0x06, 0x86, 0x74, 0x63, 0xFA, 0xC5, 0x00, + 0x83, 0x22, 0x05, 0x00, 0x23, 0xA0, 0x55, 0x00, 0x11, 0x05, 0x91, 0x05, + 0xE3, 0xEA, 0xC5, 0xFE, 0x17, 0x05, 0x00, 0x10, 0x13, 0x05, 0xC5, 0x72, + 0x93, 0x85, 0x81, 0xC7, 0x63, 0x77, 0xB5, 0x00, 0x23, 0x20, 0x05, 0x00, + 0x11, 0x05, 0xE3, 0x6D, 0xB5, 0xFE, 0x73, 0xF0, 0x02, 0x32, 0x17, 0xD5, + 0x00, 0x00, 0x13, 0x05, 0x05, 0x17, 0xEF, 0xD0, 0xA0, 0x12, 0xEF, 0xD0, + 0xE0, 0x19, 0x01, 0x45, 0x81, 0x45, 0x8D, 0x20, 0x6F, 0xD0, 0x20, 0x13, + 0x01, 0xA0, 0x73, 0xE0, 0x02, 0x32, 0x82, 0x80, 0x73, 0xF0, 0x02, 0x32, + 0x82, 0x80, 0x73, 0x70, 0x04, 0x30, 0x73, 0xE0, 0x00, 0x81, 0x73, 0x00, + 0x50, 0x10, 0x73, 0xF0, 0x00, 0x81, 0x73, 0x60, 0x04, 0x30, 0x82, 0x80, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x69, 0x73, 0x79, 0x71, + 0x9D, 0x67, 0x13, 0x03, 0x03, 0x81, 0x22, 0xD4, 0x26, 0xD2, 0x4A, 0xD0, + 0x4E, 0xCE, 0x52, 0xCC, 0x06, 0xD6, 0x13, 0x87, 0x07, 0x80, 0x1A, 0x91, + 0x0A, 0x97, 0x71, 0x7A, 0x69, 0x79, 0x3A, 0x9A, 0x13, 0x87, 0x07, 0x80, + 0x93, 0x09, 0x09, 0x80, 0x0A, 0x97, 0x37, 0x24, 0x01, 0x10, 0x85, 0x44, + 0xBA, 0x99, 0x3A, 0x99, 0x1C, 0x58, 0x09, 0x47, 0xE1, 0x83, 0x63, 0x8D, + 0x97, 0x00, 0x1C, 0x58, 0xE1, 0x83, 0x63, 0x8E, 0xE7, 0x00, 0xA1, 0x47, + 0x5C, 0xC8, 0x1C, 0x58, 0x09, 0x47, 0xE1, 0x83, 0xE3, 0x97, 0x97, 0xFE, + 0x52, 0x86, 0xCE, 0x85, 0x4A, 0x85, 0x29, 0x20, 0xE1, 0xBF, 0xEF, 0x70, + 0x10, 0x03, 0xC9, 0xBF, 0x79, 0x71, 0xB7, 0xB8, 0x00, 0x20, 0x22, 0xD6, + 0x26, 0xD4, 0x4A, 0xD2, 0x4E, 0xD0, 0x52, 0xCE, 0x56, 0xCC, 0x5A, 0xCA, + 0x5E, 0xC8, 0x62, 0xC6, 0x66, 0xC4, 0x6A, 0xC2, 0x6E, 0xC0, 0xB7, 0x27, + 0x01, 0x10, 0x05, 0x47, 0xD8, 0xCB, 0x85, 0x46, 0x37, 0x08, 0x00, 0x0F, + 0x11, 0x43, 0x37, 0x0E, 0x05, 0x10, 0x89, 0x4E, 0x8D, 0x42, 0x13, 0x89, + 0xC8, 0x12, 0x93, 0x84, 0xC8, 0x13, 0x13, 0x84, 0x48, 0x12, 0x93, 0x83, + 0x48, 0x13, 0x93, 0x8F, 0xC8, 0x15, 0x13, 0x8F, 0x08, 0x15, 0x98, 0x5B, + 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RFdc; #endif +#define MIN_FREQ 121.88 +#define MAX_FREQ 5000 +#define FREQ_SEP 200 + /*****************************************************************************/ /** * @brief Hardware_SwitchFreq @@ -330,10 +335,16 @@ int CX9261A_spiRead(int address) return reg; } +void CX9261A_udelay(double us) +{ + usleep((uint32_t)us); +} + void CX9261A_mdelay(double ms) { - mdelay((uint32_t)(ms)); + usleep((uint32_t)(ms*1000)); } + void CX9261A_setPin(int pin, int value) { switch(pin){ @@ -389,19 +400,45 @@ void CX9261A_setPin(int pin, int value) return; } -void cx9261a_trx_ch_pll_config(u8 pll_index) +void replaceBits(uint8_t *reg, unsigned int start, unsigned int end, uint8_t after) { + // 生成掩码，用于清除目标位区间 + uint8_t mask = ((1 << (start - end + 1)) - 1) << end; + + // 清除 reg 中的指定位 + *reg &= ~mask; + + // 插入 after 的对应位到目标区间 + *reg |= (after << end) & mask; +} + +int CX9261A_afcPll1_pause(double delay_us) { - u8 rx_data; - u8 recv_buf[3]={0}; - u32 trx_ch_pll_data; + CX9261A_Log("PLL1 AFC PAUSE"); + uint8_t r61D = (uint8_t)CX9261A_spiRead(0x61D); + int saved = r61D; + replaceBits(&r61D, 5, 4, 0b10); + CX9261A_spiWrite(0x61D, r61D); + CX9261A_spiWrite(0x617, 0x00); + CX9261A_spiWrite(0x617, 0x13); +// CX9261A_udelay(delay_us); + CX9261A_spiWrite(0x61D, saved); + int lock = CX9261A_spiRead(0x635); + return 0x10 & lock; +} - if(pll_index==1){ - trx_ch_pll_data = 0x00077DCF; - }else if(pll_index==2){ - trx_ch_pll_data = 0x00077D0C; - } - - cx9261a_write(cx9261a_inst,trx_ch_pll_data >> 8, trx_ch_pll_data); +int CX9261A_afcPll2_pause(double delay_us) +{ + CX9261A_Log("PLL2 AFC PAUSE"); + uint8_t r63F = (uint8_t)CX9261A_spiRead(0x63F); + int saved = r63F; + replaceBits(&r63F, 5, 4, 0b10); + CX9261A_spiWrite(0x63F, r63F); + CX9261A_spiWrite(0x639, 0x00); + CX9261A_spiWrite(0x639, 0x13); +// CX9261A_udelay(delay_us); + CX9261A_spiWrite(0x63F, saved); + int lock = CX9261A_spiRead(0x657); + return 0x10 & lock; } /*****************************************************************************/ @@ -762,6 +799,20 @@ int32_t Hardware_Init(void) /**********************************************************/ cx9261a_init(&cx9261a_inst, &cx9261a_default_init_param); + double min_freq = 3000.0; + double max_freq = 5000.0; + int cal_freq_num = 21; + double freq_sep = (max_freq-min_freq)/(cal_freq_num-1); + + for (int ii = 0; ii < cal_freq_num; ii++) + { + cx9261a_configuration.calib.rxMultiPoints[ii] = min_freq + ii*freq_sep; + cx9261a_configuration.calib.txMultiPoints[ii] = min_freq + ii*freq_sep; + } + + cx9261a_configuration.calib.numRxPoint = cal_freq_num; + cx9261a_configuration.calib.numTxPoint = cal_freq_num; + // 绑定函数 CX9261A_setLoggingFunc(CX9261A_Log); CX9261A_setWriteSpiFunc(CX9261A_spiWrite); @@ -771,8 +822,6 @@ int32_t Hardware_Init(void) // 开始配置芯片 CX9261A_initialChip(); // 最开始需要调用此函数 - int reg; - reg = CX9261A_spiRead(0x000); CX9261A_initialPowerConfig(&cx9261a_configuration); // 配置温补 CX9261A_configTemperatureCompensation(cx9261a_configuration.tempComp); @@ -825,77 +874,143 @@ int32_t Hardware_Init(void) CX9261A_configADCCalib(cx9261a_configuration.clock.adc); CX9261A_configFlashCalib(); CX9261A_configDcCalib(&(cx9261a_configuration.calib)); -// CX9261A_configQecCalib(&cx9261a_configuration); + CX9261A_configQecCalib(&cx9261a_configuration); // CX9261A_loadRxCalibPredis(0, CX9261A_RXCH_Rx1, CX9261A_LOSRC_Pll1); // CX9261A_loadRxCalibPredis(0, CX9261A_RXCH_Rx2, CX9261A_LOSRC_Pll1); // 切换到工作模式 CX9261A_configPowerMode(cx9261a_configuration.powerManagement.powerMode); + + + int reg; + CX9261A_spiWrite(0x02E,0x03); + reg = CX9261A_spiRead(0x0AB); + CX9261A_spiWrite(0x02E,0x06); // 跳频 uint8_t hop_flag = 0; uint8_t hop_flag_new = 0; - double hop_freq; -// while (true) +// int hop_freq_num = 3*floor((cal_freq_num-1)/2); // 切换顺序为 0, 1, 2, 0, 3, 4, 0, 5, 6 ... +// double hop_freq[hop_freq_num]; +// int next_pll_index = 1; +// double curr_freq; +// int freq_index = 0; +// +// for (int ii = 0; ii < hop_freq_num/3; ii++) // { -// gpio_get_value(cx9261a_inst->gpio_desc_hop_flag, &hop_flag_new); -// if (hop_flag != hop_flag_new) -// { -// hop_flag = hop_flag_new; -// -// double hop_freq; -// double hop_freq1 = 800.25; -// int pll_index=1; -// int unlock_pll1_cnt=0,unlock_pll2_cnt=0; -// -// hop_freq = (rand()%(800-30))+30+(rand()%(101))/(double)100; -// -// if(hop_freq == hop_freq1){ -// if(pll_index == 2){ -// pll_index = 4; -// } -// else if(pll_index == 1){ -// pll_index = 3; -// } -// } -// -// if(hop_flag_new == 1) -// { -// if(pll_index == 1 || pll_index == 3) -// { -// //切换至pll2来源 -// cx9261a_trx_ch_pll_config(2); -// //配置pll1参数 -// CX9261A_configPll1(hop_freq,&(cx9261a_configuration.clock)); -// // unlock_pll1_cnt=PLL_config(1,hop_freq,ref)-1; -// while (!CX9261A_afcPll1()) { -// unlock_pll1_cnt++; -// } -// pll_index = 2; -// } -// else if(pll_index == 2 || pll_index == 4) -// { -// //切换至pll1来源 -// cx9261a_trx_ch_pll_config(1); -// //配置pll2参数 -// CX9261A_configPll2(hop_freq,&(cx9261a_configuration.clock)); -// // unlock_pll2_cnt=PLL_config(2,hop_freq,ref)-1; -// while (!CX9261A_afcPll2()) { -// unlock_pll2_cnt++; -// } -// pll_index = 1; -// } -// } -// hop_freq1 = hop_freq; -// if(unlock_pll2_cnt!=0 || unlock_pll1_cnt !=0){ -// DBG_ERROR("pll1 unlock num: %d; pll2 unlock num: %d;.\n", unlock_pll1_cnt, unlock_pll2_cnt); -// } -// } +// hop_freq[3*ii] = cx9261a_configuration.calib.rxMultiPoints[0]; +// hop_freq[3*ii+1] = cx9261a_configuration.calib.rxMultiPoints[2*ii+1]; +// hop_freq[3*ii+2] = cx9261a_configuration.calib.rxMultiPoints[2*ii+2]; // } +// +// if (hop_freq[freq_index] != cx9261a_configuration.pllFreq.pll1Freq) +// { +// curr_freq = hop_freq[freq_index]; +// +// CX9261A_configPllSource(&(cx9261a_configuration.pllSource)); +// CX9261A_configPll1(hop_freq[freq_index], &(cx9261a_configuration.clock)); +// CX9261A_afcPll1_pause(25); +// // set pll1 as default +// cx9261a_configuration.pllSource.rx1Source = CX9261A_LOSRC_Pll1; +// cx9261a_configuration.pllSource.tx1Source = CX9261A_LOSRC_Pll1; +// // // prepare next pll +// CX9261A_configPll2(hop_freq[freq_index+1], &(cx9261a_configuration.clock)); +// CX9261A_afcPll2_pause(25); +// // index update +// next_pll_index = 2; +// } + + static int hop_cnt = 0; + static int next_pll_index = 2; + static double curr_freq; + static double next_freq = MIN_FREQ; + + + while (true) + { + gpio_get_value(cx9261a_inst->gpio_desc_hop_flag, &hop_flag_new); + if (hop_flag != hop_flag_new) + { + hop_flag = hop_flag_new; + + // 1st demo of frequency hopping + int unlock_pll1_cnt = 0, unlock_pll2_cnt = 0; + curr_freq = next_freq; + hop_cnt++; + if (hop_cnt % 3 == 2) + { + next_freq = MIN_FREQ; + } + else + { + next_freq = (curr_freq + FREQ_SEP > MAX_FREQ) ? MIN_FREQ : curr_freq + FREQ_SEP; + } + + if (next_pll_index == 2) + { + // switch pll + CX9261A_spiWrite(0x77D,0x0C); + // prepare next pll + CX9261A_configPll1(next_freq, &(cx9261a_configuration.clock)); + while (!CX9261A_afcPll1_pause(20)) + { + unlock_pll1_cnt++; + } + // index update + next_pll_index = 1; + } + else + { + // switch pll + CX9261A_spiWrite(0x77D,0xCF); + // prepare next pll + CX9261A_configPll2(next_freq, &(cx9261a_configuration.clock)); + while (!CX9261A_afcPll2_pause(20)) + { + unlock_pll2_cnt++; + } + // index update + next_pll_index = 2; + } + if(unlock_pll2_cnt!=0 || unlock_pll1_cnt !=0){ + xil_printf("pll1 unlock num: %d; pll2 unlock num: %d;.\n", unlock_pll1_cnt, unlock_pll2_cnt); + } + + // 2nd demo of frequency hopping +// curr_freq = hop_freq[freq_index]; +// hop_flag = hop_flag_new; +// freq_index = (freq_index == hop_freq_num - 1) ? 0 : freq_index + 1; +// +// if (next_pll_index == 2) +// { +// // switch pll +//// cx9261a_configuration.pllSource.rx1Source = CX9261A_LOSRC_Pll2; +//// cx9261a_configuration.pllSource.tx1Source = CX9261A_LOSRC_Pll2; +//// CX9261A_configPllSource(&(cx9261a_configuration.pllSource)); +// CX9261A_spiWrite(0x77D,0x0C); +// // prepare next pll +// CX9261A_configPll1(hop_freq[freq_index], &(cx9261a_configuration.clock)); +// CX9261A_afcPll1_pause(25); +// // index update +// next_pll_index = 1; +// } +// else if (next_pll_index == 1) +// { +// // switch pll +//// cx9261a_configuration.pllSource.rx1Source = CX9261A_LOSRC_Pll1; +//// cx9261a_configuration.pllSource.tx1Source = CX9261A_LOSRC_Pll1; +//// CX9261A_configPllSource(&(cx9261a_configuration.pllSource)); +// CX9261A_spiWrite(0x77D,0xCF); +// // prepare next pll +// CX9261A_configPll2(hop_freq[freq_index], &(cx9261a_configuration.clock)); +// CX9261A_afcPll2_pause(25); +// // index update +// next_pll_index = 2; +// } + } + } #endif DBG_INFO("HDWR: configuration Done.\n"); return SUCCESS; } - - diff --git a/zc706_cx9261a_demo/vitis_classic_autobuild/source_zc706_cx9261a/include/common.h b/zc706_cx9261a_demo/vitis_classic_autobuild/source_zc706_cx9261a/include/common.h index c13de59..1421565 100644 --- a/zc706_cx9261a_demo/vitis_classic_autobuild/source_zc706_cx9261a/include/common.h +++ b/zc706_cx9261a_demo/vitis_classic_autobuild/source_zc706_cx9261a/include/common.h @@ -90,4 +90,4 @@ void AppAssert(const char *file, int line); #endif /* __COMMON_H_ */ -/** @} */ \ No newline at end of file +/** @} */ diff --git a/zc706_cx9261a_demo/zc706_cx9261a_demo.runs/impl_1/debug_nets.ltx b/zc706_cx9261a_demo/zc706_cx9261a_demo.runs/impl_1/debug_nets.ltx index 0ab1774..7390584 100644 --- a/zc706_cx9261a_demo/zc706_cx9261a_demo.runs/impl_1/debug_nets.ltx +++ b/zc706_cx9261a_demo/zc706_cx9261a_demo.runs/impl_1/debug_nets.ltx @@ -2094,7 +2094,7 @@ }, { "type": "ILA_V3", - "name": "u_ila_rx_fb", + "name": "system_bd/system_bd_i/system_ila_spi/inst/ila_lib", "spec": "labtools_ila_v6", "ipName": "ila", "core_location": { @@ -2102,7 +2102,7 @@ "slave_index": 3, "bscan_switch_index": 0 }, - "uuid": "288E890F004257D1882FBD4163CBA7AE", + "uuid": "46132012EA8358B6910BA2E27E723A16", "pins": [ { "name": "probe0", @@ -2115,7 +2115,7 @@ "portIndex": 0, "nets": [ { - "name": "data_valid3", + "name": "system_bd/system_bd_i/system_ila_spi/inst/probe0_1", "isBus": false } ] @@ -2125,64 +2125,14 @@ "id": 68, "type": "DATA_TRIGGER", "direction": "IN", - "isVector": true, + "isVector": false, "leftIndex": 0, - "rightIndex": 15, + "rightIndex": 0, "portIndex": 1, "nets": [ { - "name": "rx3_data_i", - "isBus": true, - "subnets": [ - { - "name": "rx3_data_i[15]" - }, - { - "name": "rx3_data_i[14]" - }, - { - "name": "rx3_data_i[13]" - }, - { - "name": "rx3_data_i[12]" - }, - { - "name": "rx3_data_i[11]" - }, - { - "name": "rx3_data_i[10]" - }, - { - "name": "rx3_data_i[9]" - }, - { - "name": "rx3_data_i[8]" - }, - { - "name": "rx3_data_i[7]" - }, - { - "name": "rx3_data_i[6]" - }, - { - "name": "rx3_data_i[5]" - }, - { - "name": "rx3_data_i[4]" - }, - { - "name": "rx3_data_i[3]" - }, - { - "name": "rx3_data_i[2]" - }, - { - "name": "rx3_data_i[1]" - }, - { - "name": "rx3_data_i[0]" - } - ] + "name": "system_bd/system_bd_i/system_ila_spi/inst/SLOT_0_SPI_ENGINE_sclk_1", + "isBus": false } ] }, @@ -2191,64 +2141,159 @@ "id": 69, "type": "DATA_TRIGGER", "direction": "IN", - "isVector": true, + "isVector": false, "leftIndex": 0, - "rightIndex": 15, + "rightIndex": 0, "portIndex": 2, "nets": [ { - "name": "rx3_data_q", - "isBus": true, - "subnets": [ - { - "name": "rx3_data_q[15]" - }, - { - "name": "rx3_data_q[14]" - }, - { - "name": "rx3_data_q[13]" - }, - { - "name": "rx3_data_q[12]" - }, - { - "name": "rx3_data_q[11]" - }, - { - "name": "rx3_data_q[10]" - }, - { - "name": "rx3_data_q[9]" - }, - { - "name": "rx3_data_q[8]" - }, - { - "name": "rx3_data_q[7]" - }, - { - "name": "rx3_data_q[6]" - }, - { - "name": "rx3_data_q[5]" - }, - { - "name": "rx3_data_q[4]" - }, - { - "name": "rx3_data_q[3]" - }, - { - "name": "rx3_data_q[2]" - }, - { - "name": "rx3_data_q[1]" - }, - { - "name": "rx3_data_q[0]" - } - ] + "name": "system_bd/system_bd_i/system_ila_spi/inst/SLOT_0_SPI_ENGINE_sdi_1", + "isBus": false + } + ] + }, + { + "name": "probe3", + "id": 70, + "type": "DATA_TRIGGER", + "direction": "IN", + "isVector": false, + "leftIndex": 0, + "rightIndex": 0, + "portIndex": 3, + "nets": [ + { + "name": "system_bd/system_bd_i/system_ila_spi/inst/SLOT_0_SPI_ENGINE_sdo_1", + "isBus": false + } + ] + }, + { + "name": "probe4", + "id": 71, + "type": "DATA_TRIGGER", + "direction": "IN", + "isVector": false, + "leftIndex": 0, + "rightIndex": 0, + "portIndex": 4, + "nets": [ + { + "name": "system_bd/system_bd_i/system_ila_spi/inst/SLOT_0_SPI_ENGINE_sdo_t_1", + "isBus": false + } + ] + }, + { + "name": "probe5", + "id": 72, + "type": "DATA_TRIGGER", + "direction": "IN", + "isVector": false, + "leftIndex": 0, + "rightIndex": 0, + "portIndex": 5, + "nets": [ + { + "name": "system_bd/system_bd_i/system_ila_spi/inst/SLOT_0_SPI_ENGINE_three_wire_1", + "isBus": false + } + ] + }, + { + "name": "probe6", + "id": 73, + "type": "DATA_TRIGGER", + "direction": "IN", + "isVector": false, + "leftIndex": 0, + "rightIndex": 0, + "portIndex": 6, + "nets": [ + { + "name": "system_bd/system_bd_i/system_ila_spi/inst/SLOT_0_SPI_ENGINE_cs_1", + "isBus": false + } + ] + } + ], + "bus_interfaces": [ + { + "name": "SLOT_0_SPI_ENGINE", + "vlnv": "analog.com:interface:spi_engine:1.0", + "connectedBus": "axi_spi_engine_spi", + "port_maps": [ + { + "logical_port": "cs", + "physical_pin": { + "id": 73, + "name": "probe6", + "leftBit": 0, + "width": 1 + } + }, + { + "logical_port": "sclk", + "physical_pin": { + "id": 68, + "name": "probe1", + "leftBit": 0, + "width": 1 + } + }, + { + "logical_port": "sdi", + "physical_pin": { + "id": 69, + "name": "probe2", + "leftBit": 0, + "width": 1 + } + }, + { + "logical_port": "sdo", + "physical_pin": { + "id": 70, + "name": "probe3", + "leftBit": 0, + "width": 1 + } + }, + { + "logical_port": "sdo_t", + "physical_pin": { + "id": 71, + "name": "probe4", + "leftBit": 0, + "width": 1 + } + }, + { + "logical_port": "three_wire", + "physical_pin": { + "id": 72, + "name": "probe5", + "leftBit": 0, + "width": 1 + } + } + ] + } + ], + "native_ports": [ + { + "name": "probe0", + "connectedBus": "axi_spi_engine_active", + "protocol": "PROBE", + "port_maps": [ + { + "logical_port": "probe0", + "physical_pin": { + "id": 67, + "name": "probe0", + "leftBit": 0, + "width": 1 + } } ] } @@ -2256,7 +2301,7 @@ }, { "type": "ILA_V3", - "name": "u_ila_trx1", + "name": "u_ila_trx", "spec": "labtools_ila_v6", "ipName": "ila", "core_location": { @@ -2264,11 +2309,11 @@ "slave_index": 4, "bscan_switch_index": 0 }, - "uuid": "4B0648EEAA8657BE89CDBEAA67057D4B", + "uuid": "B4AD3E48EFE85668933E662B3D102FF2", "pins": [ { "name": "probe0", - "id": 70, + "id": 74, "type": "DATA_TRIGGER", "direction": "IN", "isVector": false, @@ -2277,20 +2322,152 @@ "portIndex": 0, "nets": [ { - "name": "data_valid", + "name": "hop_flag", "isBus": false } ] }, { "name": "probe1", - "id": 71, + "id": 75, "type": "DATA_TRIGGER", "direction": "IN", "isVector": true, "leftIndex": 0, "rightIndex": 15, "portIndex": 1, + "nets": [ + { + "name": "tx_data_i", + "isBus": true, + "subnets": [ + { + "name": "tx_data_i[15]" + }, + { + "name": "tx_data_i[14]" + }, + { + "name": "tx_data_i[13]" + }, + { + "name": "tx_data_i[12]" + }, + { + "name": "tx_data_i[11]" + }, + { + "name": "tx_data_i[10]" + }, + { + "name": "tx_data_i[9]" + }, + { + "name": "tx_data_i[8]" + }, + { + "name": "tx_data_i[7]" + }, + { + "name": "tx_data_i[6]" + }, + { + "name": "tx_data_i[5]" + }, + { + "name": "tx_data_i[4]" + }, + { + "name": "tx_data_i[3]" + }, + { + "name": "tx_data_i[2]" + }, + { + "name": "tx_data_i[1]" + }, + { + "name": "tx_data_i[0]" + } + ] + } + ] + }, + { + "name": "probe2", + "id": 76, + "type": "DATA_TRIGGER", + "direction": "IN", + "isVector": true, + "leftIndex": 0, + "rightIndex": 15, + "portIndex": 2, + "nets": [ + { + "name": "tx_data_q", + "isBus": true, + "subnets": [ + { + "name": "tx_data_q[15]" + }, + { + "name": "tx_data_q[14]" + }, + { + "name": "tx_data_q[13]" + }, + { + "name": "tx_data_q[12]" + }, + { + "name": "tx_data_q[11]" + }, + { + "name": "tx_data_q[10]" + }, + { + "name": "tx_data_q[9]" + }, + { + "name": "tx_data_q[8]" + }, + { + "name": "tx_data_q[7]" + }, + { + "name": "tx_data_q[6]" + }, + { + "name": "tx_data_q[5]" + }, + { + "name": "tx_data_q[4]" + }, + { + "name": "tx_data_q[3]" + }, + { + "name": "tx_data_q[2]" + }, + { + "name": "tx_data_q[1]" + }, + { + "name": "tx_data_q[0]" + } + ] + } + ] + }, + { + "name": "probe3", + "id": 77, + "type": "DATA_TRIGGER", + "direction": "IN", + "isVector": true, + "leftIndex": 0, + "rightIndex": 15, + "portIndex": 3, "nets": [ { "name": "rx1_data_i", @@ -2349,14 +2526,14 @@ ] }, { - "name": "probe2", - "id": 72, + "name": "probe4", + "id": 78, "type": "DATA_TRIGGER", "direction": "IN", "isVector": true, "leftIndex": 0, "rightIndex": 15, - "portIndex": 2, + "portIndex": 4, "nets": [ { "name": "rx1_data_q", @@ -2414,209 +2591,15 @@ } ] }, - { - "name": "probe3", - "id": 73, - "type": "DATA_TRIGGER", - "direction": "IN", - "isVector": false, - "leftIndex": 0, - "rightIndex": 0, - "portIndex": 3, - "nets": [ - { - "name": "tx_data_ready", - "isBus": false - } - ] - }, - { - "name": "probe4", - "id": 74, - "type": "DATA_TRIGGER", - "direction": "IN", - "isVector": true, - "leftIndex": 0, - "rightIndex": 15, - "portIndex": 4, - "nets": [ - { - "name": "tx1_data_i", - "isBus": true, - "subnets": [ - { - "name": "tx1_data_i[15]" - }, - { - "name": "tx1_data_i[14]" - }, - { - "name": "tx1_data_i[13]" - }, - { - "name": "tx1_data_i[12]" - }, - { - "name": "tx1_data_i[11]" - }, - { - "name": "tx1_data_i[10]" - }, - { - "name": "tx1_data_i[9]" - }, - { - "name": "tx1_data_i[8]" - }, - { - "name": "tx1_data_i[7]" - }, - { - "name": "tx1_data_i[6]" - }, - { - "name": "tx1_data_i[5]" - }, - { - "name": "tx1_data_i[4]" - }, - { - "name": "tx1_data_i[3]" - }, - { - "name": "tx1_data_i[2]" - }, - { - "name": "tx1_data_i[1]" - }, - { - "name": "tx1_data_i[0]" - } - ] - } - ] - }, { "name": "probe5", - "id": 75, + "id": 79, "type": "DATA_TRIGGER", "direction": "IN", "isVector": true, "leftIndex": 0, "rightIndex": 15, "portIndex": 5, - "nets": [ - { - "name": "tx1_data_q", - "isBus": true, - "subnets": [ - { - "name": "tx1_data_q[15]" - }, - { - "name": "tx1_data_q[14]" - }, - { - "name": "tx1_data_q[13]" - }, - { - "name": "tx1_data_q[12]" - }, - { - "name": "tx1_data_q[11]" - }, - { - "name": "tx1_data_q[10]" - }, - { - "name": "tx1_data_q[9]" - }, - { - "name": "tx1_data_q[8]" - }, - { - "name": "tx1_data_q[7]" - }, - { - "name": "tx1_data_q[6]" - }, - { - "name": "tx1_data_q[5]" - }, - { - "name": "tx1_data_q[4]" - }, - { - "name": "tx1_data_q[3]" - }, - { - "name": "tx1_data_q[2]" - }, - { - "name": "tx1_data_q[1]" - }, - { - "name": "tx1_data_q[0]" - } - ] - } - ] - }, - { - "name": "probe6", - "id": 76, - "type": "DATA_TRIGGER", - "direction": "IN", - "isVector": false, - "leftIndex": 0, - "rightIndex": 0, - "portIndex": 6, - "nets": [ - { - "name": "hop_flag_1", - "isBus": false - } - ] - } - ] - }, - { - "type": "ILA_V3", - "name": "u_ila_trx2", - "spec": "labtools_ila_v6", - "ipName": "ila", - "core_location": { - "user_chain": 1, - "slave_index": 5, - "bscan_switch_index": 0 - }, - "uuid": "DB81E20588845620929226B20A3B4A70", - "pins": [ - { - "name": "probe0", - "id": 77, - "type": "DATA_TRIGGER", - "direction": "IN", - "isVector": false, - "leftIndex": 0, - "rightIndex": 0, - "portIndex": 0, - "nets": [ - { - "name": "data_valid2", - "isBus": false - } - ] - }, - { - "name": "probe1", - "id": 78, - "type": "DATA_TRIGGER", - "direction": "IN", - "isVector": true, - "leftIndex": 0, - "rightIndex": 15, - "portIndex": 1, "nets": [ { "name": "rx2_data_i", @@ -2675,14 +2658,14 @@ ] }, { - "name": "probe2", - "id": 79, + "name": "probe6", + "id": 80, "type": "DATA_TRIGGER", "direction": "IN", "isVector": true, "leftIndex": 0, "rightIndex": 15, - "portIndex": 2, + "portIndex": 6, "nets": [ { "name": "rx2_data_q", @@ -2739,170 +2722,6 @@ ] } ] - }, - { - "name": "probe3", - "id": 80, - "type": "DATA_TRIGGER", - "direction": "IN", - "isVector": false, - "leftIndex": 0, - "rightIndex": 0, - "portIndex": 3, - "nets": [ - { - "name": "tx_data_ready2", - "isBus": false - } - ] - }, - { - "name": "probe4", - "id": 81, - "type": "DATA_TRIGGER", - "direction": "IN", - "isVector": true, - "leftIndex": 0, - "rightIndex": 15, - "portIndex": 4, - "nets": [ - { - "name": "tx2_data_i", - "isBus": true, - "subnets": [ - { - "name": "tx2_data_i[15]" - }, - { - "name": "tx2_data_i[14]" - }, - { - "name": "tx2_data_i[13]" - }, - { - "name": "tx2_data_i[12]" - }, - { - "name": "tx2_data_i[11]" - }, - { - "name": "tx2_data_i[10]" - }, - { - "name": "tx2_data_i[9]" - }, - { - "name": "tx2_data_i[8]" - }, - { - "name": "tx2_data_i[7]" - }, - { - "name": "tx2_data_i[6]" - }, - { - "name": "tx2_data_i[5]" - }, - { - "name": "tx2_data_i[4]" - }, - { - "name": "tx2_data_i[3]" - }, - { - "name": "tx2_data_i[2]" - }, - { - "name": "tx2_data_i[1]" - }, - { - "name": "tx2_data_i[0]" - } - ] - } - ] - }, - { - "name": "probe5", - "id": 82, - "type": "DATA_TRIGGER", - "direction": "IN", - "isVector": true, - "leftIndex": 0, - "rightIndex": 15, - "portIndex": 5, - "nets": [ - { - "name": "tx2_data_q", - "isBus": true, - "subnets": [ - { - "name": "tx2_data_q[15]" - }, - { - "name": "tx2_data_q[14]" - }, - { - "name": "tx2_data_q[13]" - }, - { - "name": "tx2_data_q[12]" - }, - { - "name": "tx2_data_q[11]" - }, - { - "name": "tx2_data_q[10]" - }, - { - "name": "tx2_data_q[9]" - }, - { - "name": "tx2_data_q[8]" - }, - { - "name": "tx2_data_q[7]" - }, - { - "name": "tx2_data_q[6]" - }, - { - "name": "tx2_data_q[5]" - }, - { - "name": "tx2_data_q[4]" - }, - { - "name": "tx2_data_q[3]" - }, - { - "name": "tx2_data_q[2]" - }, - { - "name": "tx2_data_q[1]" - }, - { - "name": "tx2_data_q[0]" - } - ] - } - ] - }, - { - "name": "probe6", - "id": 83, - "type": "DATA_TRIGGER", - "direction": "IN", - "isVector": false, - "leftIndex": 0, - "rightIndex": 0, - "portIndex": 6, - "nets": [ - { - "name": "hop_flag", - "isBus": false - } - ] } ] }, @@ -2913,14 +2732,14 @@ "ipName": "vio", "core_location": { "user_chain": 1, - "slave_index": 6, + "slave_index": 5, "bscan_switch_index": 0 }, "uuid": "2DE1225B64E851E3B916B773749A598D", "pins": [ { "name": "probe_in0", - "id": 84, + "id": 81, "type": "DATA", "direction": "IN", "isVector": true, @@ -2953,7 +2772,7 @@ }, { "name": "probe_in1", - "id": 85, + "id": 82, "type": "DATA", "direction": "IN", "isVector": true, @@ -2986,7 +2805,7 @@ }, { "name": "probe_in2", - "id": 86, + "id": 83, "type": "DATA", "direction": "IN", "isVector": true, @@ -3019,7 +2838,7 @@ }, { "name": "probe_out0", - "id": 87, + "id": 84, "type": "DATA", "direction": "OUT", "isVector": true, @@ -3052,7 +2871,7 @@ }, { "name": "probe_out1", - "id": 88, + "id": 85, "type": "DATA", "direction": "OUT", "isVector": true, @@ -3085,7 +2904,7 @@ }, { "name": "probe_out2", - "id": 89, + "id": 86, "type": "DATA", "direction": "OUT", "isVector": true, @@ -3125,14 +2944,14 @@ "ipName": "vio", "core_location": { "user_chain": 1, - "slave_index": 7, + "slave_index": 6, "bscan_switch_index": 0 }, "uuid": "60CCCABCFDF559B38DD38C5105157D2D", "pins": [ { "name": "probe_out0", - "id": 90, + "id": 87, "type": "DATA", "direction": "OUT", "isVector": true, @@ -3246,7 +3065,7 @@ }, { "name": "probe_out1", - "id": 91, + "id": 88, "type": "DATA", "direction": "OUT", "isVector": false, @@ -3262,7 +3081,7 @@ }, { "name": "probe_out2", - "id": 92, + "id": 89, "type": "DATA", "direction": "OUT", "isVector": false, @@ -3280,441 +3099,219 @@ }, { "type": "VIO_V2", - "name": "u_vio_manual_ctrl_1", + "name": "u_vio_manual_ctrl", "spec": "labtools_vio_v3", "ipName": "vio", "core_location": { "user_chain": 1, - "slave_index": 8, + "slave_index": 7, "bscan_switch_index": 0 }, - "uuid": "3A4AD62DDC3A546EB5F2A986B350E154", + "uuid": "6DFBBD640CB857419C054C66C7EA7B27", "pins": [ { "name": "probe_out0", + "id": 90, + "type": "DATA", + "direction": "OUT", + "isVector": true, + "leftIndex": 0, + "rightIndex": 1, + "portIndex": 0, + "nets": [ + { + "name": "waveform_sel", + "isBus": true, + "subnets": [ + { + "name": "waveform_sel[1]" + }, + { + "name": "waveform_sel[0]" + } + ] + } + ] + }, + { + "name": "probe_out1", + "id": 91, + "type": "DATA", + "direction": "OUT", + "isVector": false, + "leftIndex": 0, + "rightIndex": 0, + "portIndex": 1, + "nets": [ + { + "name": "sweep_on", + "isBus": false + } + ] + }, + { + "name": "probe_out2", + "id": 92, + "type": "DATA", + "direction": "OUT", + "isVector": true, + "leftIndex": 0, + "rightIndex": 31, + "portIndex": 2, + "nets": [ + { + "name": "freq_set", + "isBus": true, + "subnets": [ + { + "name": "freq_set[31]" + }, + { + "name": "freq_set[30]" + }, + { + "name": "freq_set[29]" + }, + { + "name": "freq_set[28]" + }, + { + "name": "freq_set[27]" + }, + { + "name": "freq_set[26]" + }, + { + "name": "freq_set[25]" + }, + { + "name": "freq_set[24]" + }, + { + "name": "freq_set[23]" + }, + { + "name": "freq_set[22]" + }, + { + "name": "freq_set[21]" + }, + { + "name": "freq_set[20]" + }, + { + "name": "freq_set[19]" + }, + { + "name": "freq_set[18]" + }, + { + "name": "freq_set[17]" + }, + { + "name": "freq_set[16]" + }, + { + "name": "freq_set[15]" + }, + { + "name": "freq_set[14]" + }, + { + "name": "freq_set[13]" + }, + { + "name": "freq_set[12]" + }, + { + "name": "freq_set[11]" + }, + { + "name": "freq_set[10]" + }, + { + "name": "freq_set[9]" + }, + { + "name": "freq_set[8]" + }, + { + "name": "freq_set[7]" + }, + { + "name": "freq_set[6]" + }, + { + "name": "freq_set[5]" + }, + { + "name": "freq_set[4]" + }, + { + "name": "freq_set[3]" + }, + { + "name": "freq_set[2]" + }, + { + "name": "freq_set[1]" + }, + { + "name": "freq_set[0]" + } + ] + } + ] + }, + { + "name": "probe_out3", "id": 93, "type": "DATA", "direction": "OUT", "isVector": true, "leftIndex": 0, "rightIndex": 1, - "portIndex": 0, + "portIndex": 3, "nets": [ { - "name": "waveform_sel_1", + "name": "iq_sel", "isBus": true, "subnets": [ { - "name": "waveform_sel_1[1]" + "name": "iq_sel[1]" }, { - "name": "waveform_sel_1[0]" + "name": "iq_sel[0]" } ] } ] }, { - "name": "probe_out1", + "name": "probe_out4", "id": 94, "type": "DATA", "direction": "OUT", - "isVector": false, - "leftIndex": 0, - "rightIndex": 0, - "portIndex": 1, - "nets": [ - { - "name": "sweep_on_1", - "isBus": false - } - ] - }, - { - "name": "probe_out2", - "id": 95, - "type": "DATA", - "direction": "OUT", - "isVector": true, - "leftIndex": 0, - "rightIndex": 31, - "portIndex": 2, - "nets": [ - { - "name": "freq_set_1", - "isBus": true, - "subnets": [ - { - "name": "freq_set_1[31]" - }, - { - "name": "freq_set_1[30]" - }, - { - "name": "freq_set_1[29]" - }, - { - "name": "freq_set_1[28]" - }, - { - "name": "freq_set_1[27]" - }, - { - "name": "freq_set_1[26]" - }, - { - "name": "freq_set_1[25]" - }, - { - "name": "freq_set_1[24]" - }, - { - "name": "freq_set_1[23]" - }, - { - "name": "freq_set_1[22]" - }, - { - "name": "freq_set_1[21]" - }, - { - "name": "freq_set_1[20]" - }, - { - "name": "freq_set_1[19]" - }, - { - "name": "freq_set_1[18]" - }, - { - "name": "freq_set_1[17]" - }, - { - "name": "freq_set_1[16]" - }, - { - "name": "freq_set_1[15]" - }, - { - "name": "freq_set_1[14]" - }, - { - "name": "freq_set_1[13]" - }, - { - "name": "freq_set_1[12]" - }, - { - "name": "freq_set_1[11]" - }, - { - "name": "freq_set_1[10]" - }, - { - "name": "freq_set_1[9]" - }, - { - "name": "freq_set_1[8]" - }, - { - "name": "freq_set_1[7]" - }, - { - "name": "freq_set_1[6]" - }, - { - "name": "freq_set_1[5]" - }, - { - "name": "freq_set_1[4]" - }, - { - "name": "freq_set_1[3]" - }, - { - "name": "freq_set_1[2]" - }, - { - "name": "freq_set_1[1]" - }, - { - "name": "freq_set_1[0]" - } - ] - } - ] - }, - { - "name": "probe_out3", - "id": 96, - "type": "DATA", - "direction": "OUT", - "isVector": true, - "leftIndex": 0, - "rightIndex": 1, - "portIndex": 3, - "nets": [ - { - "name": "iq_sel_1", - "isBus": true, - "subnets": [ - { - "name": "iq_sel_1[1]" - }, - { - "name": "iq_sel_1[0]" - } - ] - } - ] - }, - { - "name": "probe_out4", - "id": 97, - "type": "DATA", - "direction": "OUT", "isVector": true, "leftIndex": 0, "rightIndex": 3, "portIndex": 4, "nets": [ { - "name": "bb_rshift_1", + "name": "bb_rshift", "isBus": true, "subnets": [ { - "name": "bb_rshift_1[3]" + "name": "bb_rshift[3]" }, { - "name": "bb_rshift_1[2]" + "name": "bb_rshift[2]" }, { - "name": "bb_rshift_1[1]" + "name": "bb_rshift[1]" }, { - "name": "bb_rshift_1[0]" - } - ] - } - ] - } - ] - }, - { - "type": "VIO_V2", - "name": "u_vio_manual_ctrl_2", - "spec": "labtools_vio_v3", - "ipName": "vio", - "core_location": { - "user_chain": 1, - "slave_index": 9, - "bscan_switch_index": 0 - }, - "uuid": "09D2047C4D375ED8AEA61ABD4F4AF334", - "pins": [ - { - "name": "probe_out0", - "id": 98, - "type": "DATA", - "direction": "OUT", - "isVector": true, - "leftIndex": 0, - "rightIndex": 1, - "portIndex": 0, - "nets": [ - { - "name": "waveform_sel_2", - "isBus": true, - "subnets": [ - { - "name": "waveform_sel_2[1]" - }, - { - "name": "waveform_sel_2[0]" - } - ] - } - ] - }, - { - "name": "probe_out1", - "id": 99, - "type": "DATA", - "direction": "OUT", - "isVector": false, - "leftIndex": 0, - "rightIndex": 0, - "portIndex": 1, - "nets": [ - { - "name": "sweep_on_2", - "isBus": false - } - ] - }, - { - "name": "probe_out2", - "id": 100, - "type": "DATA", - "direction": "OUT", - "isVector": true, - "leftIndex": 0, - "rightIndex": 31, - "portIndex": 2, - "nets": [ - { - "name": "freq_set_2", - "isBus": true, - "subnets": [ - { - "name": "freq_set_2[31]" - }, - { - "name": "freq_set_2[30]" - }, - { - "name": "freq_set_2[29]" - }, - { - "name": "freq_set_2[28]" - }, - { - "name": "freq_set_2[27]" - }, - { - "name": "freq_set_2[26]" - }, - { - "name": "freq_set_2[25]" - }, - { - "name": "freq_set_2[24]" - }, - { - "name": "freq_set_2[23]" - }, - { - "name": "freq_set_2[22]" - }, - { - "name": "freq_set_2[21]" - }, - { - "name": "freq_set_2[20]" - }, - { - "name": "freq_set_2[19]" - }, - { - "name": "freq_set_2[18]" - }, - { - "name": "freq_set_2[17]" - }, - { - "name": "freq_set_2[16]" - }, - { - "name": "freq_set_2[15]" - }, - { - "name": "freq_set_2[14]" - }, - { - "name": "freq_set_2[13]" - }, - { - "name": "freq_set_2[12]" - }, - { - "name": "freq_set_2[11]" - }, - { - "name": "freq_set_2[10]" - }, - { - "name": "freq_set_2[9]" - }, - { - "name": "freq_set_2[8]" - }, - { - "name": "freq_set_2[7]" - }, - { - "name": "freq_set_2[6]" - }, - { - "name": "freq_set_2[5]" - }, - { - "name": "freq_set_2[4]" - }, - { - "name": "freq_set_2[3]" - }, - { - "name": "freq_set_2[2]" - }, - { - "name": "freq_set_2[1]" - }, - { - "name": "freq_set_2[0]" - } - ] - } - ] - }, - { - "name": "probe_out3", - "id": 101, - "type": "DATA", - "direction": "OUT", - "isVector": true, - "leftIndex": 0, - "rightIndex": 1, - "portIndex": 3, - "nets": [ - { - "name": "iq_sel_2", - "isBus": true, - "subnets": [ - { - "name": "iq_sel_2[1]" - }, - { - "name": "iq_sel_2[0]" - } - ] - } - ] - }, - { - "name": "probe_out4", - "id": 102, - "type": "DATA", - "direction": "OUT", - "isVector": true, - "leftIndex": 0, - "rightIndex": 3, - "portIndex": 4, - "nets": [ - { - "name": "bb_rshift_2", - "isBus": true, - "subnets": [ - { - "name": "bb_rshift_2[3]" - }, - { - "name": "bb_rshift_2[2]" - }, - { - "name": "bb_rshift_2[1]" - }, - { - "name": "bb_rshift_2[0]" + "name": "bb_rshift[0]" } ] } diff --git a/zc706_cx9261a_demo/zc706_cx9261a_demo.runs/impl_1/system_top.bit b/zc706_cx9261a_demo/zc706_cx9261a_demo.runs/impl_1/system_top.bit index d145c42..728dd60 100644 --- a/zc706_cx9261a_demo/zc706_cx9261a_demo.runs/impl_1/system_top.bit +++ b/zc706_cx9261a_demo/zc706_cx9261a_demo.runs/impl_1/system_top.bit @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:27779cf97c45be251f2f6a58999d2c1700c26af9be1daecee0e76431c58978ed +oid sha256:ddfb4db6c97fb7ff5575089ae64343dbbcbdb965229b7cae08f65379352f0f70 size 13321510 diff --git a/zc706_cx9261a_demo/zc706_cx9261a_demo.runs/impl_1/system_top.ltx b/zc706_cx9261a_demo/zc706_cx9261a_demo.runs/impl_1/system_top.ltx index 0ab1774..7390584 100644 --- a/zc706_cx9261a_demo/zc706_cx9261a_demo.runs/impl_1/system_top.ltx +++ b/zc706_cx9261a_demo/zc706_cx9261a_demo.runs/impl_1/system_top.ltx @@ -2094,7 +2094,7 @@ }, { "type": "ILA_V3", - "name": "u_ila_rx_fb", + "name": "system_bd/system_bd_i/system_ila_spi/inst/ila_lib", "spec": "labtools_ila_v6", "ipName": "ila", "core_location": { @@ -2102,7 +2102,7 @@ "slave_index": 3, "bscan_switch_index": 0 }, - "uuid": "288E890F004257D1882FBD4163CBA7AE", + "uuid": "46132012EA8358B6910BA2E27E723A16", "pins": [ { "name": "probe0", @@ -2115,7 +2115,7 @@ "portIndex": 0, "nets": [ { - "name": "data_valid3", + "name": "system_bd/system_bd_i/system_ila_spi/inst/probe0_1", "isBus": false } ] @@ -2125,64 +2125,14 @@ "id": 68, "type": "DATA_TRIGGER", "direction": "IN", - "isVector": true, + "isVector": false, "leftIndex": 0, - "rightIndex": 15, + "rightIndex": 0, "portIndex": 1, "nets": [ { - "name": "rx3_data_i", - "isBus": true, - "subnets": [ - { - "name": "rx3_data_i[15]" - }, - { - "name": "rx3_data_i[14]" - }, - { - "name": "rx3_data_i[13]" - }, - { - "name": "rx3_data_i[12]" - }, - { - "name": "rx3_data_i[11]" - }, - { - "name": "rx3_data_i[10]" - }, - { - "name": "rx3_data_i[9]" - }, - { - "name": "rx3_data_i[8]" - }, - { - "name": "rx3_data_i[7]" - }, - { - "name": "rx3_data_i[6]" - }, - { - "name": "rx3_data_i[5]" - }, - { - "name": "rx3_data_i[4]" - }, - { - "name": "rx3_data_i[3]" - }, - { - "name": "rx3_data_i[2]" - }, - { - "name": "rx3_data_i[1]" - }, - { - "name": "rx3_data_i[0]" - } - ] + "name": "system_bd/system_bd_i/system_ila_spi/inst/SLOT_0_SPI_ENGINE_sclk_1", + "isBus": false } ] }, @@ -2191,64 +2141,159 @@ "id": 69, "type": "DATA_TRIGGER", "direction": "IN", - "isVector": true, + "isVector": false, "leftIndex": 0, - "rightIndex": 15, + "rightIndex": 0, "portIndex": 2, "nets": [ { - "name": "rx3_data_q", - "isBus": true, - "subnets": [ - { - "name": "rx3_data_q[15]" - }, - { - "name": "rx3_data_q[14]" - }, - { - "name": "rx3_data_q[13]" - }, - { - "name": "rx3_data_q[12]" - }, - { - "name": "rx3_data_q[11]" - }, - { - "name": "rx3_data_q[10]" - }, - { - "name": "rx3_data_q[9]" - }, - { - "name": "rx3_data_q[8]" - }, - { - "name": "rx3_data_q[7]" - }, - { - "name": "rx3_data_q[6]" - }, - { - "name": "rx3_data_q[5]" - }, - { - "name": "rx3_data_q[4]" - }, - { - "name": "rx3_data_q[3]" - }, - { - "name": "rx3_data_q[2]" - }, - { - "name": "rx3_data_q[1]" - }, - { - "name": "rx3_data_q[0]" - } - ] + "name": "system_bd/system_bd_i/system_ila_spi/inst/SLOT_0_SPI_ENGINE_sdi_1", + "isBus": false + } + ] + }, + { + "name": "probe3", + "id": 70, + "type": "DATA_TRIGGER", + "direction": "IN", + "isVector": false, + "leftIndex": 0, + "rightIndex": 0, + "portIndex": 3, + "nets": [ + { + "name": "system_bd/system_bd_i/system_ila_spi/inst/SLOT_0_SPI_ENGINE_sdo_1", + "isBus": false + } + ] + }, + { + "name": "probe4", + "id": 71, + "type": "DATA_TRIGGER", + "direction": "IN", + "isVector": false, + "leftIndex": 0, + "rightIndex": 0, + "portIndex": 4, + "nets": [ + { + "name": "system_bd/system_bd_i/system_ila_spi/inst/SLOT_0_SPI_ENGINE_sdo_t_1", + "isBus": false + } + ] + }, + { + "name": "probe5", + "id": 72, + "type": "DATA_TRIGGER", + "direction": "IN", + "isVector": false, + "leftIndex": 0, + "rightIndex": 0, + "portIndex": 5, + "nets": [ + { + "name": "system_bd/system_bd_i/system_ila_spi/inst/SLOT_0_SPI_ENGINE_three_wire_1", + "isBus": false + } + ] + }, + { + "name": "probe6", + "id": 73, + "type": "DATA_TRIGGER", + "direction": "IN", + "isVector": false, + "leftIndex": 0, + "rightIndex": 0, + "portIndex": 6, + "nets": [ + { + "name": "system_bd/system_bd_i/system_ila_spi/inst/SLOT_0_SPI_ENGINE_cs_1", + "isBus": false + } + ] + } + ], + "bus_interfaces": [ + { + "name": "SLOT_0_SPI_ENGINE", + "vlnv": "analog.com:interface:spi_engine:1.0", + "connectedBus": "axi_spi_engine_spi", + "port_maps": [ + { + "logical_port": "cs", + "physical_pin": { + "id": 73, + "name": "probe6", + "leftBit": 0, + "width": 1 + } + }, + { + "logical_port": "sclk", + "physical_pin": { + "id": 68, + "name": "probe1", + "leftBit": 0, + "width": 1 + } + }, + { + "logical_port": "sdi", + "physical_pin": { + "id": 69, + "name": "probe2", + "leftBit": 0, + "width": 1 + } + }, + { + "logical_port": "sdo", + "physical_pin": { + "id": 70, + "name": "probe3", + "leftBit": 0, + "width": 1 + } + }, + { + "logical_port": "sdo_t", + "physical_pin": { + "id": 71, + "name": "probe4", + "leftBit": 0, + "width": 1 + } + }, + { + "logical_port": "three_wire", + "physical_pin": { + "id": 72, + "name": "probe5", + "leftBit": 0, + "width": 1 + } + } + ] + } + ], + "native_ports": [ + { + "name": "probe0", + "connectedBus": "axi_spi_engine_active", + "protocol": "PROBE", + "port_maps": [ + { + "logical_port": "probe0", + "physical_pin": { + "id": 67, + "name": "probe0", + "leftBit": 0, + "width": 1 + } } ] } @@ -2256,7 +2301,7 @@ }, { "type": "ILA_V3", - "name": "u_ila_trx1", + "name": "u_ila_trx", "spec": "labtools_ila_v6", "ipName": "ila", "core_location": { @@ -2264,11 +2309,11 @@ "slave_index": 4, "bscan_switch_index": 0 }, - "uuid": "4B0648EEAA8657BE89CDBEAA67057D4B", + "uuid": "B4AD3E48EFE85668933E662B3D102FF2", "pins": [ { "name": "probe0", - "id": 70, + "id": 74, "type": "DATA_TRIGGER", "direction": "IN", "isVector": false, @@ -2277,20 +2322,152 @@ "portIndex": 0, "nets": [ { - "name": "data_valid", + "name": "hop_flag", "isBus": false } ] }, { "name": "probe1", - "id": 71, + "id": 75, "type": "DATA_TRIGGER", "direction": "IN", "isVector": true, "leftIndex": 0, "rightIndex": 15, "portIndex": 1, + "nets": [ + { + "name": "tx_data_i", + "isBus": true, + "subnets": [ + { + "name": "tx_data_i[15]" + }, + { + "name": "tx_data_i[14]" + }, + { + "name": "tx_data_i[13]" + }, + { + "name": "tx_data_i[12]" + }, + { + "name": "tx_data_i[11]" + }, + { + "name": "tx_data_i[10]" + }, + { + "name": "tx_data_i[9]" + }, + { + "name": "tx_data_i[8]" + }, + { + "name": "tx_data_i[7]" + }, + { + "name": "tx_data_i[6]" + }, + { + "name": "tx_data_i[5]" + }, + { + "name": "tx_data_i[4]" + }, + { + "name": "tx_data_i[3]" + }, + { + "name": "tx_data_i[2]" + }, + { + "name": "tx_data_i[1]" + }, + { + "name": "tx_data_i[0]" + } + ] + } + ] + }, + { + "name": "probe2", + "id": 76, + "type": "DATA_TRIGGER", + "direction": "IN", + "isVector": true, + "leftIndex": 0, + "rightIndex": 15, + "portIndex": 2, + "nets": [ + { + "name": "tx_data_q", + "isBus": true, + "subnets": [ + { + "name": "tx_data_q[15]" + }, + { + "name": "tx_data_q[14]" + }, + { + "name": "tx_data_q[13]" + }, + { + "name": "tx_data_q[12]" + }, + { + "name": "tx_data_q[11]" + }, + { + "name": "tx_data_q[10]" + }, + { + "name": "tx_data_q[9]" + }, + { + "name": "tx_data_q[8]" + }, + { + "name": "tx_data_q[7]" + }, + { + "name": "tx_data_q[6]" + }, + { + "name": "tx_data_q[5]" + }, + { + "name": "tx_data_q[4]" + }, + { + "name": "tx_data_q[3]" + }, + { + "name": "tx_data_q[2]" + }, + { + "name": "tx_data_q[1]" + }, + { + "name": "tx_data_q[0]" + } + ] + } + ] + }, + { + "name": "probe3", + "id": 77, + "type": "DATA_TRIGGER", + "direction": "IN", + "isVector": true, + "leftIndex": 0, + "rightIndex": 15, + "portIndex": 3, "nets": [ { "name": "rx1_data_i", @@ -2349,14 +2526,14 @@ ] }, { - "name": "probe2", - "id": 72, + "name": "probe4", + "id": 78, "type": "DATA_TRIGGER", "direction": "IN", "isVector": true, "leftIndex": 0, "rightIndex": 15, - "portIndex": 2, + "portIndex": 4, "nets": [ { "name": "rx1_data_q", @@ -2414,209 +2591,15 @@ } ] }, - { - "name": "probe3", - "id": 73, - "type": "DATA_TRIGGER", - "direction": "IN", - "isVector": false, - "leftIndex": 0, - "rightIndex": 0, - "portIndex": 3, - "nets": [ - { - "name": "tx_data_ready", - "isBus": false - } - ] - }, - { - "name": "probe4", - "id": 74, - "type": "DATA_TRIGGER", - "direction": "IN", - "isVector": true, - "leftIndex": 0, - "rightIndex": 15, - "portIndex": 4, - "nets": [ - { - "name": "tx1_data_i", - "isBus": true, - "subnets": [ - { - "name": "tx1_data_i[15]" - }, - { - "name": "tx1_data_i[14]" - }, - { - "name": "tx1_data_i[13]" - }, - { - "name": "tx1_data_i[12]" - }, - { - "name": "tx1_data_i[11]" - }, - { - "name": "tx1_data_i[10]" - }, - { - "name": "tx1_data_i[9]" - }, - { - "name": "tx1_data_i[8]" - }, - { - "name": "tx1_data_i[7]" - }, - { - "name": "tx1_data_i[6]" - }, - { - "name": "tx1_data_i[5]" - }, - { - "name": "tx1_data_i[4]" - }, - { - "name": "tx1_data_i[3]" - }, - { - "name": "tx1_data_i[2]" - }, - { - "name": "tx1_data_i[1]" - }, - { - "name": "tx1_data_i[0]" - } - ] - } - ] - }, { "name": "probe5", - "id": 75, + "id": 79, "type": "DATA_TRIGGER", "direction": "IN", "isVector": true, "leftIndex": 0, "rightIndex": 15, "portIndex": 5, - "nets": [ - { - "name": "tx1_data_q", - "isBus": true, - "subnets": [ - { - "name": "tx1_data_q[15]" - }, - { - "name": "tx1_data_q[14]" - }, - { - "name": "tx1_data_q[13]" - }, - { - "name": "tx1_data_q[12]" - }, - { - "name": "tx1_data_q[11]" - }, - { - "name": "tx1_data_q[10]" - }, - { - "name": "tx1_data_q[9]" - }, - { - "name": "tx1_data_q[8]" - }, - { - "name": "tx1_data_q[7]" - }, - { - "name": "tx1_data_q[6]" - }, - { - "name": "tx1_data_q[5]" - }, - { - "name": "tx1_data_q[4]" - }, - { - "name": "tx1_data_q[3]" - }, - { - "name": "tx1_data_q[2]" - }, - { - "name": "tx1_data_q[1]" - }, - { - "name": "tx1_data_q[0]" - } - ] - } - ] - }, - { - "name": "probe6", - "id": 76, - "type": "DATA_TRIGGER", - "direction": "IN", - "isVector": false, - "leftIndex": 0, - "rightIndex": 0, - "portIndex": 6, - "nets": [ - { - "name": "hop_flag_1", - "isBus": false - } - ] - } - ] - }, - { - "type": "ILA_V3", - "name": "u_ila_trx2", - "spec": "labtools_ila_v6", - "ipName": "ila", - "core_location": { - "user_chain": 1, - "slave_index": 5, - "bscan_switch_index": 0 - }, - "uuid": "DB81E20588845620929226B20A3B4A70", - "pins": [ - { - "name": "probe0", - "id": 77, - "type": "DATA_TRIGGER", - "direction": "IN", - "isVector": false, - "leftIndex": 0, - "rightIndex": 0, - "portIndex": 0, - "nets": [ - { - "name": "data_valid2", - "isBus": false - } - ] - }, - { - "name": "probe1", - "id": 78, - "type": "DATA_TRIGGER", - "direction": "IN", - "isVector": true, - "leftIndex": 0, - "rightIndex": 15, - "portIndex": 1, "nets": [ { "name": "rx2_data_i", @@ -2675,14 +2658,14 @@ ] }, { - "name": "probe2", - "id": 79, + "name": "probe6", + "id": 80, "type": "DATA_TRIGGER", "direction": "IN", "isVector": true, "leftIndex": 0, "rightIndex": 15, - "portIndex": 2, + "portIndex": 6, "nets": [ { "name": "rx2_data_q", @@ -2739,170 +2722,6 @@ ] } ] - }, - { - "name": "probe3", - "id": 80, - "type": "DATA_TRIGGER", - "direction": "IN", - "isVector": false, - "leftIndex": 0, - "rightIndex": 0, - "portIndex": 3, - "nets": [ - { - "name": "tx_data_ready2", - "isBus": false - } - ] - }, - { - "name": "probe4", - "id": 81, - "type": "DATA_TRIGGER", - "direction": "IN", - "isVector": true, - "leftIndex": 0, - "rightIndex": 15, - "portIndex": 4, - "nets": [ - { - "name": "tx2_data_i", - "isBus": true, - "subnets": [ - { - "name": "tx2_data_i[15]" - }, - { - "name": "tx2_data_i[14]" - }, - { - "name": "tx2_data_i[13]" - }, - { - "name": "tx2_data_i[12]" - }, - { - "name": "tx2_data_i[11]" - }, - { - "name": "tx2_data_i[10]" - }, - { - "name": "tx2_data_i[9]" - }, - { - "name": "tx2_data_i[8]" - }, - { - "name": "tx2_data_i[7]" - }, - { - "name": "tx2_data_i[6]" - }, - { - "name": "tx2_data_i[5]" - }, - { - "name": "tx2_data_i[4]" - }, - { - "name": "tx2_data_i[3]" - }, - { - "name": "tx2_data_i[2]" - }, - { - "name": "tx2_data_i[1]" - }, - { - "name": "tx2_data_i[0]" - } - ] - } - ] - }, - { - "name": "probe5", - "id": 82, - "type": "DATA_TRIGGER", - "direction": "IN", - "isVector": true, - "leftIndex": 0, - "rightIndex": 15, - "portIndex": 5, - "nets": [ - { - "name": "tx2_data_q", - "isBus": true, - "subnets": [ - { - "name": "tx2_data_q[15]" - }, - { - "name": "tx2_data_q[14]" - }, - { - "name": "tx2_data_q[13]" - }, - { - "name": "tx2_data_q[12]" - }, - { - "name": "tx2_data_q[11]" - }, - { - "name": "tx2_data_q[10]" - }, - { - "name": "tx2_data_q[9]" - }, - { - "name": "tx2_data_q[8]" - }, - { - "name": "tx2_data_q[7]" - }, - { - "name": "tx2_data_q[6]" - }, - { - "name": "tx2_data_q[5]" - }, - { - "name": "tx2_data_q[4]" - }, - { - "name": "tx2_data_q[3]" - }, - { - "name": "tx2_data_q[2]" - }, - { - "name": "tx2_data_q[1]" - }, - { - "name": "tx2_data_q[0]" - } - ] - } - ] - }, - { - "name": "probe6", - "id": 83, - "type": "DATA_TRIGGER", - "direction": "IN", - "isVector": false, - "leftIndex": 0, - "rightIndex": 0, - "portIndex": 6, - "nets": [ - { - "name": "hop_flag", - "isBus": false - } - ] } ] }, @@ -2913,14 +2732,14 @@ "ipName": "vio", "core_location": { "user_chain": 1, - "slave_index": 6, + "slave_index": 5, "bscan_switch_index": 0 }, "uuid": "2DE1225B64E851E3B916B773749A598D", "pins": [ { "name": "probe_in0", - "id": 84, + "id": 81, "type": "DATA", "direction": "IN", "isVector": true, @@ -2953,7 +2772,7 @@ }, { "name": "probe_in1", - "id": 85, + "id": 82, "type": "DATA", "direction": "IN", "isVector": true, @@ -2986,7 +2805,7 @@ }, { "name": "probe_in2", - "id": 86, + "id": 83, "type": "DATA", "direction": "IN", "isVector": true, @@ -3019,7 +2838,7 @@ }, { "name": "probe_out0", - "id": 87, + "id": 84, "type": "DATA", "direction": "OUT", "isVector": true, @@ -3052,7 +2871,7 @@ }, { "name": "probe_out1", - "id": 88, + "id": 85, "type": "DATA", "direction": "OUT", "isVector": true, @@ -3085,7 +2904,7 @@ }, { "name": "probe_out2", - "id": 89, + "id": 86, "type": "DATA", "direction": "OUT", "isVector": true, @@ -3125,14 +2944,14 @@ "ipName": "vio", "core_location": { "user_chain": 1, - "slave_index": 7, + "slave_index": 6, "bscan_switch_index": 0 }, "uuid": "60CCCABCFDF559B38DD38C5105157D2D", "pins": [ { "name": "probe_out0", - "id": 90, + "id": 87, "type": "DATA", "direction": "OUT", "isVector": true, @@ -3246,7 +3065,7 @@ }, { "name": "probe_out1", - "id": 91, + "id": 88, "type": "DATA", "direction": "OUT", "isVector": false, @@ -3262,7 +3081,7 @@ }, { "name": "probe_out2", - "id": 92, + "id": 89, "type": "DATA", "direction": "OUT", "isVector": false, @@ -3280,441 +3099,219 @@ }, { "type": "VIO_V2", - "name": "u_vio_manual_ctrl_1", + "name": "u_vio_manual_ctrl", "spec": "labtools_vio_v3", "ipName": "vio", "core_location": { "user_chain": 1, - "slave_index": 8, + "slave_index": 7, "bscan_switch_index": 0 }, - "uuid": "3A4AD62DDC3A546EB5F2A986B350E154", + "uuid": "6DFBBD640CB857419C054C66C7EA7B27", "pins": [ { "name": "probe_out0", + "id": 90, + "type": "DATA", + "direction": "OUT", + "isVector": true, + "leftIndex": 0, + "rightIndex": 1, + "portIndex": 0, + "nets": [ + { + "name": "waveform_sel", + "isBus": true, + "subnets": [ + { + "name": "waveform_sel[1]" + }, + { + "name": "waveform_sel[0]" + } + ] + } + ] + }, + { + "name": "probe_out1", + "id": 91, + "type": "DATA", + "direction": "OUT", + "isVector": false, + "leftIndex": 0, + "rightIndex": 0, + "portIndex": 1, + "nets": [ + { + "name": "sweep_on", + "isBus": false + } + ] + }, + { + "name": "probe_out2", + "id": 92, + "type": "DATA", + "direction": "OUT", + "isVector": true, + "leftIndex": 0, + "rightIndex": 31, + "portIndex": 2, + "nets": [ + { + "name": "freq_set", + "isBus": true, + "subnets": [ + { + "name": "freq_set[31]" + }, + { + "name": "freq_set[30]" + }, + { + "name": "freq_set[29]" + }, + { + "name": "freq_set[28]" + }, + { + "name": "freq_set[27]" + }, + { + "name": "freq_set[26]" + }, + { + "name": "freq_set[25]" + }, + { + "name": "freq_set[24]" + }, + { + "name": "freq_set[23]" + }, + { + "name": "freq_set[22]" + }, + { + "name": "freq_set[21]" + }, + { + "name": "freq_set[20]" + }, + { + "name": "freq_set[19]" + }, + { + "name": "freq_set[18]" + }, + { + "name": "freq_set[17]" + }, + { + "name": "freq_set[16]" + }, + { + "name": "freq_set[15]" + }, + { + "name": "freq_set[14]" + }, + { + "name": "freq_set[13]" + }, + { + "name": "freq_set[12]" + }, + { + "name": "freq_set[11]" + }, + { + "name": "freq_set[10]" + }, + { + "name": "freq_set[9]" + }, + { + "name": "freq_set[8]" + }, + { + "name": "freq_set[7]" + }, + { + "name": "freq_set[6]" + }, + { + "name": "freq_set[5]" + }, + { + "name": "freq_set[4]" + }, + { + "name": "freq_set[3]" + }, + { + "name": "freq_set[2]" + }, + { + "name": "freq_set[1]" + }, + { + "name": "freq_set[0]" + } + ] + } + ] + }, + { + "name": "probe_out3", "id": 93, "type": "DATA", "direction": "OUT", "isVector": true, "leftIndex": 0, "rightIndex": 1, - "portIndex": 0, + "portIndex": 3, "nets": [ { - "name": "waveform_sel_1", + "name": "iq_sel", "isBus": true, "subnets": [ { - "name": "waveform_sel_1[1]" + "name": "iq_sel[1]" }, { - "name": "waveform_sel_1[0]" + "name": "iq_sel[0]" } ] } ] }, { - "name": "probe_out1", + "name": "probe_out4", "id": 94, "type": "DATA", "direction": "OUT", - "isVector": false, - "leftIndex": 0, - "rightIndex": 0, - "portIndex": 1, - "nets": [ - { - "name": "sweep_on_1", - "isBus": false - } - ] - }, - { - "name": "probe_out2", - "id": 95, - "type": "DATA", - "direction": "OUT", - "isVector": true, - "leftIndex": 0, - "rightIndex": 31, - "portIndex": 2, - "nets": [ - { - "name": "freq_set_1", - "isBus": true, - "subnets": [ - { - "name": "freq_set_1[31]" - }, - { - "name": "freq_set_1[30]" - }, - { - "name": "freq_set_1[29]" - }, - { - "name": "freq_set_1[28]" - }, - { - "name": "freq_set_1[27]" - }, - { - "name": "freq_set_1[26]" - }, - { - "name": "freq_set_1[25]" - }, - { - "name": "freq_set_1[24]" - }, - { - "name": "freq_set_1[23]" - }, - { - "name": "freq_set_1[22]" - }, - { - "name": "freq_set_1[21]" - }, - { - "name": "freq_set_1[20]" - }, - { - "name": "freq_set_1[19]" - }, - { - "name": "freq_set_1[18]" - }, - { - "name": "freq_set_1[17]" - }, - { - "name": "freq_set_1[16]" - }, - { - "name": "freq_set_1[15]" - }, - { - "name": "freq_set_1[14]" - }, - { - "name": "freq_set_1[13]" - }, - { - "name": "freq_set_1[12]" - }, - { - "name": "freq_set_1[11]" - }, - { - "name": "freq_set_1[10]" - }, - { - "name": "freq_set_1[9]" - }, - { - "name": "freq_set_1[8]" - }, - { - "name": "freq_set_1[7]" - }, - { - "name": "freq_set_1[6]" - }, - { - "name": "freq_set_1[5]" - }, - { - "name": "freq_set_1[4]" - }, - { - "name": "freq_set_1[3]" - }, - { - "name": "freq_set_1[2]" - }, - { - "name": "freq_set_1[1]" - }, - { - "name": "freq_set_1[0]" - } - ] - } - ] - }, - { - "name": "probe_out3", - "id": 96, - "type": "DATA", - "direction": "OUT", - "isVector": true, - "leftIndex": 0, - "rightIndex": 1, - "portIndex": 3, - "nets": [ - { - "name": "iq_sel_1", - "isBus": true, - "subnets": [ - { - "name": "iq_sel_1[1]" - }, - { - "name": "iq_sel_1[0]" - } - ] - } - ] - }, - { - "name": "probe_out4", - "id": 97, - "type": "DATA", - "direction": "OUT", "isVector": true, "leftIndex": 0, "rightIndex": 3, "portIndex": 4, "nets": [ { - "name": "bb_rshift_1", + "name": "bb_rshift", "isBus": true, "subnets": [ { - "name": "bb_rshift_1[3]" + "name": "bb_rshift[3]" }, { - "name": "bb_rshift_1[2]" + "name": "bb_rshift[2]" }, { - "name": "bb_rshift_1[1]" + "name": "bb_rshift[1]" }, { - "name": "bb_rshift_1[0]" - } - ] - } - ] - } - ] - }, - { - "type": "VIO_V2", - "name": "u_vio_manual_ctrl_2", - "spec": "labtools_vio_v3", - "ipName": "vio", - "core_location": { - "user_chain": 1, - "slave_index": 9, - "bscan_switch_index": 0 - }, - "uuid": "09D2047C4D375ED8AEA61ABD4F4AF334", - "pins": [ - { - "name": "probe_out0", - "id": 98, - "type": "DATA", - "direction": "OUT", - "isVector": true, - "leftIndex": 0, - "rightIndex": 1, - "portIndex": 0, - "nets": [ - { - "name": "waveform_sel_2", - "isBus": true, - "subnets": [ - { - "name": "waveform_sel_2[1]" - }, - { - "name": "waveform_sel_2[0]" - } - ] - } - ] - }, - { - "name": "probe_out1", - "id": 99, - "type": "DATA", - "direction": "OUT", - "isVector": false, - "leftIndex": 0, - "rightIndex": 0, - "portIndex": 1, - "nets": [ - { - "name": "sweep_on_2", - "isBus": false - } - ] - }, - { - "name": "probe_out2", - "id": 100, - "type": "DATA", - "direction": "OUT", - "isVector": true, - "leftIndex": 0, - "rightIndex": 31, - "portIndex": 2, - "nets": [ - { - "name": "freq_set_2", - "isBus": true, - "subnets": [ - { - "name": "freq_set_2[31]" - }, - { - "name": "freq_set_2[30]" - }, - { - "name": "freq_set_2[29]" - }, - { - "name": "freq_set_2[28]" - }, - { - "name": "freq_set_2[27]" - }, - { - "name": "freq_set_2[26]" - }, - { - "name": "freq_set_2[25]" - }, - { - "name": "freq_set_2[24]" - }, - { - "name": "freq_set_2[23]" - }, - { - "name": "freq_set_2[22]" - }, - { - "name": "freq_set_2[21]" - }, - { - "name": "freq_set_2[20]" - }, - { - "name": "freq_set_2[19]" - }, - { - "name": "freq_set_2[18]" - }, - { - "name": "freq_set_2[17]" - }, - { - "name": "freq_set_2[16]" - }, - { - "name": "freq_set_2[15]" - }, - { - "name": "freq_set_2[14]" - }, - { - "name": "freq_set_2[13]" - }, - { - "name": "freq_set_2[12]" - }, - { - "name": "freq_set_2[11]" - }, - { - "name": "freq_set_2[10]" - }, - { - "name": "freq_set_2[9]" - }, - { - "name": "freq_set_2[8]" - }, - { - "name": "freq_set_2[7]" - }, - { - "name": "freq_set_2[6]" - }, - { - "name": "freq_set_2[5]" - }, - { - "name": "freq_set_2[4]" - }, - { - "name": "freq_set_2[3]" - }, - { - "name": "freq_set_2[2]" - }, - { - "name": "freq_set_2[1]" - }, - { - "name": "freq_set_2[0]" - } - ] - } - ] - }, - { - "name": "probe_out3", - "id": 101, - "type": "DATA", - "direction": "OUT", - "isVector": true, - "leftIndex": 0, - "rightIndex": 1, - "portIndex": 3, - "nets": [ - { - "name": "iq_sel_2", - "isBus": true, - "subnets": [ - { - "name": "iq_sel_2[1]" - }, - { - "name": "iq_sel_2[0]" - } - ] - } - ] - }, - { - "name": "probe_out4", - "id": 102, - "type": "DATA", - "direction": "OUT", - "isVector": true, - "leftIndex": 0, - "rightIndex": 3, - "portIndex": 4, - "nets": [ - { - "name": "bb_rshift_2", - "isBus": true, - "subnets": [ - { - "name": "bb_rshift_2[3]" - }, - { - "name": "bb_rshift_2[2]" - }, - { - "name": "bb_rshift_2[1]" - }, - { - "name": "bb_rshift_2[0]" + "name": "bb_rshift[0]" } ] } diff --git a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/sim/system_bd_axi_spi_engine_0_0.v b/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/sim/system_bd_axi_spi_engine_0_0.v deleted file mode 100644 index 08a7705..0000000 --- a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/sim/system_bd_axi_spi_engine_0_0.v +++ /dev/null @@ -1,245 +0,0 @@ -// (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// -// DO NOT MODIFY THIS FILE. - - -// IP VLNV: analog.com:user:axi_spi_engine:1.0 -// IP Revision: 1 - -`timescale 1ns/1ps - -(* IP_DEFINITION_SOURCE = "package_project" *) -(* DowngradeIPIdentifiedWarnings = "yes" *) -module system_bd_axi_spi_engine_0_0 ( - s_axi_aclk, - s_axi_aresetn, - s_axi_awvalid, - s_axi_awaddr, - s_axi_awready, - s_axi_awprot, - s_axi_wvalid, - s_axi_wdata, - s_axi_wstrb, - s_axi_wready, - s_axi_bvalid, - s_axi_bresp, - s_axi_bready, - s_axi_arvalid, - s_axi_araddr, - s_axi_arready, - s_axi_arprot, - s_axi_rvalid, - s_axi_rready, - s_axi_rresp, - s_axi_rdata, - irq, - spi_clk, - spi_resetn, - cmd_ready, - cmd_valid, - cmd_data, - sdo_data_ready, - sdo_data_valid, - sdo_data, - sdi_data_ready, - sdi_data_valid, - sdi_data, - sync_ready, - sync_valid, - sync_data -); - -(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi_aclk, ASSOCIATED_BUSIF s_axi, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0, XIL_INTERFACENAME spi_engine_offload_ctrl0_s_axi_signal_clock, ASSOCIATED_BUSIF spi_engine_offload_ctrl0:s_axi, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *) -(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 s_axi_aclk CLK, xilinx.com:signal:clock:1.0 spi_engine_offload_ctrl0_s_axi_signal_clock CLK" *) -input wire s_axi_aclk; -(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0, XIL_INTERFACENAME spi_engine_offload_ctrl0_s_axi_signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) -(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 s_axi_aresetn RST, xilinx.com:signal:reset:1.0 spi_engine_offload_ctrl0_s_axi_signal_reset RST" *) -input wire s_axi_aresetn; -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWVALID" *) -input wire s_axi_awvalid; -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWADDR" *) -input wire [15 : 0] s_axi_awaddr; -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWREADY" *) -output wire s_axi_awready; -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWPROT" *) -input wire [2 : 0] s_axi_awprot; -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WVALID" *) -input wire s_axi_wvalid; -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WDATA" *) -input wire [31 : 0] s_axi_wdata; -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WSTRB" *) -input wire [3 : 0] s_axi_wstrb; -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WREADY" *) -output wire s_axi_wready; -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BVALID" *) -output wire s_axi_bvalid; -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BRESP" *) -output wire [1 : 0] s_axi_bresp; -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BREADY" *) -input wire s_axi_bready; -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARVALID" *) -input wire s_axi_arvalid; -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARADDR" *) -input wire [15 : 0] s_axi_araddr; -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARREADY" *) -output wire s_axi_arready; -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARPROT" *) -input wire [2 : 0] s_axi_arprot; -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RVALID" *) -output wire s_axi_rvalid; -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RREADY" *) -input wire s_axi_rready; -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RRESP" *) -output wire [1 : 0] s_axi_rresp; -(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 50000000, ID_WIDTH 0, ADDR_WIDTH 16, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREAD\ -S 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RDATA" *) -output wire [31 : 0] s_axi_rdata; -output wire irq; -(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME spi_engine_ctrl_signal_clock, ASSOCIATED_BUSIF spi_engine_ctrl, ASSOCIATED_RESET spi_resetn, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *) -(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 spi_engine_ctrl_signal_clock CLK" *) -input wire spi_clk; -(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME spi_engine_ctrl_signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) -(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 spi_engine_ctrl_signal_reset RST" *) -output wire spi_resetn; -(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl CMD_READY" *) -input wire cmd_ready; -(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl CMD_VALID" *) -output wire cmd_valid; -(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl CMD_DATA" *) -output wire [15 : 0] cmd_data; -(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDO_READY" *) -input wire sdo_data_ready; -(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDO_VALID" *) -output wire sdo_data_valid; -(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDO_DATA" *) -output wire [7 : 0] sdo_data; -(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDI_READY" *) -output wire sdi_data_ready; -(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDI_VALID" *) -input wire sdi_data_valid; -(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDI_DATA" *) -input wire [7 : 0] sdi_data; -(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SYNC_READY" *) -output wire sync_ready; -(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SYNC_VALID" *) -input wire sync_valid; -(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SYNC_DATA" *) -input wire [7 : 0] sync_data; - - axi_spi_engine #( - .CMD_FIFO_ADDRESS_WIDTH(4), - .SYNC_FIFO_ADDRESS_WIDTH(4), - .SDO_FIFO_ADDRESS_WIDTH(5), - .SDI_FIFO_ADDRESS_WIDTH(5), - .MM_IF_TYPE(0), - .ASYNC_SPI_CLK(1'B0), - .NUM_OFFLOAD(0), - .OFFLOAD0_CMD_MEM_ADDRESS_WIDTH(4), - .OFFLOAD0_SDO_MEM_ADDRESS_WIDTH(4), - .ID(0), - .DATA_WIDTH(8), - .NUM_OF_SDI(1) - ) inst ( - .s_axi_aclk(s_axi_aclk), - .s_axi_aresetn(s_axi_aresetn), - .s_axi_awvalid(s_axi_awvalid), - .s_axi_awaddr(s_axi_awaddr), - .s_axi_awready(s_axi_awready), - .s_axi_awprot(s_axi_awprot), - .s_axi_wvalid(s_axi_wvalid), - .s_axi_wdata(s_axi_wdata), - .s_axi_wstrb(s_axi_wstrb), - .s_axi_wready(s_axi_wready), - .s_axi_bvalid(s_axi_bvalid), - .s_axi_bresp(s_axi_bresp), - .s_axi_bready(s_axi_bready), - .s_axi_arvalid(s_axi_arvalid), - .s_axi_araddr(s_axi_araddr), - .s_axi_arready(s_axi_arready), - .s_axi_arprot(s_axi_arprot), - .s_axi_rvalid(s_axi_rvalid), - .s_axi_rready(s_axi_rready), - .s_axi_rresp(s_axi_rresp), - .s_axi_rdata(s_axi_rdata), - .up_clk(1'B0), - .up_rstn(1'B0), - .up_wreq(1'B0), - .up_waddr(14'B0), - .up_wdata(32'B0), - .up_wack(), - .up_rreq(1'B0), - .up_raddr(14'B0), - .up_rdata(), - .up_rack(), - .irq(irq), - .spi_clk(spi_clk), - .spi_resetn(spi_resetn), - .cmd_ready(cmd_ready), - .cmd_valid(cmd_valid), - .cmd_data(cmd_data), - .sdo_data_ready(sdo_data_ready), - .sdo_data_valid(sdo_data_valid), - .sdo_data(sdo_data), - .sdi_data_ready(sdi_data_ready), - .sdi_data_valid(sdi_data_valid), - .sdi_data(sdi_data), - .sync_ready(sync_ready), - .sync_valid(sync_valid), - .sync_data(sync_data), - .offload0_cmd_wr_en(), - .offload0_cmd_wr_data(), - .offload0_sdo_wr_en(), - .offload0_sdo_wr_data(), - .offload0_mem_reset(), - .offload0_enable(), - .offload0_enabled(1'B0), - .offload_sync_ready(), - .offload_sync_valid(1'B0), - .offload_sync_data(8'B0) - ); -endmodule diff --git a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/synth/system_bd_axi_spi_engine_0_0.v b/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/synth/system_bd_axi_spi_engine_0_0.v deleted file mode 100644 index d8770e2..0000000 --- a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/synth/system_bd_axi_spi_engine_0_0.v +++ /dev/null @@ -1,245 +0,0 @@ -// (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// -// DO NOT MODIFY THIS FILE. - - -// IP VLNV: analog.com:user:axi_spi_engine:1.0 -// IP Revision: 1 - -(* X_CORE_INFO = "axi_spi_engine,Vivado 2019.1.3" *) -(* CHECK_LICENSE_TYPE = "system_bd_axi_spi_engine_0_0,axi_spi_engine,{}" *) -(* IP_DEFINITION_SOURCE = "package_project" *) -(* DowngradeIPIdentifiedWarnings = "yes" *) -module system_bd_axi_spi_engine_0_0 ( - s_axi_aclk, - s_axi_aresetn, - s_axi_awvalid, - s_axi_awaddr, - s_axi_awready, - s_axi_awprot, - s_axi_wvalid, - s_axi_wdata, - s_axi_wstrb, - s_axi_wready, - s_axi_bvalid, - s_axi_bresp, - s_axi_bready, - s_axi_arvalid, - s_axi_araddr, - s_axi_arready, - s_axi_arprot, - s_axi_rvalid, - s_axi_rready, - s_axi_rresp, - s_axi_rdata, - irq, - spi_clk, - spi_resetn, - cmd_ready, - cmd_valid, - cmd_data, - sdo_data_ready, - sdo_data_valid, - sdo_data, - sdi_data_ready, - sdi_data_valid, - sdi_data, - sync_ready, - sync_valid, - sync_data -); - -(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi_aclk, ASSOCIATED_BUSIF s_axi, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0, XIL_INTERFACENAME spi_engine_offload_ctrl0_s_axi_signal_clock, ASSOCIATED_BUSIF spi_engine_offload_ctrl0:s_axi, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *) -(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 s_axi_aclk CLK, xilinx.com:signal:clock:1.0 spi_engine_offload_ctrl0_s_axi_signal_clock CLK" *) -input wire s_axi_aclk; -(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0, XIL_INTERFACENAME spi_engine_offload_ctrl0_s_axi_signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) -(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 s_axi_aresetn RST, xilinx.com:signal:reset:1.0 spi_engine_offload_ctrl0_s_axi_signal_reset RST" *) -input wire s_axi_aresetn; -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWVALID" *) -input wire s_axi_awvalid; -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWADDR" *) -input wire [15 : 0] s_axi_awaddr; -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWREADY" *) -output wire s_axi_awready; -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWPROT" *) -input wire [2 : 0] s_axi_awprot; -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WVALID" *) -input wire s_axi_wvalid; -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WDATA" *) -input wire [31 : 0] s_axi_wdata; -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WSTRB" *) -input wire [3 : 0] s_axi_wstrb; -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WREADY" *) -output wire s_axi_wready; -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BVALID" *) -output wire s_axi_bvalid; -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BRESP" *) -output wire [1 : 0] s_axi_bresp; -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BREADY" *) -input wire s_axi_bready; -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARVALID" *) -input wire s_axi_arvalid; -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARADDR" *) -input wire [15 : 0] s_axi_araddr; -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARREADY" *) -output wire s_axi_arready; -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARPROT" *) -input wire [2 : 0] s_axi_arprot; -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RVALID" *) -output wire s_axi_rvalid; -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RREADY" *) -input wire s_axi_rready; -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RRESP" *) -output wire [1 : 0] s_axi_rresp; -(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 50000000, ID_WIDTH 0, ADDR_WIDTH 16, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREAD\ -S 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RDATA" *) -output wire [31 : 0] s_axi_rdata; -output wire irq; -(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME spi_engine_ctrl_signal_clock, ASSOCIATED_BUSIF spi_engine_ctrl, ASSOCIATED_RESET spi_resetn, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *) -(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 spi_engine_ctrl_signal_clock CLK" *) -input wire spi_clk; -(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME spi_engine_ctrl_signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) -(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 spi_engine_ctrl_signal_reset RST" *) -output wire spi_resetn; -(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl CMD_READY" *) -input wire cmd_ready; -(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl CMD_VALID" *) -output wire cmd_valid; -(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl CMD_DATA" *) -output wire [15 : 0] cmd_data; -(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDO_READY" *) -input wire sdo_data_ready; -(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDO_VALID" *) -output wire sdo_data_valid; -(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDO_DATA" *) -output wire [7 : 0] sdo_data; -(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDI_READY" *) -output wire sdi_data_ready; -(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDI_VALID" *) -input wire sdi_data_valid; -(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDI_DATA" *) -input wire [7 : 0] sdi_data; -(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SYNC_READY" *) -output wire sync_ready; -(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SYNC_VALID" *) -input wire sync_valid; -(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SYNC_DATA" *) -input wire [7 : 0] sync_data; - - axi_spi_engine #( - .CMD_FIFO_ADDRESS_WIDTH(4), - .SYNC_FIFO_ADDRESS_WIDTH(4), - .SDO_FIFO_ADDRESS_WIDTH(5), - .SDI_FIFO_ADDRESS_WIDTH(5), - .MM_IF_TYPE(0), - .ASYNC_SPI_CLK(1'B0), - .NUM_OFFLOAD(0), - .OFFLOAD0_CMD_MEM_ADDRESS_WIDTH(4), - .OFFLOAD0_SDO_MEM_ADDRESS_WIDTH(4), - .ID(0), - .DATA_WIDTH(8), - .NUM_OF_SDI(1) - ) inst ( - .s_axi_aclk(s_axi_aclk), - .s_axi_aresetn(s_axi_aresetn), - .s_axi_awvalid(s_axi_awvalid), - .s_axi_awaddr(s_axi_awaddr), - .s_axi_awready(s_axi_awready), - .s_axi_awprot(s_axi_awprot), - .s_axi_wvalid(s_axi_wvalid), - .s_axi_wdata(s_axi_wdata), - .s_axi_wstrb(s_axi_wstrb), - .s_axi_wready(s_axi_wready), - .s_axi_bvalid(s_axi_bvalid), - .s_axi_bresp(s_axi_bresp), - .s_axi_bready(s_axi_bready), - .s_axi_arvalid(s_axi_arvalid), - .s_axi_araddr(s_axi_araddr), - .s_axi_arready(s_axi_arready), - .s_axi_arprot(s_axi_arprot), - .s_axi_rvalid(s_axi_rvalid), - .s_axi_rready(s_axi_rready), - .s_axi_rresp(s_axi_rresp), - .s_axi_rdata(s_axi_rdata), - .up_clk(1'B0), - .up_rstn(1'B0), - .up_wreq(1'B0), - .up_waddr(14'B0), - .up_wdata(32'B0), - .up_wack(), - .up_rreq(1'B0), - .up_raddr(14'B0), - .up_rdata(), - .up_rack(), - .irq(irq), - .spi_clk(spi_clk), - .spi_resetn(spi_resetn), - .cmd_ready(cmd_ready), - .cmd_valid(cmd_valid), - .cmd_data(cmd_data), - .sdo_data_ready(sdo_data_ready), - .sdo_data_valid(sdo_data_valid), - .sdo_data(sdo_data), - .sdi_data_ready(sdi_data_ready), - .sdi_data_valid(sdi_data_valid), - .sdi_data(sdi_data), - .sync_ready(sync_ready), - .sync_valid(sync_valid), - .sync_data(sync_data), - .offload0_cmd_wr_en(), - .offload0_cmd_wr_data(), - .offload0_sdo_wr_en(), - .offload0_sdo_wr_data(), - .offload0_mem_reset(), - .offload0_enable(), - .offload0_enabled(1'B0), - .offload_sync_ready(), - .offload_sync_valid(1'B0), - .offload_sync_data(8'B0) - ); -endmodule diff --git a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0.dcp b/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0.dcp deleted file mode 100644 index 4e8d0ad..0000000 --- a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0.dcp +++ /dev/null @@ -1,3 +0,0 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:616c7e8177bcf17818e73c5aee23af1af76c4386a4615bd54f5cbabe019a2782 -size 120437 diff --git a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0.xci b/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0.xci index 4622e85..a290063 100644 --- a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0.xci +++ b/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0.xci @@ -2,10 +2,10 @@ "schema": "xilinx.com:schema:json_instance:1.0", "ip_inst": { "xci_name": "system_bd_axi_spi_engine_0_0", - "cell_name": "axi_spi_engine/axi_spi_engine", + "cell_name": "axi_spi_engine", "component_reference": "analog.com:user:axi_spi_engine:1.0", "ip_revision": "1", - "gen_directory": ".", + "gen_directory": "../../../../../../zc706_cx9261a_demo.gen/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0", "parameters": { "component_parameters": { "CMD_FIFO_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ], @@ -20,6 +20,10 @@ "ID": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], "DATA_WIDTH": [ { "value": "8", "resolve_type": "user", "format": "long", "usage": "all" } ], "NUM_OF_SDI": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "CFG_INFO_0": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "CFG_INFO_1": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "CFG_INFO_2": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "CFG_INFO_3": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], "Component_Name": [ { "value": "system_bd_axi_spi_engine_0_0", "resolve_type": "user", "usage": "all" } ] }, "model_parameters": { @@ -34,7 +38,11 @@ "OFFLOAD0_SDO_MEM_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], "ID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "DATA_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "NUM_OF_SDI": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ] + "NUM_OF_SDI": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "CFG_INFO_0": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "CFG_INFO_1": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "CFG_INFO_2": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "CFG_INFO_3": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ] }, "project_parameters": { "ARCHITECTURE": [ { "value": "zynq" } ], @@ -53,12 +61,11 @@ "runtime_parameters": { "IPCONTEXT": [ { "value": "IP_Integrator" } ], "IPREVISION": [ { "value": "1" } ], - "LOCKEDBYUSER": [ { "value": "TRUE" } ], "MANAGED": [ { "value": "TRUE" } ], - "OUTPUTDIR": [ { "value": "." } ], + "OUTPUTDIR": [ { "value": "../../../../../../zc706_cx9261a_demo.gen/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0" } ], "SELECTEDSIMMODEL": [ { "value": "" } ], "SHAREDDIR": [ { "value": "../../ipshared" } ], - "SWVERSION": [ { "value": "2019.1.3" } ], + "SWVERSION": [ { "value": "2024.1" } ], "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ] } }, @@ -108,37 +115,37 @@ "mode": "slave", "memory_map_ref": "s_axi", "parameters": { - "DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ], - "FREQ_HZ": [ { "value": "50000000", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "ADDR_WIDTH": [ { "value": "16", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ], - "HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "HAS_PROT": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "HAS_WSTRB": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "HAS_BRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "HAS_RRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "NUM_READ_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "MAX_BURST_LENGTH": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "is_static_object": false } ], - "CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_static_object": false } ], - "NUM_READ_THREADS": [ { "value": "1", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "NUM_WRITE_THREADS": [ { "value": "1", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "RUSER_BITS_PER_BYTE": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "WUSER_BITS_PER_BYTE": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ] + "DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_HZ": [ { "value": "5e+07", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "ADDR_WIDTH": [ { "value": "16", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_PROT": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_WSTRB": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_BRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_RRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "NUM_READ_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "MAX_BURST_LENGTH": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] }, "port_maps": { "AWADDR": [ { "physical_name": "s_axi_awaddr" } ], @@ -167,14 +174,14 @@ "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", "mode": "slave", "parameters": { - "ASSOCIATED_BUSIF": [ { "value": "s_axi", "value_src": "constant", "usage": "all" } ], - "ASSOCIATED_RESET": [ { "value": "s_axi_aresetn", "value_src": "constant", "usage": "all" } ], - "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "is_static_object": false } ], - "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_static_object": false } ], - "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ], - "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ] + "ASSOCIATED_BUSIF": [ { "value": "s_axi", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ], + "ASSOCIATED_RESET": [ { "value": "s_axi_aresetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ], + "FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] }, "port_maps": { "CLK": [ { "physical_name": "s_axi_aclk" } ] @@ -185,8 +192,8 @@ "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", "mode": "slave", "parameters": { - "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ], - "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ] + "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] }, "port_maps": { "RST": [ { "physical_name": "s_axi_aresetn" } ] @@ -197,18 +204,18 @@ "abstraction_type": "analog.com:interface:spi_engine_ctrl_rtl:1.0", "mode": "master", "port_maps": { - "CMD_READY": [ { "physical_name": "cmd_ready" } ], - "CMD_VALID": [ { "physical_name": "cmd_valid" } ], - "CMD_DATA": [ { "physical_name": "cmd_data" } ], - "SDO_READY": [ { "physical_name": "sdo_data_ready" } ], - "SDO_VALID": [ { "physical_name": "sdo_data_valid" } ], - "SDO_DATA": [ { "physical_name": "sdo_data" } ], - "SDI_READY": [ { "physical_name": "sdi_data_ready" } ], - "SDI_VALID": [ { "physical_name": "sdi_data_valid" } ], - "SDI_DATA": [ { "physical_name": "sdi_data" } ], - "SYNC_READY": [ { "physical_name": "sync_ready" } ], - "SYNC_VALID": [ { "physical_name": "sync_valid" } ], - "SYNC_DATA": [ { "physical_name": "sync_data" } ] + "cmd_ready": [ { "physical_name": "cmd_ready" } ], + "cmd_valid": [ { "physical_name": "cmd_valid" } ], + "cmd_data": [ { "physical_name": "cmd_data" } ], + "sdo_ready": [ { "physical_name": "sdo_data_ready" } ], + "sdo_valid": [ { "physical_name": "sdo_data_valid" } ], + "sdo_data": [ { "physical_name": "sdo_data" } ], + "sdi_ready": [ { "physical_name": "sdi_data_ready" } ], + "sdi_valid": [ { "physical_name": "sdi_data_valid" } ], + "sdi_data": [ { "physical_name": "sdi_data" } ], + "sync_ready": [ { "physical_name": "sync_ready" } ], + "sync_valid": [ { "physical_name": "sync_valid" } ], + "sync_data": [ { "physical_name": "sync_data" } ] } }, "spi_engine_ctrl_signal_clock": { @@ -216,14 +223,14 @@ "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", "mode": "slave", "parameters": { - "ASSOCIATED_BUSIF": [ { "value": "spi_engine_ctrl", "value_src": "constant", "usage": "all" } ], - "ASSOCIATED_RESET": [ { "value": "spi_resetn", "value_src": "constant", "usage": "all" } ], - "FREQ_HZ": [ { "value": "50000000", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "is_static_object": false } ], - "CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_static_object": false } ], - "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ], - "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ] + "ASSOCIATED_BUSIF": [ { "value": "spi_engine_ctrl", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ], + "ASSOCIATED_RESET": [ { "value": "spi_resetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ], + "FREQ_HZ": [ { "value": "2e+08", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK1", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] }, "port_maps": { "CLK": [ { "physical_name": "spi_clk" } ] @@ -234,8 +241,8 @@ "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", "mode": "master", "parameters": { - "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ], - "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ] + "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] }, "port_maps": { "RST": [ { "physical_name": "spi_resetn" } ] @@ -246,14 +253,14 @@ "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", "mode": "slave", "parameters": { - "ASSOCIATED_BUSIF": [ { "value": "spi_engine_offload_ctrl0:s_axi", "value_src": "constant", "usage": "all" } ], - "ASSOCIATED_RESET": [ { "value": "s_axi_aresetn", "value_src": "constant", "usage": "all" } ], - "FREQ_HZ": [ { "value": "50000000", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "is_static_object": false } ], - "CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_static_object": false } ], - "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ], - "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ] + "ASSOCIATED_BUSIF": [ { "value": "spi_engine_offload_ctrl0:s_axi", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ], + "ASSOCIATED_RESET": [ { "value": "s_axi_aresetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ], + "FREQ_HZ": [ { "value": "5e+07", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] }, "port_maps": { "CLK": [ { "physical_name": "s_axi_aclk" } ] @@ -264,8 +271,8 @@ "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", "mode": "slave", "parameters": { - "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ], - "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ] + "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] }, "port_maps": { "RST": [ { "physical_name": "s_axi_aresetn" } ] diff --git a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0.xml b/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0.xml deleted file mode 100644 index a28b39b..0000000 --- a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0.xml +++ /dev/null @@ -1,2744 +0,0 @@ - - - analog.com - customized_ip - system_bd_axi_spi_engine_0_0 - 1.0 - - - s_axi - - - - - - - - - AWADDR - - - s_axi_awaddr - - - - - AWPROT - - - s_axi_awprot - - - - - AWVALID - - - s_axi_awvalid - - - - - AWREADY - - - s_axi_awready - - - - - WDATA - - - s_axi_wdata - - - - - WSTRB - - - s_axi_wstrb - - - - - WVALID - - - s_axi_wvalid - - - - - WREADY - - - s_axi_wready - - - - - BRESP - - - s_axi_bresp - - - - - BVALID - - - s_axi_bvalid - - - - - BREADY - - - s_axi_bready - - - - - ARADDR - - - s_axi_araddr - - - - - ARPROT - - - s_axi_arprot - - - - - ARVALID - - - s_axi_arvalid - - - - - ARREADY - - - s_axi_arready - - - - - RDATA - - - s_axi_rdata - - - - - RRESP - - - s_axi_rresp - - - - - RVALID - - - s_axi_rvalid - - - - - RREADY - - - s_axi_rready - - - - - - DATA_WIDTH - 32 - - - none - - - - - PROTOCOL - AXI4LITE - - - none - - - - - FREQ_HZ - 50000000 - - - none - - - - - ID_WIDTH - 0 - - - none - - - - - ADDR_WIDTH - 16 - - - none - - - - - AWUSER_WIDTH - 0 - - - none - - - - - ARUSER_WIDTH - 0 - - - none - - - - - WUSER_WIDTH - 0 - - - none - - - - - RUSER_WIDTH - 0 - - - none - - - - - BUSER_WIDTH - 0 - - - none - - - - - READ_WRITE_MODE - READ_WRITE - - - none - - - - - HAS_BURST - 0 - - - none - - - - - HAS_LOCK - 0 - - - none - - - - - HAS_PROT - 1 - - - none - - - - - HAS_CACHE - 0 - - - none - - - - - HAS_QOS - 0 - - - none - - - - - HAS_REGION - 0 - - - none - - - - - HAS_WSTRB - 1 - - - none - - - - - HAS_BRESP - 1 - - - none - - - - - HAS_RRESP - 1 - - - none - - - - - SUPPORTS_NARROW_BURST - 0 - - - none - - - - - NUM_READ_OUTSTANDING - 1 - - - none - - - - - NUM_WRITE_OUTSTANDING - 1 - - - none - - - - - MAX_BURST_LENGTH - 1 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - system_bd_processing_system7_0_0_FCLK_CLK0 - - - none - - - - - NUM_READ_THREADS - 1 - - - none - - - - - NUM_WRITE_THREADS - 1 - - - none - - - - - RUSER_BITS_PER_BYTE - 0 - - - none - - - - - WUSER_BITS_PER_BYTE - 0 - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - true - - - - - - s_axi_aclk - - - - - - - CLK - - - s_axi_aclk - - - - - - ASSOCIATED_BUSIF - s_axi - - - ASSOCIATED_RESET - s_axi_aresetn - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - FREQ_TOLERANCE_HZ - 0 - - - none - - - - - ASSOCIATED_PORT - - - - none - - - - - - - s_axi_aresetn - - - - - - - RST - - - s_axi_aresetn - - - - - - POLARITY - ACTIVE_LOW - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - spi_engine_ctrl - - - - - - - CMD_READY - - - cmd_ready - - - - - CMD_VALID - - - cmd_valid - - - - - CMD_DATA - - - cmd_data - - - - - SDO_READY - - - sdo_data_ready - - - - - SDO_VALID - - - sdo_data_valid - - - - - SDO_DATA - - - sdo_data - - - - - SDI_READY - - - sdi_data_ready - - - - - SDI_VALID - - - sdi_data_valid - - - - - SDI_DATA - - - sdi_data - - - - - SYNC_READY - - - sync_ready - - - - - SYNC_VALID - - - sync_valid - - - - - SYNC_DATA - - - sync_data - - - - - - spi_engine_ctrl_signal_clock - spi_engine_ctrl_signal_clock - - - - - - - CLK - - - spi_clk - - - - - - ASSOCIATED_BUSIF - spi_engine_ctrl - - - ASSOCIATED_RESET - spi_resetn - - - FREQ_HZ - 50000000 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - system_bd_processing_system7_0_0_FCLK_CLK0 - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - FREQ_TOLERANCE_HZ - 0 - - - none - - - - - ASSOCIATED_PORT - - - - none - - - - - - - spi_engine_ctrl_signal_reset - spi_engine_ctrl_signal_reset - - - - - - - RST - - - spi_resetn - - - - - - POLARITY - ACTIVE_LOW - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - spi_engine_offload_ctrl0 - - - - - - - CMD_WR_EN - - - offload0_cmd_wr_en - - - - - CMD_WR_DATA - - - offload0_cmd_wr_data - - - - - SDO_WR_EN - - - offload0_sdo_wr_en - - - - - SDO_WR_DATA - - - offload0_sdo_wr_data - - - - - ENABLE - - - offload0_enable - - - - - ENABLED - - - offload0_enabled - - - - - MEM_RESET - - - offload0_mem_reset - - - - - SYNC_READY - - - offload_sync_ready - - - - - SYNC_VALID - - - offload_sync_valid - - - - - SYNC_DATA - - - offload_sync_data - - - - - - - false - - - - - - spi_engine_offload_ctrl0_s_axi_signal_clock - spi_engine_offload_ctrl0_s_axi_signal_clock - - - - - - - CLK - - - s_axi_aclk - - - - - - ASSOCIATED_BUSIF - spi_engine_offload_ctrl0:s_axi - - - ASSOCIATED_RESET - s_axi_aresetn - - - FREQ_HZ - 50000000 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - system_bd_processing_system7_0_0_FCLK_CLK0 - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - FREQ_TOLERANCE_HZ - 0 - - - none - - - - - ASSOCIATED_PORT - - - - none - - - - - - - spi_engine_offload_ctrl0_s_axi_signal_reset - spi_engine_offload_ctrl0_s_axi_signal_reset - - - - - - - RST - - - s_axi_aresetn - - - - - - POLARITY - ACTIVE_LOW - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - - s_axi - - axi_lite - 0 - 65536 - 0 - - - - - - - xilinx_anylanguagebehavioralsimulation - Simulation - :vivado.xilinx.com:simulation - axi_spi_engine - - xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset - - - xilinx_anylanguagebehavioralsimulation_analog_com_user_util_axis_fifo_1_0__ref_view_fileset - - - xilinx_anylanguagebehavioralsimulation_view_fileset - - - - GENtimestamp - Sun Sep 29 08:31:28 UTC 2024 - - - outputProductCRC - 9:9f992344 - - - - - xilinx_anylanguagesynthesis - Synthesis - :vivado.xilinx.com:synthesis - axi_spi_engine - - xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset - - - xilinx_anylanguagesynthesis_analog_com_user_util_axis_fifo_1_0__ref_view_fileset - - - xilinx_anylanguagesynthesis_view_fileset - - - - GENtimestamp - Sun Sep 29 08:31:28 UTC 2024 - - - outputProductCRC - 9:08061356 - - - - - xilinx_externalfiles - External Files - :vivado.xilinx.com:external.files - - xilinx_externalfiles_view_fileset - - - - GENtimestamp - Sun Sep 29 08:31:49 UTC 2024 - - - outputProductCRC - 9:08061356 - - - - - xilinx_synthesisconstraints - Synthesis Constraints - :vivado.xilinx.com:synthesis.constraints - - - outputProductCRC - 9:08061356 - - - - - xilinx_verilogsimulationwrapper - Verilog Simulation Wrapper - verilogSource:vivado.xilinx.com:simulation.wrapper - verilog - system_bd_axi_spi_engine_0_0 - - xilinx_verilogsimulationwrapper_view_fileset - - - - GENtimestamp - Sun Sep 29 08:31:28 UTC 2024 - - - outputProductCRC - 9:9f992344 - - - - - xilinx_verilogsynthesiswrapper - Verilog Synthesis Wrapper - verilogSource:vivado.xilinx.com:synthesis.wrapper - verilog - system_bd_axi_spi_engine_0_0 - - xilinx_verilogsynthesiswrapper_view_fileset - - - - GENtimestamp - Sun Sep 29 08:31:28 UTC 2024 - - - outputProductCRC - 9:08061356 - - - - - - - s_axi_aclk - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - true - - - - - - s_axi_aresetn - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - true - - - - - - s_axi_awvalid - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - true - - - - - - s_axi_awaddr - - in - - 15 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - true - - - - - - s_axi_awready - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - true - - - - - - s_axi_awprot - - in - - 2 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - true - - - - - - s_axi_wvalid - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - true - - - - - - s_axi_wdata - - in - - 31 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - true - - - - - - s_axi_wstrb - - in - - 3 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - true - - - - - - s_axi_wready - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - true - - - - - - s_axi_bvalid - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - true - - - - - - s_axi_bresp - - out - - 1 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - true - - - - - - s_axi_bready - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - true - - - - - - s_axi_arvalid - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - true - - - - - - s_axi_araddr - - in - - 15 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - true - - - - - - s_axi_arready - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - true - - - - - - s_axi_arprot - - in - - 2 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - true - - - - - - s_axi_rvalid - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - true - - - - - - s_axi_rready - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - true - - - - - - s_axi_rresp - - out - - 1 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - true - - - - - - s_axi_rdata - - out - - 31 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - true - - - - - - up_clk - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - up_rstn - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - up_wreq - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - up_waddr - - in - - 13 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - up_wdata - - in - - 31 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - up_wack - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - - false - - - - - - up_rreq - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - up_raddr - - in - - 13 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - up_rdata - - out - - 31 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - - false - - - - - - up_rack - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - - false - - - - - - irq - - out - - - reg - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - spi_clk - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - spi_resetn - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - cmd_ready - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - cmd_valid - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - cmd_data - - out - - 15 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - sdo_data_ready - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - sdo_data_valid - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - sdo_data - - out - - 7 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - sdi_data_ready - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - sdi_data_valid - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - sdi_data - - in - - 7 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - sync_ready - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - sync_valid - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - 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NUM_OFFLOAD - Num Offload - 0 - - - OFFLOAD0_CMD_MEM_ADDRESS_WIDTH - Offload0 Cmd Mem Address Width - 4 - - - - false - - - - - - OFFLOAD0_SDO_MEM_ADDRESS_WIDTH - Offload0 Sdo Mem Address Width - 4 - - - - false - - - - - - ID - Id - 0 - - - DATA_WIDTH - Data Width - 8 - - - NUM_OF_SDI - Num Of Sdi - 1 - - - - - - choice_list_9d8b0d81 - ACTIVE_HIGH - ACTIVE_LOW - - - choice_pairs_a1d277e1 - 0 - 1 - - - - - xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset - - ../../ipshared/cb53/sync_bits.v - verilogSource - - - ../../ipshared/cb53/sync_data.v - verilogSource - - - ../../ipshared/cb53/sync_event.v - verilogSource - - - ../../ipshared/cb53/sync_gray.v - verilogSource - - - - - - - - - - - xilinx_anylanguagebehavioralsimulation_analog_com_user_util_axis_fifo_1_0__ref_view_fileset - - ../../ipshared/common/ad_mem.v - verilogSource - - - ../../ipshared/cf62/address_gray_pipelined.v - verilogSource - - - ../../ipshared/cf62/address_sync.v - verilogSource - - - ../../ipshared/cf62/util_axis_fifo.v - verilogSource - - - - - - - - - - - xilinx_anylanguagebehavioralsimulation_view_fileset - - ../../common/ad_rst.v - verilogSource - - - ../../common/up_axi.v - verilogSource - - - ../../ipshared/1cb1/axi_spi_engine.v - verilogSource - - - - xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset - - ../../ipshared/cb53/sync_bits.v - verilogSource - - - ../../ipshared/cb53/sync_data.v - verilogSource - - - ../../ipshared/cb53/sync_event.v - verilogSource - - - ../../ipshared/cb53/sync_gray.v - verilogSource - - - - - - - - - - - xilinx_anylanguagesynthesis_analog_com_user_util_axis_fifo_1_0__ref_view_fileset - - ../../ipshared/common/ad_mem.v - verilogSource - - - ../../ipshared/cf62/address_gray_pipelined.v - verilogSource - - - ../../ipshared/cf62/address_sync.v - verilogSource - - - ../../ipshared/cf62/util_axis_fifo.v - verilogSource - - - - - - - - - - - xilinx_anylanguagesynthesis_view_fileset - - system_bd_axi_spi_engine_0_0_constr.xdc - xdc - - processing_order - late - - - - ../../xilinx/common/ad_rst_constr.xdc - xdc - - - ../../common/ad_rst.v - verilogSource - - - ../../common/up_axi.v - verilogSource - - - ../../ipshared/1cb1/axi_spi_engine.v - verilogSource - - - - xilinx_externalfiles_view_fileset - - system_bd_axi_spi_engine_0_0.dcp - dcp - USED_IN_implementation - USED_IN_synthesis - xil_defaultlib - - - system_bd_axi_spi_engine_0_0_stub.v - verilogSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - system_bd_axi_spi_engine_0_0_stub.vhdl - vhdlSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - system_bd_axi_spi_engine_0_0_sim_netlist.v - verilogSource - USED_IN_simulation - USED_IN_single_language - xil_defaultlib - - - system_bd_axi_spi_engine_0_0_sim_netlist.vhdl - vhdlSource - USED_IN_simulation - USED_IN_single_language - xil_defaultlib - - - - xilinx_verilogsimulationwrapper_view_fileset - - sim/system_bd_axi_spi_engine_0_0.v - verilogSource - xil_defaultlib - - - - xilinx_verilogsynthesiswrapper_view_fileset - - synth/system_bd_axi_spi_engine_0_0.v - verilogSource - xil_defaultlib - - - - axi_spi_engine_v1_0 - - - CMD_FIFO_ADDRESS_WIDTH - Command FIFO address width - 4 - - - SYNC_FIFO_ADDRESS_WIDTH - SYNC FIFO address width - 4 - - - SDO_FIFO_ADDRESS_WIDTH - MOSI FIFO address width - 5 - - - SDI_FIFO_ADDRESS_WIDTH - MISO FIFO address width - 5 - - - MM_IF_TYPE - Memory Mapped Interface Type - 0 - - - ASYNC_SPI_CLK - Asynchronous core clock - false - - - NUM_OFFLOAD - Number of offloads - 0 - - - OFFLOAD0_CMD_MEM_ADDRESS_WIDTH - Offload command FIFO address width - 4 - - - - false - - - - - - OFFLOAD0_SDO_MEM_ADDRESS_WIDTH - Offload MOSI FIFO address width - 4 - - - - false - - - - - - ID - Core ID - 0 - - - DATA_WIDTH - Parallel data width - 8 - - - NUM_OF_SDI - Number of MISO lines - 1 - - - Component_Name - system_bd_axi_spi_engine_0_0 - - - - - axi_spi_engine_v1_0 - package_project - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2019.1.3 - - - - - - - diff --git a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0_constr.xdc b/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0_constr.xdc deleted file mode 100644 index 8b13789..0000000 --- a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0_constr.xdc +++ /dev/null @@ -1 +0,0 @@ - diff --git a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0_sim_netlist.v b/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0_sim_netlist.v deleted file mode 100644 index 7d2ca7b..0000000 --- a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0_sim_netlist.v +++ /dev/null @@ -1,6411 +0,0 @@ -// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -// -------------------------------------------------------------------------------- -// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 -// Date : Sun Sep 29 16:31:49 2024 -// Host : gatsby-dev running 64-bit Red Hat Enterprise Linux release 8.10 (Ootpa) -// Command : write_verilog -force -mode funcsim -// /home/josh/Workspace/CX9261A/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0_sim_netlist.v -// Design : system_bd_axi_spi_engine_0_0 -// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified -// or synthesized. This netlist cannot be used for SDF annotated simulation. -// Device : xc7z045ffg900-2 -// -------------------------------------------------------------------------------- -`timescale 1 ps / 1 ps - -(* CHECK_LICENSE_TYPE = "system_bd_axi_spi_engine_0_0,axi_spi_engine,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* IP_DEFINITION_SOURCE = "package_project" *) -(* X_CORE_INFO = "axi_spi_engine,Vivado 2019.1.3" *) -(* NotValidForBitStream *) -module system_bd_axi_spi_engine_0_0 - (s_axi_aclk, - s_axi_aresetn, - s_axi_awvalid, - s_axi_awaddr, - s_axi_awready, - s_axi_awprot, - s_axi_wvalid, - s_axi_wdata, - s_axi_wstrb, - s_axi_wready, - s_axi_bvalid, - s_axi_bresp, - s_axi_bready, - s_axi_arvalid, - s_axi_araddr, - s_axi_arready, - s_axi_arprot, - s_axi_rvalid, - s_axi_rready, - s_axi_rresp, - s_axi_rdata, - irq, - spi_clk, - spi_resetn, - cmd_ready, - cmd_valid, - cmd_data, - sdo_data_ready, - sdo_data_valid, - sdo_data, - sdi_data_ready, - sdi_data_valid, - sdi_data, - sync_ready, - sync_valid, - sync_data); - (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 s_axi_aclk CLK, xilinx.com:signal:clock:1.0 spi_engine_offload_ctrl0_s_axi_signal_clock CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi_aclk, ASSOCIATED_BUSIF s_axi, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0, XIL_INTERFACENAME spi_engine_offload_ctrl0_s_axi_signal_clock, ASSOCIATED_BUSIF spi_engine_offload_ctrl0:s_axi, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *) input s_axi_aclk; - (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 s_axi_aresetn RST, xilinx.com:signal:reset:1.0 spi_engine_offload_ctrl0_s_axi_signal_reset RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0, XIL_INTERFACENAME spi_engine_offload_ctrl0_s_axi_signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input s_axi_aresetn; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWVALID" *) input s_axi_awvalid; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWADDR" *) input [15:0]s_axi_awaddr; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWREADY" *) output s_axi_awready; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWPROT" *) input [2:0]s_axi_awprot; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WVALID" *) input s_axi_wvalid; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WDATA" *) input [31:0]s_axi_wdata; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WSTRB" *) input [3:0]s_axi_wstrb; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WREADY" *) output s_axi_wready; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BVALID" *) output s_axi_bvalid; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BRESP" *) output [1:0]s_axi_bresp; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BREADY" *) input s_axi_bready; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARVALID" *) input s_axi_arvalid; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARADDR" *) input [15:0]s_axi_araddr; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARREADY" *) output s_axi_arready; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARPROT" *) input [2:0]s_axi_arprot; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RVALID" *) output s_axi_rvalid; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RREADY" *) input s_axi_rready; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RRESP" *) output [1:0]s_axi_rresp; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RDATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 50000000, ID_WIDTH 0, ADDR_WIDTH 16, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) output [31:0]s_axi_rdata; - output irq; - (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 spi_engine_ctrl_signal_clock CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME spi_engine_ctrl_signal_clock, ASSOCIATED_BUSIF spi_engine_ctrl, ASSOCIATED_RESET spi_resetn, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *) input spi_clk; - (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 spi_engine_ctrl_signal_reset RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME spi_engine_ctrl_signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) output spi_resetn; - (* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl CMD_READY" *) input cmd_ready; - (* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl CMD_VALID" *) output cmd_valid; - (* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl CMD_DATA" *) output [15:0]cmd_data; - (* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDO_READY" *) input sdo_data_ready; - (* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDO_VALID" *) output sdo_data_valid; - (* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDO_DATA" *) output [7:0]sdo_data; - (* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDI_READY" *) output sdi_data_ready; - (* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDI_VALID" *) input sdi_data_valid; - (* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDI_DATA" *) input [7:0]sdi_data; - (* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SYNC_READY" *) output sync_ready; - (* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SYNC_VALID" *) input sync_valid; - (* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SYNC_DATA" *) input [7:0]sync_data; - - wire [15:0]cmd_data; - wire cmd_ready; - wire cmd_valid; - wire irq; - wire s_axi_aclk; - wire [15:0]s_axi_araddr; - wire s_axi_aresetn; - wire [2:0]s_axi_arprot; - wire s_axi_arready; - wire s_axi_arvalid; - wire [15:0]s_axi_awaddr; - wire [2:0]s_axi_awprot; - wire s_axi_awready; - wire s_axi_awvalid; - wire s_axi_bready; - wire [1:0]s_axi_bresp; - wire s_axi_bvalid; - wire [31:0]s_axi_rdata; - wire s_axi_rready; - wire [1:0]s_axi_rresp; - wire s_axi_rvalid; - wire [31:0]s_axi_wdata; - wire s_axi_wready; - wire [3:0]s_axi_wstrb; - wire s_axi_wvalid; - wire [7:0]sdi_data; - wire sdi_data_ready; - wire sdi_data_valid; - wire [7:0]sdo_data; - wire sdo_data_ready; - wire sdo_data_valid; - wire spi_clk; - wire spi_resetn; - wire [7:0]sync_data; - wire sync_ready; - wire sync_valid; - wire NLW_inst_offload0_cmd_wr_en_UNCONNECTED; - wire NLW_inst_offload0_enable_UNCONNECTED; - wire NLW_inst_offload0_mem_reset_UNCONNECTED; - wire NLW_inst_offload0_sdo_wr_en_UNCONNECTED; - wire NLW_inst_offload_sync_ready_UNCONNECTED; - wire NLW_inst_up_rack_UNCONNECTED; - wire NLW_inst_up_wack_UNCONNECTED; - wire [15:0]NLW_inst_offload0_cmd_wr_data_UNCONNECTED; - wire [7:0]NLW_inst_offload0_sdo_wr_data_UNCONNECTED; - wire [31:0]NLW_inst_up_rdata_UNCONNECTED; - - (* ASYNC_SPI_CLK = "1'b0" *) - (* CMD_FIFO_ADDRESS_WIDTH = "4" *) - (* DATA_WIDTH = "16'b0000000000001000" *) - (* ID = "0" *) - (* MM_IF_TYPE = "0" *) - (* NUM_OFFLOAD = "0" *) - (* NUM_OF_SDI = "8'b00000001" *) - (* OFFLOAD0_CMD_MEM_ADDRESS_WIDTH = "4" *) - (* OFFLOAD0_SDO_MEM_ADDRESS_WIDTH = "4" *) - (* PCORE_VERSION = "65649" *) - (* SDI_FIFO_ADDRESS_WIDTH = "5" *) - (* SDO_FIFO_ADDRESS_WIDTH = "5" *) - (* SYNC_FIFO_ADDRESS_WIDTH = "4" *) - (* S_AXI = "0" *) - (* UP_FIFO = "1" *) - system_bd_axi_spi_engine_0_0_axi_spi_engine inst - (.cmd_data(cmd_data), - .cmd_ready(cmd_ready), - .cmd_valid(cmd_valid), - .irq(irq), - .offload0_cmd_wr_data(NLW_inst_offload0_cmd_wr_data_UNCONNECTED[15:0]), - .offload0_cmd_wr_en(NLW_inst_offload0_cmd_wr_en_UNCONNECTED), - .offload0_enable(NLW_inst_offload0_enable_UNCONNECTED), - .offload0_enabled(1'b0), - .offload0_mem_reset(NLW_inst_offload0_mem_reset_UNCONNECTED), - .offload0_sdo_wr_data(NLW_inst_offload0_sdo_wr_data_UNCONNECTED[7:0]), - .offload0_sdo_wr_en(NLW_inst_offload0_sdo_wr_en_UNCONNECTED), - .offload_sync_data({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .offload_sync_ready(NLW_inst_offload_sync_ready_UNCONNECTED), - .offload_sync_valid(1'b0), - .s_axi_aclk(s_axi_aclk), - .s_axi_araddr(s_axi_araddr), - .s_axi_aresetn(s_axi_aresetn), - .s_axi_arprot(s_axi_arprot), - .s_axi_arready(s_axi_arready), - .s_axi_arvalid(s_axi_arvalid), - .s_axi_awaddr(s_axi_awaddr), - .s_axi_awprot(s_axi_awprot), - .s_axi_awready(s_axi_awready), - .s_axi_awvalid(s_axi_awvalid), - .s_axi_bready(s_axi_bready), - .s_axi_bresp(s_axi_bresp), - .s_axi_bvalid(s_axi_bvalid), - .s_axi_rdata(s_axi_rdata), - .s_axi_rready(s_axi_rready), - .s_axi_rresp(s_axi_rresp), - .s_axi_rvalid(s_axi_rvalid), - .s_axi_wdata(s_axi_wdata), - .s_axi_wready(s_axi_wready), - .s_axi_wstrb(s_axi_wstrb), - .s_axi_wvalid(s_axi_wvalid), - .sdi_data(sdi_data), - .sdi_data_ready(sdi_data_ready), - .sdi_data_valid(sdi_data_valid), - .sdo_data(sdo_data), - .sdo_data_ready(sdo_data_ready), - .sdo_data_valid(sdo_data_valid), - .spi_clk(spi_clk), - .spi_resetn(spi_resetn), - .sync_data(sync_data), - .sync_ready(sync_ready), - .sync_valid(sync_valid), - .up_clk(1'b0), - .up_rack(NLW_inst_up_rack_UNCONNECTED), - .up_raddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .up_rdata(NLW_inst_up_rdata_UNCONNECTED[31:0]), - .up_rreq(1'b0), - .up_rstn(1'b0), - .up_wack(NLW_inst_up_wack_UNCONNECTED), - .up_waddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .up_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .up_wreq(1'b0)); -endmodule - -(* ASYNC_SPI_CLK = "1'b0" *) (* CMD_FIFO_ADDRESS_WIDTH = "4" *) (* DATA_WIDTH = "16'b0000000000001000" *) -(* ID = "0" *) (* MM_IF_TYPE = "0" *) (* NUM_OFFLOAD = "0" *) -(* NUM_OF_SDI = "8'b00000001" *) (* OFFLOAD0_CMD_MEM_ADDRESS_WIDTH = "4" *) (* OFFLOAD0_SDO_MEM_ADDRESS_WIDTH = "4" *) -(* ORIG_REF_NAME = "axi_spi_engine" *) (* PCORE_VERSION = "65649" *) (* SDI_FIFO_ADDRESS_WIDTH = "5" *) -(* SDO_FIFO_ADDRESS_WIDTH = "5" *) (* SYNC_FIFO_ADDRESS_WIDTH = "4" *) (* S_AXI = "0" *) -(* UP_FIFO = "1" *) -module system_bd_axi_spi_engine_0_0_axi_spi_engine - (s_axi_aclk, - s_axi_aresetn, - s_axi_awvalid, - s_axi_awaddr, - s_axi_awready, - s_axi_awprot, - s_axi_wvalid, - s_axi_wdata, - s_axi_wstrb, - s_axi_wready, - s_axi_bvalid, - s_axi_bresp, - s_axi_bready, - s_axi_arvalid, - s_axi_araddr, - s_axi_arready, - s_axi_arprot, - s_axi_rvalid, - s_axi_rready, - s_axi_rresp, - s_axi_rdata, - up_clk, - up_rstn, - up_wreq, - up_waddr, - up_wdata, - up_wack, - up_rreq, - up_raddr, - up_rdata, - up_rack, - irq, - spi_clk, - spi_resetn, - cmd_ready, - cmd_valid, - cmd_data, - sdo_data_ready, - sdo_data_valid, - sdo_data, - sdi_data_ready, - sdi_data_valid, - sdi_data, - sync_ready, - sync_valid, - sync_data, - offload0_cmd_wr_en, - offload0_cmd_wr_data, - offload0_sdo_wr_en, - offload0_sdo_wr_data, - offload0_mem_reset, - offload0_enable, - offload0_enabled, - offload_sync_ready, - offload_sync_valid, - offload_sync_data); - input s_axi_aclk; - input s_axi_aresetn; - input s_axi_awvalid; - input [15:0]s_axi_awaddr; - output s_axi_awready; - input [2:0]s_axi_awprot; - input s_axi_wvalid; - input [31:0]s_axi_wdata; - input [3:0]s_axi_wstrb; - output s_axi_wready; - output s_axi_bvalid; - output [1:0]s_axi_bresp; - input s_axi_bready; - input s_axi_arvalid; - input [15:0]s_axi_araddr; - output s_axi_arready; - input [2:0]s_axi_arprot; - output s_axi_rvalid; - input s_axi_rready; - output [1:0]s_axi_rresp; - output [31:0]s_axi_rdata; - input up_clk; - input up_rstn; - input up_wreq; - input [13:0]up_waddr; - input [31:0]up_wdata; - output up_wack; - input up_rreq; - input [13:0]up_raddr; - output [31:0]up_rdata; - output up_rack; - output irq; - input spi_clk; - output spi_resetn; - input cmd_ready; - output cmd_valid; - output [15:0]cmd_data; - input sdo_data_ready; - output sdo_data_valid; - output [7:0]sdo_data; - output sdi_data_ready; - input sdi_data_valid; - input [7:0]sdi_data; - output sync_ready; - input sync_valid; - input [7:0]sync_data; - output offload0_cmd_wr_en; - output [15:0]offload0_cmd_wr_data; - output offload0_sdo_wr_en; - output [7:0]offload0_sdo_wr_data; - output offload0_mem_reset; - output offload0_enable; - input offload0_enabled; - output offload_sync_ready; - input offload_sync_valid; - input [7:0]offload_sync_data; - - wire \ ; - wire \ ; - wire [15:0]cmd_data; - wire [4:1]cmd_fifo_room; - wire cmd_ready; - wire cmd_valid; - wire \i_address_sync/level_next1 ; - wire [0:0]\i_address_sync/level_reg ; - wire \i_address_sync/p_0_in ; - wire \i_address_sync/p_1_in ; - wire \i_address_sync/p_1_in_0 ; - wire i_cmd_fifo_n_0; - wire i_sdi_fifo_n_1; - wire i_sdi_fifo_n_8; - wire i_sdo_fifo_n_0; - wire i_sdo_fifo_n_2; - wire i_up_axi_n_0; - wire i_up_axi_n_10; - wire i_up_axi_n_12; - wire i_up_axi_n_18; - wire i_up_axi_n_21; - wire i_up_axi_n_22; - wire i_up_axi_n_23; - wire i_up_axi_n_24; - wire i_up_axi_n_25; - wire i_up_axi_n_26; - wire i_up_axi_n_27; - wire i_up_axi_n_28; - wire i_up_axi_n_29; - wire i_up_axi_n_30; - wire i_up_axi_n_31; - wire i_up_axi_n_32; - wire i_up_axi_n_33; - wire i_up_axi_n_34; - wire i_up_axi_n_35; - wire i_up_axi_n_36; - wire i_up_axi_n_37; - wire i_up_axi_n_38; - wire i_up_axi_n_39; - wire i_up_axi_n_40; - wire i_up_axi_n_41; - wire i_up_axi_n_42; - wire i_up_axi_n_43; - wire i_up_axi_n_44; - wire i_up_axi_n_45; - wire i_up_axi_n_46; - wire i_up_axi_n_49; - wire i_up_axi_n_50; - wire i_up_axi_n_51; - wire i_up_axi_n_52; - wire i_up_axi_n_53; - wire i_up_axi_n_54; - wire i_up_axi_n_55; - wire i_up_axi_n_56; - wire i_up_axi_n_89; - wire i_up_axi_n_90; - wire i_up_axi_n_91; - wire irq; - wire [7:0]m_axis_data; - wire [15:1]\^offload0_cmd_wr_data ; - wire offload0_cmd_wr_en; - wire offload0_enable; - wire offload0_enabled; - wire offload0_mem_reset; - wire [7:0]\^offload0_sdo_wr_data ; - wire offload0_sdo_wr_en; - wire [7:0]offload_sync_data; - wire [7:0]offload_sync_id; - wire offload_sync_valid; - wire s_axi_aclk; - wire [15:0]s_axi_araddr; - wire s_axi_aresetn; - wire s_axi_arready; - wire s_axi_arvalid; - wire [15:0]s_axi_awaddr; - wire s_axi_awready; - wire s_axi_awvalid; - wire s_axi_bready; - wire s_axi_bvalid; - wire [31:0]s_axi_rdata; - wire s_axi_rready; - wire s_axi_rvalid; - wire [31:0]s_axi_wdata; - wire s_axi_wready; - wire s_axi_wvalid; - wire s_mem_write; - wire s_mem_write__0; - wire [7:0]sdi_data; - wire sdi_data_ready; - wire sdi_data_valid; - wire [5:0]sdi_fifo_level; - wire [7:0]sdo_data; - wire sdo_data_ready; - wire sdo_data_valid; - wire [5:0]sdo_fifo_room; - wire spi_clk; - wire spi_resetn; - wire [7:0]sync_data; - wire [7:0]sync_id; - wire sync_valid; - wire \up_irq_mask_reg_n_0_[0] ; - wire \up_irq_mask_reg_n_0_[1] ; - wire \up_irq_mask_reg_n_0_[2] ; - wire \up_irq_mask_reg_n_0_[3] ; - wire [3:3]up_irq_source; - wire [2:0]up_irq_source__0; - wire up_rack_ff; - wire [4:2]up_raddr_s; - wire [31:0]up_rdata_ff; - wire up_rreq_s; - wire up_scratch; - wire \up_scratch_reg_n_0_[0] ; - wire \up_scratch_reg_n_0_[10] ; - wire \up_scratch_reg_n_0_[11] ; - wire \up_scratch_reg_n_0_[12] ; - wire \up_scratch_reg_n_0_[13] ; - wire \up_scratch_reg_n_0_[14] ; - wire \up_scratch_reg_n_0_[15] ; - wire \up_scratch_reg_n_0_[16] ; - wire \up_scratch_reg_n_0_[17] ; - wire \up_scratch_reg_n_0_[18] ; - wire \up_scratch_reg_n_0_[19] ; - wire \up_scratch_reg_n_0_[1] ; - wire \up_scratch_reg_n_0_[20] ; - wire \up_scratch_reg_n_0_[21] ; - wire \up_scratch_reg_n_0_[22] ; - wire \up_scratch_reg_n_0_[23] ; - wire \up_scratch_reg_n_0_[24] ; - wire \up_scratch_reg_n_0_[25] ; - wire \up_scratch_reg_n_0_[26] ; - wire \up_scratch_reg_n_0_[27] ; - wire \up_scratch_reg_n_0_[28] ; - wire \up_scratch_reg_n_0_[29] ; - wire \up_scratch_reg_n_0_[2] ; - wire \up_scratch_reg_n_0_[30] ; - wire \up_scratch_reg_n_0_[31] ; - wire \up_scratch_reg_n_0_[3] ; - wire \up_scratch_reg_n_0_[4] ; - wire \up_scratch_reg_n_0_[5] ; - wire \up_scratch_reg_n_0_[6] ; - wire \up_scratch_reg_n_0_[7] ; - wire \up_scratch_reg_n_0_[8] ; - wire \up_scratch_reg_n_0_[9] ; - wire up_sw_reset; - wire up_wack_ff; - wire [0:0]up_waddr_s; - wire [31:16]up_wdata_int; - wire up_wreq_s; - - assign offload0_cmd_wr_data[15:8] = \^offload0_cmd_wr_data [15:8]; - assign offload0_cmd_wr_data[7:3] = \^offload0_sdo_wr_data [7:3]; - assign offload0_cmd_wr_data[2:1] = \^offload0_cmd_wr_data [2:1]; - assign offload0_cmd_wr_data[0] = \^offload0_sdo_wr_data [0]; - assign offload0_sdo_wr_data[7:3] = \^offload0_sdo_wr_data [7:3]; - assign offload0_sdo_wr_data[2:1] = \^offload0_cmd_wr_data [2:1]; - assign offload0_sdo_wr_data[0] = \^offload0_sdo_wr_data [0]; - assign offload_sync_ready = \ ; - assign s_axi_bresp[1] = \ ; - assign s_axi_bresp[0] = \ ; - assign s_axi_rresp[1] = \ ; - assign s_axi_rresp[0] = \ ; - assign sync_ready = \ ; - assign up_rack = \ ; - assign up_rdata[31] = \ ; - assign up_rdata[30] = \ ; - assign up_rdata[29] = \ ; - assign up_rdata[28] = \ ; - assign up_rdata[27] = \ ; - assign up_rdata[26] = \ ; - assign up_rdata[25] = \ ; - assign up_rdata[24] = \ ; - assign up_rdata[23] = \ ; - assign up_rdata[22] = \ ; - assign up_rdata[21] = \ ; - assign up_rdata[20] = \ ; - assign up_rdata[19] = \ ; - assign up_rdata[18] = \ ; - assign up_rdata[17] = \ ; - assign up_rdata[16] = \ ; - assign up_rdata[15] = \ ; - assign up_rdata[14] = \ ; - assign up_rdata[13] = \ ; - assign up_rdata[12] = \ ; - assign up_rdata[11] = \ ; - assign up_rdata[10] = \ ; - assign up_rdata[9] = \ ; - assign up_rdata[8] = \ ; - assign up_rdata[7] = \ ; - assign up_rdata[6] = \ ; - assign up_rdata[5] = \ ; - assign up_rdata[4] = \ ; - assign up_rdata[3] = \ ; - assign up_rdata[2] = \ ; - assign up_rdata[1] = \ ; - assign up_rdata[0] = \ ; - assign up_wack = \ ; - GND GND - (.G(\ )); - VCC VCC - (.P(\ )); - system_bd_axi_spi_engine_0_0_util_axis_fifo i_cmd_fifo - (.Q(up_waddr_s), - .cmd_data(cmd_data), - .cmd_ready(cmd_ready), - .\level_reg[0] (\i_address_sync/level_reg ), - .\level_reg[0]_0 (i_up_axi_n_10), - .m_axis_valid_reg(cmd_valid), - .offload0_cmd_wr_data({\^offload0_cmd_wr_data [15:8],\^offload0_sdo_wr_data [7:3],\^offload0_cmd_wr_data [2:1],\^offload0_sdo_wr_data [0]}), - .p_1_in(\i_address_sync/p_1_in ), - .\room_reg[4] (cmd_fifo_room), - .s_axi_aclk(s_axi_aclk), - .s_axis_ready_reg(i_cmd_fifo_n_0), - .s_mem_write(s_mem_write), - .spi_clk(spi_clk), - .up_irq_source(up_irq_source__0[0]), - .up_sw_reset(up_sw_reset)); - system_bd_axi_spi_engine_0_0_util_axis_fifo__parameterized0 i_sdi_fifo - (.DI(i_up_axi_n_55), - .Q(sdi_fifo_level), - .irq_reg({\up_irq_mask_reg_n_0_[3] ,\up_irq_mask_reg_n_0_[2] ,\up_irq_mask_reg_n_0_[1] ,\up_irq_mask_reg_n_0_[0] }), - .irq_reg_0(up_irq_source), - .\level_reg[4] (up_irq_source__0[2]), - .m_axis_data(m_axis_data), - .m_axis_valid_reg(i_sdi_fifo_n_1), - .m_axis_valid_reg_0(\i_address_sync/level_next1 ), - .p_0_in(\i_address_sync/p_0_in ), - .s_axi_aclk(s_axi_aclk), - .s_axis_ready_reg(sdi_data_ready), - .sdi_data(sdi_data), - .sdi_data_valid(sdi_data_valid), - .spi_clk(spi_clk), - .\up_irq_mask_reg[0] (i_sdi_fifo_n_8), - .up_irq_source(up_irq_source__0[1:0]), - .up_sw_reset(up_sw_reset)); - system_bd_axi_spi_engine_0_0_util_axis_fifo__parameterized0_0 i_sdo_fifo - (.E(\i_address_sync/p_1_in_0 ), - .Q(\up_irq_mask_reg_n_0_[1] ), - .\level_reg[0] (up_waddr_s), - .\level_reg[0]_0 (i_up_axi_n_10), - .m_axis_valid_reg(sdo_data_valid), - .offload0_cmd_wr_data({\^offload0_sdo_wr_data [7:3],\^offload0_cmd_wr_data [2:1],\^offload0_sdo_wr_data [0]}), - .\room_reg[5] ({sdo_fifo_room[5:2],sdo_fifo_room[0]}), - .s_axi_aclk(s_axi_aclk), - .s_axis_ready_reg(i_sdo_fifo_n_0), - .s_mem_write(s_mem_write__0), - .sdo_data(sdo_data), - .sdo_data_ready(sdo_data_ready), - .spi_clk(spi_clk), - .\up_irq_mask_reg[1] (i_sdo_fifo_n_2), - .up_irq_source(up_irq_source__0[1]), - .\up_rdata_ff_reg[1] (offload_sync_id[1]), - .\up_rdata_ff_reg[1]_0 ({up_raddr_s[4],up_raddr_s[2]}), - .up_sw_reset(up_sw_reset)); - system_bd_axi_spi_engine_0_0_up_axi i_up_axi - (.DI(i_up_axi_n_55), - .E(i_up_axi_n_12), - .Q(up_waddr_s), - .m_axis_data(m_axis_data), - .\m_axis_raddr_reg[0] (i_sdi_fifo_n_1), - .offload0_cmd_wr_en(offload0_cmd_wr_en), - .offload0_enable(offload0_enable), - .offload0_enabled(offload0_enabled), - .offload0_mem_reset(offload0_mem_reset), - .offload0_sdo_wr_en(offload0_sdo_wr_en), - .p_0_in(\i_address_sync/p_0_in ), - .p_1_in(\i_address_sync/p_1_in ), - .s_axi_aclk(s_axi_aclk), - .s_axi_araddr(s_axi_araddr[15:2]), - .s_axi_aresetn(s_axi_aresetn), - .s_axi_aresetn_0(i_up_axi_n_0), - .s_axi_arready(s_axi_arready), - .s_axi_arvalid(s_axi_arvalid), - .s_axi_awaddr(s_axi_awaddr[15:2]), - .s_axi_awready(s_axi_awready), - .s_axi_awvalid(s_axi_awvalid), - .s_axi_bready(s_axi_bready), - .s_axi_bvalid(s_axi_bvalid), - .s_axi_rdata(s_axi_rdata), - .s_axi_rready(s_axi_rready), - .s_axi_wdata(s_axi_wdata), - .s_axi_wready(s_axi_wready), - .s_axi_wvalid(s_axi_wvalid), - .s_axis_ready_reg(s_mem_write__0), - .s_axis_ready_reg_0(\i_address_sync/p_1_in_0 ), - .\s_axis_waddr_reg[0] (i_cmd_fifo_n_0), - .\s_axis_waddr_reg[0]_0 (i_sdo_fifo_n_0), - .s_mem_write(s_mem_write), - .sdi_data_ready(sdi_data_ready), - .sdi_data_valid(sdi_data_valid), - .sdi_data_valid_0(\i_address_sync/level_next1 ), - .sync_id_pending_reg(up_irq_source), - .sync_valid(sync_valid), - .up_axi_rvalid_int_reg_0(s_axi_rvalid), - .up_irq_source(up_irq_source__0), - .up_rack_ff(up_rack_ff), - .\up_raddr_int_reg[0]_0 (i_up_axi_n_21), - .\up_raddr_int_reg[0]_1 (i_up_axi_n_22), - .\up_raddr_int_reg[3]_0 (i_up_axi_n_23), - .\up_raddr_int_reg[3]_1 (i_up_axi_n_49), - .\up_raddr_int_reg[3]_2 (i_up_axi_n_50), - .\up_raddr_int_reg[3]_3 (i_up_axi_n_51), - .\up_raddr_int_reg[3]_4 (i_up_axi_n_52), - .\up_raddr_int_reg[4]_0 ({up_raddr_s[4],up_raddr_s[2]}), - .\up_raddr_int_reg[5]_0 (i_up_axi_n_18), - .\up_raddr_int_reg[6]_0 (i_up_axi_n_54), - .\up_raddr_int_reg[9]_0 (i_up_axi_n_53), - .up_rdata_ff(up_rdata_ff), - .\up_rdata_ff[0]_i_8_0 (\i_address_sync/level_reg ), - .\up_rdata_ff[3]_i_3_0 ({\up_irq_mask_reg_n_0_[3] ,\up_irq_mask_reg_n_0_[2] ,\up_irq_mask_reg_n_0_[1] ,\up_irq_mask_reg_n_0_[0] }), - .\up_rdata_ff_reg[1] (i_sdo_fifo_n_2), - .\up_rdata_ff_reg[31] ({\up_scratch_reg_n_0_[31] ,\up_scratch_reg_n_0_[30] ,\up_scratch_reg_n_0_[29] ,\up_scratch_reg_n_0_[28] ,\up_scratch_reg_n_0_[27] ,\up_scratch_reg_n_0_[26] ,\up_scratch_reg_n_0_[25] ,\up_scratch_reg_n_0_[24] ,\up_scratch_reg_n_0_[23] ,\up_scratch_reg_n_0_[22] ,\up_scratch_reg_n_0_[21] ,\up_scratch_reg_n_0_[20] ,\up_scratch_reg_n_0_[19] ,\up_scratch_reg_n_0_[18] ,\up_scratch_reg_n_0_[17] ,\up_scratch_reg_n_0_[16] ,\up_scratch_reg_n_0_[15] ,\up_scratch_reg_n_0_[14] ,\up_scratch_reg_n_0_[13] ,\up_scratch_reg_n_0_[12] ,\up_scratch_reg_n_0_[11] ,\up_scratch_reg_n_0_[10] ,\up_scratch_reg_n_0_[9] ,\up_scratch_reg_n_0_[8] ,\up_scratch_reg_n_0_[7] ,\up_scratch_reg_n_0_[6] ,\up_scratch_reg_n_0_[5] ,\up_scratch_reg_n_0_[4] ,\up_scratch_reg_n_0_[3] ,\up_scratch_reg_n_0_[2] ,\up_scratch_reg_n_0_[1] ,\up_scratch_reg_n_0_[0] }), - .\up_rdata_ff_reg[4] (cmd_fifo_room), - .\up_rdata_ff_reg[5] (sdi_fifo_level), - .\up_rdata_ff_reg[5]_0 ({sdo_fifo_room[5:2],sdo_fifo_room[0]}), - .\up_rdata_ff_reg[7] ({offload_sync_id[7:2],offload_sync_id[0]}), - .\up_rdata_ff_reg[7]_0 (sync_id), - .up_rreq_s(up_rreq_s), - .\up_scratch_reg[10] (i_up_axi_n_26), - .\up_scratch_reg[11] (i_up_axi_n_27), - .\up_scratch_reg[12] (i_up_axi_n_28), - .\up_scratch_reg[13] (i_up_axi_n_29), - .\up_scratch_reg[14] (i_up_axi_n_30), - .\up_scratch_reg[15] (i_up_axi_n_31), - .\up_scratch_reg[17] (i_up_axi_n_32), - .\up_scratch_reg[18] (i_up_axi_n_33), - .\up_scratch_reg[19] (i_up_axi_n_34), - .\up_scratch_reg[20] (i_up_axi_n_35), - .\up_scratch_reg[21] (i_up_axi_n_36), - .\up_scratch_reg[22] (i_up_axi_n_37), - .\up_scratch_reg[23] (i_up_axi_n_38), - .\up_scratch_reg[24] (i_up_axi_n_39), - .\up_scratch_reg[25] (i_up_axi_n_40), - .\up_scratch_reg[26] (i_up_axi_n_41), - .\up_scratch_reg[27] (i_up_axi_n_42), - .\up_scratch_reg[28] (i_up_axi_n_43), - .\up_scratch_reg[29] (i_up_axi_n_44), - .\up_scratch_reg[30] (i_up_axi_n_45), - .\up_scratch_reg[31] (i_up_axi_n_46), - .\up_scratch_reg[8] (i_up_axi_n_24), - .\up_scratch_reg[9] (i_up_axi_n_25), - .up_sw_reset(up_sw_reset), - .up_wack_ff(up_wack_ff), - .\up_waddr_int_reg[0]_0 (i_up_axi_n_89), - .\up_waddr_int_reg[2]_0 (up_scratch), - .\up_waddr_int_reg[4]_0 (i_up_axi_n_10), - .\up_wdata_int_reg[0]_0 (i_up_axi_n_56), - .\up_wdata_int_reg[0]_1 (i_up_axi_n_90), - .\up_wdata_int_reg[0]_2 (i_up_axi_n_91), - .\up_wdata_int_reg[31]_0 ({up_wdata_int,\^offload0_cmd_wr_data [15:8],\^offload0_sdo_wr_data [7:3],\^offload0_cmd_wr_data [2:1],\^offload0_sdo_wr_data [0]}), - .up_wreq_s(up_wreq_s)); - FDRE irq_reg - (.C(s_axi_aclk), - .CE(1'b1), - .D(i_sdi_fifo_n_8), - .Q(irq), - .R(i_up_axi_n_0)); - FDRE offload0_enable_reg_reg - (.C(s_axi_aclk), - .CE(1'b1), - .D(i_up_axi_n_90), - .Q(offload0_enable), - .R(up_sw_reset)); - FDRE offload0_mem_reset_reg_reg - (.C(s_axi_aclk), - .CE(1'b1), - .D(i_up_axi_n_91), - .Q(offload0_mem_reset), - .R(up_sw_reset)); - FDRE #( - .INIT(1'b0)) - \offload_sync_id_reg[0] - (.C(s_axi_aclk), - .CE(offload_sync_valid), - .D(offload_sync_data[0]), - .Q(offload_sync_id[0]), - .R(up_sw_reset)); - FDRE #( - .INIT(1'b0)) - \offload_sync_id_reg[1] - (.C(s_axi_aclk), - .CE(offload_sync_valid), - .D(offload_sync_data[1]), - .Q(offload_sync_id[1]), - .R(up_sw_reset)); - FDRE #( - .INIT(1'b0)) - \offload_sync_id_reg[2] - (.C(s_axi_aclk), - .CE(offload_sync_valid), - .D(offload_sync_data[2]), - .Q(offload_sync_id[2]), - .R(up_sw_reset)); - FDRE #( - .INIT(1'b0)) - \offload_sync_id_reg[3] - (.C(s_axi_aclk), - .CE(offload_sync_valid), - .D(offload_sync_data[3]), - .Q(offload_sync_id[3]), - .R(up_sw_reset)); - FDRE #( - .INIT(1'b0)) - \offload_sync_id_reg[4] - (.C(s_axi_aclk), - .CE(offload_sync_valid), - .D(offload_sync_data[4]), - .Q(offload_sync_id[4]), - .R(up_sw_reset)); - FDRE #( - .INIT(1'b0)) - \offload_sync_id_reg[5] - (.C(s_axi_aclk), - .CE(offload_sync_valid), - .D(offload_sync_data[5]), - .Q(offload_sync_id[5]), - .R(up_sw_reset)); - FDRE #( - .INIT(1'b0)) - \offload_sync_id_reg[6] - (.C(s_axi_aclk), - .CE(offload_sync_valid), - .D(offload_sync_data[6]), - .Q(offload_sync_id[6]), - .R(up_sw_reset)); - FDRE #( - .INIT(1'b0)) - \offload_sync_id_reg[7] - (.C(s_axi_aclk), - .CE(offload_sync_valid), - .D(offload_sync_data[7]), - .Q(offload_sync_id[7]), - .R(up_sw_reset)); - LUT1 #( - .INIT(2'h1)) - spi_resetn_INST_0 - (.I0(up_sw_reset), - .O(spi_resetn)); - FDRE #( - .INIT(1'b0)) - sync_id_pending_reg - (.C(s_axi_aclk), - .CE(1'b1), - .D(i_up_axi_n_89), - .Q(up_irq_source), - .R(up_sw_reset)); - FDRE #( - .INIT(1'b0)) - \sync_id_reg[0] - (.C(s_axi_aclk), - .CE(sync_valid), - .D(sync_data[0]), - .Q(sync_id[0]), - .R(up_sw_reset)); - FDRE #( - .INIT(1'b0)) - \sync_id_reg[1] - (.C(s_axi_aclk), - .CE(sync_valid), - .D(sync_data[1]), - .Q(sync_id[1]), - .R(up_sw_reset)); - FDRE #( - .INIT(1'b0)) - \sync_id_reg[2] - (.C(s_axi_aclk), - .CE(sync_valid), - .D(sync_data[2]), - .Q(sync_id[2]), - .R(up_sw_reset)); - FDRE #( - .INIT(1'b0)) - \sync_id_reg[3] - (.C(s_axi_aclk), - .CE(sync_valid), - .D(sync_data[3]), - .Q(sync_id[3]), - .R(up_sw_reset)); - FDRE #( - .INIT(1'b0)) - \sync_id_reg[4] - (.C(s_axi_aclk), - .CE(sync_valid), - .D(sync_data[4]), - .Q(sync_id[4]), - .R(up_sw_reset)); - FDRE #( - .INIT(1'b0)) - \sync_id_reg[5] - (.C(s_axi_aclk), - .CE(sync_valid), - .D(sync_data[5]), - .Q(sync_id[5]), - .R(up_sw_reset)); - FDRE #( - .INIT(1'b0)) - \sync_id_reg[6] - (.C(s_axi_aclk), - .CE(sync_valid), - .D(sync_data[6]), - .Q(sync_id[6]), - .R(up_sw_reset)); - FDRE #( - .INIT(1'b0)) - \sync_id_reg[7] - (.C(s_axi_aclk), - .CE(sync_valid), - .D(sync_data[7]), - .Q(sync_id[7]), - .R(up_sw_reset)); - FDRE #( - .INIT(1'b0)) - \up_irq_mask_reg[0] - (.C(s_axi_aclk), - .CE(i_up_axi_n_12), - .D(\^offload0_sdo_wr_data [0]), - .Q(\up_irq_mask_reg_n_0_[0] ), - .R(up_sw_reset)); - FDRE #( - .INIT(1'b0)) - \up_irq_mask_reg[1] - (.C(s_axi_aclk), - .CE(i_up_axi_n_12), - .D(\^offload0_cmd_wr_data [1]), - .Q(\up_irq_mask_reg_n_0_[1] ), - .R(up_sw_reset)); - FDRE #( - .INIT(1'b0)) - \up_irq_mask_reg[2] - (.C(s_axi_aclk), - .CE(i_up_axi_n_12), - .D(\^offload0_cmd_wr_data [2]), - .Q(\up_irq_mask_reg_n_0_[2] ), - .R(up_sw_reset)); - FDRE #( - .INIT(1'b0)) - \up_irq_mask_reg[3] - (.C(s_axi_aclk), - .CE(i_up_axi_n_12), - .D(\^offload0_sdo_wr_data [3]), - .Q(\up_irq_mask_reg_n_0_[3] ), - .R(up_sw_reset)); - FDRE #( - .INIT(1'b0)) - up_rack_ff_reg - (.C(s_axi_aclk), - .CE(1'b1), - .D(up_rreq_s), - .Q(up_rack_ff), - .R(i_up_axi_n_0)); - FDRE #( - .INIT(1'b0)) - \up_rdata_ff_reg[0] - (.C(s_axi_aclk), - .CE(1'b1), - .D(i_up_axi_n_51), - .Q(up_rdata_ff[0]), - .R(i_up_axi_n_53)); - FDRE #( - .INIT(1'b0)) - \up_rdata_ff_reg[10] - (.C(s_axi_aclk), - .CE(1'b1), - .D(i_up_axi_n_26), - .Q(up_rdata_ff[10]), - .R(i_up_axi_n_53)); - FDRE #( - .INIT(1'b0)) - \up_rdata_ff_reg[11] - (.C(s_axi_aclk), - .CE(1'b1), - .D(i_up_axi_n_27), - .Q(up_rdata_ff[11]), - .R(i_up_axi_n_53)); - FDRE #( - .INIT(1'b0)) - \up_rdata_ff_reg[12] - (.C(s_axi_aclk), - .CE(1'b1), - .D(i_up_axi_n_28), - .Q(up_rdata_ff[12]), - .R(i_up_axi_n_53)); - FDRE #( - .INIT(1'b0)) - \up_rdata_ff_reg[13] - (.C(s_axi_aclk), - .CE(1'b1), - .D(i_up_axi_n_29), - .Q(up_rdata_ff[13]), - .R(i_up_axi_n_53)); - FDRE #( - .INIT(1'b0)) - \up_rdata_ff_reg[14] - (.C(s_axi_aclk), - .CE(1'b1), - .D(i_up_axi_n_30), - .Q(up_rdata_ff[14]), - .R(i_up_axi_n_53)); - FDRE #( - .INIT(1'b0)) - \up_rdata_ff_reg[15] - (.C(s_axi_aclk), - .CE(1'b1), - .D(i_up_axi_n_31), - .Q(up_rdata_ff[15]), - .R(i_up_axi_n_53)); - FDRE #( - .INIT(1'b0)) - \up_rdata_ff_reg[16] - (.C(s_axi_aclk), - .CE(1'b1), - .D(i_up_axi_n_54), - .Q(up_rdata_ff[16]), - .R(i_up_axi_n_53)); - FDRE #( - .INIT(1'b0)) - \up_rdata_ff_reg[17] - (.C(s_axi_aclk), - .CE(1'b1), - .D(i_up_axi_n_32), - .Q(up_rdata_ff[17]), - .R(i_up_axi_n_53)); - FDRE #( - .INIT(1'b0)) - \up_rdata_ff_reg[18] - (.C(s_axi_aclk), - .CE(1'b1), - .D(i_up_axi_n_33), - .Q(up_rdata_ff[18]), - .R(i_up_axi_n_53)); - FDRE #( - .INIT(1'b0)) - \up_rdata_ff_reg[19] - (.C(s_axi_aclk), - .CE(1'b1), - .D(i_up_axi_n_34), - .Q(up_rdata_ff[19]), - .R(i_up_axi_n_53)); - FDRE #( - .INIT(1'b0)) - \up_rdata_ff_reg[1] - (.C(s_axi_aclk), - .CE(1'b1), - .D(i_up_axi_n_49), - .Q(up_rdata_ff[1]), - .R(i_up_axi_n_53)); - FDRE #( - .INIT(1'b0)) - \up_rdata_ff_reg[20] - (.C(s_axi_aclk), - .CE(1'b1), - .D(i_up_axi_n_35), - .Q(up_rdata_ff[20]), - .R(i_up_axi_n_53)); - FDRE #( - .INIT(1'b0)) - \up_rdata_ff_reg[21] - (.C(s_axi_aclk), - .CE(1'b1), - .D(i_up_axi_n_36), - .Q(up_rdata_ff[21]), - .R(i_up_axi_n_53)); - FDRE #( - .INIT(1'b0)) - \up_rdata_ff_reg[22] - (.C(s_axi_aclk), - .CE(1'b1), - .D(i_up_axi_n_37), - .Q(up_rdata_ff[22]), - .R(i_up_axi_n_53)); - FDRE #( - .INIT(1'b0)) - \up_rdata_ff_reg[23] - (.C(s_axi_aclk), - .CE(1'b1), - .D(i_up_axi_n_38), - .Q(up_rdata_ff[23]), - .R(i_up_axi_n_53)); - FDRE #( - .INIT(1'b0)) - \up_rdata_ff_reg[24] - (.C(s_axi_aclk), - .CE(1'b1), - .D(i_up_axi_n_39), - .Q(up_rdata_ff[24]), - .R(i_up_axi_n_53)); - FDRE #( - .INIT(1'b0)) - \up_rdata_ff_reg[25] - (.C(s_axi_aclk), - .CE(1'b1), - .D(i_up_axi_n_40), - .Q(up_rdata_ff[25]), - .R(i_up_axi_n_53)); - FDRE #( - .INIT(1'b0)) - \up_rdata_ff_reg[26] - (.C(s_axi_aclk), - .CE(1'b1), - .D(i_up_axi_n_41), - .Q(up_rdata_ff[26]), - .R(i_up_axi_n_53)); - FDRE #( - .INIT(1'b0)) - \up_rdata_ff_reg[27] - (.C(s_axi_aclk), - .CE(1'b1), - .D(i_up_axi_n_42), - .Q(up_rdata_ff[27]), - .R(i_up_axi_n_53)); - FDRE #( - .INIT(1'b0)) - \up_rdata_ff_reg[28] - (.C(s_axi_aclk), - .CE(1'b1), - .D(i_up_axi_n_43), - .Q(up_rdata_ff[28]), - .R(i_up_axi_n_53)); - FDRE #( - .INIT(1'b0)) - \up_rdata_ff_reg[29] - (.C(s_axi_aclk), - .CE(1'b1), - .D(i_up_axi_n_44), - .Q(up_rdata_ff[29]), - .R(i_up_axi_n_53)); - FDRE #( - .INIT(1'b0)) - \up_rdata_ff_reg[2] - (.C(s_axi_aclk), - .CE(1'b1), - .D(i_up_axi_n_50), - .Q(up_rdata_ff[2]), - .R(i_up_axi_n_53)); - FDRE #( - .INIT(1'b0)) - \up_rdata_ff_reg[30] - (.C(s_axi_aclk), - .CE(1'b1), - .D(i_up_axi_n_45), - .Q(up_rdata_ff[30]), - .R(i_up_axi_n_53)); - FDRE #( - .INIT(1'b0)) - \up_rdata_ff_reg[31] - (.C(s_axi_aclk), - .CE(1'b1), - .D(i_up_axi_n_46), - .Q(up_rdata_ff[31]), - .R(i_up_axi_n_53)); - FDRE #( - .INIT(1'b0)) - \up_rdata_ff_reg[3] - (.C(s_axi_aclk), - .CE(1'b1), - .D(i_up_axi_n_18), - .Q(up_rdata_ff[3]), - .R(i_up_axi_n_53)); - FDRE #( - .INIT(1'b0)) - \up_rdata_ff_reg[4] - (.C(s_axi_aclk), - .CE(1'b1), - .D(i_up_axi_n_21), - .Q(up_rdata_ff[4]), - .R(i_up_axi_n_53)); - FDRE #( - .INIT(1'b0)) - \up_rdata_ff_reg[5] - (.C(s_axi_aclk), - .CE(1'b1), - .D(i_up_axi_n_22), - .Q(up_rdata_ff[5]), - .R(i_up_axi_n_53)); - FDRE #( - .INIT(1'b0)) - \up_rdata_ff_reg[6] - (.C(s_axi_aclk), - .CE(1'b1), - .D(i_up_axi_n_23), - .Q(up_rdata_ff[6]), - .R(i_up_axi_n_53)); - FDRE #( - .INIT(1'b0)) - \up_rdata_ff_reg[7] - (.C(s_axi_aclk), - .CE(1'b1), - .D(i_up_axi_n_52), - .Q(up_rdata_ff[7]), - .R(i_up_axi_n_53)); - FDRE #( - .INIT(1'b0)) - \up_rdata_ff_reg[8] - (.C(s_axi_aclk), - .CE(1'b1), - .D(i_up_axi_n_24), - .Q(up_rdata_ff[8]), - .R(i_up_axi_n_53)); - FDRE #( - .INIT(1'b0)) - \up_rdata_ff_reg[9] - (.C(s_axi_aclk), - .CE(1'b1), - .D(i_up_axi_n_25), - .Q(up_rdata_ff[9]), - .R(i_up_axi_n_53)); - FDRE #( - .INIT(1'b0)) - \up_scratch_reg[0] - (.C(s_axi_aclk), - .CE(up_scratch), - .D(\^offload0_sdo_wr_data [0]), - .Q(\up_scratch_reg_n_0_[0] ), - .R(i_up_axi_n_0)); - FDRE #( - .INIT(1'b0)) - \up_scratch_reg[10] - (.C(s_axi_aclk), - .CE(up_scratch), - .D(\^offload0_cmd_wr_data [10]), - .Q(\up_scratch_reg_n_0_[10] ), - .R(i_up_axi_n_0)); - FDRE #( - .INIT(1'b0)) - \up_scratch_reg[11] - (.C(s_axi_aclk), - .CE(up_scratch), - .D(\^offload0_cmd_wr_data [11]), - .Q(\up_scratch_reg_n_0_[11] ), - .R(i_up_axi_n_0)); - FDRE #( - .INIT(1'b0)) - \up_scratch_reg[12] - (.C(s_axi_aclk), - .CE(up_scratch), - .D(\^offload0_cmd_wr_data [12]), - .Q(\up_scratch_reg_n_0_[12] ), - .R(i_up_axi_n_0)); - FDRE #( - .INIT(1'b0)) - \up_scratch_reg[13] - (.C(s_axi_aclk), - .CE(up_scratch), - .D(\^offload0_cmd_wr_data [13]), - .Q(\up_scratch_reg_n_0_[13] ), - .R(i_up_axi_n_0)); - FDRE #( - .INIT(1'b0)) - \up_scratch_reg[14] - (.C(s_axi_aclk), - .CE(up_scratch), - .D(\^offload0_cmd_wr_data [14]), - .Q(\up_scratch_reg_n_0_[14] ), - .R(i_up_axi_n_0)); - FDRE #( - .INIT(1'b0)) - \up_scratch_reg[15] - (.C(s_axi_aclk), - .CE(up_scratch), - .D(\^offload0_cmd_wr_data [15]), - .Q(\up_scratch_reg_n_0_[15] ), - .R(i_up_axi_n_0)); - FDRE #( - .INIT(1'b0)) - \up_scratch_reg[16] - (.C(s_axi_aclk), - .CE(up_scratch), - .D(up_wdata_int[16]), - .Q(\up_scratch_reg_n_0_[16] ), - .R(i_up_axi_n_0)); - FDRE #( - .INIT(1'b0)) - \up_scratch_reg[17] - (.C(s_axi_aclk), - .CE(up_scratch), - .D(up_wdata_int[17]), - .Q(\up_scratch_reg_n_0_[17] ), - .R(i_up_axi_n_0)); - FDRE #( - .INIT(1'b0)) - \up_scratch_reg[18] - (.C(s_axi_aclk), - .CE(up_scratch), - .D(up_wdata_int[18]), - .Q(\up_scratch_reg_n_0_[18] ), - .R(i_up_axi_n_0)); - FDRE #( - .INIT(1'b0)) - \up_scratch_reg[19] - (.C(s_axi_aclk), - .CE(up_scratch), - .D(up_wdata_int[19]), - .Q(\up_scratch_reg_n_0_[19] ), - .R(i_up_axi_n_0)); - FDRE #( - .INIT(1'b0)) - \up_scratch_reg[1] - (.C(s_axi_aclk), - .CE(up_scratch), - .D(\^offload0_cmd_wr_data [1]), - .Q(\up_scratch_reg_n_0_[1] ), - .R(i_up_axi_n_0)); - FDRE #( - .INIT(1'b0)) - \up_scratch_reg[20] - (.C(s_axi_aclk), - .CE(up_scratch), - .D(up_wdata_int[20]), - .Q(\up_scratch_reg_n_0_[20] ), - .R(i_up_axi_n_0)); - FDRE #( - .INIT(1'b0)) - \up_scratch_reg[21] - (.C(s_axi_aclk), - .CE(up_scratch), - .D(up_wdata_int[21]), - .Q(\up_scratch_reg_n_0_[21] ), - .R(i_up_axi_n_0)); - FDRE #( - .INIT(1'b0)) - \up_scratch_reg[22] - (.C(s_axi_aclk), - .CE(up_scratch), - .D(up_wdata_int[22]), - .Q(\up_scratch_reg_n_0_[22] ), - .R(i_up_axi_n_0)); - FDRE #( - .INIT(1'b0)) - \up_scratch_reg[23] - (.C(s_axi_aclk), - .CE(up_scratch), - .D(up_wdata_int[23]), - .Q(\up_scratch_reg_n_0_[23] ), - .R(i_up_axi_n_0)); - FDRE #( - .INIT(1'b0)) - \up_scratch_reg[24] - (.C(s_axi_aclk), - .CE(up_scratch), - .D(up_wdata_int[24]), - .Q(\up_scratch_reg_n_0_[24] ), - .R(i_up_axi_n_0)); - FDRE #( - .INIT(1'b0)) - \up_scratch_reg[25] - (.C(s_axi_aclk), - .CE(up_scratch), - .D(up_wdata_int[25]), - .Q(\up_scratch_reg_n_0_[25] ), - .R(i_up_axi_n_0)); - FDRE #( - .INIT(1'b0)) - \up_scratch_reg[26] - (.C(s_axi_aclk), - .CE(up_scratch), - .D(up_wdata_int[26]), - .Q(\up_scratch_reg_n_0_[26] ), - .R(i_up_axi_n_0)); - FDRE #( - .INIT(1'b0)) - \up_scratch_reg[27] - (.C(s_axi_aclk), - .CE(up_scratch), - .D(up_wdata_int[27]), - .Q(\up_scratch_reg_n_0_[27] ), - .R(i_up_axi_n_0)); - FDRE #( - .INIT(1'b0)) - \up_scratch_reg[28] - (.C(s_axi_aclk), - .CE(up_scratch), - .D(up_wdata_int[28]), - .Q(\up_scratch_reg_n_0_[28] ), - .R(i_up_axi_n_0)); - FDRE #( - .INIT(1'b0)) - \up_scratch_reg[29] - (.C(s_axi_aclk), - .CE(up_scratch), - .D(up_wdata_int[29]), - .Q(\up_scratch_reg_n_0_[29] ), - .R(i_up_axi_n_0)); - FDRE #( - .INIT(1'b0)) - \up_scratch_reg[2] - (.C(s_axi_aclk), - .CE(up_scratch), - .D(\^offload0_cmd_wr_data [2]), - .Q(\up_scratch_reg_n_0_[2] ), - .R(i_up_axi_n_0)); - FDRE #( - .INIT(1'b0)) - \up_scratch_reg[30] - (.C(s_axi_aclk), - .CE(up_scratch), - .D(up_wdata_int[30]), - .Q(\up_scratch_reg_n_0_[30] ), - .R(i_up_axi_n_0)); - FDRE #( - .INIT(1'b0)) - \up_scratch_reg[31] - (.C(s_axi_aclk), - .CE(up_scratch), - .D(up_wdata_int[31]), - .Q(\up_scratch_reg_n_0_[31] ), - .R(i_up_axi_n_0)); - FDRE #( - .INIT(1'b0)) - \up_scratch_reg[3] - (.C(s_axi_aclk), - .CE(up_scratch), - .D(\^offload0_sdo_wr_data [3]), - .Q(\up_scratch_reg_n_0_[3] ), - .R(i_up_axi_n_0)); - FDRE #( - .INIT(1'b0)) - \up_scratch_reg[4] - (.C(s_axi_aclk), - .CE(up_scratch), - .D(\^offload0_sdo_wr_data [4]), - .Q(\up_scratch_reg_n_0_[4] ), - .R(i_up_axi_n_0)); - FDRE #( - .INIT(1'b0)) - \up_scratch_reg[5] - (.C(s_axi_aclk), - .CE(up_scratch), - .D(\^offload0_sdo_wr_data [5]), - .Q(\up_scratch_reg_n_0_[5] ), - .R(i_up_axi_n_0)); - FDRE #( - .INIT(1'b0)) - \up_scratch_reg[6] - (.C(s_axi_aclk), - .CE(up_scratch), - .D(\^offload0_sdo_wr_data [6]), - .Q(\up_scratch_reg_n_0_[6] ), - .R(i_up_axi_n_0)); - FDRE #( - .INIT(1'b0)) - \up_scratch_reg[7] - (.C(s_axi_aclk), - .CE(up_scratch), - .D(\^offload0_sdo_wr_data [7]), - .Q(\up_scratch_reg_n_0_[7] ), - .R(i_up_axi_n_0)); - FDRE #( - .INIT(1'b0)) - \up_scratch_reg[8] - (.C(s_axi_aclk), - .CE(up_scratch), - .D(\^offload0_cmd_wr_data [8]), - .Q(\up_scratch_reg_n_0_[8] ), - .R(i_up_axi_n_0)); - FDRE #( - .INIT(1'b0)) - \up_scratch_reg[9] - (.C(s_axi_aclk), - .CE(up_scratch), - .D(\^offload0_cmd_wr_data [9]), - .Q(\up_scratch_reg_n_0_[9] ), - .R(i_up_axi_n_0)); - FDSE #( - .INIT(1'b1)) - up_sw_reset_reg - (.C(s_axi_aclk), - .CE(1'b1), - .D(i_up_axi_n_56), - .Q(up_sw_reset), - .S(i_up_axi_n_0)); - FDRE #( - .INIT(1'b0)) - up_wack_ff_reg - (.C(s_axi_aclk), - .CE(1'b1), - .D(up_wreq_s), - .Q(up_wack_ff), - .R(i_up_axi_n_0)); -endmodule - -(* ORIG_REF_NAME = "fifo_address_sync" *) -module system_bd_axi_spi_engine_0_0_fifo_address_sync - (s_axis_ready_reg_0, - m_axis_valid_reg_0, - \level_reg[0]_0 , - \s_axis_waddr_reg[3]_0 , - \m_axis_raddr_reg[3]_0 , - up_irq_source, - \room_reg[4]_0 , - up_sw_reset, - spi_clk, - p_1_in, - cmd_ready, - \level_reg[0]_1 , - Q); - output s_axis_ready_reg_0; - output m_axis_valid_reg_0; - output \level_reg[0]_0 ; - output [3:0]\s_axis_waddr_reg[3]_0 ; - output [3:0]\m_axis_raddr_reg[3]_0 ; - output [0:0]up_irq_source; - output [3:0]\room_reg[4]_0 ; - input up_sw_reset; - input spi_clk; - input p_1_in; - input cmd_ready; - input \level_reg[0]_1 ; - input [0:0]Q; - - wire [0:0]Q; - wire cmd_ready; - wire [0:0]level_next; - wire [4:1]level_next__0; - wire [4:1]level_reg; - wire \level_reg[0]_0 ; - wire \level_reg[0]_1 ; - wire [3:0]\m_axis_raddr_reg[3]_0 ; - wire m_axis_valid_i_1_n_0; - wire m_axis_valid_i_2_n_0; - wire m_axis_valid_i_3_n_0; - wire m_axis_valid_reg_0; - wire [3:0]p_0_in; - wire p_0_in_0; - wire [3:0]p_0_in__0; - wire p_1_in; - wire [4:1]room0; - wire \room[2]_i_1_n_0 ; - wire [3:0]\room_reg[4]_0 ; - wire s_axis_ready_i_1_n_0; - wire s_axis_ready_reg_0; - wire [3:0]\s_axis_waddr_reg[3]_0 ; - wire spi_clk; - wire [0:0]up_irq_source; - wire up_sw_reset; - - LUT3 #( - .INIT(8'hF8)) - irq_i_3 - (.I0(\room_reg[4]_0 [2]), - .I1(\room_reg[4]_0 [1]), - .I2(\room_reg[4]_0 [3]), - .O(up_irq_source)); - LUT6 #( - .INIT(64'h6A6A6A6A956A6A6A)) - \level[0]_i_1 - (.I0(\level_reg[0]_0 ), - .I1(m_axis_valid_reg_0), - .I2(cmd_ready), - .I3(\level_reg[0]_1 ), - .I4(s_axis_ready_reg_0), - .I5(Q), - .O(level_next)); - (* SOFT_HLUTNM = "soft_lutpair0" *) - LUT5 #( - .INIT(32'hC6669CCC)) - \level[1]_i_1 - (.I0(\level_reg[0]_0 ), - .I1(level_reg[1]), - .I2(m_axis_valid_reg_0), - .I3(cmd_ready), - .I4(p_1_in), - .O(level_next__0[1])); - LUT6 #( - .INIT(64'hF0787878E1F0F0F0)) - \level[2]_i_1 - (.I0(level_reg[1]), - .I1(\level_reg[0]_0 ), - .I2(level_reg[2]), - .I3(m_axis_valid_reg_0), - .I4(cmd_ready), - .I5(p_1_in), - .O(level_next__0[2])); - (* SOFT_HLUTNM = "soft_lutpair2" *) - LUT3 #( - .INIT(8'h69)) - \level[3]_i_1 - (.I0(m_axis_valid_i_3_n_0), - .I1(level_reg[3]), - .I2(level_reg[2]), - .O(level_next__0[3])); - (* SOFT_HLUTNM = "soft_lutpair2" *) - LUT4 #( - .INIT(16'h78E1)) - \level[4]_i_1 - (.I0(level_reg[2]), - .I1(m_axis_valid_i_3_n_0), - .I2(level_reg[4]), - .I3(level_reg[3]), - .O(level_next__0[4])); - FDRE #( - .INIT(1'b0)) - \level_reg[0] - (.C(spi_clk), - .CE(1'b1), - .D(level_next), - .Q(\level_reg[0]_0 ), - .R(up_sw_reset)); - FDRE #( - .INIT(1'b0)) - \level_reg[1] - (.C(spi_clk), - .CE(1'b1), - .D(level_next__0[1]), - .Q(level_reg[1]), - .R(up_sw_reset)); - FDRE #( - .INIT(1'b0)) - \level_reg[2] - (.C(spi_clk), - .CE(1'b1), - .D(level_next__0[2]), - .Q(level_reg[2]), - .R(up_sw_reset)); - FDRE #( - .INIT(1'b0)) - \level_reg[3] - (.C(spi_clk), - .CE(1'b1), - .D(level_next__0[3]), - .Q(level_reg[3]), - .R(up_sw_reset)); - FDRE #( - .INIT(1'b0)) - \level_reg[4] - (.C(spi_clk), - .CE(1'b1), - .D(level_next__0[4]), - .Q(level_reg[4]), - .R(up_sw_reset)); - (* SOFT_HLUTNM = "soft_lutpair6" *) - LUT1 #( - .INIT(2'h1)) - \m_axis_raddr[0]_i_1 - (.I0(\m_axis_raddr_reg[3]_0 [0]), - .O(p_0_in__0[0])); - (* SOFT_HLUTNM = "soft_lutpair6" *) - LUT2 #( - .INIT(4'h6)) - \m_axis_raddr[1]_i_1 - (.I0(\m_axis_raddr_reg[3]_0 [0]), - .I1(\m_axis_raddr_reg[3]_0 [1]), - .O(p_0_in__0[1])); - (* SOFT_HLUTNM = "soft_lutpair4" *) - LUT3 #( - .INIT(8'h78)) - \m_axis_raddr[2]_i_1 - (.I0(\m_axis_raddr_reg[3]_0 [0]), - .I1(\m_axis_raddr_reg[3]_0 [1]), - .I2(\m_axis_raddr_reg[3]_0 [2]), - .O(p_0_in__0[2])); - LUT2 #( - .INIT(4'h8)) - \m_axis_raddr[3]_i_1 - (.I0(cmd_ready), - .I1(m_axis_valid_reg_0), - .O(p_0_in_0)); - (* SOFT_HLUTNM = "soft_lutpair4" *) - LUT4 #( - .INIT(16'h7F80)) - \m_axis_raddr[3]_i_2 - (.I0(\m_axis_raddr_reg[3]_0 [1]), - .I1(\m_axis_raddr_reg[3]_0 [0]), - .I2(\m_axis_raddr_reg[3]_0 [2]), - .I3(\m_axis_raddr_reg[3]_0 [3]), - .O(p_0_in__0[3])); - FDRE \m_axis_raddr_reg[0] - (.C(spi_clk), - .CE(p_0_in_0), - .D(p_0_in__0[0]), - .Q(\m_axis_raddr_reg[3]_0 [0]), - .R(up_sw_reset)); - FDRE \m_axis_raddr_reg[1] - (.C(spi_clk), - .CE(p_0_in_0), - .D(p_0_in__0[1]), - .Q(\m_axis_raddr_reg[3]_0 [1]), - .R(up_sw_reset)); - FDRE \m_axis_raddr_reg[2] - (.C(spi_clk), - .CE(p_0_in_0), - .D(p_0_in__0[2]), - .Q(\m_axis_raddr_reg[3]_0 [2]), - .R(up_sw_reset)); - FDRE \m_axis_raddr_reg[3] - (.C(spi_clk), - .CE(p_0_in_0), - .D(p_0_in__0[3]), - .Q(\m_axis_raddr_reg[3]_0 [3]), - .R(up_sw_reset)); - (* SOFT_HLUTNM = "soft_lutpair1" *) - LUT5 #( - .INIT(32'hBFFEFEFB)) - m_axis_valid_i_1 - (.I0(m_axis_valid_i_2_n_0), - .I1(level_reg[3]), - .I2(level_reg[4]), - .I3(m_axis_valid_i_3_n_0), - .I4(level_reg[2]), - .O(m_axis_valid_i_1_n_0)); - LUT6 #( - .INIT(64'hFE7F7F7FFBFEFEFE)) - m_axis_valid_i_2 - (.I0(level_reg[2]), - .I1(\level_reg[0]_0 ), - .I2(level_reg[1]), - .I3(m_axis_valid_reg_0), - .I4(cmd_ready), - .I5(p_1_in), - .O(m_axis_valid_i_2_n_0)); - LUT6 #( - .INIT(64'h7F55555555555515)) - m_axis_valid_i_3 - (.I0(level_reg[2]), - .I1(m_axis_valid_reg_0), - .I2(cmd_ready), - .I3(p_1_in), - .I4(\level_reg[0]_0 ), - .I5(level_reg[1]), - .O(m_axis_valid_i_3_n_0)); - FDRE m_axis_valid_reg - (.C(spi_clk), - .CE(1'b1), - .D(m_axis_valid_i_1_n_0), - .Q(m_axis_valid_reg_0), - .R(up_sw_reset)); - (* SOFT_HLUTNM = "soft_lutpair0" *) - LUT5 #( - .INIT(32'h40BFD52A)) - \room[1]_i_1 - (.I0(p_1_in), - .I1(cmd_ready), - .I2(m_axis_valid_reg_0), - .I3(level_reg[1]), - .I4(\level_reg[0]_0 ), - .O(room0[1])); - LUT6 #( - .INIT(64'h00FF00FF40BFD52A)) - \room[2]_i_1 - (.I0(p_1_in), - .I1(cmd_ready), - .I2(m_axis_valid_reg_0), - .I3(level_reg[2]), - .I4(\level_reg[0]_0 ), - .I5(level_reg[1]), - .O(\room[2]_i_1_n_0 )); - LUT6 #( - .INIT(64'h3333333333636366)) - \room[3]_i_1 - (.I0(level_reg[2]), - .I1(level_reg[3]), - .I2(p_0_in_0), - .I3(p_1_in), - .I4(\level_reg[0]_0 ), - .I5(level_reg[1]), - .O(room0[3])); - LUT5 #( - .INIT(32'h78E1E187)) - \room[4]_i_1 - (.I0(m_axis_valid_i_2_n_0), - .I1(level_reg[3]), - .I2(level_reg[4]), - .I3(m_axis_valid_i_3_n_0), - .I4(level_reg[2]), - .O(room0[4])); - FDRE #( - .INIT(1'b0)) - \room_reg[1] - (.C(spi_clk), - .CE(1'b1), - .D(room0[1]), - .Q(\room_reg[4]_0 [0]), - .R(up_sw_reset)); - FDRE #( - .INIT(1'b0)) - \room_reg[2] - (.C(spi_clk), - .CE(1'b1), - .D(\room[2]_i_1_n_0 ), - .Q(\room_reg[4]_0 [1]), - .R(up_sw_reset)); - FDRE #( - .INIT(1'b0)) - \room_reg[3] - (.C(spi_clk), - .CE(1'b1), - .D(room0[3]), - .Q(\room_reg[4]_0 [2]), - .R(up_sw_reset)); - FDSE #( - .INIT(1'b1)) - \room_reg[4] - (.C(spi_clk), - .CE(1'b1), - .D(room0[4]), - .Q(\room_reg[4]_0 [3]), - .S(up_sw_reset)); - (* SOFT_HLUTNM = "soft_lutpair1" *) - LUT5 #( - .INIT(32'hFFFFE79F)) - s_axis_ready_i_1 - (.I0(level_reg[2]), - .I1(m_axis_valid_i_3_n_0), - .I2(level_reg[4]), - .I3(level_reg[3]), - .I4(m_axis_valid_i_2_n_0), - .O(s_axis_ready_i_1_n_0)); - FDRE s_axis_ready_reg - (.C(spi_clk), - .CE(1'b1), - .D(s_axis_ready_i_1_n_0), - .Q(s_axis_ready_reg_0), - .R(up_sw_reset)); - (* SOFT_HLUTNM = "soft_lutpair5" *) - LUT1 #( - .INIT(2'h1)) - \s_axis_waddr[0]_i_1 - (.I0(\s_axis_waddr_reg[3]_0 [0]), - .O(p_0_in[0])); - (* SOFT_HLUTNM = "soft_lutpair5" *) - LUT2 #( - .INIT(4'h6)) - \s_axis_waddr[1]_i_1 - (.I0(\s_axis_waddr_reg[3]_0 [0]), - .I1(\s_axis_waddr_reg[3]_0 [1]), - .O(p_0_in[1])); - (* SOFT_HLUTNM = "soft_lutpair3" *) - LUT3 #( - .INIT(8'h78)) - \s_axis_waddr[2]_i_1 - (.I0(\s_axis_waddr_reg[3]_0 [0]), - .I1(\s_axis_waddr_reg[3]_0 [1]), - .I2(\s_axis_waddr_reg[3]_0 [2]), - .O(p_0_in[2])); - (* SOFT_HLUTNM = "soft_lutpair3" *) - LUT4 #( - .INIT(16'h7F80)) - \s_axis_waddr[3]_i_2 - (.I0(\s_axis_waddr_reg[3]_0 [1]), - .I1(\s_axis_waddr_reg[3]_0 [0]), - .I2(\s_axis_waddr_reg[3]_0 [2]), - .I3(\s_axis_waddr_reg[3]_0 [3]), - .O(p_0_in[3])); - FDRE \s_axis_waddr_reg[0] - (.C(spi_clk), - .CE(p_1_in), - .D(p_0_in[0]), - .Q(\s_axis_waddr_reg[3]_0 [0]), - .R(up_sw_reset)); - FDRE \s_axis_waddr_reg[1] - (.C(spi_clk), - .CE(p_1_in), - .D(p_0_in[1]), - .Q(\s_axis_waddr_reg[3]_0 [1]), - .R(up_sw_reset)); - FDRE \s_axis_waddr_reg[2] - (.C(spi_clk), - .CE(p_1_in), - .D(p_0_in[2]), - .Q(\s_axis_waddr_reg[3]_0 [2]), - .R(up_sw_reset)); - FDRE \s_axis_waddr_reg[3] - (.C(spi_clk), - .CE(p_1_in), - .D(p_0_in[3]), - .Q(\s_axis_waddr_reg[3]_0 [3]), - .R(up_sw_reset)); -endmodule - -(* ORIG_REF_NAME = "fifo_address_sync" *) -module system_bd_axi_spi_engine_0_0_fifo_address_sync__parameterized0 - (s_axis_ready_reg_0, - m_axis_valid_reg_0, - Q, - \m_axis_raddr_reg[4]_0 , - \up_irq_mask_reg[1] , - up_irq_source, - \room_reg[5]_0 , - up_sw_reset, - spi_clk, - sdo_data_ready, - \up_rdata_ff_reg[1] , - \up_rdata_ff_reg[1]_0 , - \up_rdata_ff_reg[1]_1 , - \level_reg[0]_0 , - \level_reg[0]_1 , - E); - output s_axis_ready_reg_0; - output m_axis_valid_reg_0; - output [4:0]Q; - output [4:0]\m_axis_raddr_reg[4]_0 ; - output \up_irq_mask_reg[1] ; - output [0:0]up_irq_source; - output [4:0]\room_reg[5]_0 ; - input up_sw_reset; - input spi_clk; - input sdo_data_ready; - input [0:0]\up_rdata_ff_reg[1] ; - input [0:0]\up_rdata_ff_reg[1]_0 ; - input [1:0]\up_rdata_ff_reg[1]_1 ; - input [0:0]\level_reg[0]_0 ; - input \level_reg[0]_1 ; - input [0:0]E; - - wire [0:0]E; - wire [4:0]Q; - wire [5:0]level_next; - wire level_next0_carry__0_i_1_n_0; - wire level_next0_carry__0_i_2_n_0; - wire level_next0_carry__0_n_3; - wire level_next0_carry_i_1__0_n_0; - wire level_next0_carry_i_2__0_n_0; - wire level_next0_carry_i_3_n_0; - wire level_next0_carry_i_4__0_n_0; - wire level_next0_carry_i_5__0_n_0; - wire level_next0_carry_i_6__0_n_0; - wire level_next0_carry_n_0; - wire level_next0_carry_n_1; - wire level_next0_carry_n_2; - wire level_next0_carry_n_3; - wire level_next0_carry_n_7; - wire level_next1; - wire [5:0]level_reg; - wire [0:0]\level_reg[0]_0 ; - wire \level_reg[0]_1 ; - wire [4:0]\m_axis_raddr_reg[4]_0 ; - wire m_axis_valid_i_10_n_0; - wire m_axis_valid_i_11_n_0; - wire m_axis_valid_i_1__0_n_0; - wire m_axis_valid_i_4_n_0; - wire m_axis_valid_i_5_n_0; - wire m_axis_valid_i_6_n_0; - wire m_axis_valid_i_8_n_0; - wire m_axis_valid_i_9_n_0; - wire m_axis_valid_reg_0; - wire m_axis_valid_reg_i_2_n_3; - wire m_axis_valid_reg_i_2_n_6; - wire m_axis_valid_reg_i_2_n_7; - wire m_axis_valid_reg_i_3_n_0; - wire m_axis_valid_reg_i_3_n_1; - wire m_axis_valid_reg_i_3_n_2; - wire m_axis_valid_reg_i_3_n_3; - wire m_axis_valid_reg_i_3_n_4; - wire m_axis_valid_reg_i_3_n_5; - wire m_axis_valid_reg_i_3_n_6; - wire [4:0]p_0_in; - wire p_0_in_0; - wire [4:0]p_0_in__0; - wire \room[1]_i_1__0_n_0 ; - wire \room[2]_i_1__0_n_0 ; - wire \room[3]_i_1__0_n_0 ; - wire \room[4]_i_1__0_n_0 ; - wire \room[5]_i_1_n_0 ; - wire [4:0]\room_reg[5]_0 ; - wire s_axis_ready_i_1__0_n_0; - wire s_axis_ready_reg_0; - wire sdo_data_ready; - wire [1:1]sdo_fifo_room; - wire spi_clk; - wire \up_irq_mask_reg[1] ; - wire [0:0]up_irq_source; - wire [0:0]\up_rdata_ff_reg[1] ; - wire [0:0]\up_rdata_ff_reg[1]_0 ; - wire [1:0]\up_rdata_ff_reg[1]_1 ; - wire up_sw_reset; - wire [3:1]NLW_level_next0_carry__0_CO_UNCONNECTED; - wire [3:2]NLW_level_next0_carry__0_O_UNCONNECTED; - wire [3:1]NLW_m_axis_valid_reg_i_2_CO_UNCONNECTED; - wire [3:2]NLW_m_axis_valid_reg_i_2_O_UNCONNECTED; - wire [0:0]NLW_m_axis_valid_reg_i_3_O_UNCONNECTED; - - LUT3 #( - .INIT(8'hF8)) - irq_i_4 - (.I0(\room_reg[5]_0 [3]), - .I1(\room_reg[5]_0 [2]), - .I2(\room_reg[5]_0 [4]), - .O(up_irq_source)); - LUT6 #( - .INIT(64'h807F7F807F807F80)) - \level[0]_i_1__1 - (.I0(s_axis_ready_reg_0), - .I1(\level_reg[0]_0 ), - .I2(\level_reg[0]_1 ), - .I3(level_reg[0]), - .I4(m_axis_valid_reg_0), - .I5(sdo_data_ready), - .O(level_next[0])); - CARRY4 level_next0_carry - (.CI(1'b0), - .CO({level_next0_carry_n_0,level_next0_carry_n_1,level_next0_carry_n_2,level_next0_carry_n_3}), - .CYINIT(1'b0), - .DI({level_reg[2],level_next0_carry_i_1__0_n_0,level_next0_carry_i_2__0_n_0,level_reg[0]}), - .O({level_next[3:1],level_next0_carry_n_7}), - .S({level_next0_carry_i_3_n_0,level_next0_carry_i_4__0_n_0,level_next0_carry_i_5__0_n_0,level_next0_carry_i_6__0_n_0})); - CARRY4 level_next0_carry__0 - (.CI(level_next0_carry_n_0), - .CO({NLW_level_next0_carry__0_CO_UNCONNECTED[3:1],level_next0_carry__0_n_3}), - .CYINIT(1'b0), - .DI({1'b0,1'b0,1'b0,level_reg[3]}), - .O({NLW_level_next0_carry__0_O_UNCONNECTED[3:2],level_next[5:4]}), - .S({1'b0,1'b0,level_next0_carry__0_i_1_n_0,level_next0_carry__0_i_2_n_0})); - LUT2 #( - .INIT(4'h9)) - level_next0_carry__0_i_1 - (.I0(level_reg[4]), - .I1(level_reg[5]), - .O(level_next0_carry__0_i_1_n_0)); - LUT2 #( - .INIT(4'h9)) - level_next0_carry__0_i_2 - (.I0(level_reg[3]), - .I1(level_reg[4]), - .O(level_next0_carry__0_i_2_n_0)); - LUT5 #( - .INIT(32'h80FFFFFF)) - level_next0_carry_i_1__0 - (.I0(s_axis_ready_reg_0), - .I1(\level_reg[0]_0 ), - .I2(\level_reg[0]_1 ), - .I3(sdo_data_ready), - .I4(m_axis_valid_reg_0), - .O(level_next0_carry_i_1__0_n_0)); - LUT5 #( - .INIT(32'h7F000000)) - level_next0_carry_i_2__0 - (.I0(s_axis_ready_reg_0), - .I1(\level_reg[0]_0 ), - .I2(\level_reg[0]_1 ), - .I3(m_axis_valid_reg_0), - .I4(sdo_data_ready), - .O(level_next0_carry_i_2__0_n_0)); - LUT2 #( - .INIT(4'h9)) - level_next0_carry_i_3 - (.I0(level_reg[2]), - .I1(level_reg[3]), - .O(level_next0_carry_i_3_n_0)); - LUT6 #( - .INIT(64'h80FFFFFF7F000000)) - level_next0_carry_i_4__0 - (.I0(s_axis_ready_reg_0), - .I1(\level_reg[0]_0 ), - .I2(\level_reg[0]_1 ), - .I3(sdo_data_ready), - .I4(m_axis_valid_reg_0), - .I5(level_reg[2]), - .O(level_next0_carry_i_4__0_n_0)); - LUT6 #( - .INIT(64'h80FFFFFF7F000000)) - level_next0_carry_i_5__0 - (.I0(s_axis_ready_reg_0), - .I1(\level_reg[0]_0 ), - .I2(\level_reg[0]_1 ), - .I3(sdo_data_ready), - .I4(m_axis_valid_reg_0), - .I5(level_reg[1]), - .O(level_next0_carry_i_5__0_n_0)); - LUT6 #( - .INIT(64'h807F7F807F807F80)) - level_next0_carry_i_6__0 - (.I0(s_axis_ready_reg_0), - .I1(\level_reg[0]_0 ), - .I2(\level_reg[0]_1 ), - .I3(level_reg[0]), - .I4(m_axis_valid_reg_0), - .I5(sdo_data_ready), - .O(level_next0_carry_i_6__0_n_0)); - FDRE #( - .INIT(1'b0)) - \level_reg[0] - (.C(spi_clk), - .CE(1'b1), - .D(level_next[0]), - .Q(level_reg[0]), - .R(up_sw_reset)); - FDRE #( - .INIT(1'b0)) - \level_reg[1] - (.C(spi_clk), - .CE(1'b1), - .D(level_next[1]), - .Q(level_reg[1]), - .R(up_sw_reset)); - FDRE #( - .INIT(1'b0)) - \level_reg[2] - (.C(spi_clk), - .CE(1'b1), - .D(level_next[2]), - .Q(level_reg[2]), - .R(up_sw_reset)); - FDRE #( - .INIT(1'b0)) - \level_reg[3] - (.C(spi_clk), - .CE(1'b1), - .D(level_next[3]), - .Q(level_reg[3]), - .R(up_sw_reset)); - FDRE #( - .INIT(1'b0)) - \level_reg[4] - (.C(spi_clk), - .CE(1'b1), - .D(level_next[4]), - .Q(level_reg[4]), - .R(up_sw_reset)); - FDRE #( - .INIT(1'b0)) - \level_reg[5] - (.C(spi_clk), - .CE(1'b1), - .D(level_next[5]), - .Q(level_reg[5]), - .R(up_sw_reset)); - LUT1 #( - .INIT(2'h1)) - \m_axis_raddr[0]_i_1__0 - (.I0(\m_axis_raddr_reg[4]_0 [0]), - .O(p_0_in__0[0])); - (* SOFT_HLUTNM = "soft_lutpair16" *) - LUT2 #( - .INIT(4'h6)) - \m_axis_raddr[1]_i_1__0 - (.I0(\m_axis_raddr_reg[4]_0 [0]), - .I1(\m_axis_raddr_reg[4]_0 [1]), - .O(p_0_in__0[1])); - (* SOFT_HLUTNM = "soft_lutpair16" *) - LUT3 #( - .INIT(8'h78)) - \m_axis_raddr[2]_i_1__0 - (.I0(\m_axis_raddr_reg[4]_0 [0]), - .I1(\m_axis_raddr_reg[4]_0 [1]), - .I2(\m_axis_raddr_reg[4]_0 [2]), - .O(p_0_in__0[2])); - (* SOFT_HLUTNM = "soft_lutpair12" *) - LUT4 #( - .INIT(16'h7F80)) - \m_axis_raddr[3]_i_1__0 - (.I0(\m_axis_raddr_reg[4]_0 [1]), - .I1(\m_axis_raddr_reg[4]_0 [0]), - .I2(\m_axis_raddr_reg[4]_0 [2]), - .I3(\m_axis_raddr_reg[4]_0 [3]), - .O(p_0_in__0[3])); - LUT2 #( - .INIT(4'h8)) - \m_axis_raddr[4]_i_1 - (.I0(sdo_data_ready), - .I1(m_axis_valid_reg_0), - .O(p_0_in_0)); - (* SOFT_HLUTNM = "soft_lutpair12" *) - LUT5 #( - .INIT(32'h7FFF8000)) - \m_axis_raddr[4]_i_2 - (.I0(\m_axis_raddr_reg[4]_0 [2]), - .I1(\m_axis_raddr_reg[4]_0 [0]), - .I2(\m_axis_raddr_reg[4]_0 [1]), - .I3(\m_axis_raddr_reg[4]_0 [3]), - .I4(\m_axis_raddr_reg[4]_0 [4]), - .O(p_0_in__0[4])); - FDRE \m_axis_raddr_reg[0] - (.C(spi_clk), - .CE(p_0_in_0), - .D(p_0_in__0[0]), - .Q(\m_axis_raddr_reg[4]_0 [0]), - .R(up_sw_reset)); - FDRE \m_axis_raddr_reg[1] - (.C(spi_clk), - .CE(p_0_in_0), - .D(p_0_in__0[1]), - .Q(\m_axis_raddr_reg[4]_0 [1]), - .R(up_sw_reset)); - FDRE \m_axis_raddr_reg[2] - (.C(spi_clk), - .CE(p_0_in_0), - .D(p_0_in__0[2]), - .Q(\m_axis_raddr_reg[4]_0 [2]), - .R(up_sw_reset)); - FDRE \m_axis_raddr_reg[3] - (.C(spi_clk), - .CE(p_0_in_0), - .D(p_0_in__0[3]), - .Q(\m_axis_raddr_reg[4]_0 [3]), - .R(up_sw_reset)); - FDRE \m_axis_raddr_reg[4] - (.C(spi_clk), - .CE(p_0_in_0), - .D(p_0_in__0[4]), - .Q(\m_axis_raddr_reg[4]_0 [4]), - .R(up_sw_reset)); - LUT6 #( - .INIT(64'h80FFFFFF7F000000)) - m_axis_valid_i_10 - (.I0(s_axis_ready_reg_0), - .I1(\level_reg[0]_0 ), - .I2(\level_reg[0]_1 ), - .I3(sdo_data_ready), - .I4(m_axis_valid_reg_0), - .I5(level_reg[1]), - .O(m_axis_valid_i_10_n_0)); - LUT6 #( - .INIT(64'h807F7F807F807F80)) - m_axis_valid_i_11 - (.I0(s_axis_ready_reg_0), - .I1(\level_reg[0]_0 ), - .I2(\level_reg[0]_1 ), - .I3(level_reg[0]), - .I4(m_axis_valid_reg_0), - .I5(sdo_data_ready), - .O(m_axis_valid_i_11_n_0)); - LUT6 #( - .INIT(64'hFFFFFFFFFFFFFFFE)) - m_axis_valid_i_1__0 - (.I0(m_axis_valid_reg_i_2_n_7), - .I1(m_axis_valid_reg_i_3_n_4), - .I2(m_axis_valid_reg_i_2_n_6), - .I3(m_axis_valid_reg_i_3_n_6), - .I4(level_next0_carry_n_7), - .I5(m_axis_valid_reg_i_3_n_5), - .O(m_axis_valid_i_1__0_n_0)); - LUT2 #( - .INIT(4'h9)) - m_axis_valid_i_4 - (.I0(level_reg[4]), - .I1(level_reg[5]), - .O(m_axis_valid_i_4_n_0)); - LUT2 #( - .INIT(4'h9)) - m_axis_valid_i_5 - (.I0(level_reg[3]), - .I1(level_reg[4]), - .O(m_axis_valid_i_5_n_0)); - LUT5 #( - .INIT(32'h80FFFFFF)) - m_axis_valid_i_6 - (.I0(s_axis_ready_reg_0), - .I1(\level_reg[0]_0 ), - .I2(\level_reg[0]_1 ), - .I3(sdo_data_ready), - .I4(m_axis_valid_reg_0), - .O(m_axis_valid_i_6_n_0)); - LUT5 #( - .INIT(32'h7F000000)) - m_axis_valid_i_7 - (.I0(s_axis_ready_reg_0), - .I1(\level_reg[0]_0 ), - .I2(\level_reg[0]_1 ), - .I3(m_axis_valid_reg_0), - .I4(sdo_data_ready), - .O(level_next1)); - LUT2 #( - .INIT(4'h9)) - m_axis_valid_i_8 - (.I0(level_reg[2]), - .I1(level_reg[3]), - .O(m_axis_valid_i_8_n_0)); - LUT6 #( - .INIT(64'h80FFFFFF7F000000)) - m_axis_valid_i_9 - (.I0(s_axis_ready_reg_0), - .I1(\level_reg[0]_0 ), - .I2(\level_reg[0]_1 ), - .I3(sdo_data_ready), - .I4(m_axis_valid_reg_0), - .I5(level_reg[2]), - .O(m_axis_valid_i_9_n_0)); - FDRE m_axis_valid_reg - (.C(spi_clk), - .CE(1'b1), - .D(m_axis_valid_i_1__0_n_0), - .Q(m_axis_valid_reg_0), - .R(up_sw_reset)); - CARRY4 m_axis_valid_reg_i_2 - (.CI(m_axis_valid_reg_i_3_n_0), - .CO({NLW_m_axis_valid_reg_i_2_CO_UNCONNECTED[3:1],m_axis_valid_reg_i_2_n_3}), - .CYINIT(1'b0), - .DI({1'b0,1'b0,1'b0,level_reg[3]}), - .O({NLW_m_axis_valid_reg_i_2_O_UNCONNECTED[3:2],m_axis_valid_reg_i_2_n_6,m_axis_valid_reg_i_2_n_7}), - .S({1'b0,1'b0,m_axis_valid_i_4_n_0,m_axis_valid_i_5_n_0})); - CARRY4 m_axis_valid_reg_i_3 - (.CI(1'b0), - .CO({m_axis_valid_reg_i_3_n_0,m_axis_valid_reg_i_3_n_1,m_axis_valid_reg_i_3_n_2,m_axis_valid_reg_i_3_n_3}), - .CYINIT(1'b0), - .DI({level_reg[2],m_axis_valid_i_6_n_0,level_next1,level_reg[0]}), - .O({m_axis_valid_reg_i_3_n_4,m_axis_valid_reg_i_3_n_5,m_axis_valid_reg_i_3_n_6,NLW_m_axis_valid_reg_i_3_O_UNCONNECTED[0]}), - .S({m_axis_valid_i_8_n_0,m_axis_valid_i_9_n_0,m_axis_valid_i_10_n_0,m_axis_valid_i_11_n_0})); - (* SOFT_HLUTNM = "soft_lutpair15" *) - LUT2 #( - .INIT(4'h6)) - \room[1]_i_1__0 - (.I0(level_next0_carry_n_7), - .I1(m_axis_valid_reg_i_3_n_6), - .O(\room[1]_i_1__0_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair15" *) - LUT3 #( - .INIT(8'h1E)) - \room[2]_i_1__0 - (.I0(level_next0_carry_n_7), - .I1(m_axis_valid_reg_i_3_n_6), - .I2(m_axis_valid_reg_i_3_n_5), - .O(\room[2]_i_1__0_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair13" *) - LUT4 #( - .INIT(16'h01FE)) - \room[3]_i_1__0 - (.I0(m_axis_valid_reg_i_3_n_5), - .I1(level_next0_carry_n_7), - .I2(m_axis_valid_reg_i_3_n_6), - .I3(m_axis_valid_reg_i_3_n_4), - .O(\room[3]_i_1__0_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair13" *) - LUT5 #( - .INIT(32'h0001FFFE)) - \room[4]_i_1__0 - (.I0(m_axis_valid_reg_i_3_n_4), - .I1(m_axis_valid_reg_i_3_n_6), - .I2(level_next0_carry_n_7), - .I3(m_axis_valid_reg_i_3_n_5), - .I4(m_axis_valid_reg_i_2_n_7), - .O(\room[4]_i_1__0_n_0 )); - LUT6 #( - .INIT(64'hFFFFFFFE00000001)) - \room[5]_i_1 - (.I0(m_axis_valid_reg_i_2_n_7), - .I1(m_axis_valid_reg_i_3_n_5), - .I2(level_next0_carry_n_7), - .I3(m_axis_valid_reg_i_3_n_6), - .I4(m_axis_valid_reg_i_3_n_4), - .I5(m_axis_valid_reg_i_2_n_6), - .O(\room[5]_i_1_n_0 )); - FDRE #( - .INIT(1'b0)) - \room_reg[0] - (.C(spi_clk), - .CE(1'b1), - .D(level_next0_carry_n_7), - .Q(\room_reg[5]_0 [0]), - .R(up_sw_reset)); - FDRE #( - .INIT(1'b0)) - \room_reg[1] - (.C(spi_clk), - .CE(1'b1), - .D(\room[1]_i_1__0_n_0 ), - .Q(sdo_fifo_room), - .R(up_sw_reset)); - FDRE #( - .INIT(1'b0)) - \room_reg[2] - (.C(spi_clk), - .CE(1'b1), - .D(\room[2]_i_1__0_n_0 ), - .Q(\room_reg[5]_0 [1]), - .R(up_sw_reset)); - FDRE #( - .INIT(1'b0)) - \room_reg[3] - (.C(spi_clk), - .CE(1'b1), - .D(\room[3]_i_1__0_n_0 ), - .Q(\room_reg[5]_0 [2]), - .R(up_sw_reset)); - FDRE #( - .INIT(1'b0)) - \room_reg[4] - (.C(spi_clk), - .CE(1'b1), - .D(\room[4]_i_1__0_n_0 ), - .Q(\room_reg[5]_0 [3]), - .R(up_sw_reset)); - FDSE #( - .INIT(1'b1)) - \room_reg[5] - (.C(spi_clk), - .CE(1'b1), - .D(\room[5]_i_1_n_0 ), - .Q(\room_reg[5]_0 [4]), - .S(up_sw_reset)); - LUT6 #( - .INIT(64'hFFFFFFFFFFFFFEFF)) - s_axis_ready_i_1__0 - (.I0(m_axis_valid_reg_i_2_n_7), - .I1(m_axis_valid_reg_i_3_n_5), - .I2(m_axis_valid_reg_i_3_n_4), - .I3(m_axis_valid_reg_i_2_n_6), - .I4(m_axis_valid_reg_i_3_n_6), - .I5(level_next0_carry_n_7), - .O(s_axis_ready_i_1__0_n_0)); - FDRE s_axis_ready_reg - (.C(spi_clk), - .CE(1'b1), - .D(s_axis_ready_i_1__0_n_0), - .Q(s_axis_ready_reg_0), - .R(up_sw_reset)); - LUT1 #( - .INIT(2'h1)) - \s_axis_waddr[0]_i_1__0 - (.I0(Q[0]), - .O(p_0_in[0])); - (* SOFT_HLUTNM = "soft_lutpair14" *) - LUT2 #( - .INIT(4'h6)) - \s_axis_waddr[1]_i_1__0 - (.I0(Q[0]), - .I1(Q[1]), - .O(p_0_in[1])); - (* SOFT_HLUTNM = "soft_lutpair14" *) - LUT3 #( - .INIT(8'h78)) - \s_axis_waddr[2]_i_1__0 - (.I0(Q[0]), - .I1(Q[1]), - .I2(Q[2]), - .O(p_0_in[2])); - (* SOFT_HLUTNM = "soft_lutpair11" *) - LUT4 #( - .INIT(16'h7F80)) - \s_axis_waddr[3]_i_1__0 - (.I0(Q[1]), - .I1(Q[0]), - .I2(Q[2]), - .I3(Q[3]), - .O(p_0_in[3])); - (* SOFT_HLUTNM = "soft_lutpair11" *) - LUT5 #( - .INIT(32'h7FFF8000)) - \s_axis_waddr[4]_i_2 - (.I0(Q[2]), - .I1(Q[0]), - .I2(Q[1]), - .I3(Q[3]), - .I4(Q[4]), - .O(p_0_in[4])); - FDRE \s_axis_waddr_reg[0] - (.C(spi_clk), - .CE(E), - .D(p_0_in[0]), - .Q(Q[0]), - .R(up_sw_reset)); - FDRE \s_axis_waddr_reg[1] - (.C(spi_clk), - .CE(E), - .D(p_0_in[1]), - .Q(Q[1]), - .R(up_sw_reset)); - FDRE \s_axis_waddr_reg[2] - (.C(spi_clk), - .CE(E), - .D(p_0_in[2]), - .Q(Q[2]), - .R(up_sw_reset)); - FDRE \s_axis_waddr_reg[3] - (.C(spi_clk), - .CE(E), - .D(p_0_in[3]), - .Q(Q[3]), - .R(up_sw_reset)); - FDRE \s_axis_waddr_reg[4] - (.C(spi_clk), - .CE(E), - .D(p_0_in[4]), - .Q(Q[4]), - .R(up_sw_reset)); - LUT6 #( - .INIT(64'hFF000000F0F08888)) - \up_rdata_ff[1]_i_2 - (.I0(\up_rdata_ff_reg[1] ), - .I1(up_irq_source), - .I2(\up_rdata_ff_reg[1]_0 ), - .I3(sdo_fifo_room), - .I4(\up_rdata_ff_reg[1]_1 [1]), - .I5(\up_rdata_ff_reg[1]_1 [0]), - .O(\up_irq_mask_reg[1] )); -endmodule - -(* ORIG_REF_NAME = "fifo_address_sync" *) -module system_bd_axi_spi_engine_0_0_fifo_address_sync__parameterized0_1 - (s_axis_ready_reg_0, - m_axis_valid_reg_0, - Q, - \s_axis_waddr_reg[4]_0 , - \m_axis_raddr_reg[4]_0 , - \up_irq_mask_reg[0] , - \level_reg[4]_0 , - s_mem_write, - up_sw_reset, - s_axi_aclk, - DI, - sdi_data_valid, - p_0_in, - irq_reg, - up_irq_source, - irq_reg_0, - m_axis_valid_reg_1); - output s_axis_ready_reg_0; - output m_axis_valid_reg_0; - output [5:0]Q; - output [4:0]\s_axis_waddr_reg[4]_0 ; - output [4:0]\m_axis_raddr_reg[4]_0 ; - output \up_irq_mask_reg[0] ; - output [0:0]\level_reg[4]_0 ; - output s_mem_write; - input up_sw_reset; - input s_axi_aclk; - input [0:0]DI; - input sdi_data_valid; - input p_0_in; - input [3:0]irq_reg; - input [1:0]up_irq_source; - input [0:0]irq_reg_0; - input [0:0]m_axis_valid_reg_1; - - wire [0:0]DI; - wire [5:0]Q; - wire irq_i_2_n_0; - wire [3:0]irq_reg; - wire [0:0]irq_reg_0; - wire [5:0]level_next; - wire level_next0_carry__0_i_1__0_n_0; - wire level_next0_carry__0_i_2__0_n_0; - wire level_next0_carry__0_n_3; - wire level_next0_carry_i_1_n_0; - wire level_next0_carry_i_3__0_n_0; - wire level_next0_carry_i_4_n_0; - wire level_next0_carry_i_5_n_0; - wire level_next0_carry_i_6_n_0; - wire level_next0_carry_n_0; - wire level_next0_carry_n_1; - wire level_next0_carry_n_2; - wire level_next0_carry_n_3; - wire level_next0_carry_n_7; - wire [0:0]\level_reg[4]_0 ; - wire [4:0]\m_axis_raddr_reg[4]_0 ; - wire m_axis_valid_i_1__1_n_0; - wire m_axis_valid_reg_0; - wire [0:0]m_axis_valid_reg_1; - wire p_0_in; - wire [4:0]p_0_in__0; - wire [4:0]p_0_in__1; - wire s_axi_aclk; - wire s_axis_ready_i_10_n_0; - wire s_axis_ready_i_11_n_0; - wire s_axis_ready_i_1__1_n_0; - wire s_axis_ready_i_4_n_0; - wire s_axis_ready_i_5_n_0; - wire s_axis_ready_i_6_n_0; - wire s_axis_ready_i_8_n_0; - wire s_axis_ready_i_9_n_0; - wire s_axis_ready_reg_0; - wire s_axis_ready_reg_i_2_n_3; - wire s_axis_ready_reg_i_2_n_6; - wire s_axis_ready_reg_i_2_n_7; - wire s_axis_ready_reg_i_3_n_0; - wire s_axis_ready_reg_i_3_n_1; - wire s_axis_ready_reg_i_3_n_2; - wire s_axis_ready_reg_i_3_n_3; - wire s_axis_ready_reg_i_3_n_4; - wire s_axis_ready_reg_i_3_n_5; - wire s_axis_ready_reg_i_3_n_6; - wire [4:0]\s_axis_waddr_reg[4]_0 ; - wire s_mem_write; - wire sdi_data_valid; - wire \up_irq_mask_reg[0] ; - wire [1:0]up_irq_source; - wire up_sw_reset; - wire [3:1]NLW_level_next0_carry__0_CO_UNCONNECTED; - wire [3:2]NLW_level_next0_carry__0_O_UNCONNECTED; - wire [3:1]NLW_s_axis_ready_reg_i_2_CO_UNCONNECTED; - wire [3:2]NLW_s_axis_ready_reg_i_2_O_UNCONNECTED; - wire [0:0]NLW_s_axis_ready_reg_i_3_O_UNCONNECTED; - - LUT5 #( - .INIT(32'hFFEAEAEA)) - irq_i_1 - (.I0(irq_i_2_n_0), - .I1(irq_reg[0]), - .I2(up_irq_source[0]), - .I3(irq_reg[1]), - .I4(up_irq_source[1]), - .O(\up_irq_mask_reg[0] )); - LUT6 #( - .INIT(64'hFFFFF88888888888)) - irq_i_2 - (.I0(irq_reg_0), - .I1(irq_reg[3]), - .I2(Q[4]), - .I3(Q[3]), - .I4(Q[5]), - .I5(irq_reg[2]), - .O(irq_i_2_n_0)); - LUT4 #( - .INIT(16'h9666)) - \level[0]_i_1__0 - (.I0(Q[0]), - .I1(p_0_in), - .I2(sdi_data_valid), - .I3(s_axis_ready_reg_0), - .O(level_next[0])); - CARRY4 level_next0_carry - (.CI(1'b0), - .CO({level_next0_carry_n_0,level_next0_carry_n_1,level_next0_carry_n_2,level_next0_carry_n_3}), - .CYINIT(1'b0), - .DI({Q[2],level_next0_carry_i_1_n_0,DI,Q[0]}), - .O({level_next[3:1],level_next0_carry_n_7}), - .S({level_next0_carry_i_3__0_n_0,level_next0_carry_i_4_n_0,level_next0_carry_i_5_n_0,level_next0_carry_i_6_n_0})); - CARRY4 level_next0_carry__0 - (.CI(level_next0_carry_n_0), - .CO({NLW_level_next0_carry__0_CO_UNCONNECTED[3:1],level_next0_carry__0_n_3}), - .CYINIT(1'b0), - .DI({1'b0,1'b0,1'b0,Q[3]}), - .O({NLW_level_next0_carry__0_O_UNCONNECTED[3:2],level_next[5:4]}), - .S({1'b0,1'b0,level_next0_carry__0_i_1__0_n_0,level_next0_carry__0_i_2__0_n_0})); - LUT2 #( - .INIT(4'h9)) - level_next0_carry__0_i_1__0 - (.I0(Q[4]), - .I1(Q[5]), - .O(level_next0_carry__0_i_1__0_n_0)); - LUT2 #( - .INIT(4'h9)) - level_next0_carry__0_i_2__0 - (.I0(Q[3]), - .I1(Q[4]), - .O(level_next0_carry__0_i_2__0_n_0)); - LUT3 #( - .INIT(8'h8F)) - level_next0_carry_i_1 - (.I0(s_axis_ready_reg_0), - .I1(sdi_data_valid), - .I2(p_0_in), - .O(level_next0_carry_i_1_n_0)); - LUT2 #( - .INIT(4'h9)) - level_next0_carry_i_3__0 - (.I0(Q[2]), - .I1(Q[3]), - .O(level_next0_carry_i_3__0_n_0)); - LUT4 #( - .INIT(16'h8F70)) - level_next0_carry_i_4 - (.I0(s_axis_ready_reg_0), - .I1(sdi_data_valid), - .I2(p_0_in), - .I3(Q[2]), - .O(level_next0_carry_i_4_n_0)); - LUT4 #( - .INIT(16'h8F70)) - level_next0_carry_i_5 - (.I0(s_axis_ready_reg_0), - .I1(sdi_data_valid), - .I2(p_0_in), - .I3(Q[1]), - .O(level_next0_carry_i_5_n_0)); - LUT4 #( - .INIT(16'h9666)) - level_next0_carry_i_6 - (.I0(Q[0]), - .I1(p_0_in), - .I2(sdi_data_valid), - .I3(s_axis_ready_reg_0), - .O(level_next0_carry_i_6_n_0)); - FDRE #( - .INIT(1'b0)) - \level_reg[0] - (.C(s_axi_aclk), - .CE(1'b1), - .D(level_next[0]), - .Q(Q[0]), - .R(up_sw_reset)); - FDRE #( - .INIT(1'b0)) - \level_reg[1] - (.C(s_axi_aclk), - .CE(1'b1), - .D(level_next[1]), - .Q(Q[1]), - .R(up_sw_reset)); - FDRE #( - .INIT(1'b0)) - \level_reg[2] - (.C(s_axi_aclk), - .CE(1'b1), - .D(level_next[2]), - .Q(Q[2]), - .R(up_sw_reset)); - FDRE #( - .INIT(1'b0)) - \level_reg[3] - (.C(s_axi_aclk), - .CE(1'b1), - .D(level_next[3]), - .Q(Q[3]), - .R(up_sw_reset)); - FDRE #( - .INIT(1'b0)) - \level_reg[4] - (.C(s_axi_aclk), - .CE(1'b1), - .D(level_next[4]), - .Q(Q[4]), - .R(up_sw_reset)); - FDRE #( - .INIT(1'b0)) - \level_reg[5] - (.C(s_axi_aclk), - .CE(1'b1), - .D(level_next[5]), - .Q(Q[5]), - .R(up_sw_reset)); - LUT1 #( - .INIT(2'h1)) - \m_axis_raddr[0]_i_1__1 - (.I0(\m_axis_raddr_reg[4]_0 [0]), - .O(p_0_in__1[0])); - (* SOFT_HLUTNM = "soft_lutpair9" *) - LUT2 #( - .INIT(4'h6)) - \m_axis_raddr[1]_i_1__1 - (.I0(\m_axis_raddr_reg[4]_0 [0]), - .I1(\m_axis_raddr_reg[4]_0 [1]), - .O(p_0_in__1[1])); - (* SOFT_HLUTNM = "soft_lutpair9" *) - LUT3 #( - .INIT(8'h78)) - \m_axis_raddr[2]_i_1__1 - (.I0(\m_axis_raddr_reg[4]_0 [0]), - .I1(\m_axis_raddr_reg[4]_0 [1]), - .I2(\m_axis_raddr_reg[4]_0 [2]), - .O(p_0_in__1[2])); - (* SOFT_HLUTNM = "soft_lutpair8" *) - LUT4 #( - .INIT(16'h7F80)) - \m_axis_raddr[3]_i_1__1 - (.I0(\m_axis_raddr_reg[4]_0 [1]), - .I1(\m_axis_raddr_reg[4]_0 [0]), - .I2(\m_axis_raddr_reg[4]_0 [2]), - .I3(\m_axis_raddr_reg[4]_0 [3]), - .O(p_0_in__1[3])); - (* SOFT_HLUTNM = "soft_lutpair8" *) - LUT5 #( - .INIT(32'h7FFF8000)) - \m_axis_raddr[4]_i_2__0 - (.I0(\m_axis_raddr_reg[4]_0 [2]), - .I1(\m_axis_raddr_reg[4]_0 [0]), - .I2(\m_axis_raddr_reg[4]_0 [1]), - .I3(\m_axis_raddr_reg[4]_0 [3]), - .I4(\m_axis_raddr_reg[4]_0 [4]), - .O(p_0_in__1[4])); - FDRE \m_axis_raddr_reg[0] - (.C(s_axi_aclk), - .CE(p_0_in), - .D(p_0_in__1[0]), - .Q(\m_axis_raddr_reg[4]_0 [0]), - .R(up_sw_reset)); - FDRE \m_axis_raddr_reg[1] - (.C(s_axi_aclk), - .CE(p_0_in), - .D(p_0_in__1[1]), - .Q(\m_axis_raddr_reg[4]_0 [1]), - .R(up_sw_reset)); - FDRE \m_axis_raddr_reg[2] - (.C(s_axi_aclk), - .CE(p_0_in), - .D(p_0_in__1[2]), - .Q(\m_axis_raddr_reg[4]_0 [2]), - .R(up_sw_reset)); - FDRE \m_axis_raddr_reg[3] - (.C(s_axi_aclk), - .CE(p_0_in), - .D(p_0_in__1[3]), - .Q(\m_axis_raddr_reg[4]_0 [3]), - .R(up_sw_reset)); - FDRE \m_axis_raddr_reg[4] - (.C(s_axi_aclk), - .CE(p_0_in), - .D(p_0_in__1[4]), - .Q(\m_axis_raddr_reg[4]_0 [4]), - .R(up_sw_reset)); - LUT6 #( - .INIT(64'hFFFFFFFFFFFFFFFE)) - m_axis_valid_i_1__1 - (.I0(level_next0_carry_n_7), - .I1(s_axis_ready_reg_i_3_n_6), - .I2(s_axis_ready_reg_i_2_n_6), - .I3(s_axis_ready_reg_i_3_n_5), - .I4(s_axis_ready_reg_i_3_n_4), - .I5(s_axis_ready_reg_i_2_n_7), - .O(m_axis_valid_i_1__1_n_0)); - FDRE m_axis_valid_reg - (.C(s_axi_aclk), - .CE(1'b1), - .D(m_axis_valid_i_1__1_n_0), - .Q(m_axis_valid_reg_0), - .R(up_sw_reset)); - LUT2 #( - .INIT(4'h8)) - ram_reg_0_31_0_5_i_1 - (.I0(s_axis_ready_reg_0), - .I1(sdi_data_valid), - .O(s_mem_write)); - LUT4 #( - .INIT(16'h8F70)) - s_axis_ready_i_10 - (.I0(s_axis_ready_reg_0), - .I1(sdi_data_valid), - .I2(p_0_in), - .I3(Q[1]), - .O(s_axis_ready_i_10_n_0)); - LUT4 #( - .INIT(16'h9666)) - s_axis_ready_i_11 - (.I0(Q[0]), - .I1(p_0_in), - .I2(sdi_data_valid), - .I3(s_axis_ready_reg_0), - .O(s_axis_ready_i_11_n_0)); - LUT6 #( - .INIT(64'hFFFFFFFFFFFFFFFB)) - s_axis_ready_i_1__1 - (.I0(level_next0_carry_n_7), - .I1(s_axis_ready_reg_i_2_n_6), - .I2(s_axis_ready_reg_i_3_n_4), - .I3(s_axis_ready_reg_i_3_n_6), - .I4(s_axis_ready_reg_i_3_n_5), - .I5(s_axis_ready_reg_i_2_n_7), - .O(s_axis_ready_i_1__1_n_0)); - LUT2 #( - .INIT(4'h9)) - s_axis_ready_i_4 - (.I0(Q[4]), - .I1(Q[5]), - .O(s_axis_ready_i_4_n_0)); - LUT2 #( - .INIT(4'h9)) - s_axis_ready_i_5 - (.I0(Q[3]), - .I1(Q[4]), - .O(s_axis_ready_i_5_n_0)); - LUT3 #( - .INIT(8'h8F)) - s_axis_ready_i_6 - (.I0(s_axis_ready_reg_0), - .I1(sdi_data_valid), - .I2(p_0_in), - .O(s_axis_ready_i_6_n_0)); - LUT2 #( - .INIT(4'h9)) - s_axis_ready_i_8 - (.I0(Q[2]), - .I1(Q[3]), - .O(s_axis_ready_i_8_n_0)); - LUT4 #( - .INIT(16'h8F70)) - s_axis_ready_i_9 - (.I0(s_axis_ready_reg_0), - .I1(sdi_data_valid), - .I2(p_0_in), - .I3(Q[2]), - .O(s_axis_ready_i_9_n_0)); - FDRE s_axis_ready_reg - (.C(s_axi_aclk), - .CE(1'b1), - .D(s_axis_ready_i_1__1_n_0), - .Q(s_axis_ready_reg_0), - .R(up_sw_reset)); - CARRY4 s_axis_ready_reg_i_2 - (.CI(s_axis_ready_reg_i_3_n_0), - .CO({NLW_s_axis_ready_reg_i_2_CO_UNCONNECTED[3:1],s_axis_ready_reg_i_2_n_3}), - .CYINIT(1'b0), - .DI({1'b0,1'b0,1'b0,Q[3]}), - .O({NLW_s_axis_ready_reg_i_2_O_UNCONNECTED[3:2],s_axis_ready_reg_i_2_n_6,s_axis_ready_reg_i_2_n_7}), - .S({1'b0,1'b0,s_axis_ready_i_4_n_0,s_axis_ready_i_5_n_0})); - CARRY4 s_axis_ready_reg_i_3 - (.CI(1'b0), - .CO({s_axis_ready_reg_i_3_n_0,s_axis_ready_reg_i_3_n_1,s_axis_ready_reg_i_3_n_2,s_axis_ready_reg_i_3_n_3}), - .CYINIT(1'b0), - .DI({Q[2],s_axis_ready_i_6_n_0,m_axis_valid_reg_1,Q[0]}), - .O({s_axis_ready_reg_i_3_n_4,s_axis_ready_reg_i_3_n_5,s_axis_ready_reg_i_3_n_6,NLW_s_axis_ready_reg_i_3_O_UNCONNECTED[0]}), - .S({s_axis_ready_i_8_n_0,s_axis_ready_i_9_n_0,s_axis_ready_i_10_n_0,s_axis_ready_i_11_n_0})); - LUT1 #( - .INIT(2'h1)) - \s_axis_waddr[0]_i_1__1 - (.I0(\s_axis_waddr_reg[4]_0 [0]), - .O(p_0_in__0[0])); - (* SOFT_HLUTNM = "soft_lutpair10" *) - LUT2 #( - .INIT(4'h6)) - \s_axis_waddr[1]_i_1__1 - (.I0(\s_axis_waddr_reg[4]_0 [0]), - .I1(\s_axis_waddr_reg[4]_0 [1]), - .O(p_0_in__0[1])); - (* SOFT_HLUTNM = "soft_lutpair10" *) - LUT3 #( - .INIT(8'h78)) - \s_axis_waddr[2]_i_1__1 - (.I0(\s_axis_waddr_reg[4]_0 [0]), - .I1(\s_axis_waddr_reg[4]_0 [1]), - .I2(\s_axis_waddr_reg[4]_0 [2]), - .O(p_0_in__0[2])); - (* SOFT_HLUTNM = "soft_lutpair7" *) - LUT4 #( - .INIT(16'h7F80)) - \s_axis_waddr[3]_i_1__1 - (.I0(\s_axis_waddr_reg[4]_0 [1]), - .I1(\s_axis_waddr_reg[4]_0 [0]), - .I2(\s_axis_waddr_reg[4]_0 [2]), - .I3(\s_axis_waddr_reg[4]_0 [3]), - .O(p_0_in__0[3])); - (* SOFT_HLUTNM = "soft_lutpair7" *) - LUT5 #( - .INIT(32'h7FFF8000)) - \s_axis_waddr[4]_i_1__0 - (.I0(\s_axis_waddr_reg[4]_0 [2]), - .I1(\s_axis_waddr_reg[4]_0 [0]), - .I2(\s_axis_waddr_reg[4]_0 [1]), - .I3(\s_axis_waddr_reg[4]_0 [3]), - .I4(\s_axis_waddr_reg[4]_0 [4]), - .O(p_0_in__0[4])); - FDRE \s_axis_waddr_reg[0] - (.C(s_axi_aclk), - .CE(s_mem_write), - .D(p_0_in__0[0]), - .Q(\s_axis_waddr_reg[4]_0 [0]), - .R(up_sw_reset)); - FDRE \s_axis_waddr_reg[1] - (.C(s_axi_aclk), - .CE(s_mem_write), - .D(p_0_in__0[1]), - .Q(\s_axis_waddr_reg[4]_0 [1]), - .R(up_sw_reset)); - FDRE \s_axis_waddr_reg[2] - (.C(s_axi_aclk), - .CE(s_mem_write), - .D(p_0_in__0[2]), - .Q(\s_axis_waddr_reg[4]_0 [2]), - .R(up_sw_reset)); - FDRE \s_axis_waddr_reg[3] - (.C(s_axi_aclk), - .CE(s_mem_write), - .D(p_0_in__0[3]), - .Q(\s_axis_waddr_reg[4]_0 [3]), - .R(up_sw_reset)); - FDRE \s_axis_waddr_reg[4] - (.C(s_axi_aclk), - .CE(s_mem_write), - .D(p_0_in__0[4]), - .Q(\s_axis_waddr_reg[4]_0 [4]), - .R(up_sw_reset)); - LUT3 #( - .INIT(8'hF8)) - \up_rdata_ff[2]_i_6 - (.I0(Q[4]), - .I1(Q[3]), - .I2(Q[5]), - .O(\level_reg[4]_0 )); -endmodule - -(* ORIG_REF_NAME = "up_axi" *) -module system_bd_axi_spi_engine_0_0_up_axi - (s_axi_aresetn_0, - up_wreq_s, - s_axi_bvalid, - s_axi_awready, - s_axi_wready, - up_rreq_s, - up_axi_rvalid_int_reg_0, - s_axi_arready, - s_mem_write, - Q, - \up_waddr_int_reg[4]_0 , - s_axis_ready_reg, - E, - \up_waddr_int_reg[2]_0 , - offload0_cmd_wr_en, - offload0_sdo_wr_en, - s_axis_ready_reg_0, - p_1_in, - \up_raddr_int_reg[5]_0 , - \up_raddr_int_reg[4]_0 , - \up_raddr_int_reg[0]_0 , - \up_raddr_int_reg[0]_1 , - \up_raddr_int_reg[3]_0 , - \up_scratch_reg[8] , - \up_scratch_reg[9] , - \up_scratch_reg[10] , - \up_scratch_reg[11] , - \up_scratch_reg[12] , - \up_scratch_reg[13] , - \up_scratch_reg[14] , - \up_scratch_reg[15] , - \up_scratch_reg[17] , - \up_scratch_reg[18] , - \up_scratch_reg[19] , - \up_scratch_reg[20] , - \up_scratch_reg[21] , - \up_scratch_reg[22] , - \up_scratch_reg[23] , - \up_scratch_reg[24] , - \up_scratch_reg[25] , - \up_scratch_reg[26] , - \up_scratch_reg[27] , - \up_scratch_reg[28] , - \up_scratch_reg[29] , - \up_scratch_reg[30] , - \up_scratch_reg[31] , - sdi_data_valid_0, - p_0_in, - \up_raddr_int_reg[3]_1 , - \up_raddr_int_reg[3]_2 , - \up_raddr_int_reg[3]_3 , - \up_raddr_int_reg[3]_4 , - \up_raddr_int_reg[9]_0 , - \up_raddr_int_reg[6]_0 , - DI, - \up_wdata_int_reg[0]_0 , - \up_wdata_int_reg[31]_0 , - \up_waddr_int_reg[0]_0 , - \up_wdata_int_reg[0]_1 , - \up_wdata_int_reg[0]_2 , - s_axi_rdata, - s_axi_aclk, - \s_axis_waddr_reg[0] , - \s_axis_waddr_reg[0]_0 , - up_wack_ff, - up_rack_ff, - s_axi_aresetn, - m_axis_data, - \up_rdata_ff_reg[31] , - sdi_data_valid, - sdi_data_ready, - \m_axis_raddr_reg[0] , - \up_rdata_ff_reg[7] , - \up_rdata_ff_reg[1] , - \up_rdata_ff_reg[5] , - \up_rdata_ff_reg[5]_0 , - up_irq_source, - offload0_enable, - \up_rdata_ff[3]_i_3_0 , - \up_rdata_ff_reg[7]_0 , - up_sw_reset, - sync_id_pending_reg, - \up_rdata_ff_reg[4] , - s_axi_wvalid, - s_axi_awvalid, - s_axi_bready, - s_axi_arvalid, - s_axi_rready, - up_rdata_ff, - offload0_enabled, - \up_rdata_ff[0]_i_8_0 , - sync_valid, - offload0_mem_reset, - s_axi_awaddr, - s_axi_wdata, - s_axi_araddr); - output s_axi_aresetn_0; - output up_wreq_s; - output s_axi_bvalid; - output s_axi_awready; - output s_axi_wready; - output up_rreq_s; - output up_axi_rvalid_int_reg_0; - output s_axi_arready; - output s_mem_write; - output [0:0]Q; - output \up_waddr_int_reg[4]_0 ; - output s_axis_ready_reg; - output [0:0]E; - output [0:0]\up_waddr_int_reg[2]_0 ; - output offload0_cmd_wr_en; - output offload0_sdo_wr_en; - output [0:0]s_axis_ready_reg_0; - output p_1_in; - output \up_raddr_int_reg[5]_0 ; - output [1:0]\up_raddr_int_reg[4]_0 ; - output \up_raddr_int_reg[0]_0 ; - output \up_raddr_int_reg[0]_1 ; - output \up_raddr_int_reg[3]_0 ; - output \up_scratch_reg[8] ; - output \up_scratch_reg[9] ; - output \up_scratch_reg[10] ; - output \up_scratch_reg[11] ; - output \up_scratch_reg[12] ; - output \up_scratch_reg[13] ; - output \up_scratch_reg[14] ; - output \up_scratch_reg[15] ; - output \up_scratch_reg[17] ; - output \up_scratch_reg[18] ; - output \up_scratch_reg[19] ; - output \up_scratch_reg[20] ; - output \up_scratch_reg[21] ; - output \up_scratch_reg[22] ; - output \up_scratch_reg[23] ; - output \up_scratch_reg[24] ; - output \up_scratch_reg[25] ; - output \up_scratch_reg[26] ; - output \up_scratch_reg[27] ; - output \up_scratch_reg[28] ; - output \up_scratch_reg[29] ; - output \up_scratch_reg[30] ; - output \up_scratch_reg[31] ; - output [0:0]sdi_data_valid_0; - output p_0_in; - output \up_raddr_int_reg[3]_1 ; - output \up_raddr_int_reg[3]_2 ; - output \up_raddr_int_reg[3]_3 ; - output \up_raddr_int_reg[3]_4 ; - output \up_raddr_int_reg[9]_0 ; - output \up_raddr_int_reg[6]_0 ; - output [0:0]DI; - output \up_wdata_int_reg[0]_0 ; - output [31:0]\up_wdata_int_reg[31]_0 ; - output \up_waddr_int_reg[0]_0 ; - output \up_wdata_int_reg[0]_1 ; - output \up_wdata_int_reg[0]_2 ; - output [31:0]s_axi_rdata; - input s_axi_aclk; - input \s_axis_waddr_reg[0] ; - input \s_axis_waddr_reg[0]_0 ; - input up_wack_ff; - input up_rack_ff; - input s_axi_aresetn; - input [7:0]m_axis_data; - input [31:0]\up_rdata_ff_reg[31] ; - input sdi_data_valid; - input sdi_data_ready; - input \m_axis_raddr_reg[0] ; - input [6:0]\up_rdata_ff_reg[7] ; - input \up_rdata_ff_reg[1] ; - input [5:0]\up_rdata_ff_reg[5] ; - input [4:0]\up_rdata_ff_reg[5]_0 ; - input [2:0]up_irq_source; - input offload0_enable; - input [3:0]\up_rdata_ff[3]_i_3_0 ; - input [7:0]\up_rdata_ff_reg[7]_0 ; - input up_sw_reset; - input [0:0]sync_id_pending_reg; - input [3:0]\up_rdata_ff_reg[4] ; - input s_axi_wvalid; - input s_axi_awvalid; - input s_axi_bready; - input s_axi_arvalid; - input s_axi_rready; - input [31:0]up_rdata_ff; - input offload0_enabled; - input [0:0]\up_rdata_ff[0]_i_8_0 ; - input sync_valid; - input offload0_mem_reset; - input [13:0]s_axi_awaddr; - input [31:0]s_axi_wdata; - input [13:0]s_axi_araddr; - - wire [0:0]DI; - wire [0:0]E; - wire [0:0]Q; - wire [7:0]m_axis_data; - wire \m_axis_raddr[4]_i_3_n_0 ; - wire \m_axis_raddr[4]_i_4_n_0 ; - wire \m_axis_raddr[4]_i_5_n_0 ; - wire \m_axis_raddr_reg[0] ; - wire offload0_cmd_wr_en; - wire offload0_cmd_wr_en_INST_0_i_1_n_0; - wire offload0_cmd_wr_en_INST_0_i_2_n_0; - wire offload0_cmd_wr_en_INST_0_i_3_n_0; - wire offload0_enable; - wire offload0_enable_reg_i_2_n_0; - wire offload0_enable_reg_i_3_n_0; - wire offload0_enable_reg_i_4_n_0; - wire offload0_enabled; - wire offload0_mem_reset; - wire offload0_mem_reset_reg_i_2_n_0; - wire offload0_mem_reset_reg_i_3_n_0; - wire offload0_mem_reset_reg_i_4_n_0; - wire offload0_sdo_wr_en; - wire p_0_in; - wire p_0_in6_in; - wire p_0_in7_in; - wire p_1_in; - wire p_1_in_0; - wire p_1_in__0; - wire [4:0]p_2_in; - wire p_5_in; - wire ram_reg_0_15_12_15_i_3_n_0; - wire s_axi_aclk; - wire [13:0]s_axi_araddr; - wire s_axi_aresetn; - wire s_axi_aresetn_0; - wire s_axi_arready; - wire s_axi_arvalid; - wire [13:0]s_axi_awaddr; - wire s_axi_awready; - wire s_axi_awvalid; - wire s_axi_bready; - wire s_axi_bvalid; - wire [31:0]s_axi_rdata; - wire s_axi_rready; - wire [31:0]s_axi_wdata; - wire s_axi_wready; - wire s_axi_wvalid; - wire s_axis_ready_reg; - wire [0:0]s_axis_ready_reg_0; - wire \s_axis_waddr[3]_i_3_n_0 ; - wire \s_axis_waddr[3]_i_4_n_0 ; - wire \s_axis_waddr[3]_i_5_n_0 ; - wire \s_axis_waddr[3]_i_6_n_0 ; - wire \s_axis_waddr_reg[0] ; - wire \s_axis_waddr_reg[0]_0 ; - wire s_mem_write; - wire sdi_data_ready; - wire sdi_data_valid; - wire [0:0]sdi_data_valid_0; - wire sync_id_pending_i_2_n_0; - wire sync_id_pending_i_3_n_0; - wire [0:0]sync_id_pending_reg; - wire sync_valid; - wire up_axi_arready_int_i_1_n_0; - wire up_axi_arready_int_i_2_n_0; - wire up_axi_awready_int_i_2_n_0; - wire up_axi_bvalid_int_i_1_n_0; - wire \up_axi_rdata_int[31]_i_1_n_0 ; - wire up_axi_rvalid_int_i_1_n_0; - wire up_axi_rvalid_int_reg_0; - wire up_axi_wready_int_i_1_n_0; - wire [2:0]up_irq_source; - wire up_rack_d; - wire up_rack_ff; - wire up_rack_s; - wire up_rack_s_1; - wire \up_raddr_int_reg[0]_0 ; - wire \up_raddr_int_reg[0]_1 ; - wire \up_raddr_int_reg[3]_0 ; - wire \up_raddr_int_reg[3]_1 ; - wire \up_raddr_int_reg[3]_2 ; - wire \up_raddr_int_reg[3]_3 ; - wire \up_raddr_int_reg[3]_4 ; - wire [1:0]\up_raddr_int_reg[4]_0 ; - wire \up_raddr_int_reg[5]_0 ; - wire \up_raddr_int_reg[6]_0 ; - wire \up_raddr_int_reg[9]_0 ; - wire [13:0]up_raddr_s; - wire \up_rcount[0]_i_1_n_0 ; - wire \up_rcount[1]_i_1_n_0 ; - wire \up_rcount[2]_i_1_n_0 ; - wire \up_rcount[3]_i_1_n_0 ; - wire \up_rcount[4]_i_1_n_0 ; - wire \up_rcount[4]_i_2_n_0 ; - wire \up_rcount_reg_n_0_[0] ; - wire \up_rcount_reg_n_0_[1] ; - wire \up_rcount_reg_n_0_[2] ; - wire \up_rcount_reg_n_0_[3] ; - wire [31:0]up_rdata_d; - wire \up_rdata_d[0]_i_1_n_0 ; - wire \up_rdata_d[10]_i_1_n_0 ; - wire \up_rdata_d[11]_i_1_n_0 ; - wire \up_rdata_d[12]_i_1_n_0 ; - wire \up_rdata_d[14]_i_1_n_0 ; - wire \up_rdata_d[15]_i_1_n_0 ; - wire \up_rdata_d[16]_i_1_n_0 ; - wire \up_rdata_d[18]_i_1_n_0 ; - wire \up_rdata_d[19]_i_1_n_0 ; - wire \up_rdata_d[21]_i_1_n_0 ; - wire \up_rdata_d[23]_i_1_n_0 ; - wire \up_rdata_d[25]_i_1_n_0 ; - wire \up_rdata_d[26]_i_1_n_0 ; - wire \up_rdata_d[27]_i_1_n_0 ; - wire \up_rdata_d[28]_i_1_n_0 ; - wire \up_rdata_d[29]_i_1_n_0 ; - wire \up_rdata_d[2]_i_1_n_0 ; - wire \up_rdata_d[30]_i_1_n_0 ; - wire \up_rdata_d[31]_i_1_n_0 ; - wire \up_rdata_d[31]_i_2_n_0 ; - wire \up_rdata_d[3]_i_1_n_0 ; - wire \up_rdata_d[5]_i_1_n_0 ; - wire \up_rdata_d[7]_i_1_n_0 ; - wire \up_rdata_d[9]_i_1_n_0 ; - wire [31:0]up_rdata_ff; - wire \up_rdata_ff[0]_i_10_n_0 ; - wire \up_rdata_ff[0]_i_11_n_0 ; - wire \up_rdata_ff[0]_i_12_n_0 ; - wire \up_rdata_ff[0]_i_2_n_0 ; - wire \up_rdata_ff[0]_i_3_n_0 ; - wire \up_rdata_ff[0]_i_4_n_0 ; - wire \up_rdata_ff[0]_i_5_n_0 ; - wire \up_rdata_ff[0]_i_6_n_0 ; - wire \up_rdata_ff[0]_i_7_n_0 ; - wire [0:0]\up_rdata_ff[0]_i_8_0 ; - wire \up_rdata_ff[0]_i_8_n_0 ; - wire \up_rdata_ff[0]_i_9_n_0 ; - wire \up_rdata_ff[16]_i_2_n_0 ; - wire \up_rdata_ff[16]_i_3_n_0 ; - wire \up_rdata_ff[1]_i_3_n_0 ; - wire \up_rdata_ff[1]_i_4_n_0 ; - wire \up_rdata_ff[1]_i_5_n_0 ; - wire \up_rdata_ff[1]_i_6_n_0 ; - wire \up_rdata_ff[1]_i_7_n_0 ; - wire \up_rdata_ff[2]_i_10_n_0 ; - wire \up_rdata_ff[2]_i_2_n_0 ; - wire \up_rdata_ff[2]_i_3_n_0 ; - wire \up_rdata_ff[2]_i_4_n_0 ; - wire \up_rdata_ff[2]_i_5_n_0 ; - wire \up_rdata_ff[2]_i_7_n_0 ; - wire \up_rdata_ff[2]_i_8_n_0 ; - wire \up_rdata_ff[2]_i_9_n_0 ; - wire \up_rdata_ff[31]_i_3_n_0 ; - wire \up_rdata_ff[31]_i_4_n_0 ; - wire \up_rdata_ff[3]_i_2_n_0 ; - wire [3:0]\up_rdata_ff[3]_i_3_0 ; - wire \up_rdata_ff[3]_i_3_n_0 ; - wire \up_rdata_ff[3]_i_4_n_0 ; - wire \up_rdata_ff[3]_i_5_n_0 ; - wire \up_rdata_ff[3]_i_6_n_0 ; - wire \up_rdata_ff[3]_i_7_n_0 ; - wire \up_rdata_ff[3]_i_8_n_0 ; - wire \up_rdata_ff[3]_i_9_n_0 ; - wire \up_rdata_ff[4]_i_2_n_0 ; - wire \up_rdata_ff[4]_i_3_n_0 ; - wire \up_rdata_ff[4]_i_4_n_0 ; - wire \up_rdata_ff[4]_i_5_n_0 ; - wire \up_rdata_ff[5]_i_2_n_0 ; - wire \up_rdata_ff[5]_i_3_n_0 ; - wire \up_rdata_ff[5]_i_4_n_0 ; - wire \up_rdata_ff[5]_i_5_n_0 ; - wire \up_rdata_ff[6]_i_2_n_0 ; - wire \up_rdata_ff[6]_i_3_n_0 ; - wire \up_rdata_ff[6]_i_4_n_0 ; - wire \up_rdata_ff[7]_i_2_n_0 ; - wire \up_rdata_ff[7]_i_3_n_0 ; - wire \up_rdata_ff_reg[1] ; - wire [31:0]\up_rdata_ff_reg[31] ; - wire [3:0]\up_rdata_ff_reg[4] ; - wire [5:0]\up_rdata_ff_reg[5] ; - wire [4:0]\up_rdata_ff_reg[5]_0 ; - wire [6:0]\up_rdata_ff_reg[7] ; - wire [7:0]\up_rdata_ff_reg[7]_0 ; - wire up_rreq_int_i_1_n_0; - wire up_rreq_s; - wire up_rsel_i_1_n_0; - wire up_rsel_reg_n_0; - wire \up_scratch[31]_i_2_n_0 ; - wire \up_scratch[31]_i_3_n_0 ; - wire \up_scratch_reg[10] ; - wire \up_scratch_reg[11] ; - wire \up_scratch_reg[12] ; - wire \up_scratch_reg[13] ; - wire \up_scratch_reg[14] ; - wire \up_scratch_reg[15] ; - wire \up_scratch_reg[17] ; - wire \up_scratch_reg[18] ; - wire \up_scratch_reg[19] ; - wire \up_scratch_reg[20] ; - wire \up_scratch_reg[21] ; - wire \up_scratch_reg[22] ; - wire \up_scratch_reg[23] ; - wire \up_scratch_reg[24] ; - wire \up_scratch_reg[25] ; - wire \up_scratch_reg[26] ; - wire \up_scratch_reg[27] ; - wire \up_scratch_reg[28] ; - wire \up_scratch_reg[29] ; - wire \up_scratch_reg[30] ; - wire \up_scratch_reg[31] ; - wire \up_scratch_reg[8] ; - wire \up_scratch_reg[9] ; - wire up_sw_reset; - wire up_sw_reset_i_2_n_0; - wire up_wack_d; - wire up_wack_ff; - wire up_wack_s; - wire \up_waddr_int_reg[0]_0 ; - wire [0:0]\up_waddr_int_reg[2]_0 ; - wire \up_waddr_int_reg[4]_0 ; - wire [13:1]up_waddr_s; - wire \up_wcount_reg_n_0_[0] ; - wire \up_wcount_reg_n_0_[1] ; - wire \up_wcount_reg_n_0_[2] ; - wire \up_wcount_reg_n_0_[3] ; - wire \up_wdata_int_reg[0]_0 ; - wire \up_wdata_int_reg[0]_1 ; - wire \up_wdata_int_reg[0]_2 ; - wire [31:0]\up_wdata_int_reg[31]_0 ; - wire up_wreq_int_i_1_n_0; - wire up_wreq_s; - wire up_wsel_i_1_n_0; - wire up_wsel_reg_n_0; - - LUT3 #( - .INIT(8'h2A)) - level_next0_carry_i_2 - (.I0(p_0_in), - .I1(sdi_data_valid), - .I2(sdi_data_ready), - .O(DI)); - LUT6 #( - .INIT(64'h0000000000080000)) - \m_axis_raddr[4]_i_1__0 - (.I0(\m_axis_raddr[4]_i_3_n_0 ), - .I1(\m_axis_raddr[4]_i_4_n_0 ), - .I2(\up_rdata_ff[3]_i_2_n_0 ), - .I3(up_raddr_s[13]), - .I4(\m_axis_raddr_reg[0] ), - .I5(\m_axis_raddr[4]_i_5_n_0 ), - .O(p_0_in)); - (* SOFT_HLUTNM = "soft_lutpair28" *) - LUT3 #( - .INIT(8'h40)) - \m_axis_raddr[4]_i_3 - (.I0(\up_raddr_int_reg[4]_0 [0]), - .I1(up_raddr_s[1]), - .I2(up_raddr_s[3]), - .O(\m_axis_raddr[4]_i_3_n_0 )); - LUT6 #( - .INIT(64'h0000000200000000)) - \m_axis_raddr[4]_i_4 - (.I0(up_rreq_s), - .I1(up_raddr_s[7]), - .I2(up_raddr_s[8]), - .I3(up_raddr_s[9]), - .I4(up_raddr_s[10]), - .I5(\up_rdata_ff[31]_i_3_n_0 ), - .O(\m_axis_raddr[4]_i_4_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair23" *) - LUT2 #( - .INIT(4'h7)) - \m_axis_raddr[4]_i_5 - (.I0(\up_raddr_int_reg[4]_0 [1]), - .I1(up_raddr_s[5]), - .O(\m_axis_raddr[4]_i_5_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair32" *) - LUT2 #( - .INIT(4'h2)) - offload0_cmd_wr_en_INST_0 - (.I0(offload0_cmd_wr_en_INST_0_i_1_n_0), - .I1(Q), - .O(offload0_cmd_wr_en)); - LUT6 #( - .INIT(64'h0002000000000000)) - offload0_cmd_wr_en_INST_0_i_1 - (.I0(up_waddr_s[6]), - .I1(up_waddr_s[5]), - .I2(up_waddr_s[4]), - .I3(up_waddr_s[3]), - .I4(up_waddr_s[2]), - .I5(offload0_cmd_wr_en_INST_0_i_2_n_0), - .O(offload0_cmd_wr_en_INST_0_i_1_n_0)); - LUT6 #( - .INIT(64'h0000000000000004)) - offload0_cmd_wr_en_INST_0_i_2 - (.I0(offload0_cmd_wr_en_INST_0_i_3_n_0), - .I1(up_wreq_s), - .I2(up_waddr_s[1]), - .I3(up_waddr_s[13]), - .I4(up_waddr_s[12]), - .I5(up_waddr_s[11]), - .O(offload0_cmd_wr_en_INST_0_i_2_n_0)); - (* SOFT_HLUTNM = "soft_lutpair29" *) - LUT4 #( - .INIT(16'hFFFE)) - offload0_cmd_wr_en_INST_0_i_3 - (.I0(up_waddr_s[7]), - .I1(up_waddr_s[8]), - .I2(up_waddr_s[9]), - .I3(up_waddr_s[10]), - .O(offload0_cmd_wr_en_INST_0_i_3_n_0)); - LUT6 #( - .INIT(64'hEFFFFFFF20000000)) - offload0_enable_reg_i_1 - (.I0(\up_wdata_int_reg[31]_0 [0]), - .I1(offload0_enable_reg_i_2_n_0), - .I2(offload0_enable_reg_i_3_n_0), - .I3(offload0_enable_reg_i_4_n_0), - .I4(offload0_mem_reset_reg_i_3_n_0), - .I5(offload0_enable), - .O(\up_wdata_int_reg[0]_1 )); - (* SOFT_HLUTNM = "soft_lutpair31" *) - LUT4 #( - .INIT(16'hFFFE)) - offload0_enable_reg_i_2 - (.I0(up_waddr_s[4]), - .I1(up_waddr_s[3]), - .I2(up_waddr_s[2]), - .I3(up_waddr_s[1]), - .O(offload0_enable_reg_i_2_n_0)); - (* SOFT_HLUTNM = "soft_lutpair58" *) - LUT2 #( - .INIT(4'h2)) - offload0_enable_reg_i_3 - (.I0(up_waddr_s[6]), - .I1(up_waddr_s[5]), - .O(offload0_enable_reg_i_3_n_0)); - (* SOFT_HLUTNM = "soft_lutpair42" *) - LUT2 #( - .INIT(4'h2)) - offload0_enable_reg_i_4 - (.I0(up_wreq_s), - .I1(Q), - .O(offload0_enable_reg_i_4_n_0)); - LUT4 #( - .INIT(16'hBF80)) - offload0_mem_reset_reg_i_1 - (.I0(\up_wdata_int_reg[31]_0 [0]), - .I1(offload0_mem_reset_reg_i_2_n_0), - .I2(offload0_mem_reset_reg_i_3_n_0), - .I3(offload0_mem_reset), - .O(\up_wdata_int_reg[0]_2 )); - LUT6 #( - .INIT(64'h0000000002000000)) - offload0_mem_reset_reg_i_2 - (.I0(up_wreq_s), - .I1(Q), - .I2(up_waddr_s[5]), - .I3(up_waddr_s[6]), - .I4(up_waddr_s[1]), - .I5(offload0_mem_reset_reg_i_4_n_0), - .O(offload0_mem_reset_reg_i_2_n_0)); - (* SOFT_HLUTNM = "soft_lutpair29" *) - LUT5 #( - .INIT(32'h00000001)) - offload0_mem_reset_reg_i_3 - (.I0(\s_axis_waddr[3]_i_4_n_0 ), - .I1(up_waddr_s[10]), - .I2(up_waddr_s[9]), - .I3(up_waddr_s[8]), - .I4(up_waddr_s[7]), - .O(offload0_mem_reset_reg_i_3_n_0)); - (* SOFT_HLUTNM = "soft_lutpair31" *) - LUT3 #( - .INIT(8'hFE)) - offload0_mem_reset_reg_i_4 - (.I0(up_waddr_s[2]), - .I1(up_waddr_s[3]), - .I2(up_waddr_s[4]), - .O(offload0_mem_reset_reg_i_4_n_0)); - (* SOFT_HLUTNM = "soft_lutpair42" *) - LUT2 #( - .INIT(4'h8)) - offload0_sdo_wr_en_INST_0 - (.I0(Q), - .I1(offload0_cmd_wr_en_INST_0_i_1_n_0), - .O(offload0_sdo_wr_en)); - LUT3 #( - .INIT(8'h20)) - ram_reg_0_15_12_15_i_1 - (.I0(\s_axis_waddr_reg[0] ), - .I1(Q), - .I2(\up_waddr_int_reg[4]_0 ), - .O(s_mem_write)); - LUT6 #( - .INIT(64'h0000000000800000)) - ram_reg_0_15_12_15_i_2 - (.I0(up_waddr_s[4]), - .I1(up_waddr_s[3]), - .I2(\s_axis_waddr[3]_i_5_n_0 ), - .I3(\s_axis_waddr[3]_i_4_n_0 ), - .I4(ram_reg_0_15_12_15_i_3_n_0), - .I5(up_waddr_s[2]), - .O(\up_waddr_int_reg[4]_0 )); - (* SOFT_HLUTNM = "soft_lutpair58" *) - LUT2 #( - .INIT(4'h2)) - ram_reg_0_15_12_15_i_3 - (.I0(up_waddr_s[5]), - .I1(up_waddr_s[6]), - .O(ram_reg_0_15_12_15_i_3_n_0)); - LUT3 #( - .INIT(8'h80)) - ram_reg_0_31_6_7_i_1 - (.I0(\s_axis_waddr_reg[0]_0 ), - .I1(\up_waddr_int_reg[4]_0 ), - .I2(Q), - .O(s_axis_ready_reg)); - LUT3 #( - .INIT(8'h2A)) - s_axis_ready_i_7 - (.I0(p_0_in), - .I1(sdi_data_valid), - .I2(sdi_data_ready), - .O(sdi_data_valid_0)); - LUT6 #( - .INIT(64'h0040000000000000)) - \s_axis_waddr[3]_i_1 - (.I0(Q), - .I1(\s_axis_waddr_reg[0] ), - .I2(\s_axis_waddr[3]_i_3_n_0 ), - .I3(\s_axis_waddr[3]_i_4_n_0 ), - .I4(\s_axis_waddr[3]_i_5_n_0 ), - .I5(\s_axis_waddr[3]_i_6_n_0 ), - .O(p_1_in)); - (* SOFT_HLUTNM = "soft_lutpair25" *) - LUT3 #( - .INIT(8'h04)) - \s_axis_waddr[3]_i_3 - (.I0(up_waddr_s[6]), - .I1(up_waddr_s[5]), - .I2(up_waddr_s[2]), - .O(\s_axis_waddr[3]_i_3_n_0 )); - LUT3 #( - .INIT(8'hFE)) - \s_axis_waddr[3]_i_4 - (.I0(up_waddr_s[11]), - .I1(up_waddr_s[12]), - .I2(up_waddr_s[13]), - .O(\s_axis_waddr[3]_i_4_n_0 )); - LUT6 #( - .INIT(64'h0000000000000004)) - \s_axis_waddr[3]_i_5 - (.I0(up_waddr_s[1]), - .I1(up_wreq_s), - .I2(up_waddr_s[10]), - .I3(up_waddr_s[9]), - .I4(up_waddr_s[8]), - .I5(up_waddr_s[7]), - .O(\s_axis_waddr[3]_i_5_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair33" *) - LUT2 #( - .INIT(4'h8)) - \s_axis_waddr[3]_i_6 - (.I0(up_waddr_s[3]), - .I1(up_waddr_s[4]), - .O(\s_axis_waddr[3]_i_6_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair32" *) - LUT3 #( - .INIT(8'h80)) - \s_axis_waddr[4]_i_1 - (.I0(\s_axis_waddr_reg[0]_0 ), - .I1(Q), - .I2(\up_waddr_int_reg[4]_0 ), - .O(s_axis_ready_reg_0)); - LUT6 #( - .INIT(64'hFFFF7FFFFFFF0000)) - sync_id_pending_i_1 - (.I0(sync_id_pending_i_2_n_0), - .I1(Q), - .I2(\up_wdata_int_reg[31]_0 [3]), - .I3(sync_id_pending_i_3_n_0), - .I4(sync_valid), - .I5(sync_id_pending_reg), - .O(\up_waddr_int_reg[0]_0 )); - (* SOFT_HLUTNM = "soft_lutpair25" *) - LUT5 #( - .INIT(32'h00040000)) - sync_id_pending_i_2 - (.I0(up_waddr_s[2]), - .I1(up_waddr_s[5]), - .I2(up_waddr_s[6]), - .I3(\s_axis_waddr[3]_i_4_n_0 ), - .I4(\s_axis_waddr[3]_i_5_n_0 ), - .O(sync_id_pending_i_2_n_0)); - (* SOFT_HLUTNM = "soft_lutpair33" *) - LUT2 #( - .INIT(4'h1)) - sync_id_pending_i_3 - (.I0(up_waddr_s[4]), - .I1(up_waddr_s[3]), - .O(sync_id_pending_i_3_n_0)); - LUT4 #( - .INIT(16'h5540)) - up_axi_arready_int_i_1 - (.I0(s_axi_arready), - .I1(p_0_in6_in), - .I2(up_rack_ff), - .I3(up_axi_arready_int_i_2_n_0), - .O(up_axi_arready_int_i_1_n_0)); - LUT5 #( - .INIT(32'h80000000)) - up_axi_arready_int_i_2 - (.I0(\up_rcount_reg_n_0_[0] ), - .I1(\up_rcount_reg_n_0_[1] ), - .I2(\up_rcount_reg_n_0_[2] ), - .I3(p_0_in6_in), - .I4(\up_rcount_reg_n_0_[3] ), - .O(up_axi_arready_int_i_2_n_0)); - FDRE #( - .INIT(1'b0)) - up_axi_arready_int_reg - (.C(s_axi_aclk), - .CE(1'b1), - .D(up_axi_arready_int_i_1_n_0), - .Q(s_axi_arready), - .R(s_axi_aresetn_0)); - LUT1 #( - .INIT(2'h1)) - up_axi_awready_int_i_1 - (.I0(s_axi_aresetn), - .O(s_axi_aresetn_0)); - (* SOFT_HLUTNM = "soft_lutpair57" *) - LUT2 #( - .INIT(4'h4)) - up_axi_awready_int_i_2 - (.I0(s_axi_awready), - .I1(up_wack_s), - .O(up_axi_awready_int_i_2_n_0)); - FDRE #( - .INIT(1'b0)) - up_axi_awready_int_reg - (.C(s_axi_aclk), - .CE(1'b1), - .D(up_axi_awready_int_i_2_n_0), - .Q(s_axi_awready), - .R(s_axi_aresetn_0)); - LUT4 #( - .INIT(16'h0C88)) - up_axi_bvalid_int_i_1 - (.I0(up_wack_d), - .I1(s_axi_aresetn), - .I2(s_axi_bready), - .I3(s_axi_bvalid), - .O(up_axi_bvalid_int_i_1_n_0)); - FDRE #( - .INIT(1'b0)) - up_axi_bvalid_int_reg - (.C(s_axi_aclk), - .CE(1'b1), - .D(up_axi_bvalid_int_i_1_n_0), - .Q(s_axi_bvalid), - .R(1'b0)); - LUT3 #( - .INIT(8'h8F)) - \up_axi_rdata_int[31]_i_1 - (.I0(up_axi_rvalid_int_reg_0), - .I1(s_axi_rready), - .I2(s_axi_aresetn), - .O(\up_axi_rdata_int[31]_i_1_n_0 )); - FDRE #( - .INIT(1'b0)) - \up_axi_rdata_int_reg[0] - (.C(s_axi_aclk), - .CE(up_rack_d), - .D(up_rdata_d[0]), - .Q(s_axi_rdata[0]), - .R(\up_axi_rdata_int[31]_i_1_n_0 )); - FDRE #( - .INIT(1'b0)) - \up_axi_rdata_int_reg[10] - (.C(s_axi_aclk), - .CE(up_rack_d), - .D(up_rdata_d[10]), - .Q(s_axi_rdata[10]), - .R(\up_axi_rdata_int[31]_i_1_n_0 )); - FDRE #( - .INIT(1'b0)) - \up_axi_rdata_int_reg[11] - (.C(s_axi_aclk), - .CE(up_rack_d), - .D(up_rdata_d[11]), - .Q(s_axi_rdata[11]), - .R(\up_axi_rdata_int[31]_i_1_n_0 )); - FDRE #( - .INIT(1'b0)) - \up_axi_rdata_int_reg[12] - (.C(s_axi_aclk), - .CE(up_rack_d), - .D(up_rdata_d[12]), - .Q(s_axi_rdata[12]), - .R(\up_axi_rdata_int[31]_i_1_n_0 )); - FDRE #( - .INIT(1'b0)) - \up_axi_rdata_int_reg[13] - (.C(s_axi_aclk), - .CE(up_rack_d), - .D(up_rdata_d[13]), - .Q(s_axi_rdata[13]), - .R(\up_axi_rdata_int[31]_i_1_n_0 )); - FDRE #( - .INIT(1'b0)) - \up_axi_rdata_int_reg[14] - (.C(s_axi_aclk), - .CE(up_rack_d), - .D(up_rdata_d[14]), - .Q(s_axi_rdata[14]), - .R(\up_axi_rdata_int[31]_i_1_n_0 )); - FDRE #( - .INIT(1'b0)) - \up_axi_rdata_int_reg[15] - (.C(s_axi_aclk), - .CE(up_rack_d), - .D(up_rdata_d[15]), - .Q(s_axi_rdata[15]), - .R(\up_axi_rdata_int[31]_i_1_n_0 )); - FDRE #( - .INIT(1'b0)) - \up_axi_rdata_int_reg[16] - (.C(s_axi_aclk), - .CE(up_rack_d), - .D(up_rdata_d[16]), - .Q(s_axi_rdata[16]), - .R(\up_axi_rdata_int[31]_i_1_n_0 )); - FDRE #( - .INIT(1'b0)) - \up_axi_rdata_int_reg[17] - (.C(s_axi_aclk), - .CE(up_rack_d), - .D(up_rdata_d[17]), - .Q(s_axi_rdata[17]), - .R(\up_axi_rdata_int[31]_i_1_n_0 )); - FDRE #( - .INIT(1'b0)) - \up_axi_rdata_int_reg[18] - (.C(s_axi_aclk), - .CE(up_rack_d), - .D(up_rdata_d[18]), - .Q(s_axi_rdata[18]), - .R(\up_axi_rdata_int[31]_i_1_n_0 )); - FDRE #( - .INIT(1'b0)) - \up_axi_rdata_int_reg[19] - (.C(s_axi_aclk), - .CE(up_rack_d), - .D(up_rdata_d[19]), - .Q(s_axi_rdata[19]), - .R(\up_axi_rdata_int[31]_i_1_n_0 )); - FDRE #( - .INIT(1'b0)) - \up_axi_rdata_int_reg[1] - (.C(s_axi_aclk), - .CE(up_rack_d), - .D(up_rdata_d[1]), - .Q(s_axi_rdata[1]), - .R(\up_axi_rdata_int[31]_i_1_n_0 )); - FDRE #( - .INIT(1'b0)) - \up_axi_rdata_int_reg[20] - (.C(s_axi_aclk), - .CE(up_rack_d), - .D(up_rdata_d[20]), - .Q(s_axi_rdata[20]), - .R(\up_axi_rdata_int[31]_i_1_n_0 )); - FDRE #( - .INIT(1'b0)) - \up_axi_rdata_int_reg[21] - (.C(s_axi_aclk), - .CE(up_rack_d), - .D(up_rdata_d[21]), - .Q(s_axi_rdata[21]), - .R(\up_axi_rdata_int[31]_i_1_n_0 )); - FDRE #( - .INIT(1'b0)) - \up_axi_rdata_int_reg[22] - (.C(s_axi_aclk), - .CE(up_rack_d), - .D(up_rdata_d[22]), - .Q(s_axi_rdata[22]), - .R(\up_axi_rdata_int[31]_i_1_n_0 )); - FDRE #( - .INIT(1'b0)) - \up_axi_rdata_int_reg[23] - (.C(s_axi_aclk), - .CE(up_rack_d), - .D(up_rdata_d[23]), - .Q(s_axi_rdata[23]), - .R(\up_axi_rdata_int[31]_i_1_n_0 )); - FDRE #( - .INIT(1'b0)) - \up_axi_rdata_int_reg[24] - (.C(s_axi_aclk), - .CE(up_rack_d), - .D(up_rdata_d[24]), - .Q(s_axi_rdata[24]), - .R(\up_axi_rdata_int[31]_i_1_n_0 )); - FDRE #( - .INIT(1'b0)) - \up_axi_rdata_int_reg[25] - (.C(s_axi_aclk), - .CE(up_rack_d), - .D(up_rdata_d[25]), - .Q(s_axi_rdata[25]), - .R(\up_axi_rdata_int[31]_i_1_n_0 )); - FDRE #( - .INIT(1'b0)) - \up_axi_rdata_int_reg[26] - (.C(s_axi_aclk), - .CE(up_rack_d), - .D(up_rdata_d[26]), - .Q(s_axi_rdata[26]), - .R(\up_axi_rdata_int[31]_i_1_n_0 )); - FDRE #( - .INIT(1'b0)) - \up_axi_rdata_int_reg[27] - (.C(s_axi_aclk), - .CE(up_rack_d), - .D(up_rdata_d[27]), - .Q(s_axi_rdata[27]), - .R(\up_axi_rdata_int[31]_i_1_n_0 )); - FDRE #( - .INIT(1'b0)) - \up_axi_rdata_int_reg[28] - (.C(s_axi_aclk), - .CE(up_rack_d), - .D(up_rdata_d[28]), - .Q(s_axi_rdata[28]), - .R(\up_axi_rdata_int[31]_i_1_n_0 )); - FDRE #( - .INIT(1'b0)) - \up_axi_rdata_int_reg[29] - (.C(s_axi_aclk), - .CE(up_rack_d), - .D(up_rdata_d[29]), - .Q(s_axi_rdata[29]), - .R(\up_axi_rdata_int[31]_i_1_n_0 )); - FDRE #( - .INIT(1'b0)) - \up_axi_rdata_int_reg[2] - (.C(s_axi_aclk), - .CE(up_rack_d), - .D(up_rdata_d[2]), - .Q(s_axi_rdata[2]), - .R(\up_axi_rdata_int[31]_i_1_n_0 )); - FDRE #( - .INIT(1'b0)) - \up_axi_rdata_int_reg[30] - (.C(s_axi_aclk), - .CE(up_rack_d), - .D(up_rdata_d[30]), - .Q(s_axi_rdata[30]), - .R(\up_axi_rdata_int[31]_i_1_n_0 )); - FDRE #( - .INIT(1'b0)) - \up_axi_rdata_int_reg[31] - (.C(s_axi_aclk), - .CE(up_rack_d), - .D(up_rdata_d[31]), - .Q(s_axi_rdata[31]), - .R(\up_axi_rdata_int[31]_i_1_n_0 )); - FDRE #( - .INIT(1'b0)) - \up_axi_rdata_int_reg[3] - (.C(s_axi_aclk), - .CE(up_rack_d), - .D(up_rdata_d[3]), - .Q(s_axi_rdata[3]), - .R(\up_axi_rdata_int[31]_i_1_n_0 )); - FDRE #( - .INIT(1'b0)) - \up_axi_rdata_int_reg[4] - (.C(s_axi_aclk), - .CE(up_rack_d), - .D(up_rdata_d[4]), - .Q(s_axi_rdata[4]), - .R(\up_axi_rdata_int[31]_i_1_n_0 )); - FDRE #( - .INIT(1'b0)) - \up_axi_rdata_int_reg[5] - (.C(s_axi_aclk), - .CE(up_rack_d), - .D(up_rdata_d[5]), - .Q(s_axi_rdata[5]), - .R(\up_axi_rdata_int[31]_i_1_n_0 )); - FDRE #( - .INIT(1'b0)) - \up_axi_rdata_int_reg[6] - (.C(s_axi_aclk), - .CE(up_rack_d), - .D(up_rdata_d[6]), - .Q(s_axi_rdata[6]), - .R(\up_axi_rdata_int[31]_i_1_n_0 )); - FDRE #( - .INIT(1'b0)) - \up_axi_rdata_int_reg[7] - (.C(s_axi_aclk), - .CE(up_rack_d), - .D(up_rdata_d[7]), - .Q(s_axi_rdata[7]), - .R(\up_axi_rdata_int[31]_i_1_n_0 )); - FDRE #( - .INIT(1'b0)) - \up_axi_rdata_int_reg[8] - (.C(s_axi_aclk), - .CE(up_rack_d), - .D(up_rdata_d[8]), - .Q(s_axi_rdata[8]), - .R(\up_axi_rdata_int[31]_i_1_n_0 )); - FDRE #( - .INIT(1'b0)) - \up_axi_rdata_int_reg[9] - (.C(s_axi_aclk), - .CE(up_rack_d), - .D(up_rdata_d[9]), - .Q(s_axi_rdata[9]), - .R(\up_axi_rdata_int[31]_i_1_n_0 )); - LUT4 #( - .INIT(16'h0C88)) - up_axi_rvalid_int_i_1 - (.I0(up_rack_d), - .I1(s_axi_aresetn), - .I2(s_axi_rready), - .I3(up_axi_rvalid_int_reg_0), - .O(up_axi_rvalid_int_i_1_n_0)); - FDRE #( - .INIT(1'b0)) - up_axi_rvalid_int_reg - (.C(s_axi_aclk), - .CE(1'b1), - .D(up_axi_rvalid_int_i_1_n_0), - .Q(up_axi_rvalid_int_reg_0), - .R(1'b0)); - (* SOFT_HLUTNM = "soft_lutpair57" *) - LUT2 #( - .INIT(4'h4)) - up_axi_wready_int_i_1 - (.I0(s_axi_wready), - .I1(up_wack_s), - .O(up_axi_wready_int_i_1_n_0)); - FDRE #( - .INIT(1'b0)) - up_axi_wready_int_reg - (.C(s_axi_aclk), - .CE(1'b1), - .D(up_axi_wready_int_i_1_n_0), - .Q(s_axi_wready), - .R(s_axi_aresetn_0)); - LUT6 #( - .INIT(64'h0010000000000000)) - \up_irq_mask[3]_i_1 - (.I0(offload0_enable_reg_i_2_n_0), - .I1(up_waddr_s[6]), - .I2(up_waddr_s[5]), - .I3(Q), - .I4(up_wreq_s), - .I5(offload0_mem_reset_reg_i_3_n_0), - .O(E)); - LUT6 #( - .INIT(64'hFFFF800000000000)) - up_rack_d_i_1 - (.I0(\up_rcount_reg_n_0_[3] ), - .I1(\up_rcount_reg_n_0_[2] ), - .I2(\up_rcount_reg_n_0_[1] ), - .I3(\up_rcount_reg_n_0_[0] ), - .I4(up_rack_ff), - .I5(p_0_in6_in), - .O(up_rack_s_1)); - FDRE #( - .INIT(1'b0)) - up_rack_d_reg - (.C(s_axi_aclk), - .CE(1'b1), - .D(up_rack_s_1), - .Q(up_rack_d), - .R(s_axi_aresetn_0)); - LUT1 #( - .INIT(2'h1)) - \up_raddr_int[13]_i_1 - (.I0(up_rsel_reg_n_0), - .O(p_1_in_0)); - FDRE #( - .INIT(1'b0)) - \up_raddr_int_reg[0] - (.C(s_axi_aclk), - .CE(p_1_in_0), - .D(s_axi_araddr[0]), - .Q(up_raddr_s[0]), - .R(s_axi_aresetn_0)); - FDRE #( - .INIT(1'b0)) - \up_raddr_int_reg[10] - (.C(s_axi_aclk), - .CE(p_1_in_0), - .D(s_axi_araddr[10]), - .Q(up_raddr_s[10]), - .R(s_axi_aresetn_0)); - FDRE #( - .INIT(1'b0)) - \up_raddr_int_reg[11] - (.C(s_axi_aclk), - .CE(p_1_in_0), - .D(s_axi_araddr[11]), - .Q(up_raddr_s[11]), - .R(s_axi_aresetn_0)); - FDRE #( - .INIT(1'b0)) - \up_raddr_int_reg[12] - (.C(s_axi_aclk), - .CE(p_1_in_0), - .D(s_axi_araddr[12]), - .Q(up_raddr_s[12]), - .R(s_axi_aresetn_0)); - FDRE #( - .INIT(1'b0)) - \up_raddr_int_reg[13] - (.C(s_axi_aclk), - .CE(p_1_in_0), - .D(s_axi_araddr[13]), - .Q(up_raddr_s[13]), - .R(s_axi_aresetn_0)); - FDRE #( - .INIT(1'b0)) - \up_raddr_int_reg[1] - (.C(s_axi_aclk), - .CE(p_1_in_0), - .D(s_axi_araddr[1]), - .Q(up_raddr_s[1]), - .R(s_axi_aresetn_0)); - FDRE #( - .INIT(1'b0)) - \up_raddr_int_reg[2] - (.C(s_axi_aclk), - .CE(p_1_in_0), - .D(s_axi_araddr[2]), - .Q(\up_raddr_int_reg[4]_0 [0]), - .R(s_axi_aresetn_0)); - FDRE #( - .INIT(1'b0)) - \up_raddr_int_reg[3] - (.C(s_axi_aclk), - .CE(p_1_in_0), - .D(s_axi_araddr[3]), - .Q(up_raddr_s[3]), - .R(s_axi_aresetn_0)); - FDRE #( - .INIT(1'b0)) - \up_raddr_int_reg[4] - (.C(s_axi_aclk), - .CE(p_1_in_0), - .D(s_axi_araddr[4]), - .Q(\up_raddr_int_reg[4]_0 [1]), - .R(s_axi_aresetn_0)); - FDRE #( - .INIT(1'b0)) - \up_raddr_int_reg[5] - (.C(s_axi_aclk), - .CE(p_1_in_0), - .D(s_axi_araddr[5]), - .Q(up_raddr_s[5]), - .R(s_axi_aresetn_0)); - FDRE #( - .INIT(1'b0)) - \up_raddr_int_reg[6] - (.C(s_axi_aclk), - .CE(p_1_in_0), - .D(s_axi_araddr[6]), - .Q(up_raddr_s[6]), - .R(s_axi_aresetn_0)); - FDRE #( - .INIT(1'b0)) - \up_raddr_int_reg[7] - (.C(s_axi_aclk), - .CE(p_1_in_0), - .D(s_axi_araddr[7]), - .Q(up_raddr_s[7]), - .R(s_axi_aresetn_0)); - FDRE #( - .INIT(1'b0)) - \up_raddr_int_reg[8] - (.C(s_axi_aclk), - .CE(p_1_in_0), - .D(s_axi_araddr[8]), - .Q(up_raddr_s[8]), - .R(s_axi_aresetn_0)); - FDRE #( - .INIT(1'b0)) - \up_raddr_int_reg[9] - (.C(s_axi_aclk), - .CE(p_1_in_0), - .D(s_axi_araddr[9]), - .Q(up_raddr_s[9]), - .R(s_axi_aresetn_0)); - LUT3 #( - .INIT(8'h04)) - \up_rcount[0]_i_1 - (.I0(up_rack_ff), - .I1(p_0_in6_in), - .I2(\up_rcount_reg_n_0_[0] ), - .O(\up_rcount[0]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair19" *) - LUT4 #( - .INIT(16'h0060)) - \up_rcount[1]_i_1 - (.I0(\up_rcount_reg_n_0_[0] ), - .I1(\up_rcount_reg_n_0_[1] ), - .I2(p_0_in6_in), - .I3(up_rack_ff), - .O(\up_rcount[1]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair19" *) - LUT5 #( - .INIT(32'h00007800)) - \up_rcount[2]_i_1 - (.I0(\up_rcount_reg_n_0_[0] ), - .I1(\up_rcount_reg_n_0_[1] ), - .I2(\up_rcount_reg_n_0_[2] ), - .I3(p_0_in6_in), - .I4(up_rack_ff), - .O(\up_rcount[2]_i_1_n_0 )); - LUT6 #( - .INIT(64'h000000007F008000)) - \up_rcount[3]_i_1 - (.I0(\up_rcount_reg_n_0_[0] ), - .I1(\up_rcount_reg_n_0_[1] ), - .I2(\up_rcount_reg_n_0_[2] ), - .I3(p_0_in6_in), - .I4(\up_rcount_reg_n_0_[3] ), - .I5(up_rack_ff), - .O(\up_rcount[3]_i_1_n_0 )); - LUT3 #( - .INIT(8'hFE)) - \up_rcount[4]_i_1 - (.I0(up_rreq_s), - .I1(p_0_in6_in), - .I2(up_rack_s), - .O(\up_rcount[4]_i_1_n_0 )); - LUT6 #( - .INIT(64'h1F5F5F5F5F5F5F5F)) - \up_rcount[4]_i_2 - (.I0(up_rack_ff), - .I1(\up_rcount_reg_n_0_[3] ), - .I2(p_0_in6_in), - .I3(\up_rcount_reg_n_0_[2] ), - .I4(\up_rcount_reg_n_0_[1] ), - .I5(\up_rcount_reg_n_0_[0] ), - .O(\up_rcount[4]_i_2_n_0 )); - LUT6 #( - .INIT(64'hE0A0A0A0A0A0A0A0)) - \up_rcount[4]_i_3 - (.I0(up_rack_ff), - .I1(\up_rcount_reg_n_0_[3] ), - .I2(p_0_in6_in), - .I3(\up_rcount_reg_n_0_[2] ), - .I4(\up_rcount_reg_n_0_[1] ), - .I5(\up_rcount_reg_n_0_[0] ), - .O(up_rack_s)); - FDRE #( - .INIT(1'b0)) - \up_rcount_reg[0] - (.C(s_axi_aclk), - .CE(\up_rcount[4]_i_1_n_0 ), - .D(\up_rcount[0]_i_1_n_0 ), - .Q(\up_rcount_reg_n_0_[0] ), - .R(s_axi_aresetn_0)); - FDRE #( - .INIT(1'b0)) - \up_rcount_reg[1] - (.C(s_axi_aclk), - .CE(\up_rcount[4]_i_1_n_0 ), - .D(\up_rcount[1]_i_1_n_0 ), - .Q(\up_rcount_reg_n_0_[1] ), - .R(s_axi_aresetn_0)); - FDRE #( - .INIT(1'b0)) - \up_rcount_reg[2] - (.C(s_axi_aclk), - .CE(\up_rcount[4]_i_1_n_0 ), - .D(\up_rcount[2]_i_1_n_0 ), - .Q(\up_rcount_reg_n_0_[2] ), - .R(s_axi_aresetn_0)); - FDRE #( - .INIT(1'b0)) - \up_rcount_reg[3] - (.C(s_axi_aclk), - .CE(\up_rcount[4]_i_1_n_0 ), - .D(\up_rcount[3]_i_1_n_0 ), - .Q(\up_rcount_reg_n_0_[3] ), - .R(s_axi_aresetn_0)); - FDRE #( - .INIT(1'b0)) - \up_rcount_reg[4] - (.C(s_axi_aclk), - .CE(\up_rcount[4]_i_1_n_0 ), - .D(\up_rcount[4]_i_2_n_0 ), - .Q(p_0_in6_in), - .R(s_axi_aresetn_0)); - (* SOFT_HLUTNM = "soft_lutpair45" *) - LUT2 #( - .INIT(4'h8)) - \up_rdata_d[0]_i_1 - (.I0(up_rdata_ff[0]), - .I1(s_axi_aresetn), - .O(\up_rdata_d[0]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair41" *) - LUT2 #( - .INIT(4'h8)) - \up_rdata_d[10]_i_1 - (.I0(up_rdata_ff[10]), - .I1(s_axi_aresetn), - .O(\up_rdata_d[10]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair41" *) - LUT2 #( - .INIT(4'h8)) - \up_rdata_d[11]_i_1 - (.I0(up_rdata_ff[11]), - .I1(s_axi_aresetn), - .O(\up_rdata_d[11]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair40" *) - LUT2 #( - .INIT(4'h8)) - \up_rdata_d[12]_i_1 - (.I0(up_rdata_ff[12]), - .I1(s_axi_aresetn), - .O(\up_rdata_d[12]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair40" *) - LUT2 #( - .INIT(4'h8)) - \up_rdata_d[14]_i_1 - (.I0(up_rdata_ff[14]), - .I1(s_axi_aresetn), - .O(\up_rdata_d[14]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair39" *) - LUT2 #( - .INIT(4'h8)) - \up_rdata_d[15]_i_1 - (.I0(up_rdata_ff[15]), - .I1(s_axi_aresetn), - .O(\up_rdata_d[15]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair39" *) - LUT2 #( - .INIT(4'h8)) - \up_rdata_d[16]_i_1 - (.I0(up_rdata_ff[16]), - .I1(s_axi_aresetn), - .O(\up_rdata_d[16]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair38" *) - LUT2 #( - .INIT(4'h8)) - \up_rdata_d[18]_i_1 - (.I0(up_rdata_ff[18]), - .I1(s_axi_aresetn), - .O(\up_rdata_d[18]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair38" *) - LUT2 #( - .INIT(4'h8)) - \up_rdata_d[19]_i_1 - (.I0(up_rdata_ff[19]), - .I1(s_axi_aresetn), - .O(\up_rdata_d[19]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair37" *) - LUT2 #( - .INIT(4'h8)) - \up_rdata_d[21]_i_1 - (.I0(up_rdata_ff[21]), - .I1(s_axi_aresetn), - .O(\up_rdata_d[21]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair37" *) - LUT2 #( - .INIT(4'h8)) - \up_rdata_d[23]_i_1 - (.I0(up_rdata_ff[23]), - .I1(s_axi_aresetn), - .O(\up_rdata_d[23]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair36" *) - LUT2 #( - .INIT(4'h8)) - \up_rdata_d[25]_i_1 - (.I0(up_rdata_ff[25]), - .I1(s_axi_aresetn), - .O(\up_rdata_d[25]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair36" *) - LUT2 #( - .INIT(4'h8)) - \up_rdata_d[26]_i_1 - (.I0(up_rdata_ff[26]), - .I1(s_axi_aresetn), - .O(\up_rdata_d[26]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair35" *) - LUT2 #( - .INIT(4'h8)) - \up_rdata_d[27]_i_1 - (.I0(up_rdata_ff[27]), - .I1(s_axi_aresetn), - .O(\up_rdata_d[27]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair35" *) - LUT2 #( - .INIT(4'h8)) - \up_rdata_d[28]_i_1 - (.I0(up_rdata_ff[28]), - .I1(s_axi_aresetn), - .O(\up_rdata_d[28]_i_1_n_0 )); - LUT6 #( - .INIT(64'h80000000FFFFFFFF)) - \up_rdata_d[29]_i_1 - (.I0(\up_rcount_reg_n_0_[3] ), - .I1(p_0_in6_in), - .I2(\up_rcount_reg_n_0_[2] ), - .I3(\up_rcount_reg_n_0_[1] ), - .I4(\up_rcount_reg_n_0_[0] ), - .I5(s_axi_aresetn), - .O(\up_rdata_d[29]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair44" *) - LUT2 #( - .INIT(4'h8)) - \up_rdata_d[2]_i_1 - (.I0(up_rdata_ff[2]), - .I1(s_axi_aresetn), - .O(\up_rdata_d[2]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair34" *) - LUT2 #( - .INIT(4'h8)) - \up_rdata_d[30]_i_1 - (.I0(up_rdata_ff[30]), - .I1(s_axi_aresetn), - .O(\up_rdata_d[30]_i_1_n_0 )); - LUT6 #( - .INIT(64'h8000000000000000)) - \up_rdata_d[31]_i_1 - (.I0(\up_rcount_reg_n_0_[3] ), - .I1(p_0_in6_in), - .I2(\up_rcount_reg_n_0_[2] ), - .I3(\up_rcount_reg_n_0_[1] ), - .I4(\up_rcount_reg_n_0_[0] ), - .I5(s_axi_aresetn), - .O(\up_rdata_d[31]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair34" *) - LUT2 #( - .INIT(4'h8)) - \up_rdata_d[31]_i_2 - (.I0(up_rdata_ff[31]), - .I1(s_axi_aresetn), - .O(\up_rdata_d[31]_i_2_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair45" *) - LUT2 #( - .INIT(4'h8)) - \up_rdata_d[3]_i_1 - (.I0(up_rdata_ff[3]), - .I1(s_axi_aresetn), - .O(\up_rdata_d[3]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair43" *) - LUT2 #( - .INIT(4'h8)) - \up_rdata_d[5]_i_1 - (.I0(up_rdata_ff[5]), - .I1(s_axi_aresetn), - .O(\up_rdata_d[5]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair44" *) - LUT2 #( - .INIT(4'h8)) - \up_rdata_d[7]_i_1 - (.I0(up_rdata_ff[7]), - .I1(s_axi_aresetn), - .O(\up_rdata_d[7]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair43" *) - LUT2 #( - .INIT(4'h8)) - \up_rdata_d[9]_i_1 - (.I0(up_rdata_ff[9]), - .I1(s_axi_aresetn), - .O(\up_rdata_d[9]_i_1_n_0 )); - FDSE #( - .INIT(1'b0)) - \up_rdata_d_reg[0] - (.C(s_axi_aclk), - .CE(1'b1), - .D(\up_rdata_d[0]_i_1_n_0 ), - .Q(up_rdata_d[0]), - .S(\up_rdata_d[31]_i_1_n_0 )); - FDSE #( - .INIT(1'b0)) - \up_rdata_d_reg[10] - (.C(s_axi_aclk), - .CE(1'b1), - .D(\up_rdata_d[10]_i_1_n_0 ), - .Q(up_rdata_d[10]), - .S(\up_rdata_d[31]_i_1_n_0 )); - FDSE #( - .INIT(1'b0)) - \up_rdata_d_reg[11] - (.C(s_axi_aclk), - .CE(1'b1), - .D(\up_rdata_d[11]_i_1_n_0 ), - .Q(up_rdata_d[11]), - .S(\up_rdata_d[31]_i_1_n_0 )); - FDSE #( - .INIT(1'b0)) - \up_rdata_d_reg[12] - (.C(s_axi_aclk), - .CE(1'b1), - .D(\up_rdata_d[12]_i_1_n_0 ), - .Q(up_rdata_d[12]), - .S(\up_rdata_d[31]_i_1_n_0 )); - FDRE #( - .INIT(1'b0)) - \up_rdata_d_reg[13] - (.C(s_axi_aclk), - .CE(1'b1), - .D(up_rdata_ff[13]), - .Q(up_rdata_d[13]), - .R(\up_rdata_d[29]_i_1_n_0 )); - FDSE #( - .INIT(1'b0)) - \up_rdata_d_reg[14] - (.C(s_axi_aclk), - .CE(1'b1), - .D(\up_rdata_d[14]_i_1_n_0 ), - .Q(up_rdata_d[14]), - .S(\up_rdata_d[31]_i_1_n_0 )); - FDSE #( - .INIT(1'b0)) - \up_rdata_d_reg[15] - (.C(s_axi_aclk), - .CE(1'b1), - .D(\up_rdata_d[15]_i_1_n_0 ), - .Q(up_rdata_d[15]), - .S(\up_rdata_d[31]_i_1_n_0 )); - FDSE #( - .INIT(1'b0)) - \up_rdata_d_reg[16] - (.C(s_axi_aclk), - .CE(1'b1), - .D(\up_rdata_d[16]_i_1_n_0 ), - .Q(up_rdata_d[16]), - .S(\up_rdata_d[31]_i_1_n_0 )); - FDRE #( - .INIT(1'b0)) - \up_rdata_d_reg[17] - (.C(s_axi_aclk), - .CE(1'b1), - .D(up_rdata_ff[17]), - .Q(up_rdata_d[17]), - .R(\up_rdata_d[29]_i_1_n_0 )); - FDSE #( - .INIT(1'b0)) - \up_rdata_d_reg[18] - (.C(s_axi_aclk), - .CE(1'b1), - .D(\up_rdata_d[18]_i_1_n_0 ), - .Q(up_rdata_d[18]), - .S(\up_rdata_d[31]_i_1_n_0 )); - FDSE #( - .INIT(1'b0)) - \up_rdata_d_reg[19] - (.C(s_axi_aclk), - .CE(1'b1), - .D(\up_rdata_d[19]_i_1_n_0 ), - .Q(up_rdata_d[19]), - .S(\up_rdata_d[31]_i_1_n_0 )); - FDRE #( - .INIT(1'b0)) - \up_rdata_d_reg[1] - (.C(s_axi_aclk), - .CE(1'b1), - .D(up_rdata_ff[1]), - .Q(up_rdata_d[1]), - .R(\up_rdata_d[29]_i_1_n_0 )); - FDRE #( - .INIT(1'b0)) - \up_rdata_d_reg[20] - (.C(s_axi_aclk), - .CE(1'b1), - .D(up_rdata_ff[20]), - .Q(up_rdata_d[20]), - .R(\up_rdata_d[29]_i_1_n_0 )); - FDSE #( - .INIT(1'b0)) - \up_rdata_d_reg[21] - (.C(s_axi_aclk), - .CE(1'b1), - .D(\up_rdata_d[21]_i_1_n_0 ), - .Q(up_rdata_d[21]), - .S(\up_rdata_d[31]_i_1_n_0 )); - FDRE #( - .INIT(1'b0)) - \up_rdata_d_reg[22] - (.C(s_axi_aclk), - .CE(1'b1), - .D(up_rdata_ff[22]), - .Q(up_rdata_d[22]), - .R(\up_rdata_d[29]_i_1_n_0 )); - FDSE #( - .INIT(1'b0)) - \up_rdata_d_reg[23] - (.C(s_axi_aclk), - .CE(1'b1), - .D(\up_rdata_d[23]_i_1_n_0 ), - .Q(up_rdata_d[23]), - .S(\up_rdata_d[31]_i_1_n_0 )); - FDRE #( - .INIT(1'b0)) - \up_rdata_d_reg[24] - (.C(s_axi_aclk), - .CE(1'b1), - .D(up_rdata_ff[24]), - .Q(up_rdata_d[24]), - .R(\up_rdata_d[29]_i_1_n_0 )); - FDSE #( - .INIT(1'b0)) - \up_rdata_d_reg[25] - (.C(s_axi_aclk), - .CE(1'b1), - .D(\up_rdata_d[25]_i_1_n_0 ), - .Q(up_rdata_d[25]), - .S(\up_rdata_d[31]_i_1_n_0 )); - FDSE #( - .INIT(1'b0)) - \up_rdata_d_reg[26] - (.C(s_axi_aclk), - .CE(1'b1), - .D(\up_rdata_d[26]_i_1_n_0 ), - .Q(up_rdata_d[26]), - .S(\up_rdata_d[31]_i_1_n_0 )); - FDSE #( - .INIT(1'b0)) - \up_rdata_d_reg[27] - (.C(s_axi_aclk), - .CE(1'b1), - .D(\up_rdata_d[27]_i_1_n_0 ), - .Q(up_rdata_d[27]), - .S(\up_rdata_d[31]_i_1_n_0 )); - FDSE #( - .INIT(1'b0)) - \up_rdata_d_reg[28] - (.C(s_axi_aclk), - .CE(1'b1), - .D(\up_rdata_d[28]_i_1_n_0 ), - .Q(up_rdata_d[28]), - .S(\up_rdata_d[31]_i_1_n_0 )); - FDRE #( - .INIT(1'b0)) - \up_rdata_d_reg[29] - (.C(s_axi_aclk), - .CE(1'b1), - .D(up_rdata_ff[29]), - .Q(up_rdata_d[29]), - .R(\up_rdata_d[29]_i_1_n_0 )); - FDSE #( - .INIT(1'b0)) - \up_rdata_d_reg[2] - (.C(s_axi_aclk), - .CE(1'b1), - .D(\up_rdata_d[2]_i_1_n_0 ), - .Q(up_rdata_d[2]), - .S(\up_rdata_d[31]_i_1_n_0 )); - FDSE #( - .INIT(1'b0)) - \up_rdata_d_reg[30] - (.C(s_axi_aclk), - .CE(1'b1), - .D(\up_rdata_d[30]_i_1_n_0 ), - .Q(up_rdata_d[30]), - .S(\up_rdata_d[31]_i_1_n_0 )); - FDSE #( - .INIT(1'b0)) - \up_rdata_d_reg[31] - (.C(s_axi_aclk), - .CE(1'b1), - .D(\up_rdata_d[31]_i_2_n_0 ), - .Q(up_rdata_d[31]), - .S(\up_rdata_d[31]_i_1_n_0 )); - FDSE #( - .INIT(1'b0)) - \up_rdata_d_reg[3] - (.C(s_axi_aclk), - .CE(1'b1), - .D(\up_rdata_d[3]_i_1_n_0 ), - .Q(up_rdata_d[3]), - .S(\up_rdata_d[31]_i_1_n_0 )); - FDRE #( - .INIT(1'b0)) - \up_rdata_d_reg[4] - (.C(s_axi_aclk), - .CE(1'b1), - .D(up_rdata_ff[4]), - .Q(up_rdata_d[4]), - .R(\up_rdata_d[29]_i_1_n_0 )); - FDSE #( - .INIT(1'b0)) - \up_rdata_d_reg[5] - (.C(s_axi_aclk), - .CE(1'b1), - .D(\up_rdata_d[5]_i_1_n_0 ), - .Q(up_rdata_d[5]), - .S(\up_rdata_d[31]_i_1_n_0 )); - FDRE #( - .INIT(1'b0)) - \up_rdata_d_reg[6] - (.C(s_axi_aclk), - .CE(1'b1), - .D(up_rdata_ff[6]), - .Q(up_rdata_d[6]), - .R(\up_rdata_d[29]_i_1_n_0 )); - FDSE #( - .INIT(1'b0)) - \up_rdata_d_reg[7] - (.C(s_axi_aclk), - .CE(1'b1), - .D(\up_rdata_d[7]_i_1_n_0 ), - .Q(up_rdata_d[7]), - .S(\up_rdata_d[31]_i_1_n_0 )); - FDRE #( - .INIT(1'b0)) - \up_rdata_d_reg[8] - (.C(s_axi_aclk), - .CE(1'b1), - .D(up_rdata_ff[8]), - .Q(up_rdata_d[8]), - .R(\up_rdata_d[29]_i_1_n_0 )); - FDSE #( - .INIT(1'b0)) - \up_rdata_d_reg[9] - (.C(s_axi_aclk), - .CE(1'b1), - .D(\up_rdata_d[9]_i_1_n_0 ), - .Q(up_rdata_d[9]), - .S(\up_rdata_d[31]_i_1_n_0 )); - LUT6 #( - .INIT(64'hFFFFFFFFABABABAA)) - \up_rdata_ff[0]_i_1 - (.I0(\up_rdata_ff[0]_i_2_n_0 ), - .I1(up_raddr_s[3]), - .I2(up_raddr_s[0]), - .I3(\up_rdata_ff[0]_i_3_n_0 ), - .I4(\up_rdata_ff[0]_i_4_n_0 ), - .I5(\up_rdata_ff[0]_i_5_n_0 ), - .O(\up_raddr_int_reg[3]_3 )); - (* SOFT_HLUTNM = "soft_lutpair22" *) - LUT5 #( - .INIT(32'h12020000)) - \up_rdata_ff[0]_i_10 - (.I0(up_raddr_s[5]), - .I1(up_raddr_s[1]), - .I2(up_raddr_s[6]), - .I3(offload0_enabled), - .I4(up_raddr_s[0]), - .O(\up_rdata_ff[0]_i_10_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair27" *) - LUT5 #( - .INIT(32'h8888F555)) - \up_rdata_ff[0]_i_11 - (.I0(up_raddr_s[5]), - .I1(\up_rdata_ff_reg[7] [0]), - .I2(up_irq_source[0]), - .I3(\up_rdata_ff[3]_i_3_0 [0]), - .I4(\up_raddr_int_reg[4]_0 [1]), - .O(\up_rdata_ff[0]_i_11_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair20" *) - LUT5 #( - .INIT(32'h44400040)) - \up_rdata_ff[0]_i_12 - (.I0(up_raddr_s[6]), - .I1(\up_raddr_int_reg[4]_0 [0]), - .I2(\up_rdata_ff[0]_i_8_0 ), - .I3(up_raddr_s[1]), - .I4(\up_rdata_ff_reg[5] [0]), - .O(\up_rdata_ff[0]_i_12_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair28" *) - LUT5 #( - .INIT(32'h03100000)) - \up_rdata_ff[0]_i_2 - (.I0(up_raddr_s[0]), - .I1(\up_rdata_ff[0]_i_6_n_0 ), - .I2(\up_raddr_int_reg[4]_0 [0]), - .I3(up_raddr_s[1]), - .I4(up_raddr_s[3]), - .O(\up_rdata_ff[0]_i_2_n_0 )); - LUT6 #( - .INIT(64'h00000022000000F2)) - \up_rdata_ff[0]_i_3 - (.I0(offload0_enable), - .I1(\up_rdata_ff[16]_i_3_n_0 ), - .I2(\up_rdata_ff[0]_i_7_n_0 ), - .I3(\up_raddr_int_reg[4]_0 [0]), - .I4(up_raddr_s[1]), - .I5(up_raddr_s[6]), - .O(\up_rdata_ff[0]_i_3_n_0 )); - LUT6 #( - .INIT(64'hAAAAAEAAAAAAAAAA)) - \up_rdata_ff[0]_i_4 - (.I0(\up_rdata_ff[0]_i_8_n_0 ), - .I1(up_irq_source[0]), - .I2(up_raddr_s[6]), - .I3(up_raddr_s[5]), - .I4(\up_raddr_int_reg[4]_0 [1]), - .I5(\up_rdata_ff[0]_i_9_n_0 ), - .O(\up_rdata_ff[0]_i_4_n_0 )); - LUT6 #( - .INIT(64'h000800A800080008)) - \up_rdata_ff[0]_i_5 - (.I0(\up_rdata_ff[0]_i_10_n_0 ), - .I1(\up_rdata_ff[0]_i_11_n_0 ), - .I2(\up_raddr_int_reg[4]_0 [0]), - .I3(up_raddr_s[3]), - .I4(\m_axis_raddr[4]_i_5_n_0 ), - .I5(\up_rdata_ff_reg[5]_0 [0]), - .O(\up_rdata_ff[0]_i_5_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair30" *) - LUT4 #( - .INIT(16'hDFFF)) - \up_rdata_ff[0]_i_6 - (.I0(m_axis_data[0]), - .I1(up_raddr_s[6]), - .I2(up_raddr_s[5]), - .I3(\up_raddr_int_reg[4]_0 [1]), - .O(\up_rdata_ff[0]_i_6_n_0 )); - LUT5 #( - .INIT(32'hCAFFCA0F)) - \up_rdata_ff[0]_i_7 - (.I0(\up_rdata_ff[3]_i_3_0 [0]), - .I1(\up_rdata_ff_reg[7]_0 [0]), - .I2(\up_raddr_int_reg[4]_0 [1]), - .I3(up_raddr_s[5]), - .I4(up_sw_reset), - .O(\up_rdata_ff[0]_i_7_n_0 )); - LUT6 #( - .INIT(64'h8080808080838080)) - \up_rdata_ff[0]_i_8 - (.I0(\up_rdata_ff[0]_i_12_n_0 ), - .I1(\up_raddr_int_reg[4]_0 [1]), - .I2(up_raddr_s[5]), - .I3(\up_raddr_int_reg[4]_0 [0]), - .I4(\up_rdata_ff_reg[31] [0]), - .I5(up_raddr_s[6]), - .O(\up_rdata_ff[0]_i_8_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair26" *) - LUT2 #( - .INIT(4'h2)) - \up_rdata_ff[0]_i_9 - (.I0(up_raddr_s[1]), - .I1(\up_raddr_int_reg[4]_0 [0]), - .O(\up_rdata_ff[0]_i_9_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair48" *) - LUT2 #( - .INIT(4'h8)) - \up_rdata_ff[10]_i_1 - (.I0(\up_rdata_ff[31]_i_4_n_0 ), - .I1(\up_rdata_ff_reg[31] [10]), - .O(\up_scratch_reg[10] )); - (* SOFT_HLUTNM = "soft_lutpair49" *) - LUT2 #( - .INIT(4'h8)) - \up_rdata_ff[11]_i_1 - (.I0(\up_rdata_ff[31]_i_4_n_0 ), - .I1(\up_rdata_ff_reg[31] [11]), - .O(\up_scratch_reg[11] )); - (* SOFT_HLUTNM = "soft_lutpair50" *) - LUT2 #( - .INIT(4'h8)) - \up_rdata_ff[12]_i_1 - (.I0(\up_rdata_ff[31]_i_4_n_0 ), - .I1(\up_rdata_ff_reg[31] [12]), - .O(\up_scratch_reg[12] )); - (* SOFT_HLUTNM = "soft_lutpair51" *) - LUT2 #( - .INIT(4'h8)) - \up_rdata_ff[13]_i_1 - (.I0(\up_rdata_ff[31]_i_4_n_0 ), - .I1(\up_rdata_ff_reg[31] [13]), - .O(\up_scratch_reg[13] )); - (* SOFT_HLUTNM = "soft_lutpair52" *) - LUT2 #( - .INIT(4'h8)) - \up_rdata_ff[14]_i_1 - (.I0(\up_rdata_ff[31]_i_4_n_0 ), - .I1(\up_rdata_ff_reg[31] [14]), - .O(\up_scratch_reg[14] )); - (* SOFT_HLUTNM = "soft_lutpair53" *) - LUT2 #( - .INIT(4'h8)) - \up_rdata_ff[15]_i_1 - (.I0(\up_rdata_ff[31]_i_4_n_0 ), - .I1(\up_rdata_ff_reg[31] [15]), - .O(\up_scratch_reg[15] )); - LUT6 #( - .INIT(64'h0101000101000001)) - \up_rdata_ff[16]_i_1 - (.I0(\up_rdata_ff[16]_i_2_n_0 ), - .I1(\up_rdata_ff[16]_i_3_n_0 ), - .I2(up_raddr_s[6]), - .I3(up_raddr_s[0]), - .I4(up_raddr_s[1]), - .I5(\up_rdata_ff_reg[31] [16]), - .O(\up_raddr_int_reg[6]_0 )); - (* SOFT_HLUTNM = "soft_lutpair18" *) - LUT2 #( - .INIT(4'hE)) - \up_rdata_ff[16]_i_2 - (.I0(up_raddr_s[3]), - .I1(\up_raddr_int_reg[4]_0 [0]), - .O(\up_rdata_ff[16]_i_2_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair27" *) - LUT2 #( - .INIT(4'hE)) - \up_rdata_ff[16]_i_3 - (.I0(\up_raddr_int_reg[4]_0 [1]), - .I1(up_raddr_s[5]), - .O(\up_rdata_ff[16]_i_3_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair54" *) - LUT2 #( - .INIT(4'h8)) - \up_rdata_ff[17]_i_1 - (.I0(\up_rdata_ff[31]_i_4_n_0 ), - .I1(\up_rdata_ff_reg[31] [17]), - .O(\up_scratch_reg[17] )); - (* SOFT_HLUTNM = "soft_lutpair55" *) - LUT2 #( - .INIT(4'h8)) - \up_rdata_ff[18]_i_1 - (.I0(\up_rdata_ff[31]_i_4_n_0 ), - .I1(\up_rdata_ff_reg[31] [18]), - .O(\up_scratch_reg[18] )); - (* SOFT_HLUTNM = "soft_lutpair56" *) - LUT2 #( - .INIT(4'h8)) - \up_rdata_ff[19]_i_1 - (.I0(\up_rdata_ff[31]_i_4_n_0 ), - .I1(\up_rdata_ff_reg[31] [19]), - .O(\up_scratch_reg[19] )); - LUT6 #( - .INIT(64'h02020000FF000000)) - \up_rdata_ff[1]_i_1 - (.I0(\up_rdata_ff_reg[1] ), - .I1(\up_rdata_ff[2]_i_3_n_0 ), - .I2(up_raddr_s[3]), - .I3(\up_rdata_ff[1]_i_3_n_0 ), - .I4(\up_rdata_ff[1]_i_4_n_0 ), - .I5(up_raddr_s[0]), - .O(\up_raddr_int_reg[3]_1 )); - LUT6 #( - .INIT(64'hEFEEEEEEEEEEEEEE)) - \up_rdata_ff[1]_i_3 - (.I0(\up_rdata_ff[1]_i_5_n_0 ), - .I1(\up_rdata_ff[1]_i_6_n_0 ), - .I2(\m_axis_raddr[4]_i_5_n_0 ), - .I3(up_raddr_s[1]), - .I4(\up_rdata_ff[2]_i_9_n_0 ), - .I5(\up_rdata_ff_reg[5] [1]), - .O(\up_rdata_ff[1]_i_3_n_0 )); - LUT3 #( - .INIT(8'h32)) - \up_rdata_ff[1]_i_4 - (.I0(up_raddr_s[5]), - .I1(up_raddr_s[6]), - .I2(\up_rdata_ff_reg[31] [1]), - .O(\up_rdata_ff[1]_i_4_n_0 )); - LUT6 #( - .INIT(64'h00000000FFFF2230)) - \up_rdata_ff[1]_i_5 - (.I0(\up_rdata_ff_reg[7]_0 [1]), - .I1(\up_rdata_ff[16]_i_2_n_0 ), - .I2(\up_rdata_ff[3]_i_3_0 [1]), - .I3(\up_raddr_int_reg[4]_0 [1]), - .I4(\up_rdata_ff[1]_i_7_n_0 ), - .I5(\up_rdata_ff[2]_i_3_n_0 ), - .O(\up_rdata_ff[1]_i_5_n_0 )); - LUT6 #( - .INIT(64'h8280020002020202)) - \up_rdata_ff[1]_i_6 - (.I0(\up_rdata_ff[0]_i_9_n_0 ), - .I1(\up_raddr_int_reg[4]_0 [1]), - .I2(up_raddr_s[3]), - .I3(up_irq_source[1]), - .I4(m_axis_data[1]), - .I5(up_raddr_s[5]), - .O(\up_rdata_ff[1]_i_6_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair24" *) - LUT5 #( - .INIT(32'h8080C000)) - \up_rdata_ff[1]_i_7 - (.I0(m_axis_data[1]), - .I1(\up_raddr_int_reg[4]_0 [1]), - .I2(\up_raddr_int_reg[4]_0 [0]), - .I3(\up_rdata_ff_reg[4] [0]), - .I4(up_raddr_s[3]), - .O(\up_rdata_ff[1]_i_7_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair56" *) - LUT2 #( - .INIT(4'h8)) - \up_rdata_ff[20]_i_1 - (.I0(\up_rdata_ff[31]_i_4_n_0 ), - .I1(\up_rdata_ff_reg[31] [20]), - .O(\up_scratch_reg[20] )); - (* SOFT_HLUTNM = "soft_lutpair55" *) - LUT2 #( - .INIT(4'h8)) - \up_rdata_ff[21]_i_1 - (.I0(\up_rdata_ff[31]_i_4_n_0 ), - .I1(\up_rdata_ff_reg[31] [21]), - .O(\up_scratch_reg[21] )); - (* SOFT_HLUTNM = "soft_lutpair54" *) - LUT2 #( - .INIT(4'h8)) - \up_rdata_ff[22]_i_1 - (.I0(\up_rdata_ff[31]_i_4_n_0 ), - .I1(\up_rdata_ff_reg[31] [22]), - .O(\up_scratch_reg[22] )); - (* SOFT_HLUTNM = "soft_lutpair53" *) - LUT2 #( - .INIT(4'h8)) - \up_rdata_ff[23]_i_1 - (.I0(\up_rdata_ff[31]_i_4_n_0 ), - .I1(\up_rdata_ff_reg[31] [23]), - .O(\up_scratch_reg[23] )); - (* SOFT_HLUTNM = "soft_lutpair52" *) - LUT2 #( - .INIT(4'h8)) - \up_rdata_ff[24]_i_1 - (.I0(\up_rdata_ff[31]_i_4_n_0 ), - .I1(\up_rdata_ff_reg[31] [24]), - .O(\up_scratch_reg[24] )); - (* SOFT_HLUTNM = "soft_lutpair51" *) - LUT2 #( - .INIT(4'h8)) - \up_rdata_ff[25]_i_1 - (.I0(\up_rdata_ff[31]_i_4_n_0 ), - .I1(\up_rdata_ff_reg[31] [25]), - .O(\up_scratch_reg[25] )); - (* SOFT_HLUTNM = "soft_lutpair50" *) - LUT2 #( - .INIT(4'h8)) - \up_rdata_ff[26]_i_1 - (.I0(\up_rdata_ff[31]_i_4_n_0 ), - .I1(\up_rdata_ff_reg[31] [26]), - .O(\up_scratch_reg[26] )); - (* SOFT_HLUTNM = "soft_lutpair49" *) - LUT2 #( - .INIT(4'h8)) - \up_rdata_ff[27]_i_1 - (.I0(\up_rdata_ff[31]_i_4_n_0 ), - .I1(\up_rdata_ff_reg[31] [27]), - .O(\up_scratch_reg[27] )); - LUT2 #( - .INIT(4'h8)) - \up_rdata_ff[28]_i_1 - (.I0(\up_rdata_ff[31]_i_4_n_0 ), - .I1(\up_rdata_ff_reg[31] [28]), - .O(\up_scratch_reg[28] )); - (* SOFT_HLUTNM = "soft_lutpair48" *) - LUT2 #( - .INIT(4'h8)) - \up_rdata_ff[29]_i_1 - (.I0(\up_rdata_ff[31]_i_4_n_0 ), - .I1(\up_rdata_ff_reg[31] [29]), - .O(\up_scratch_reg[29] )); - LUT6 #( - .INIT(64'h02020000FF000000)) - \up_rdata_ff[2]_i_1 - (.I0(\up_rdata_ff[2]_i_2_n_0 ), - .I1(\up_rdata_ff[2]_i_3_n_0 ), - .I2(up_raddr_s[3]), - .I3(\up_rdata_ff[2]_i_4_n_0 ), - .I4(\up_rdata_ff[2]_i_5_n_0 ), - .I5(up_raddr_s[0]), - .O(\up_raddr_int_reg[3]_2 )); - (* SOFT_HLUTNM = "soft_lutpair18" *) - LUT5 #( - .INIT(32'h8080C000)) - \up_rdata_ff[2]_i_10 - (.I0(m_axis_data[2]), - .I1(\up_raddr_int_reg[4]_0 [1]), - .I2(\up_raddr_int_reg[4]_0 [0]), - .I3(\up_rdata_ff_reg[4] [1]), - .I4(up_raddr_s[3]), - .O(\up_rdata_ff[2]_i_10_n_0 )); - LUT6 #( - .INIT(64'hFF000000F0F08888)) - \up_rdata_ff[2]_i_2 - (.I0(\up_rdata_ff[3]_i_3_0 [2]), - .I1(up_irq_source[2]), - .I2(\up_rdata_ff_reg[7] [1]), - .I3(\up_rdata_ff_reg[5]_0 [1]), - .I4(\up_raddr_int_reg[4]_0 [1]), - .I5(\up_raddr_int_reg[4]_0 [0]), - .O(\up_rdata_ff[2]_i_2_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair22" *) - LUT2 #( - .INIT(4'hB)) - \up_rdata_ff[2]_i_3 - (.I0(up_raddr_s[1]), - .I1(up_raddr_s[5]), - .O(\up_rdata_ff[2]_i_3_n_0 )); - LUT6 #( - .INIT(64'hEFEEEEEEEEEEEEEE)) - \up_rdata_ff[2]_i_4 - (.I0(\up_rdata_ff[2]_i_7_n_0 ), - .I1(\up_rdata_ff[2]_i_8_n_0 ), - .I2(\m_axis_raddr[4]_i_5_n_0 ), - .I3(up_raddr_s[1]), - .I4(\up_rdata_ff[2]_i_9_n_0 ), - .I5(\up_rdata_ff_reg[5] [2]), - .O(\up_rdata_ff[2]_i_4_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair30" *) - LUT3 #( - .INIT(8'h32)) - \up_rdata_ff[2]_i_5 - (.I0(up_raddr_s[5]), - .I1(up_raddr_s[6]), - .I2(\up_rdata_ff_reg[31] [2]), - .O(\up_rdata_ff[2]_i_5_n_0 )); - LUT6 #( - .INIT(64'h00000000FFFF2230)) - \up_rdata_ff[2]_i_7 - (.I0(\up_rdata_ff_reg[7]_0 [2]), - .I1(\up_rdata_ff[16]_i_2_n_0 ), - .I2(\up_rdata_ff[3]_i_3_0 [2]), - .I3(\up_raddr_int_reg[4]_0 [1]), - .I4(\up_rdata_ff[2]_i_10_n_0 ), - .I5(\up_rdata_ff[2]_i_3_n_0 ), - .O(\up_rdata_ff[2]_i_7_n_0 )); - LUT6 #( - .INIT(64'h8280020002020202)) - \up_rdata_ff[2]_i_8 - (.I0(\up_rdata_ff[0]_i_9_n_0 ), - .I1(\up_raddr_int_reg[4]_0 [1]), - .I2(up_raddr_s[3]), - .I3(up_irq_source[2]), - .I4(m_axis_data[2]), - .I5(up_raddr_s[5]), - .O(\up_rdata_ff[2]_i_8_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair24" *) - LUT2 #( - .INIT(4'h2)) - \up_rdata_ff[2]_i_9 - (.I0(\up_raddr_int_reg[4]_0 [0]), - .I1(up_raddr_s[3]), - .O(\up_rdata_ff[2]_i_9_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair47" *) - LUT2 #( - .INIT(4'h8)) - \up_rdata_ff[30]_i_1 - (.I0(\up_rdata_ff[31]_i_4_n_0 ), - .I1(\up_rdata_ff_reg[31] [30]), - .O(\up_scratch_reg[30] )); - LUT6 #( - .INIT(64'hFFFFFFFFFFFEFFFF)) - \up_rdata_ff[31]_i_1 - (.I0(up_raddr_s[9]), - .I1(up_raddr_s[13]), - .I2(up_raddr_s[7]), - .I3(up_raddr_s[10]), - .I4(\up_rdata_ff[31]_i_3_n_0 ), - .I5(up_raddr_s[8]), - .O(\up_raddr_int_reg[9]_0 )); - (* SOFT_HLUTNM = "soft_lutpair46" *) - LUT2 #( - .INIT(4'h8)) - \up_rdata_ff[31]_i_2 - (.I0(\up_rdata_ff[31]_i_4_n_0 ), - .I1(\up_rdata_ff_reg[31] [31]), - .O(\up_scratch_reg[31] )); - LUT2 #( - .INIT(4'h1)) - \up_rdata_ff[31]_i_3 - (.I0(up_raddr_s[11]), - .I1(up_raddr_s[12]), - .O(\up_rdata_ff[31]_i_3_n_0 )); - LUT6 #( - .INIT(64'h0000000100000000)) - \up_rdata_ff[31]_i_4 - (.I0(\up_rdata_ff[16]_i_2_n_0 ), - .I1(up_raddr_s[6]), - .I2(up_raddr_s[0]), - .I3(up_raddr_s[5]), - .I4(\up_raddr_int_reg[4]_0 [1]), - .I5(up_raddr_s[1]), - .O(\up_rdata_ff[31]_i_4_n_0 )); - LUT6 #( - .INIT(64'hFFFFFFFFFFFF0400)) - \up_rdata_ff[3]_i_1 - (.I0(\up_rdata_ff[3]_i_2_n_0 ), - .I1(up_raddr_s[5]), - .I2(up_raddr_s[3]), - .I3(\up_rdata_ff[3]_i_3_n_0 ), - .I4(\up_rdata_ff[3]_i_4_n_0 ), - .I5(\up_rdata_ff[3]_i_5_n_0 ), - .O(\up_raddr_int_reg[5]_0 )); - (* SOFT_HLUTNM = "soft_lutpair17" *) - LUT2 #( - .INIT(4'hE)) - \up_rdata_ff[3]_i_2 - (.I0(up_raddr_s[0]), - .I1(up_raddr_s[6]), - .O(\up_rdata_ff[3]_i_2_n_0 )); - LUT6 #( - .INIT(64'hFAAEAAAAAAAEAAAA)) - \up_rdata_ff[3]_i_3 - (.I0(\up_rdata_ff[3]_i_6_n_0 ), - .I1(sync_id_pending_reg), - .I2(\up_raddr_int_reg[4]_0 [1]), - .I3(\up_raddr_int_reg[4]_0 [0]), - .I4(up_raddr_s[1]), - .I5(\up_rdata_ff_reg[5] [3]), - .O(\up_rdata_ff[3]_i_3_n_0 )); - LUT6 #( - .INIT(64'h0000040000000000)) - \up_rdata_ff[3]_i_4 - (.I0(up_raddr_s[1]), - .I1(up_raddr_s[5]), - .I2(up_raddr_s[6]), - .I3(up_raddr_s[0]), - .I4(up_raddr_s[3]), - .I5(\up_rdata_ff[3]_i_7_n_0 ), - .O(\up_rdata_ff[3]_i_4_n_0 )); - LUT6 #( - .INIT(64'hFFFFFFFF10000000)) - \up_rdata_ff[3]_i_5 - (.I0(\m_axis_raddr[4]_i_5_n_0 ), - .I1(\up_rdata_ff[3]_i_2_n_0 ), - .I2(up_raddr_s[3]), - .I3(m_axis_data[3]), - .I4(\up_rdata_ff[3]_i_8_n_0 ), - .I5(\up_rdata_ff[3]_i_9_n_0 ), - .O(\up_rdata_ff[3]_i_5_n_0 )); - LUT6 #( - .INIT(64'h00000000D591C480)) - \up_rdata_ff[3]_i_6 - (.I0(\up_raddr_int_reg[4]_0 [0]), - .I1(\up_raddr_int_reg[4]_0 [1]), - .I2(\up_rdata_ff_reg[4] [2]), - .I3(\up_rdata_ff_reg[7]_0 [3]), - .I4(\up_rdata_ff[3]_i_3_0 [3]), - .I5(up_raddr_s[1]), - .O(\up_rdata_ff[3]_i_6_n_0 )); - LUT6 #( - .INIT(64'hFF000000F0F08888)) - \up_rdata_ff[3]_i_7 - (.I0(\up_rdata_ff[3]_i_3_0 [3]), - .I1(sync_id_pending_reg), - .I2(\up_rdata_ff_reg[7] [2]), - .I3(\up_rdata_ff_reg[5]_0 [2]), - .I4(\up_raddr_int_reg[4]_0 [1]), - .I5(\up_raddr_int_reg[4]_0 [0]), - .O(\up_rdata_ff[3]_i_7_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair20" *) - LUT2 #( - .INIT(4'h6)) - \up_rdata_ff[3]_i_8 - (.I0(\up_raddr_int_reg[4]_0 [0]), - .I1(up_raddr_s[1]), - .O(\up_rdata_ff[3]_i_8_n_0 )); - LUT6 #( - .INIT(64'h0100010001000000)) - \up_rdata_ff[3]_i_9 - (.I0(\up_rdata_ff[16]_i_3_n_0 ), - .I1(\up_rdata_ff[16]_i_2_n_0 ), - .I2(up_raddr_s[6]), - .I3(up_raddr_s[1]), - .I4(up_raddr_s[0]), - .I5(\up_rdata_ff_reg[31] [3]), - .O(\up_rdata_ff[3]_i_9_n_0 )); - LUT5 #( - .INIT(32'h00005503)) - \up_rdata_ff[4]_i_1 - (.I0(\up_rdata_ff[4]_i_2_n_0 ), - .I1(\up_rdata_ff[4]_i_3_n_0 ), - .I2(\up_rdata_ff[4]_i_4_n_0 ), - .I3(up_raddr_s[0]), - .I4(up_raddr_s[6]), - .O(\up_raddr_int_reg[0]_0 )); - LUT6 #( - .INIT(64'hFEFEFFFFFEFFFEFF)) - \up_rdata_ff[4]_i_2 - (.I0(up_raddr_s[3]), - .I1(up_raddr_s[1]), - .I2(\m_axis_raddr[4]_i_5_n_0 ), - .I3(\up_rdata_ff_reg[7] [3]), - .I4(\up_rdata_ff_reg[5]_0 [3]), - .I5(\up_raddr_int_reg[4]_0 [0]), - .O(\up_rdata_ff[4]_i_2_n_0 )); - LUT6 #( - .INIT(64'h7575BABA757FBABA)) - \up_rdata_ff[4]_i_3 - (.I0(up_raddr_s[5]), - .I1(m_axis_data[4]), - .I2(up_raddr_s[3]), - .I3(\up_raddr_int_reg[4]_0 [0]), - .I4(\up_raddr_int_reg[4]_0 [1]), - .I5(\up_rdata_ff_reg[7]_0 [4]), - .O(\up_rdata_ff[4]_i_3_n_0 )); - LUT6 #( - .INIT(64'h55555500F5F7FFF0)) - \up_rdata_ff[4]_i_4 - (.I0(\up_raddr_int_reg[4]_0 [1]), - .I1(\up_rdata_ff_reg[4] [3]), - .I2(up_raddr_s[1]), - .I3(up_raddr_s[3]), - .I4(\up_raddr_int_reg[4]_0 [0]), - .I5(\up_rdata_ff[4]_i_5_n_0 ), - .O(\up_rdata_ff[4]_i_4_n_0 )); - LUT6 #( - .INIT(64'h2FF222222F222222)) - \up_rdata_ff[4]_i_5 - (.I0(\up_rdata_ff_reg[31] [4]), - .I1(\up_raddr_int_reg[4]_0 [1]), - .I2(\up_raddr_int_reg[4]_0 [0]), - .I3(up_raddr_s[3]), - .I4(up_raddr_s[1]), - .I5(\up_rdata_ff_reg[5] [4]), - .O(\up_rdata_ff[4]_i_5_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair17" *) - LUT5 #( - .INIT(32'h00005503)) - \up_rdata_ff[5]_i_1 - (.I0(\up_rdata_ff[5]_i_2_n_0 ), - .I1(\up_rdata_ff[5]_i_3_n_0 ), - .I2(\up_rdata_ff[5]_i_4_n_0 ), - .I3(up_raddr_s[0]), - .I4(up_raddr_s[6]), - .O(\up_raddr_int_reg[0]_1 )); - LUT6 #( - .INIT(64'hFEFEFFFFFEFFFEFF)) - \up_rdata_ff[5]_i_2 - (.I0(up_raddr_s[3]), - .I1(up_raddr_s[1]), - .I2(\m_axis_raddr[4]_i_5_n_0 ), - .I3(\up_rdata_ff_reg[7] [4]), - .I4(\up_rdata_ff_reg[5]_0 [4]), - .I5(\up_raddr_int_reg[4]_0 [0]), - .O(\up_rdata_ff[5]_i_2_n_0 )); - LUT6 #( - .INIT(64'h00DF00FF00DF0000)) - \up_rdata_ff[5]_i_3 - (.I0(up_raddr_s[1]), - .I1(\m_axis_raddr[4]_i_5_n_0 ), - .I2(\up_rdata_ff_reg[5] [5]), - .I3(up_raddr_s[3]), - .I4(\up_raddr_int_reg[4]_0 [0]), - .I5(\up_rdata_ff[5]_i_5_n_0 ), - .O(\up_rdata_ff[5]_i_3_n_0 )); - LUT6 #( - .INIT(64'h9FFFFFFF00000000)) - \up_rdata_ff[5]_i_4 - (.I0(\up_raddr_int_reg[4]_0 [0]), - .I1(up_raddr_s[1]), - .I2(up_raddr_s[5]), - .I3(\up_raddr_int_reg[4]_0 [1]), - .I4(m_axis_data[5]), - .I5(up_raddr_s[3]), - .O(\up_rdata_ff[5]_i_4_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair23" *) - LUT5 #( - .INIT(32'hFD3CFDFC)) - \up_rdata_ff[5]_i_5 - (.I0(\up_rdata_ff_reg[31] [5]), - .I1(\up_raddr_int_reg[4]_0 [1]), - .I2(up_raddr_s[5]), - .I3(up_raddr_s[1]), - .I4(\up_rdata_ff_reg[7]_0 [5]), - .O(\up_rdata_ff[5]_i_5_n_0 )); - LUT6 #( - .INIT(64'hFFFFFFFFFFFF0001)) - \up_rdata_ff[6]_i_1 - (.I0(up_raddr_s[3]), - .I1(up_raddr_s[0]), - .I2(up_raddr_s[6]), - .I3(\up_rdata_ff[6]_i_2_n_0 ), - .I4(\up_rdata_ff[6]_i_3_n_0 ), - .I5(\up_rdata_ff[6]_i_4_n_0 ), - .O(\up_raddr_int_reg[3]_0 )); - LUT6 #( - .INIT(64'hFFFFCFFFFDFDFCFC)) - \up_rdata_ff[6]_i_2 - (.I0(\up_rdata_ff_reg[31] [6]), - .I1(\up_raddr_int_reg[4]_0 [0]), - .I2(up_raddr_s[5]), - .I3(\up_rdata_ff_reg[7]_0 [6]), - .I4(up_raddr_s[1]), - .I5(\up_raddr_int_reg[4]_0 [1]), - .O(\up_rdata_ff[6]_i_2_n_0 )); - LUT6 #( - .INIT(64'h0000000000040000)) - \up_rdata_ff[6]_i_3 - (.I0(\m_axis_raddr[4]_i_5_n_0 ), - .I1(up_raddr_s[0]), - .I2(up_raddr_s[6]), - .I3(\up_rdata_ff[16]_i_2_n_0 ), - .I4(\up_rdata_ff_reg[7] [5]), - .I5(up_raddr_s[1]), - .O(\up_rdata_ff[6]_i_3_n_0 )); - LUT6 #( - .INIT(64'h0000004000400000)) - \up_rdata_ff[6]_i_4 - (.I0(\up_rdata_ff[3]_i_2_n_0 ), - .I1(m_axis_data[6]), - .I2(up_raddr_s[3]), - .I3(\m_axis_raddr[4]_i_5_n_0 ), - .I4(up_raddr_s[1]), - .I5(\up_raddr_int_reg[4]_0 [0]), - .O(\up_rdata_ff[6]_i_4_n_0 )); - LUT6 #( - .INIT(64'h2390000000000000)) - \up_rdata_ff[7]_i_1 - (.I0(up_raddr_s[3]), - .I1(\up_raddr_int_reg[4]_0 [0]), - .I2(\up_raddr_int_reg[4]_0 [1]), - .I3(up_raddr_s[1]), - .I4(\up_rdata_ff[7]_i_2_n_0 ), - .I5(\up_rdata_ff[7]_i_3_n_0 ), - .O(\up_raddr_int_reg[3]_4 )); - LUT6 #( - .INIT(64'h0A0A000A00040004)) - \up_rdata_ff[7]_i_2 - (.I0(up_raddr_s[5]), - .I1(\up_rdata_ff_reg[31] [7]), - .I2(up_raddr_s[6]), - .I3(up_raddr_s[3]), - .I4(m_axis_data[7]), - .I5(\up_raddr_int_reg[4]_0 [1]), - .O(\up_rdata_ff[7]_i_2_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair26" *) - LUT5 #( - .INIT(32'h333B3338)) - \up_rdata_ff[7]_i_3 - (.I0(\up_rdata_ff_reg[7] [6]), - .I1(up_raddr_s[0]), - .I2(\up_raddr_int_reg[4]_0 [0]), - .I3(up_raddr_s[1]), - .I4(\up_rdata_ff_reg[7]_0 [7]), - .O(\up_rdata_ff[7]_i_3_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair46" *) - LUT2 #( - .INIT(4'h8)) - \up_rdata_ff[8]_i_1 - (.I0(\up_rdata_ff[31]_i_4_n_0 ), - .I1(\up_rdata_ff_reg[31] [8]), - .O(\up_scratch_reg[8] )); - (* SOFT_HLUTNM = "soft_lutpair47" *) - LUT2 #( - .INIT(4'h8)) - \up_rdata_ff[9]_i_1 - (.I0(\up_rdata_ff[31]_i_4_n_0 ), - .I1(\up_rdata_ff_reg[31] [9]), - .O(\up_scratch_reg[9] )); - LUT3 #( - .INIT(8'h08)) - up_rreq_int_i_1 - (.I0(s_axi_arvalid), - .I1(s_axi_aresetn), - .I2(up_rsel_reg_n_0), - .O(up_rreq_int_i_1_n_0)); - FDRE #( - .INIT(1'b0)) - up_rreq_int_reg - (.C(s_axi_aclk), - .CE(1'b1), - .D(up_rreq_int_i_1_n_0), - .Q(up_rreq_s), - .R(1'b0)); - LUT4 #( - .INIT(16'h3FAA)) - up_rsel_i_1 - (.I0(s_axi_arvalid), - .I1(up_axi_rvalid_int_reg_0), - .I2(s_axi_rready), - .I3(up_rsel_reg_n_0), - .O(up_rsel_i_1_n_0)); - FDRE #( - .INIT(1'b0)) - up_rsel_reg - (.C(s_axi_aclk), - .CE(1'b1), - .D(up_rsel_i_1_n_0), - .Q(up_rsel_reg_n_0), - .R(s_axi_aresetn_0)); - LUT6 #( - .INIT(64'h0000000001000000)) - \up_scratch[31]_i_1 - (.I0(up_waddr_s[2]), - .I1(up_waddr_s[3]), - .I2(up_waddr_s[4]), - .I3(offload0_enable_reg_i_4_n_0), - .I4(up_waddr_s[1]), - .I5(\up_scratch[31]_i_2_n_0 ), - .O(\up_waddr_int_reg[2]_0 )); - LUT6 #( - .INIT(64'hFFFFFFFFFFFFFFFE)) - \up_scratch[31]_i_2 - (.I0(up_waddr_s[5]), - .I1(\s_axis_waddr[3]_i_4_n_0 ), - .I2(up_waddr_s[7]), - .I3(up_waddr_s[6]), - .I4(up_waddr_s[8]), - .I5(\up_scratch[31]_i_3_n_0 ), - .O(\up_scratch[31]_i_2_n_0 )); - LUT2 #( - .INIT(4'hE)) - \up_scratch[31]_i_3 - (.I0(up_waddr_s[10]), - .I1(up_waddr_s[9]), - .O(\up_scratch[31]_i_3_n_0 )); - LUT4 #( - .INIT(16'hFB08)) - up_sw_reset_i_1 - (.I0(\up_wdata_int_reg[31]_0 [0]), - .I1(up_sw_reset_i_2_n_0), - .I2(\up_scratch[31]_i_2_n_0 ), - .I3(up_sw_reset), - .O(\up_wdata_int_reg[0]_0 )); - LUT6 #( - .INIT(64'h0000000200000000)) - up_sw_reset_i_2 - (.I0(up_waddr_s[4]), - .I1(up_waddr_s[3]), - .I2(up_waddr_s[1]), - .I3(up_waddr_s[2]), - .I4(Q), - .I5(up_wreq_s), - .O(up_sw_reset_i_2_n_0)); - LUT6 #( - .INIT(64'hEAAAAAAA00000000)) - up_wack_d_i_1 - (.I0(up_wack_ff), - .I1(\up_wcount_reg_n_0_[1] ), - .I2(\up_wcount_reg_n_0_[0] ), - .I3(\up_wcount_reg_n_0_[3] ), - .I4(\up_wcount_reg_n_0_[2] ), - .I5(p_0_in7_in), - .O(up_wack_s)); - FDRE #( - .INIT(1'b0)) - up_wack_d_reg - (.C(s_axi_aclk), - .CE(1'b1), - .D(up_wack_s), - .Q(up_wack_d), - .R(s_axi_aresetn_0)); - FDRE #( - .INIT(1'b0)) - \up_waddr_int_reg[0] - (.C(s_axi_aclk), - .CE(p_5_in), - .D(s_axi_awaddr[0]), - .Q(Q), - .R(s_axi_aresetn_0)); - FDRE #( - .INIT(1'b0)) - \up_waddr_int_reg[10] - (.C(s_axi_aclk), - .CE(p_5_in), - .D(s_axi_awaddr[10]), - .Q(up_waddr_s[10]), - .R(s_axi_aresetn_0)); - FDRE #( - .INIT(1'b0)) - \up_waddr_int_reg[11] - (.C(s_axi_aclk), - .CE(p_5_in), - .D(s_axi_awaddr[11]), - .Q(up_waddr_s[11]), - .R(s_axi_aresetn_0)); - FDRE #( - .INIT(1'b0)) - \up_waddr_int_reg[12] - (.C(s_axi_aclk), - .CE(p_5_in), - .D(s_axi_awaddr[12]), - .Q(up_waddr_s[12]), - .R(s_axi_aresetn_0)); - FDRE #( - .INIT(1'b0)) - \up_waddr_int_reg[13] - (.C(s_axi_aclk), - .CE(p_5_in), - .D(s_axi_awaddr[13]), - .Q(up_waddr_s[13]), - .R(s_axi_aresetn_0)); - FDRE #( - .INIT(1'b0)) - \up_waddr_int_reg[1] - (.C(s_axi_aclk), - .CE(p_5_in), - .D(s_axi_awaddr[1]), - .Q(up_waddr_s[1]), - .R(s_axi_aresetn_0)); - FDRE #( - .INIT(1'b0)) - \up_waddr_int_reg[2] - (.C(s_axi_aclk), - .CE(p_5_in), - .D(s_axi_awaddr[2]), - .Q(up_waddr_s[2]), - .R(s_axi_aresetn_0)); - FDRE #( - .INIT(1'b0)) - \up_waddr_int_reg[3] - (.C(s_axi_aclk), - .CE(p_5_in), - .D(s_axi_awaddr[3]), - .Q(up_waddr_s[3]), - .R(s_axi_aresetn_0)); - FDRE #( - .INIT(1'b0)) - \up_waddr_int_reg[4] - (.C(s_axi_aclk), - .CE(p_5_in), - .D(s_axi_awaddr[4]), - .Q(up_waddr_s[4]), - .R(s_axi_aresetn_0)); - FDRE #( - .INIT(1'b0)) - \up_waddr_int_reg[5] - (.C(s_axi_aclk), - .CE(p_5_in), - .D(s_axi_awaddr[5]), - .Q(up_waddr_s[5]), - .R(s_axi_aresetn_0)); - FDRE #( - .INIT(1'b0)) - \up_waddr_int_reg[6] - (.C(s_axi_aclk), - .CE(p_5_in), - .D(s_axi_awaddr[6]), - .Q(up_waddr_s[6]), - .R(s_axi_aresetn_0)); - FDRE #( - .INIT(1'b0)) - \up_waddr_int_reg[7] - (.C(s_axi_aclk), - .CE(p_5_in), - .D(s_axi_awaddr[7]), - .Q(up_waddr_s[7]), - .R(s_axi_aresetn_0)); - FDRE #( - .INIT(1'b0)) - \up_waddr_int_reg[8] - (.C(s_axi_aclk), - .CE(p_5_in), - .D(s_axi_awaddr[8]), - .Q(up_waddr_s[8]), - .R(s_axi_aresetn_0)); - FDRE #( - .INIT(1'b0)) - \up_waddr_int_reg[9] - (.C(s_axi_aclk), - .CE(p_5_in), - .D(s_axi_awaddr[9]), - .Q(up_waddr_s[9]), - .R(s_axi_aresetn_0)); - LUT3 #( - .INIT(8'h04)) - \up_wcount[0]_i_1 - (.I0(up_wack_ff), - .I1(p_0_in7_in), - .I2(\up_wcount_reg_n_0_[0] ), - .O(p_2_in[0])); - (* SOFT_HLUTNM = "soft_lutpair21" *) - LUT4 #( - .INIT(16'h0028)) - \up_wcount[1]_i_1 - (.I0(p_0_in7_in), - .I1(\up_wcount_reg_n_0_[0] ), - .I2(\up_wcount_reg_n_0_[1] ), - .I3(up_wack_ff), - .O(p_2_in[1])); - (* SOFT_HLUTNM = "soft_lutpair21" *) - LUT5 #( - .INIT(32'h00002888)) - \up_wcount[2]_i_1 - (.I0(p_0_in7_in), - .I1(\up_wcount_reg_n_0_[2] ), - .I2(\up_wcount_reg_n_0_[0] ), - .I3(\up_wcount_reg_n_0_[1] ), - .I4(up_wack_ff), - .O(p_2_in[2])); - LUT6 #( - .INIT(64'h0000000028A0A0A0)) - \up_wcount[3]_i_1 - (.I0(p_0_in7_in), - .I1(\up_wcount_reg_n_0_[2] ), - .I2(\up_wcount_reg_n_0_[3] ), - .I3(\up_wcount_reg_n_0_[0] ), - .I4(\up_wcount_reg_n_0_[1] ), - .I5(up_wack_ff), - .O(p_2_in[3])); - LUT3 #( - .INIT(8'hFE)) - \up_wcount[4]_i_1 - (.I0(up_wreq_s), - .I1(p_0_in7_in), - .I2(up_wack_s), - .O(p_1_in__0)); - LUT6 #( - .INIT(64'h5777777777777777)) - \up_wcount[4]_i_2 - (.I0(p_0_in7_in), - .I1(up_wack_ff), - .I2(\up_wcount_reg_n_0_[1] ), - .I3(\up_wcount_reg_n_0_[0] ), - .I4(\up_wcount_reg_n_0_[3] ), - .I5(\up_wcount_reg_n_0_[2] ), - .O(p_2_in[4])); - FDRE #( - .INIT(1'b0)) - \up_wcount_reg[0] - (.C(s_axi_aclk), - .CE(p_1_in__0), - .D(p_2_in[0]), - .Q(\up_wcount_reg_n_0_[0] ), - .R(s_axi_aresetn_0)); - FDRE #( - .INIT(1'b0)) - \up_wcount_reg[1] - (.C(s_axi_aclk), - .CE(p_1_in__0), - .D(p_2_in[1]), - .Q(\up_wcount_reg_n_0_[1] ), - .R(s_axi_aresetn_0)); - FDRE #( - .INIT(1'b0)) - \up_wcount_reg[2] - (.C(s_axi_aclk), - .CE(p_1_in__0), - .D(p_2_in[2]), - .Q(\up_wcount_reg_n_0_[2] ), - .R(s_axi_aresetn_0)); - FDRE #( - .INIT(1'b0)) - \up_wcount_reg[3] - (.C(s_axi_aclk), - .CE(p_1_in__0), - .D(p_2_in[3]), - .Q(\up_wcount_reg_n_0_[3] ), - .R(s_axi_aresetn_0)); - FDRE #( - .INIT(1'b0)) - \up_wcount_reg[4] - (.C(s_axi_aclk), - .CE(p_1_in__0), - .D(p_2_in[4]), - .Q(p_0_in7_in), - .R(s_axi_aresetn_0)); - LUT1 #( - .INIT(2'h1)) - \up_wdata_int[15]_i_1 - (.I0(up_wsel_reg_n_0), - .O(p_5_in)); - FDRE #( - .INIT(1'b0)) - \up_wdata_int_reg[0] - (.C(s_axi_aclk), - .CE(p_5_in), - .D(s_axi_wdata[0]), - .Q(\up_wdata_int_reg[31]_0 [0]), - .R(s_axi_aresetn_0)); - FDRE #( - .INIT(1'b0)) - \up_wdata_int_reg[10] - (.C(s_axi_aclk), - .CE(p_5_in), - .D(s_axi_wdata[10]), - .Q(\up_wdata_int_reg[31]_0 [10]), - .R(s_axi_aresetn_0)); - FDRE #( - .INIT(1'b0)) - \up_wdata_int_reg[11] - (.C(s_axi_aclk), - .CE(p_5_in), - .D(s_axi_wdata[11]), - .Q(\up_wdata_int_reg[31]_0 [11]), - .R(s_axi_aresetn_0)); - FDRE #( - .INIT(1'b0)) - \up_wdata_int_reg[12] - (.C(s_axi_aclk), - .CE(p_5_in), - .D(s_axi_wdata[12]), - .Q(\up_wdata_int_reg[31]_0 [12]), - .R(s_axi_aresetn_0)); - FDRE #( - .INIT(1'b0)) - \up_wdata_int_reg[13] - (.C(s_axi_aclk), - .CE(p_5_in), - .D(s_axi_wdata[13]), - .Q(\up_wdata_int_reg[31]_0 [13]), - .R(s_axi_aresetn_0)); - FDRE #( - .INIT(1'b0)) - \up_wdata_int_reg[14] - (.C(s_axi_aclk), - .CE(p_5_in), - .D(s_axi_wdata[14]), - .Q(\up_wdata_int_reg[31]_0 [14]), - .R(s_axi_aresetn_0)); - FDRE #( - .INIT(1'b0)) - \up_wdata_int_reg[15] - (.C(s_axi_aclk), - .CE(p_5_in), - .D(s_axi_wdata[15]), - .Q(\up_wdata_int_reg[31]_0 [15]), - .R(s_axi_aresetn_0)); - FDRE #( - .INIT(1'b0)) - \up_wdata_int_reg[16] - (.C(s_axi_aclk), - .CE(p_5_in), - .D(s_axi_wdata[16]), - .Q(\up_wdata_int_reg[31]_0 [16]), - .R(s_axi_aresetn_0)); - FDRE #( - .INIT(1'b0)) - \up_wdata_int_reg[17] - (.C(s_axi_aclk), - .CE(p_5_in), - .D(s_axi_wdata[17]), - .Q(\up_wdata_int_reg[31]_0 [17]), - .R(s_axi_aresetn_0)); - FDRE #( - .INIT(1'b0)) - \up_wdata_int_reg[18] - (.C(s_axi_aclk), - .CE(p_5_in), - .D(s_axi_wdata[18]), - .Q(\up_wdata_int_reg[31]_0 [18]), - .R(s_axi_aresetn_0)); - FDRE #( - .INIT(1'b0)) - \up_wdata_int_reg[19] - (.C(s_axi_aclk), - .CE(p_5_in), - .D(s_axi_wdata[19]), - .Q(\up_wdata_int_reg[31]_0 [19]), - .R(s_axi_aresetn_0)); - FDRE #( - .INIT(1'b0)) - \up_wdata_int_reg[1] - (.C(s_axi_aclk), - .CE(p_5_in), - .D(s_axi_wdata[1]), - .Q(\up_wdata_int_reg[31]_0 [1]), - .R(s_axi_aresetn_0)); - FDRE #( - .INIT(1'b0)) - \up_wdata_int_reg[20] - (.C(s_axi_aclk), - .CE(p_5_in), - .D(s_axi_wdata[20]), - .Q(\up_wdata_int_reg[31]_0 [20]), - .R(s_axi_aresetn_0)); - FDRE #( - .INIT(1'b0)) - \up_wdata_int_reg[21] - (.C(s_axi_aclk), - .CE(p_5_in), - .D(s_axi_wdata[21]), - .Q(\up_wdata_int_reg[31]_0 [21]), - .R(s_axi_aresetn_0)); - FDRE #( - .INIT(1'b0)) - \up_wdata_int_reg[22] - (.C(s_axi_aclk), - .CE(p_5_in), - .D(s_axi_wdata[22]), - .Q(\up_wdata_int_reg[31]_0 [22]), - .R(s_axi_aresetn_0)); - FDRE #( - .INIT(1'b0)) - \up_wdata_int_reg[23] - (.C(s_axi_aclk), - .CE(p_5_in), - .D(s_axi_wdata[23]), - .Q(\up_wdata_int_reg[31]_0 [23]), - .R(s_axi_aresetn_0)); - FDRE #( - .INIT(1'b0)) - \up_wdata_int_reg[24] - (.C(s_axi_aclk), - .CE(p_5_in), - .D(s_axi_wdata[24]), - .Q(\up_wdata_int_reg[31]_0 [24]), - .R(s_axi_aresetn_0)); - FDRE #( - .INIT(1'b0)) - \up_wdata_int_reg[25] - (.C(s_axi_aclk), - .CE(p_5_in), - .D(s_axi_wdata[25]), - .Q(\up_wdata_int_reg[31]_0 [25]), - .R(s_axi_aresetn_0)); - FDRE #( - .INIT(1'b0)) - \up_wdata_int_reg[26] - (.C(s_axi_aclk), - .CE(p_5_in), - .D(s_axi_wdata[26]), - .Q(\up_wdata_int_reg[31]_0 [26]), - .R(s_axi_aresetn_0)); - FDRE #( - .INIT(1'b0)) - \up_wdata_int_reg[27] - (.C(s_axi_aclk), - .CE(p_5_in), - .D(s_axi_wdata[27]), - .Q(\up_wdata_int_reg[31]_0 [27]), - .R(s_axi_aresetn_0)); - FDRE #( - .INIT(1'b0)) - \up_wdata_int_reg[28] - (.C(s_axi_aclk), - .CE(p_5_in), - .D(s_axi_wdata[28]), - .Q(\up_wdata_int_reg[31]_0 [28]), - .R(s_axi_aresetn_0)); - FDRE #( - .INIT(1'b0)) - \up_wdata_int_reg[29] - (.C(s_axi_aclk), - .CE(p_5_in), - .D(s_axi_wdata[29]), - .Q(\up_wdata_int_reg[31]_0 [29]), - .R(s_axi_aresetn_0)); - FDRE #( - .INIT(1'b0)) - \up_wdata_int_reg[2] - (.C(s_axi_aclk), - .CE(p_5_in), - .D(s_axi_wdata[2]), - .Q(\up_wdata_int_reg[31]_0 [2]), - .R(s_axi_aresetn_0)); - FDRE #( - .INIT(1'b0)) - \up_wdata_int_reg[30] - (.C(s_axi_aclk), - .CE(p_5_in), - .D(s_axi_wdata[30]), - .Q(\up_wdata_int_reg[31]_0 [30]), - .R(s_axi_aresetn_0)); - FDRE #( - .INIT(1'b0)) - \up_wdata_int_reg[31] - (.C(s_axi_aclk), - .CE(p_5_in), - .D(s_axi_wdata[31]), - .Q(\up_wdata_int_reg[31]_0 [31]), - .R(s_axi_aresetn_0)); - FDRE #( - .INIT(1'b0)) - \up_wdata_int_reg[3] - (.C(s_axi_aclk), - .CE(p_5_in), - .D(s_axi_wdata[3]), - .Q(\up_wdata_int_reg[31]_0 [3]), - .R(s_axi_aresetn_0)); - FDRE #( - .INIT(1'b0)) - \up_wdata_int_reg[4] - (.C(s_axi_aclk), - .CE(p_5_in), - .D(s_axi_wdata[4]), - .Q(\up_wdata_int_reg[31]_0 [4]), - .R(s_axi_aresetn_0)); - FDRE #( - .INIT(1'b0)) - \up_wdata_int_reg[5] - (.C(s_axi_aclk), - .CE(p_5_in), - .D(s_axi_wdata[5]), - .Q(\up_wdata_int_reg[31]_0 [5]), - .R(s_axi_aresetn_0)); - FDRE #( - .INIT(1'b0)) - \up_wdata_int_reg[6] - (.C(s_axi_aclk), - .CE(p_5_in), - .D(s_axi_wdata[6]), - .Q(\up_wdata_int_reg[31]_0 [6]), - .R(s_axi_aresetn_0)); - FDRE #( - .INIT(1'b0)) - \up_wdata_int_reg[7] - (.C(s_axi_aclk), - .CE(p_5_in), - .D(s_axi_wdata[7]), - .Q(\up_wdata_int_reg[31]_0 [7]), - .R(s_axi_aresetn_0)); - FDRE #( - .INIT(1'b0)) - \up_wdata_int_reg[8] - (.C(s_axi_aclk), - .CE(p_5_in), - .D(s_axi_wdata[8]), - .Q(\up_wdata_int_reg[31]_0 [8]), - .R(s_axi_aresetn_0)); - FDRE #( - .INIT(1'b0)) - \up_wdata_int_reg[9] - (.C(s_axi_aclk), - .CE(p_5_in), - .D(s_axi_wdata[9]), - .Q(\up_wdata_int_reg[31]_0 [9]), - .R(s_axi_aresetn_0)); - LUT4 #( - .INIT(16'h4000)) - up_wreq_int_i_1 - (.I0(up_wsel_reg_n_0), - .I1(s_axi_aresetn), - .I2(s_axi_wvalid), - .I3(s_axi_awvalid), - .O(up_wreq_int_i_1_n_0)); - FDRE #( - .INIT(1'b0)) - up_wreq_int_reg - (.C(s_axi_aclk), - .CE(1'b1), - .D(up_wreq_int_i_1_n_0), - .Q(up_wreq_s), - .R(1'b0)); - LUT5 #( - .INIT(32'h0FFF8888)) - up_wsel_i_1 - (.I0(s_axi_wvalid), - .I1(s_axi_awvalid), - .I2(s_axi_bvalid), - .I3(s_axi_bready), - .I4(up_wsel_reg_n_0), - .O(up_wsel_i_1_n_0)); - FDRE #( - .INIT(1'b0)) - up_wsel_reg - (.C(s_axi_aclk), - .CE(1'b1), - .D(up_wsel_i_1_n_0), - .Q(up_wsel_reg_n_0), - .R(s_axi_aresetn_0)); -endmodule - -(* ORIG_REF_NAME = "util_axis_fifo" *) -module system_bd_axi_spi_engine_0_0_util_axis_fifo - (s_axis_ready_reg, - m_axis_valid_reg, - \level_reg[0] , - up_irq_source, - \room_reg[4] , - cmd_data, - up_sw_reset, - spi_clk, - p_1_in, - cmd_ready, - \level_reg[0]_0 , - Q, - s_axi_aclk, - s_mem_write, - offload0_cmd_wr_data); - output s_axis_ready_reg; - output m_axis_valid_reg; - output [0:0]\level_reg[0] ; - output [0:0]up_irq_source; - output [3:0]\room_reg[4] ; - output [15:0]cmd_data; - input up_sw_reset; - input spi_clk; - input p_1_in; - input cmd_ready; - input \level_reg[0]_0 ; - input [0:0]Q; - input s_axi_aclk; - input s_mem_write; - input [15:0]offload0_cmd_wr_data; - - wire [0:0]Q; - wire [15:0]cmd_data; - wire cmd_ready; - wire [0:0]\level_reg[0] ; - wire \level_reg[0]_0 ; - wire [3:0]m_axis_raddr; - wire m_axis_valid_reg; - wire [15:0]offload0_cmd_wr_data; - wire p_1_in; - wire [3:0]\room_reg[4] ; - wire s_axi_aclk; - wire s_axis_ready_reg; - wire [3:0]s_axis_waddr; - wire s_mem_write; - wire spi_clk; - wire [0:0]up_irq_source; - wire up_sw_reset; - wire [1:0]NLW_ram_reg_0_15_0_5_DOD_UNCONNECTED; - wire [1:0]NLW_ram_reg_0_15_12_15_DOC_UNCONNECTED; - wire [1:0]NLW_ram_reg_0_15_12_15_DOD_UNCONNECTED; - wire [1:0]NLW_ram_reg_0_15_6_11_DOD_UNCONNECTED; - - system_bd_axi_spi_engine_0_0_fifo_address_sync i_address_sync - (.Q(Q), - .cmd_ready(cmd_ready), - .\level_reg[0]_0 (\level_reg[0] ), - .\level_reg[0]_1 (\level_reg[0]_0 ), - .\m_axis_raddr_reg[3]_0 (m_axis_raddr), - .m_axis_valid_reg_0(m_axis_valid_reg), - .p_1_in(p_1_in), - .\room_reg[4]_0 (\room_reg[4] ), - .s_axis_ready_reg_0(s_axis_ready_reg), - .\s_axis_waddr_reg[3]_0 (s_axis_waddr), - .spi_clk(spi_clk), - .up_irq_source(up_irq_source), - .up_sw_reset(up_sw_reset)); - (* METHODOLOGY_DRC_VIOS = "" *) - (* RTL_RAM_BITS = "256" *) - (* RTL_RAM_NAME = "i_cmd_fifo/ram" *) - (* ram_addr_begin = "0" *) - (* ram_addr_end = "15" *) - (* ram_offset = "0" *) - (* ram_slice_begin = "0" *) - (* ram_slice_end = "5" *) - RAM32M ram_reg_0_15_0_5 - (.ADDRA({1'b0,m_axis_raddr}), - .ADDRB({1'b0,m_axis_raddr}), - .ADDRC({1'b0,m_axis_raddr}), - .ADDRD({1'b0,s_axis_waddr}), - .DIA(offload0_cmd_wr_data[1:0]), - .DIB(offload0_cmd_wr_data[3:2]), - .DIC(offload0_cmd_wr_data[5:4]), - .DID({1'b0,1'b0}), - .DOA(cmd_data[1:0]), - .DOB(cmd_data[3:2]), - .DOC(cmd_data[5:4]), - .DOD(NLW_ram_reg_0_15_0_5_DOD_UNCONNECTED[1:0]), - .WCLK(s_axi_aclk), - .WE(s_mem_write)); - (* METHODOLOGY_DRC_VIOS = "" *) - (* RTL_RAM_BITS = "256" *) - (* RTL_RAM_NAME = "i_cmd_fifo/ram" *) - (* ram_addr_begin = "0" *) - (* ram_addr_end = "15" *) - (* ram_offset = "0" *) - (* ram_slice_begin = "12" *) - (* ram_slice_end = "15" *) - RAM32M ram_reg_0_15_12_15 - (.ADDRA({1'b0,m_axis_raddr}), - .ADDRB({1'b0,m_axis_raddr}), - .ADDRC({1'b0,m_axis_raddr}), - .ADDRD({1'b0,s_axis_waddr}), - .DIA(offload0_cmd_wr_data[13:12]), - .DIB(offload0_cmd_wr_data[15:14]), - .DIC({1'b0,1'b0}), - .DID({1'b0,1'b0}), - .DOA(cmd_data[13:12]), - .DOB(cmd_data[15:14]), - .DOC(NLW_ram_reg_0_15_12_15_DOC_UNCONNECTED[1:0]), - .DOD(NLW_ram_reg_0_15_12_15_DOD_UNCONNECTED[1:0]), - .WCLK(s_axi_aclk), - .WE(s_mem_write)); - (* METHODOLOGY_DRC_VIOS = "" *) - (* RTL_RAM_BITS = "256" *) - (* RTL_RAM_NAME = "i_cmd_fifo/ram" *) - (* ram_addr_begin = "0" *) - (* ram_addr_end = "15" *) - (* ram_offset = "0" *) - (* ram_slice_begin = "6" *) - (* ram_slice_end = "11" *) - RAM32M ram_reg_0_15_6_11 - (.ADDRA({1'b0,m_axis_raddr}), - .ADDRB({1'b0,m_axis_raddr}), - .ADDRC({1'b0,m_axis_raddr}), - .ADDRD({1'b0,s_axis_waddr}), - .DIA(offload0_cmd_wr_data[7:6]), - .DIB(offload0_cmd_wr_data[9:8]), - .DIC(offload0_cmd_wr_data[11:10]), - .DID({1'b0,1'b0}), - .DOA(cmd_data[7:6]), - .DOB(cmd_data[9:8]), - .DOC(cmd_data[11:10]), - .DOD(NLW_ram_reg_0_15_6_11_DOD_UNCONNECTED[1:0]), - .WCLK(s_axi_aclk), - .WE(s_mem_write)); -endmodule - -(* ORIG_REF_NAME = "util_axis_fifo" *) -module system_bd_axi_spi_engine_0_0_util_axis_fifo__parameterized0 - (s_axis_ready_reg, - m_axis_valid_reg, - Q, - \up_irq_mask_reg[0] , - \level_reg[4] , - m_axis_data, - up_sw_reset, - s_axi_aclk, - DI, - sdi_data_valid, - p_0_in, - irq_reg, - up_irq_source, - irq_reg_0, - m_axis_valid_reg_0, - spi_clk, - sdi_data); - output s_axis_ready_reg; - output m_axis_valid_reg; - output [5:0]Q; - output \up_irq_mask_reg[0] ; - output [0:0]\level_reg[4] ; - output [7:0]m_axis_data; - input up_sw_reset; - input s_axi_aclk; - input [0:0]DI; - input sdi_data_valid; - input p_0_in; - input [3:0]irq_reg; - input [1:0]up_irq_source; - input [0:0]irq_reg_0; - input [0:0]m_axis_valid_reg_0; - input spi_clk; - input [7:0]sdi_data; - - wire [0:0]DI; - wire [5:0]Q; - wire i_address_sync_n_10; - wire i_address_sync_n_11; - wire i_address_sync_n_12; - wire i_address_sync_n_13; - wire i_address_sync_n_14; - wire i_address_sync_n_15; - wire i_address_sync_n_16; - wire i_address_sync_n_17; - wire i_address_sync_n_8; - wire i_address_sync_n_9; - wire [3:0]irq_reg; - wire [0:0]irq_reg_0; - wire [0:0]\level_reg[4] ; - wire [7:0]m_axis_data; - wire m_axis_valid_reg; - wire [0:0]m_axis_valid_reg_0; - wire p_0_in; - wire p_1_in; - wire s_axi_aclk; - wire s_axis_ready_reg; - wire [7:0]sdi_data; - wire sdi_data_valid; - wire spi_clk; - wire \up_irq_mask_reg[0] ; - wire [1:0]up_irq_source; - wire up_sw_reset; - wire [1:0]NLW_ram_reg_0_31_0_5_DOD_UNCONNECTED; - wire [1:0]NLW_ram_reg_0_31_6_7_DOB_UNCONNECTED; - wire [1:0]NLW_ram_reg_0_31_6_7_DOC_UNCONNECTED; - wire [1:0]NLW_ram_reg_0_31_6_7_DOD_UNCONNECTED; - - system_bd_axi_spi_engine_0_0_fifo_address_sync__parameterized0_1 i_address_sync - (.DI(DI), - .Q(Q), - .irq_reg(irq_reg), - .irq_reg_0(irq_reg_0), - .\level_reg[4]_0 (\level_reg[4] ), - .\m_axis_raddr_reg[4]_0 ({i_address_sync_n_13,i_address_sync_n_14,i_address_sync_n_15,i_address_sync_n_16,i_address_sync_n_17}), - .m_axis_valid_reg_0(m_axis_valid_reg), - .m_axis_valid_reg_1(m_axis_valid_reg_0), - .p_0_in(p_0_in), - .s_axi_aclk(s_axi_aclk), - .s_axis_ready_reg_0(s_axis_ready_reg), - .\s_axis_waddr_reg[4]_0 ({i_address_sync_n_8,i_address_sync_n_9,i_address_sync_n_10,i_address_sync_n_11,i_address_sync_n_12}), - .s_mem_write(p_1_in), - .sdi_data_valid(sdi_data_valid), - .\up_irq_mask_reg[0] (\up_irq_mask_reg[0] ), - .up_irq_source(up_irq_source), - .up_sw_reset(up_sw_reset)); - (* METHODOLOGY_DRC_VIOS = "" *) - (* RTL_RAM_BITS = "256" *) - (* RTL_RAM_NAME = "i_sdi_fifo/ram" *) - (* ram_addr_begin = "0" *) - (* ram_addr_end = "31" *) - (* ram_offset = "0" *) - (* ram_slice_begin = "0" *) - (* ram_slice_end = "5" *) - RAM32M ram_reg_0_31_0_5 - (.ADDRA({i_address_sync_n_13,i_address_sync_n_14,i_address_sync_n_15,i_address_sync_n_16,i_address_sync_n_17}), - .ADDRB({i_address_sync_n_13,i_address_sync_n_14,i_address_sync_n_15,i_address_sync_n_16,i_address_sync_n_17}), - .ADDRC({i_address_sync_n_13,i_address_sync_n_14,i_address_sync_n_15,i_address_sync_n_16,i_address_sync_n_17}), - .ADDRD({i_address_sync_n_8,i_address_sync_n_9,i_address_sync_n_10,i_address_sync_n_11,i_address_sync_n_12}), - .DIA(sdi_data[1:0]), - .DIB(sdi_data[3:2]), - .DIC(sdi_data[5:4]), - .DID({1'b0,1'b0}), - .DOA(m_axis_data[1:0]), - .DOB(m_axis_data[3:2]), - .DOC(m_axis_data[5:4]), - .DOD(NLW_ram_reg_0_31_0_5_DOD_UNCONNECTED[1:0]), - .WCLK(spi_clk), - .WE(p_1_in)); - (* METHODOLOGY_DRC_VIOS = "" *) - (* RTL_RAM_BITS = "256" *) - (* RTL_RAM_NAME = "i_sdi_fifo/ram" *) - (* ram_addr_begin = "0" *) - (* ram_addr_end = "31" *) - (* ram_offset = "0" *) - (* ram_slice_begin = "6" *) - (* ram_slice_end = "7" *) - RAM32M ram_reg_0_31_6_7 - (.ADDRA({i_address_sync_n_13,i_address_sync_n_14,i_address_sync_n_15,i_address_sync_n_16,i_address_sync_n_17}), - .ADDRB({i_address_sync_n_13,i_address_sync_n_14,i_address_sync_n_15,i_address_sync_n_16,i_address_sync_n_17}), - .ADDRC({i_address_sync_n_13,i_address_sync_n_14,i_address_sync_n_15,i_address_sync_n_16,i_address_sync_n_17}), - .ADDRD({i_address_sync_n_8,i_address_sync_n_9,i_address_sync_n_10,i_address_sync_n_11,i_address_sync_n_12}), - .DIA(sdi_data[7:6]), - .DIB({1'b0,1'b0}), - .DIC({1'b0,1'b0}), - .DID({1'b0,1'b0}), - .DOA(m_axis_data[7:6]), - .DOB(NLW_ram_reg_0_31_6_7_DOB_UNCONNECTED[1:0]), - .DOC(NLW_ram_reg_0_31_6_7_DOC_UNCONNECTED[1:0]), - .DOD(NLW_ram_reg_0_31_6_7_DOD_UNCONNECTED[1:0]), - .WCLK(spi_clk), - .WE(p_1_in)); -endmodule - -(* ORIG_REF_NAME = "util_axis_fifo" *) -module system_bd_axi_spi_engine_0_0_util_axis_fifo__parameterized0_0 - (s_axis_ready_reg, - m_axis_valid_reg, - \up_irq_mask_reg[1] , - up_irq_source, - \room_reg[5] , - sdo_data, - up_sw_reset, - spi_clk, - sdo_data_ready, - Q, - \up_rdata_ff_reg[1] , - \up_rdata_ff_reg[1]_0 , - \level_reg[0] , - \level_reg[0]_0 , - s_axi_aclk, - s_mem_write, - offload0_cmd_wr_data, - E); - output s_axis_ready_reg; - output m_axis_valid_reg; - output \up_irq_mask_reg[1] ; - output [0:0]up_irq_source; - output [4:0]\room_reg[5] ; - output [7:0]sdo_data; - input up_sw_reset; - input spi_clk; - input sdo_data_ready; - input [0:0]Q; - input [0:0]\up_rdata_ff_reg[1] ; - input [1:0]\up_rdata_ff_reg[1]_0 ; - input [0:0]\level_reg[0] ; - input \level_reg[0]_0 ; - input s_axi_aclk; - input s_mem_write; - input [7:0]offload0_cmd_wr_data; - input [0:0]E; - - wire [0:0]E; - wire [0:0]Q; - wire i_address_sync_n_10; - wire i_address_sync_n_11; - wire i_address_sync_n_2; - wire i_address_sync_n_3; - wire i_address_sync_n_4; - wire i_address_sync_n_5; - wire i_address_sync_n_6; - wire i_address_sync_n_7; - wire i_address_sync_n_8; - wire i_address_sync_n_9; - wire [0:0]\level_reg[0] ; - wire \level_reg[0]_0 ; - wire m_axis_valid_reg; - wire [7:0]offload0_cmd_wr_data; - wire [4:0]\room_reg[5] ; - wire s_axi_aclk; - wire s_axis_ready_reg; - wire s_mem_write; - wire [7:0]sdo_data; - wire sdo_data_ready; - wire spi_clk; - wire \up_irq_mask_reg[1] ; - wire [0:0]up_irq_source; - wire [0:0]\up_rdata_ff_reg[1] ; - wire [1:0]\up_rdata_ff_reg[1]_0 ; - wire up_sw_reset; - wire [1:0]NLW_ram_reg_0_31_0_5_DOD_UNCONNECTED; - wire [1:0]NLW_ram_reg_0_31_6_7_DOB_UNCONNECTED; - wire [1:0]NLW_ram_reg_0_31_6_7_DOC_UNCONNECTED; - wire [1:0]NLW_ram_reg_0_31_6_7_DOD_UNCONNECTED; - - system_bd_axi_spi_engine_0_0_fifo_address_sync__parameterized0 i_address_sync - (.E(E), - .Q({i_address_sync_n_2,i_address_sync_n_3,i_address_sync_n_4,i_address_sync_n_5,i_address_sync_n_6}), - .\level_reg[0]_0 (\level_reg[0] ), - .\level_reg[0]_1 (\level_reg[0]_0 ), - .\m_axis_raddr_reg[4]_0 ({i_address_sync_n_7,i_address_sync_n_8,i_address_sync_n_9,i_address_sync_n_10,i_address_sync_n_11}), - .m_axis_valid_reg_0(m_axis_valid_reg), - .\room_reg[5]_0 (\room_reg[5] ), - .s_axis_ready_reg_0(s_axis_ready_reg), - .sdo_data_ready(sdo_data_ready), - .spi_clk(spi_clk), - .\up_irq_mask_reg[1] (\up_irq_mask_reg[1] ), - .up_irq_source(up_irq_source), - .\up_rdata_ff_reg[1] (Q), - .\up_rdata_ff_reg[1]_0 (\up_rdata_ff_reg[1] ), - .\up_rdata_ff_reg[1]_1 (\up_rdata_ff_reg[1]_0 ), - .up_sw_reset(up_sw_reset)); - (* METHODOLOGY_DRC_VIOS = "" *) - (* RTL_RAM_BITS = "256" *) - (* RTL_RAM_NAME = "i_sdo_fifo/ram" *) - (* ram_addr_begin = "0" *) - (* ram_addr_end = "31" *) - (* ram_offset = "0" *) - (* ram_slice_begin = "0" *) - (* ram_slice_end = "5" *) - RAM32M ram_reg_0_31_0_5 - (.ADDRA({i_address_sync_n_7,i_address_sync_n_8,i_address_sync_n_9,i_address_sync_n_10,i_address_sync_n_11}), - .ADDRB({i_address_sync_n_7,i_address_sync_n_8,i_address_sync_n_9,i_address_sync_n_10,i_address_sync_n_11}), - .ADDRC({i_address_sync_n_7,i_address_sync_n_8,i_address_sync_n_9,i_address_sync_n_10,i_address_sync_n_11}), - .ADDRD({i_address_sync_n_2,i_address_sync_n_3,i_address_sync_n_4,i_address_sync_n_5,i_address_sync_n_6}), - .DIA(offload0_cmd_wr_data[1:0]), - .DIB(offload0_cmd_wr_data[3:2]), - .DIC(offload0_cmd_wr_data[5:4]), - .DID({1'b0,1'b0}), - .DOA(sdo_data[1:0]), - .DOB(sdo_data[3:2]), - .DOC(sdo_data[5:4]), - .DOD(NLW_ram_reg_0_31_0_5_DOD_UNCONNECTED[1:0]), - .WCLK(s_axi_aclk), - .WE(s_mem_write)); - (* METHODOLOGY_DRC_VIOS = "" *) - (* RTL_RAM_BITS = "256" *) - (* RTL_RAM_NAME = "i_sdo_fifo/ram" *) - (* ram_addr_begin = "0" *) - (* ram_addr_end = "31" *) - (* ram_offset = "0" *) - (* ram_slice_begin = "6" *) - (* ram_slice_end = "7" *) - RAM32M ram_reg_0_31_6_7 - (.ADDRA({i_address_sync_n_7,i_address_sync_n_8,i_address_sync_n_9,i_address_sync_n_10,i_address_sync_n_11}), - .ADDRB({i_address_sync_n_7,i_address_sync_n_8,i_address_sync_n_9,i_address_sync_n_10,i_address_sync_n_11}), - .ADDRC({i_address_sync_n_7,i_address_sync_n_8,i_address_sync_n_9,i_address_sync_n_10,i_address_sync_n_11}), - .ADDRD({i_address_sync_n_2,i_address_sync_n_3,i_address_sync_n_4,i_address_sync_n_5,i_address_sync_n_6}), - .DIA(offload0_cmd_wr_data[7:6]), - .DIB({1'b0,1'b0}), - .DIC({1'b0,1'b0}), - .DID({1'b0,1'b0}), - .DOA(sdo_data[7:6]), - .DOB(NLW_ram_reg_0_31_6_7_DOB_UNCONNECTED[1:0]), - .DOC(NLW_ram_reg_0_31_6_7_DOC_UNCONNECTED[1:0]), - .DOD(NLW_ram_reg_0_31_6_7_DOD_UNCONNECTED[1:0]), - .WCLK(s_axi_aclk), - .WE(s_mem_write)); -endmodule -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0_sim_netlist.vhdl b/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0_sim_netlist.vhdl deleted file mode 100644 index f96ae33..0000000 --- a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0_sim_netlist.vhdl +++ /dev/null @@ -1,7953 +0,0 @@ --- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. --- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 --- Date : Sun Sep 29 16:31:49 2024 --- Host : gatsby-dev running 64-bit Red Hat Enterprise Linux release 8.10 (Ootpa) --- Command : write_vhdl -force -mode funcsim --- /home/josh/Workspace/CX9261A/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0_sim_netlist.vhdl --- Design : system_bd_axi_spi_engine_0_0 --- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or --- synthesized. This netlist cannot be used for SDF annotated simulation. --- Device : xc7z045ffg900-2 --- -------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity system_bd_axi_spi_engine_0_0_fifo_address_sync is - port ( - s_axis_ready_reg_0 : out STD_LOGIC; - m_axis_valid_reg_0 : out STD_LOGIC; - \level_reg[0]_0\ : out STD_LOGIC; - \s_axis_waddr_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); - \m_axis_raddr_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); - up_irq_source : out STD_LOGIC_VECTOR ( 0 to 0 ); - \room_reg[4]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); - up_sw_reset : in STD_LOGIC; - spi_clk : in STD_LOGIC; - p_1_in : in STD_LOGIC; - cmd_ready : in STD_LOGIC; - \level_reg[0]_1\ : in STD_LOGIC; - Q : in STD_LOGIC_VECTOR ( 0 to 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of system_bd_axi_spi_engine_0_0_fifo_address_sync : entity is "fifo_address_sync"; -end system_bd_axi_spi_engine_0_0_fifo_address_sync; - -architecture STRUCTURE of system_bd_axi_spi_engine_0_0_fifo_address_sync is - signal level_next : STD_LOGIC_VECTOR ( 0 to 0 ); - signal \level_next__0\ : STD_LOGIC_VECTOR ( 4 downto 1 ); - signal level_reg : STD_LOGIC_VECTOR ( 4 downto 1 ); - signal \^level_reg[0]_0\ : STD_LOGIC; - signal \^m_axis_raddr_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal m_axis_valid_i_1_n_0 : STD_LOGIC; - signal m_axis_valid_i_2_n_0 : STD_LOGIC; - signal m_axis_valid_i_3_n_0 : STD_LOGIC; - signal \^m_axis_valid_reg_0\ : STD_LOGIC; - signal p_0_in : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal p_0_in_0 : STD_LOGIC; - signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal room0 : STD_LOGIC_VECTOR ( 4 downto 1 ); - signal \room[2]_i_1_n_0\ : STD_LOGIC; - signal \^room_reg[4]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal s_axis_ready_i_1_n_0 : STD_LOGIC; - signal \^s_axis_ready_reg_0\ : STD_LOGIC; - signal \^s_axis_waddr_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); - attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of \level[1]_i_1\ : label is "soft_lutpair0"; - attribute SOFT_HLUTNM of \level[3]_i_1\ : label is "soft_lutpair2"; - attribute SOFT_HLUTNM of \level[4]_i_1\ : label is "soft_lutpair2"; - attribute SOFT_HLUTNM of \m_axis_raddr[0]_i_1\ : label is "soft_lutpair6"; - attribute SOFT_HLUTNM of \m_axis_raddr[1]_i_1\ : label is "soft_lutpair6"; - attribute SOFT_HLUTNM of \m_axis_raddr[2]_i_1\ : label is "soft_lutpair4"; - attribute SOFT_HLUTNM of \m_axis_raddr[3]_i_2\ : label is "soft_lutpair4"; - attribute SOFT_HLUTNM of m_axis_valid_i_1 : label is "soft_lutpair1"; - attribute SOFT_HLUTNM of \room[1]_i_1\ : label is "soft_lutpair0"; - attribute SOFT_HLUTNM of s_axis_ready_i_1 : label is "soft_lutpair1"; - attribute SOFT_HLUTNM of \s_axis_waddr[0]_i_1\ : label is "soft_lutpair5"; - attribute SOFT_HLUTNM of \s_axis_waddr[1]_i_1\ : label is "soft_lutpair5"; - attribute SOFT_HLUTNM of \s_axis_waddr[2]_i_1\ : label is "soft_lutpair3"; - attribute SOFT_HLUTNM of \s_axis_waddr[3]_i_2\ : label is "soft_lutpair3"; -begin - \level_reg[0]_0\ <= \^level_reg[0]_0\; - \m_axis_raddr_reg[3]_0\(3 downto 0) <= \^m_axis_raddr_reg[3]_0\(3 downto 0); - m_axis_valid_reg_0 <= \^m_axis_valid_reg_0\; - \room_reg[4]_0\(3 downto 0) <= \^room_reg[4]_0\(3 downto 0); - s_axis_ready_reg_0 <= \^s_axis_ready_reg_0\; - \s_axis_waddr_reg[3]_0\(3 downto 0) <= \^s_axis_waddr_reg[3]_0\(3 downto 0); -irq_i_3: unisim.vcomponents.LUT3 - generic map( - INIT => X"F8" - ) - port map ( - I0 => \^room_reg[4]_0\(2), - I1 => \^room_reg[4]_0\(1), - I2 => \^room_reg[4]_0\(3), - O => up_irq_source(0) - ); -\level[0]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"6A6A6A6A956A6A6A" - ) - port map ( - I0 => \^level_reg[0]_0\, - I1 => \^m_axis_valid_reg_0\, - I2 => cmd_ready, - I3 => \level_reg[0]_1\, - I4 => \^s_axis_ready_reg_0\, - I5 => Q(0), - O => level_next(0) - ); -\level[1]_i_1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"C6669CCC" - ) - port map ( - I0 => \^level_reg[0]_0\, - I1 => level_reg(1), - I2 => \^m_axis_valid_reg_0\, - I3 => cmd_ready, - I4 => p_1_in, - O => \level_next__0\(1) - ); -\level[2]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"F0787878E1F0F0F0" - ) - port map ( - I0 => level_reg(1), - I1 => \^level_reg[0]_0\, - I2 => level_reg(2), - I3 => \^m_axis_valid_reg_0\, - I4 => cmd_ready, - I5 => p_1_in, - O => \level_next__0\(2) - ); -\level[3]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"69" - ) - port map ( - I0 => m_axis_valid_i_3_n_0, - I1 => level_reg(3), - I2 => level_reg(2), - O => \level_next__0\(3) - ); -\level[4]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"78E1" - ) - port map ( - I0 => level_reg(2), - I1 => m_axis_valid_i_3_n_0, - I2 => level_reg(4), - I3 => level_reg(3), - O => \level_next__0\(4) - ); -\level_reg[0]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => spi_clk, - CE => '1', - D => level_next(0), - Q => \^level_reg[0]_0\, - R => up_sw_reset - ); -\level_reg[1]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => spi_clk, - CE => '1', - D => \level_next__0\(1), - Q => level_reg(1), - R => up_sw_reset - ); -\level_reg[2]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => spi_clk, - CE => '1', - D => \level_next__0\(2), - Q => level_reg(2), - R => up_sw_reset - ); -\level_reg[3]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => spi_clk, - CE => '1', - D => \level_next__0\(3), - Q => level_reg(3), - R => up_sw_reset - ); -\level_reg[4]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => spi_clk, - CE => '1', - D => \level_next__0\(4), - Q => level_reg(4), - R => up_sw_reset - ); -\m_axis_raddr[0]_i_1\: unisim.vcomponents.LUT1 - generic map( - INIT => X"1" - ) - port map ( - I0 => \^m_axis_raddr_reg[3]_0\(0), - O => \p_0_in__0\(0) - ); -\m_axis_raddr[1]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => \^m_axis_raddr_reg[3]_0\(0), - I1 => \^m_axis_raddr_reg[3]_0\(1), - O => \p_0_in__0\(1) - ); -\m_axis_raddr[2]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"78" - ) - port map ( - I0 => \^m_axis_raddr_reg[3]_0\(0), - I1 => \^m_axis_raddr_reg[3]_0\(1), - I2 => \^m_axis_raddr_reg[3]_0\(2), - O => \p_0_in__0\(2) - ); -\m_axis_raddr[3]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"8" - ) - port map ( - I0 => cmd_ready, - I1 => \^m_axis_valid_reg_0\, - O => p_0_in_0 - ); -\m_axis_raddr[3]_i_2\: unisim.vcomponents.LUT4 - generic map( - INIT => X"7F80" - ) - port map ( - I0 => \^m_axis_raddr_reg[3]_0\(1), - I1 => \^m_axis_raddr_reg[3]_0\(0), - I2 => \^m_axis_raddr_reg[3]_0\(2), - I3 => \^m_axis_raddr_reg[3]_0\(3), - O => \p_0_in__0\(3) - ); -\m_axis_raddr_reg[0]\: unisim.vcomponents.FDRE - port map ( - C => spi_clk, - CE => p_0_in_0, - D => \p_0_in__0\(0), - Q => \^m_axis_raddr_reg[3]_0\(0), - R => up_sw_reset - ); -\m_axis_raddr_reg[1]\: unisim.vcomponents.FDRE - port map ( - C => spi_clk, - CE => p_0_in_0, - D => \p_0_in__0\(1), - Q => \^m_axis_raddr_reg[3]_0\(1), - R => up_sw_reset - ); -\m_axis_raddr_reg[2]\: unisim.vcomponents.FDRE - port map ( - C => spi_clk, - CE => p_0_in_0, - D => \p_0_in__0\(2), - Q => \^m_axis_raddr_reg[3]_0\(2), - R => up_sw_reset - ); -\m_axis_raddr_reg[3]\: unisim.vcomponents.FDRE - port map ( - C => spi_clk, - CE => p_0_in_0, - D => \p_0_in__0\(3), - Q => \^m_axis_raddr_reg[3]_0\(3), - R => up_sw_reset - ); -m_axis_valid_i_1: unisim.vcomponents.LUT5 - generic map( - INIT => X"BFFEFEFB" - ) - port map ( - I0 => m_axis_valid_i_2_n_0, - I1 => level_reg(3), - I2 => level_reg(4), - I3 => m_axis_valid_i_3_n_0, - I4 => level_reg(2), - O => m_axis_valid_i_1_n_0 - ); -m_axis_valid_i_2: unisim.vcomponents.LUT6 - generic map( - INIT => X"FE7F7F7FFBFEFEFE" - ) - port map ( - I0 => level_reg(2), - I1 => \^level_reg[0]_0\, - I2 => level_reg(1), - I3 => \^m_axis_valid_reg_0\, - I4 => cmd_ready, - I5 => p_1_in, - O => m_axis_valid_i_2_n_0 - ); -m_axis_valid_i_3: unisim.vcomponents.LUT6 - generic map( - INIT => X"7F55555555555515" - ) - port map ( - I0 => level_reg(2), - I1 => \^m_axis_valid_reg_0\, - I2 => cmd_ready, - I3 => p_1_in, - I4 => \^level_reg[0]_0\, - I5 => level_reg(1), - O => m_axis_valid_i_3_n_0 - ); -m_axis_valid_reg: unisim.vcomponents.FDRE - port map ( - C => spi_clk, - CE => '1', - D => m_axis_valid_i_1_n_0, - Q => \^m_axis_valid_reg_0\, - R => up_sw_reset - ); -\room[1]_i_1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"40BFD52A" - ) - port map ( - I0 => p_1_in, - I1 => cmd_ready, - I2 => \^m_axis_valid_reg_0\, - I3 => level_reg(1), - I4 => \^level_reg[0]_0\, - O => room0(1) - ); -\room[2]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"00FF00FF40BFD52A" - ) - port map ( - I0 => p_1_in, - I1 => cmd_ready, - I2 => \^m_axis_valid_reg_0\, - I3 => level_reg(2), - I4 => \^level_reg[0]_0\, - I5 => level_reg(1), - O => \room[2]_i_1_n_0\ - ); -\room[3]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"3333333333636366" - ) - port map ( - I0 => level_reg(2), - I1 => level_reg(3), - I2 => p_0_in_0, - I3 => p_1_in, - I4 => \^level_reg[0]_0\, - I5 => level_reg(1), - O => room0(3) - ); -\room[4]_i_1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"78E1E187" - ) - port map ( - I0 => m_axis_valid_i_2_n_0, - I1 => level_reg(3), - I2 => level_reg(4), - I3 => m_axis_valid_i_3_n_0, - I4 => level_reg(2), - O => room0(4) - ); -\room_reg[1]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => spi_clk, - CE => '1', - D => room0(1), - Q => \^room_reg[4]_0\(0), - R => up_sw_reset - ); -\room_reg[2]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => spi_clk, - CE => '1', - D => \room[2]_i_1_n_0\, - Q => \^room_reg[4]_0\(1), - R => up_sw_reset - ); -\room_reg[3]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => spi_clk, - CE => '1', - D => room0(3), - Q => \^room_reg[4]_0\(2), - R => up_sw_reset - ); -\room_reg[4]\: unisim.vcomponents.FDSE - generic map( - INIT => '1' - ) - port map ( - C => spi_clk, - CE => '1', - D => room0(4), - Q => \^room_reg[4]_0\(3), - S => up_sw_reset - ); -s_axis_ready_i_1: unisim.vcomponents.LUT5 - generic map( - INIT => X"FFFFE79F" - ) - port map ( - I0 => level_reg(2), - I1 => m_axis_valid_i_3_n_0, - I2 => level_reg(4), - I3 => level_reg(3), - I4 => m_axis_valid_i_2_n_0, - O => s_axis_ready_i_1_n_0 - ); -s_axis_ready_reg: unisim.vcomponents.FDRE - port map ( - C => spi_clk, - CE => '1', - D => s_axis_ready_i_1_n_0, - Q => \^s_axis_ready_reg_0\, - R => up_sw_reset - ); -\s_axis_waddr[0]_i_1\: unisim.vcomponents.LUT1 - generic map( - INIT => X"1" - ) - port map ( - I0 => \^s_axis_waddr_reg[3]_0\(0), - O => p_0_in(0) - ); -\s_axis_waddr[1]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => \^s_axis_waddr_reg[3]_0\(0), - I1 => \^s_axis_waddr_reg[3]_0\(1), - O => p_0_in(1) - ); -\s_axis_waddr[2]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"78" - ) - port map ( - I0 => \^s_axis_waddr_reg[3]_0\(0), - I1 => \^s_axis_waddr_reg[3]_0\(1), - I2 => \^s_axis_waddr_reg[3]_0\(2), - O => p_0_in(2) - ); -\s_axis_waddr[3]_i_2\: unisim.vcomponents.LUT4 - generic map( - INIT => X"7F80" - ) - port map ( - I0 => \^s_axis_waddr_reg[3]_0\(1), - I1 => \^s_axis_waddr_reg[3]_0\(0), - I2 => \^s_axis_waddr_reg[3]_0\(2), - I3 => \^s_axis_waddr_reg[3]_0\(3), - O => p_0_in(3) - ); -\s_axis_waddr_reg[0]\: unisim.vcomponents.FDRE - port map ( - C => spi_clk, - CE => p_1_in, - D => p_0_in(0), - Q => \^s_axis_waddr_reg[3]_0\(0), - R => up_sw_reset - ); -\s_axis_waddr_reg[1]\: unisim.vcomponents.FDRE - port map ( - C => spi_clk, - CE => p_1_in, - D => p_0_in(1), - Q => \^s_axis_waddr_reg[3]_0\(1), - R => up_sw_reset - ); -\s_axis_waddr_reg[2]\: unisim.vcomponents.FDRE - port map ( - C => spi_clk, - CE => p_1_in, - D => p_0_in(2), - Q => \^s_axis_waddr_reg[3]_0\(2), - R => up_sw_reset - ); -\s_axis_waddr_reg[3]\: unisim.vcomponents.FDRE - port map ( - C => spi_clk, - CE => p_1_in, - D => p_0_in(3), - Q => \^s_axis_waddr_reg[3]_0\(3), - R => up_sw_reset - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity \system_bd_axi_spi_engine_0_0_fifo_address_sync__parameterized0\ is - port ( - s_axis_ready_reg_0 : out STD_LOGIC; - m_axis_valid_reg_0 : out STD_LOGIC; - Q : out STD_LOGIC_VECTOR ( 4 downto 0 ); - \m_axis_raddr_reg[4]_0\ : out STD_LOGIC_VECTOR ( 4 downto 0 ); - \up_irq_mask_reg[1]\ : out STD_LOGIC; - up_irq_source : out STD_LOGIC_VECTOR ( 0 to 0 ); - \room_reg[5]_0\ : out STD_LOGIC_VECTOR ( 4 downto 0 ); - up_sw_reset : in STD_LOGIC; - spi_clk : in STD_LOGIC; - sdo_data_ready : in STD_LOGIC; - \up_rdata_ff_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); - \up_rdata_ff_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); - \up_rdata_ff_reg[1]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); - \level_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); - \level_reg[0]_1\ : in STD_LOGIC; - E : in STD_LOGIC_VECTOR ( 0 to 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of \system_bd_axi_spi_engine_0_0_fifo_address_sync__parameterized0\ : entity is "fifo_address_sync"; -end \system_bd_axi_spi_engine_0_0_fifo_address_sync__parameterized0\; - -architecture STRUCTURE of \system_bd_axi_spi_engine_0_0_fifo_address_sync__parameterized0\ is - signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 ); - signal level_next : STD_LOGIC_VECTOR ( 5 downto 0 ); - signal \level_next0_carry__0_i_1_n_0\ : STD_LOGIC; - signal \level_next0_carry__0_i_2_n_0\ : STD_LOGIC; - signal \level_next0_carry__0_n_3\ : STD_LOGIC; - signal \level_next0_carry_i_1__0_n_0\ : STD_LOGIC; - signal \level_next0_carry_i_2__0_n_0\ : STD_LOGIC; - signal level_next0_carry_i_3_n_0 : STD_LOGIC; - signal \level_next0_carry_i_4__0_n_0\ : STD_LOGIC; - signal \level_next0_carry_i_5__0_n_0\ : STD_LOGIC; - signal \level_next0_carry_i_6__0_n_0\ : STD_LOGIC; - signal level_next0_carry_n_0 : STD_LOGIC; - signal level_next0_carry_n_1 : STD_LOGIC; - signal level_next0_carry_n_2 : STD_LOGIC; - signal level_next0_carry_n_3 : STD_LOGIC; - signal level_next0_carry_n_7 : STD_LOGIC; - signal level_next1 : STD_LOGIC; - signal level_reg : STD_LOGIC_VECTOR ( 5 downto 0 ); - signal \^m_axis_raddr_reg[4]_0\ : STD_LOGIC_VECTOR ( 4 downto 0 ); - signal m_axis_valid_i_10_n_0 : STD_LOGIC; - signal m_axis_valid_i_11_n_0 : STD_LOGIC; - signal \m_axis_valid_i_1__0_n_0\ : STD_LOGIC; - signal m_axis_valid_i_4_n_0 : STD_LOGIC; - signal m_axis_valid_i_5_n_0 : STD_LOGIC; - signal m_axis_valid_i_6_n_0 : STD_LOGIC; - signal m_axis_valid_i_8_n_0 : STD_LOGIC; - signal m_axis_valid_i_9_n_0 : STD_LOGIC; - signal \^m_axis_valid_reg_0\ : STD_LOGIC; - signal m_axis_valid_reg_i_2_n_3 : STD_LOGIC; - signal m_axis_valid_reg_i_2_n_6 : STD_LOGIC; - signal m_axis_valid_reg_i_2_n_7 : STD_LOGIC; - signal m_axis_valid_reg_i_3_n_0 : STD_LOGIC; - signal m_axis_valid_reg_i_3_n_1 : STD_LOGIC; - signal m_axis_valid_reg_i_3_n_2 : STD_LOGIC; - signal m_axis_valid_reg_i_3_n_3 : STD_LOGIC; - signal m_axis_valid_reg_i_3_n_4 : STD_LOGIC; - signal m_axis_valid_reg_i_3_n_5 : STD_LOGIC; - signal m_axis_valid_reg_i_3_n_6 : STD_LOGIC; - signal p_0_in : STD_LOGIC_VECTOR ( 4 downto 0 ); - signal p_0_in_0 : STD_LOGIC; - signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 4 downto 0 ); - signal \room[1]_i_1__0_n_0\ : STD_LOGIC; - signal \room[2]_i_1__0_n_0\ : STD_LOGIC; - signal \room[3]_i_1__0_n_0\ : STD_LOGIC; - signal \room[4]_i_1__0_n_0\ : STD_LOGIC; - signal \room[5]_i_1_n_0\ : STD_LOGIC; - signal \^room_reg[5]_0\ : STD_LOGIC_VECTOR ( 4 downto 0 ); - signal \s_axis_ready_i_1__0_n_0\ : STD_LOGIC; - signal \^s_axis_ready_reg_0\ : STD_LOGIC; - signal sdo_fifo_room : STD_LOGIC_VECTOR ( 1 to 1 ); - signal \^up_irq_source\ : STD_LOGIC_VECTOR ( 0 to 0 ); - signal \NLW_level_next0_carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); - signal \NLW_level_next0_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); - signal NLW_m_axis_valid_reg_i_2_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 1 ); - signal NLW_m_axis_valid_reg_i_2_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 ); - signal NLW_m_axis_valid_reg_i_3_O_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of \m_axis_raddr[1]_i_1__0\ : label is "soft_lutpair16"; - attribute SOFT_HLUTNM of \m_axis_raddr[2]_i_1__0\ : label is "soft_lutpair16"; - attribute SOFT_HLUTNM of \m_axis_raddr[3]_i_1__0\ : label is "soft_lutpair12"; - attribute SOFT_HLUTNM of \m_axis_raddr[4]_i_2\ : label is "soft_lutpair12"; - attribute SOFT_HLUTNM of \room[1]_i_1__0\ : label is "soft_lutpair15"; - attribute SOFT_HLUTNM of \room[2]_i_1__0\ : label is "soft_lutpair15"; - attribute SOFT_HLUTNM of \room[3]_i_1__0\ : label is "soft_lutpair13"; - attribute SOFT_HLUTNM of \room[4]_i_1__0\ : label is "soft_lutpair13"; - attribute SOFT_HLUTNM of \s_axis_waddr[1]_i_1__0\ : label is "soft_lutpair14"; - attribute SOFT_HLUTNM of \s_axis_waddr[2]_i_1__0\ : label is "soft_lutpair14"; - attribute SOFT_HLUTNM of \s_axis_waddr[3]_i_1__0\ : label is "soft_lutpair11"; - attribute SOFT_HLUTNM of \s_axis_waddr[4]_i_2\ : label is "soft_lutpair11"; -begin - Q(4 downto 0) <= \^q\(4 downto 0); - \m_axis_raddr_reg[4]_0\(4 downto 0) <= \^m_axis_raddr_reg[4]_0\(4 downto 0); - m_axis_valid_reg_0 <= \^m_axis_valid_reg_0\; - \room_reg[5]_0\(4 downto 0) <= \^room_reg[5]_0\(4 downto 0); - s_axis_ready_reg_0 <= \^s_axis_ready_reg_0\; - up_irq_source(0) <= \^up_irq_source\(0); -irq_i_4: unisim.vcomponents.LUT3 - generic map( - INIT => X"F8" - ) - port map ( - I0 => \^room_reg[5]_0\(3), - I1 => \^room_reg[5]_0\(2), - I2 => \^room_reg[5]_0\(4), - O => \^up_irq_source\(0) - ); -\level[0]_i_1__1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"807F7F807F807F80" - ) - port map ( - I0 => \^s_axis_ready_reg_0\, - I1 => \level_reg[0]_0\(0), - I2 => \level_reg[0]_1\, - I3 => level_reg(0), - I4 => \^m_axis_valid_reg_0\, - I5 => sdo_data_ready, - O => level_next(0) - ); -level_next0_carry: unisim.vcomponents.CARRY4 - port map ( - CI => '0', - CO(3) => level_next0_carry_n_0, - CO(2) => level_next0_carry_n_1, - CO(1) => level_next0_carry_n_2, - CO(0) => level_next0_carry_n_3, - CYINIT => '0', - DI(3) => level_reg(2), - DI(2) => \level_next0_carry_i_1__0_n_0\, - DI(1) => \level_next0_carry_i_2__0_n_0\, - DI(0) => level_reg(0), - O(3 downto 1) => level_next(3 downto 1), - O(0) => level_next0_carry_n_7, - S(3) => level_next0_carry_i_3_n_0, - S(2) => \level_next0_carry_i_4__0_n_0\, - S(1) => \level_next0_carry_i_5__0_n_0\, - S(0) => \level_next0_carry_i_6__0_n_0\ - ); -\level_next0_carry__0\: unisim.vcomponents.CARRY4 - port map ( - CI => level_next0_carry_n_0, - CO(3 downto 1) => \NLW_level_next0_carry__0_CO_UNCONNECTED\(3 downto 1), - CO(0) => \level_next0_carry__0_n_3\, - CYINIT => '0', - DI(3 downto 1) => B"000", - DI(0) => level_reg(3), - O(3 downto 2) => \NLW_level_next0_carry__0_O_UNCONNECTED\(3 downto 2), - O(1 downto 0) => level_next(5 downto 4), - S(3 downto 2) => B"00", - S(1) => \level_next0_carry__0_i_1_n_0\, - S(0) => \level_next0_carry__0_i_2_n_0\ - ); -\level_next0_carry__0_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"9" - ) - port map ( - I0 => level_reg(4), - I1 => level_reg(5), - O => \level_next0_carry__0_i_1_n_0\ - ); -\level_next0_carry__0_i_2\: unisim.vcomponents.LUT2 - generic map( - INIT => X"9" - ) - port map ( - I0 => level_reg(3), - I1 => level_reg(4), - O => \level_next0_carry__0_i_2_n_0\ - ); -\level_next0_carry_i_1__0\: unisim.vcomponents.LUT5 - generic map( - INIT => X"80FFFFFF" - ) - port map ( - I0 => \^s_axis_ready_reg_0\, - I1 => \level_reg[0]_0\(0), - I2 => \level_reg[0]_1\, - I3 => sdo_data_ready, - I4 => \^m_axis_valid_reg_0\, - O => \level_next0_carry_i_1__0_n_0\ - ); -\level_next0_carry_i_2__0\: unisim.vcomponents.LUT5 - generic map( - INIT => X"7F000000" - ) - port map ( - I0 => \^s_axis_ready_reg_0\, - I1 => \level_reg[0]_0\(0), - I2 => \level_reg[0]_1\, - I3 => \^m_axis_valid_reg_0\, - I4 => sdo_data_ready, - O => \level_next0_carry_i_2__0_n_0\ - ); -level_next0_carry_i_3: unisim.vcomponents.LUT2 - generic map( - INIT => X"9" - ) - port map ( - I0 => level_reg(2), - I1 => level_reg(3), - O => level_next0_carry_i_3_n_0 - ); -\level_next0_carry_i_4__0\: unisim.vcomponents.LUT6 - generic map( - INIT => X"80FFFFFF7F000000" - ) - port map ( - I0 => \^s_axis_ready_reg_0\, - I1 => \level_reg[0]_0\(0), - I2 => \level_reg[0]_1\, - I3 => sdo_data_ready, - I4 => \^m_axis_valid_reg_0\, - I5 => level_reg(2), - O => \level_next0_carry_i_4__0_n_0\ - ); -\level_next0_carry_i_5__0\: unisim.vcomponents.LUT6 - generic map( - INIT => X"80FFFFFF7F000000" - ) - port map ( - I0 => \^s_axis_ready_reg_0\, - I1 => \level_reg[0]_0\(0), - I2 => \level_reg[0]_1\, - I3 => sdo_data_ready, - I4 => \^m_axis_valid_reg_0\, - I5 => level_reg(1), - O => \level_next0_carry_i_5__0_n_0\ - ); -\level_next0_carry_i_6__0\: unisim.vcomponents.LUT6 - generic map( - INIT => X"807F7F807F807F80" - ) - port map ( - I0 => \^s_axis_ready_reg_0\, - I1 => \level_reg[0]_0\(0), - I2 => \level_reg[0]_1\, - I3 => level_reg(0), - I4 => \^m_axis_valid_reg_0\, - I5 => sdo_data_ready, - O => \level_next0_carry_i_6__0_n_0\ - ); -\level_reg[0]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => spi_clk, - CE => '1', - D => level_next(0), - Q => level_reg(0), - R => up_sw_reset - ); -\level_reg[1]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => spi_clk, - CE => '1', - D => level_next(1), - Q => level_reg(1), - R => up_sw_reset - ); -\level_reg[2]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => spi_clk, - CE => '1', - D => level_next(2), - Q => level_reg(2), - R => up_sw_reset - ); -\level_reg[3]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => spi_clk, - CE => '1', - D => level_next(3), - Q => level_reg(3), - R => up_sw_reset - ); -\level_reg[4]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => spi_clk, - CE => '1', - D => level_next(4), - Q => level_reg(4), - R => up_sw_reset - ); -\level_reg[5]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => spi_clk, - CE => '1', - D => level_next(5), - Q => level_reg(5), - R => up_sw_reset - ); -\m_axis_raddr[0]_i_1__0\: unisim.vcomponents.LUT1 - generic map( - INIT => X"1" - ) - port map ( - I0 => \^m_axis_raddr_reg[4]_0\(0), - O => \p_0_in__0\(0) - ); -\m_axis_raddr[1]_i_1__0\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => \^m_axis_raddr_reg[4]_0\(0), - I1 => \^m_axis_raddr_reg[4]_0\(1), - O => \p_0_in__0\(1) - ); -\m_axis_raddr[2]_i_1__0\: unisim.vcomponents.LUT3 - generic map( - INIT => X"78" - ) - port map ( - I0 => \^m_axis_raddr_reg[4]_0\(0), - I1 => \^m_axis_raddr_reg[4]_0\(1), - I2 => \^m_axis_raddr_reg[4]_0\(2), - O => \p_0_in__0\(2) - ); -\m_axis_raddr[3]_i_1__0\: unisim.vcomponents.LUT4 - generic map( - INIT => X"7F80" - ) - port map ( - I0 => \^m_axis_raddr_reg[4]_0\(1), - I1 => \^m_axis_raddr_reg[4]_0\(0), - I2 => \^m_axis_raddr_reg[4]_0\(2), - I3 => \^m_axis_raddr_reg[4]_0\(3), - O => \p_0_in__0\(3) - ); -\m_axis_raddr[4]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"8" - ) - port map ( - I0 => sdo_data_ready, - I1 => \^m_axis_valid_reg_0\, - O => p_0_in_0 - ); -\m_axis_raddr[4]_i_2\: unisim.vcomponents.LUT5 - generic map( - INIT => X"7FFF8000" - ) - port map ( - I0 => \^m_axis_raddr_reg[4]_0\(2), - I1 => \^m_axis_raddr_reg[4]_0\(0), - I2 => \^m_axis_raddr_reg[4]_0\(1), - I3 => \^m_axis_raddr_reg[4]_0\(3), - I4 => \^m_axis_raddr_reg[4]_0\(4), - O => \p_0_in__0\(4) - ); -\m_axis_raddr_reg[0]\: unisim.vcomponents.FDRE - port map ( - C => spi_clk, - CE => p_0_in_0, - D => \p_0_in__0\(0), - Q => \^m_axis_raddr_reg[4]_0\(0), - R => up_sw_reset - ); -\m_axis_raddr_reg[1]\: unisim.vcomponents.FDRE - port map ( - C => spi_clk, - CE => p_0_in_0, - D => \p_0_in__0\(1), - Q => \^m_axis_raddr_reg[4]_0\(1), - R => up_sw_reset - ); -\m_axis_raddr_reg[2]\: unisim.vcomponents.FDRE - port map ( - C => spi_clk, - CE => p_0_in_0, - D => \p_0_in__0\(2), - Q => \^m_axis_raddr_reg[4]_0\(2), - R => up_sw_reset - ); -\m_axis_raddr_reg[3]\: unisim.vcomponents.FDRE - port map ( - C => spi_clk, - CE => p_0_in_0, - D => \p_0_in__0\(3), - Q => \^m_axis_raddr_reg[4]_0\(3), - R => up_sw_reset - ); -\m_axis_raddr_reg[4]\: unisim.vcomponents.FDRE - port map ( - C => spi_clk, - CE => p_0_in_0, - D => \p_0_in__0\(4), - Q => \^m_axis_raddr_reg[4]_0\(4), - R => up_sw_reset - ); -m_axis_valid_i_10: unisim.vcomponents.LUT6 - generic map( - INIT => X"80FFFFFF7F000000" - ) - port map ( - I0 => \^s_axis_ready_reg_0\, - I1 => \level_reg[0]_0\(0), - I2 => \level_reg[0]_1\, - I3 => sdo_data_ready, - I4 => \^m_axis_valid_reg_0\, - I5 => level_reg(1), - O => m_axis_valid_i_10_n_0 - ); -m_axis_valid_i_11: unisim.vcomponents.LUT6 - generic map( - INIT => X"807F7F807F807F80" - ) - port map ( - I0 => \^s_axis_ready_reg_0\, - I1 => \level_reg[0]_0\(0), - I2 => \level_reg[0]_1\, - I3 => level_reg(0), - I4 => \^m_axis_valid_reg_0\, - I5 => sdo_data_ready, - O => m_axis_valid_i_11_n_0 - ); -\m_axis_valid_i_1__0\: unisim.vcomponents.LUT6 - generic map( - INIT => X"FFFFFFFFFFFFFFFE" - ) - port map ( - I0 => m_axis_valid_reg_i_2_n_7, - I1 => m_axis_valid_reg_i_3_n_4, - I2 => m_axis_valid_reg_i_2_n_6, - I3 => m_axis_valid_reg_i_3_n_6, - I4 => level_next0_carry_n_7, - I5 => m_axis_valid_reg_i_3_n_5, - O => \m_axis_valid_i_1__0_n_0\ - ); -m_axis_valid_i_4: unisim.vcomponents.LUT2 - generic map( - INIT => X"9" - ) - port map ( - I0 => level_reg(4), - I1 => level_reg(5), - O => m_axis_valid_i_4_n_0 - ); -m_axis_valid_i_5: unisim.vcomponents.LUT2 - generic map( - INIT => X"9" - ) - port map ( - I0 => level_reg(3), - I1 => level_reg(4), - O => m_axis_valid_i_5_n_0 - ); -m_axis_valid_i_6: unisim.vcomponents.LUT5 - generic map( - INIT => X"80FFFFFF" - ) - port map ( - I0 => \^s_axis_ready_reg_0\, - I1 => \level_reg[0]_0\(0), - I2 => \level_reg[0]_1\, - I3 => sdo_data_ready, - I4 => \^m_axis_valid_reg_0\, - O => m_axis_valid_i_6_n_0 - ); -m_axis_valid_i_7: unisim.vcomponents.LUT5 - generic map( - INIT => X"7F000000" - ) - port map ( - I0 => \^s_axis_ready_reg_0\, - I1 => \level_reg[0]_0\(0), - I2 => \level_reg[0]_1\, - I3 => \^m_axis_valid_reg_0\, - I4 => sdo_data_ready, - O => level_next1 - ); -m_axis_valid_i_8: unisim.vcomponents.LUT2 - generic map( - INIT => X"9" - ) - port map ( - I0 => level_reg(2), - I1 => level_reg(3), - O => m_axis_valid_i_8_n_0 - ); -m_axis_valid_i_9: unisim.vcomponents.LUT6 - generic map( - INIT => X"80FFFFFF7F000000" - ) - port map ( - I0 => \^s_axis_ready_reg_0\, - I1 => \level_reg[0]_0\(0), - I2 => \level_reg[0]_1\, - I3 => sdo_data_ready, - I4 => \^m_axis_valid_reg_0\, - I5 => level_reg(2), - O => m_axis_valid_i_9_n_0 - ); -m_axis_valid_reg: unisim.vcomponents.FDRE - port map ( - C => spi_clk, - CE => '1', - D => \m_axis_valid_i_1__0_n_0\, - Q => \^m_axis_valid_reg_0\, - R => up_sw_reset - ); -m_axis_valid_reg_i_2: unisim.vcomponents.CARRY4 - port map ( - CI => m_axis_valid_reg_i_3_n_0, - CO(3 downto 1) => NLW_m_axis_valid_reg_i_2_CO_UNCONNECTED(3 downto 1), - CO(0) => m_axis_valid_reg_i_2_n_3, - CYINIT => '0', - DI(3 downto 1) => B"000", - DI(0) => level_reg(3), - O(3 downto 2) => NLW_m_axis_valid_reg_i_2_O_UNCONNECTED(3 downto 2), - O(1) => m_axis_valid_reg_i_2_n_6, - O(0) => m_axis_valid_reg_i_2_n_7, - S(3 downto 2) => B"00", - S(1) => m_axis_valid_i_4_n_0, - S(0) => m_axis_valid_i_5_n_0 - ); -m_axis_valid_reg_i_3: unisim.vcomponents.CARRY4 - port map ( - CI => '0', - CO(3) => m_axis_valid_reg_i_3_n_0, - CO(2) => m_axis_valid_reg_i_3_n_1, - CO(1) => m_axis_valid_reg_i_3_n_2, - CO(0) => m_axis_valid_reg_i_3_n_3, - CYINIT => '0', - DI(3) => level_reg(2), - DI(2) => m_axis_valid_i_6_n_0, - DI(1) => level_next1, - DI(0) => level_reg(0), - O(3) => m_axis_valid_reg_i_3_n_4, - O(2) => m_axis_valid_reg_i_3_n_5, - O(1) => m_axis_valid_reg_i_3_n_6, - O(0) => NLW_m_axis_valid_reg_i_3_O_UNCONNECTED(0), - S(3) => m_axis_valid_i_8_n_0, - S(2) => m_axis_valid_i_9_n_0, - S(1) => m_axis_valid_i_10_n_0, - S(0) => m_axis_valid_i_11_n_0 - ); -\room[1]_i_1__0\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => level_next0_carry_n_7, - I1 => m_axis_valid_reg_i_3_n_6, - O => \room[1]_i_1__0_n_0\ - ); -\room[2]_i_1__0\: unisim.vcomponents.LUT3 - generic map( - INIT => X"1E" - ) - port map ( - I0 => level_next0_carry_n_7, - I1 => m_axis_valid_reg_i_3_n_6, - I2 => m_axis_valid_reg_i_3_n_5, - O => \room[2]_i_1__0_n_0\ - ); -\room[3]_i_1__0\: unisim.vcomponents.LUT4 - generic map( - INIT => X"01FE" - ) - port map ( - I0 => m_axis_valid_reg_i_3_n_5, - I1 => level_next0_carry_n_7, - I2 => m_axis_valid_reg_i_3_n_6, - I3 => m_axis_valid_reg_i_3_n_4, - O => \room[3]_i_1__0_n_0\ - ); -\room[4]_i_1__0\: unisim.vcomponents.LUT5 - generic map( - INIT => X"0001FFFE" - ) - port map ( - I0 => m_axis_valid_reg_i_3_n_4, - I1 => m_axis_valid_reg_i_3_n_6, - I2 => level_next0_carry_n_7, - I3 => m_axis_valid_reg_i_3_n_5, - I4 => m_axis_valid_reg_i_2_n_7, - O => \room[4]_i_1__0_n_0\ - ); -\room[5]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"FFFFFFFE00000001" - ) - port map ( - I0 => m_axis_valid_reg_i_2_n_7, - I1 => m_axis_valid_reg_i_3_n_5, - I2 => level_next0_carry_n_7, - I3 => m_axis_valid_reg_i_3_n_6, - I4 => m_axis_valid_reg_i_3_n_4, - I5 => m_axis_valid_reg_i_2_n_6, - O => \room[5]_i_1_n_0\ - ); -\room_reg[0]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => spi_clk, - CE => '1', - D => level_next0_carry_n_7, - Q => \^room_reg[5]_0\(0), - R => up_sw_reset - ); -\room_reg[1]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => spi_clk, - CE => '1', - D => \room[1]_i_1__0_n_0\, - Q => sdo_fifo_room(1), - R => up_sw_reset - ); -\room_reg[2]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => spi_clk, - CE => '1', - D => \room[2]_i_1__0_n_0\, - Q => \^room_reg[5]_0\(1), - R => up_sw_reset - ); -\room_reg[3]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => spi_clk, - CE => '1', - D => \room[3]_i_1__0_n_0\, - Q => \^room_reg[5]_0\(2), - R => up_sw_reset - ); -\room_reg[4]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => spi_clk, - CE => '1', - D => \room[4]_i_1__0_n_0\, - Q => \^room_reg[5]_0\(3), - R => up_sw_reset - ); -\room_reg[5]\: unisim.vcomponents.FDSE - generic map( - INIT => '1' - ) - port map ( - C => spi_clk, - CE => '1', - D => \room[5]_i_1_n_0\, - Q => \^room_reg[5]_0\(4), - S => up_sw_reset - ); -\s_axis_ready_i_1__0\: unisim.vcomponents.LUT6 - generic map( - INIT => X"FFFFFFFFFFFFFEFF" - ) - port map ( - I0 => m_axis_valid_reg_i_2_n_7, - I1 => m_axis_valid_reg_i_3_n_5, - I2 => m_axis_valid_reg_i_3_n_4, - I3 => m_axis_valid_reg_i_2_n_6, - I4 => m_axis_valid_reg_i_3_n_6, - I5 => level_next0_carry_n_7, - O => \s_axis_ready_i_1__0_n_0\ - ); -s_axis_ready_reg: unisim.vcomponents.FDRE - port map ( - C => spi_clk, - CE => '1', - D => \s_axis_ready_i_1__0_n_0\, - Q => \^s_axis_ready_reg_0\, - R => up_sw_reset - ); -\s_axis_waddr[0]_i_1__0\: unisim.vcomponents.LUT1 - generic map( - INIT => X"1" - ) - port map ( - I0 => \^q\(0), - O => p_0_in(0) - ); -\s_axis_waddr[1]_i_1__0\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => \^q\(0), - I1 => \^q\(1), - O => p_0_in(1) - ); -\s_axis_waddr[2]_i_1__0\: unisim.vcomponents.LUT3 - generic map( - INIT => X"78" - ) - port map ( - I0 => \^q\(0), - I1 => \^q\(1), - I2 => \^q\(2), - O => p_0_in(2) - ); -\s_axis_waddr[3]_i_1__0\: unisim.vcomponents.LUT4 - generic map( - INIT => X"7F80" - ) - port map ( - I0 => \^q\(1), - I1 => \^q\(0), - I2 => \^q\(2), - I3 => \^q\(3), - O => p_0_in(3) - ); -\s_axis_waddr[4]_i_2\: unisim.vcomponents.LUT5 - generic map( - INIT => X"7FFF8000" - ) - port map ( - I0 => \^q\(2), - I1 => \^q\(0), - I2 => \^q\(1), - I3 => \^q\(3), - I4 => \^q\(4), - O => p_0_in(4) - ); -\s_axis_waddr_reg[0]\: unisim.vcomponents.FDRE - port map ( - C => spi_clk, - CE => E(0), - D => p_0_in(0), - Q => \^q\(0), - R => up_sw_reset - ); -\s_axis_waddr_reg[1]\: unisim.vcomponents.FDRE - port map ( - C => spi_clk, - CE => E(0), - D => p_0_in(1), - Q => \^q\(1), - R => up_sw_reset - ); -\s_axis_waddr_reg[2]\: unisim.vcomponents.FDRE - port map ( - C => spi_clk, - CE => E(0), - D => p_0_in(2), - Q => \^q\(2), - R => up_sw_reset - ); -\s_axis_waddr_reg[3]\: unisim.vcomponents.FDRE - port map ( - C => spi_clk, - CE => E(0), - D => p_0_in(3), - Q => \^q\(3), - R => up_sw_reset - ); -\s_axis_waddr_reg[4]\: unisim.vcomponents.FDRE - port map ( - C => spi_clk, - CE => E(0), - D => p_0_in(4), - Q => \^q\(4), - R => up_sw_reset - ); -\up_rdata_ff[1]_i_2\: unisim.vcomponents.LUT6 - generic map( - INIT => X"FF000000F0F08888" - ) - port map ( - I0 => \up_rdata_ff_reg[1]\(0), - I1 => \^up_irq_source\(0), - I2 => \up_rdata_ff_reg[1]_0\(0), - I3 => sdo_fifo_room(1), - I4 => \up_rdata_ff_reg[1]_1\(1), - I5 => \up_rdata_ff_reg[1]_1\(0), - O => \up_irq_mask_reg[1]\ - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity \system_bd_axi_spi_engine_0_0_fifo_address_sync__parameterized0_1\ is - port ( - s_axis_ready_reg_0 : out STD_LOGIC; - m_axis_valid_reg_0 : out STD_LOGIC; - Q : out STD_LOGIC_VECTOR ( 5 downto 0 ); - \s_axis_waddr_reg[4]_0\ : out STD_LOGIC_VECTOR ( 4 downto 0 ); - \m_axis_raddr_reg[4]_0\ : out STD_LOGIC_VECTOR ( 4 downto 0 ); - \up_irq_mask_reg[0]\ : out STD_LOGIC; - \level_reg[4]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); - s_mem_write : out STD_LOGIC; - up_sw_reset : in STD_LOGIC; - s_axi_aclk : in STD_LOGIC; - DI : in STD_LOGIC_VECTOR ( 0 to 0 ); - sdi_data_valid : in STD_LOGIC; - p_0_in : in STD_LOGIC; - irq_reg : in STD_LOGIC_VECTOR ( 3 downto 0 ); - up_irq_source : in STD_LOGIC_VECTOR ( 1 downto 0 ); - irq_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 ); - m_axis_valid_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of \system_bd_axi_spi_engine_0_0_fifo_address_sync__parameterized0_1\ : entity is "fifo_address_sync"; -end \system_bd_axi_spi_engine_0_0_fifo_address_sync__parameterized0_1\; - -architecture STRUCTURE of \system_bd_axi_spi_engine_0_0_fifo_address_sync__parameterized0_1\ is - signal \^q\ : STD_LOGIC_VECTOR ( 5 downto 0 ); - signal irq_i_2_n_0 : STD_LOGIC; - signal level_next : STD_LOGIC_VECTOR ( 5 downto 0 ); - signal \level_next0_carry__0_i_1__0_n_0\ : STD_LOGIC; - signal \level_next0_carry__0_i_2__0_n_0\ : STD_LOGIC; - signal \level_next0_carry__0_n_3\ : STD_LOGIC; - signal level_next0_carry_i_1_n_0 : STD_LOGIC; - signal \level_next0_carry_i_3__0_n_0\ : STD_LOGIC; - signal level_next0_carry_i_4_n_0 : STD_LOGIC; - signal level_next0_carry_i_5_n_0 : STD_LOGIC; - signal level_next0_carry_i_6_n_0 : STD_LOGIC; - signal level_next0_carry_n_0 : STD_LOGIC; - signal level_next0_carry_n_1 : STD_LOGIC; - signal level_next0_carry_n_2 : STD_LOGIC; - signal level_next0_carry_n_3 : STD_LOGIC; - signal level_next0_carry_n_7 : STD_LOGIC; - signal \^m_axis_raddr_reg[4]_0\ : STD_LOGIC_VECTOR ( 4 downto 0 ); - signal \m_axis_valid_i_1__1_n_0\ : STD_LOGIC; - signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 4 downto 0 ); - signal \p_0_in__1\ : STD_LOGIC_VECTOR ( 4 downto 0 ); - signal s_axis_ready_i_10_n_0 : STD_LOGIC; - signal s_axis_ready_i_11_n_0 : STD_LOGIC; - signal \s_axis_ready_i_1__1_n_0\ : STD_LOGIC; - signal s_axis_ready_i_4_n_0 : STD_LOGIC; - signal s_axis_ready_i_5_n_0 : STD_LOGIC; - signal s_axis_ready_i_6_n_0 : STD_LOGIC; - signal s_axis_ready_i_8_n_0 : STD_LOGIC; - signal s_axis_ready_i_9_n_0 : STD_LOGIC; - signal \^s_axis_ready_reg_0\ : STD_LOGIC; - signal s_axis_ready_reg_i_2_n_3 : STD_LOGIC; - signal s_axis_ready_reg_i_2_n_6 : STD_LOGIC; - signal s_axis_ready_reg_i_2_n_7 : STD_LOGIC; - signal s_axis_ready_reg_i_3_n_0 : STD_LOGIC; - signal s_axis_ready_reg_i_3_n_1 : STD_LOGIC; - signal s_axis_ready_reg_i_3_n_2 : STD_LOGIC; - signal s_axis_ready_reg_i_3_n_3 : STD_LOGIC; - signal s_axis_ready_reg_i_3_n_4 : STD_LOGIC; - signal s_axis_ready_reg_i_3_n_5 : STD_LOGIC; - signal s_axis_ready_reg_i_3_n_6 : STD_LOGIC; - signal \^s_axis_waddr_reg[4]_0\ : STD_LOGIC_VECTOR ( 4 downto 0 ); - signal \^s_mem_write\ : STD_LOGIC; - signal \NLW_level_next0_carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); - signal \NLW_level_next0_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); - signal NLW_s_axis_ready_reg_i_2_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 1 ); - signal NLW_s_axis_ready_reg_i_2_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 ); - signal NLW_s_axis_ready_reg_i_3_O_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of \m_axis_raddr[1]_i_1__1\ : label is "soft_lutpair9"; - attribute SOFT_HLUTNM of \m_axis_raddr[2]_i_1__1\ : label is "soft_lutpair9"; - attribute SOFT_HLUTNM of \m_axis_raddr[3]_i_1__1\ : label is "soft_lutpair8"; - attribute SOFT_HLUTNM of \m_axis_raddr[4]_i_2__0\ : label is "soft_lutpair8"; - attribute SOFT_HLUTNM of \s_axis_waddr[1]_i_1__1\ : label is "soft_lutpair10"; - attribute SOFT_HLUTNM of \s_axis_waddr[2]_i_1__1\ : label is "soft_lutpair10"; - attribute SOFT_HLUTNM of \s_axis_waddr[3]_i_1__1\ : label is "soft_lutpair7"; - attribute SOFT_HLUTNM of \s_axis_waddr[4]_i_1__0\ : label is "soft_lutpair7"; -begin - Q(5 downto 0) <= \^q\(5 downto 0); - \m_axis_raddr_reg[4]_0\(4 downto 0) <= \^m_axis_raddr_reg[4]_0\(4 downto 0); - s_axis_ready_reg_0 <= \^s_axis_ready_reg_0\; - \s_axis_waddr_reg[4]_0\(4 downto 0) <= \^s_axis_waddr_reg[4]_0\(4 downto 0); - s_mem_write <= \^s_mem_write\; -irq_i_1: unisim.vcomponents.LUT5 - generic map( - INIT => X"FFEAEAEA" - ) - port map ( - I0 => irq_i_2_n_0, - I1 => irq_reg(0), - I2 => up_irq_source(0), - I3 => irq_reg(1), - I4 => up_irq_source(1), - O => \up_irq_mask_reg[0]\ - ); -irq_i_2: unisim.vcomponents.LUT6 - generic map( - INIT => X"FFFFF88888888888" - ) - port map ( - I0 => irq_reg_0(0), - I1 => irq_reg(3), - I2 => \^q\(4), - I3 => \^q\(3), - I4 => \^q\(5), - I5 => irq_reg(2), - O => irq_i_2_n_0 - ); -\level[0]_i_1__0\: unisim.vcomponents.LUT4 - generic map( - INIT => X"9666" - ) - port map ( - I0 => \^q\(0), - I1 => p_0_in, - I2 => sdi_data_valid, - I3 => \^s_axis_ready_reg_0\, - O => level_next(0) - ); -level_next0_carry: unisim.vcomponents.CARRY4 - port map ( - CI => '0', - CO(3) => level_next0_carry_n_0, - CO(2) => level_next0_carry_n_1, - CO(1) => level_next0_carry_n_2, - CO(0) => level_next0_carry_n_3, - CYINIT => '0', - DI(3) => \^q\(2), - DI(2) => level_next0_carry_i_1_n_0, - DI(1) => DI(0), - DI(0) => \^q\(0), - O(3 downto 1) => level_next(3 downto 1), - O(0) => level_next0_carry_n_7, - S(3) => \level_next0_carry_i_3__0_n_0\, - S(2) => level_next0_carry_i_4_n_0, - S(1) => level_next0_carry_i_5_n_0, - S(0) => level_next0_carry_i_6_n_0 - ); -\level_next0_carry__0\: unisim.vcomponents.CARRY4 - port map ( - CI => level_next0_carry_n_0, - CO(3 downto 1) => \NLW_level_next0_carry__0_CO_UNCONNECTED\(3 downto 1), - CO(0) => \level_next0_carry__0_n_3\, - CYINIT => '0', - DI(3 downto 1) => B"000", - DI(0) => \^q\(3), - O(3 downto 2) => \NLW_level_next0_carry__0_O_UNCONNECTED\(3 downto 2), - O(1 downto 0) => level_next(5 downto 4), - S(3 downto 2) => B"00", - S(1) => \level_next0_carry__0_i_1__0_n_0\, - S(0) => \level_next0_carry__0_i_2__0_n_0\ - ); -\level_next0_carry__0_i_1__0\: unisim.vcomponents.LUT2 - generic map( - INIT => X"9" - ) - port map ( - I0 => \^q\(4), - I1 => \^q\(5), - O => \level_next0_carry__0_i_1__0_n_0\ - ); -\level_next0_carry__0_i_2__0\: unisim.vcomponents.LUT2 - generic map( - INIT => X"9" - ) - port map ( - I0 => \^q\(3), - I1 => \^q\(4), - O => \level_next0_carry__0_i_2__0_n_0\ - ); -level_next0_carry_i_1: unisim.vcomponents.LUT3 - generic map( - INIT => X"8F" - ) - port map ( - I0 => \^s_axis_ready_reg_0\, - I1 => sdi_data_valid, - I2 => p_0_in, - O => level_next0_carry_i_1_n_0 - ); -\level_next0_carry_i_3__0\: unisim.vcomponents.LUT2 - generic map( - INIT => X"9" - ) - port map ( - I0 => \^q\(2), - I1 => \^q\(3), - O => \level_next0_carry_i_3__0_n_0\ - ); -level_next0_carry_i_4: unisim.vcomponents.LUT4 - generic map( - INIT => X"8F70" - ) - port map ( - I0 => \^s_axis_ready_reg_0\, - I1 => sdi_data_valid, - I2 => p_0_in, - I3 => \^q\(2), - O => level_next0_carry_i_4_n_0 - ); -level_next0_carry_i_5: unisim.vcomponents.LUT4 - generic map( - INIT => X"8F70" - ) - port map ( - I0 => \^s_axis_ready_reg_0\, - I1 => sdi_data_valid, - I2 => p_0_in, - I3 => \^q\(1), - O => level_next0_carry_i_5_n_0 - ); -level_next0_carry_i_6: unisim.vcomponents.LUT4 - generic map( - INIT => X"9666" - ) - port map ( - I0 => \^q\(0), - I1 => p_0_in, - I2 => sdi_data_valid, - I3 => \^s_axis_ready_reg_0\, - O => level_next0_carry_i_6_n_0 - ); -\level_reg[0]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => level_next(0), - Q => \^q\(0), - R => up_sw_reset - ); -\level_reg[1]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => level_next(1), - Q => \^q\(1), - R => up_sw_reset - ); -\level_reg[2]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => level_next(2), - Q => \^q\(2), - R => up_sw_reset - ); -\level_reg[3]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => level_next(3), - Q => \^q\(3), - R => up_sw_reset - ); -\level_reg[4]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => level_next(4), - Q => \^q\(4), - R => up_sw_reset - ); -\level_reg[5]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => level_next(5), - Q => \^q\(5), - R => up_sw_reset - ); -\m_axis_raddr[0]_i_1__1\: unisim.vcomponents.LUT1 - generic map( - INIT => X"1" - ) - port map ( - I0 => \^m_axis_raddr_reg[4]_0\(0), - O => \p_0_in__1\(0) - ); -\m_axis_raddr[1]_i_1__1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => \^m_axis_raddr_reg[4]_0\(0), - I1 => \^m_axis_raddr_reg[4]_0\(1), - O => \p_0_in__1\(1) - ); -\m_axis_raddr[2]_i_1__1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"78" - ) - port map ( - I0 => \^m_axis_raddr_reg[4]_0\(0), - I1 => \^m_axis_raddr_reg[4]_0\(1), - I2 => \^m_axis_raddr_reg[4]_0\(2), - O => \p_0_in__1\(2) - ); -\m_axis_raddr[3]_i_1__1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"7F80" - ) - port map ( - I0 => \^m_axis_raddr_reg[4]_0\(1), - I1 => \^m_axis_raddr_reg[4]_0\(0), - I2 => \^m_axis_raddr_reg[4]_0\(2), - I3 => \^m_axis_raddr_reg[4]_0\(3), - O => \p_0_in__1\(3) - ); -\m_axis_raddr[4]_i_2__0\: unisim.vcomponents.LUT5 - generic map( - INIT => X"7FFF8000" - ) - port map ( - I0 => \^m_axis_raddr_reg[4]_0\(2), - I1 => \^m_axis_raddr_reg[4]_0\(0), - I2 => \^m_axis_raddr_reg[4]_0\(1), - I3 => \^m_axis_raddr_reg[4]_0\(3), - I4 => \^m_axis_raddr_reg[4]_0\(4), - O => \p_0_in__1\(4) - ); -\m_axis_raddr_reg[0]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => p_0_in, - D => \p_0_in__1\(0), - Q => \^m_axis_raddr_reg[4]_0\(0), - R => up_sw_reset - ); -\m_axis_raddr_reg[1]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => p_0_in, - D => \p_0_in__1\(1), - Q => \^m_axis_raddr_reg[4]_0\(1), - R => up_sw_reset - ); -\m_axis_raddr_reg[2]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => p_0_in, - D => \p_0_in__1\(2), - Q => \^m_axis_raddr_reg[4]_0\(2), - R => up_sw_reset - ); -\m_axis_raddr_reg[3]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => p_0_in, - D => \p_0_in__1\(3), - Q => \^m_axis_raddr_reg[4]_0\(3), - R => up_sw_reset - ); -\m_axis_raddr_reg[4]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => p_0_in, - D => \p_0_in__1\(4), - Q => \^m_axis_raddr_reg[4]_0\(4), - R => up_sw_reset - ); -\m_axis_valid_i_1__1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"FFFFFFFFFFFFFFFE" - ) - port map ( - I0 => level_next0_carry_n_7, - I1 => s_axis_ready_reg_i_3_n_6, - I2 => s_axis_ready_reg_i_2_n_6, - I3 => s_axis_ready_reg_i_3_n_5, - I4 => s_axis_ready_reg_i_3_n_4, - I5 => s_axis_ready_reg_i_2_n_7, - O => \m_axis_valid_i_1__1_n_0\ - ); -m_axis_valid_reg: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => '1', - D => \m_axis_valid_i_1__1_n_0\, - Q => m_axis_valid_reg_0, - R => up_sw_reset - ); -ram_reg_0_31_0_5_i_1: unisim.vcomponents.LUT2 - generic map( - INIT => X"8" - ) - port map ( - I0 => \^s_axis_ready_reg_0\, - I1 => sdi_data_valid, - O => \^s_mem_write\ - ); -s_axis_ready_i_10: unisim.vcomponents.LUT4 - generic map( - INIT => X"8F70" - ) - port map ( - I0 => \^s_axis_ready_reg_0\, - I1 => sdi_data_valid, - I2 => p_0_in, - I3 => \^q\(1), - O => s_axis_ready_i_10_n_0 - ); -s_axis_ready_i_11: unisim.vcomponents.LUT4 - generic map( - INIT => X"9666" - ) - port map ( - I0 => \^q\(0), - I1 => p_0_in, - I2 => sdi_data_valid, - I3 => \^s_axis_ready_reg_0\, - O => s_axis_ready_i_11_n_0 - ); -\s_axis_ready_i_1__1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"FFFFFFFFFFFFFFFB" - ) - port map ( - I0 => level_next0_carry_n_7, - I1 => s_axis_ready_reg_i_2_n_6, - I2 => s_axis_ready_reg_i_3_n_4, - I3 => s_axis_ready_reg_i_3_n_6, - I4 => s_axis_ready_reg_i_3_n_5, - I5 => s_axis_ready_reg_i_2_n_7, - O => \s_axis_ready_i_1__1_n_0\ - ); -s_axis_ready_i_4: unisim.vcomponents.LUT2 - generic map( - INIT => X"9" - ) - port map ( - I0 => \^q\(4), - I1 => \^q\(5), - O => s_axis_ready_i_4_n_0 - ); -s_axis_ready_i_5: unisim.vcomponents.LUT2 - generic map( - INIT => X"9" - ) - port map ( - I0 => \^q\(3), - I1 => \^q\(4), - O => s_axis_ready_i_5_n_0 - ); -s_axis_ready_i_6: unisim.vcomponents.LUT3 - generic map( - INIT => X"8F" - ) - port map ( - I0 => \^s_axis_ready_reg_0\, - I1 => sdi_data_valid, - I2 => p_0_in, - O => s_axis_ready_i_6_n_0 - ); -s_axis_ready_i_8: unisim.vcomponents.LUT2 - generic map( - INIT => X"9" - ) - port map ( - I0 => \^q\(2), - I1 => \^q\(3), - O => s_axis_ready_i_8_n_0 - ); -s_axis_ready_i_9: unisim.vcomponents.LUT4 - generic map( - INIT => X"8F70" - ) - port map ( - I0 => \^s_axis_ready_reg_0\, - I1 => sdi_data_valid, - I2 => p_0_in, - I3 => \^q\(2), - O => s_axis_ready_i_9_n_0 - ); -s_axis_ready_reg: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => '1', - D => \s_axis_ready_i_1__1_n_0\, - Q => \^s_axis_ready_reg_0\, - R => up_sw_reset - ); -s_axis_ready_reg_i_2: unisim.vcomponents.CARRY4 - port map ( - CI => s_axis_ready_reg_i_3_n_0, - CO(3 downto 1) => NLW_s_axis_ready_reg_i_2_CO_UNCONNECTED(3 downto 1), - CO(0) => s_axis_ready_reg_i_2_n_3, - CYINIT => '0', - DI(3 downto 1) => B"000", - DI(0) => \^q\(3), - O(3 downto 2) => NLW_s_axis_ready_reg_i_2_O_UNCONNECTED(3 downto 2), - O(1) => s_axis_ready_reg_i_2_n_6, - O(0) => s_axis_ready_reg_i_2_n_7, - S(3 downto 2) => B"00", - S(1) => s_axis_ready_i_4_n_0, - S(0) => s_axis_ready_i_5_n_0 - ); -s_axis_ready_reg_i_3: unisim.vcomponents.CARRY4 - port map ( - CI => '0', - CO(3) => s_axis_ready_reg_i_3_n_0, - CO(2) => s_axis_ready_reg_i_3_n_1, - CO(1) => s_axis_ready_reg_i_3_n_2, - CO(0) => s_axis_ready_reg_i_3_n_3, - CYINIT => '0', - DI(3) => \^q\(2), - DI(2) => s_axis_ready_i_6_n_0, - DI(1) => m_axis_valid_reg_1(0), - DI(0) => \^q\(0), - O(3) => s_axis_ready_reg_i_3_n_4, - O(2) => s_axis_ready_reg_i_3_n_5, - O(1) => s_axis_ready_reg_i_3_n_6, - O(0) => NLW_s_axis_ready_reg_i_3_O_UNCONNECTED(0), - S(3) => s_axis_ready_i_8_n_0, - S(2) => s_axis_ready_i_9_n_0, - S(1) => s_axis_ready_i_10_n_0, - S(0) => s_axis_ready_i_11_n_0 - ); -\s_axis_waddr[0]_i_1__1\: unisim.vcomponents.LUT1 - generic map( - INIT => X"1" - ) - port map ( - I0 => \^s_axis_waddr_reg[4]_0\(0), - O => \p_0_in__0\(0) - ); -\s_axis_waddr[1]_i_1__1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => \^s_axis_waddr_reg[4]_0\(0), - I1 => \^s_axis_waddr_reg[4]_0\(1), - O => \p_0_in__0\(1) - ); -\s_axis_waddr[2]_i_1__1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"78" - ) - port map ( - I0 => \^s_axis_waddr_reg[4]_0\(0), - I1 => \^s_axis_waddr_reg[4]_0\(1), - I2 => \^s_axis_waddr_reg[4]_0\(2), - O => \p_0_in__0\(2) - ); -\s_axis_waddr[3]_i_1__1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"7F80" - ) - port map ( - I0 => \^s_axis_waddr_reg[4]_0\(1), - I1 => \^s_axis_waddr_reg[4]_0\(0), - I2 => \^s_axis_waddr_reg[4]_0\(2), - I3 => \^s_axis_waddr_reg[4]_0\(3), - O => \p_0_in__0\(3) - ); -\s_axis_waddr[4]_i_1__0\: unisim.vcomponents.LUT5 - generic map( - INIT => X"7FFF8000" - ) - port map ( - I0 => \^s_axis_waddr_reg[4]_0\(2), - I1 => \^s_axis_waddr_reg[4]_0\(0), - I2 => \^s_axis_waddr_reg[4]_0\(1), - I3 => \^s_axis_waddr_reg[4]_0\(3), - I4 => \^s_axis_waddr_reg[4]_0\(4), - O => \p_0_in__0\(4) - ); -\s_axis_waddr_reg[0]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => \^s_mem_write\, - D => \p_0_in__0\(0), - Q => \^s_axis_waddr_reg[4]_0\(0), - R => up_sw_reset - ); -\s_axis_waddr_reg[1]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => \^s_mem_write\, - D => \p_0_in__0\(1), - Q => \^s_axis_waddr_reg[4]_0\(1), - R => up_sw_reset - ); -\s_axis_waddr_reg[2]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => \^s_mem_write\, - D => \p_0_in__0\(2), - Q => \^s_axis_waddr_reg[4]_0\(2), - R => up_sw_reset - ); -\s_axis_waddr_reg[3]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => \^s_mem_write\, - D => \p_0_in__0\(3), - Q => \^s_axis_waddr_reg[4]_0\(3), - R => up_sw_reset - ); -\s_axis_waddr_reg[4]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => \^s_mem_write\, - D => \p_0_in__0\(4), - Q => \^s_axis_waddr_reg[4]_0\(4), - R => up_sw_reset - ); -\up_rdata_ff[2]_i_6\: unisim.vcomponents.LUT3 - generic map( - INIT => X"F8" - ) - port map ( - I0 => \^q\(4), - I1 => \^q\(3), - I2 => \^q\(5), - O => \level_reg[4]_0\(0) - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity system_bd_axi_spi_engine_0_0_up_axi is - port ( - s_axi_aresetn_0 : out STD_LOGIC; - up_wreq_s : out STD_LOGIC; - s_axi_bvalid : out STD_LOGIC; - s_axi_awready : out STD_LOGIC; - s_axi_wready : out STD_LOGIC; - up_rreq_s : out STD_LOGIC; - up_axi_rvalid_int_reg_0 : out STD_LOGIC; - s_axi_arready : out STD_LOGIC; - s_mem_write : out STD_LOGIC; - Q : out STD_LOGIC_VECTOR ( 0 to 0 ); - \up_waddr_int_reg[4]_0\ : out STD_LOGIC; - s_axis_ready_reg : out STD_LOGIC; - E : out STD_LOGIC_VECTOR ( 0 to 0 ); - \up_waddr_int_reg[2]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); - offload0_cmd_wr_en : out STD_LOGIC; - offload0_sdo_wr_en : out STD_LOGIC; - s_axis_ready_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 ); - p_1_in : out STD_LOGIC; - \up_raddr_int_reg[5]_0\ : out STD_LOGIC; - \up_raddr_int_reg[4]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); - \up_raddr_int_reg[0]_0\ : out STD_LOGIC; - \up_raddr_int_reg[0]_1\ : out STD_LOGIC; - \up_raddr_int_reg[3]_0\ : out STD_LOGIC; - \up_scratch_reg[8]\ : out STD_LOGIC; - \up_scratch_reg[9]\ : out STD_LOGIC; - \up_scratch_reg[10]\ : out STD_LOGIC; - \up_scratch_reg[11]\ : out STD_LOGIC; - \up_scratch_reg[12]\ : out STD_LOGIC; - \up_scratch_reg[13]\ : out STD_LOGIC; - \up_scratch_reg[14]\ : out STD_LOGIC; - \up_scratch_reg[15]\ : out STD_LOGIC; - \up_scratch_reg[17]\ : out STD_LOGIC; - \up_scratch_reg[18]\ : out STD_LOGIC; - \up_scratch_reg[19]\ : out STD_LOGIC; - \up_scratch_reg[20]\ : out STD_LOGIC; - \up_scratch_reg[21]\ : out STD_LOGIC; - \up_scratch_reg[22]\ : out STD_LOGIC; - \up_scratch_reg[23]\ : out STD_LOGIC; - \up_scratch_reg[24]\ : out STD_LOGIC; - \up_scratch_reg[25]\ : out STD_LOGIC; - \up_scratch_reg[26]\ : out STD_LOGIC; - \up_scratch_reg[27]\ : out STD_LOGIC; - \up_scratch_reg[28]\ : out STD_LOGIC; - \up_scratch_reg[29]\ : out STD_LOGIC; - \up_scratch_reg[30]\ : out STD_LOGIC; - \up_scratch_reg[31]\ : out STD_LOGIC; - sdi_data_valid_0 : out STD_LOGIC_VECTOR ( 0 to 0 ); - p_0_in : out STD_LOGIC; - \up_raddr_int_reg[3]_1\ : out STD_LOGIC; - \up_raddr_int_reg[3]_2\ : out STD_LOGIC; - \up_raddr_int_reg[3]_3\ : out STD_LOGIC; - \up_raddr_int_reg[3]_4\ : out STD_LOGIC; - \up_raddr_int_reg[9]_0\ : out STD_LOGIC; - \up_raddr_int_reg[6]_0\ : out STD_LOGIC; - DI : out STD_LOGIC_VECTOR ( 0 to 0 ); - \up_wdata_int_reg[0]_0\ : out STD_LOGIC; - \up_wdata_int_reg[31]_0\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); - \up_waddr_int_reg[0]_0\ : out STD_LOGIC; - \up_wdata_int_reg[0]_1\ : out STD_LOGIC; - \up_wdata_int_reg[0]_2\ : out STD_LOGIC; - s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); - s_axi_aclk : in STD_LOGIC; - \s_axis_waddr_reg[0]\ : in STD_LOGIC; - \s_axis_waddr_reg[0]_0\ : in STD_LOGIC; - up_wack_ff : in STD_LOGIC; - up_rack_ff : in STD_LOGIC; - s_axi_aresetn : in STD_LOGIC; - m_axis_data : in STD_LOGIC_VECTOR ( 7 downto 0 ); - \up_rdata_ff_reg[31]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); - sdi_data_valid : in STD_LOGIC; - sdi_data_ready : in STD_LOGIC; - \m_axis_raddr_reg[0]\ : in STD_LOGIC; - \up_rdata_ff_reg[7]\ : in STD_LOGIC_VECTOR ( 6 downto 0 ); - \up_rdata_ff_reg[1]\ : in STD_LOGIC; - \up_rdata_ff_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 ); - \up_rdata_ff_reg[5]_0\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); - up_irq_source : in STD_LOGIC_VECTOR ( 2 downto 0 ); - offload0_enable : in STD_LOGIC; - \up_rdata_ff[3]_i_3_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); - \up_rdata_ff_reg[7]_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); - up_sw_reset : in STD_LOGIC; - sync_id_pending_reg : in STD_LOGIC_VECTOR ( 0 to 0 ); - \up_rdata_ff_reg[4]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); - s_axi_wvalid : in STD_LOGIC; - s_axi_awvalid : in STD_LOGIC; - s_axi_bready : in STD_LOGIC; - s_axi_arvalid : in STD_LOGIC; - s_axi_rready : in STD_LOGIC; - up_rdata_ff : in STD_LOGIC_VECTOR ( 31 downto 0 ); - offload0_enabled : in STD_LOGIC; - \up_rdata_ff[0]_i_8_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); - sync_valid : in STD_LOGIC; - offload0_mem_reset : in STD_LOGIC; - s_axi_awaddr : in STD_LOGIC_VECTOR ( 13 downto 0 ); - s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); - s_axi_araddr : in STD_LOGIC_VECTOR ( 13 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of system_bd_axi_spi_engine_0_0_up_axi : entity is "up_axi"; -end system_bd_axi_spi_engine_0_0_up_axi; - -architecture STRUCTURE of system_bd_axi_spi_engine_0_0_up_axi is - signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 ); - signal \m_axis_raddr[4]_i_3_n_0\ : STD_LOGIC; - signal \m_axis_raddr[4]_i_4_n_0\ : STD_LOGIC; - signal \m_axis_raddr[4]_i_5_n_0\ : STD_LOGIC; - signal offload0_cmd_wr_en_INST_0_i_1_n_0 : STD_LOGIC; - signal offload0_cmd_wr_en_INST_0_i_2_n_0 : STD_LOGIC; - signal offload0_cmd_wr_en_INST_0_i_3_n_0 : STD_LOGIC; - signal offload0_enable_reg_i_2_n_0 : STD_LOGIC; - signal offload0_enable_reg_i_3_n_0 : STD_LOGIC; - signal offload0_enable_reg_i_4_n_0 : STD_LOGIC; - signal offload0_mem_reset_reg_i_2_n_0 : STD_LOGIC; - signal offload0_mem_reset_reg_i_3_n_0 : STD_LOGIC; - signal offload0_mem_reset_reg_i_4_n_0 : STD_LOGIC; - signal \^p_0_in\ : STD_LOGIC; - signal p_0_in6_in : STD_LOGIC; - signal p_0_in7_in : STD_LOGIC; - signal p_1_in_0 : STD_LOGIC; - signal \p_1_in__0\ : STD_LOGIC; - signal p_2_in : STD_LOGIC_VECTOR ( 4 downto 0 ); - signal p_5_in : STD_LOGIC; - signal ram_reg_0_15_12_15_i_3_n_0 : STD_LOGIC; - signal \^s_axi_aresetn_0\ : STD_LOGIC; - signal \^s_axi_arready\ : STD_LOGIC; - signal \^s_axi_awready\ : STD_LOGIC; - signal \^s_axi_bvalid\ : STD_LOGIC; - signal \^s_axi_wready\ : STD_LOGIC; - signal \s_axis_waddr[3]_i_3_n_0\ : STD_LOGIC; - signal \s_axis_waddr[3]_i_4_n_0\ : STD_LOGIC; - signal \s_axis_waddr[3]_i_5_n_0\ : STD_LOGIC; - signal \s_axis_waddr[3]_i_6_n_0\ : STD_LOGIC; - signal sync_id_pending_i_2_n_0 : STD_LOGIC; - signal sync_id_pending_i_3_n_0 : STD_LOGIC; - signal up_axi_arready_int_i_1_n_0 : STD_LOGIC; - signal up_axi_arready_int_i_2_n_0 : STD_LOGIC; - signal up_axi_awready_int_i_2_n_0 : STD_LOGIC; - signal up_axi_bvalid_int_i_1_n_0 : STD_LOGIC; - signal \up_axi_rdata_int[31]_i_1_n_0\ : STD_LOGIC; - signal up_axi_rvalid_int_i_1_n_0 : STD_LOGIC; - signal \^up_axi_rvalid_int_reg_0\ : STD_LOGIC; - signal up_axi_wready_int_i_1_n_0 : STD_LOGIC; - signal up_rack_d : STD_LOGIC; - signal up_rack_s : STD_LOGIC; - signal up_rack_s_1 : STD_LOGIC; - signal \^up_raddr_int_reg[4]_0\ : STD_LOGIC_VECTOR ( 1 downto 0 ); - signal up_raddr_s : STD_LOGIC_VECTOR ( 13 downto 0 ); - signal \up_rcount[0]_i_1_n_0\ : STD_LOGIC; - signal \up_rcount[1]_i_1_n_0\ : STD_LOGIC; - signal \up_rcount[2]_i_1_n_0\ : STD_LOGIC; - signal \up_rcount[3]_i_1_n_0\ : STD_LOGIC; - signal \up_rcount[4]_i_1_n_0\ : STD_LOGIC; - signal \up_rcount[4]_i_2_n_0\ : STD_LOGIC; - signal \up_rcount_reg_n_0_[0]\ : STD_LOGIC; - signal \up_rcount_reg_n_0_[1]\ : STD_LOGIC; - signal \up_rcount_reg_n_0_[2]\ : STD_LOGIC; - signal \up_rcount_reg_n_0_[3]\ : STD_LOGIC; - signal up_rdata_d : STD_LOGIC_VECTOR ( 31 downto 0 ); - signal \up_rdata_d[0]_i_1_n_0\ : STD_LOGIC; - signal \up_rdata_d[10]_i_1_n_0\ : STD_LOGIC; - signal \up_rdata_d[11]_i_1_n_0\ : STD_LOGIC; - signal \up_rdata_d[12]_i_1_n_0\ : STD_LOGIC; - signal \up_rdata_d[14]_i_1_n_0\ : STD_LOGIC; - signal \up_rdata_d[15]_i_1_n_0\ : STD_LOGIC; - signal \up_rdata_d[16]_i_1_n_0\ : STD_LOGIC; - signal \up_rdata_d[18]_i_1_n_0\ : STD_LOGIC; - signal \up_rdata_d[19]_i_1_n_0\ : STD_LOGIC; - signal \up_rdata_d[21]_i_1_n_0\ : STD_LOGIC; - signal \up_rdata_d[23]_i_1_n_0\ : STD_LOGIC; - signal \up_rdata_d[25]_i_1_n_0\ : STD_LOGIC; - signal \up_rdata_d[26]_i_1_n_0\ : STD_LOGIC; - signal \up_rdata_d[27]_i_1_n_0\ : STD_LOGIC; - signal \up_rdata_d[28]_i_1_n_0\ : STD_LOGIC; - signal \up_rdata_d[29]_i_1_n_0\ : STD_LOGIC; - signal \up_rdata_d[2]_i_1_n_0\ : STD_LOGIC; - signal \up_rdata_d[30]_i_1_n_0\ : STD_LOGIC; - signal \up_rdata_d[31]_i_1_n_0\ : STD_LOGIC; - signal \up_rdata_d[31]_i_2_n_0\ : STD_LOGIC; - signal \up_rdata_d[3]_i_1_n_0\ : STD_LOGIC; - signal \up_rdata_d[5]_i_1_n_0\ : STD_LOGIC; - signal \up_rdata_d[7]_i_1_n_0\ : STD_LOGIC; - signal \up_rdata_d[9]_i_1_n_0\ : STD_LOGIC; - signal \up_rdata_ff[0]_i_10_n_0\ : STD_LOGIC; - signal \up_rdata_ff[0]_i_11_n_0\ : STD_LOGIC; - signal \up_rdata_ff[0]_i_12_n_0\ : STD_LOGIC; - signal \up_rdata_ff[0]_i_2_n_0\ : STD_LOGIC; - signal \up_rdata_ff[0]_i_3_n_0\ : STD_LOGIC; - signal \up_rdata_ff[0]_i_4_n_0\ : STD_LOGIC; - signal \up_rdata_ff[0]_i_5_n_0\ : STD_LOGIC; - signal \up_rdata_ff[0]_i_6_n_0\ : STD_LOGIC; - signal \up_rdata_ff[0]_i_7_n_0\ : STD_LOGIC; - signal \up_rdata_ff[0]_i_8_n_0\ : STD_LOGIC; - signal \up_rdata_ff[0]_i_9_n_0\ : STD_LOGIC; - signal \up_rdata_ff[16]_i_2_n_0\ : STD_LOGIC; - signal \up_rdata_ff[16]_i_3_n_0\ : STD_LOGIC; - signal \up_rdata_ff[1]_i_3_n_0\ : STD_LOGIC; - signal \up_rdata_ff[1]_i_4_n_0\ : STD_LOGIC; - signal \up_rdata_ff[1]_i_5_n_0\ : STD_LOGIC; - signal \up_rdata_ff[1]_i_6_n_0\ : STD_LOGIC; - signal \up_rdata_ff[1]_i_7_n_0\ : STD_LOGIC; - signal \up_rdata_ff[2]_i_10_n_0\ : STD_LOGIC; - signal \up_rdata_ff[2]_i_2_n_0\ : STD_LOGIC; - signal \up_rdata_ff[2]_i_3_n_0\ : STD_LOGIC; - signal \up_rdata_ff[2]_i_4_n_0\ : STD_LOGIC; - signal \up_rdata_ff[2]_i_5_n_0\ : STD_LOGIC; - signal \up_rdata_ff[2]_i_7_n_0\ : STD_LOGIC; - signal \up_rdata_ff[2]_i_8_n_0\ : STD_LOGIC; - signal \up_rdata_ff[2]_i_9_n_0\ : STD_LOGIC; - signal \up_rdata_ff[31]_i_3_n_0\ : STD_LOGIC; - signal \up_rdata_ff[31]_i_4_n_0\ : STD_LOGIC; - signal \up_rdata_ff[3]_i_2_n_0\ : STD_LOGIC; - signal \up_rdata_ff[3]_i_3_n_0\ : STD_LOGIC; - signal \up_rdata_ff[3]_i_4_n_0\ : STD_LOGIC; - signal \up_rdata_ff[3]_i_5_n_0\ : STD_LOGIC; - signal \up_rdata_ff[3]_i_6_n_0\ : STD_LOGIC; - signal \up_rdata_ff[3]_i_7_n_0\ : STD_LOGIC; - signal \up_rdata_ff[3]_i_8_n_0\ : STD_LOGIC; - signal \up_rdata_ff[3]_i_9_n_0\ : STD_LOGIC; - signal \up_rdata_ff[4]_i_2_n_0\ : STD_LOGIC; - signal \up_rdata_ff[4]_i_3_n_0\ : STD_LOGIC; - signal \up_rdata_ff[4]_i_4_n_0\ : STD_LOGIC; - signal \up_rdata_ff[4]_i_5_n_0\ : STD_LOGIC; - signal \up_rdata_ff[5]_i_2_n_0\ : STD_LOGIC; - signal \up_rdata_ff[5]_i_3_n_0\ : STD_LOGIC; - signal \up_rdata_ff[5]_i_4_n_0\ : STD_LOGIC; - signal \up_rdata_ff[5]_i_5_n_0\ : STD_LOGIC; - signal \up_rdata_ff[6]_i_2_n_0\ : STD_LOGIC; - signal \up_rdata_ff[6]_i_3_n_0\ : STD_LOGIC; - signal \up_rdata_ff[6]_i_4_n_0\ : STD_LOGIC; - signal \up_rdata_ff[7]_i_2_n_0\ : STD_LOGIC; - signal \up_rdata_ff[7]_i_3_n_0\ : STD_LOGIC; - signal up_rreq_int_i_1_n_0 : STD_LOGIC; - signal \^up_rreq_s\ : STD_LOGIC; - signal up_rsel_i_1_n_0 : STD_LOGIC; - signal up_rsel_reg_n_0 : STD_LOGIC; - signal \up_scratch[31]_i_2_n_0\ : STD_LOGIC; - signal \up_scratch[31]_i_3_n_0\ : STD_LOGIC; - signal up_sw_reset_i_2_n_0 : STD_LOGIC; - signal up_wack_d : STD_LOGIC; - signal up_wack_s : STD_LOGIC; - signal \^up_waddr_int_reg[4]_0\ : STD_LOGIC; - signal up_waddr_s : STD_LOGIC_VECTOR ( 13 downto 1 ); - signal \up_wcount_reg_n_0_[0]\ : STD_LOGIC; - signal \up_wcount_reg_n_0_[1]\ : STD_LOGIC; - signal \up_wcount_reg_n_0_[2]\ : STD_LOGIC; - signal \up_wcount_reg_n_0_[3]\ : STD_LOGIC; - signal \^up_wdata_int_reg[31]_0\ : STD_LOGIC_VECTOR ( 31 downto 0 ); - signal up_wreq_int_i_1_n_0 : STD_LOGIC; - signal \^up_wreq_s\ : STD_LOGIC; - signal up_wsel_i_1_n_0 : STD_LOGIC; - signal up_wsel_reg_n_0 : STD_LOGIC; - attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of \m_axis_raddr[4]_i_3\ : label is "soft_lutpair28"; - attribute SOFT_HLUTNM of \m_axis_raddr[4]_i_5\ : label is "soft_lutpair23"; - attribute SOFT_HLUTNM of offload0_cmd_wr_en_INST_0 : label is "soft_lutpair32"; - attribute SOFT_HLUTNM of offload0_cmd_wr_en_INST_0_i_3 : label is "soft_lutpair29"; - attribute SOFT_HLUTNM of offload0_enable_reg_i_2 : label is "soft_lutpair31"; - attribute SOFT_HLUTNM of offload0_enable_reg_i_3 : label is "soft_lutpair58"; - attribute SOFT_HLUTNM of offload0_enable_reg_i_4 : label is "soft_lutpair42"; - attribute SOFT_HLUTNM of offload0_mem_reset_reg_i_3 : label is "soft_lutpair29"; - attribute SOFT_HLUTNM of offload0_mem_reset_reg_i_4 : label is "soft_lutpair31"; - attribute SOFT_HLUTNM of offload0_sdo_wr_en_INST_0 : label is "soft_lutpair42"; - attribute SOFT_HLUTNM of ram_reg_0_15_12_15_i_3 : label is "soft_lutpair58"; - attribute SOFT_HLUTNM of \s_axis_waddr[3]_i_3\ : label is "soft_lutpair25"; - attribute SOFT_HLUTNM of \s_axis_waddr[3]_i_6\ : label is "soft_lutpair33"; - attribute SOFT_HLUTNM of \s_axis_waddr[4]_i_1\ : label is "soft_lutpair32"; - attribute SOFT_HLUTNM of sync_id_pending_i_2 : label is "soft_lutpair25"; - attribute SOFT_HLUTNM of sync_id_pending_i_3 : label is "soft_lutpair33"; - attribute SOFT_HLUTNM of up_axi_awready_int_i_2 : label is "soft_lutpair57"; - attribute SOFT_HLUTNM of up_axi_wready_int_i_1 : label is "soft_lutpair57"; - attribute SOFT_HLUTNM of \up_rcount[1]_i_1\ : label is "soft_lutpair19"; - attribute SOFT_HLUTNM of \up_rcount[2]_i_1\ : label is "soft_lutpair19"; - attribute SOFT_HLUTNM of \up_rdata_d[0]_i_1\ : label is "soft_lutpair45"; - attribute SOFT_HLUTNM of \up_rdata_d[10]_i_1\ : label is "soft_lutpair41"; - attribute SOFT_HLUTNM of \up_rdata_d[11]_i_1\ : label is "soft_lutpair41"; - attribute SOFT_HLUTNM of \up_rdata_d[12]_i_1\ : label is "soft_lutpair40"; - attribute SOFT_HLUTNM of \up_rdata_d[14]_i_1\ : label is "soft_lutpair40"; - attribute SOFT_HLUTNM of \up_rdata_d[15]_i_1\ : label is "soft_lutpair39"; - attribute SOFT_HLUTNM of \up_rdata_d[16]_i_1\ : label is "soft_lutpair39"; - attribute SOFT_HLUTNM of \up_rdata_d[18]_i_1\ : label is "soft_lutpair38"; - attribute SOFT_HLUTNM of \up_rdata_d[19]_i_1\ : label is "soft_lutpair38"; - attribute SOFT_HLUTNM of \up_rdata_d[21]_i_1\ : label is "soft_lutpair37"; - attribute SOFT_HLUTNM of \up_rdata_d[23]_i_1\ : label is "soft_lutpair37"; - attribute SOFT_HLUTNM of \up_rdata_d[25]_i_1\ : label is "soft_lutpair36"; - attribute SOFT_HLUTNM of \up_rdata_d[26]_i_1\ : label is "soft_lutpair36"; - attribute SOFT_HLUTNM of \up_rdata_d[27]_i_1\ : label is "soft_lutpair35"; - attribute SOFT_HLUTNM of \up_rdata_d[28]_i_1\ : label is "soft_lutpair35"; - attribute SOFT_HLUTNM of \up_rdata_d[2]_i_1\ : label is "soft_lutpair44"; - attribute SOFT_HLUTNM of \up_rdata_d[30]_i_1\ : label is "soft_lutpair34"; - attribute SOFT_HLUTNM of \up_rdata_d[31]_i_2\ : label is "soft_lutpair34"; - attribute SOFT_HLUTNM of \up_rdata_d[3]_i_1\ : label is "soft_lutpair45"; - attribute SOFT_HLUTNM of \up_rdata_d[5]_i_1\ : label is "soft_lutpair43"; - attribute SOFT_HLUTNM of \up_rdata_d[7]_i_1\ : label is "soft_lutpair44"; - attribute SOFT_HLUTNM of \up_rdata_d[9]_i_1\ : label is "soft_lutpair43"; - attribute SOFT_HLUTNM of \up_rdata_ff[0]_i_10\ : label is "soft_lutpair22"; - attribute SOFT_HLUTNM of \up_rdata_ff[0]_i_11\ : label is "soft_lutpair27"; - attribute SOFT_HLUTNM of \up_rdata_ff[0]_i_12\ : label is "soft_lutpair20"; - attribute SOFT_HLUTNM of \up_rdata_ff[0]_i_2\ : label is "soft_lutpair28"; - attribute SOFT_HLUTNM of \up_rdata_ff[0]_i_6\ : label is "soft_lutpair30"; - attribute SOFT_HLUTNM of \up_rdata_ff[0]_i_9\ : label is "soft_lutpair26"; - attribute SOFT_HLUTNM of \up_rdata_ff[10]_i_1\ : label is "soft_lutpair48"; - attribute SOFT_HLUTNM of \up_rdata_ff[11]_i_1\ : label is "soft_lutpair49"; - attribute SOFT_HLUTNM of \up_rdata_ff[12]_i_1\ : label is "soft_lutpair50"; - attribute SOFT_HLUTNM of \up_rdata_ff[13]_i_1\ : label is "soft_lutpair51"; - attribute SOFT_HLUTNM of \up_rdata_ff[14]_i_1\ : label is "soft_lutpair52"; - attribute SOFT_HLUTNM of \up_rdata_ff[15]_i_1\ : label is "soft_lutpair53"; - attribute SOFT_HLUTNM of \up_rdata_ff[16]_i_2\ : label is "soft_lutpair18"; - attribute SOFT_HLUTNM of \up_rdata_ff[16]_i_3\ : label is "soft_lutpair27"; - attribute SOFT_HLUTNM of \up_rdata_ff[17]_i_1\ : label is "soft_lutpair54"; - attribute SOFT_HLUTNM of \up_rdata_ff[18]_i_1\ : label is "soft_lutpair55"; - attribute SOFT_HLUTNM of \up_rdata_ff[19]_i_1\ : label is "soft_lutpair56"; - attribute SOFT_HLUTNM of \up_rdata_ff[1]_i_7\ : label is "soft_lutpair24"; - attribute SOFT_HLUTNM of \up_rdata_ff[20]_i_1\ : label is "soft_lutpair56"; - attribute SOFT_HLUTNM of \up_rdata_ff[21]_i_1\ : label is "soft_lutpair55"; - attribute SOFT_HLUTNM of \up_rdata_ff[22]_i_1\ : label is "soft_lutpair54"; - attribute SOFT_HLUTNM of \up_rdata_ff[23]_i_1\ : label is "soft_lutpair53"; - attribute SOFT_HLUTNM of \up_rdata_ff[24]_i_1\ : label is "soft_lutpair52"; - attribute SOFT_HLUTNM of \up_rdata_ff[25]_i_1\ : label is "soft_lutpair51"; - attribute SOFT_HLUTNM of \up_rdata_ff[26]_i_1\ : label is "soft_lutpair50"; - attribute SOFT_HLUTNM of \up_rdata_ff[27]_i_1\ : label is "soft_lutpair49"; - attribute SOFT_HLUTNM of \up_rdata_ff[29]_i_1\ : label is "soft_lutpair48"; - attribute SOFT_HLUTNM of \up_rdata_ff[2]_i_10\ : label is "soft_lutpair18"; - attribute SOFT_HLUTNM of \up_rdata_ff[2]_i_3\ : label is "soft_lutpair22"; - attribute SOFT_HLUTNM of \up_rdata_ff[2]_i_5\ : label is "soft_lutpair30"; - attribute SOFT_HLUTNM of \up_rdata_ff[2]_i_9\ : label is "soft_lutpair24"; - attribute SOFT_HLUTNM of \up_rdata_ff[30]_i_1\ : label is "soft_lutpair47"; - attribute SOFT_HLUTNM of \up_rdata_ff[31]_i_2\ : label is "soft_lutpair46"; - attribute SOFT_HLUTNM of \up_rdata_ff[3]_i_2\ : label is "soft_lutpair17"; - attribute SOFT_HLUTNM of \up_rdata_ff[3]_i_8\ : label is "soft_lutpair20"; - attribute SOFT_HLUTNM of \up_rdata_ff[5]_i_1\ : label is "soft_lutpair17"; - attribute SOFT_HLUTNM of \up_rdata_ff[5]_i_5\ : label is "soft_lutpair23"; - attribute SOFT_HLUTNM of \up_rdata_ff[7]_i_3\ : label is "soft_lutpair26"; - attribute SOFT_HLUTNM of \up_rdata_ff[8]_i_1\ : label is "soft_lutpair46"; - attribute SOFT_HLUTNM of \up_rdata_ff[9]_i_1\ : label is "soft_lutpair47"; - attribute SOFT_HLUTNM of \up_wcount[1]_i_1\ : label is "soft_lutpair21"; - attribute SOFT_HLUTNM of \up_wcount[2]_i_1\ : label is "soft_lutpair21"; -begin - Q(0) <= \^q\(0); - p_0_in <= \^p_0_in\; - s_axi_aresetn_0 <= \^s_axi_aresetn_0\; - s_axi_arready <= \^s_axi_arready\; - s_axi_awready <= \^s_axi_awready\; - s_axi_bvalid <= \^s_axi_bvalid\; - s_axi_wready <= \^s_axi_wready\; - up_axi_rvalid_int_reg_0 <= \^up_axi_rvalid_int_reg_0\; - \up_raddr_int_reg[4]_0\(1 downto 0) <= \^up_raddr_int_reg[4]_0\(1 downto 0); - up_rreq_s <= \^up_rreq_s\; - \up_waddr_int_reg[4]_0\ <= \^up_waddr_int_reg[4]_0\; - \up_wdata_int_reg[31]_0\(31 downto 0) <= \^up_wdata_int_reg[31]_0\(31 downto 0); - up_wreq_s <= \^up_wreq_s\; -level_next0_carry_i_2: unisim.vcomponents.LUT3 - generic map( - INIT => X"2A" - ) - port map ( - I0 => \^p_0_in\, - I1 => sdi_data_valid, - I2 => sdi_data_ready, - O => DI(0) - ); -\m_axis_raddr[4]_i_1__0\: unisim.vcomponents.LUT6 - generic map( - INIT => X"0000000000080000" - ) - port map ( - I0 => \m_axis_raddr[4]_i_3_n_0\, - I1 => \m_axis_raddr[4]_i_4_n_0\, - I2 => \up_rdata_ff[3]_i_2_n_0\, - I3 => up_raddr_s(13), - I4 => \m_axis_raddr_reg[0]\, - I5 => \m_axis_raddr[4]_i_5_n_0\, - O => \^p_0_in\ - ); -\m_axis_raddr[4]_i_3\: unisim.vcomponents.LUT3 - generic map( - INIT => X"40" - ) - port map ( - I0 => \^up_raddr_int_reg[4]_0\(0), - I1 => up_raddr_s(1), - I2 => up_raddr_s(3), - O => \m_axis_raddr[4]_i_3_n_0\ - ); -\m_axis_raddr[4]_i_4\: unisim.vcomponents.LUT6 - generic map( - INIT => X"0000000200000000" - ) - port map ( - I0 => \^up_rreq_s\, - I1 => up_raddr_s(7), - I2 => up_raddr_s(8), - I3 => up_raddr_s(9), - I4 => up_raddr_s(10), - I5 => \up_rdata_ff[31]_i_3_n_0\, - O => \m_axis_raddr[4]_i_4_n_0\ - ); -\m_axis_raddr[4]_i_5\: unisim.vcomponents.LUT2 - generic map( - INIT => X"7" - ) - port map ( - I0 => \^up_raddr_int_reg[4]_0\(1), - I1 => up_raddr_s(5), - O => \m_axis_raddr[4]_i_5_n_0\ - ); -offload0_cmd_wr_en_INST_0: unisim.vcomponents.LUT2 - generic map( - INIT => X"2" - ) - port map ( - I0 => offload0_cmd_wr_en_INST_0_i_1_n_0, - I1 => \^q\(0), - O => offload0_cmd_wr_en - ); -offload0_cmd_wr_en_INST_0_i_1: unisim.vcomponents.LUT6 - generic map( - INIT => X"0002000000000000" - ) - port map ( - I0 => up_waddr_s(6), - I1 => up_waddr_s(5), - I2 => up_waddr_s(4), - I3 => up_waddr_s(3), - I4 => up_waddr_s(2), - I5 => offload0_cmd_wr_en_INST_0_i_2_n_0, - O => offload0_cmd_wr_en_INST_0_i_1_n_0 - ); -offload0_cmd_wr_en_INST_0_i_2: unisim.vcomponents.LUT6 - generic map( - INIT => X"0000000000000004" - ) - port map ( - I0 => offload0_cmd_wr_en_INST_0_i_3_n_0, - I1 => \^up_wreq_s\, - I2 => up_waddr_s(1), - I3 => up_waddr_s(13), - I4 => up_waddr_s(12), - I5 => up_waddr_s(11), - O => offload0_cmd_wr_en_INST_0_i_2_n_0 - ); -offload0_cmd_wr_en_INST_0_i_3: unisim.vcomponents.LUT4 - generic map( - INIT => X"FFFE" - ) - port map ( - I0 => up_waddr_s(7), - I1 => up_waddr_s(8), - I2 => up_waddr_s(9), - I3 => up_waddr_s(10), - O => offload0_cmd_wr_en_INST_0_i_3_n_0 - ); -offload0_enable_reg_i_1: unisim.vcomponents.LUT6 - generic map( - INIT => X"EFFFFFFF20000000" - ) - port map ( - I0 => \^up_wdata_int_reg[31]_0\(0), - I1 => offload0_enable_reg_i_2_n_0, - I2 => offload0_enable_reg_i_3_n_0, - I3 => offload0_enable_reg_i_4_n_0, - I4 => offload0_mem_reset_reg_i_3_n_0, - I5 => offload0_enable, - O => \up_wdata_int_reg[0]_1\ - ); -offload0_enable_reg_i_2: unisim.vcomponents.LUT4 - generic map( - INIT => X"FFFE" - ) - port map ( - I0 => up_waddr_s(4), - I1 => up_waddr_s(3), - I2 => up_waddr_s(2), - I3 => up_waddr_s(1), - O => offload0_enable_reg_i_2_n_0 - ); -offload0_enable_reg_i_3: unisim.vcomponents.LUT2 - generic map( - INIT => X"2" - ) - port map ( - I0 => up_waddr_s(6), - I1 => up_waddr_s(5), - O => offload0_enable_reg_i_3_n_0 - ); -offload0_enable_reg_i_4: unisim.vcomponents.LUT2 - generic map( - INIT => X"2" - ) - port map ( - I0 => \^up_wreq_s\, - I1 => \^q\(0), - O => offload0_enable_reg_i_4_n_0 - ); -offload0_mem_reset_reg_i_1: unisim.vcomponents.LUT4 - generic map( - INIT => X"BF80" - ) - port map ( - I0 => \^up_wdata_int_reg[31]_0\(0), - I1 => offload0_mem_reset_reg_i_2_n_0, - I2 => offload0_mem_reset_reg_i_3_n_0, - I3 => offload0_mem_reset, - O => \up_wdata_int_reg[0]_2\ - ); -offload0_mem_reset_reg_i_2: unisim.vcomponents.LUT6 - generic map( - INIT => X"0000000002000000" - ) - port map ( - I0 => \^up_wreq_s\, - I1 => \^q\(0), - I2 => up_waddr_s(5), - I3 => up_waddr_s(6), - I4 => up_waddr_s(1), - I5 => offload0_mem_reset_reg_i_4_n_0, - O => offload0_mem_reset_reg_i_2_n_0 - ); -offload0_mem_reset_reg_i_3: unisim.vcomponents.LUT5 - generic map( - INIT => X"00000001" - ) - port map ( - I0 => \s_axis_waddr[3]_i_4_n_0\, - I1 => up_waddr_s(10), - I2 => up_waddr_s(9), - I3 => up_waddr_s(8), - I4 => up_waddr_s(7), - O => offload0_mem_reset_reg_i_3_n_0 - ); -offload0_mem_reset_reg_i_4: unisim.vcomponents.LUT3 - generic map( - INIT => X"FE" - ) - port map ( - I0 => up_waddr_s(2), - I1 => up_waddr_s(3), - I2 => up_waddr_s(4), - O => offload0_mem_reset_reg_i_4_n_0 - ); -offload0_sdo_wr_en_INST_0: unisim.vcomponents.LUT2 - generic map( - INIT => X"8" - ) - port map ( - I0 => \^q\(0), - I1 => offload0_cmd_wr_en_INST_0_i_1_n_0, - O => offload0_sdo_wr_en - ); -ram_reg_0_15_12_15_i_1: unisim.vcomponents.LUT3 - generic map( - INIT => X"20" - ) - port map ( - I0 => \s_axis_waddr_reg[0]\, - I1 => \^q\(0), - I2 => \^up_waddr_int_reg[4]_0\, - O => s_mem_write - ); -ram_reg_0_15_12_15_i_2: unisim.vcomponents.LUT6 - generic map( - INIT => X"0000000000800000" - ) - port map ( - I0 => up_waddr_s(4), - I1 => up_waddr_s(3), - I2 => \s_axis_waddr[3]_i_5_n_0\, - I3 => \s_axis_waddr[3]_i_4_n_0\, - I4 => ram_reg_0_15_12_15_i_3_n_0, - I5 => up_waddr_s(2), - O => \^up_waddr_int_reg[4]_0\ - ); -ram_reg_0_15_12_15_i_3: unisim.vcomponents.LUT2 - generic map( - INIT => X"2" - ) - port map ( - I0 => up_waddr_s(5), - I1 => up_waddr_s(6), - O => ram_reg_0_15_12_15_i_3_n_0 - ); -ram_reg_0_31_6_7_i_1: unisim.vcomponents.LUT3 - generic map( - INIT => X"80" - ) - port map ( - I0 => \s_axis_waddr_reg[0]_0\, - I1 => \^up_waddr_int_reg[4]_0\, - I2 => \^q\(0), - O => s_axis_ready_reg - ); -s_axis_ready_i_7: unisim.vcomponents.LUT3 - generic map( - INIT => X"2A" - ) - port map ( - I0 => \^p_0_in\, - I1 => sdi_data_valid, - I2 => sdi_data_ready, - O => sdi_data_valid_0(0) - ); -\s_axis_waddr[3]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"0040000000000000" - ) - port map ( - I0 => \^q\(0), - I1 => \s_axis_waddr_reg[0]\, - I2 => \s_axis_waddr[3]_i_3_n_0\, - I3 => \s_axis_waddr[3]_i_4_n_0\, - I4 => \s_axis_waddr[3]_i_5_n_0\, - I5 => \s_axis_waddr[3]_i_6_n_0\, - O => p_1_in - ); -\s_axis_waddr[3]_i_3\: unisim.vcomponents.LUT3 - generic map( - INIT => X"04" - ) - port map ( - I0 => up_waddr_s(6), - I1 => up_waddr_s(5), - I2 => up_waddr_s(2), - O => \s_axis_waddr[3]_i_3_n_0\ - ); -\s_axis_waddr[3]_i_4\: unisim.vcomponents.LUT3 - generic map( - INIT => X"FE" - ) - port map ( - I0 => up_waddr_s(11), - I1 => up_waddr_s(12), - I2 => up_waddr_s(13), - O => \s_axis_waddr[3]_i_4_n_0\ - ); -\s_axis_waddr[3]_i_5\: unisim.vcomponents.LUT6 - generic map( - INIT => X"0000000000000004" - ) - port map ( - I0 => up_waddr_s(1), - I1 => \^up_wreq_s\, - I2 => up_waddr_s(10), - I3 => up_waddr_s(9), - I4 => up_waddr_s(8), - I5 => up_waddr_s(7), - O => \s_axis_waddr[3]_i_5_n_0\ - ); -\s_axis_waddr[3]_i_6\: unisim.vcomponents.LUT2 - generic map( - INIT => X"8" - ) - port map ( - I0 => up_waddr_s(3), - I1 => up_waddr_s(4), - O => \s_axis_waddr[3]_i_6_n_0\ - ); -\s_axis_waddr[4]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"80" - ) - port map ( - I0 => \s_axis_waddr_reg[0]_0\, - I1 => \^q\(0), - I2 => \^up_waddr_int_reg[4]_0\, - O => s_axis_ready_reg_0(0) - ); -sync_id_pending_i_1: unisim.vcomponents.LUT6 - generic map( - INIT => X"FFFF7FFFFFFF0000" - ) - port map ( - I0 => sync_id_pending_i_2_n_0, - I1 => \^q\(0), - I2 => \^up_wdata_int_reg[31]_0\(3), - I3 => sync_id_pending_i_3_n_0, - I4 => sync_valid, - I5 => sync_id_pending_reg(0), - O => \up_waddr_int_reg[0]_0\ - ); -sync_id_pending_i_2: unisim.vcomponents.LUT5 - generic map( - INIT => X"00040000" - ) - port map ( - I0 => up_waddr_s(2), - I1 => up_waddr_s(5), - I2 => up_waddr_s(6), - I3 => \s_axis_waddr[3]_i_4_n_0\, - I4 => \s_axis_waddr[3]_i_5_n_0\, - O => sync_id_pending_i_2_n_0 - ); -sync_id_pending_i_3: unisim.vcomponents.LUT2 - generic map( - INIT => X"1" - ) - port map ( - I0 => up_waddr_s(4), - I1 => up_waddr_s(3), - O => sync_id_pending_i_3_n_0 - ); -up_axi_arready_int_i_1: unisim.vcomponents.LUT4 - generic map( - INIT => X"5540" - ) - port map ( - I0 => \^s_axi_arready\, - I1 => p_0_in6_in, - I2 => up_rack_ff, - I3 => up_axi_arready_int_i_2_n_0, - O => up_axi_arready_int_i_1_n_0 - ); -up_axi_arready_int_i_2: unisim.vcomponents.LUT5 - generic map( - INIT => X"80000000" - ) - port map ( - I0 => \up_rcount_reg_n_0_[0]\, - I1 => \up_rcount_reg_n_0_[1]\, - I2 => \up_rcount_reg_n_0_[2]\, - I3 => p_0_in6_in, - I4 => \up_rcount_reg_n_0_[3]\, - O => up_axi_arready_int_i_2_n_0 - ); -up_axi_arready_int_reg: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => up_axi_arready_int_i_1_n_0, - Q => \^s_axi_arready\, - R => \^s_axi_aresetn_0\ - ); -up_axi_awready_int_i_1: unisim.vcomponents.LUT1 - generic map( - INIT => X"1" - ) - port map ( - I0 => s_axi_aresetn, - O => \^s_axi_aresetn_0\ - ); -up_axi_awready_int_i_2: unisim.vcomponents.LUT2 - generic map( - INIT => X"4" - ) - port map ( - I0 => \^s_axi_awready\, - I1 => up_wack_s, - O => up_axi_awready_int_i_2_n_0 - ); -up_axi_awready_int_reg: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => up_axi_awready_int_i_2_n_0, - Q => \^s_axi_awready\, - R => \^s_axi_aresetn_0\ - ); -up_axi_bvalid_int_i_1: unisim.vcomponents.LUT4 - generic map( - INIT => X"0C88" - ) - port map ( - I0 => up_wack_d, - I1 => s_axi_aresetn, - I2 => s_axi_bready, - I3 => \^s_axi_bvalid\, - O => up_axi_bvalid_int_i_1_n_0 - ); -up_axi_bvalid_int_reg: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => up_axi_bvalid_int_i_1_n_0, - Q => \^s_axi_bvalid\, - R => '0' - ); -\up_axi_rdata_int[31]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"8F" - ) - port map ( - I0 => \^up_axi_rvalid_int_reg_0\, - I1 => s_axi_rready, - I2 => s_axi_aresetn, - O => \up_axi_rdata_int[31]_i_1_n_0\ - ); -\up_axi_rdata_int_reg[0]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => up_rack_d, - D => up_rdata_d(0), - Q => s_axi_rdata(0), - R => \up_axi_rdata_int[31]_i_1_n_0\ - ); -\up_axi_rdata_int_reg[10]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => up_rack_d, - D => up_rdata_d(10), - Q => s_axi_rdata(10), - R => \up_axi_rdata_int[31]_i_1_n_0\ - ); -\up_axi_rdata_int_reg[11]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => up_rack_d, - D => up_rdata_d(11), - Q => s_axi_rdata(11), - R => \up_axi_rdata_int[31]_i_1_n_0\ - ); -\up_axi_rdata_int_reg[12]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => up_rack_d, - D => up_rdata_d(12), - Q => s_axi_rdata(12), - R => \up_axi_rdata_int[31]_i_1_n_0\ - ); -\up_axi_rdata_int_reg[13]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => up_rack_d, - D => up_rdata_d(13), - Q => s_axi_rdata(13), - R => \up_axi_rdata_int[31]_i_1_n_0\ - ); -\up_axi_rdata_int_reg[14]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => up_rack_d, - D => up_rdata_d(14), - Q => s_axi_rdata(14), - R => \up_axi_rdata_int[31]_i_1_n_0\ - ); -\up_axi_rdata_int_reg[15]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => up_rack_d, - D => up_rdata_d(15), - Q => s_axi_rdata(15), - R => \up_axi_rdata_int[31]_i_1_n_0\ - ); -\up_axi_rdata_int_reg[16]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => up_rack_d, - D => up_rdata_d(16), - Q => s_axi_rdata(16), - R => \up_axi_rdata_int[31]_i_1_n_0\ - ); -\up_axi_rdata_int_reg[17]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => up_rack_d, - D => up_rdata_d(17), - Q => s_axi_rdata(17), - R => \up_axi_rdata_int[31]_i_1_n_0\ - ); -\up_axi_rdata_int_reg[18]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => up_rack_d, - D => up_rdata_d(18), - Q => s_axi_rdata(18), - R => \up_axi_rdata_int[31]_i_1_n_0\ - ); -\up_axi_rdata_int_reg[19]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => up_rack_d, - D => up_rdata_d(19), - Q => s_axi_rdata(19), - R => \up_axi_rdata_int[31]_i_1_n_0\ - ); -\up_axi_rdata_int_reg[1]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => up_rack_d, - D => up_rdata_d(1), - Q => s_axi_rdata(1), - R => \up_axi_rdata_int[31]_i_1_n_0\ - ); -\up_axi_rdata_int_reg[20]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => up_rack_d, - D => up_rdata_d(20), - Q => s_axi_rdata(20), - R => \up_axi_rdata_int[31]_i_1_n_0\ - ); -\up_axi_rdata_int_reg[21]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => up_rack_d, - D => up_rdata_d(21), - Q => s_axi_rdata(21), - R => \up_axi_rdata_int[31]_i_1_n_0\ - ); -\up_axi_rdata_int_reg[22]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => up_rack_d, - D => up_rdata_d(22), - Q => s_axi_rdata(22), - R => \up_axi_rdata_int[31]_i_1_n_0\ - ); -\up_axi_rdata_int_reg[23]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => up_rack_d, - D => up_rdata_d(23), - Q => s_axi_rdata(23), - R => \up_axi_rdata_int[31]_i_1_n_0\ - ); -\up_axi_rdata_int_reg[24]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => up_rack_d, - D => up_rdata_d(24), - Q => s_axi_rdata(24), - R => \up_axi_rdata_int[31]_i_1_n_0\ - ); -\up_axi_rdata_int_reg[25]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => up_rack_d, - D => up_rdata_d(25), - Q => s_axi_rdata(25), - R => \up_axi_rdata_int[31]_i_1_n_0\ - ); -\up_axi_rdata_int_reg[26]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => up_rack_d, - D => up_rdata_d(26), - Q => s_axi_rdata(26), - R => \up_axi_rdata_int[31]_i_1_n_0\ - ); -\up_axi_rdata_int_reg[27]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => up_rack_d, - D => up_rdata_d(27), - Q => s_axi_rdata(27), - R => \up_axi_rdata_int[31]_i_1_n_0\ - ); -\up_axi_rdata_int_reg[28]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => up_rack_d, - D => up_rdata_d(28), - Q => s_axi_rdata(28), - R => \up_axi_rdata_int[31]_i_1_n_0\ - ); -\up_axi_rdata_int_reg[29]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => up_rack_d, - D => up_rdata_d(29), - Q => s_axi_rdata(29), - R => \up_axi_rdata_int[31]_i_1_n_0\ - ); -\up_axi_rdata_int_reg[2]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => up_rack_d, - D => up_rdata_d(2), - Q => s_axi_rdata(2), - R => \up_axi_rdata_int[31]_i_1_n_0\ - ); -\up_axi_rdata_int_reg[30]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => up_rack_d, - D => up_rdata_d(30), - Q => s_axi_rdata(30), - R => \up_axi_rdata_int[31]_i_1_n_0\ - ); -\up_axi_rdata_int_reg[31]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => up_rack_d, - D => up_rdata_d(31), - Q => s_axi_rdata(31), - R => \up_axi_rdata_int[31]_i_1_n_0\ - ); -\up_axi_rdata_int_reg[3]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => up_rack_d, - D => up_rdata_d(3), - Q => s_axi_rdata(3), - R => \up_axi_rdata_int[31]_i_1_n_0\ - ); -\up_axi_rdata_int_reg[4]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => up_rack_d, - D => up_rdata_d(4), - Q => s_axi_rdata(4), - R => \up_axi_rdata_int[31]_i_1_n_0\ - ); -\up_axi_rdata_int_reg[5]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => up_rack_d, - D => up_rdata_d(5), - Q => s_axi_rdata(5), - R => \up_axi_rdata_int[31]_i_1_n_0\ - ); -\up_axi_rdata_int_reg[6]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => up_rack_d, - D => up_rdata_d(6), - Q => s_axi_rdata(6), - R => \up_axi_rdata_int[31]_i_1_n_0\ - ); -\up_axi_rdata_int_reg[7]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => up_rack_d, - D => up_rdata_d(7), - Q => s_axi_rdata(7), - R => \up_axi_rdata_int[31]_i_1_n_0\ - ); -\up_axi_rdata_int_reg[8]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => up_rack_d, - D => up_rdata_d(8), - Q => s_axi_rdata(8), - R => \up_axi_rdata_int[31]_i_1_n_0\ - ); -\up_axi_rdata_int_reg[9]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => up_rack_d, - D => up_rdata_d(9), - Q => s_axi_rdata(9), - R => \up_axi_rdata_int[31]_i_1_n_0\ - ); -up_axi_rvalid_int_i_1: unisim.vcomponents.LUT4 - generic map( - INIT => X"0C88" - ) - port map ( - I0 => up_rack_d, - I1 => s_axi_aresetn, - I2 => s_axi_rready, - I3 => \^up_axi_rvalid_int_reg_0\, - O => up_axi_rvalid_int_i_1_n_0 - ); -up_axi_rvalid_int_reg: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => up_axi_rvalid_int_i_1_n_0, - Q => \^up_axi_rvalid_int_reg_0\, - R => '0' - ); -up_axi_wready_int_i_1: unisim.vcomponents.LUT2 - generic map( - INIT => X"4" - ) - port map ( - I0 => \^s_axi_wready\, - I1 => up_wack_s, - O => up_axi_wready_int_i_1_n_0 - ); -up_axi_wready_int_reg: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => up_axi_wready_int_i_1_n_0, - Q => \^s_axi_wready\, - R => \^s_axi_aresetn_0\ - ); -\up_irq_mask[3]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"0010000000000000" - ) - port map ( - I0 => offload0_enable_reg_i_2_n_0, - I1 => up_waddr_s(6), - I2 => up_waddr_s(5), - I3 => \^q\(0), - I4 => \^up_wreq_s\, - I5 => offload0_mem_reset_reg_i_3_n_0, - O => E(0) - ); -up_rack_d_i_1: unisim.vcomponents.LUT6 - generic map( - INIT => X"FFFF800000000000" - ) - port map ( - I0 => \up_rcount_reg_n_0_[3]\, - I1 => \up_rcount_reg_n_0_[2]\, - I2 => \up_rcount_reg_n_0_[1]\, - I3 => \up_rcount_reg_n_0_[0]\, - I4 => up_rack_ff, - I5 => p_0_in6_in, - O => up_rack_s_1 - ); -up_rack_d_reg: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => up_rack_s_1, - Q => up_rack_d, - R => \^s_axi_aresetn_0\ - ); -\up_raddr_int[13]_i_1\: unisim.vcomponents.LUT1 - generic map( - INIT => X"1" - ) - port map ( - I0 => up_rsel_reg_n_0, - O => p_1_in_0 - ); -\up_raddr_int_reg[0]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => p_1_in_0, - D => s_axi_araddr(0), - Q => up_raddr_s(0), - R => \^s_axi_aresetn_0\ - ); -\up_raddr_int_reg[10]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => p_1_in_0, - D => s_axi_araddr(10), - Q => up_raddr_s(10), - R => \^s_axi_aresetn_0\ - ); -\up_raddr_int_reg[11]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => p_1_in_0, - D => s_axi_araddr(11), - Q => up_raddr_s(11), - R => \^s_axi_aresetn_0\ - ); -\up_raddr_int_reg[12]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => p_1_in_0, - D => s_axi_araddr(12), - Q => up_raddr_s(12), - R => \^s_axi_aresetn_0\ - ); -\up_raddr_int_reg[13]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => p_1_in_0, - D => s_axi_araddr(13), - Q => up_raddr_s(13), - R => \^s_axi_aresetn_0\ - ); -\up_raddr_int_reg[1]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => p_1_in_0, - D => s_axi_araddr(1), - Q => up_raddr_s(1), - R => \^s_axi_aresetn_0\ - ); -\up_raddr_int_reg[2]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => p_1_in_0, - D => s_axi_araddr(2), - Q => \^up_raddr_int_reg[4]_0\(0), - R => \^s_axi_aresetn_0\ - ); -\up_raddr_int_reg[3]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => p_1_in_0, - D => s_axi_araddr(3), - Q => up_raddr_s(3), - R => \^s_axi_aresetn_0\ - ); -\up_raddr_int_reg[4]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => p_1_in_0, - D => s_axi_araddr(4), - Q => \^up_raddr_int_reg[4]_0\(1), - R => \^s_axi_aresetn_0\ - ); -\up_raddr_int_reg[5]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => p_1_in_0, - D => s_axi_araddr(5), - Q => up_raddr_s(5), - R => \^s_axi_aresetn_0\ - ); -\up_raddr_int_reg[6]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => p_1_in_0, - D => s_axi_araddr(6), - Q => up_raddr_s(6), - R => \^s_axi_aresetn_0\ - ); -\up_raddr_int_reg[7]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => p_1_in_0, - D => s_axi_araddr(7), - Q => up_raddr_s(7), - R => \^s_axi_aresetn_0\ - ); -\up_raddr_int_reg[8]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => p_1_in_0, - D => s_axi_araddr(8), - Q => up_raddr_s(8), - R => \^s_axi_aresetn_0\ - ); -\up_raddr_int_reg[9]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => p_1_in_0, - D => s_axi_araddr(9), - Q => up_raddr_s(9), - R => \^s_axi_aresetn_0\ - ); -\up_rcount[0]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"04" - ) - port map ( - I0 => up_rack_ff, - I1 => p_0_in6_in, - I2 => \up_rcount_reg_n_0_[0]\, - O => \up_rcount[0]_i_1_n_0\ - ); -\up_rcount[1]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0060" - ) - port map ( - I0 => \up_rcount_reg_n_0_[0]\, - I1 => \up_rcount_reg_n_0_[1]\, - I2 => p_0_in6_in, - I3 => up_rack_ff, - O => \up_rcount[1]_i_1_n_0\ - ); -\up_rcount[2]_i_1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"00007800" - ) - port map ( - I0 => \up_rcount_reg_n_0_[0]\, - I1 => \up_rcount_reg_n_0_[1]\, - I2 => \up_rcount_reg_n_0_[2]\, - I3 => p_0_in6_in, - I4 => up_rack_ff, - O => \up_rcount[2]_i_1_n_0\ - ); -\up_rcount[3]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"000000007F008000" - ) - port map ( - I0 => \up_rcount_reg_n_0_[0]\, - I1 => \up_rcount_reg_n_0_[1]\, - I2 => \up_rcount_reg_n_0_[2]\, - I3 => p_0_in6_in, - I4 => \up_rcount_reg_n_0_[3]\, - I5 => up_rack_ff, - O => \up_rcount[3]_i_1_n_0\ - ); -\up_rcount[4]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"FE" - ) - port map ( - I0 => \^up_rreq_s\, - I1 => p_0_in6_in, - I2 => up_rack_s, - O => \up_rcount[4]_i_1_n_0\ - ); -\up_rcount[4]_i_2\: unisim.vcomponents.LUT6 - generic map( - INIT => X"1F5F5F5F5F5F5F5F" - ) - port map ( - I0 => up_rack_ff, - I1 => \up_rcount_reg_n_0_[3]\, - I2 => p_0_in6_in, - I3 => \up_rcount_reg_n_0_[2]\, - I4 => \up_rcount_reg_n_0_[1]\, - I5 => \up_rcount_reg_n_0_[0]\, - O => \up_rcount[4]_i_2_n_0\ - ); -\up_rcount[4]_i_3\: unisim.vcomponents.LUT6 - generic map( - INIT => X"E0A0A0A0A0A0A0A0" - ) - port map ( - I0 => up_rack_ff, - I1 => \up_rcount_reg_n_0_[3]\, - I2 => p_0_in6_in, - I3 => \up_rcount_reg_n_0_[2]\, - I4 => \up_rcount_reg_n_0_[1]\, - I5 => \up_rcount_reg_n_0_[0]\, - O => up_rack_s - ); -\up_rcount_reg[0]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => \up_rcount[4]_i_1_n_0\, - D => \up_rcount[0]_i_1_n_0\, - Q => \up_rcount_reg_n_0_[0]\, - R => \^s_axi_aresetn_0\ - ); -\up_rcount_reg[1]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => \up_rcount[4]_i_1_n_0\, - D => \up_rcount[1]_i_1_n_0\, - Q => \up_rcount_reg_n_0_[1]\, - R => \^s_axi_aresetn_0\ - ); -\up_rcount_reg[2]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => \up_rcount[4]_i_1_n_0\, - D => \up_rcount[2]_i_1_n_0\, - Q => \up_rcount_reg_n_0_[2]\, - R => \^s_axi_aresetn_0\ - ); -\up_rcount_reg[3]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => \up_rcount[4]_i_1_n_0\, - D => \up_rcount[3]_i_1_n_0\, - Q => \up_rcount_reg_n_0_[3]\, - R => \^s_axi_aresetn_0\ - ); -\up_rcount_reg[4]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => \up_rcount[4]_i_1_n_0\, - D => \up_rcount[4]_i_2_n_0\, - Q => p_0_in6_in, - R => \^s_axi_aresetn_0\ - ); -\up_rdata_d[0]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"8" - ) - port map ( - I0 => up_rdata_ff(0), - I1 => s_axi_aresetn, - O => \up_rdata_d[0]_i_1_n_0\ - ); -\up_rdata_d[10]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"8" - ) - port map ( - I0 => up_rdata_ff(10), - I1 => s_axi_aresetn, - O => \up_rdata_d[10]_i_1_n_0\ - ); -\up_rdata_d[11]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"8" - ) - port map ( - I0 => up_rdata_ff(11), - I1 => s_axi_aresetn, - O => \up_rdata_d[11]_i_1_n_0\ - ); -\up_rdata_d[12]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"8" - ) - port map ( - I0 => up_rdata_ff(12), - I1 => s_axi_aresetn, - O => \up_rdata_d[12]_i_1_n_0\ - ); -\up_rdata_d[14]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"8" - ) - port map ( - I0 => up_rdata_ff(14), - I1 => s_axi_aresetn, - O => \up_rdata_d[14]_i_1_n_0\ - ); -\up_rdata_d[15]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"8" - ) - port map ( - I0 => up_rdata_ff(15), - I1 => s_axi_aresetn, - O => \up_rdata_d[15]_i_1_n_0\ - ); -\up_rdata_d[16]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"8" - ) - port map ( - I0 => up_rdata_ff(16), - I1 => s_axi_aresetn, - O => \up_rdata_d[16]_i_1_n_0\ - ); -\up_rdata_d[18]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"8" - ) - port map ( - I0 => up_rdata_ff(18), - I1 => s_axi_aresetn, - O => \up_rdata_d[18]_i_1_n_0\ - ); -\up_rdata_d[19]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"8" - ) - port map ( - I0 => up_rdata_ff(19), - I1 => s_axi_aresetn, - O => \up_rdata_d[19]_i_1_n_0\ - ); -\up_rdata_d[21]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"8" - ) - port map ( - I0 => up_rdata_ff(21), - I1 => s_axi_aresetn, - O => \up_rdata_d[21]_i_1_n_0\ - ); -\up_rdata_d[23]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"8" - ) - port map ( - I0 => up_rdata_ff(23), - I1 => s_axi_aresetn, - O => \up_rdata_d[23]_i_1_n_0\ - ); -\up_rdata_d[25]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"8" - ) - port map ( - I0 => up_rdata_ff(25), - I1 => s_axi_aresetn, - O => \up_rdata_d[25]_i_1_n_0\ - ); -\up_rdata_d[26]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"8" - ) - port map ( - I0 => up_rdata_ff(26), - I1 => s_axi_aresetn, - O => \up_rdata_d[26]_i_1_n_0\ - ); -\up_rdata_d[27]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"8" - ) - port map ( - I0 => up_rdata_ff(27), - I1 => s_axi_aresetn, - O => \up_rdata_d[27]_i_1_n_0\ - ); -\up_rdata_d[28]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"8" - ) - port map ( - I0 => up_rdata_ff(28), - I1 => s_axi_aresetn, - O => \up_rdata_d[28]_i_1_n_0\ - ); -\up_rdata_d[29]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"80000000FFFFFFFF" - ) - port map ( - I0 => \up_rcount_reg_n_0_[3]\, - I1 => p_0_in6_in, - I2 => \up_rcount_reg_n_0_[2]\, - I3 => \up_rcount_reg_n_0_[1]\, - I4 => \up_rcount_reg_n_0_[0]\, - I5 => s_axi_aresetn, - O => \up_rdata_d[29]_i_1_n_0\ - ); -\up_rdata_d[2]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"8" - ) - port map ( - I0 => up_rdata_ff(2), - I1 => s_axi_aresetn, - O => \up_rdata_d[2]_i_1_n_0\ - ); -\up_rdata_d[30]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"8" - ) - port map ( - I0 => up_rdata_ff(30), - I1 => s_axi_aresetn, - O => \up_rdata_d[30]_i_1_n_0\ - ); -\up_rdata_d[31]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"8000000000000000" - ) - port map ( - I0 => \up_rcount_reg_n_0_[3]\, - I1 => p_0_in6_in, - I2 => \up_rcount_reg_n_0_[2]\, - I3 => \up_rcount_reg_n_0_[1]\, - I4 => \up_rcount_reg_n_0_[0]\, - I5 => s_axi_aresetn, - O => \up_rdata_d[31]_i_1_n_0\ - ); -\up_rdata_d[31]_i_2\: unisim.vcomponents.LUT2 - generic map( - INIT => X"8" - ) - port map ( - I0 => up_rdata_ff(31), - I1 => s_axi_aresetn, - O => \up_rdata_d[31]_i_2_n_0\ - ); -\up_rdata_d[3]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"8" - ) - port map ( - I0 => up_rdata_ff(3), - I1 => s_axi_aresetn, - O => \up_rdata_d[3]_i_1_n_0\ - ); -\up_rdata_d[5]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"8" - ) - port map ( - I0 => up_rdata_ff(5), - I1 => s_axi_aresetn, - O => \up_rdata_d[5]_i_1_n_0\ - ); -\up_rdata_d[7]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"8" - ) - port map ( - I0 => up_rdata_ff(7), - I1 => s_axi_aresetn, - O => \up_rdata_d[7]_i_1_n_0\ - ); -\up_rdata_d[9]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"8" - ) - port map ( - I0 => up_rdata_ff(9), - I1 => s_axi_aresetn, - O => \up_rdata_d[9]_i_1_n_0\ - ); -\up_rdata_d_reg[0]\: unisim.vcomponents.FDSE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => \up_rdata_d[0]_i_1_n_0\, - Q => up_rdata_d(0), - S => \up_rdata_d[31]_i_1_n_0\ - ); -\up_rdata_d_reg[10]\: unisim.vcomponents.FDSE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => \up_rdata_d[10]_i_1_n_0\, - Q => up_rdata_d(10), - S => \up_rdata_d[31]_i_1_n_0\ - ); -\up_rdata_d_reg[11]\: unisim.vcomponents.FDSE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => \up_rdata_d[11]_i_1_n_0\, - Q => up_rdata_d(11), - S => \up_rdata_d[31]_i_1_n_0\ - ); -\up_rdata_d_reg[12]\: unisim.vcomponents.FDSE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => \up_rdata_d[12]_i_1_n_0\, - Q => up_rdata_d(12), - S => \up_rdata_d[31]_i_1_n_0\ - ); -\up_rdata_d_reg[13]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => up_rdata_ff(13), - Q => up_rdata_d(13), - R => \up_rdata_d[29]_i_1_n_0\ - ); -\up_rdata_d_reg[14]\: unisim.vcomponents.FDSE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => \up_rdata_d[14]_i_1_n_0\, - Q => up_rdata_d(14), - S => \up_rdata_d[31]_i_1_n_0\ - ); -\up_rdata_d_reg[15]\: unisim.vcomponents.FDSE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => \up_rdata_d[15]_i_1_n_0\, - Q => up_rdata_d(15), - S => \up_rdata_d[31]_i_1_n_0\ - ); -\up_rdata_d_reg[16]\: unisim.vcomponents.FDSE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => \up_rdata_d[16]_i_1_n_0\, - Q => up_rdata_d(16), - S => \up_rdata_d[31]_i_1_n_0\ - ); -\up_rdata_d_reg[17]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => up_rdata_ff(17), - Q => up_rdata_d(17), - R => \up_rdata_d[29]_i_1_n_0\ - ); -\up_rdata_d_reg[18]\: unisim.vcomponents.FDSE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => \up_rdata_d[18]_i_1_n_0\, - Q => up_rdata_d(18), - S => \up_rdata_d[31]_i_1_n_0\ - ); -\up_rdata_d_reg[19]\: unisim.vcomponents.FDSE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => \up_rdata_d[19]_i_1_n_0\, - Q => up_rdata_d(19), - S => \up_rdata_d[31]_i_1_n_0\ - ); -\up_rdata_d_reg[1]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => up_rdata_ff(1), - Q => up_rdata_d(1), - R => \up_rdata_d[29]_i_1_n_0\ - ); -\up_rdata_d_reg[20]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => up_rdata_ff(20), - Q => up_rdata_d(20), - R => \up_rdata_d[29]_i_1_n_0\ - ); -\up_rdata_d_reg[21]\: unisim.vcomponents.FDSE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => \up_rdata_d[21]_i_1_n_0\, - Q => up_rdata_d(21), - S => \up_rdata_d[31]_i_1_n_0\ - ); -\up_rdata_d_reg[22]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => up_rdata_ff(22), - Q => up_rdata_d(22), - R => \up_rdata_d[29]_i_1_n_0\ - ); -\up_rdata_d_reg[23]\: unisim.vcomponents.FDSE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => \up_rdata_d[23]_i_1_n_0\, - Q => up_rdata_d(23), - S => \up_rdata_d[31]_i_1_n_0\ - ); -\up_rdata_d_reg[24]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => up_rdata_ff(24), - Q => up_rdata_d(24), - R => \up_rdata_d[29]_i_1_n_0\ - ); -\up_rdata_d_reg[25]\: unisim.vcomponents.FDSE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => \up_rdata_d[25]_i_1_n_0\, - Q => up_rdata_d(25), - S => \up_rdata_d[31]_i_1_n_0\ - ); -\up_rdata_d_reg[26]\: unisim.vcomponents.FDSE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => \up_rdata_d[26]_i_1_n_0\, - Q => up_rdata_d(26), - S => \up_rdata_d[31]_i_1_n_0\ - ); -\up_rdata_d_reg[27]\: unisim.vcomponents.FDSE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => \up_rdata_d[27]_i_1_n_0\, - Q => up_rdata_d(27), - S => \up_rdata_d[31]_i_1_n_0\ - ); -\up_rdata_d_reg[28]\: unisim.vcomponents.FDSE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => \up_rdata_d[28]_i_1_n_0\, - Q => up_rdata_d(28), - S => \up_rdata_d[31]_i_1_n_0\ - ); -\up_rdata_d_reg[29]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => up_rdata_ff(29), - Q => up_rdata_d(29), - R => \up_rdata_d[29]_i_1_n_0\ - ); -\up_rdata_d_reg[2]\: unisim.vcomponents.FDSE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => \up_rdata_d[2]_i_1_n_0\, - Q => up_rdata_d(2), - S => \up_rdata_d[31]_i_1_n_0\ - ); -\up_rdata_d_reg[30]\: unisim.vcomponents.FDSE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => \up_rdata_d[30]_i_1_n_0\, - Q => up_rdata_d(30), - S => \up_rdata_d[31]_i_1_n_0\ - ); -\up_rdata_d_reg[31]\: unisim.vcomponents.FDSE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => \up_rdata_d[31]_i_2_n_0\, - Q => up_rdata_d(31), - S => \up_rdata_d[31]_i_1_n_0\ - ); -\up_rdata_d_reg[3]\: unisim.vcomponents.FDSE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => \up_rdata_d[3]_i_1_n_0\, - Q => up_rdata_d(3), - S => \up_rdata_d[31]_i_1_n_0\ - ); -\up_rdata_d_reg[4]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => up_rdata_ff(4), - Q => up_rdata_d(4), - R => \up_rdata_d[29]_i_1_n_0\ - ); -\up_rdata_d_reg[5]\: unisim.vcomponents.FDSE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => \up_rdata_d[5]_i_1_n_0\, - Q => up_rdata_d(5), - S => \up_rdata_d[31]_i_1_n_0\ - ); -\up_rdata_d_reg[6]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => up_rdata_ff(6), - Q => up_rdata_d(6), - R => \up_rdata_d[29]_i_1_n_0\ - ); -\up_rdata_d_reg[7]\: unisim.vcomponents.FDSE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => \up_rdata_d[7]_i_1_n_0\, - Q => up_rdata_d(7), - S => \up_rdata_d[31]_i_1_n_0\ - ); -\up_rdata_d_reg[8]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => up_rdata_ff(8), - Q => up_rdata_d(8), - R => \up_rdata_d[29]_i_1_n_0\ - ); -\up_rdata_d_reg[9]\: unisim.vcomponents.FDSE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => \up_rdata_d[9]_i_1_n_0\, - Q => up_rdata_d(9), - S => \up_rdata_d[31]_i_1_n_0\ - ); -\up_rdata_ff[0]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"FFFFFFFFABABABAA" - ) - port map ( - I0 => \up_rdata_ff[0]_i_2_n_0\, - I1 => up_raddr_s(3), - I2 => up_raddr_s(0), - I3 => \up_rdata_ff[0]_i_3_n_0\, - I4 => \up_rdata_ff[0]_i_4_n_0\, - I5 => \up_rdata_ff[0]_i_5_n_0\, - O => \up_raddr_int_reg[3]_3\ - ); -\up_rdata_ff[0]_i_10\: unisim.vcomponents.LUT5 - generic map( - INIT => X"12020000" - ) - port map ( - I0 => up_raddr_s(5), - I1 => up_raddr_s(1), - I2 => up_raddr_s(6), - I3 => offload0_enabled, - I4 => up_raddr_s(0), - O => \up_rdata_ff[0]_i_10_n_0\ - ); -\up_rdata_ff[0]_i_11\: unisim.vcomponents.LUT5 - generic map( - INIT => X"8888F555" - ) - port map ( - I0 => up_raddr_s(5), - I1 => \up_rdata_ff_reg[7]\(0), - I2 => up_irq_source(0), - I3 => \up_rdata_ff[3]_i_3_0\(0), - I4 => \^up_raddr_int_reg[4]_0\(1), - O => \up_rdata_ff[0]_i_11_n_0\ - ); -\up_rdata_ff[0]_i_12\: unisim.vcomponents.LUT5 - generic map( - INIT => X"44400040" - ) - port map ( - I0 => up_raddr_s(6), - I1 => \^up_raddr_int_reg[4]_0\(0), - I2 => \up_rdata_ff[0]_i_8_0\(0), - I3 => up_raddr_s(1), - I4 => \up_rdata_ff_reg[5]\(0), - O => \up_rdata_ff[0]_i_12_n_0\ - ); -\up_rdata_ff[0]_i_2\: unisim.vcomponents.LUT5 - generic map( - INIT => X"03100000" - ) - port map ( - I0 => up_raddr_s(0), - I1 => \up_rdata_ff[0]_i_6_n_0\, - I2 => \^up_raddr_int_reg[4]_0\(0), - I3 => up_raddr_s(1), - I4 => up_raddr_s(3), - O => \up_rdata_ff[0]_i_2_n_0\ - ); -\up_rdata_ff[0]_i_3\: unisim.vcomponents.LUT6 - generic map( - INIT => X"00000022000000F2" - ) - port map ( - I0 => offload0_enable, - I1 => \up_rdata_ff[16]_i_3_n_0\, - I2 => \up_rdata_ff[0]_i_7_n_0\, - I3 => \^up_raddr_int_reg[4]_0\(0), - I4 => up_raddr_s(1), - I5 => up_raddr_s(6), - O => \up_rdata_ff[0]_i_3_n_0\ - ); -\up_rdata_ff[0]_i_4\: unisim.vcomponents.LUT6 - generic map( - INIT => X"AAAAAEAAAAAAAAAA" - ) - port map ( - I0 => \up_rdata_ff[0]_i_8_n_0\, - I1 => up_irq_source(0), - I2 => up_raddr_s(6), - I3 => up_raddr_s(5), - I4 => \^up_raddr_int_reg[4]_0\(1), - I5 => \up_rdata_ff[0]_i_9_n_0\, - O => \up_rdata_ff[0]_i_4_n_0\ - ); -\up_rdata_ff[0]_i_5\: unisim.vcomponents.LUT6 - generic map( - INIT => X"000800A800080008" - ) - port map ( - I0 => \up_rdata_ff[0]_i_10_n_0\, - I1 => \up_rdata_ff[0]_i_11_n_0\, - I2 => \^up_raddr_int_reg[4]_0\(0), - I3 => up_raddr_s(3), - I4 => \m_axis_raddr[4]_i_5_n_0\, - I5 => \up_rdata_ff_reg[5]_0\(0), - O => \up_rdata_ff[0]_i_5_n_0\ - ); -\up_rdata_ff[0]_i_6\: unisim.vcomponents.LUT4 - generic map( - INIT => X"DFFF" - ) - port map ( - I0 => m_axis_data(0), - I1 => up_raddr_s(6), - I2 => up_raddr_s(5), - I3 => \^up_raddr_int_reg[4]_0\(1), - O => \up_rdata_ff[0]_i_6_n_0\ - ); -\up_rdata_ff[0]_i_7\: unisim.vcomponents.LUT5 - generic map( - INIT => X"CAFFCA0F" - ) - port map ( - I0 => \up_rdata_ff[3]_i_3_0\(0), - I1 => \up_rdata_ff_reg[7]_0\(0), - I2 => \^up_raddr_int_reg[4]_0\(1), - I3 => up_raddr_s(5), - I4 => up_sw_reset, - O => \up_rdata_ff[0]_i_7_n_0\ - ); -\up_rdata_ff[0]_i_8\: unisim.vcomponents.LUT6 - generic map( - INIT => X"8080808080838080" - ) - port map ( - I0 => \up_rdata_ff[0]_i_12_n_0\, - I1 => \^up_raddr_int_reg[4]_0\(1), - I2 => up_raddr_s(5), - I3 => \^up_raddr_int_reg[4]_0\(0), - I4 => \up_rdata_ff_reg[31]\(0), - I5 => up_raddr_s(6), - O => \up_rdata_ff[0]_i_8_n_0\ - ); -\up_rdata_ff[0]_i_9\: unisim.vcomponents.LUT2 - generic map( - INIT => X"2" - ) - port map ( - I0 => up_raddr_s(1), - I1 => \^up_raddr_int_reg[4]_0\(0), - O => \up_rdata_ff[0]_i_9_n_0\ - ); -\up_rdata_ff[10]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"8" - ) - port map ( - I0 => \up_rdata_ff[31]_i_4_n_0\, - I1 => \up_rdata_ff_reg[31]\(10), - O => \up_scratch_reg[10]\ - ); -\up_rdata_ff[11]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"8" - ) - port map ( - I0 => \up_rdata_ff[31]_i_4_n_0\, - I1 => \up_rdata_ff_reg[31]\(11), - O => \up_scratch_reg[11]\ - ); -\up_rdata_ff[12]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"8" - ) - port map ( - I0 => \up_rdata_ff[31]_i_4_n_0\, - I1 => \up_rdata_ff_reg[31]\(12), - O => \up_scratch_reg[12]\ - ); -\up_rdata_ff[13]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"8" - ) - port map ( - I0 => \up_rdata_ff[31]_i_4_n_0\, - I1 => \up_rdata_ff_reg[31]\(13), - O => \up_scratch_reg[13]\ - ); -\up_rdata_ff[14]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"8" - ) - port map ( - I0 => \up_rdata_ff[31]_i_4_n_0\, - I1 => \up_rdata_ff_reg[31]\(14), - O => \up_scratch_reg[14]\ - ); -\up_rdata_ff[15]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"8" - ) - port map ( - I0 => \up_rdata_ff[31]_i_4_n_0\, - I1 => \up_rdata_ff_reg[31]\(15), - O => \up_scratch_reg[15]\ - ); -\up_rdata_ff[16]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"0101000101000001" - ) - port map ( - I0 => \up_rdata_ff[16]_i_2_n_0\, - I1 => \up_rdata_ff[16]_i_3_n_0\, - I2 => up_raddr_s(6), - I3 => up_raddr_s(0), - I4 => up_raddr_s(1), - I5 => \up_rdata_ff_reg[31]\(16), - O => \up_raddr_int_reg[6]_0\ - ); -\up_rdata_ff[16]_i_2\: unisim.vcomponents.LUT2 - generic map( - INIT => X"E" - ) - port map ( - I0 => up_raddr_s(3), - I1 => \^up_raddr_int_reg[4]_0\(0), - O => \up_rdata_ff[16]_i_2_n_0\ - ); -\up_rdata_ff[16]_i_3\: unisim.vcomponents.LUT2 - generic map( - INIT => X"E" - ) - port map ( - I0 => \^up_raddr_int_reg[4]_0\(1), - I1 => up_raddr_s(5), - O => \up_rdata_ff[16]_i_3_n_0\ - ); -\up_rdata_ff[17]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"8" - ) - port map ( - I0 => \up_rdata_ff[31]_i_4_n_0\, - I1 => \up_rdata_ff_reg[31]\(17), - O => \up_scratch_reg[17]\ - ); -\up_rdata_ff[18]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"8" - ) - port map ( - I0 => \up_rdata_ff[31]_i_4_n_0\, - I1 => \up_rdata_ff_reg[31]\(18), - O => \up_scratch_reg[18]\ - ); -\up_rdata_ff[19]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"8" - ) - port map ( - I0 => \up_rdata_ff[31]_i_4_n_0\, - I1 => \up_rdata_ff_reg[31]\(19), - O => \up_scratch_reg[19]\ - ); -\up_rdata_ff[1]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"02020000FF000000" - ) - port map ( - I0 => \up_rdata_ff_reg[1]\, - I1 => \up_rdata_ff[2]_i_3_n_0\, - I2 => up_raddr_s(3), - I3 => \up_rdata_ff[1]_i_3_n_0\, - I4 => \up_rdata_ff[1]_i_4_n_0\, - I5 => up_raddr_s(0), - O => \up_raddr_int_reg[3]_1\ - ); -\up_rdata_ff[1]_i_3\: unisim.vcomponents.LUT6 - generic map( - INIT => X"EFEEEEEEEEEEEEEE" - ) - port map ( - I0 => \up_rdata_ff[1]_i_5_n_0\, - I1 => \up_rdata_ff[1]_i_6_n_0\, - I2 => \m_axis_raddr[4]_i_5_n_0\, - I3 => up_raddr_s(1), - I4 => \up_rdata_ff[2]_i_9_n_0\, - I5 => \up_rdata_ff_reg[5]\(1), - O => \up_rdata_ff[1]_i_3_n_0\ - ); -\up_rdata_ff[1]_i_4\: unisim.vcomponents.LUT3 - generic map( - INIT => X"32" - ) - port map ( - I0 => up_raddr_s(5), - I1 => up_raddr_s(6), - I2 => \up_rdata_ff_reg[31]\(1), - O => \up_rdata_ff[1]_i_4_n_0\ - ); -\up_rdata_ff[1]_i_5\: unisim.vcomponents.LUT6 - generic map( - INIT => X"00000000FFFF2230" - ) - port map ( - I0 => \up_rdata_ff_reg[7]_0\(1), - I1 => \up_rdata_ff[16]_i_2_n_0\, - I2 => \up_rdata_ff[3]_i_3_0\(1), - I3 => \^up_raddr_int_reg[4]_0\(1), - I4 => \up_rdata_ff[1]_i_7_n_0\, - I5 => \up_rdata_ff[2]_i_3_n_0\, - O => \up_rdata_ff[1]_i_5_n_0\ - ); -\up_rdata_ff[1]_i_6\: unisim.vcomponents.LUT6 - generic map( - INIT => X"8280020002020202" - ) - port map ( - I0 => \up_rdata_ff[0]_i_9_n_0\, - I1 => \^up_raddr_int_reg[4]_0\(1), - I2 => up_raddr_s(3), - I3 => up_irq_source(1), - I4 => m_axis_data(1), - I5 => up_raddr_s(5), - O => \up_rdata_ff[1]_i_6_n_0\ - ); -\up_rdata_ff[1]_i_7\: unisim.vcomponents.LUT5 - generic map( - INIT => X"8080C000" - ) - port map ( - I0 => m_axis_data(1), - I1 => \^up_raddr_int_reg[4]_0\(1), - I2 => \^up_raddr_int_reg[4]_0\(0), - I3 => \up_rdata_ff_reg[4]\(0), - I4 => up_raddr_s(3), - O => \up_rdata_ff[1]_i_7_n_0\ - ); -\up_rdata_ff[20]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"8" - ) - port map ( - I0 => \up_rdata_ff[31]_i_4_n_0\, - I1 => \up_rdata_ff_reg[31]\(20), - O => \up_scratch_reg[20]\ - ); -\up_rdata_ff[21]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"8" - ) - port map ( - I0 => \up_rdata_ff[31]_i_4_n_0\, - I1 => \up_rdata_ff_reg[31]\(21), - O => \up_scratch_reg[21]\ - ); -\up_rdata_ff[22]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"8" - ) - port map ( - I0 => \up_rdata_ff[31]_i_4_n_0\, - I1 => \up_rdata_ff_reg[31]\(22), - O => \up_scratch_reg[22]\ - ); -\up_rdata_ff[23]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"8" - ) - port map ( - I0 => \up_rdata_ff[31]_i_4_n_0\, - I1 => \up_rdata_ff_reg[31]\(23), - O => \up_scratch_reg[23]\ - ); -\up_rdata_ff[24]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"8" - ) - port map ( - I0 => \up_rdata_ff[31]_i_4_n_0\, - I1 => \up_rdata_ff_reg[31]\(24), - O => \up_scratch_reg[24]\ - ); -\up_rdata_ff[25]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"8" - ) - port map ( - I0 => \up_rdata_ff[31]_i_4_n_0\, - I1 => \up_rdata_ff_reg[31]\(25), - O => \up_scratch_reg[25]\ - ); -\up_rdata_ff[26]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"8" - ) - port map ( - I0 => \up_rdata_ff[31]_i_4_n_0\, - I1 => \up_rdata_ff_reg[31]\(26), - O => \up_scratch_reg[26]\ - ); -\up_rdata_ff[27]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"8" - ) - port map ( - I0 => \up_rdata_ff[31]_i_4_n_0\, - I1 => \up_rdata_ff_reg[31]\(27), - O => \up_scratch_reg[27]\ - ); -\up_rdata_ff[28]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"8" - ) - port map ( - I0 => \up_rdata_ff[31]_i_4_n_0\, - I1 => \up_rdata_ff_reg[31]\(28), - O => \up_scratch_reg[28]\ - ); -\up_rdata_ff[29]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"8" - ) - port map ( - I0 => \up_rdata_ff[31]_i_4_n_0\, - I1 => \up_rdata_ff_reg[31]\(29), - O => \up_scratch_reg[29]\ - ); -\up_rdata_ff[2]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"02020000FF000000" - ) - port map ( - I0 => \up_rdata_ff[2]_i_2_n_0\, - I1 => \up_rdata_ff[2]_i_3_n_0\, - I2 => up_raddr_s(3), - I3 => \up_rdata_ff[2]_i_4_n_0\, - I4 => \up_rdata_ff[2]_i_5_n_0\, - I5 => up_raddr_s(0), - O => \up_raddr_int_reg[3]_2\ - ); -\up_rdata_ff[2]_i_10\: unisim.vcomponents.LUT5 - generic map( - INIT => X"8080C000" - ) - port map ( - I0 => m_axis_data(2), - I1 => \^up_raddr_int_reg[4]_0\(1), - I2 => \^up_raddr_int_reg[4]_0\(0), - I3 => \up_rdata_ff_reg[4]\(1), - I4 => up_raddr_s(3), - O => \up_rdata_ff[2]_i_10_n_0\ - ); -\up_rdata_ff[2]_i_2\: unisim.vcomponents.LUT6 - generic map( - INIT => X"FF000000F0F08888" - ) - port map ( - I0 => \up_rdata_ff[3]_i_3_0\(2), - I1 => up_irq_source(2), - I2 => \up_rdata_ff_reg[7]\(1), - I3 => \up_rdata_ff_reg[5]_0\(1), - I4 => \^up_raddr_int_reg[4]_0\(1), - I5 => \^up_raddr_int_reg[4]_0\(0), - O => \up_rdata_ff[2]_i_2_n_0\ - ); -\up_rdata_ff[2]_i_3\: unisim.vcomponents.LUT2 - generic map( - INIT => X"B" - ) - port map ( - I0 => up_raddr_s(1), - I1 => up_raddr_s(5), - O => \up_rdata_ff[2]_i_3_n_0\ - ); -\up_rdata_ff[2]_i_4\: unisim.vcomponents.LUT6 - generic map( - INIT => X"EFEEEEEEEEEEEEEE" - ) - port map ( - I0 => \up_rdata_ff[2]_i_7_n_0\, - I1 => \up_rdata_ff[2]_i_8_n_0\, - I2 => \m_axis_raddr[4]_i_5_n_0\, - I3 => up_raddr_s(1), - I4 => \up_rdata_ff[2]_i_9_n_0\, - I5 => \up_rdata_ff_reg[5]\(2), - O => \up_rdata_ff[2]_i_4_n_0\ - ); -\up_rdata_ff[2]_i_5\: unisim.vcomponents.LUT3 - generic map( - INIT => X"32" - ) - port map ( - I0 => up_raddr_s(5), - I1 => up_raddr_s(6), - I2 => \up_rdata_ff_reg[31]\(2), - O => \up_rdata_ff[2]_i_5_n_0\ - ); -\up_rdata_ff[2]_i_7\: unisim.vcomponents.LUT6 - generic map( - INIT => X"00000000FFFF2230" - ) - port map ( - I0 => \up_rdata_ff_reg[7]_0\(2), - I1 => \up_rdata_ff[16]_i_2_n_0\, - I2 => \up_rdata_ff[3]_i_3_0\(2), - I3 => \^up_raddr_int_reg[4]_0\(1), - I4 => \up_rdata_ff[2]_i_10_n_0\, - I5 => \up_rdata_ff[2]_i_3_n_0\, - O => \up_rdata_ff[2]_i_7_n_0\ - ); -\up_rdata_ff[2]_i_8\: unisim.vcomponents.LUT6 - generic map( - INIT => X"8280020002020202" - ) - port map ( - I0 => \up_rdata_ff[0]_i_9_n_0\, - I1 => \^up_raddr_int_reg[4]_0\(1), - I2 => up_raddr_s(3), - I3 => up_irq_source(2), - I4 => m_axis_data(2), - I5 => up_raddr_s(5), - O => \up_rdata_ff[2]_i_8_n_0\ - ); -\up_rdata_ff[2]_i_9\: unisim.vcomponents.LUT2 - generic map( - INIT => X"2" - ) - port map ( - I0 => \^up_raddr_int_reg[4]_0\(0), - I1 => up_raddr_s(3), - O => \up_rdata_ff[2]_i_9_n_0\ - ); -\up_rdata_ff[30]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"8" - ) - port map ( - I0 => \up_rdata_ff[31]_i_4_n_0\, - I1 => \up_rdata_ff_reg[31]\(30), - O => \up_scratch_reg[30]\ - ); -\up_rdata_ff[31]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"FFFFFFFFFFFEFFFF" - ) - port map ( - I0 => up_raddr_s(9), - I1 => up_raddr_s(13), - I2 => up_raddr_s(7), - I3 => up_raddr_s(10), - I4 => \up_rdata_ff[31]_i_3_n_0\, - I5 => up_raddr_s(8), - O => \up_raddr_int_reg[9]_0\ - ); -\up_rdata_ff[31]_i_2\: unisim.vcomponents.LUT2 - generic map( - INIT => X"8" - ) - port map ( - I0 => \up_rdata_ff[31]_i_4_n_0\, - I1 => \up_rdata_ff_reg[31]\(31), - O => \up_scratch_reg[31]\ - ); -\up_rdata_ff[31]_i_3\: unisim.vcomponents.LUT2 - generic map( - INIT => X"1" - ) - port map ( - I0 => up_raddr_s(11), - I1 => up_raddr_s(12), - O => \up_rdata_ff[31]_i_3_n_0\ - ); -\up_rdata_ff[31]_i_4\: unisim.vcomponents.LUT6 - generic map( - INIT => X"0000000100000000" - ) - port map ( - I0 => \up_rdata_ff[16]_i_2_n_0\, - I1 => up_raddr_s(6), - I2 => up_raddr_s(0), - I3 => up_raddr_s(5), - I4 => \^up_raddr_int_reg[4]_0\(1), - I5 => up_raddr_s(1), - O => \up_rdata_ff[31]_i_4_n_0\ - ); -\up_rdata_ff[3]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"FFFFFFFFFFFF0400" - ) - port map ( - I0 => \up_rdata_ff[3]_i_2_n_0\, - I1 => up_raddr_s(5), - I2 => up_raddr_s(3), - I3 => \up_rdata_ff[3]_i_3_n_0\, - I4 => \up_rdata_ff[3]_i_4_n_0\, - I5 => \up_rdata_ff[3]_i_5_n_0\, - O => \up_raddr_int_reg[5]_0\ - ); -\up_rdata_ff[3]_i_2\: unisim.vcomponents.LUT2 - generic map( - INIT => X"E" - ) - port map ( - I0 => up_raddr_s(0), - I1 => up_raddr_s(6), - O => \up_rdata_ff[3]_i_2_n_0\ - ); -\up_rdata_ff[3]_i_3\: unisim.vcomponents.LUT6 - generic map( - INIT => X"FAAEAAAAAAAEAAAA" - ) - port map ( - I0 => \up_rdata_ff[3]_i_6_n_0\, - I1 => sync_id_pending_reg(0), - I2 => \^up_raddr_int_reg[4]_0\(1), - I3 => \^up_raddr_int_reg[4]_0\(0), - I4 => up_raddr_s(1), - I5 => \up_rdata_ff_reg[5]\(3), - O => \up_rdata_ff[3]_i_3_n_0\ - ); -\up_rdata_ff[3]_i_4\: unisim.vcomponents.LUT6 - generic map( - INIT => X"0000040000000000" - ) - port map ( - I0 => up_raddr_s(1), - I1 => up_raddr_s(5), - I2 => up_raddr_s(6), - I3 => up_raddr_s(0), - I4 => up_raddr_s(3), - I5 => \up_rdata_ff[3]_i_7_n_0\, - O => \up_rdata_ff[3]_i_4_n_0\ - ); -\up_rdata_ff[3]_i_5\: unisim.vcomponents.LUT6 - generic map( - INIT => X"FFFFFFFF10000000" - ) - port map ( - I0 => \m_axis_raddr[4]_i_5_n_0\, - I1 => \up_rdata_ff[3]_i_2_n_0\, - I2 => up_raddr_s(3), - I3 => m_axis_data(3), - I4 => \up_rdata_ff[3]_i_8_n_0\, - I5 => \up_rdata_ff[3]_i_9_n_0\, - O => \up_rdata_ff[3]_i_5_n_0\ - ); -\up_rdata_ff[3]_i_6\: unisim.vcomponents.LUT6 - generic map( - INIT => X"00000000D591C480" - ) - port map ( - I0 => \^up_raddr_int_reg[4]_0\(0), - I1 => \^up_raddr_int_reg[4]_0\(1), - I2 => \up_rdata_ff_reg[4]\(2), - I3 => \up_rdata_ff_reg[7]_0\(3), - I4 => \up_rdata_ff[3]_i_3_0\(3), - I5 => up_raddr_s(1), - O => \up_rdata_ff[3]_i_6_n_0\ - ); -\up_rdata_ff[3]_i_7\: unisim.vcomponents.LUT6 - generic map( - INIT => X"FF000000F0F08888" - ) - port map ( - I0 => \up_rdata_ff[3]_i_3_0\(3), - I1 => sync_id_pending_reg(0), - I2 => \up_rdata_ff_reg[7]\(2), - I3 => \up_rdata_ff_reg[5]_0\(2), - I4 => \^up_raddr_int_reg[4]_0\(1), - I5 => \^up_raddr_int_reg[4]_0\(0), - O => \up_rdata_ff[3]_i_7_n_0\ - ); -\up_rdata_ff[3]_i_8\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => \^up_raddr_int_reg[4]_0\(0), - I1 => up_raddr_s(1), - O => \up_rdata_ff[3]_i_8_n_0\ - ); -\up_rdata_ff[3]_i_9\: unisim.vcomponents.LUT6 - generic map( - INIT => X"0100010001000000" - ) - port map ( - I0 => \up_rdata_ff[16]_i_3_n_0\, - I1 => \up_rdata_ff[16]_i_2_n_0\, - I2 => up_raddr_s(6), - I3 => up_raddr_s(1), - I4 => up_raddr_s(0), - I5 => \up_rdata_ff_reg[31]\(3), - O => \up_rdata_ff[3]_i_9_n_0\ - ); -\up_rdata_ff[4]_i_1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"00005503" - ) - port map ( - I0 => \up_rdata_ff[4]_i_2_n_0\, - I1 => \up_rdata_ff[4]_i_3_n_0\, - I2 => \up_rdata_ff[4]_i_4_n_0\, - I3 => up_raddr_s(0), - I4 => up_raddr_s(6), - O => \up_raddr_int_reg[0]_0\ - ); -\up_rdata_ff[4]_i_2\: unisim.vcomponents.LUT6 - generic map( - INIT => X"FEFEFFFFFEFFFEFF" - ) - port map ( - I0 => up_raddr_s(3), - I1 => up_raddr_s(1), - I2 => \m_axis_raddr[4]_i_5_n_0\, - I3 => \up_rdata_ff_reg[7]\(3), - I4 => \up_rdata_ff_reg[5]_0\(3), - I5 => \^up_raddr_int_reg[4]_0\(0), - O => \up_rdata_ff[4]_i_2_n_0\ - ); -\up_rdata_ff[4]_i_3\: unisim.vcomponents.LUT6 - generic map( - INIT => X"7575BABA757FBABA" - ) - port map ( - I0 => up_raddr_s(5), - I1 => m_axis_data(4), - I2 => up_raddr_s(3), - I3 => \^up_raddr_int_reg[4]_0\(0), - I4 => \^up_raddr_int_reg[4]_0\(1), - I5 => \up_rdata_ff_reg[7]_0\(4), - O => \up_rdata_ff[4]_i_3_n_0\ - ); -\up_rdata_ff[4]_i_4\: unisim.vcomponents.LUT6 - generic map( - INIT => X"55555500F5F7FFF0" - ) - port map ( - I0 => \^up_raddr_int_reg[4]_0\(1), - I1 => \up_rdata_ff_reg[4]\(3), - I2 => up_raddr_s(1), - I3 => up_raddr_s(3), - I4 => \^up_raddr_int_reg[4]_0\(0), - I5 => \up_rdata_ff[4]_i_5_n_0\, - O => \up_rdata_ff[4]_i_4_n_0\ - ); -\up_rdata_ff[4]_i_5\: unisim.vcomponents.LUT6 - generic map( - INIT => X"2FF222222F222222" - ) - port map ( - I0 => \up_rdata_ff_reg[31]\(4), - I1 => \^up_raddr_int_reg[4]_0\(1), - I2 => \^up_raddr_int_reg[4]_0\(0), - I3 => up_raddr_s(3), - I4 => up_raddr_s(1), - I5 => \up_rdata_ff_reg[5]\(4), - O => \up_rdata_ff[4]_i_5_n_0\ - ); -\up_rdata_ff[5]_i_1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"00005503" - ) - port map ( - I0 => \up_rdata_ff[5]_i_2_n_0\, - I1 => \up_rdata_ff[5]_i_3_n_0\, - I2 => \up_rdata_ff[5]_i_4_n_0\, - I3 => up_raddr_s(0), - I4 => up_raddr_s(6), - O => \up_raddr_int_reg[0]_1\ - ); -\up_rdata_ff[5]_i_2\: unisim.vcomponents.LUT6 - generic map( - INIT => X"FEFEFFFFFEFFFEFF" - ) - port map ( - I0 => up_raddr_s(3), - I1 => up_raddr_s(1), - I2 => \m_axis_raddr[4]_i_5_n_0\, - I3 => \up_rdata_ff_reg[7]\(4), - I4 => \up_rdata_ff_reg[5]_0\(4), - I5 => \^up_raddr_int_reg[4]_0\(0), - O => \up_rdata_ff[5]_i_2_n_0\ - ); -\up_rdata_ff[5]_i_3\: unisim.vcomponents.LUT6 - generic map( - INIT => X"00DF00FF00DF0000" - ) - port map ( - I0 => up_raddr_s(1), - I1 => \m_axis_raddr[4]_i_5_n_0\, - I2 => \up_rdata_ff_reg[5]\(5), - I3 => up_raddr_s(3), - I4 => \^up_raddr_int_reg[4]_0\(0), - I5 => \up_rdata_ff[5]_i_5_n_0\, - O => \up_rdata_ff[5]_i_3_n_0\ - ); -\up_rdata_ff[5]_i_4\: unisim.vcomponents.LUT6 - generic map( - INIT => X"9FFFFFFF00000000" - ) - port map ( - I0 => \^up_raddr_int_reg[4]_0\(0), - I1 => up_raddr_s(1), - I2 => up_raddr_s(5), - I3 => \^up_raddr_int_reg[4]_0\(1), - I4 => m_axis_data(5), - I5 => up_raddr_s(3), - O => \up_rdata_ff[5]_i_4_n_0\ - ); -\up_rdata_ff[5]_i_5\: unisim.vcomponents.LUT5 - generic map( - INIT => X"FD3CFDFC" - ) - port map ( - I0 => \up_rdata_ff_reg[31]\(5), - I1 => \^up_raddr_int_reg[4]_0\(1), - I2 => up_raddr_s(5), - I3 => up_raddr_s(1), - I4 => \up_rdata_ff_reg[7]_0\(5), - O => \up_rdata_ff[5]_i_5_n_0\ - ); -\up_rdata_ff[6]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"FFFFFFFFFFFF0001" - ) - port map ( - I0 => up_raddr_s(3), - I1 => up_raddr_s(0), - I2 => up_raddr_s(6), - I3 => \up_rdata_ff[6]_i_2_n_0\, - I4 => \up_rdata_ff[6]_i_3_n_0\, - I5 => \up_rdata_ff[6]_i_4_n_0\, - O => \up_raddr_int_reg[3]_0\ - ); -\up_rdata_ff[6]_i_2\: unisim.vcomponents.LUT6 - generic map( - INIT => X"FFFFCFFFFDFDFCFC" - ) - port map ( - I0 => \up_rdata_ff_reg[31]\(6), - I1 => \^up_raddr_int_reg[4]_0\(0), - I2 => up_raddr_s(5), - I3 => \up_rdata_ff_reg[7]_0\(6), - I4 => up_raddr_s(1), - I5 => \^up_raddr_int_reg[4]_0\(1), - O => \up_rdata_ff[6]_i_2_n_0\ - ); -\up_rdata_ff[6]_i_3\: unisim.vcomponents.LUT6 - generic map( - INIT => X"0000000000040000" - ) - port map ( - I0 => \m_axis_raddr[4]_i_5_n_0\, - I1 => up_raddr_s(0), - I2 => up_raddr_s(6), - I3 => \up_rdata_ff[16]_i_2_n_0\, - I4 => \up_rdata_ff_reg[7]\(5), - I5 => up_raddr_s(1), - O => \up_rdata_ff[6]_i_3_n_0\ - ); -\up_rdata_ff[6]_i_4\: unisim.vcomponents.LUT6 - generic map( - INIT => X"0000004000400000" - ) - port map ( - I0 => \up_rdata_ff[3]_i_2_n_0\, - I1 => m_axis_data(6), - I2 => up_raddr_s(3), - I3 => \m_axis_raddr[4]_i_5_n_0\, - I4 => up_raddr_s(1), - I5 => \^up_raddr_int_reg[4]_0\(0), - O => \up_rdata_ff[6]_i_4_n_0\ - ); -\up_rdata_ff[7]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"2390000000000000" - ) - port map ( - I0 => up_raddr_s(3), - I1 => \^up_raddr_int_reg[4]_0\(0), - I2 => \^up_raddr_int_reg[4]_0\(1), - I3 => up_raddr_s(1), - I4 => \up_rdata_ff[7]_i_2_n_0\, - I5 => \up_rdata_ff[7]_i_3_n_0\, - O => \up_raddr_int_reg[3]_4\ - ); -\up_rdata_ff[7]_i_2\: unisim.vcomponents.LUT6 - generic map( - INIT => X"0A0A000A00040004" - ) - port map ( - I0 => up_raddr_s(5), - I1 => \up_rdata_ff_reg[31]\(7), - I2 => up_raddr_s(6), - I3 => up_raddr_s(3), - I4 => m_axis_data(7), - I5 => \^up_raddr_int_reg[4]_0\(1), - O => \up_rdata_ff[7]_i_2_n_0\ - ); -\up_rdata_ff[7]_i_3\: unisim.vcomponents.LUT5 - generic map( - INIT => X"333B3338" - ) - port map ( - I0 => \up_rdata_ff_reg[7]\(6), - I1 => up_raddr_s(0), - I2 => \^up_raddr_int_reg[4]_0\(0), - I3 => up_raddr_s(1), - I4 => \up_rdata_ff_reg[7]_0\(7), - O => \up_rdata_ff[7]_i_3_n_0\ - ); -\up_rdata_ff[8]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"8" - ) - port map ( - I0 => \up_rdata_ff[31]_i_4_n_0\, - I1 => \up_rdata_ff_reg[31]\(8), - O => \up_scratch_reg[8]\ - ); -\up_rdata_ff[9]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"8" - ) - port map ( - I0 => \up_rdata_ff[31]_i_4_n_0\, - I1 => \up_rdata_ff_reg[31]\(9), - O => \up_scratch_reg[9]\ - ); -up_rreq_int_i_1: unisim.vcomponents.LUT3 - generic map( - INIT => X"08" - ) - port map ( - I0 => s_axi_arvalid, - I1 => s_axi_aresetn, - I2 => up_rsel_reg_n_0, - O => up_rreq_int_i_1_n_0 - ); -up_rreq_int_reg: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => up_rreq_int_i_1_n_0, - Q => \^up_rreq_s\, - R => '0' - ); -up_rsel_i_1: unisim.vcomponents.LUT4 - generic map( - INIT => X"3FAA" - ) - port map ( - I0 => s_axi_arvalid, - I1 => \^up_axi_rvalid_int_reg_0\, - I2 => s_axi_rready, - I3 => up_rsel_reg_n_0, - O => up_rsel_i_1_n_0 - ); -up_rsel_reg: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => up_rsel_i_1_n_0, - Q => up_rsel_reg_n_0, - R => \^s_axi_aresetn_0\ - ); -\up_scratch[31]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"0000000001000000" - ) - port map ( - I0 => up_waddr_s(2), - I1 => up_waddr_s(3), - I2 => up_waddr_s(4), - I3 => offload0_enable_reg_i_4_n_0, - I4 => up_waddr_s(1), - I5 => \up_scratch[31]_i_2_n_0\, - O => \up_waddr_int_reg[2]_0\(0) - ); -\up_scratch[31]_i_2\: unisim.vcomponents.LUT6 - generic map( - INIT => X"FFFFFFFFFFFFFFFE" - ) - port map ( - I0 => up_waddr_s(5), - I1 => \s_axis_waddr[3]_i_4_n_0\, - I2 => up_waddr_s(7), - I3 => up_waddr_s(6), - I4 => up_waddr_s(8), - I5 => \up_scratch[31]_i_3_n_0\, - O => \up_scratch[31]_i_2_n_0\ - ); -\up_scratch[31]_i_3\: unisim.vcomponents.LUT2 - generic map( - INIT => X"E" - ) - port map ( - I0 => up_waddr_s(10), - I1 => up_waddr_s(9), - O => \up_scratch[31]_i_3_n_0\ - ); -up_sw_reset_i_1: unisim.vcomponents.LUT4 - generic map( - INIT => X"FB08" - ) - port map ( - I0 => \^up_wdata_int_reg[31]_0\(0), - I1 => up_sw_reset_i_2_n_0, - I2 => \up_scratch[31]_i_2_n_0\, - I3 => up_sw_reset, - O => \up_wdata_int_reg[0]_0\ - ); -up_sw_reset_i_2: unisim.vcomponents.LUT6 - generic map( - INIT => X"0000000200000000" - ) - port map ( - I0 => up_waddr_s(4), - I1 => up_waddr_s(3), - I2 => up_waddr_s(1), - I3 => up_waddr_s(2), - I4 => \^q\(0), - I5 => \^up_wreq_s\, - O => up_sw_reset_i_2_n_0 - ); -up_wack_d_i_1: unisim.vcomponents.LUT6 - generic map( - INIT => X"EAAAAAAA00000000" - ) - port map ( - I0 => up_wack_ff, - I1 => \up_wcount_reg_n_0_[1]\, - I2 => \up_wcount_reg_n_0_[0]\, - I3 => \up_wcount_reg_n_0_[3]\, - I4 => \up_wcount_reg_n_0_[2]\, - I5 => p_0_in7_in, - O => up_wack_s - ); -up_wack_d_reg: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => up_wack_s, - Q => up_wack_d, - R => \^s_axi_aresetn_0\ - ); -\up_waddr_int_reg[0]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => p_5_in, - D => s_axi_awaddr(0), - Q => \^q\(0), - R => \^s_axi_aresetn_0\ - ); -\up_waddr_int_reg[10]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => p_5_in, - D => s_axi_awaddr(10), - Q => up_waddr_s(10), - R => \^s_axi_aresetn_0\ - ); -\up_waddr_int_reg[11]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => p_5_in, - D => s_axi_awaddr(11), - Q => up_waddr_s(11), - R => \^s_axi_aresetn_0\ - ); -\up_waddr_int_reg[12]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => p_5_in, - D => s_axi_awaddr(12), - Q => up_waddr_s(12), - R => \^s_axi_aresetn_0\ - ); -\up_waddr_int_reg[13]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => p_5_in, - D => s_axi_awaddr(13), - Q => up_waddr_s(13), - R => \^s_axi_aresetn_0\ - ); -\up_waddr_int_reg[1]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => p_5_in, - D => s_axi_awaddr(1), - Q => up_waddr_s(1), - R => \^s_axi_aresetn_0\ - ); -\up_waddr_int_reg[2]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => p_5_in, - D => s_axi_awaddr(2), - Q => up_waddr_s(2), - R => \^s_axi_aresetn_0\ - ); -\up_waddr_int_reg[3]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => p_5_in, - D => s_axi_awaddr(3), - Q => up_waddr_s(3), - R => \^s_axi_aresetn_0\ - ); -\up_waddr_int_reg[4]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => p_5_in, - D => s_axi_awaddr(4), - Q => up_waddr_s(4), - R => \^s_axi_aresetn_0\ - ); -\up_waddr_int_reg[5]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => p_5_in, - D => s_axi_awaddr(5), - Q => up_waddr_s(5), - R => \^s_axi_aresetn_0\ - ); -\up_waddr_int_reg[6]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => p_5_in, - D => s_axi_awaddr(6), - Q => up_waddr_s(6), - R => \^s_axi_aresetn_0\ - ); -\up_waddr_int_reg[7]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => p_5_in, - D => s_axi_awaddr(7), - Q => up_waddr_s(7), - R => \^s_axi_aresetn_0\ - ); -\up_waddr_int_reg[8]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => p_5_in, - D => s_axi_awaddr(8), - Q => up_waddr_s(8), - R => \^s_axi_aresetn_0\ - ); -\up_waddr_int_reg[9]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => p_5_in, - D => s_axi_awaddr(9), - Q => up_waddr_s(9), - R => \^s_axi_aresetn_0\ - ); -\up_wcount[0]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"04" - ) - port map ( - I0 => up_wack_ff, - I1 => p_0_in7_in, - I2 => \up_wcount_reg_n_0_[0]\, - O => p_2_in(0) - ); -\up_wcount[1]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0028" - ) - port map ( - I0 => p_0_in7_in, - I1 => \up_wcount_reg_n_0_[0]\, - I2 => \up_wcount_reg_n_0_[1]\, - I3 => up_wack_ff, - O => p_2_in(1) - ); -\up_wcount[2]_i_1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"00002888" - ) - port map ( - I0 => p_0_in7_in, - I1 => \up_wcount_reg_n_0_[2]\, - I2 => \up_wcount_reg_n_0_[0]\, - I3 => \up_wcount_reg_n_0_[1]\, - I4 => up_wack_ff, - O => p_2_in(2) - ); -\up_wcount[3]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"0000000028A0A0A0" - ) - port map ( - I0 => p_0_in7_in, - I1 => \up_wcount_reg_n_0_[2]\, - I2 => \up_wcount_reg_n_0_[3]\, - I3 => \up_wcount_reg_n_0_[0]\, - I4 => \up_wcount_reg_n_0_[1]\, - I5 => up_wack_ff, - O => p_2_in(3) - ); -\up_wcount[4]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"FE" - ) - port map ( - I0 => \^up_wreq_s\, - I1 => p_0_in7_in, - I2 => up_wack_s, - O => \p_1_in__0\ - ); -\up_wcount[4]_i_2\: unisim.vcomponents.LUT6 - generic map( - INIT => X"5777777777777777" - ) - port map ( - I0 => p_0_in7_in, - I1 => up_wack_ff, - I2 => \up_wcount_reg_n_0_[1]\, - I3 => \up_wcount_reg_n_0_[0]\, - I4 => \up_wcount_reg_n_0_[3]\, - I5 => \up_wcount_reg_n_0_[2]\, - O => p_2_in(4) - ); -\up_wcount_reg[0]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => \p_1_in__0\, - D => p_2_in(0), - Q => \up_wcount_reg_n_0_[0]\, - R => \^s_axi_aresetn_0\ - ); -\up_wcount_reg[1]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => \p_1_in__0\, - D => p_2_in(1), - Q => \up_wcount_reg_n_0_[1]\, - R => \^s_axi_aresetn_0\ - ); -\up_wcount_reg[2]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => \p_1_in__0\, - D => p_2_in(2), - Q => \up_wcount_reg_n_0_[2]\, - R => \^s_axi_aresetn_0\ - ); -\up_wcount_reg[3]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => \p_1_in__0\, - D => p_2_in(3), - Q => \up_wcount_reg_n_0_[3]\, - R => \^s_axi_aresetn_0\ - ); -\up_wcount_reg[4]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => \p_1_in__0\, - D => p_2_in(4), - Q => p_0_in7_in, - R => \^s_axi_aresetn_0\ - ); -\up_wdata_int[15]_i_1\: unisim.vcomponents.LUT1 - generic map( - INIT => X"1" - ) - port map ( - I0 => up_wsel_reg_n_0, - O => p_5_in - ); -\up_wdata_int_reg[0]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => p_5_in, - D => s_axi_wdata(0), - Q => \^up_wdata_int_reg[31]_0\(0), - R => \^s_axi_aresetn_0\ - ); -\up_wdata_int_reg[10]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => p_5_in, - D => s_axi_wdata(10), - Q => \^up_wdata_int_reg[31]_0\(10), - R => \^s_axi_aresetn_0\ - ); -\up_wdata_int_reg[11]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => p_5_in, - D => s_axi_wdata(11), - Q => \^up_wdata_int_reg[31]_0\(11), - R => \^s_axi_aresetn_0\ - ); -\up_wdata_int_reg[12]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => p_5_in, - D => s_axi_wdata(12), - Q => \^up_wdata_int_reg[31]_0\(12), - R => \^s_axi_aresetn_0\ - ); -\up_wdata_int_reg[13]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => p_5_in, - D => s_axi_wdata(13), - Q => \^up_wdata_int_reg[31]_0\(13), - R => \^s_axi_aresetn_0\ - ); -\up_wdata_int_reg[14]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => p_5_in, - D => s_axi_wdata(14), - Q => \^up_wdata_int_reg[31]_0\(14), - R => \^s_axi_aresetn_0\ - ); -\up_wdata_int_reg[15]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => p_5_in, - D => s_axi_wdata(15), - Q => \^up_wdata_int_reg[31]_0\(15), - R => \^s_axi_aresetn_0\ - ); -\up_wdata_int_reg[16]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => p_5_in, - D => s_axi_wdata(16), - Q => \^up_wdata_int_reg[31]_0\(16), - R => \^s_axi_aresetn_0\ - ); -\up_wdata_int_reg[17]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => p_5_in, - D => s_axi_wdata(17), - Q => \^up_wdata_int_reg[31]_0\(17), - R => \^s_axi_aresetn_0\ - ); -\up_wdata_int_reg[18]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => p_5_in, - D => s_axi_wdata(18), - Q => \^up_wdata_int_reg[31]_0\(18), - R => \^s_axi_aresetn_0\ - ); -\up_wdata_int_reg[19]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => p_5_in, - D => s_axi_wdata(19), - Q => \^up_wdata_int_reg[31]_0\(19), - R => \^s_axi_aresetn_0\ - ); -\up_wdata_int_reg[1]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => p_5_in, - D => s_axi_wdata(1), - Q => \^up_wdata_int_reg[31]_0\(1), - R => \^s_axi_aresetn_0\ - ); -\up_wdata_int_reg[20]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => p_5_in, - D => s_axi_wdata(20), - Q => \^up_wdata_int_reg[31]_0\(20), - R => \^s_axi_aresetn_0\ - ); -\up_wdata_int_reg[21]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => p_5_in, - D => s_axi_wdata(21), - Q => \^up_wdata_int_reg[31]_0\(21), - R => \^s_axi_aresetn_0\ - ); -\up_wdata_int_reg[22]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => p_5_in, - D => s_axi_wdata(22), - Q => \^up_wdata_int_reg[31]_0\(22), - R => \^s_axi_aresetn_0\ - ); -\up_wdata_int_reg[23]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => p_5_in, - D => s_axi_wdata(23), - Q => \^up_wdata_int_reg[31]_0\(23), - R => \^s_axi_aresetn_0\ - ); -\up_wdata_int_reg[24]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => p_5_in, - D => s_axi_wdata(24), - Q => \^up_wdata_int_reg[31]_0\(24), - R => \^s_axi_aresetn_0\ - ); -\up_wdata_int_reg[25]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => p_5_in, - D => s_axi_wdata(25), - Q => \^up_wdata_int_reg[31]_0\(25), - R => \^s_axi_aresetn_0\ - ); -\up_wdata_int_reg[26]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => p_5_in, - D => s_axi_wdata(26), - Q => \^up_wdata_int_reg[31]_0\(26), - R => \^s_axi_aresetn_0\ - ); -\up_wdata_int_reg[27]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => p_5_in, - D => s_axi_wdata(27), - Q => \^up_wdata_int_reg[31]_0\(27), - R => \^s_axi_aresetn_0\ - ); -\up_wdata_int_reg[28]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => p_5_in, - D => s_axi_wdata(28), - Q => \^up_wdata_int_reg[31]_0\(28), - R => \^s_axi_aresetn_0\ - ); -\up_wdata_int_reg[29]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => p_5_in, - D => s_axi_wdata(29), - Q => \^up_wdata_int_reg[31]_0\(29), - R => \^s_axi_aresetn_0\ - ); -\up_wdata_int_reg[2]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => p_5_in, - D => s_axi_wdata(2), - Q => \^up_wdata_int_reg[31]_0\(2), - R => \^s_axi_aresetn_0\ - ); -\up_wdata_int_reg[30]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => p_5_in, - D => s_axi_wdata(30), - Q => \^up_wdata_int_reg[31]_0\(30), - R => \^s_axi_aresetn_0\ - ); -\up_wdata_int_reg[31]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => p_5_in, - D => s_axi_wdata(31), - Q => \^up_wdata_int_reg[31]_0\(31), - R => \^s_axi_aresetn_0\ - ); -\up_wdata_int_reg[3]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => p_5_in, - D => s_axi_wdata(3), - Q => \^up_wdata_int_reg[31]_0\(3), - R => \^s_axi_aresetn_0\ - ); -\up_wdata_int_reg[4]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => p_5_in, - D => s_axi_wdata(4), - Q => \^up_wdata_int_reg[31]_0\(4), - R => \^s_axi_aresetn_0\ - ); -\up_wdata_int_reg[5]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => p_5_in, - D => s_axi_wdata(5), - Q => \^up_wdata_int_reg[31]_0\(5), - R => \^s_axi_aresetn_0\ - ); -\up_wdata_int_reg[6]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => p_5_in, - D => s_axi_wdata(6), - Q => \^up_wdata_int_reg[31]_0\(6), - R => \^s_axi_aresetn_0\ - ); -\up_wdata_int_reg[7]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => p_5_in, - D => s_axi_wdata(7), - Q => \^up_wdata_int_reg[31]_0\(7), - R => \^s_axi_aresetn_0\ - ); -\up_wdata_int_reg[8]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => p_5_in, - D => s_axi_wdata(8), - Q => \^up_wdata_int_reg[31]_0\(8), - R => \^s_axi_aresetn_0\ - ); -\up_wdata_int_reg[9]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => p_5_in, - D => s_axi_wdata(9), - Q => \^up_wdata_int_reg[31]_0\(9), - R => \^s_axi_aresetn_0\ - ); -up_wreq_int_i_1: unisim.vcomponents.LUT4 - generic map( - INIT => X"4000" - ) - port map ( - I0 => up_wsel_reg_n_0, - I1 => s_axi_aresetn, - I2 => s_axi_wvalid, - I3 => s_axi_awvalid, - O => up_wreq_int_i_1_n_0 - ); -up_wreq_int_reg: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => up_wreq_int_i_1_n_0, - Q => \^up_wreq_s\, - R => '0' - ); -up_wsel_i_1: unisim.vcomponents.LUT5 - generic map( - INIT => X"0FFF8888" - ) - port map ( - I0 => s_axi_wvalid, - I1 => s_axi_awvalid, - I2 => \^s_axi_bvalid\, - I3 => s_axi_bready, - I4 => up_wsel_reg_n_0, - O => up_wsel_i_1_n_0 - ); -up_wsel_reg: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => up_wsel_i_1_n_0, - Q => up_wsel_reg_n_0, - R => \^s_axi_aresetn_0\ - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity system_bd_axi_spi_engine_0_0_util_axis_fifo is - port ( - s_axis_ready_reg : out STD_LOGIC; - m_axis_valid_reg : out STD_LOGIC; - \level_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); - up_irq_source : out STD_LOGIC_VECTOR ( 0 to 0 ); - \room_reg[4]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); - cmd_data : out STD_LOGIC_VECTOR ( 15 downto 0 ); - up_sw_reset : in STD_LOGIC; - spi_clk : in STD_LOGIC; - p_1_in : in STD_LOGIC; - cmd_ready : in STD_LOGIC; - \level_reg[0]_0\ : in STD_LOGIC; - Q : in STD_LOGIC_VECTOR ( 0 to 0 ); - s_axi_aclk : in STD_LOGIC; - s_mem_write : in STD_LOGIC; - offload0_cmd_wr_data : in STD_LOGIC_VECTOR ( 15 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of system_bd_axi_spi_engine_0_0_util_axis_fifo : entity is "util_axis_fifo"; -end system_bd_axi_spi_engine_0_0_util_axis_fifo; - -architecture STRUCTURE of system_bd_axi_spi_engine_0_0_util_axis_fifo is - signal m_axis_raddr : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal s_axis_waddr : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal NLW_ram_reg_0_15_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); - signal NLW_ram_reg_0_15_12_15_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); - signal NLW_ram_reg_0_15_12_15_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); - signal NLW_ram_reg_0_15_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); - attribute METHODOLOGY_DRC_VIOS : string; - attribute METHODOLOGY_DRC_VIOS of ram_reg_0_15_0_5 : label is ""; - attribute RTL_RAM_BITS : integer; - attribute RTL_RAM_BITS of ram_reg_0_15_0_5 : label is 256; - attribute RTL_RAM_NAME : string; - attribute RTL_RAM_NAME of ram_reg_0_15_0_5 : label is "i_cmd_fifo/ram"; - attribute ram_addr_begin : integer; - attribute ram_addr_begin of ram_reg_0_15_0_5 : label is 0; - attribute ram_addr_end : integer; - attribute ram_addr_end of ram_reg_0_15_0_5 : label is 15; - attribute ram_offset : integer; - attribute ram_offset of ram_reg_0_15_0_5 : label is 0; - attribute ram_slice_begin : integer; - attribute ram_slice_begin of ram_reg_0_15_0_5 : label is 0; - attribute ram_slice_end : integer; - attribute ram_slice_end of ram_reg_0_15_0_5 : label is 5; - attribute METHODOLOGY_DRC_VIOS of ram_reg_0_15_12_15 : label is ""; - attribute RTL_RAM_BITS of ram_reg_0_15_12_15 : label is 256; - attribute RTL_RAM_NAME of ram_reg_0_15_12_15 : label is "i_cmd_fifo/ram"; - attribute ram_addr_begin of ram_reg_0_15_12_15 : label is 0; - attribute ram_addr_end of ram_reg_0_15_12_15 : label is 15; - attribute ram_offset of ram_reg_0_15_12_15 : label is 0; - attribute ram_slice_begin of ram_reg_0_15_12_15 : label is 12; - attribute ram_slice_end of ram_reg_0_15_12_15 : label is 15; - attribute METHODOLOGY_DRC_VIOS of ram_reg_0_15_6_11 : label is ""; - attribute RTL_RAM_BITS of ram_reg_0_15_6_11 : label is 256; - attribute RTL_RAM_NAME of ram_reg_0_15_6_11 : label is "i_cmd_fifo/ram"; - attribute ram_addr_begin of ram_reg_0_15_6_11 : label is 0; - attribute ram_addr_end of ram_reg_0_15_6_11 : label is 15; - attribute ram_offset of ram_reg_0_15_6_11 : label is 0; - attribute ram_slice_begin of ram_reg_0_15_6_11 : label is 6; - attribute ram_slice_end of ram_reg_0_15_6_11 : label is 11; -begin -i_address_sync: entity work.system_bd_axi_spi_engine_0_0_fifo_address_sync - port map ( - Q(0) => Q(0), - cmd_ready => cmd_ready, - \level_reg[0]_0\ => \level_reg[0]\(0), - \level_reg[0]_1\ => \level_reg[0]_0\, - \m_axis_raddr_reg[3]_0\(3 downto 0) => m_axis_raddr(3 downto 0), - m_axis_valid_reg_0 => m_axis_valid_reg, - p_1_in => p_1_in, - \room_reg[4]_0\(3 downto 0) => \room_reg[4]\(3 downto 0), - s_axis_ready_reg_0 => s_axis_ready_reg, - \s_axis_waddr_reg[3]_0\(3 downto 0) => s_axis_waddr(3 downto 0), - spi_clk => spi_clk, - up_irq_source(0) => up_irq_source(0), - up_sw_reset => up_sw_reset - ); -ram_reg_0_15_0_5: unisim.vcomponents.RAM32M - port map ( - ADDRA(4) => '0', - ADDRA(3 downto 0) => m_axis_raddr(3 downto 0), - ADDRB(4) => '0', - ADDRB(3 downto 0) => m_axis_raddr(3 downto 0), - ADDRC(4) => '0', - ADDRC(3 downto 0) => m_axis_raddr(3 downto 0), - ADDRD(4) => '0', - ADDRD(3 downto 0) => s_axis_waddr(3 downto 0), - DIA(1 downto 0) => offload0_cmd_wr_data(1 downto 0), - DIB(1 downto 0) => offload0_cmd_wr_data(3 downto 2), - DIC(1 downto 0) => offload0_cmd_wr_data(5 downto 4), - DID(1 downto 0) => B"00", - DOA(1 downto 0) => cmd_data(1 downto 0), - DOB(1 downto 0) => cmd_data(3 downto 2), - DOC(1 downto 0) => cmd_data(5 downto 4), - DOD(1 downto 0) => NLW_ram_reg_0_15_0_5_DOD_UNCONNECTED(1 downto 0), - WCLK => s_axi_aclk, - WE => s_mem_write - ); -ram_reg_0_15_12_15: unisim.vcomponents.RAM32M - port map ( - ADDRA(4) => '0', - ADDRA(3 downto 0) => m_axis_raddr(3 downto 0), - ADDRB(4) => '0', - ADDRB(3 downto 0) => m_axis_raddr(3 downto 0), - ADDRC(4) => '0', - ADDRC(3 downto 0) => m_axis_raddr(3 downto 0), - ADDRD(4) => '0', - ADDRD(3 downto 0) => s_axis_waddr(3 downto 0), - DIA(1 downto 0) => offload0_cmd_wr_data(13 downto 12), - DIB(1 downto 0) => offload0_cmd_wr_data(15 downto 14), - DIC(1 downto 0) => B"00", - DID(1 downto 0) => B"00", - DOA(1 downto 0) => cmd_data(13 downto 12), - DOB(1 downto 0) => cmd_data(15 downto 14), - DOC(1 downto 0) => NLW_ram_reg_0_15_12_15_DOC_UNCONNECTED(1 downto 0), - DOD(1 downto 0) => NLW_ram_reg_0_15_12_15_DOD_UNCONNECTED(1 downto 0), - WCLK => s_axi_aclk, - WE => s_mem_write - ); -ram_reg_0_15_6_11: unisim.vcomponents.RAM32M - port map ( - ADDRA(4) => '0', - ADDRA(3 downto 0) => m_axis_raddr(3 downto 0), - ADDRB(4) => '0', - ADDRB(3 downto 0) => m_axis_raddr(3 downto 0), - ADDRC(4) => '0', - ADDRC(3 downto 0) => m_axis_raddr(3 downto 0), - ADDRD(4) => '0', - ADDRD(3 downto 0) => s_axis_waddr(3 downto 0), - DIA(1 downto 0) => offload0_cmd_wr_data(7 downto 6), - DIB(1 downto 0) => offload0_cmd_wr_data(9 downto 8), - DIC(1 downto 0) => offload0_cmd_wr_data(11 downto 10), - DID(1 downto 0) => B"00", - DOA(1 downto 0) => cmd_data(7 downto 6), - DOB(1 downto 0) => cmd_data(9 downto 8), - DOC(1 downto 0) => cmd_data(11 downto 10), - DOD(1 downto 0) => NLW_ram_reg_0_15_6_11_DOD_UNCONNECTED(1 downto 0), - WCLK => s_axi_aclk, - WE => s_mem_write - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity \system_bd_axi_spi_engine_0_0_util_axis_fifo__parameterized0\ is - port ( - s_axis_ready_reg : out STD_LOGIC; - m_axis_valid_reg : out STD_LOGIC; - Q : out STD_LOGIC_VECTOR ( 5 downto 0 ); - \up_irq_mask_reg[0]\ : out STD_LOGIC; - \level_reg[4]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); - m_axis_data : out STD_LOGIC_VECTOR ( 7 downto 0 ); - up_sw_reset : in STD_LOGIC; - s_axi_aclk : in STD_LOGIC; - DI : in STD_LOGIC_VECTOR ( 0 to 0 ); - sdi_data_valid : in STD_LOGIC; - p_0_in : in STD_LOGIC; - irq_reg : in STD_LOGIC_VECTOR ( 3 downto 0 ); - up_irq_source : in STD_LOGIC_VECTOR ( 1 downto 0 ); - irq_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 ); - m_axis_valid_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 ); - spi_clk : in STD_LOGIC; - sdi_data : in STD_LOGIC_VECTOR ( 7 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of \system_bd_axi_spi_engine_0_0_util_axis_fifo__parameterized0\ : entity is "util_axis_fifo"; -end \system_bd_axi_spi_engine_0_0_util_axis_fifo__parameterized0\; - -architecture STRUCTURE of \system_bd_axi_spi_engine_0_0_util_axis_fifo__parameterized0\ is - signal i_address_sync_n_10 : STD_LOGIC; - signal i_address_sync_n_11 : STD_LOGIC; - signal i_address_sync_n_12 : STD_LOGIC; - signal i_address_sync_n_13 : STD_LOGIC; - signal i_address_sync_n_14 : STD_LOGIC; - signal i_address_sync_n_15 : STD_LOGIC; - signal i_address_sync_n_16 : STD_LOGIC; - signal i_address_sync_n_17 : STD_LOGIC; - signal i_address_sync_n_8 : STD_LOGIC; - signal i_address_sync_n_9 : STD_LOGIC; - signal p_1_in : STD_LOGIC; - signal NLW_ram_reg_0_31_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); - signal NLW_ram_reg_0_31_6_7_DOB_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); - signal NLW_ram_reg_0_31_6_7_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); - signal NLW_ram_reg_0_31_6_7_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); - attribute METHODOLOGY_DRC_VIOS : string; - attribute METHODOLOGY_DRC_VIOS of ram_reg_0_31_0_5 : label is ""; - attribute RTL_RAM_BITS : integer; - attribute RTL_RAM_BITS of ram_reg_0_31_0_5 : label is 256; - attribute RTL_RAM_NAME : string; - attribute RTL_RAM_NAME of ram_reg_0_31_0_5 : label is "i_sdi_fifo/ram"; - attribute ram_addr_begin : integer; - attribute ram_addr_begin of ram_reg_0_31_0_5 : label is 0; - attribute ram_addr_end : integer; - attribute ram_addr_end of ram_reg_0_31_0_5 : label is 31; - attribute ram_offset : integer; - attribute ram_offset of ram_reg_0_31_0_5 : label is 0; - attribute ram_slice_begin : integer; - attribute ram_slice_begin of ram_reg_0_31_0_5 : label is 0; - attribute ram_slice_end : integer; - attribute ram_slice_end of ram_reg_0_31_0_5 : label is 5; - attribute METHODOLOGY_DRC_VIOS of ram_reg_0_31_6_7 : label is ""; - attribute RTL_RAM_BITS of ram_reg_0_31_6_7 : label is 256; - attribute RTL_RAM_NAME of ram_reg_0_31_6_7 : label is "i_sdi_fifo/ram"; - attribute ram_addr_begin of ram_reg_0_31_6_7 : label is 0; - attribute ram_addr_end of ram_reg_0_31_6_7 : label is 31; - attribute ram_offset of ram_reg_0_31_6_7 : label is 0; - attribute ram_slice_begin of ram_reg_0_31_6_7 : label is 6; - attribute ram_slice_end of ram_reg_0_31_6_7 : label is 7; -begin -i_address_sync: entity work.\system_bd_axi_spi_engine_0_0_fifo_address_sync__parameterized0_1\ - port map ( - DI(0) => DI(0), - Q(5 downto 0) => Q(5 downto 0), - irq_reg(3 downto 0) => irq_reg(3 downto 0), - irq_reg_0(0) => irq_reg_0(0), - \level_reg[4]_0\(0) => \level_reg[4]\(0), - \m_axis_raddr_reg[4]_0\(4) => i_address_sync_n_13, - \m_axis_raddr_reg[4]_0\(3) => i_address_sync_n_14, - \m_axis_raddr_reg[4]_0\(2) => i_address_sync_n_15, - \m_axis_raddr_reg[4]_0\(1) => i_address_sync_n_16, - \m_axis_raddr_reg[4]_0\(0) => i_address_sync_n_17, - m_axis_valid_reg_0 => m_axis_valid_reg, - m_axis_valid_reg_1(0) => m_axis_valid_reg_0(0), - p_0_in => p_0_in, - s_axi_aclk => s_axi_aclk, - s_axis_ready_reg_0 => s_axis_ready_reg, - \s_axis_waddr_reg[4]_0\(4) => i_address_sync_n_8, - \s_axis_waddr_reg[4]_0\(3) => i_address_sync_n_9, - \s_axis_waddr_reg[4]_0\(2) => i_address_sync_n_10, - \s_axis_waddr_reg[4]_0\(1) => i_address_sync_n_11, - \s_axis_waddr_reg[4]_0\(0) => i_address_sync_n_12, - s_mem_write => p_1_in, - sdi_data_valid => sdi_data_valid, - \up_irq_mask_reg[0]\ => \up_irq_mask_reg[0]\, - up_irq_source(1 downto 0) => up_irq_source(1 downto 0), - up_sw_reset => up_sw_reset - ); -ram_reg_0_31_0_5: unisim.vcomponents.RAM32M - port map ( - ADDRA(4) => i_address_sync_n_13, - ADDRA(3) => i_address_sync_n_14, - ADDRA(2) => i_address_sync_n_15, - ADDRA(1) => i_address_sync_n_16, - ADDRA(0) => i_address_sync_n_17, - ADDRB(4) => i_address_sync_n_13, - ADDRB(3) => i_address_sync_n_14, - ADDRB(2) => i_address_sync_n_15, - ADDRB(1) => i_address_sync_n_16, - ADDRB(0) => i_address_sync_n_17, - ADDRC(4) => i_address_sync_n_13, - ADDRC(3) => i_address_sync_n_14, - ADDRC(2) => i_address_sync_n_15, - ADDRC(1) => i_address_sync_n_16, - ADDRC(0) => i_address_sync_n_17, - ADDRD(4) => i_address_sync_n_8, - ADDRD(3) => i_address_sync_n_9, - ADDRD(2) => i_address_sync_n_10, - ADDRD(1) => i_address_sync_n_11, - ADDRD(0) => i_address_sync_n_12, - DIA(1 downto 0) => sdi_data(1 downto 0), - DIB(1 downto 0) => sdi_data(3 downto 2), - DIC(1 downto 0) => sdi_data(5 downto 4), - DID(1 downto 0) => B"00", - DOA(1 downto 0) => m_axis_data(1 downto 0), - DOB(1 downto 0) => m_axis_data(3 downto 2), - DOC(1 downto 0) => m_axis_data(5 downto 4), - DOD(1 downto 0) => NLW_ram_reg_0_31_0_5_DOD_UNCONNECTED(1 downto 0), - WCLK => spi_clk, - WE => p_1_in - ); -ram_reg_0_31_6_7: unisim.vcomponents.RAM32M - port map ( - ADDRA(4) => i_address_sync_n_13, - ADDRA(3) => i_address_sync_n_14, - ADDRA(2) => i_address_sync_n_15, - ADDRA(1) => i_address_sync_n_16, - ADDRA(0) => i_address_sync_n_17, - ADDRB(4) => i_address_sync_n_13, - ADDRB(3) => i_address_sync_n_14, - ADDRB(2) => i_address_sync_n_15, - ADDRB(1) => i_address_sync_n_16, - ADDRB(0) => i_address_sync_n_17, - ADDRC(4) => i_address_sync_n_13, - ADDRC(3) => i_address_sync_n_14, - ADDRC(2) => i_address_sync_n_15, - ADDRC(1) => i_address_sync_n_16, - ADDRC(0) => i_address_sync_n_17, - ADDRD(4) => i_address_sync_n_8, - ADDRD(3) => i_address_sync_n_9, - ADDRD(2) => i_address_sync_n_10, - ADDRD(1) => i_address_sync_n_11, - ADDRD(0) => i_address_sync_n_12, - DIA(1 downto 0) => sdi_data(7 downto 6), - DIB(1 downto 0) => B"00", - DIC(1 downto 0) => B"00", - DID(1 downto 0) => B"00", - DOA(1 downto 0) => m_axis_data(7 downto 6), - DOB(1 downto 0) => NLW_ram_reg_0_31_6_7_DOB_UNCONNECTED(1 downto 0), - DOC(1 downto 0) => NLW_ram_reg_0_31_6_7_DOC_UNCONNECTED(1 downto 0), - DOD(1 downto 0) => NLW_ram_reg_0_31_6_7_DOD_UNCONNECTED(1 downto 0), - WCLK => spi_clk, - WE => p_1_in - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity \system_bd_axi_spi_engine_0_0_util_axis_fifo__parameterized0_0\ is - port ( - s_axis_ready_reg : out STD_LOGIC; - m_axis_valid_reg : out STD_LOGIC; - \up_irq_mask_reg[1]\ : out STD_LOGIC; - up_irq_source : out STD_LOGIC_VECTOR ( 0 to 0 ); - \room_reg[5]\ : out STD_LOGIC_VECTOR ( 4 downto 0 ); - sdo_data : out STD_LOGIC_VECTOR ( 7 downto 0 ); - up_sw_reset : in STD_LOGIC; - spi_clk : in STD_LOGIC; - sdo_data_ready : in STD_LOGIC; - Q : in STD_LOGIC_VECTOR ( 0 to 0 ); - \up_rdata_ff_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); - \up_rdata_ff_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); - \level_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); - \level_reg[0]_0\ : in STD_LOGIC; - s_axi_aclk : in STD_LOGIC; - s_mem_write : in STD_LOGIC; - offload0_cmd_wr_data : in STD_LOGIC_VECTOR ( 7 downto 0 ); - E : in STD_LOGIC_VECTOR ( 0 to 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of \system_bd_axi_spi_engine_0_0_util_axis_fifo__parameterized0_0\ : entity is "util_axis_fifo"; -end \system_bd_axi_spi_engine_0_0_util_axis_fifo__parameterized0_0\; - -architecture STRUCTURE of \system_bd_axi_spi_engine_0_0_util_axis_fifo__parameterized0_0\ is - signal i_address_sync_n_10 : STD_LOGIC; - signal i_address_sync_n_11 : STD_LOGIC; - signal i_address_sync_n_2 : STD_LOGIC; - signal i_address_sync_n_3 : STD_LOGIC; - signal i_address_sync_n_4 : STD_LOGIC; - signal i_address_sync_n_5 : STD_LOGIC; - signal i_address_sync_n_6 : STD_LOGIC; - signal i_address_sync_n_7 : STD_LOGIC; - signal i_address_sync_n_8 : STD_LOGIC; - signal i_address_sync_n_9 : STD_LOGIC; - signal NLW_ram_reg_0_31_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); - signal NLW_ram_reg_0_31_6_7_DOB_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); - signal NLW_ram_reg_0_31_6_7_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); - signal NLW_ram_reg_0_31_6_7_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); - attribute METHODOLOGY_DRC_VIOS : string; - attribute METHODOLOGY_DRC_VIOS of ram_reg_0_31_0_5 : label is ""; - attribute RTL_RAM_BITS : integer; - attribute RTL_RAM_BITS of ram_reg_0_31_0_5 : label is 256; - attribute RTL_RAM_NAME : string; - attribute RTL_RAM_NAME of ram_reg_0_31_0_5 : label is "i_sdo_fifo/ram"; - attribute ram_addr_begin : integer; - attribute ram_addr_begin of ram_reg_0_31_0_5 : label is 0; - attribute ram_addr_end : integer; - attribute ram_addr_end of ram_reg_0_31_0_5 : label is 31; - attribute ram_offset : integer; - attribute ram_offset of ram_reg_0_31_0_5 : label is 0; - attribute ram_slice_begin : integer; - attribute ram_slice_begin of ram_reg_0_31_0_5 : label is 0; - attribute ram_slice_end : integer; - attribute ram_slice_end of ram_reg_0_31_0_5 : label is 5; - attribute METHODOLOGY_DRC_VIOS of ram_reg_0_31_6_7 : label is ""; - attribute RTL_RAM_BITS of ram_reg_0_31_6_7 : label is 256; - attribute RTL_RAM_NAME of ram_reg_0_31_6_7 : label is "i_sdo_fifo/ram"; - attribute ram_addr_begin of ram_reg_0_31_6_7 : label is 0; - attribute ram_addr_end of ram_reg_0_31_6_7 : label is 31; - attribute ram_offset of ram_reg_0_31_6_7 : label is 0; - attribute ram_slice_begin of ram_reg_0_31_6_7 : label is 6; - attribute ram_slice_end of ram_reg_0_31_6_7 : label is 7; -begin -i_address_sync: entity work.\system_bd_axi_spi_engine_0_0_fifo_address_sync__parameterized0\ - port map ( - E(0) => E(0), - Q(4) => i_address_sync_n_2, - Q(3) => i_address_sync_n_3, - Q(2) => i_address_sync_n_4, - Q(1) => i_address_sync_n_5, - Q(0) => i_address_sync_n_6, - \level_reg[0]_0\(0) => \level_reg[0]\(0), - \level_reg[0]_1\ => \level_reg[0]_0\, - \m_axis_raddr_reg[4]_0\(4) => i_address_sync_n_7, - \m_axis_raddr_reg[4]_0\(3) => i_address_sync_n_8, - \m_axis_raddr_reg[4]_0\(2) => i_address_sync_n_9, - \m_axis_raddr_reg[4]_0\(1) => i_address_sync_n_10, - \m_axis_raddr_reg[4]_0\(0) => i_address_sync_n_11, - m_axis_valid_reg_0 => m_axis_valid_reg, - \room_reg[5]_0\(4 downto 0) => \room_reg[5]\(4 downto 0), - s_axis_ready_reg_0 => s_axis_ready_reg, - sdo_data_ready => sdo_data_ready, - spi_clk => spi_clk, - \up_irq_mask_reg[1]\ => \up_irq_mask_reg[1]\, - up_irq_source(0) => up_irq_source(0), - \up_rdata_ff_reg[1]\(0) => Q(0), - \up_rdata_ff_reg[1]_0\(0) => \up_rdata_ff_reg[1]\(0), - \up_rdata_ff_reg[1]_1\(1 downto 0) => \up_rdata_ff_reg[1]_0\(1 downto 0), - up_sw_reset => up_sw_reset - ); -ram_reg_0_31_0_5: unisim.vcomponents.RAM32M - port map ( - ADDRA(4) => i_address_sync_n_7, - ADDRA(3) => i_address_sync_n_8, - ADDRA(2) => i_address_sync_n_9, - ADDRA(1) => i_address_sync_n_10, - ADDRA(0) => i_address_sync_n_11, - ADDRB(4) => i_address_sync_n_7, - ADDRB(3) => i_address_sync_n_8, - ADDRB(2) => i_address_sync_n_9, - ADDRB(1) => i_address_sync_n_10, - ADDRB(0) => i_address_sync_n_11, - ADDRC(4) => i_address_sync_n_7, - ADDRC(3) => i_address_sync_n_8, - ADDRC(2) => i_address_sync_n_9, - ADDRC(1) => i_address_sync_n_10, - ADDRC(0) => i_address_sync_n_11, - ADDRD(4) => i_address_sync_n_2, - ADDRD(3) => i_address_sync_n_3, - ADDRD(2) => i_address_sync_n_4, - ADDRD(1) => i_address_sync_n_5, - ADDRD(0) => i_address_sync_n_6, - DIA(1 downto 0) => offload0_cmd_wr_data(1 downto 0), - DIB(1 downto 0) => offload0_cmd_wr_data(3 downto 2), - DIC(1 downto 0) => offload0_cmd_wr_data(5 downto 4), - DID(1 downto 0) => B"00", - DOA(1 downto 0) => sdo_data(1 downto 0), - DOB(1 downto 0) => sdo_data(3 downto 2), - DOC(1 downto 0) => sdo_data(5 downto 4), - DOD(1 downto 0) => NLW_ram_reg_0_31_0_5_DOD_UNCONNECTED(1 downto 0), - WCLK => s_axi_aclk, - WE => s_mem_write - ); -ram_reg_0_31_6_7: unisim.vcomponents.RAM32M - port map ( - ADDRA(4) => i_address_sync_n_7, - ADDRA(3) => i_address_sync_n_8, - ADDRA(2) => i_address_sync_n_9, - ADDRA(1) => i_address_sync_n_10, - ADDRA(0) => i_address_sync_n_11, - ADDRB(4) => i_address_sync_n_7, - ADDRB(3) => i_address_sync_n_8, - ADDRB(2) => i_address_sync_n_9, - ADDRB(1) => i_address_sync_n_10, - ADDRB(0) => i_address_sync_n_11, - ADDRC(4) => i_address_sync_n_7, - ADDRC(3) => i_address_sync_n_8, - ADDRC(2) => i_address_sync_n_9, - ADDRC(1) => i_address_sync_n_10, - ADDRC(0) => i_address_sync_n_11, - ADDRD(4) => i_address_sync_n_2, - ADDRD(3) => i_address_sync_n_3, - ADDRD(2) => i_address_sync_n_4, - ADDRD(1) => i_address_sync_n_5, - ADDRD(0) => i_address_sync_n_6, - DIA(1 downto 0) => offload0_cmd_wr_data(7 downto 6), - DIB(1 downto 0) => B"00", - DIC(1 downto 0) => B"00", - DID(1 downto 0) => B"00", - DOA(1 downto 0) => sdo_data(7 downto 6), - DOB(1 downto 0) => NLW_ram_reg_0_31_6_7_DOB_UNCONNECTED(1 downto 0), - DOC(1 downto 0) => NLW_ram_reg_0_31_6_7_DOC_UNCONNECTED(1 downto 0), - DOD(1 downto 0) => NLW_ram_reg_0_31_6_7_DOD_UNCONNECTED(1 downto 0), - WCLK => s_axi_aclk, - WE => s_mem_write - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity system_bd_axi_spi_engine_0_0_axi_spi_engine is - port ( - s_axi_aclk : in STD_LOGIC; - s_axi_aresetn : in STD_LOGIC; - s_axi_awvalid : in STD_LOGIC; - s_axi_awaddr : in STD_LOGIC_VECTOR ( 15 downto 0 ); - s_axi_awready : out STD_LOGIC; - s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); - s_axi_wvalid : in STD_LOGIC; - s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); - s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); - s_axi_wready : out STD_LOGIC; - s_axi_bvalid : out STD_LOGIC; - s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); - s_axi_bready : in STD_LOGIC; - s_axi_arvalid : in STD_LOGIC; - s_axi_araddr : in STD_LOGIC_VECTOR ( 15 downto 0 ); - s_axi_arready : out STD_LOGIC; - s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); - s_axi_rvalid : out STD_LOGIC; - s_axi_rready : in STD_LOGIC; - s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); - s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); - up_clk : in STD_LOGIC; - up_rstn : in STD_LOGIC; - up_wreq : in STD_LOGIC; - up_waddr : in STD_LOGIC_VECTOR ( 13 downto 0 ); - up_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); - up_wack : out STD_LOGIC; - up_rreq : in STD_LOGIC; - up_raddr : in STD_LOGIC_VECTOR ( 13 downto 0 ); - up_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); - up_rack : out STD_LOGIC; - irq : out STD_LOGIC; - spi_clk : in STD_LOGIC; - spi_resetn : out STD_LOGIC; - cmd_ready : in STD_LOGIC; - cmd_valid : out STD_LOGIC; - cmd_data : out STD_LOGIC_VECTOR ( 15 downto 0 ); - sdo_data_ready : in STD_LOGIC; - sdo_data_valid : out STD_LOGIC; - sdo_data : out STD_LOGIC_VECTOR ( 7 downto 0 ); - sdi_data_ready : out STD_LOGIC; - sdi_data_valid : in STD_LOGIC; - sdi_data : in STD_LOGIC_VECTOR ( 7 downto 0 ); - sync_ready : out STD_LOGIC; - sync_valid : in STD_LOGIC; - sync_data : in STD_LOGIC_VECTOR ( 7 downto 0 ); - offload0_cmd_wr_en : out STD_LOGIC; - offload0_cmd_wr_data : out STD_LOGIC_VECTOR ( 15 downto 0 ); - offload0_sdo_wr_en : out STD_LOGIC; - offload0_sdo_wr_data : out STD_LOGIC_VECTOR ( 7 downto 0 ); - offload0_mem_reset : out STD_LOGIC; - offload0_enable : out STD_LOGIC; - offload0_enabled : in STD_LOGIC; - offload_sync_ready : out STD_LOGIC; - offload_sync_valid : in STD_LOGIC; - offload_sync_data : in STD_LOGIC_VECTOR ( 7 downto 0 ) - ); - attribute ASYNC_SPI_CLK : string; - attribute ASYNC_SPI_CLK of system_bd_axi_spi_engine_0_0_axi_spi_engine : entity is "1'b0"; - attribute CMD_FIFO_ADDRESS_WIDTH : integer; - attribute CMD_FIFO_ADDRESS_WIDTH of system_bd_axi_spi_engine_0_0_axi_spi_engine : entity is 4; - attribute DATA_WIDTH : string; - attribute DATA_WIDTH of system_bd_axi_spi_engine_0_0_axi_spi_engine : entity is "16'b0000000000001000"; - attribute ID : integer; - attribute ID of system_bd_axi_spi_engine_0_0_axi_spi_engine : entity is 0; - attribute MM_IF_TYPE : integer; - attribute MM_IF_TYPE of system_bd_axi_spi_engine_0_0_axi_spi_engine : entity is 0; - attribute NUM_OFFLOAD : integer; - attribute NUM_OFFLOAD of system_bd_axi_spi_engine_0_0_axi_spi_engine : entity is 0; - attribute NUM_OF_SDI : string; - attribute NUM_OF_SDI of system_bd_axi_spi_engine_0_0_axi_spi_engine : entity is "8'b00000001"; - attribute OFFLOAD0_CMD_MEM_ADDRESS_WIDTH : integer; - attribute OFFLOAD0_CMD_MEM_ADDRESS_WIDTH of system_bd_axi_spi_engine_0_0_axi_spi_engine : entity is 4; - attribute OFFLOAD0_SDO_MEM_ADDRESS_WIDTH : integer; - attribute OFFLOAD0_SDO_MEM_ADDRESS_WIDTH of system_bd_axi_spi_engine_0_0_axi_spi_engine : entity is 4; - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of system_bd_axi_spi_engine_0_0_axi_spi_engine : entity is "axi_spi_engine"; - attribute PCORE_VERSION : integer; - attribute PCORE_VERSION of system_bd_axi_spi_engine_0_0_axi_spi_engine : entity is 65649; - attribute SDI_FIFO_ADDRESS_WIDTH : integer; - attribute SDI_FIFO_ADDRESS_WIDTH of system_bd_axi_spi_engine_0_0_axi_spi_engine : entity is 5; - attribute SDO_FIFO_ADDRESS_WIDTH : integer; - attribute SDO_FIFO_ADDRESS_WIDTH of system_bd_axi_spi_engine_0_0_axi_spi_engine : entity is 5; - attribute SYNC_FIFO_ADDRESS_WIDTH : integer; - attribute SYNC_FIFO_ADDRESS_WIDTH of system_bd_axi_spi_engine_0_0_axi_spi_engine : entity is 4; - attribute S_AXI : integer; - attribute S_AXI of system_bd_axi_spi_engine_0_0_axi_spi_engine : entity is 0; - attribute UP_FIFO : integer; - attribute UP_FIFO of system_bd_axi_spi_engine_0_0_axi_spi_engine : entity is 1; -end system_bd_axi_spi_engine_0_0_axi_spi_engine; - -architecture STRUCTURE of system_bd_axi_spi_engine_0_0_axi_spi_engine is - signal \\ : STD_LOGIC; - signal \\ : STD_LOGIC; - signal cmd_fifo_room : STD_LOGIC_VECTOR ( 4 downto 1 ); - signal \i_address_sync/level_next1\ : STD_LOGIC; - signal \i_address_sync/level_reg\ : STD_LOGIC_VECTOR ( 0 to 0 ); - signal \i_address_sync/p_0_in\ : STD_LOGIC; - signal \i_address_sync/p_1_in\ : STD_LOGIC; - signal \i_address_sync/p_1_in_0\ : STD_LOGIC; - signal i_cmd_fifo_n_0 : STD_LOGIC; - signal i_sdi_fifo_n_1 : STD_LOGIC; - signal i_sdi_fifo_n_8 : STD_LOGIC; - signal i_sdo_fifo_n_0 : STD_LOGIC; - signal i_sdo_fifo_n_2 : STD_LOGIC; - signal i_up_axi_n_0 : STD_LOGIC; - signal i_up_axi_n_10 : STD_LOGIC; - signal i_up_axi_n_12 : STD_LOGIC; - signal i_up_axi_n_18 : STD_LOGIC; - signal i_up_axi_n_21 : STD_LOGIC; - signal i_up_axi_n_22 : STD_LOGIC; - signal i_up_axi_n_23 : STD_LOGIC; - signal i_up_axi_n_24 : STD_LOGIC; - signal i_up_axi_n_25 : STD_LOGIC; - signal i_up_axi_n_26 : STD_LOGIC; - signal i_up_axi_n_27 : STD_LOGIC; - signal i_up_axi_n_28 : STD_LOGIC; - signal i_up_axi_n_29 : STD_LOGIC; - signal i_up_axi_n_30 : STD_LOGIC; - signal i_up_axi_n_31 : STD_LOGIC; - signal i_up_axi_n_32 : STD_LOGIC; - signal i_up_axi_n_33 : STD_LOGIC; - signal i_up_axi_n_34 : STD_LOGIC; - signal i_up_axi_n_35 : STD_LOGIC; - signal i_up_axi_n_36 : STD_LOGIC; - signal i_up_axi_n_37 : STD_LOGIC; - signal i_up_axi_n_38 : STD_LOGIC; - signal i_up_axi_n_39 : STD_LOGIC; - signal i_up_axi_n_40 : STD_LOGIC; - signal i_up_axi_n_41 : STD_LOGIC; - signal i_up_axi_n_42 : STD_LOGIC; - signal i_up_axi_n_43 : STD_LOGIC; - signal i_up_axi_n_44 : STD_LOGIC; - signal i_up_axi_n_45 : STD_LOGIC; - signal i_up_axi_n_46 : STD_LOGIC; - signal i_up_axi_n_49 : STD_LOGIC; - signal i_up_axi_n_50 : STD_LOGIC; - signal i_up_axi_n_51 : STD_LOGIC; - signal i_up_axi_n_52 : STD_LOGIC; - signal i_up_axi_n_53 : STD_LOGIC; - signal i_up_axi_n_54 : STD_LOGIC; - signal i_up_axi_n_55 : STD_LOGIC; - signal i_up_axi_n_56 : STD_LOGIC; - signal i_up_axi_n_89 : STD_LOGIC; - signal i_up_axi_n_90 : STD_LOGIC; - signal i_up_axi_n_91 : STD_LOGIC; - signal m_axis_data : STD_LOGIC_VECTOR ( 7 downto 0 ); - signal \^offload0_cmd_wr_data\ : STD_LOGIC_VECTOR ( 15 downto 1 ); - signal \^offload0_enable\ : STD_LOGIC; - signal \^offload0_mem_reset\ : STD_LOGIC; - signal \^offload0_sdo_wr_data\ : STD_LOGIC_VECTOR ( 7 downto 0 ); - signal offload_sync_id : STD_LOGIC_VECTOR ( 7 downto 0 ); - signal s_mem_write : STD_LOGIC; - signal \s_mem_write__0\ : STD_LOGIC; - signal \^sdi_data_ready\ : STD_LOGIC; - signal sdi_fifo_level : STD_LOGIC_VECTOR ( 5 downto 0 ); - signal sdo_fifo_room : STD_LOGIC_VECTOR ( 5 downto 0 ); - signal sync_id : STD_LOGIC_VECTOR ( 7 downto 0 ); - signal \up_irq_mask_reg_n_0_[0]\ : STD_LOGIC; - signal \up_irq_mask_reg_n_0_[1]\ : STD_LOGIC; - signal \up_irq_mask_reg_n_0_[2]\ : STD_LOGIC; - signal \up_irq_mask_reg_n_0_[3]\ : STD_LOGIC; - signal up_irq_source : STD_LOGIC_VECTOR ( 3 to 3 ); - signal \up_irq_source__0\ : STD_LOGIC_VECTOR ( 2 downto 0 ); - signal up_rack_ff : STD_LOGIC; - signal up_raddr_s : STD_LOGIC_VECTOR ( 4 downto 2 ); - signal up_rdata_ff : STD_LOGIC_VECTOR ( 31 downto 0 ); - signal up_rreq_s : STD_LOGIC; - signal up_scratch : STD_LOGIC; - signal \up_scratch_reg_n_0_[0]\ : STD_LOGIC; - signal \up_scratch_reg_n_0_[10]\ : STD_LOGIC; - signal \up_scratch_reg_n_0_[11]\ : STD_LOGIC; - signal \up_scratch_reg_n_0_[12]\ : STD_LOGIC; - signal \up_scratch_reg_n_0_[13]\ : STD_LOGIC; - signal \up_scratch_reg_n_0_[14]\ : STD_LOGIC; - signal \up_scratch_reg_n_0_[15]\ : STD_LOGIC; - signal \up_scratch_reg_n_0_[16]\ : STD_LOGIC; - signal \up_scratch_reg_n_0_[17]\ : STD_LOGIC; - signal \up_scratch_reg_n_0_[18]\ : STD_LOGIC; - signal \up_scratch_reg_n_0_[19]\ : STD_LOGIC; - signal \up_scratch_reg_n_0_[1]\ : STD_LOGIC; - signal \up_scratch_reg_n_0_[20]\ : STD_LOGIC; - signal \up_scratch_reg_n_0_[21]\ : STD_LOGIC; - signal \up_scratch_reg_n_0_[22]\ : STD_LOGIC; - signal \up_scratch_reg_n_0_[23]\ : STD_LOGIC; - signal \up_scratch_reg_n_0_[24]\ : STD_LOGIC; - signal \up_scratch_reg_n_0_[25]\ : STD_LOGIC; - signal \up_scratch_reg_n_0_[26]\ : STD_LOGIC; - signal \up_scratch_reg_n_0_[27]\ : STD_LOGIC; - signal \up_scratch_reg_n_0_[28]\ : STD_LOGIC; - signal \up_scratch_reg_n_0_[29]\ : STD_LOGIC; - signal \up_scratch_reg_n_0_[2]\ : STD_LOGIC; - signal \up_scratch_reg_n_0_[30]\ : STD_LOGIC; - signal \up_scratch_reg_n_0_[31]\ : STD_LOGIC; - signal \up_scratch_reg_n_0_[3]\ : STD_LOGIC; - signal \up_scratch_reg_n_0_[4]\ : STD_LOGIC; - signal \up_scratch_reg_n_0_[5]\ : STD_LOGIC; - signal \up_scratch_reg_n_0_[6]\ : STD_LOGIC; - signal \up_scratch_reg_n_0_[7]\ : STD_LOGIC; - signal \up_scratch_reg_n_0_[8]\ : STD_LOGIC; - signal \up_scratch_reg_n_0_[9]\ : STD_LOGIC; - signal up_sw_reset : STD_LOGIC; - signal up_wack_ff : STD_LOGIC; - signal up_waddr_s : STD_LOGIC_VECTOR ( 0 to 0 ); - signal up_wdata_int : STD_LOGIC_VECTOR ( 31 downto 16 ); - signal up_wreq_s : STD_LOGIC; -begin - offload0_cmd_wr_data(15 downto 8) <= \^offload0_cmd_wr_data\(15 downto 8); - offload0_cmd_wr_data(7 downto 3) <= \^offload0_sdo_wr_data\(7 downto 3); - offload0_cmd_wr_data(2 downto 1) <= \^offload0_cmd_wr_data\(2 downto 1); - offload0_cmd_wr_data(0) <= \^offload0_sdo_wr_data\(0); - offload0_enable <= \^offload0_enable\; - offload0_mem_reset <= \^offload0_mem_reset\; - offload0_sdo_wr_data(7 downto 3) <= \^offload0_sdo_wr_data\(7 downto 3); - offload0_sdo_wr_data(2 downto 1) <= \^offload0_cmd_wr_data\(2 downto 1); - offload0_sdo_wr_data(0) <= \^offload0_sdo_wr_data\(0); - offload_sync_ready <= \\; - s_axi_bresp(1) <= \\; - s_axi_bresp(0) <= \\; - s_axi_rresp(1) <= \\; - s_axi_rresp(0) <= \\; - sdi_data_ready <= \^sdi_data_ready\; - sync_ready <= \\; - up_rack <= \\; - up_rdata(31) <= \\; - up_rdata(30) <= \\; - up_rdata(29) <= \\; - up_rdata(28) <= \\; - up_rdata(27) <= \\; - up_rdata(26) <= \\; - up_rdata(25) <= \\; - up_rdata(24) <= \\; - up_rdata(23) <= \\; - up_rdata(22) <= \\; - up_rdata(21) <= \\; - up_rdata(20) <= \\; - up_rdata(19) <= \\; - up_rdata(18) <= \\; - up_rdata(17) <= \\; - up_rdata(16) <= \\; - up_rdata(15) <= \\; - up_rdata(14) <= \\; - up_rdata(13) <= \\; - up_rdata(12) <= \\; - up_rdata(11) <= \\; - up_rdata(10) <= \\; - up_rdata(9) <= \\; - up_rdata(8) <= \\; - up_rdata(7) <= \\; - up_rdata(6) <= \\; - up_rdata(5) <= \\; - up_rdata(4) <= \\; - up_rdata(3) <= \\; - up_rdata(2) <= \\; - up_rdata(1) <= \\; - up_rdata(0) <= \\; - up_wack <= \\; -GND: unisim.vcomponents.GND - port map ( - G => \\ - ); -VCC: unisim.vcomponents.VCC - port map ( - P => \\ - ); -i_cmd_fifo: entity work.system_bd_axi_spi_engine_0_0_util_axis_fifo - port map ( - Q(0) => up_waddr_s(0), - cmd_data(15 downto 0) => cmd_data(15 downto 0), - cmd_ready => cmd_ready, - \level_reg[0]\(0) => \i_address_sync/level_reg\(0), - \level_reg[0]_0\ => i_up_axi_n_10, - m_axis_valid_reg => cmd_valid, - offload0_cmd_wr_data(15 downto 8) => \^offload0_cmd_wr_data\(15 downto 8), - offload0_cmd_wr_data(7 downto 3) => \^offload0_sdo_wr_data\(7 downto 3), - offload0_cmd_wr_data(2 downto 1) => \^offload0_cmd_wr_data\(2 downto 1), - offload0_cmd_wr_data(0) => \^offload0_sdo_wr_data\(0), - p_1_in => \i_address_sync/p_1_in\, - \room_reg[4]\(3 downto 0) => cmd_fifo_room(4 downto 1), - s_axi_aclk => s_axi_aclk, - s_axis_ready_reg => i_cmd_fifo_n_0, - s_mem_write => s_mem_write, - spi_clk => spi_clk, - up_irq_source(0) => \up_irq_source__0\(0), - up_sw_reset => up_sw_reset - ); -i_sdi_fifo: entity work.\system_bd_axi_spi_engine_0_0_util_axis_fifo__parameterized0\ - port map ( - DI(0) => i_up_axi_n_55, - Q(5 downto 0) => sdi_fifo_level(5 downto 0), - irq_reg(3) => \up_irq_mask_reg_n_0_[3]\, - irq_reg(2) => \up_irq_mask_reg_n_0_[2]\, - irq_reg(1) => \up_irq_mask_reg_n_0_[1]\, - irq_reg(0) => \up_irq_mask_reg_n_0_[0]\, - irq_reg_0(0) => up_irq_source(3), - \level_reg[4]\(0) => \up_irq_source__0\(2), - m_axis_data(7 downto 0) => m_axis_data(7 downto 0), - m_axis_valid_reg => i_sdi_fifo_n_1, - m_axis_valid_reg_0(0) => \i_address_sync/level_next1\, - p_0_in => \i_address_sync/p_0_in\, - s_axi_aclk => s_axi_aclk, - s_axis_ready_reg => \^sdi_data_ready\, - sdi_data(7 downto 0) => sdi_data(7 downto 0), - sdi_data_valid => sdi_data_valid, - spi_clk => spi_clk, - \up_irq_mask_reg[0]\ => i_sdi_fifo_n_8, - up_irq_source(1 downto 0) => \up_irq_source__0\(1 downto 0), - up_sw_reset => up_sw_reset - ); -i_sdo_fifo: entity work.\system_bd_axi_spi_engine_0_0_util_axis_fifo__parameterized0_0\ - port map ( - E(0) => \i_address_sync/p_1_in_0\, - Q(0) => \up_irq_mask_reg_n_0_[1]\, - \level_reg[0]\(0) => up_waddr_s(0), - \level_reg[0]_0\ => i_up_axi_n_10, - m_axis_valid_reg => sdo_data_valid, - offload0_cmd_wr_data(7 downto 3) => \^offload0_sdo_wr_data\(7 downto 3), - offload0_cmd_wr_data(2 downto 1) => \^offload0_cmd_wr_data\(2 downto 1), - offload0_cmd_wr_data(0) => \^offload0_sdo_wr_data\(0), - \room_reg[5]\(4 downto 1) => sdo_fifo_room(5 downto 2), - \room_reg[5]\(0) => sdo_fifo_room(0), - s_axi_aclk => s_axi_aclk, - s_axis_ready_reg => i_sdo_fifo_n_0, - s_mem_write => \s_mem_write__0\, - sdo_data(7 downto 0) => sdo_data(7 downto 0), - sdo_data_ready => sdo_data_ready, - spi_clk => spi_clk, - \up_irq_mask_reg[1]\ => i_sdo_fifo_n_2, - up_irq_source(0) => \up_irq_source__0\(1), - \up_rdata_ff_reg[1]\(0) => offload_sync_id(1), - \up_rdata_ff_reg[1]_0\(1) => up_raddr_s(4), - \up_rdata_ff_reg[1]_0\(0) => up_raddr_s(2), - up_sw_reset => up_sw_reset - ); -i_up_axi: entity work.system_bd_axi_spi_engine_0_0_up_axi - port map ( - DI(0) => i_up_axi_n_55, - E(0) => i_up_axi_n_12, - Q(0) => up_waddr_s(0), - m_axis_data(7 downto 0) => m_axis_data(7 downto 0), - \m_axis_raddr_reg[0]\ => i_sdi_fifo_n_1, - offload0_cmd_wr_en => offload0_cmd_wr_en, - offload0_enable => \^offload0_enable\, - offload0_enabled => offload0_enabled, - offload0_mem_reset => \^offload0_mem_reset\, - offload0_sdo_wr_en => offload0_sdo_wr_en, - p_0_in => \i_address_sync/p_0_in\, - p_1_in => \i_address_sync/p_1_in\, - s_axi_aclk => s_axi_aclk, - s_axi_araddr(13 downto 0) => s_axi_araddr(15 downto 2), - s_axi_aresetn => s_axi_aresetn, - s_axi_aresetn_0 => i_up_axi_n_0, - s_axi_arready => s_axi_arready, - s_axi_arvalid => s_axi_arvalid, - s_axi_awaddr(13 downto 0) => s_axi_awaddr(15 downto 2), - s_axi_awready => s_axi_awready, - s_axi_awvalid => s_axi_awvalid, - s_axi_bready => s_axi_bready, - s_axi_bvalid => s_axi_bvalid, - s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0), - s_axi_rready => s_axi_rready, - s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0), - s_axi_wready => s_axi_wready, - s_axi_wvalid => s_axi_wvalid, - s_axis_ready_reg => \s_mem_write__0\, - s_axis_ready_reg_0(0) => \i_address_sync/p_1_in_0\, - \s_axis_waddr_reg[0]\ => i_cmd_fifo_n_0, - \s_axis_waddr_reg[0]_0\ => i_sdo_fifo_n_0, - s_mem_write => s_mem_write, - sdi_data_ready => \^sdi_data_ready\, - sdi_data_valid => sdi_data_valid, - sdi_data_valid_0(0) => \i_address_sync/level_next1\, - sync_id_pending_reg(0) => up_irq_source(3), - sync_valid => sync_valid, - up_axi_rvalid_int_reg_0 => s_axi_rvalid, - up_irq_source(2 downto 0) => \up_irq_source__0\(2 downto 0), - up_rack_ff => up_rack_ff, - \up_raddr_int_reg[0]_0\ => i_up_axi_n_21, - \up_raddr_int_reg[0]_1\ => i_up_axi_n_22, - \up_raddr_int_reg[3]_0\ => i_up_axi_n_23, - \up_raddr_int_reg[3]_1\ => i_up_axi_n_49, - \up_raddr_int_reg[3]_2\ => i_up_axi_n_50, - \up_raddr_int_reg[3]_3\ => i_up_axi_n_51, - \up_raddr_int_reg[3]_4\ => i_up_axi_n_52, - \up_raddr_int_reg[4]_0\(1) => up_raddr_s(4), - \up_raddr_int_reg[4]_0\(0) => up_raddr_s(2), - \up_raddr_int_reg[5]_0\ => i_up_axi_n_18, - \up_raddr_int_reg[6]_0\ => i_up_axi_n_54, - \up_raddr_int_reg[9]_0\ => i_up_axi_n_53, - up_rdata_ff(31 downto 0) => up_rdata_ff(31 downto 0), - \up_rdata_ff[0]_i_8_0\(0) => \i_address_sync/level_reg\(0), - \up_rdata_ff[3]_i_3_0\(3) => \up_irq_mask_reg_n_0_[3]\, - \up_rdata_ff[3]_i_3_0\(2) => \up_irq_mask_reg_n_0_[2]\, - \up_rdata_ff[3]_i_3_0\(1) => \up_irq_mask_reg_n_0_[1]\, - \up_rdata_ff[3]_i_3_0\(0) => \up_irq_mask_reg_n_0_[0]\, - \up_rdata_ff_reg[1]\ => i_sdo_fifo_n_2, - \up_rdata_ff_reg[31]\(31) => \up_scratch_reg_n_0_[31]\, - \up_rdata_ff_reg[31]\(30) => \up_scratch_reg_n_0_[30]\, - \up_rdata_ff_reg[31]\(29) => \up_scratch_reg_n_0_[29]\, - \up_rdata_ff_reg[31]\(28) => \up_scratch_reg_n_0_[28]\, - \up_rdata_ff_reg[31]\(27) => \up_scratch_reg_n_0_[27]\, - \up_rdata_ff_reg[31]\(26) => \up_scratch_reg_n_0_[26]\, - \up_rdata_ff_reg[31]\(25) => \up_scratch_reg_n_0_[25]\, - \up_rdata_ff_reg[31]\(24) => \up_scratch_reg_n_0_[24]\, - \up_rdata_ff_reg[31]\(23) => \up_scratch_reg_n_0_[23]\, - \up_rdata_ff_reg[31]\(22) => \up_scratch_reg_n_0_[22]\, - \up_rdata_ff_reg[31]\(21) => \up_scratch_reg_n_0_[21]\, - \up_rdata_ff_reg[31]\(20) => \up_scratch_reg_n_0_[20]\, - \up_rdata_ff_reg[31]\(19) => \up_scratch_reg_n_0_[19]\, - \up_rdata_ff_reg[31]\(18) => \up_scratch_reg_n_0_[18]\, - \up_rdata_ff_reg[31]\(17) => \up_scratch_reg_n_0_[17]\, - \up_rdata_ff_reg[31]\(16) => \up_scratch_reg_n_0_[16]\, - \up_rdata_ff_reg[31]\(15) => \up_scratch_reg_n_0_[15]\, - \up_rdata_ff_reg[31]\(14) => \up_scratch_reg_n_0_[14]\, - \up_rdata_ff_reg[31]\(13) => \up_scratch_reg_n_0_[13]\, - \up_rdata_ff_reg[31]\(12) => \up_scratch_reg_n_0_[12]\, - \up_rdata_ff_reg[31]\(11) => \up_scratch_reg_n_0_[11]\, - \up_rdata_ff_reg[31]\(10) => \up_scratch_reg_n_0_[10]\, - \up_rdata_ff_reg[31]\(9) => \up_scratch_reg_n_0_[9]\, - \up_rdata_ff_reg[31]\(8) => \up_scratch_reg_n_0_[8]\, - \up_rdata_ff_reg[31]\(7) => \up_scratch_reg_n_0_[7]\, - \up_rdata_ff_reg[31]\(6) => \up_scratch_reg_n_0_[6]\, - \up_rdata_ff_reg[31]\(5) => \up_scratch_reg_n_0_[5]\, - \up_rdata_ff_reg[31]\(4) => \up_scratch_reg_n_0_[4]\, - \up_rdata_ff_reg[31]\(3) => \up_scratch_reg_n_0_[3]\, - \up_rdata_ff_reg[31]\(2) => \up_scratch_reg_n_0_[2]\, - \up_rdata_ff_reg[31]\(1) => \up_scratch_reg_n_0_[1]\, - \up_rdata_ff_reg[31]\(0) => \up_scratch_reg_n_0_[0]\, - \up_rdata_ff_reg[4]\(3 downto 0) => cmd_fifo_room(4 downto 1), - \up_rdata_ff_reg[5]\(5 downto 0) => sdi_fifo_level(5 downto 0), - \up_rdata_ff_reg[5]_0\(4 downto 1) => sdo_fifo_room(5 downto 2), - \up_rdata_ff_reg[5]_0\(0) => sdo_fifo_room(0), - \up_rdata_ff_reg[7]\(6 downto 1) => offload_sync_id(7 downto 2), - \up_rdata_ff_reg[7]\(0) => offload_sync_id(0), - \up_rdata_ff_reg[7]_0\(7 downto 0) => sync_id(7 downto 0), - up_rreq_s => up_rreq_s, - \up_scratch_reg[10]\ => i_up_axi_n_26, - \up_scratch_reg[11]\ => i_up_axi_n_27, - \up_scratch_reg[12]\ => i_up_axi_n_28, - \up_scratch_reg[13]\ => i_up_axi_n_29, - \up_scratch_reg[14]\ => i_up_axi_n_30, - \up_scratch_reg[15]\ => i_up_axi_n_31, - \up_scratch_reg[17]\ => i_up_axi_n_32, - \up_scratch_reg[18]\ => i_up_axi_n_33, - \up_scratch_reg[19]\ => i_up_axi_n_34, - \up_scratch_reg[20]\ => i_up_axi_n_35, - \up_scratch_reg[21]\ => i_up_axi_n_36, - \up_scratch_reg[22]\ => i_up_axi_n_37, - \up_scratch_reg[23]\ => i_up_axi_n_38, - \up_scratch_reg[24]\ => i_up_axi_n_39, - \up_scratch_reg[25]\ => i_up_axi_n_40, - \up_scratch_reg[26]\ => i_up_axi_n_41, - \up_scratch_reg[27]\ => i_up_axi_n_42, - \up_scratch_reg[28]\ => i_up_axi_n_43, - \up_scratch_reg[29]\ => i_up_axi_n_44, - \up_scratch_reg[30]\ => i_up_axi_n_45, - \up_scratch_reg[31]\ => i_up_axi_n_46, - \up_scratch_reg[8]\ => i_up_axi_n_24, - \up_scratch_reg[9]\ => i_up_axi_n_25, - up_sw_reset => up_sw_reset, - up_wack_ff => up_wack_ff, - \up_waddr_int_reg[0]_0\ => i_up_axi_n_89, - \up_waddr_int_reg[2]_0\(0) => up_scratch, - \up_waddr_int_reg[4]_0\ => i_up_axi_n_10, - \up_wdata_int_reg[0]_0\ => i_up_axi_n_56, - \up_wdata_int_reg[0]_1\ => i_up_axi_n_90, - \up_wdata_int_reg[0]_2\ => i_up_axi_n_91, - \up_wdata_int_reg[31]_0\(31 downto 16) => up_wdata_int(31 downto 16), - \up_wdata_int_reg[31]_0\(15 downto 8) => \^offload0_cmd_wr_data\(15 downto 8), - \up_wdata_int_reg[31]_0\(7 downto 3) => \^offload0_sdo_wr_data\(7 downto 3), - \up_wdata_int_reg[31]_0\(2 downto 1) => \^offload0_cmd_wr_data\(2 downto 1), - \up_wdata_int_reg[31]_0\(0) => \^offload0_sdo_wr_data\(0), - up_wreq_s => up_wreq_s - ); -irq_reg: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => '1', - D => i_sdi_fifo_n_8, - Q => irq, - R => i_up_axi_n_0 - ); -offload0_enable_reg_reg: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => '1', - D => i_up_axi_n_90, - Q => \^offload0_enable\, - R => up_sw_reset - ); -offload0_mem_reset_reg_reg: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => '1', - D => i_up_axi_n_91, - Q => \^offload0_mem_reset\, - R => up_sw_reset - ); -\offload_sync_id_reg[0]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => offload_sync_valid, - D => offload_sync_data(0), - Q => offload_sync_id(0), - R => up_sw_reset - ); -\offload_sync_id_reg[1]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => offload_sync_valid, - D => offload_sync_data(1), - Q => offload_sync_id(1), - R => up_sw_reset - ); -\offload_sync_id_reg[2]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => offload_sync_valid, - D => offload_sync_data(2), - Q => offload_sync_id(2), - R => up_sw_reset - ); -\offload_sync_id_reg[3]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => offload_sync_valid, - D => offload_sync_data(3), - Q => offload_sync_id(3), - R => up_sw_reset - ); -\offload_sync_id_reg[4]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => offload_sync_valid, - D => offload_sync_data(4), - Q => offload_sync_id(4), - R => up_sw_reset - ); -\offload_sync_id_reg[5]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => offload_sync_valid, - D => offload_sync_data(5), - Q => offload_sync_id(5), - R => up_sw_reset - ); -\offload_sync_id_reg[6]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => offload_sync_valid, - D => offload_sync_data(6), - Q => offload_sync_id(6), - R => up_sw_reset - ); -\offload_sync_id_reg[7]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => offload_sync_valid, - D => offload_sync_data(7), - Q => offload_sync_id(7), - R => up_sw_reset - ); -spi_resetn_INST_0: unisim.vcomponents.LUT1 - generic map( - INIT => X"1" - ) - port map ( - I0 => up_sw_reset, - O => spi_resetn - ); -sync_id_pending_reg: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => i_up_axi_n_89, - Q => up_irq_source(3), - R => up_sw_reset - ); -\sync_id_reg[0]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => sync_valid, - D => sync_data(0), - Q => sync_id(0), - R => up_sw_reset - ); -\sync_id_reg[1]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => sync_valid, - D => sync_data(1), - Q => sync_id(1), - R => up_sw_reset - ); -\sync_id_reg[2]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => sync_valid, - D => sync_data(2), - Q => sync_id(2), - R => up_sw_reset - ); -\sync_id_reg[3]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => sync_valid, - D => sync_data(3), - Q => sync_id(3), - R => up_sw_reset - ); -\sync_id_reg[4]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => sync_valid, - D => sync_data(4), - Q => sync_id(4), - R => up_sw_reset - ); -\sync_id_reg[5]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => sync_valid, - D => sync_data(5), - Q => sync_id(5), - R => up_sw_reset - ); -\sync_id_reg[6]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => sync_valid, - D => sync_data(6), - Q => sync_id(6), - R => up_sw_reset - ); -\sync_id_reg[7]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => sync_valid, - D => sync_data(7), - Q => sync_id(7), - R => up_sw_reset - ); -\up_irq_mask_reg[0]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => i_up_axi_n_12, - D => \^offload0_sdo_wr_data\(0), - Q => \up_irq_mask_reg_n_0_[0]\, - R => up_sw_reset - ); -\up_irq_mask_reg[1]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => i_up_axi_n_12, - D => \^offload0_cmd_wr_data\(1), - Q => \up_irq_mask_reg_n_0_[1]\, - R => up_sw_reset - ); -\up_irq_mask_reg[2]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => i_up_axi_n_12, - D => \^offload0_cmd_wr_data\(2), - Q => \up_irq_mask_reg_n_0_[2]\, - R => up_sw_reset - ); -\up_irq_mask_reg[3]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => i_up_axi_n_12, - D => \^offload0_sdo_wr_data\(3), - Q => \up_irq_mask_reg_n_0_[3]\, - R => up_sw_reset - ); -up_rack_ff_reg: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => up_rreq_s, - Q => up_rack_ff, - R => i_up_axi_n_0 - ); -\up_rdata_ff_reg[0]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => i_up_axi_n_51, - Q => up_rdata_ff(0), - R => i_up_axi_n_53 - ); -\up_rdata_ff_reg[10]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => i_up_axi_n_26, - Q => up_rdata_ff(10), - R => i_up_axi_n_53 - ); -\up_rdata_ff_reg[11]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => i_up_axi_n_27, - Q => up_rdata_ff(11), - R => i_up_axi_n_53 - ); -\up_rdata_ff_reg[12]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => i_up_axi_n_28, - Q => up_rdata_ff(12), - R => i_up_axi_n_53 - ); -\up_rdata_ff_reg[13]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => i_up_axi_n_29, - Q => up_rdata_ff(13), - R => i_up_axi_n_53 - ); -\up_rdata_ff_reg[14]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => i_up_axi_n_30, - Q => up_rdata_ff(14), - R => i_up_axi_n_53 - ); -\up_rdata_ff_reg[15]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => i_up_axi_n_31, - Q => up_rdata_ff(15), - R => i_up_axi_n_53 - ); -\up_rdata_ff_reg[16]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => i_up_axi_n_54, - Q => up_rdata_ff(16), - R => i_up_axi_n_53 - ); -\up_rdata_ff_reg[17]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => i_up_axi_n_32, - Q => up_rdata_ff(17), - R => i_up_axi_n_53 - ); -\up_rdata_ff_reg[18]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => i_up_axi_n_33, - Q => up_rdata_ff(18), - R => i_up_axi_n_53 - ); -\up_rdata_ff_reg[19]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => i_up_axi_n_34, - Q => up_rdata_ff(19), - R => i_up_axi_n_53 - ); -\up_rdata_ff_reg[1]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => i_up_axi_n_49, - Q => up_rdata_ff(1), - R => i_up_axi_n_53 - ); -\up_rdata_ff_reg[20]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => i_up_axi_n_35, - Q => up_rdata_ff(20), - R => i_up_axi_n_53 - ); -\up_rdata_ff_reg[21]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => i_up_axi_n_36, - Q => up_rdata_ff(21), - R => i_up_axi_n_53 - ); -\up_rdata_ff_reg[22]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => i_up_axi_n_37, - Q => up_rdata_ff(22), - R => i_up_axi_n_53 - ); -\up_rdata_ff_reg[23]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => i_up_axi_n_38, - Q => up_rdata_ff(23), - R => i_up_axi_n_53 - ); -\up_rdata_ff_reg[24]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => i_up_axi_n_39, - Q => up_rdata_ff(24), - R => i_up_axi_n_53 - ); -\up_rdata_ff_reg[25]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => i_up_axi_n_40, - Q => up_rdata_ff(25), - R => i_up_axi_n_53 - ); -\up_rdata_ff_reg[26]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => i_up_axi_n_41, - Q => up_rdata_ff(26), - R => i_up_axi_n_53 - ); -\up_rdata_ff_reg[27]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => i_up_axi_n_42, - Q => up_rdata_ff(27), - R => i_up_axi_n_53 - ); -\up_rdata_ff_reg[28]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => i_up_axi_n_43, - Q => up_rdata_ff(28), - R => i_up_axi_n_53 - ); -\up_rdata_ff_reg[29]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => i_up_axi_n_44, - Q => up_rdata_ff(29), - R => i_up_axi_n_53 - ); -\up_rdata_ff_reg[2]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => i_up_axi_n_50, - Q => up_rdata_ff(2), - R => i_up_axi_n_53 - ); -\up_rdata_ff_reg[30]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => i_up_axi_n_45, - Q => up_rdata_ff(30), - R => i_up_axi_n_53 - ); -\up_rdata_ff_reg[31]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => i_up_axi_n_46, - Q => up_rdata_ff(31), - R => i_up_axi_n_53 - ); -\up_rdata_ff_reg[3]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => i_up_axi_n_18, - Q => up_rdata_ff(3), - R => i_up_axi_n_53 - ); -\up_rdata_ff_reg[4]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => i_up_axi_n_21, - Q => up_rdata_ff(4), - R => i_up_axi_n_53 - ); -\up_rdata_ff_reg[5]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => i_up_axi_n_22, - Q => up_rdata_ff(5), - R => i_up_axi_n_53 - ); -\up_rdata_ff_reg[6]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => i_up_axi_n_23, - Q => up_rdata_ff(6), - R => i_up_axi_n_53 - ); -\up_rdata_ff_reg[7]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => i_up_axi_n_52, - Q => up_rdata_ff(7), - R => i_up_axi_n_53 - ); -\up_rdata_ff_reg[8]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => i_up_axi_n_24, - Q => up_rdata_ff(8), - R => i_up_axi_n_53 - ); -\up_rdata_ff_reg[9]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => i_up_axi_n_25, - Q => up_rdata_ff(9), - R => i_up_axi_n_53 - ); -\up_scratch_reg[0]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => up_scratch, - D => \^offload0_sdo_wr_data\(0), - Q => \up_scratch_reg_n_0_[0]\, - R => i_up_axi_n_0 - ); -\up_scratch_reg[10]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => up_scratch, - D => \^offload0_cmd_wr_data\(10), - Q => \up_scratch_reg_n_0_[10]\, - R => i_up_axi_n_0 - ); -\up_scratch_reg[11]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => up_scratch, - D => \^offload0_cmd_wr_data\(11), - Q => \up_scratch_reg_n_0_[11]\, - R => i_up_axi_n_0 - ); -\up_scratch_reg[12]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => up_scratch, - D => \^offload0_cmd_wr_data\(12), - Q => \up_scratch_reg_n_0_[12]\, - R => i_up_axi_n_0 - ); -\up_scratch_reg[13]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => up_scratch, - D => \^offload0_cmd_wr_data\(13), - Q => \up_scratch_reg_n_0_[13]\, - R => i_up_axi_n_0 - ); -\up_scratch_reg[14]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => up_scratch, - D => \^offload0_cmd_wr_data\(14), - Q => \up_scratch_reg_n_0_[14]\, - R => i_up_axi_n_0 - ); -\up_scratch_reg[15]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => up_scratch, - D => \^offload0_cmd_wr_data\(15), - Q => \up_scratch_reg_n_0_[15]\, - R => i_up_axi_n_0 - ); -\up_scratch_reg[16]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => up_scratch, - D => up_wdata_int(16), - Q => \up_scratch_reg_n_0_[16]\, - R => i_up_axi_n_0 - ); -\up_scratch_reg[17]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => up_scratch, - D => up_wdata_int(17), - Q => \up_scratch_reg_n_0_[17]\, - R => i_up_axi_n_0 - ); -\up_scratch_reg[18]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => up_scratch, - D => up_wdata_int(18), - Q => \up_scratch_reg_n_0_[18]\, - R => i_up_axi_n_0 - ); -\up_scratch_reg[19]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => up_scratch, - D => up_wdata_int(19), - Q => \up_scratch_reg_n_0_[19]\, - R => i_up_axi_n_0 - ); -\up_scratch_reg[1]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => up_scratch, - D => \^offload0_cmd_wr_data\(1), - Q => \up_scratch_reg_n_0_[1]\, - R => i_up_axi_n_0 - ); -\up_scratch_reg[20]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => up_scratch, - D => up_wdata_int(20), - Q => \up_scratch_reg_n_0_[20]\, - R => i_up_axi_n_0 - ); -\up_scratch_reg[21]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => up_scratch, - D => up_wdata_int(21), - Q => \up_scratch_reg_n_0_[21]\, - R => i_up_axi_n_0 - ); -\up_scratch_reg[22]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => up_scratch, - D => up_wdata_int(22), - Q => \up_scratch_reg_n_0_[22]\, - R => i_up_axi_n_0 - ); -\up_scratch_reg[23]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => up_scratch, - D => up_wdata_int(23), - Q => \up_scratch_reg_n_0_[23]\, - R => i_up_axi_n_0 - ); -\up_scratch_reg[24]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => up_scratch, - D => up_wdata_int(24), - Q => \up_scratch_reg_n_0_[24]\, - R => i_up_axi_n_0 - ); -\up_scratch_reg[25]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => up_scratch, - D => up_wdata_int(25), - Q => \up_scratch_reg_n_0_[25]\, - R => i_up_axi_n_0 - ); -\up_scratch_reg[26]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => up_scratch, - D => up_wdata_int(26), - Q => \up_scratch_reg_n_0_[26]\, - R => i_up_axi_n_0 - ); -\up_scratch_reg[27]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => up_scratch, - D => up_wdata_int(27), - Q => \up_scratch_reg_n_0_[27]\, - R => i_up_axi_n_0 - ); -\up_scratch_reg[28]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => up_scratch, - D => up_wdata_int(28), - Q => \up_scratch_reg_n_0_[28]\, - R => i_up_axi_n_0 - ); -\up_scratch_reg[29]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => up_scratch, - D => up_wdata_int(29), - Q => \up_scratch_reg_n_0_[29]\, - R => i_up_axi_n_0 - ); -\up_scratch_reg[2]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => up_scratch, - D => \^offload0_cmd_wr_data\(2), - Q => \up_scratch_reg_n_0_[2]\, - R => i_up_axi_n_0 - ); -\up_scratch_reg[30]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => up_scratch, - D => up_wdata_int(30), - Q => \up_scratch_reg_n_0_[30]\, - R => i_up_axi_n_0 - ); -\up_scratch_reg[31]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => up_scratch, - D => up_wdata_int(31), - Q => \up_scratch_reg_n_0_[31]\, - R => i_up_axi_n_0 - ); -\up_scratch_reg[3]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => up_scratch, - D => \^offload0_sdo_wr_data\(3), - Q => \up_scratch_reg_n_0_[3]\, - R => i_up_axi_n_0 - ); -\up_scratch_reg[4]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => up_scratch, - D => \^offload0_sdo_wr_data\(4), - Q => \up_scratch_reg_n_0_[4]\, - R => i_up_axi_n_0 - ); -\up_scratch_reg[5]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => up_scratch, - D => \^offload0_sdo_wr_data\(5), - Q => \up_scratch_reg_n_0_[5]\, - R => i_up_axi_n_0 - ); -\up_scratch_reg[6]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => up_scratch, - D => \^offload0_sdo_wr_data\(6), - Q => \up_scratch_reg_n_0_[6]\, - R => i_up_axi_n_0 - ); -\up_scratch_reg[7]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => up_scratch, - D => \^offload0_sdo_wr_data\(7), - Q => \up_scratch_reg_n_0_[7]\, - R => i_up_axi_n_0 - ); -\up_scratch_reg[8]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => up_scratch, - D => \^offload0_cmd_wr_data\(8), - Q => \up_scratch_reg_n_0_[8]\, - R => i_up_axi_n_0 - ); -\up_scratch_reg[9]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => up_scratch, - D => \^offload0_cmd_wr_data\(9), - Q => \up_scratch_reg_n_0_[9]\, - R => i_up_axi_n_0 - ); -up_sw_reset_reg: unisim.vcomponents.FDSE - generic map( - INIT => '1' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => i_up_axi_n_56, - Q => up_sw_reset, - S => i_up_axi_n_0 - ); -up_wack_ff_reg: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => '1', - D => up_wreq_s, - Q => up_wack_ff, - R => i_up_axi_n_0 - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity system_bd_axi_spi_engine_0_0 is - port ( - s_axi_aclk : in STD_LOGIC; - s_axi_aresetn : in STD_LOGIC; - s_axi_awvalid : in STD_LOGIC; - s_axi_awaddr : in STD_LOGIC_VECTOR ( 15 downto 0 ); - s_axi_awready : out STD_LOGIC; - s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); - s_axi_wvalid : in STD_LOGIC; - s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); - s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); - s_axi_wready : out STD_LOGIC; - s_axi_bvalid : out STD_LOGIC; - s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); - s_axi_bready : in STD_LOGIC; - s_axi_arvalid : in STD_LOGIC; - s_axi_araddr : in STD_LOGIC_VECTOR ( 15 downto 0 ); - s_axi_arready : out STD_LOGIC; - s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); - s_axi_rvalid : out STD_LOGIC; - s_axi_rready : in STD_LOGIC; - s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); - s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); - irq : out STD_LOGIC; - spi_clk : in STD_LOGIC; - spi_resetn : out STD_LOGIC; - cmd_ready : in STD_LOGIC; - cmd_valid : out STD_LOGIC; - cmd_data : out STD_LOGIC_VECTOR ( 15 downto 0 ); - sdo_data_ready : in STD_LOGIC; - sdo_data_valid : out STD_LOGIC; - sdo_data : out STD_LOGIC_VECTOR ( 7 downto 0 ); - sdi_data_ready : out STD_LOGIC; - sdi_data_valid : in STD_LOGIC; - sdi_data : in STD_LOGIC_VECTOR ( 7 downto 0 ); - sync_ready : out STD_LOGIC; - sync_valid : in STD_LOGIC; - sync_data : in STD_LOGIC_VECTOR ( 7 downto 0 ) - ); - attribute NotValidForBitStream : boolean; - attribute NotValidForBitStream of system_bd_axi_spi_engine_0_0 : entity is true; - attribute CHECK_LICENSE_TYPE : string; - attribute CHECK_LICENSE_TYPE of system_bd_axi_spi_engine_0_0 : entity is "system_bd_axi_spi_engine_0_0,axi_spi_engine,{}"; - attribute DowngradeIPIdentifiedWarnings : string; - attribute DowngradeIPIdentifiedWarnings of system_bd_axi_spi_engine_0_0 : entity is "yes"; - attribute IP_DEFINITION_SOURCE : string; - attribute IP_DEFINITION_SOURCE of system_bd_axi_spi_engine_0_0 : entity is "package_project"; - attribute X_CORE_INFO : string; - attribute X_CORE_INFO of system_bd_axi_spi_engine_0_0 : entity is "axi_spi_engine,Vivado 2019.1.3"; -end system_bd_axi_spi_engine_0_0; - -architecture STRUCTURE of system_bd_axi_spi_engine_0_0 is - signal NLW_inst_offload0_cmd_wr_en_UNCONNECTED : STD_LOGIC; - signal NLW_inst_offload0_enable_UNCONNECTED : STD_LOGIC; - signal NLW_inst_offload0_mem_reset_UNCONNECTED : STD_LOGIC; - signal NLW_inst_offload0_sdo_wr_en_UNCONNECTED : STD_LOGIC; - signal NLW_inst_offload_sync_ready_UNCONNECTED : STD_LOGIC; - signal NLW_inst_up_rack_UNCONNECTED : STD_LOGIC; - signal NLW_inst_up_wack_UNCONNECTED : STD_LOGIC; - signal NLW_inst_offload0_cmd_wr_data_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 ); - signal NLW_inst_offload0_sdo_wr_data_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); - signal NLW_inst_up_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); - attribute ASYNC_SPI_CLK : string; - attribute ASYNC_SPI_CLK of inst : label is "1'b0"; - attribute CMD_FIFO_ADDRESS_WIDTH : integer; - attribute CMD_FIFO_ADDRESS_WIDTH of inst : label is 4; - attribute DATA_WIDTH : string; - attribute DATA_WIDTH of inst : label is "16'b0000000000001000"; - attribute ID : integer; - attribute ID of inst : label is 0; - attribute MM_IF_TYPE : integer; - attribute MM_IF_TYPE of inst : label is 0; - attribute NUM_OFFLOAD : integer; - attribute NUM_OFFLOAD of inst : label is 0; - attribute NUM_OF_SDI : string; - attribute NUM_OF_SDI of inst : label is "8'b00000001"; - attribute OFFLOAD0_CMD_MEM_ADDRESS_WIDTH : integer; - attribute OFFLOAD0_CMD_MEM_ADDRESS_WIDTH of inst : label is 4; - attribute OFFLOAD0_SDO_MEM_ADDRESS_WIDTH : integer; - attribute OFFLOAD0_SDO_MEM_ADDRESS_WIDTH of inst : label is 4; - attribute PCORE_VERSION : integer; - attribute PCORE_VERSION of inst : label is 65649; - attribute SDI_FIFO_ADDRESS_WIDTH : integer; - attribute SDI_FIFO_ADDRESS_WIDTH of inst : label is 5; - attribute SDO_FIFO_ADDRESS_WIDTH : integer; - attribute SDO_FIFO_ADDRESS_WIDTH of inst : label is 5; - attribute SYNC_FIFO_ADDRESS_WIDTH : integer; - attribute SYNC_FIFO_ADDRESS_WIDTH of inst : label is 4; - attribute S_AXI : integer; - attribute S_AXI of inst : label is 0; - attribute UP_FIFO : integer; - attribute UP_FIFO of inst : label is 1; - attribute X_INTERFACE_INFO : string; - attribute X_INTERFACE_INFO of cmd_ready : signal is "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl CMD_READY"; - attribute X_INTERFACE_INFO of cmd_valid : signal is "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl CMD_VALID"; - attribute X_INTERFACE_INFO of s_axi_aclk : signal is "xilinx.com:signal:clock:1.0 s_axi_aclk CLK, xilinx.com:signal:clock:1.0 spi_engine_offload_ctrl0_s_axi_signal_clock CLK"; - attribute X_INTERFACE_PARAMETER : string; - attribute X_INTERFACE_PARAMETER of s_axi_aclk : signal is "XIL_INTERFACENAME s_axi_aclk, ASSOCIATED_BUSIF s_axi, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0, XIL_INTERFACENAME spi_engine_offload_ctrl0_s_axi_signal_clock, ASSOCIATED_BUSIF spi_engine_offload_ctrl0:s_axi, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0"; - attribute X_INTERFACE_INFO of s_axi_aresetn : signal is "xilinx.com:signal:reset:1.0 s_axi_aresetn RST, xilinx.com:signal:reset:1.0 spi_engine_offload_ctrl0_s_axi_signal_reset RST"; - attribute X_INTERFACE_PARAMETER of s_axi_aresetn : signal is "XIL_INTERFACENAME s_axi_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0, XIL_INTERFACENAME spi_engine_offload_ctrl0_s_axi_signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; - attribute X_INTERFACE_INFO of s_axi_arready : signal is "xilinx.com:interface:aximm:1.0 s_axi ARREADY"; - attribute X_INTERFACE_INFO of s_axi_arvalid : signal is "xilinx.com:interface:aximm:1.0 s_axi ARVALID"; - attribute X_INTERFACE_INFO of s_axi_awready : signal is "xilinx.com:interface:aximm:1.0 s_axi AWREADY"; - attribute X_INTERFACE_INFO of s_axi_awvalid : signal is "xilinx.com:interface:aximm:1.0 s_axi AWVALID"; - attribute X_INTERFACE_INFO of s_axi_bready : signal is "xilinx.com:interface:aximm:1.0 s_axi BREADY"; - attribute X_INTERFACE_INFO of s_axi_bvalid : signal is "xilinx.com:interface:aximm:1.0 s_axi BVALID"; - attribute X_INTERFACE_INFO of s_axi_rready : signal is "xilinx.com:interface:aximm:1.0 s_axi RREADY"; - attribute X_INTERFACE_INFO of s_axi_rvalid : signal is "xilinx.com:interface:aximm:1.0 s_axi RVALID"; - attribute X_INTERFACE_INFO of s_axi_wready : signal is "xilinx.com:interface:aximm:1.0 s_axi WREADY"; - attribute X_INTERFACE_INFO of s_axi_wvalid : signal is "xilinx.com:interface:aximm:1.0 s_axi WVALID"; - attribute X_INTERFACE_INFO of sdi_data_ready : signal is "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDI_READY"; - attribute X_INTERFACE_INFO of sdi_data_valid : signal is "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDI_VALID"; - attribute X_INTERFACE_INFO of sdo_data_ready : signal is "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDO_READY"; - attribute X_INTERFACE_INFO of sdo_data_valid : signal is "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDO_VALID"; - attribute X_INTERFACE_INFO of spi_clk : signal is "xilinx.com:signal:clock:1.0 spi_engine_ctrl_signal_clock CLK"; - attribute X_INTERFACE_PARAMETER of spi_clk : signal is "XIL_INTERFACENAME spi_engine_ctrl_signal_clock, ASSOCIATED_BUSIF spi_engine_ctrl, ASSOCIATED_RESET spi_resetn, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0"; - attribute X_INTERFACE_INFO of spi_resetn : signal is "xilinx.com:signal:reset:1.0 spi_engine_ctrl_signal_reset RST"; - attribute X_INTERFACE_PARAMETER of spi_resetn : signal is "XIL_INTERFACENAME spi_engine_ctrl_signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; - attribute X_INTERFACE_INFO of sync_ready : signal is "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SYNC_READY"; - attribute X_INTERFACE_INFO of sync_valid : signal is "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SYNC_VALID"; - attribute X_INTERFACE_INFO of cmd_data : signal is "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl CMD_DATA"; - attribute X_INTERFACE_INFO of s_axi_araddr : signal is "xilinx.com:interface:aximm:1.0 s_axi ARADDR"; - attribute X_INTERFACE_INFO of s_axi_arprot : signal is "xilinx.com:interface:aximm:1.0 s_axi ARPROT"; - attribute X_INTERFACE_INFO of s_axi_awaddr : signal is "xilinx.com:interface:aximm:1.0 s_axi AWADDR"; - attribute X_INTERFACE_INFO of s_axi_awprot : signal is "xilinx.com:interface:aximm:1.0 s_axi AWPROT"; - attribute X_INTERFACE_INFO of s_axi_bresp : signal is "xilinx.com:interface:aximm:1.0 s_axi BRESP"; - attribute X_INTERFACE_INFO of s_axi_rdata : signal is "xilinx.com:interface:aximm:1.0 s_axi RDATA"; - attribute X_INTERFACE_PARAMETER of s_axi_rdata : signal is "XIL_INTERFACENAME s_axi, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 50000000, ID_WIDTH 0, ADDR_WIDTH 16, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0"; - attribute X_INTERFACE_INFO of s_axi_rresp : signal is "xilinx.com:interface:aximm:1.0 s_axi RRESP"; - attribute X_INTERFACE_INFO of s_axi_wdata : signal is "xilinx.com:interface:aximm:1.0 s_axi WDATA"; - attribute X_INTERFACE_INFO of s_axi_wstrb : signal is "xilinx.com:interface:aximm:1.0 s_axi WSTRB"; - attribute X_INTERFACE_INFO of sdi_data : signal is "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDI_DATA"; - attribute X_INTERFACE_INFO of sdo_data : signal is "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDO_DATA"; - attribute X_INTERFACE_INFO of sync_data : signal is "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SYNC_DATA"; -begin -inst: entity work.system_bd_axi_spi_engine_0_0_axi_spi_engine - port map ( - cmd_data(15 downto 0) => cmd_data(15 downto 0), - cmd_ready => cmd_ready, - cmd_valid => cmd_valid, - irq => irq, - offload0_cmd_wr_data(15 downto 0) => NLW_inst_offload0_cmd_wr_data_UNCONNECTED(15 downto 0), - offload0_cmd_wr_en => NLW_inst_offload0_cmd_wr_en_UNCONNECTED, - offload0_enable => NLW_inst_offload0_enable_UNCONNECTED, - offload0_enabled => '0', - offload0_mem_reset => NLW_inst_offload0_mem_reset_UNCONNECTED, - offload0_sdo_wr_data(7 downto 0) => NLW_inst_offload0_sdo_wr_data_UNCONNECTED(7 downto 0), - offload0_sdo_wr_en => NLW_inst_offload0_sdo_wr_en_UNCONNECTED, - offload_sync_data(7 downto 0) => B"00000000", - offload_sync_ready => NLW_inst_offload_sync_ready_UNCONNECTED, - offload_sync_valid => '0', - s_axi_aclk => s_axi_aclk, - s_axi_araddr(15 downto 0) => s_axi_araddr(15 downto 0), - s_axi_aresetn => s_axi_aresetn, - s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0), - s_axi_arready => s_axi_arready, - s_axi_arvalid => s_axi_arvalid, - s_axi_awaddr(15 downto 0) => s_axi_awaddr(15 downto 0), - s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0), - s_axi_awready => s_axi_awready, - s_axi_awvalid => s_axi_awvalid, - s_axi_bready => s_axi_bready, - s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0), - s_axi_bvalid => s_axi_bvalid, - s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0), - s_axi_rready => s_axi_rready, - s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0), - s_axi_rvalid => s_axi_rvalid, - s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0), - s_axi_wready => s_axi_wready, - s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0), - s_axi_wvalid => s_axi_wvalid, - sdi_data(7 downto 0) => sdi_data(7 downto 0), - sdi_data_ready => sdi_data_ready, - sdi_data_valid => sdi_data_valid, - sdo_data(7 downto 0) => sdo_data(7 downto 0), - sdo_data_ready => sdo_data_ready, - sdo_data_valid => sdo_data_valid, - spi_clk => spi_clk, - spi_resetn => spi_resetn, - sync_data(7 downto 0) => sync_data(7 downto 0), - sync_ready => sync_ready, - sync_valid => sync_valid, - up_clk => '0', - up_rack => NLW_inst_up_rack_UNCONNECTED, - up_raddr(13 downto 0) => B"00000000000000", - up_rdata(31 downto 0) => NLW_inst_up_rdata_UNCONNECTED(31 downto 0), - up_rreq => '0', - up_rstn => '0', - up_wack => NLW_inst_up_wack_UNCONNECTED, - up_waddr(13 downto 0) => B"00000000000000", - up_wdata(31 downto 0) => B"00000000000000000000000000000000", - up_wreq => '0' - ); -end STRUCTURE; diff --git a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0_stub.v b/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0_stub.v deleted file mode 100644 index 79cc224..0000000 --- a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0_stub.v +++ /dev/null @@ -1,60 +0,0 @@ -// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -// -------------------------------------------------------------------------------- -// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 -// Date : Sun Sep 29 16:31:49 2024 -// Host : gatsby-dev running 64-bit Red Hat Enterprise Linux release 8.10 (Ootpa) -// Command : write_verilog -force -mode synth_stub -// /home/josh/Workspace/CX9261A/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0_stub.v -// Design : system_bd_axi_spi_engine_0_0 -// Purpose : Stub declaration of top-level module interface -// Device : xc7z045ffg900-2 -// -------------------------------------------------------------------------------- - -// This empty module with port declaration file causes synthesis tools to infer a black box for IP. -// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. -// Please paste the declaration into a Verilog source file or add the file as an additional source. -(* X_CORE_INFO = "axi_spi_engine,Vivado 2019.1.3" *) -module system_bd_axi_spi_engine_0_0(s_axi_aclk, s_axi_aresetn, s_axi_awvalid, - s_axi_awaddr, s_axi_awready, s_axi_awprot, s_axi_wvalid, s_axi_wdata, s_axi_wstrb, - s_axi_wready, s_axi_bvalid, s_axi_bresp, s_axi_bready, s_axi_arvalid, s_axi_araddr, - s_axi_arready, s_axi_arprot, s_axi_rvalid, s_axi_rready, s_axi_rresp, s_axi_rdata, irq, - spi_clk, spi_resetn, cmd_ready, cmd_valid, cmd_data, sdo_data_ready, sdo_data_valid, sdo_data, - sdi_data_ready, sdi_data_valid, sdi_data, sync_ready, sync_valid, sync_data) -/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,s_axi_awvalid,s_axi_awaddr[15:0],s_axi_awready,s_axi_awprot[2:0],s_axi_wvalid,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wready,s_axi_bvalid,s_axi_bresp[1:0],s_axi_bready,s_axi_arvalid,s_axi_araddr[15:0],s_axi_arready,s_axi_arprot[2:0],s_axi_rvalid,s_axi_rready,s_axi_rresp[1:0],s_axi_rdata[31:0],irq,spi_clk,spi_resetn,cmd_ready,cmd_valid,cmd_data[15:0],sdo_data_ready,sdo_data_valid,sdo_data[7:0],sdi_data_ready,sdi_data_valid,sdi_data[7:0],sync_ready,sync_valid,sync_data[7:0]" */; - input s_axi_aclk; - input s_axi_aresetn; - input s_axi_awvalid; - input [15:0]s_axi_awaddr; - output s_axi_awready; - input [2:0]s_axi_awprot; - input s_axi_wvalid; - input [31:0]s_axi_wdata; - input [3:0]s_axi_wstrb; - output s_axi_wready; - output s_axi_bvalid; - output [1:0]s_axi_bresp; - input s_axi_bready; - input s_axi_arvalid; - input [15:0]s_axi_araddr; - output s_axi_arready; - input [2:0]s_axi_arprot; - output s_axi_rvalid; - input s_axi_rready; - output [1:0]s_axi_rresp; - output [31:0]s_axi_rdata; - output irq; - input spi_clk; - output spi_resetn; - input cmd_ready; - output cmd_valid; - output [15:0]cmd_data; - input sdo_data_ready; - output sdo_data_valid; - output [7:0]sdo_data; - output sdi_data_ready; - input sdi_data_valid; - input [7:0]sdi_data; - output sync_ready; - input sync_valid; - input [7:0]sync_data; -endmodule diff --git a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0_stub.vhdl b/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0_stub.vhdl deleted file mode 100644 index d189cdc..0000000 --- a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0_stub.vhdl +++ /dev/null @@ -1,65 +0,0 @@ --- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. --- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 --- Date : Sun Sep 29 16:31:49 2024 --- Host : gatsby-dev running 64-bit Red Hat Enterprise Linux release 8.10 (Ootpa) --- Command : write_vhdl -force -mode synth_stub --- /home/josh/Workspace/CX9261A/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0_stub.vhdl --- Design : system_bd_axi_spi_engine_0_0 --- Purpose : Stub declaration of top-level module interface --- Device : xc7z045ffg900-2 --- -------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; - -entity system_bd_axi_spi_engine_0_0 is - Port ( - s_axi_aclk : in STD_LOGIC; - s_axi_aresetn : in STD_LOGIC; - s_axi_awvalid : in STD_LOGIC; - s_axi_awaddr : in STD_LOGIC_VECTOR ( 15 downto 0 ); - s_axi_awready : out STD_LOGIC; - s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); - s_axi_wvalid : in STD_LOGIC; - s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); - s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); - s_axi_wready : out STD_LOGIC; - s_axi_bvalid : out STD_LOGIC; - s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); - s_axi_bready : in STD_LOGIC; - s_axi_arvalid : in STD_LOGIC; - s_axi_araddr : in STD_LOGIC_VECTOR ( 15 downto 0 ); - s_axi_arready : out STD_LOGIC; - s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); - s_axi_rvalid : out STD_LOGIC; - s_axi_rready : in STD_LOGIC; - s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); - s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); - irq : out STD_LOGIC; - spi_clk : in STD_LOGIC; - spi_resetn : out STD_LOGIC; - cmd_ready : in STD_LOGIC; - cmd_valid : out STD_LOGIC; - cmd_data : out STD_LOGIC_VECTOR ( 15 downto 0 ); - sdo_data_ready : in STD_LOGIC; - sdo_data_valid : out STD_LOGIC; - sdo_data : out STD_LOGIC_VECTOR ( 7 downto 0 ); - sdi_data_ready : out STD_LOGIC; - sdi_data_valid : in STD_LOGIC; - sdi_data : in STD_LOGIC_VECTOR ( 7 downto 0 ); - sync_ready : out STD_LOGIC; - sync_valid : in STD_LOGIC; - sync_data : in STD_LOGIC_VECTOR ( 7 downto 0 ) - ); - -end system_bd_axi_spi_engine_0_0; - -architecture stub of system_bd_axi_spi_engine_0_0 is -attribute syn_black_box : boolean; -attribute black_box_pad_pin : string; -attribute syn_black_box of stub : architecture is true; -attribute black_box_pad_pin of stub : architecture is "s_axi_aclk,s_axi_aresetn,s_axi_awvalid,s_axi_awaddr[15:0],s_axi_awready,s_axi_awprot[2:0],s_axi_wvalid,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wready,s_axi_bvalid,s_axi_bresp[1:0],s_axi_bready,s_axi_arvalid,s_axi_araddr[15:0],s_axi_arready,s_axi_arprot[2:0],s_axi_rvalid,s_axi_rready,s_axi_rresp[1:0],s_axi_rdata[31:0],irq,spi_clk,spi_resetn,cmd_ready,cmd_valid,cmd_data[15:0],sdo_data_ready,sdo_data_valid,sdo_data[7:0],sdi_data_ready,sdi_data_valid,sdi_data[7:0],sync_ready,sync_valid,sync_data[7:0]"; -attribute X_CORE_INFO : string; -attribute X_CORE_INFO of stub : architecture is "axi_spi_engine,Vivado 2019.1.3"; -begin -end; diff --git a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_spi_engine_execution_0_1/system_bd_spi_engine_execution_0_1.xci b/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_spi_engine_execution_0_1/system_bd_spi_engine_execution_0_1.xci index 1e7794f..72ace9c 100644 --- a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_spi_engine_execution_0_1/system_bd_spi_engine_execution_0_1.xci +++ b/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_spi_engine_execution_0_1/system_bd_spi_engine_execution_0_1.xci @@ -2,7 +2,7 @@ "schema": "xilinx.com:schema:json_instance:1.0", "ip_inst": { "xci_name": "system_bd_spi_engine_execution_0_1", - "cell_name": "spi_engine_execution", + "cell_name": "axi_spi_engine/spi_engine_execution", "component_reference": "analog.com:user:spi_engine_execution:1.0", "ip_revision": "1", "gen_directory": "../../../../../../zc706_cx9261a_demo.gen/sources_1/bd/system_bd/ip/system_bd_spi_engine_execution_0_1", @@ -147,10 +147,10 @@ "parameters": { "ASSOCIATED_BUSIF": [ { "value": "spi", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ], "ASSOCIATED_RESET": [ { "value": "resetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ], - "FREQ_HZ": [ { "value": "5e+07", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_HZ": [ { "value": "2e+08", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], - "CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } 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"resolve_type": "user", "usage": "all" } ] + }, + "project_parameters": { + "ARCHITECTURE": [ { "value": "zynq" } ], + "BASE_BOARD_PART": [ { "value": "xilinx.com:zc706:part0:1.4" } ], + "BOARD_CONNECTIONS": [ { "value": "" } ], + "DEVICE": [ { "value": "xc7z045" } ], + "NEXTGEN_VERSAL": [ { "value": "0" } ], + "PACKAGE": [ { "value": "ffg900" } ], + "PREFHDL": [ { "value": "VERILOG" } ], + "SILICON_REVISION": [ { "value": "" } ], + "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], + "SPEEDGRADE": [ { "value": "-2" } ], + "STATIC_POWER": [ { "value": "" } ], + "TEMPERATURE_GRADE": [ { "value": "" } ] + }, + "runtime_parameters": { + "IPCONTEXT": [ { "value": "IP_Integrator" } ], + "IPREVISION": [ { "value": "17" } ], + "MANAGED": [ { "value": "TRUE" } ], + "OUTPUTDIR": [ { "value": "../../../../../../zc706_cx9261a_demo.gen/sources_1/bd/system_bd/ip/system_bd_system_ila_0_0" } ], + "SELECTEDSIMMODEL": [ { "value": "" } ], + "SHAREDDIR": [ { "value": "../../ipshared" } ], + "SWVERSION": [ { "value": "2024.1" } ], + "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ] + } + }, + "boundary": { + "ports": { + "clk": [ { "direction": "in" } ], + "probe0": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "SLOT_0_SPI_ENGINE_sclk": [ { "direction": "in", "driver_value": "0" } ], + "SLOT_0_SPI_ENGINE_sdo": [ { "direction": "in", "driver_value": "0" } ], + "SLOT_0_SPI_ENGINE_sdo_t": [ { "direction": "in", "driver_value": "0" } ], + "SLOT_0_SPI_ENGINE_sdi": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "SLOT_0_SPI_ENGINE_cs": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "SLOT_0_SPI_ENGINE_three_wire": [ { "direction": "in", "driver_value": "0" } ] + }, + "interfaces": { + "CLK.clk": { + "vlnv": "xilinx.com:signal:clock:1.0", + "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", + "mode": "slave", + "parameters": { + "FREQ_HZ": [ { "value": "2e+08", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK1", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ], + "ASSOCIATED_BUSIF": [ { "value": "", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ], + "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ], + "ASSOCIATED_RESET": [ { "value": "", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ] + }, + "port_maps": { + "CLK": [ { "physical_name": "clk" } ] + } + }, + "SLOT_0_SPI_ENGINE": { + "vlnv": "analog.com:interface:spi_engine:1.0", + "abstraction_type": "analog.com:interface:spi_engine_rtl:1.0", + "mode": "monitor", + "port_maps": { + "sclk": [ { "physical_name": "SLOT_0_SPI_ENGINE_sclk" } ], + "sdo": [ { "physical_name": "SLOT_0_SPI_ENGINE_sdo" } ], + "sdo_t": [ { "physical_name": "SLOT_0_SPI_ENGINE_sdo_t" } ], + "sdi": [ { "physical_name": "SLOT_0_SPI_ENGINE_sdi" } ], + "cs": [ { "physical_name": "SLOT_0_SPI_ENGINE_cs" } ], + "three_wire": [ { "physical_name": "SLOT_0_SPI_ENGINE_three_wire" } ] + } + } + } + } + } +} \ No newline at end of file diff --git a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_xadc_wiz_0_0/system_bd_xadc_wiz_0_0.xci b/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_xadc_wiz_0_0/system_bd_xadc_wiz_0_0.xci index f210a1c..6a80a34 100644 --- a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_xadc_wiz_0_0/system_bd_xadc_wiz_0_0.xci +++ b/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_xadc_wiz_0_0/system_bd_xadc_wiz_0_0.xci @@ -311,25 +311,25 @@ "mode": "slave", "parameters": { "DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], "FREQ_HZ": [ { "value": "5e+07", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "ADDR_WIDTH": [ { "value": "11", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_PROT": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_WSTRB": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_BRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_RRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_PROT": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_WSTRB": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_BRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_RRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "NUM_READ_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], diff --git a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_xbar_0/system_bd_xbar_0.xci b/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_xbar_0/system_bd_xbar_0.xci index 3532546..77f513a 100644 --- a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_xbar_0/system_bd_xbar_0.xci +++ b/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_xbar_0/system_bd_xbar_0.xci @@ -2,7 +2,7 @@ "schema": "xilinx.com:schema:json_instance:1.0", "ip_inst": { "xci_name": "system_bd_xbar_0", - "cell_name": "axi_interconnect_0_upgraded_ipi/xbar", + "cell_name": "axi_interconnect_0/xbar", "component_reference": "xilinx.com:ip:axi_crossbar:2.1", "ip_revision": "32", "gen_directory": "../../../../../../zc706_cx9261a_demo.gen/sources_1/bd/system_bd/ip/system_bd_xbar_0", @@ -1316,7 +1316,7 @@ "parameters": { "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ], - "TYPE": [ { "value": "INTERCONNECT", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ] + "TYPE": [ { "value": "INTERCONNECT", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ] }, "port_maps": { "RST": [ { "physical_name": "aresetn" } ] diff --git a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ipshared/1cb1/axi_spi_engine.v b/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ipshared/1cb1/axi_spi_engine.v deleted file mode 100644 index d2491ad..0000000 --- a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ipshared/1cb1/axi_spi_engine.v +++ /dev/null @@ -1,625 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. -// -// In this HDL repository, there are many different and unique modules, consisting -// of various HDL (Verilog or VHDL) components. The individual modules are -// developed independently, and may be accompanied by separate and unique license -// terms. -// -// The user should read each of these license terms, and understand the -// freedoms and responsibilities that he or she has by using this source/core. -// -// This core is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR -// A PARTICULAR PURPOSE. -// -// Redistribution and use of source or resulting binaries, with or without modification -// of this file, are permitted under one of the following two license terms: -// -// 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory -// of this repository (LICENSE_GPL2), and also online at: -// -// -// OR -// -// 2. An ADI specific BSD license, which can be found in the top level directory -// of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD -// This will allow to generate bit files and not release the source code, -// as long as it attaches to an ADI device. -// -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module axi_spi_engine #( - - parameter CMD_FIFO_ADDRESS_WIDTH = 4, - parameter SYNC_FIFO_ADDRESS_WIDTH = 4, - parameter SDO_FIFO_ADDRESS_WIDTH = 5, - parameter SDI_FIFO_ADDRESS_WIDTH = 5, - parameter MM_IF_TYPE = 0, - parameter ASYNC_SPI_CLK = 0, - parameter NUM_OFFLOAD = 0, - parameter OFFLOAD0_CMD_MEM_ADDRESS_WIDTH = 4, - parameter OFFLOAD0_SDO_MEM_ADDRESS_WIDTH = 4, - parameter ID = 0, - parameter [15:0] DATA_WIDTH = 8, - parameter [ 7:0] NUM_OF_SDI = 1 ) ( - - // Slave AXI interface - - input s_axi_aclk, - input s_axi_aresetn, - input s_axi_awvalid, - input [15:0] s_axi_awaddr, - output s_axi_awready, - input [2:0] s_axi_awprot, - input s_axi_wvalid, - input [31:0] s_axi_wdata, - input [ 3:0] s_axi_wstrb, - output s_axi_wready, - output s_axi_bvalid, - output [ 1:0] s_axi_bresp, - input s_axi_bready, - input s_axi_arvalid, - input [15:0] s_axi_araddr, - output s_axi_arready, - input [2:0] s_axi_arprot, - output s_axi_rvalid, - input s_axi_rready, - output [ 1:0] s_axi_rresp, - output [31:0] s_axi_rdata, - - // up interface - - input up_clk, - input up_rstn, - input up_wreq, - input [13:0] up_waddr, - input [31:0] up_wdata, - output up_wack, - input up_rreq, - input [13:0] up_raddr, - output [31:0] up_rdata, - output up_rack, - - output reg irq, - - // SPI signals - - input spi_clk, - - output spi_resetn, - - input cmd_ready, - output cmd_valid, - output [15:0] cmd_data, - - input sdo_data_ready, - output sdo_data_valid, - output [(DATA_WIDTH-1):0] sdo_data, - - output sdi_data_ready, - input sdi_data_valid, - input [(NUM_OF_SDI * DATA_WIDTH-1):0] sdi_data, - - output sync_ready, - input sync_valid, - input [7:0] sync_data, - - // Offload ctrl signals - - output offload0_cmd_wr_en, - output [15:0] offload0_cmd_wr_data, - - output offload0_sdo_wr_en, - output [(DATA_WIDTH-1):0] offload0_sdo_wr_data, - - output offload0_mem_reset, - output offload0_enable, - input offload0_enabled, - - output offload_sync_ready, - input offload_sync_valid, - input [7:0] offload_sync_data); - - localparam PCORE_VERSION = 'h010071; - localparam S_AXI = 0; - localparam UP_FIFO = 1; - - wire clk; - wire rstn; - - wire [CMD_FIFO_ADDRESS_WIDTH:0] cmd_fifo_room; - wire cmd_fifo_almost_empty; - - wire [15:0] cmd_fifo_in_data; - wire cmd_fifo_in_ready; - wire cmd_fifo_in_valid; - - wire [SDO_FIFO_ADDRESS_WIDTH:0] sdo_fifo_room; - wire sdo_fifo_almost_empty; - - wire [(DATA_WIDTH-1):0] sdo_fifo_in_data; - wire sdo_fifo_in_ready; - wire sdo_fifo_in_valid; - - wire sdi_fifo_out_data_msb_s; - wire [SDI_FIFO_ADDRESS_WIDTH:0] sdi_fifo_level; - wire sdi_fifo_almost_full; - - wire [(NUM_OF_SDI * DATA_WIDTH-1):0] sdi_fifo_out_data; - wire sdi_fifo_out_ready; - wire sdi_fifo_out_valid; - - wire [7:0] sync_fifo_data; - wire sync_fifo_valid; - - wire [7:0] offload_sync_fifo_data; - wire offload_sync_fifo_valid; - - reg up_sw_reset = 1'b1; - wire up_sw_resetn = ~up_sw_reset; - - reg [31:0] up_rdata_ff = 'd0; - reg up_wack_ff = 1'b0; - reg up_rack_ff = 1'b0; - wire up_wreq_s; - wire up_rreq_s; - wire [31:0] up_wdata_s; - wire [13:0] up_waddr_s; - wire [13:0] up_raddr_s; - - // Scratch register - reg [31:0] up_scratch = 'h00; - - reg [7:0] sync_id = 'h00; - reg sync_id_pending = 1'b0; - - reg [7:0] offload_sync_id = 'h00; - reg offload_sync_id_pending = 1'b0; - - generate if (MM_IF_TYPE == S_AXI) begin - - // assign clock and reset - - assign clk = s_axi_aclk; - assign rstn = s_axi_aresetn; - - // interface wrapper - - up_axi #( - .AXI_ADDRESS_WIDTH (16) - ) i_up_axi ( - .up_rstn(rstn), - .up_clk(clk), - .up_axi_awvalid(s_axi_awvalid), - .up_axi_awaddr(s_axi_awaddr), - .up_axi_awready(s_axi_awready), - .up_axi_wvalid(s_axi_wvalid), - .up_axi_wdata(s_axi_wdata), - .up_axi_wstrb(s_axi_wstrb), - .up_axi_wready(s_axi_wready), - .up_axi_bvalid(s_axi_bvalid), - .up_axi_bresp(s_axi_bresp), - .up_axi_bready(s_axi_bready), - .up_axi_arvalid(s_axi_arvalid), - .up_axi_araddr(s_axi_araddr), - .up_axi_arready(s_axi_arready), - .up_axi_rvalid(s_axi_rvalid), - .up_axi_rresp(s_axi_rresp), - .up_axi_rdata(s_axi_rdata), - .up_axi_rready(s_axi_rready), - .up_wreq(up_wreq_s), - .up_waddr(up_waddr_s), - .up_wdata(up_wdata_s), - .up_wack(up_wack_ff), - .up_rreq(up_rreq_s), - .up_raddr(up_raddr_s), - .up_rdata(up_rdata_ff), - .up_rack(up_rack_ff) - ); - - assign up_rdata = 32'b0; - assign up_rack = 1'b0; - assign up_wack = 1'b0; - - end - endgenerate - - generate if (MM_IF_TYPE == UP_FIFO) begin - - // assign clock and reset - - assign clk = up_clk; - assign rstn = up_rstn; - - assign up_wreq_s = up_wreq; - assign up_waddr_s = up_waddr; - assign up_wdata_s = up_wdata; - assign up_wack = up_wack_ff; - assign up_rreq_s = up_rreq; - assign up_raddr_s = up_raddr; - assign up_rdata = up_rdata_ff; - assign up_rack = up_rack_ff; - - end - endgenerate - - // IRQ handling - reg [3:0] up_irq_mask = 'h0; - wire [3:0] up_irq_source; - wire [3:0] up_irq_pending; - - assign up_irq_source = { - offload_sync_id_pending, - sync_id_pending, - sdi_fifo_almost_full, - sdo_fifo_almost_empty, - cmd_fifo_almost_empty - }; - - assign up_irq_pending = up_irq_mask & up_irq_source; - - always @(posedge clk) begin - if (rstn == 1'b0) - irq <= 1'b0; - else - irq <= |up_irq_pending; - end - - always @(posedge clk) begin - if (rstn == 1'b0) begin - up_wack_ff <= 1'b0; - up_scratch <= 'h00; - up_sw_reset <= 1'b1; - end else begin - up_wack_ff <= up_wreq_s; - if (up_wreq_s) begin - case (up_waddr_s) - 8'h02: up_scratch <= up_wdata_s; - 8'h10: up_sw_reset <= up_wdata_s; - endcase - end - end - end - - reg offload0_enable_reg; - reg offload0_mem_reset_reg; - wire offload0_enabled_s; - - // the software reset should reset all the registers - always @(posedge clk) begin - if (up_sw_resetn == 1'b0) begin - up_irq_mask <= 'h00; - offload0_enable_reg <= 1'b0; - offload0_mem_reset_reg <= 1'b0; - end else begin - if (up_wreq_s) begin - case (up_waddr_s) - 8'h20: up_irq_mask <= up_wdata_s; - 8'h40: offload0_enable_reg <= up_wdata_s[0]; - 8'h42: offload0_mem_reset_reg <= up_wdata_s[0]; - endcase - end - end - end - - always @(posedge clk) begin - if (rstn == 1'b0) begin - up_rack_ff <= 'd0; - end else begin - up_rack_ff <= up_rreq_s; - end - end - - generate - if (NUM_OF_SDI > 1) begin - // Only the first two SDI data can be recovered through AXI regmap - assign sdi_fifo_out_data_msb_s = sdi_fifo_out_data[DATA_WIDTH+:DATA_WIDTH]; - end else begin - assign sdi_fifo_out_data_msb_s = sdi_fifo_out_data; - end - endgenerate - - always @(posedge clk) begin - case (up_raddr_s) - 8'h00: up_rdata_ff <= PCORE_VERSION; - 8'h01: up_rdata_ff <= ID; - 8'h02: up_rdata_ff <= up_scratch; - 8'h03: up_rdata_ff <= {8'b0, NUM_OF_SDI, DATA_WIDTH}; - 8'h10: up_rdata_ff <= up_sw_reset; - 8'h20: up_rdata_ff <= up_irq_mask; - 8'h21: up_rdata_ff <= up_irq_pending; - 8'h22: up_rdata_ff <= up_irq_source; - 8'h30: up_rdata_ff <= sync_id; - 8'h31: up_rdata_ff <= offload_sync_id; - 8'h34: up_rdata_ff <= cmd_fifo_room; - 8'h35: up_rdata_ff <= sdo_fifo_room; - 8'h36: up_rdata_ff <= sdi_fifo_level; - 8'h3a: up_rdata_ff <= sdi_fifo_out_data[DATA_WIDTH-1:0]; - 8'h3b: up_rdata_ff <= sdi_fifo_out_data_msb_s; /* store SDI's 32 bits MSB, if exists */ - 8'h3c: up_rdata_ff <= sdi_fifo_out_data; /* PEEK register */ - 8'h40: up_rdata_ff <= {offload0_enable_reg}; - 8'h41: up_rdata_ff <= {offload0_enabled_s}; - default: up_rdata_ff <= 'h00; - endcase - end - - always @(posedge clk) begin - if (up_sw_resetn == 1'b0) begin - sync_id <= 'h00; - sync_id_pending <= 1'b0; - end else begin - if (sync_fifo_valid == 1'b1) begin - sync_id <= sync_fifo_data; - sync_id_pending <= 1'b1; - end else if (up_wreq_s == 1'b1 && up_waddr_s == 8'h21 && up_wdata_s[3] == 1'b1) begin - sync_id_pending <= 1'b0; - end - end - end - - always @(posedge clk) begin - if (up_sw_resetn == 1'b0) begin - offload_sync_id <= 'h00; - offload_sync_id_pending <= 1'b0; - end else begin - if (offload_sync_fifo_valid == 1'b1) begin - offload_sync_id <= offload_sync_fifo_data; - offload_sync_id_pending <= 1'b1; - end else if (up_wreq_s == 1'b1 && up_waddr_s == 8'h21 && up_wdata_s[3] == 1'b1) begin - offload_sync_id_pending <= 1'b0; - end - end - end - - generate if (ASYNC_SPI_CLK) begin - - wire spi_reset; - ad_rst i_spi_resetn ( - .rst_async(up_sw_reset), - .clk(spi_clk), - .rst(spi_reset), - .rstn() - ); - assign spi_resetn = ~spi_reset; - end else begin - assign spi_resetn = ~up_sw_reset; - end - endgenerate - - /* Evaluates to true if FIFO level/room is 3/4 or above */ - `define axi_spi_engine_check_watermark(x, n) \ - (x[n] == 1'b1 || x[n-1:n-2] == 2'b11) - - assign cmd_fifo_in_valid = up_wreq_s == 1'b1 && up_waddr_s == 8'h38; - assign cmd_fifo_in_data = up_wdata_s[15:0]; - assign cmd_fifo_almost_empty = - `axi_spi_engine_check_watermark(cmd_fifo_room, CMD_FIFO_ADDRESS_WIDTH); - - util_axis_fifo #( - .DATA_WIDTH(16), - .ASYNC_CLK(ASYNC_SPI_CLK), - .ADDRESS_WIDTH(CMD_FIFO_ADDRESS_WIDTH), - .S_AXIS_REGISTERED(0) - ) i_cmd_fifo ( - .s_axis_aclk(clk), - .s_axis_aresetn(up_sw_resetn), - .s_axis_ready(cmd_fifo_in_ready), - .s_axis_valid(cmd_fifo_in_valid), - .s_axis_data(cmd_fifo_in_data), - .s_axis_room(cmd_fifo_room), - .s_axis_empty(), - .m_axis_aclk(spi_clk), - .m_axis_aresetn(spi_resetn), - .m_axis_ready(cmd_ready), - .m_axis_valid(cmd_valid), - .m_axis_data(cmd_data), - .m_axis_level() - ); - - assign sdo_fifo_in_valid = up_wreq_s == 1'b1 && up_waddr_s == 8'h39; - assign sdo_fifo_in_data = up_wdata_s[(DATA_WIDTH-1):0]; - assign sdo_fifo_almost_empty = - `axi_spi_engine_check_watermark(sdo_fifo_room, SDO_FIFO_ADDRESS_WIDTH); - - util_axis_fifo #( - .DATA_WIDTH(DATA_WIDTH), - .ASYNC_CLK(ASYNC_SPI_CLK), - .ADDRESS_WIDTH(SDO_FIFO_ADDRESS_WIDTH), - .S_AXIS_REGISTERED(0) - ) i_sdo_fifo ( - .s_axis_aclk(clk), - .s_axis_aresetn(up_sw_resetn), - .s_axis_ready(sdo_fifo_in_ready), - .s_axis_valid(sdo_fifo_in_valid), - .s_axis_data(sdo_fifo_in_data), - .s_axis_room(sdo_fifo_room), - .s_axis_empty(), - .m_axis_aclk(spi_clk), - .m_axis_aresetn(spi_resetn), - .m_axis_ready(sdo_data_ready), - .m_axis_valid(sdo_data_valid), - .m_axis_data(sdo_data), - .m_axis_level() - ); - - assign sdi_fifo_out_ready = up_rreq_s == 1'b1 && up_raddr_s == 8'h3a; - assign sdi_fifo_almost_full = - `axi_spi_engine_check_watermark(sdi_fifo_level, SDI_FIFO_ADDRESS_WIDTH); - - util_axis_fifo #( - .DATA_WIDTH(NUM_OF_SDI * DATA_WIDTH), - .ASYNC_CLK(ASYNC_SPI_CLK), - .ADDRESS_WIDTH(SDI_FIFO_ADDRESS_WIDTH), - .S_AXIS_REGISTERED(0) - ) i_sdi_fifo ( - .s_axis_aclk(spi_clk), - .s_axis_aresetn(spi_resetn), - .s_axis_ready(sdi_data_ready), - .s_axis_valid(sdi_data_valid), - .s_axis_data(sdi_data), - .s_axis_room(), - .s_axis_empty(), - .m_axis_aclk(clk), - .m_axis_aresetn(up_sw_resetn), - .m_axis_ready(sdi_fifo_out_ready), - .m_axis_valid(sdi_fifo_out_valid), - .m_axis_data(sdi_fifo_out_data), - .m_axis_level(sdi_fifo_level) - ); - - generate if (ASYNC_SPI_CLK) begin - - // synchronization FIFO for the SYNC interface - util_axis_fifo #( - .DATA_WIDTH(8), - .ASYNC_CLK(ASYNC_SPI_CLK), - .ADDRESS_WIDTH(SYNC_FIFO_ADDRESS_WIDTH), - .S_AXIS_REGISTERED(0) - ) i_sync_fifo ( - .s_axis_aclk(spi_clk), - .s_axis_aresetn(spi_resetn), - .s_axis_ready(sync_ready), - .s_axis_valid(sync_valid), - .s_axis_data(sync_data), - .s_axis_room(), - .s_axis_empty(), - .m_axis_aclk(clk), - .m_axis_aresetn(up_sw_resetn), - .m_axis_ready(1'b1), - .m_axis_valid(sync_fifo_valid), - .m_axis_data(sync_fifo_data), - .m_axis_level() - ); - - // synchronization FIFO for the offload command interface - wire up_offload0_cmd_wr_en_s; - wire [15:0] up_offload0_cmd_wr_data_s; - - util_axis_fifo #( - .DATA_WIDTH(16), - .ASYNC_CLK(ASYNC_SPI_CLK), - .ADDRESS_WIDTH(SYNC_FIFO_ADDRESS_WIDTH), - .S_AXIS_REGISTERED(0) - ) i_offload_cmd_fifo ( - .s_axis_aclk(clk), - .s_axis_aresetn(up_sw_resetn), - .s_axis_ready(), - .s_axis_valid(up_offload0_cmd_wr_en_s), - .s_axis_data(up_offload0_cmd_wr_data_s), - .s_axis_room(), - .s_axis_empty(), - .m_axis_aclk(spi_clk), - .m_axis_aresetn(spi_resetn), - .m_axis_ready(1'b1), - .m_axis_valid(offload0_cmd_wr_en), - .m_axis_data(offload0_cmd_wr_data), - .m_axis_level() - ); - - assign up_offload0_cmd_wr_en_s = up_wreq_s == 1'b1 && up_waddr_s == 8'h44; - assign up_offload0_cmd_wr_data_s = up_wdata_s[15:0]; - - // synchronization FIFO for the offload SDO interface - wire up_offload0_sdo_wr_en_s; - wire [DATA_WIDTH-1:0] up_offload0_sdo_wr_data_s; - - util_axis_fifo #( - .DATA_WIDTH(DATA_WIDTH), - .ASYNC_CLK(ASYNC_SPI_CLK), - .ADDRESS_WIDTH(SYNC_FIFO_ADDRESS_WIDTH), - .S_AXIS_REGISTERED(0) - ) i_offload_sdo_fifo ( - .s_axis_aclk(clk), - .s_axis_aresetn(up_sw_resetn), - .s_axis_ready(), - .s_axis_valid(up_offload0_sdo_wr_en_s), - .s_axis_data(up_offload0_sdo_wr_data_s), - .s_axis_room(), - .s_axis_empty(), - .m_axis_aclk(spi_clk), - .m_axis_aresetn(spi_resetn), - .m_axis_ready(1'b1), - .m_axis_valid(offload0_sdo_wr_en), - .m_axis_data(offload0_sdo_wr_data), - .m_axis_level() - ); - - assign up_offload0_sdo_wr_en_s = up_wreq_s == 1'b1 && up_waddr_s == 8'h45; - assign up_offload0_sdo_wr_data_s = up_wdata_s[DATA_WIDTH-1:0]; - - // synchronization FIFO for the Offload SYNC interface - util_axis_fifo #( - .DATA_WIDTH(8), - .ASYNC_CLK(ASYNC_SPI_CLK), - .ADDRESS_WIDTH(SYNC_FIFO_ADDRESS_WIDTH), - .S_AXIS_REGISTERED(0) - ) i_offload_sync_fifo ( - .s_axis_aclk(spi_clk), - .s_axis_aresetn(spi_resetn), - .s_axis_ready(offload_sync_ready), - .s_axis_valid(offload_sync_valid), - .s_axis_data(offload_sync_data), - .s_axis_room(), - .s_axis_empty(), - .m_axis_aclk(clk), - .m_axis_aresetn(up_sw_resetn), - .m_axis_ready(1'b1), - .m_axis_valid(offload_sync_fifo_valid), - .m_axis_data(offload_sync_fifo_data), - .m_axis_level() - ); - - end else begin /* ASYNC_SPI_CLK == 0 */ - - assign sync_fifo_valid = sync_valid; - assign sync_fifo_data = sync_data; - assign sync_ready = 1'b1; - - assign offload0_cmd_wr_en = up_wreq_s == 1'b1 && up_waddr_s == 8'h44; - assign offload0_cmd_wr_data = up_wdata_s[15:0]; - - assign offload0_sdo_wr_en = up_wreq_s == 1'b1 && up_waddr_s == 8'h45; - assign offload0_sdo_wr_data = up_wdata_s[DATA_WIDTH-1:0]; - - assign offload_sync_fifo_valid = offload_sync_valid; - assign offload_sync_fifo_data = offload_sync_data; - assign offload_sync_ready = 1'b1; - - end - endgenerate - - sync_bits #( - .NUM_OF_BITS (1), - .ASYNC_CLK (ASYNC_SPI_CLK) - ) i_offload_enable_sync ( - .in_bits (offload0_enable_reg), - .out_resetn (spi_resetn), - .out_clk (spi_clk), - .out_bits (offload0_enable)); - - sync_bits #( - .NUM_OF_BITS (1), - .ASYNC_CLK (ASYNC_SPI_CLK) - ) i_offload_enabled_sync ( - .in_bits (offload0_enabled), - .out_resetn (up_sw_resetn), - .out_clk (clk), - .out_bits (offload0_enabled_s)); - - sync_bits #( - .NUM_OF_BITS (1), - .ASYNC_CLK (ASYNC_SPI_CLK) - ) i_offload_mem_reset_sync ( - .in_bits (offload0_mem_reset_reg), - .out_resetn (spi_resetn), - .out_clk (spi_clk), - .out_bits (offload0_mem_reset)); - -endmodule diff --git a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ipshared/cb53/sync_bits.v b/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ipshared/cb53/sync_bits.v deleted file mode 100644 index 7d30fb9..0000000 --- a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ipshared/cb53/sync_bits.v +++ /dev/null @@ -1,79 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. -// -// In this HDL repository, there are many different and unique modules, consisting -// of various HDL (Verilog or VHDL) components. The individual modules are -// developed independently, and may be accompanied by separate and unique license -// terms. -// -// The user should read each of these license terms, and understand the -// freedoms and responsibilities that he or she has by using this source/core. -// -// This core is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR -// A PARTICULAR PURPOSE. -// -// Redistribution and use of source or resulting binaries, with or without modification -// of this file, are permitted under one of the following two license terms: -// -// 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory -// of this repository (LICENSE_GPL2), and also online at: -// -// -// OR -// -// 2. An ADI specific BSD license, which can be found in the top level directory -// of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD -// This will allow to generate bit files and not release the source code, -// as long as it attaches to an ADI device. -// -// *************************************************************************** -// *************************************************************************** - -/* - * Helper module for synchronizing bit signals from one clock domain to another. - * It uses the standard approach of 2 FF in series. - * Note, that while the module allows to synchronize multiple bits at once it is - * only able to synchronize multi-bit signals where at max one bit changes per - * clock cycle (e.g. a gray counter). - */ - -`timescale 1ns/100ps - -module sync_bits #( - - // Number of bits to synchronize - parameter NUM_OF_BITS = 1, - // Whether input and output clocks are asynchronous, if 0 the synchronizer will - // be bypassed and the output signal equals the input signal. - parameter ASYNC_CLK = 1)( - - input [NUM_OF_BITS-1:0] in_bits, - input out_resetn, - input out_clk, - output [NUM_OF_BITS-1:0] out_bits); - -generate if (ASYNC_CLK == 1) begin - reg [NUM_OF_BITS-1:0] cdc_sync_stage1 = 'h0; - reg [NUM_OF_BITS-1:0] cdc_sync_stage2 = 'h0; - - always @(posedge out_clk) - begin - if (out_resetn == 1'b0) begin - cdc_sync_stage1 <= 'b0; - cdc_sync_stage2 <= 'b0; - end else begin - cdc_sync_stage1 <= in_bits; - cdc_sync_stage2 <= cdc_sync_stage1; - end - end - - assign out_bits = cdc_sync_stage2; -end else begin - assign out_bits = in_bits; -end endgenerate - -endmodule diff --git a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ipshared/cb53/sync_data.v b/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ipshared/cb53/sync_data.v deleted file mode 100644 index 164838e..0000000 --- a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ipshared/cb53/sync_data.v +++ /dev/null @@ -1,97 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. -// -// In this HDL repository, there are many different and unique modules, consisting -// of various HDL (Verilog or VHDL) components. The individual modules are -// developed independently, and may be accompanied by separate and unique license -// terms. -// -// The user should read each of these license terms, and understand the -// freedoms and responsibilities that he or she has by using this source/core. -// -// This core is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR -// A PARTICULAR PURPOSE. -// -// Redistribution and use of source or resulting binaries, with or without modification -// of this file, are permitted under one of the following two license terms: -// -// 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory -// of this repository (LICENSE_GPL2), and also online at: -// -// -// OR -// -// 2. An ADI specific BSD license, which can be found in the top level directory -// of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD -// This will allow to generate bit files and not release the source code, -// as long as it attaches to an ADI device. -// -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module sync_data #( - parameter NUM_OF_BITS = 1, - parameter ASYNC_CLK = 1 -) ( - input in_clk, - input [NUM_OF_BITS-1:0] in_data, - input out_clk, - output reg [NUM_OF_BITS-1:0] out_data -); - -generate -if (ASYNC_CLK == 1) begin - -wire out_toggle; -wire in_toggle; - -reg out_toggle_d1 = 1'b0; -reg in_toggle_d1 = 1'b0; - -reg [NUM_OF_BITS-1:0] cdc_hold; - -sync_bits i_sync_out ( - .in_bits(in_toggle_d1), - .out_clk(out_clk), - .out_resetn(1'b1), - .out_bits(out_toggle) -); - -sync_bits i_sync_in ( - .in_bits(out_toggle_d1), - .out_clk(in_clk), - .out_resetn(1'b1), - .out_bits(in_toggle) -); - -wire in_load = in_toggle == in_toggle_d1; -wire out_load = out_toggle ^ out_toggle_d1; - -always @(posedge in_clk) begin - if (in_load == 1'b1) begin - cdc_hold <= in_data; - in_toggle_d1 <= ~in_toggle_d1; - end -end - -always @(posedge out_clk) begin - if (out_load == 1'b1) begin - out_data <= cdc_hold; - end - out_toggle_d1 <= out_toggle; -end - -end else begin - always @(*) begin - out_data <= in_data; - end -end -endgenerate - -endmodule diff --git a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ipshared/cb53/sync_event.v b/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ipshared/cb53/sync_event.v deleted file mode 100644 index 33f0110..0000000 --- a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ipshared/cb53/sync_event.v +++ /dev/null @@ -1,120 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. -// -// In this HDL repository, there are many different and unique modules, consisting -// of various HDL (Verilog or VHDL) components. The individual modules are -// developed independently, and may be accompanied by separate and unique license -// terms. -// -// The user should read each of these license terms, and understand the -// freedoms and responsibilities that he or she has by using this source/core. -// -// This core is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR -// A PARTICULAR PURPOSE. -// -// Redistribution and use of source or resulting binaries, with or without modification -// of this file, are permitted under one of the following two license terms: -// -// 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory -// of this repository (LICENSE_GPL2), and also online at: -// -// -// OR -// -// 2. An ADI specific BSD license, which can be found in the top level directory -// of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD -// This will allow to generate bit files and not release the source code, -// as long as it attaches to an ADI device. -// -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module sync_event #( - parameter NUM_OF_EVENTS = 1, - parameter ASYNC_CLK = 1 -) ( - input in_clk, - input [NUM_OF_EVENTS-1:0] in_event, - input out_clk, - output reg [NUM_OF_EVENTS-1:0] out_event -); - -generate -if (ASYNC_CLK == 1) begin - -wire out_toggle; -wire in_toggle; - -reg out_toggle_d1 = 1'b0; -reg in_toggle_d1 = 1'b0; - -sync_bits i_sync_out ( - .in_bits(in_toggle_d1), - .out_clk(out_clk), - .out_resetn(1'b1), - .out_bits(out_toggle) -); - -sync_bits i_sync_in ( - .in_bits(out_toggle_d1), - .out_clk(in_clk), - .out_resetn(1'b1), - .out_bits(in_toggle) -); - -wire in_ready = in_toggle == in_toggle_d1; -wire load_out = out_toggle ^ out_toggle_d1; - -reg [NUM_OF_EVENTS-1:0] in_event_sticky = 'h00; -wire [NUM_OF_EVENTS-1:0] pending_events = in_event_sticky | in_event; -wire [NUM_OF_EVENTS-1:0] out_event_s; - -always @(posedge in_clk) begin - if (in_ready == 1'b1) begin - in_event_sticky <= {NUM_OF_EVENTS{1'b0}}; - if (|pending_events == 1'b1) begin - in_toggle_d1 <= ~in_toggle_d1; - end - end else begin - in_event_sticky <= pending_events; - end -end - -if (NUM_OF_EVENTS > 1) begin - reg [NUM_OF_EVENTS-1:0] cdc_hold = 'h00; - - always @(posedge in_clk) begin - if (in_ready == 1'b1) begin - cdc_hold <= pending_events; - end - end - - assign out_event_s = cdc_hold; -end else begin - // When there is only one event, we know that it is set. - assign out_event_s = 1'b1; -end - -always @(posedge out_clk) begin - if (load_out == 1'b1) begin - out_event <= out_event_s; - end else begin - out_event <= {NUM_OF_EVENTS{1'b0}}; - end - out_toggle_d1 <= out_toggle; -end - -end else begin - always @(*) begin - out_event <= in_event; - end -end -endgenerate - -endmodule diff --git a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ipshared/cb53/sync_gray.v b/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ipshared/cb53/sync_gray.v deleted file mode 100644 index 9382d9d..0000000 --- a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ipshared/cb53/sync_gray.v +++ /dev/null @@ -1,115 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. -// -// In this HDL repository, there are many different and unique modules, consisting -// of various HDL (Verilog or VHDL) components. The individual modules are -// developed independently, and may be accompanied by separate and unique license -// terms. -// -// The user should read each of these license terms, and understand the -// freedoms and responsibilities that he or she has by using this source/core. -// -// This core is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR -// A PARTICULAR PURPOSE. -// -// Redistribution and use of source or resulting binaries, with or without modification -// of this file, are permitted under one of the following two license terms: -// -// 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory -// of this repository (LICENSE_GPL2), and also online at: -// -// -// OR -// -// 2. An ADI specific BSD license, which can be found in the top level directory -// of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD -// This will allow to generate bit files and not release the source code, -// as long as it attaches to an ADI device. -// -// *************************************************************************** -// *************************************************************************** - -/* - * Helper module for synchronizing a counter from one clock domain to another - * using gray code. To work correctly the counter must not change its value by - * more than one in one clock cycle in the source domain. I.e. the value may - * change by either -1, 0 or +1. - */ - -`timescale 1ns/100ps - -module sync_gray #( - - // Bit-width of the counter - parameter DATA_WIDTH = 1, - // Whether the input and output clock are asynchronous, if set to 0 the - // synchronizer will be bypassed and out_count will be in_count. - parameter ASYNC_CLK = 1)( - - input in_clk, - input in_resetn, - input [DATA_WIDTH-1:0] in_count, - input out_resetn, - input out_clk, - output [DATA_WIDTH-1:0] out_count); - -generate if (ASYNC_CLK == 1) begin - reg [DATA_WIDTH-1:0] cdc_sync_stage0 = 'h0; - reg [DATA_WIDTH-1:0] cdc_sync_stage1 = 'h0; - reg [DATA_WIDTH-1:0] cdc_sync_stage2 = 'h0; - reg [DATA_WIDTH-1:0] out_count_m = 'h0; - - function [DATA_WIDTH-1:0] g2b; - input [DATA_WIDTH-1:0] g; - reg [DATA_WIDTH-1:0] b; - integer i; - begin - b[DATA_WIDTH-1] = g[DATA_WIDTH-1]; - for (i = DATA_WIDTH - 2; i >= 0; i = i - 1) - b[i] = b[i + 1] ^ g[i]; - g2b = b; - end - endfunction - - function [DATA_WIDTH-1:0] b2g; - input [DATA_WIDTH-1:0] b; - reg [DATA_WIDTH-1:0] g; - integer i; - begin - g[DATA_WIDTH-1] = b[DATA_WIDTH-1]; - for (i = DATA_WIDTH - 2; i >= 0; i = i -1) - g[i] = b[i + 1] ^ b[i]; - b2g = g; - end - endfunction - - always @(posedge in_clk) begin - if (in_resetn == 1'b0) begin - cdc_sync_stage0 <= 'h00; - end else begin - cdc_sync_stage0 <= b2g(in_count); - end - end - - always @(posedge out_clk) begin - if (out_resetn == 1'b0) begin - cdc_sync_stage1 <= 'h00; - cdc_sync_stage2 <= 'h00; - out_count_m <= 'h00; - end else begin - cdc_sync_stage1 <= cdc_sync_stage0; - cdc_sync_stage2 <= cdc_sync_stage1; - out_count_m <= g2b(cdc_sync_stage2); - end - end - - assign out_count = out_count_m; -end else begin - assign out_count = in_count; -end endgenerate - -endmodule diff --git a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ipshared/cf62/address_gray_pipelined.v b/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ipshared/cf62/address_gray_pipelined.v deleted file mode 100644 index 1b25554..0000000 --- a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ipshared/cf62/address_gray_pipelined.v +++ /dev/null @@ -1,152 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. -// -// In this HDL repository, there are many different and unique modules, consisting -// of various HDL (Verilog or VHDL) components. The individual modules are -// developed independently, and may be accompanied by separate and unique license -// terms. -// -// The user should read each of these license terms, and understand the -// freedoms and responsibilities that he or she has by using this source/core. -// -// This core is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR -// A PARTICULAR PURPOSE. -// -// Redistribution and use of source or resulting binaries, with or without modification -// of this file, are permitted under one of the following two license terms: -// -// 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory -// of this repository (LICENSE_GPL2), and also online at: -// -// -// OR -// -// 2. An ADI specific BSD license, which can be found in the top level directory -// of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD -// This will allow to generate bit files and not release the source code, -// as long as it attaches to an ADI device. -// -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module fifo_address_gray_pipelined #( - parameter ADDRESS_WIDTH = 4 -) ( - input m_axis_aclk, - input m_axis_aresetn, - input m_axis_ready, - output reg m_axis_valid, - output [ADDRESS_WIDTH-1:0] m_axis_raddr, - output reg [ADDRESS_WIDTH:0] m_axis_level, - - input s_axis_aclk, - input s_axis_aresetn, - output reg s_axis_ready, - input s_axis_valid, - output reg s_axis_empty, - output [ADDRESS_WIDTH-1:0] s_axis_waddr, - output reg [ADDRESS_WIDTH:0] s_axis_room -); - -localparam MAX_ROOM = {1'b1,{ADDRESS_WIDTH{1'b0}}}; - -reg [ADDRESS_WIDTH:0] _s_axis_waddr = 'h00; -reg [ADDRESS_WIDTH:0] _s_axis_waddr_next; -wire [ADDRESS_WIDTH:0] _s_axis_raddr; - -reg [ADDRESS_WIDTH:0] _m_axis_raddr = 'h00; -reg [ADDRESS_WIDTH:0] _m_axis_raddr_next; -wire [ADDRESS_WIDTH:0] _m_axis_waddr; - -assign s_axis_waddr = _s_axis_waddr[ADDRESS_WIDTH-1:0]; -assign m_axis_raddr = _m_axis_raddr[ADDRESS_WIDTH-1:0]; - -always @(*) -begin - if (s_axis_ready && s_axis_valid) - _s_axis_waddr_next <= _s_axis_waddr + 1'b1; - else - _s_axis_waddr_next <= _s_axis_waddr; -end - -always @(posedge s_axis_aclk) -begin - if (s_axis_aresetn == 1'b0) begin - _s_axis_waddr <= 'h00; - end else begin - _s_axis_waddr <= _s_axis_waddr_next; - end -end - -always @(*) -begin - if (m_axis_ready && m_axis_valid) - _m_axis_raddr_next <= _m_axis_raddr + 1'b1; - else - _m_axis_raddr_next <= _m_axis_raddr; -end - -always @(posedge m_axis_aclk) -begin - if (m_axis_aresetn == 1'b0) begin - _m_axis_raddr <= 'h00; - end else begin - _m_axis_raddr <= _m_axis_raddr_next; - end -end - -sync_gray #( - .DATA_WIDTH(ADDRESS_WIDTH + 1) -) i_waddr_sync ( - .in_clk(s_axis_aclk), - .in_resetn(s_axis_aresetn), - .out_clk(m_axis_aclk), - .out_resetn(m_axis_aresetn), - .in_count(_s_axis_waddr), - .out_count(_m_axis_waddr) -); - -sync_gray #( - .DATA_WIDTH(ADDRESS_WIDTH + 1) -) i_raddr_sync ( - .in_clk(m_axis_aclk), - .in_resetn(m_axis_aresetn), - .out_clk(s_axis_aclk), - .out_resetn(s_axis_aresetn), - .in_count(_m_axis_raddr), - .out_count(_s_axis_raddr) -); - -always @(posedge s_axis_aclk) -begin - if (s_axis_aresetn == 1'b0) begin - s_axis_ready <= 1'b1; - s_axis_empty <= 1'b1; - s_axis_room <= MAX_ROOM; - end else begin - s_axis_ready <= (_s_axis_raddr[ADDRESS_WIDTH] == _s_axis_waddr_next[ADDRESS_WIDTH] || - _s_axis_raddr[ADDRESS_WIDTH-1:0] != _s_axis_waddr_next[ADDRESS_WIDTH-1:0]); - s_axis_empty <= _s_axis_raddr == _s_axis_waddr_next; - s_axis_room <= _s_axis_raddr - _s_axis_waddr_next + MAX_ROOM; - end -end - -always @(posedge m_axis_aclk) -begin - if (m_axis_aresetn == 1'b0) begin - m_axis_valid <= 1'b0; - m_axis_level <= 'h00; - end else begin - m_axis_valid <= _m_axis_waddr != _m_axis_raddr_next; - m_axis_level <= _m_axis_waddr - _m_axis_raddr_next; - end -end - -endmodule - diff --git a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ipshared/cf62/address_sync.v b/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ipshared/cf62/address_sync.v deleted file mode 100644 index c6b074f..0000000 --- a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ipshared/cf62/address_sync.v +++ /dev/null @@ -1,109 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. -// -// In this HDL repository, there are many different and unique modules, consisting -// of various HDL (Verilog or VHDL) components. The individual modules are -// developed independently, and may be accompanied by separate and unique license -// terms. -// -// The user should read each of these license terms, and understand the -// freedoms and responsibilities that he or she has by using this source/core. -// -// This core is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR -// A PARTICULAR PURPOSE. -// -// Redistribution and use of source or resulting binaries, with or without modification -// of this file, are permitted under one of the following two license terms: -// -// 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory -// of this repository (LICENSE_GPL2), and also online at: -// -// -// OR -// -// 2. An ADI specific BSD license, which can be found in the top level directory -// of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD -// This will allow to generate bit files and not release the source code, -// as long as it attaches to an ADI device. -// -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module fifo_address_sync #( - parameter ADDRESS_WIDTH = 4 -) ( - input clk, - input resetn, - - input m_axis_ready, - output reg m_axis_valid, - output reg [ADDRESS_WIDTH-1:0] m_axis_raddr, - output [ADDRESS_WIDTH:0] m_axis_level, - - output reg s_axis_ready, - input s_axis_valid, - output reg s_axis_empty, - output reg [ADDRESS_WIDTH-1:0] s_axis_waddr, - output [ADDRESS_WIDTH:0] s_axis_room -); - -localparam MAX_ROOM = {1'b1,{ADDRESS_WIDTH{1'b0}}}; - -reg [ADDRESS_WIDTH:0] room = MAX_ROOM; -reg [ADDRESS_WIDTH:0] level = 'h00; -reg [ADDRESS_WIDTH:0] level_next; - -assign s_axis_room = room; -assign m_axis_level = level; - -wire read = m_axis_ready & m_axis_valid; -wire write = s_axis_ready & s_axis_valid; - -always @(posedge clk) -begin - if (resetn == 1'b0) begin - s_axis_waddr <= 'h00; - m_axis_raddr <= 'h00; - end else begin - if (write) - s_axis_waddr <= s_axis_waddr + 1'b1; - if (read) - m_axis_raddr <= m_axis_raddr + 1'b1; - end -end - -always @(*) -begin - if (read & ~write) - level_next <= level - 1'b1; - else if (~read & write) - level_next <= level + 1'b1; - else - level_next <= level; -end - -always @(posedge clk) -begin - if (resetn == 1'b0) begin - m_axis_valid <= 1'b0; - s_axis_ready <= 1'b0; - level <= 'h00; - room <= MAX_ROOM; - s_axis_empty <= 'h00; - end else begin - level <= level_next; - room <= MAX_ROOM - level_next; - m_axis_valid <= level_next != 0; - s_axis_ready <= level_next != MAX_ROOM; - s_axis_empty <= level_next == 0; - end -end - -endmodule - diff --git a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ipshared/cf62/util_axis_fifo.v b/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ipshared/cf62/util_axis_fifo.v deleted file mode 100644 index a62ad28..0000000 --- a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ipshared/cf62/util_axis_fifo.v +++ /dev/null @@ -1,248 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. -// -// In this HDL repository, there are many different and unique modules, consisting -// of various HDL (Verilog or VHDL) components. The individual modules are -// developed independently, and may be accompanied by separate and unique license -// terms. -// -// The user should read each of these license terms, and understand the -// freedoms and responsibilities that he or she has by using this source/core. -// -// This core is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR -// A PARTICULAR PURPOSE. -// -// Redistribution and use of source or resulting binaries, with or without modification -// of this file, are permitted under one of the following two license terms: -// -// 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory -// of this repository (LICENSE_GPL2), and also online at: -// -// -// OR -// -// 2. An ADI specific BSD license, which can be found in the top level directory -// of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD -// This will allow to generate bit files and not release the source code, -// as long as it attaches to an ADI device. -// -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module util_axis_fifo #( - parameter DATA_WIDTH = 64, - parameter ASYNC_CLK = 1, - parameter ADDRESS_WIDTH = 4, - parameter S_AXIS_REGISTERED = 1 -) ( - input m_axis_aclk, - input m_axis_aresetn, - input m_axis_ready, - output m_axis_valid, - output [DATA_WIDTH-1:0] m_axis_data, - output [ADDRESS_WIDTH:0] m_axis_level, - - input s_axis_aclk, - input s_axis_aresetn, - output s_axis_ready, - input s_axis_valid, - input [DATA_WIDTH-1:0] s_axis_data, - output s_axis_empty, - output [ADDRESS_WIDTH:0] s_axis_room -); - -generate if (ADDRESS_WIDTH == 0) begin - - reg [DATA_WIDTH-1:0] cdc_sync_fifo_ram; - reg s_axis_waddr = 1'b0; - reg m_axis_raddr = 1'b0; - - wire m_axis_waddr; - wire s_axis_raddr; - - sync_bits #( - .NUM_OF_BITS(1), - .ASYNC_CLK(ASYNC_CLK) - ) i_waddr_sync ( - .out_clk(m_axis_aclk), - .out_resetn(m_axis_aresetn), - .in_bits(s_axis_waddr), - .out_bits(m_axis_waddr) - ); - - sync_bits #( - .NUM_OF_BITS(1), - .ASYNC_CLK(ASYNC_CLK) - ) i_raddr_sync ( - .out_clk(s_axis_aclk), - .out_resetn(s_axis_aresetn), - .in_bits(m_axis_raddr), - .out_bits(s_axis_raddr) - ); - - assign m_axis_valid = m_axis_raddr != m_axis_waddr; - assign m_axis_level = m_axis_valid; - assign s_axis_ready = s_axis_raddr == s_axis_waddr; - assign s_axis_empty = s_axis_ready; - assign s_axis_room = s_axis_ready; - - always @(posedge s_axis_aclk) begin - if (s_axis_ready == 1'b1 && s_axis_valid == 1'b1) - cdc_sync_fifo_ram <= s_axis_data; - end - - always @(posedge s_axis_aclk) begin - if (s_axis_aresetn == 1'b0) begin - s_axis_waddr <= 1'b0; - end else begin - if (s_axis_ready & s_axis_valid) begin - s_axis_waddr <= s_axis_waddr + 1'b1; - end - end - end - - always @(posedge m_axis_aclk) begin - if (m_axis_aresetn == 1'b0) begin - m_axis_raddr <= 1'b0; - end else begin - if (m_axis_valid & m_axis_ready) - m_axis_raddr <= m_axis_raddr + 1'b1; - end - end - - assign m_axis_data = cdc_sync_fifo_ram; - -end else begin - - reg [DATA_WIDTH-1:0] ram[0:2**ADDRESS_WIDTH-1]; - - wire [ADDRESS_WIDTH-1:0] s_axis_waddr; - wire [ADDRESS_WIDTH-1:0] m_axis_raddr; - wire _m_axis_ready; - wire _m_axis_valid; - wire [ADDRESS_WIDTH:0] _m_axis_level; - - wire s_mem_write; - wire m_mem_read; - - reg valid; - - always @(posedge m_axis_aclk) begin - if (m_axis_aresetn == 1'b0) begin - valid <= 1'b0; - end else begin - if (_m_axis_valid) - valid <= 1'b1; - else if (m_axis_ready) - valid <= 1'b0; - end - end - - assign s_mem_write = s_axis_ready & s_axis_valid; - assign m_mem_read = (~valid || m_axis_ready) && _m_axis_valid; - - if (ASYNC_CLK == 1) begin - - // The assumption is that in this mode the S_AXIS_REGISTERED is 1 - - fifo_address_gray_pipelined #( - .ADDRESS_WIDTH(ADDRESS_WIDTH) - ) i_address_gray ( - .m_axis_aclk(m_axis_aclk), - .m_axis_aresetn(m_axis_aresetn), - .m_axis_ready(_m_axis_ready), - .m_axis_valid(_m_axis_valid), - .m_axis_raddr(m_axis_raddr), - .m_axis_level(_m_axis_level), - - .s_axis_aclk(s_axis_aclk), - .s_axis_aresetn(s_axis_aresetn), - .s_axis_ready(s_axis_ready), - .s_axis_valid(s_axis_valid), - .s_axis_empty(s_axis_empty), - .s_axis_waddr(s_axis_waddr), - .s_axis_room(s_axis_room) - ); - - // When the clocks are asynchronous instantiate a block RAM - // regardless of the requested size to make sure we threat the - // clock crossing correctly - ad_mem #( - .DATA_WIDTH (DATA_WIDTH), - .ADDRESS_WIDTH (ADDRESS_WIDTH)) - i_mem ( - .clka(s_axis_aclk), - .wea(s_mem_write), - .addra(s_axis_waddr), - .dina(s_axis_data), - .clkb(m_axis_aclk), - .reb(m_mem_read), - .addrb(m_axis_raddr), - .doutb(m_axis_data) - ); - - assign _m_axis_ready = ~valid || m_axis_ready; - assign m_axis_valid = valid; - // the util_axis_fifo is functioning in 'first write fall through' mode, - // which means that we need to assure that the value of the level reflects - // the actual FIFO level plus the available data, which sits on the bus - assign m_axis_level = (m_axis_valid) ? _m_axis_level + 1'b1 : _m_axis_level; - - end else begin - - fifo_address_sync #( - .ADDRESS_WIDTH(ADDRESS_WIDTH) - ) i_address_sync ( - .clk(m_axis_aclk), - .resetn(m_axis_aresetn), - .m_axis_ready(_m_axis_ready), - .m_axis_valid(_m_axis_valid), - .m_axis_raddr(m_axis_raddr), - .m_axis_level(m_axis_level), - - .s_axis_ready(s_axis_ready), - .s_axis_valid(s_axis_valid), - .s_axis_empty(s_axis_empty), - .s_axis_waddr(s_axis_waddr), - .s_axis_room(s_axis_room) - ); - - // When the clocks are synchronous use behavioral modeling for the SDP RAM - // Let the synthesizer decide what to infer (distributed or block RAM) - always @(posedge s_axis_aclk) begin - if (s_mem_write) - ram[s_axis_waddr] <= s_axis_data; - end - - if (S_AXIS_REGISTERED == 1) begin - - reg [DATA_WIDTH-1:0] data; - - always @(posedge m_axis_aclk) begin - if (m_mem_read) - data <= ram[m_axis_raddr]; - end - - assign _m_axis_ready = ~valid || m_axis_ready; - assign m_axis_data = data; - assign m_axis_valid = valid; - - end else begin - - assign _m_axis_ready = m_axis_ready; - assign m_axis_valid = _m_axis_valid; - assign m_axis_data = ram[m_axis_raddr]; - - end - - end - -end endgenerate - -endmodule diff --git a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ipshared/common/ad_mem.v b/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ipshared/common/ad_mem.v deleted file mode 100644 index 0843d4a..0000000 --- a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ipshared/common/ad_mem.v +++ /dev/null @@ -1,71 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. -// -// In this HDL repository, there are many different and unique modules, consisting -// of various HDL (Verilog or VHDL) components. The individual modules are -// developed independently, and may be accompanied by separate and unique license -// terms. -// -// The user should read each of these license terms, and understand the -// freedoms and responsibilities that he or she has by using this source/core. -// -// This core is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR -// A PARTICULAR PURPOSE. -// -// Redistribution and use of source or resulting binaries, with or without modification -// of this file, are permitted under one of the following two license terms: -// -// 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory -// of this repository (LICENSE_GPL2), and also online at: -// -// -// OR -// -// 2. An ADI specific BSD license, which can be found in the top level directory -// of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD -// This will allow to generate bit files and not release the source code, -// as long as it attaches to an ADI device. -// -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module ad_mem #( - - parameter DATA_WIDTH = 16, - parameter ADDRESS_WIDTH = 5) ( - - input clka, - input wea, - input [(ADDRESS_WIDTH-1):0] addra, - input [(DATA_WIDTH-1):0] dina, - - input clkb, - input reb, - input [(ADDRESS_WIDTH-1):0] addrb, - output reg [(DATA_WIDTH-1):0] doutb); - - (* ram_style = "block" *) - reg [(DATA_WIDTH-1):0] m_ram[0:((2**ADDRESS_WIDTH)-1)]; - - always @(posedge clka) begin - if (wea == 1'b1) begin - m_ram[addra] <= dina; - end - end - - always @(posedge clkb) begin - if (reb == 1'b1) begin - doutb <= m_ram[addrb]; - end - end - -endmodule - -// *************************************************************************** -// *************************************************************************** diff --git a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/system_bd.bd b/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/system_bd.bd index a0f7934..d3d412c 100644 --- a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/system_bd.bd +++ b/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/system_bd.bd @@ -1,7 +1,7 @@ { "design": { "design_info": { - "boundary_crc": "0xFFC3C3D2DEE0B4A1", + "boundary_crc": "0xFFC3C3D2D3E28C10", "device": "xc7z045ffg900-2", "gen_directory": "../../../../zc706_cx9261a_demo.gen/sources_1/bd/system_bd", "name": "system_bd", @@ -26,7 +26,8 @@ "m01_couplers": {} }, "xlconcat_irq": "", - "system_management": "" + "system_management": "", + "system_ila_spi": "" }, "interface_ports": { "ddr": { @@ -1385,7 +1386,12 @@ "interface_ports": [ "spi_engine_execution/spi", "spi" - ] + ], + "hdl_attributes": { + "DEBUG": { + "value": "true" + } + } }, "axi_spi_engine_spi_engine_ctrl": { "interface_ports": [ @@ -1422,15 +1428,20 @@ "spi_clk_0_1": { "ports": [ "spi_clk", - "axi_spi_engine/spi_clk", - "spi_engine_execution/clk" + "spi_engine_execution/clk", + "axi_spi_engine/spi_clk" ] }, "spi_engine_execution_active": { "ports": [ "spi_engine_execution/active", "active" - ] + ], + "hdl_attributes": { + "DEBUG": { + "value": "true" + } + } } } }, @@ -1887,6 +1898,40 @@ "value": "false" } } + }, + "system_ila_spi": { + "vlnv": "xilinx.com:ip:system_ila:1.1", + "ip_revision": "17", + "xci_name": "system_bd_system_ila_0_0", + "xci_path": "ip/system_bd_system_ila_0_0/system_bd_system_ila_0_0.xci", + "inst_hier_path": "system_ila_spi", + "parameters": { + "C_MON_TYPE": { + "value": "MIX" + }, + "C_NUM_MONITOR_SLOTS": { + "value": "1" + }, + "C_NUM_OF_PROBES": { + "value": "1" + }, + "C_PROBE0_TYPE": { + "value": "0" + }, + "C_SLOT_0_INTF_TYPE": { + "value": "analog.com:interface:spi_engine_rtl:1.0" + }, + "C_SLOT_0_TYPE": { + "value": "0" + } + }, + "interface_ports": { + "SLOT_0_SPI_ENGINE": { + "mode": "Monitor", + "vlnv_bus_definition": "analog.com:interface:spi_engine:1.0", + "vlnv": "analog.com:interface:spi_engine_rtl:1.0" + } + } } }, "interface_nets": { @@ -1911,8 +1956,17 @@ "axi_spi_engine_spi": { "interface_ports": [ "spi", - "axi_spi_engine/spi" - ] + "axi_spi_engine/spi", + "system_ila_spi/SLOT_0_SPI_ENGINE" + ], + "hdl_attributes": { + "DEBUG": { + "value": "true" + }, + "MARK_DEBUG": { + "value": "true" + } + } }, "processing_system7_DDR": { "interface_ports": [ @@ -1943,8 +1997,17 @@ "axi_spi_engine_active": { "ports": [ "axi_spi_engine/active", - "spi_active" - ] + "spi_active", + "system_ila_spi/probe0" + ], + "hdl_attributes": { + "DEBUG": { + "value": "true" + }, + "MARK_DEBUG": { + "value": "true" + } + } }, "axi_spi_engine_irq": { "ports": [ @@ -1957,7 +2020,6 @@ "processing_system7/FCLK_CLK0", "processing_system7/M_AXI_GP0_ACLK", "axi_spi_engine/s_axi_aclk", - "axi_spi_engine/spi_clk", "axi_interconnect_0/ACLK", "axi_interconnect_0/S00_ACLK", "axi_interconnect_0/M00_ACLK", @@ -1969,7 +2031,9 @@ "processing_system7_FCLK_CLK1": { "ports": [ "processing_system7/FCLK_CLK1", - "ps_clk_200M" + "ps_clk_200M", + "axi_spi_engine/spi_clk", + "system_ila_spi/clk" ] }, "processing_system7_FCLK_RESET0_N": { diff --git a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ui/bd_c6d0cb12.ui b/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ui/bd_c6d0cb12.ui index 5cddb56..baf904e 100644 --- a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ui/bd_c6d0cb12.ui +++ b/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ui/bd_c6d0cb12.ui @@ -1,45 +1,46 @@ { "ActiveEmotionalView":"Default View", "Default View_ScaleFactor":"0.798638", - "Default View_TopLeft":"-533,0", + "Default View_TopLeft":"-601,1", "ExpandedHierarchyInLayout":"", "guistr":"# # String gsaved with Nlview 7.7.1 2023-07-26 3bc4126617 VDI=43 GEI=38 GUI=JA:21.0 TLS # -string -flagsOSRD -preplace port ddr -pg 1 -lvl 3 -x 930 -y 150 -defaultsOSRD -preplace port fixed_io -pg 1 -lvl 3 -x 930 -y 170 -defaultsOSRD -preplace port Vp_Vn -pg 1 -lvl 0 -x 0 -y 590 -defaultsOSRD -preplace port port-id_spi_active -pg 1 -lvl 3 -x 930 -y 70 -defaultsOSRD -preplace port port-id_ps_clk_200M -pg 1 -lvl 3 -x 930 -y 190 -defaultsOSRD -preplace port spi -pg 1 -lvl 3 -x 930 -y 930 -defaultsOSRD -preplace portBus gpio_i -pg 1 -lvl 3 -x 930 -y 90 -defaultsOSRD -right -preplace portBus gpio_o -pg 1 -lvl 3 -x 930 -y 110 -defaultsOSRD -preplace portBus gpio_t -pg 1 -lvl 3 -x 930 -y 130 -defaultsOSRD +preplace port ddr -pg 1 -lvl 3 -x 1040 -y 150 -defaultsOSRD +preplace port fixed_io -pg 1 -lvl 3 -x 1040 -y 170 -defaultsOSRD +preplace port Vp_Vn -pg 1 -lvl 0 -x -10 -y 590 -defaultsOSRD +preplace port spi -pg 1 -lvl 3 -x 1040 -y 930 -defaultsOSRD +preplace port port-id_spi_active -pg 1 -lvl 3 -x 1040 -y 70 -defaultsOSRD +preplace port port-id_ps_clk_200M -pg 1 -lvl 3 -x 1040 -y 190 -defaultsOSRD +preplace portBus gpio_i -pg 1 -lvl 3 -x 1040 -y 90 -defaultsOSRD -right +preplace portBus gpio_o -pg 1 -lvl 3 -x 1040 -y 110 -defaultsOSRD +preplace portBus gpio_t -pg 1 -lvl 3 -x 1040 -y 130 -defaultsOSRD preplace inst processing_system7 -pg 1 -lvl 1 -x 260 -y 200 -defaultsOSRD preplace inst axi_spi_engine -pg 1 -lvl 1 -x 260 -y 950 -defaultsOSRD -preplace inst rst_ps7_50M -pg 1 -lvl 2 -x 710 -y 270 -defaultsOSRD +preplace inst rst_ps7_50M -pg 1 -lvl 2 -x 740 -y 270 -defaultsOSRD preplace inst axi_interconnect_0 -pg 1 -lvl 1 -x 260 -y 740 -defaultsOSRD -preplace inst xlconcat_irq -pg 1 -lvl 2 -x 710 -y 420 -defaultsOSRD -orient R180 -preplace inst system_management -pg 1 -lvl 2 -x 710 -y 600 -defaultsOSRD -preplace netloc processing_system7_FCLK_CLK0 1 0 2 20 10 510 -preplace netloc processing_system7_FCLK_RESET0_N 1 1 1 500 250n -preplace netloc rst_ps7_50M_peripheral_aresetn 1 0 3 40 580 530J 490 910 +preplace inst xlconcat_irq -pg 1 -lvl 2 -x 740 -y 420 -defaultsOSRD -orient R180 +preplace inst system_management -pg 1 -lvl 2 -x 740 -y 600 -defaultsOSRD +preplace inst system_ila_spi -pg 1 -lvl 2 -x 740 -y 90 -defaultsOSRD +preplace netloc GPIO_I_0_1 1 1 2 530 490 950 +preplace netloc axi_spi_engine_active 1 1 2 560J 750 970 +preplace netloc axi_spi_engine_irq 1 1 2 N 970 930 +preplace netloc processing_system7_FCLK_CLK0 1 0 2 10 10 480 +preplace netloc processing_system7_FCLK_CLK1 1 0 3 20 570 540J 710 1000J +preplace netloc processing_system7_FCLK_RESET0_N 1 1 1 550 250n +preplace netloc processing_system7_GPIO_O 1 1 2 510J 730 980J +preplace netloc processing_system7_GPIO_T 1 1 2 500J 720 990J +preplace netloc rst_ps7_50M_peripheral_aresetn 1 0 3 40 580 490J 740 940 +preplace netloc system_management_ip2intc_irpt 1 2 1 920 410n preplace netloc xlconcat_irq_dout 1 0 2 50 420 N -preplace netloc processing_system7_FCLK_CLK1 1 1 2 480J 140 910J -preplace netloc GPIO_I_0_1 1 1 2 N 90 N -preplace netloc processing_system7_GPIO_O 1 1 2 NJ 110 NJ -preplace netloc processing_system7_GPIO_T 1 1 2 NJ 130 NJ -preplace netloc system_management_ip2intc_irpt 1 2 1 900 410n -preplace netloc axi_spi_engine_active 1 1 2 490J 70 N -preplace netloc axi_spi_engine_irq 1 1 2 N 970 890 -preplace netloc processing_system7_DDR 1 1 2 NJ 150 N -preplace netloc processing_system7_M_AXI_GP0 1 0 2 30 390 470 -preplace netloc axi_interconnect_0_M00_AXI 1 0 2 50 600 470 -preplace netloc processing_system7_FIXED_IO 1 1 2 NJ 170 N -preplace netloc axi_interconnect_0_M01_AXI 1 1 1 520 570n preplace netloc Vp_Vn_0_1 1 0 2 NJ 590 NJ -preplace netloc axi_spi_engine_spi 1 1 2 NJ 930 NJ -levelinfo -pg 1 0 260 710 930 -pagesize -pg 1 -db -bbox -sgen -100 0 1070 1030 +preplace netloc axi_interconnect_0_M00_AXI 1 0 2 50 600 470 +preplace netloc axi_interconnect_0_M01_AXI 1 1 1 550 570n +preplace netloc axi_spi_engine_spi 1 1 2 520J 930 NJ +preplace netloc processing_system7_DDR 1 1 2 490J 10 960 +preplace netloc processing_system7_FIXED_IO 1 1 2 NJ 170 N +preplace netloc processing_system7_M_AXI_GP0 1 0 2 30 390 470 +levelinfo -pg 1 -10 260 740 1040 +pagesize -pg 1 -db -bbox -sgen -110 0 1180 1030 " } { diff --git a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ui/bd_e4e34314.ui b/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ui/bd_e4e34314.ui index e7eccb5..34345e2 100644 --- a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ui/bd_e4e34314.ui +++ b/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ui/bd_e4e34314.ui @@ -1,23 +1,29 @@ { "ActiveEmotionalView":"Default View", "Default View_ScaleFactor":"1.0", - "Default View_TopLeft":"-438,-327", + "Default View_TopLeft":"-423,-321", "ExpandedHierarchyInLayout":"", "guistr":"# # String gsaved with Nlview 7.7.1 2023-07-26 3bc4126617 VDI=43 GEI=38 GUI=JA:21.0 TLS # -string -flagsOSRD preplace port s_axi -pg 1 -lvl 0 -x -10 -y 60 -defaultsOSRD -preplace port spi_0 -pg 1 -lvl 3 -x 1040 -y 90 -defaultsOSRD +preplace port spi -pg 1 -lvl 3 -x 1040 -y 80 -defaultsOSRD preplace port port-id_s_axi_aclk -pg 1 -lvl 0 -x -10 -y 80 -defaultsOSRD preplace port port-id_s_axi_aresetn -pg 1 -lvl 0 -x -10 -y 100 -defaultsOSRD preplace port port-id_spi_clk -pg 1 -lvl 0 -x -10 -y 120 -defaultsOSRD +preplace port port-id_active -pg 1 -lvl 3 -x 1040 -y 100 -defaultsOSRD +preplace port port-id_irq -pg 1 -lvl 3 -x 1040 -y 170 -defaultsOSRD preplace inst axi_spi_engine -pg 1 -lvl 1 -x 640 -y 90 -defaultsOSRD -preplace inst spi_engine_execution_0 -pg 1 -lvl 2 -x 890 -y 100 -defaultsOSRD +preplace inst spi_engine_execution -pg 1 -lvl 2 -x 900 -y 90 -defaultsOSRD +preplace netloc axi_spi_engine_irq 1 1 2 780J 170 NJ +preplace netloc axi_spi_engine_spi_resetn 1 1 1 N 110 preplace netloc s_axi_aclk_0_1 1 0 1 N 80 preplace netloc s_axi_aresetn_0_1 1 0 1 N 100 -preplace netloc spi_clk_0_1 1 0 1 N 120 +preplace netloc spi_clk_0_1 1 0 2 500 180 790 +preplace netloc spi_engine_execution_active 1 2 1 NJ 100 preplace netloc Conn1 1 0 1 N 60 -preplace netloc Conn2 1 2 1 N 90 -levelinfo -pg 1 -10 640 890 1040 +preplace netloc Conn2 1 2 1 N 80 +preplace netloc axi_spi_engine_spi_engine_ctrl 1 1 1 N 70 +levelinfo -pg 1 -10 640 900 1040 pagesize -pg 1 -db -bbox -sgen -160 -480 1140 330 " } diff --git a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/ip/coe/CreatePN40_LocalTemp_256points.m b/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/ip/coe/CreatePN40_LocalTemp_256points.m new file mode 100644 index 0000000..8851095 --- /dev/null +++ b/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/ip/coe/CreatePN40_LocalTemp_256points.m @@ -0,0 +1,75 @@ +%% PN56 +clc;clear;close all; +addpath(genpath(pwd)); +%% 参数设置 +load("PN40_reverse.mat"); +% GMSK 调制的参数 +BT = 0.3; +Rc = 1.5e6; % 码片速率 1.4Mcps +fs_clk = 48e6; % ADC 的采样速率 +fs_acq = 4.8e6; % 捕获模块采样速率为3.2M, 与 Rc并不是整数倍关系 + +SampRate = fs_clk/Rc; % 对于码片的过采样率 +% PN 码,帧结构参数 +PNLen = 40; % 一组PN码的长度 + +% 捕获时参数 +FFT_Len = 256; +Acq_Sample = fs_acq/Rc; %捕获时,采用的过采样率 +FreSearchIdx = 0; +%% 发送端 +frameSend = repmat(PN40,1,40); +[GMSKSendWave] = gmsk_base_modfpga_fuc(frameSend,BT,SampRate,4); + +%变采样率,获取本地模板 +% h = LPF_Fpass1p8_Fstop2p2_Fs48_40dB; +% hLen = floor(length(h)/2); +% +% GMSKSendWave2 = conv(GMSKSendWave,h); +% GMSKSendWave2 = GMSKSendWave2(hLen+1:end-hLen); +% 对抗混叠滤波后的数据,进行抽取 +% Acq_Din = downsample(GMSKSendWave2,fs_clk/fs_acq); +Acq_Din = downsample(GMSKSendWave,fs_clk/fs_acq); +% 取本地模板 +PNWave = Acq_Din(1:FFT_Len); + +PNWaveLocalTemp = PNWave(1:FFT_Len); +PNWaveLocalTemp_Norm = PNWaveLocalTemp/max(PNWaveLocalTemp); + +Acq_FFTLocalTemp = fft(PNWave,FFT_Len); +Acq_FFTLocalTemp_Norm = Acq_FFTLocalTemp/max(abs(Acq_FFTLocalTemp)); + + +%save("GMSKSendWave.mat","GMSKSendWave"); + +%归一化并量化 +q = quantizer([16, 15], 'fixed', 'convergent', 'saturate'); +Acq_FFTLocalTemp_Norm = quantize(q,Acq_FFTLocalTemp_Norm); + +% 转换为 16进制 +Acq_FFTLocalTemp_I_FPGA = num2hex(q,real(Acq_FFTLocalTemp_Norm)); +Acq_FFTLocalTemp_Q_FPGA = num2hex(q,imag(Acq_FFTLocalTemp_Norm)); +Acq_FFTLocalTemp_FPGA = [Acq_FFTLocalTemp_Q_FPGA,Acq_FFTLocalTemp_I_FPGA]; + +%% 写入到 coe 文件中 +data = Acq_FFTLocalTemp_FPGA; +fid = fopen("New_AcqPN40_FFTLocalTemp_256points.coe",'w'); +fprintf(fid,'memory_initialization_radix=16;\n'); +fprintf(fid,'memory_initialization_vector=\n'); +for i = 1:length(data) + fprintf(fid,'%s\n',data(i,:)); +end +fclose(fid); + +% %% 保存Maltab 变量 +% save("Acq_FFTLocalTemp.mat","Acq_FFTLocalTemp_Norm","Acq_FFTLocalTemp_FPGA"); +% +save("New_AcqPN40_FFTLocalTemp_256points.mat","Acq_FFTLocalTemp_Norm","PNWaveLocalTemp_Norm"); + +%% +rmpath(genpath(pwd)); + + + + + diff --git a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/ip/coe/coe_gen.m b/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/ip/coe/coe_gen.m new file mode 100644 index 0000000..7b89440 --- /dev/null +++ b/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/ip/coe/coe_gen.m @@ -0,0 +1,90 @@ +function coe_gen(data,file_name,varargin)%varargin : type radix [bit_width] +%coe_gen - Xilinx coe文件生成，根据官网语法说明编写 +% +% coe_gen(data, file_nanme) +% coe_gen(data,file_name,type) +% coe_gen(data,file_name,type, 'd') +% coe_gen(data,file_name,type, radix, bit_width) +% +% data - integer double 需要写入的数据,整数或定点小数一维向量 +% 为定点数时，只能使用十进制保存 +% file_name - char 文件名或完成存放路径 +% type - char coe文件类型 'memory' 'filter' 'correlator' 'interleaver' +% radix - char 数据保存进制 'b' 'd' 'h' +% 'b' 二进制 +% 'd' 十进制 +% 'h' 十六进制 +% 二进制与十六进制时候需要指明位宽 +% bit_width - integer 数据位宽 +% +% Author: Fan Hao. +% References: https://www.xilinx.com/support/documentation/sw_manuals/xilinx11/cgn_r_coe_file_syntax.htm +% Copyright Beijing Institute of Technology. + radix_dic_str = ['b','o','d','h']; + radix_dic_num = [2 8 10 16]; + narginchk(2,5); + %input check + if isempty(varargin) %default properties + radix = 10; type = 'memory'; + else %type check + if length(varargin)>=1 &&ismember(varargin{1},{'memory','filter','correlator','interleaver'}) + type = varargin{1}; + else + error('ERROR: wrong coe file type!'); + end%radix and bit_width check + if length(varargin)>=2 && ismember(varargin{2},['b','d','h']) + radix = radix_dic_num(radix_dic_str==varargin{2}); + if varargin{2} ~= 'd' + if length(varargin)==3 && ~mod(varargin{3},1) + bit_width = varargin{3}; + else + error('ERROR: bit width must be specified as a integer.'); + end + else + if length(varargin)==3 + error('ERROR: too many argument.'); + end + end + else + if length(varargin)==1 + radix = 10; + else + error("ERROR: radix must be 'b' or 'd' or 'h'."); + end + end + end + %create file + file_p = fopen(file_name, 'w+', 'n', 'UTF-8'); + if type == 'memory' + fprintf(file_p,['MEMORY_INITIALIZATION_RADIX = ' num2str(radix) ';\n']); + else + fprintf(file_p,['RADIX = ' num2str(radix) ';\n']); + end + switch type + case 'memory' + fprintf(file_p,['MEMORY_INITIALIZATION_VECTOR = ' '\n']); + case 'filter' + fprintf(file_p,['COEFDATA = ' '\n']); + case 'correlator' + fprintf(file_p,['PATTERN = ' '\n']); + case 'interleaver' + fprintf(file_p,['BRANCH_LENGTH_VECTOR = ' '\n']); + end + for i = 1:length(data) + switch radix + case 2 + temp = dec2bin(data(i),bit_width); + case 10 + temp = num2str(data(i)); + case 16 + temp = dec2hex(data(i),ceil(bit_width/4)); + end + if i == length(data) + fprintf(file_p,[temp ';\n']); + else + fprintf(file_p,[temp ',\n']); + end + end + fclose(file_p); +end + diff --git a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/ip/coe/generate_baseband_coe.m b/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/ip/coe/generate_baseband_coe.m new file mode 100644 index 0000000..eb192b0 --- /dev/null +++ b/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/ip/coe/generate_baseband_coe.m @@ -0,0 +1,29 @@ +% clear all +% clc +% % pnSequence=comn.PNSequence('Polynomial','x^10+x^7+1','InitialConditions',[zeros(1,9),1],'SamplesPerFrame',2^10-1); +% % PRBS10=pnSequence(); +% % PRB10_polar=1-2*[ PRBS10;0]; +% % coe_gen(PRBS10,'prbs10.coe','memory'); +% hrc=rcosdesign(0.35,6,8,'sqrt'); +% %hrc=rcosdesign(0.25,12,64); +% hrc_16b=round(hrc/max(hrc)*(2^15-1)); +% %coe_gen(hrc_16b,'hrc_64_12_025.coe','memory'); +% coe_gen(hrc_16b,'hrc_8_6_035.coe','memory'); + +clear all +clc +fs = 64e6; +Rs = 48e6; +alpha = 0.3; + +hrc_48 = rcosdesign(alpha,12,4,'sqrt');%span=6,sps=4 +hrc_48_16b=round(hrc_48/max(hrc_48)*(2^15-1)); +coe_gen(hrc_48_16b,'hrc_4_12_03.coe','memory'); + +hrc_12 = rcosdesign(alpha,12,16,'sqrt'); +hrc_12_16b=round(hrc_12/max(hrc_12)*(2^15-1)); +coe_gen(hrc_12_16b,'hrc_16_12_03.coe','memory'); + +hrc_1p5 = rcosdesign(alpha,12,128,'sqrt'); +hrc_1p5_16b=round(hrc_1p5/max(hrc_1p5)*(2^15-1)); +coe_gen(hrc_1p5_16b,'hrc_128_12_03.coe','memory'); \ No newline at end of file diff --git a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/ip/coe/hrc_128_12_03.coe b/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/ip/coe/hrc_128_12_03.coe new file mode 100644 index 0000000..5c769ed --- /dev/null +++ b/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/ip/coe/hrc_128_12_03.coe @@ -0,0 +1,1539 @@ +RADIX = 10; +COEFDATA = +-203, +-198, +-194, +-189, +-184, +-179, +-174, +-169, +-163, +-157, +-151, +-145, +-138, +-132, +-125, +-118, +-111, +-104, +-97, +-89, +-82, +-74, +-66, +-58, +-50, +-42, +-34, +-26, +-17, +-9, +0, +8, +17, +25, +34, +42, +51, +60, +68, +77, +85, +94, +102, +111, +119, +127, +136, +144, +152, +160, +167, +175, +183, +190, +197, +205, +212, +218, +225, +231, +238, +244, +250, +255, +261, +266, +271, +276, +280, +285, +289, +293, +296, +299, +302, +305, +308, +310, +312, +313, +315, +316, +316, +317, +317, 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+-169, +-174, +-179, +-184, +-189, +-194, +-198, +-203; diff --git a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/ip/coe/hrc_16_12_03.coe b/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/ip/coe/hrc_16_12_03.coe new file mode 100644 index 0000000..6677441 --- /dev/null +++ b/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/ip/coe/hrc_16_12_03.coe @@ -0,0 +1,195 @@ +RADIX = 10; +COEFDATA = +-203, +-163, +-111, +-50, +17, +85, +152, +212, +261, +296, +315, +315, +295, +257, +203, +134, +55, +-29, +-113, +-191, +-258, +-309, +-340, +-348, +-331, +-290, +-226, +-142, +-43, +64, +172, +273, +360, +426, +462, +465, +432, +360, +252, +112, +-55, +-238, +-428, +-612, +-778, +-911, +-1000, +-1033, +-1003, +-903, +-732, +-492, +-190, +163, +553, +960, +1363, +1738, +2060, +2305, +2451, +2476, +2368, +2114, +1714, +1171, +497, +-288, +-1154, +-2067, +-2986, +-3864, +-4652, +-5298, +-5752, +-5968, +-5902, +-5521, +-4797, +-3715, +-2271, +-476, +1651, +4073, +6744, +9606, +12592, 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b/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/ip/coe/hrc_4_12_03.coe @@ -0,0 +1,51 @@ +RADIX = 10; +COEFDATA = +-203, +17, +261, +295, +55, +-258, +-331, +-43, +360, +432, +-55, +-778, +-1003, +-190, +1363, +2451, +1714, +-1154, +-4652, +-5902, +-2271, +6744, +18635, +28782, +32767, +28782, +18635, +6744, +-2271, +-5902, +-4652, +-1154, +1714, +2451, +1363, +-190, +-1003, +-778, +-55, +432, +360, +-43, +-331, +-258, +55, +295, +261, +17, +-203; diff --git a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/ip/cx9261a_fifo/cx9261a_fifo.xci b/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/ip/cx9261a_fifo/cx9261a_fifo.xci new file mode 100644 index 0000000..6d6ed1d --- /dev/null +++ b/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/ip/cx9261a_fifo/cx9261a_fifo.xci @@ -0,0 +1,479 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "cx9261a_fifo", + "component_reference": "xilinx.com:ip:fifo_generator:13.2", + "ip_revision": "10", + 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"CLK": [ { "physical_name": "clk" } ] - } - } - } - } - } -} \ No newline at end of file diff --git a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/ip/sys_clk_gen/sys_clk_gen.xci b/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/ip/sys_clk_gen/sys_clk_gen.xci new file mode 100644 index 0000000..119a40c --- /dev/null +++ b/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/ip/sys_clk_gen/sys_clk_gen.xci @@ -0,0 +1,676 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "sys_clk_gen", + "component_reference": "xilinx.com:ip:clk_wiz:6.0", + "ip_revision": "14", + "gen_directory": "../../../../zc706_cx9261a_demo.gen/sources_1/ip/sys_clk_gen", + "parameters": { + "component_parameters": { + "Component_Name": [ { "value": "sys_clk_gen", "resolve_type": "user", "usage": "all" } ], + "USER_CLK_FREQ0": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "USER_CLK_FREQ1": [ { "value": "100.0", "resolve_type": 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"C_PLL_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLOCK_MGR_TYPE": [ { "value": "NA", "resolve_type": "generated", "usage": "all" } ], + "C_OVERRIDE_MMCM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_OVERRIDE_PLL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_PRIMARY_PORT": [ { "value": "clk_in1", "resolve_type": "generated", "usage": "all" } ], + "C_SECONDARY_PORT": [ { "value": "clk_in2", "resolve_type": "generated", "usage": "all" } ], + "C_CLK_OUT1_PORT": [ { "value": "clk_out1", "resolve_type": "generated", "usage": "all" } ], + "C_CLK_OUT2_PORT": [ { "value": "clk_out2", "resolve_type": "generated", "usage": "all" } ], + "C_CLK_OUT3_PORT": [ { "value": "clk_out3", "resolve_type": "generated", "usage": "all" } ], + "C_CLK_OUT4_PORT": [ { "value": "clk_out4", "resolve_type": "generated", "usage": "all" } ], + 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"clkfb_out_n", "resolve_type": "generated", "usage": "all" } ], + "C_POWER_DOWN_PORT": [ { "value": "power_down", "resolve_type": "generated", "usage": "all" } ], + "C_DADDR_PORT": [ { "value": "daddr", "resolve_type": "generated", "usage": "all" } ], + "C_DCLK_PORT": [ { "value": "dclk", "resolve_type": "generated", "usage": "all" } ], + "C_DRDY_PORT": [ { "value": "drdy", "resolve_type": "generated", "usage": "all" } ], + "C_DWE_PORT": [ { "value": "dwe", "resolve_type": "generated", "usage": "all" } ], + "C_DIN_PORT": [ { "value": "din", "resolve_type": "generated", "usage": "all" } ], + "C_DOUT_PORT": [ { "value": "dout", "resolve_type": "generated", "usage": "all" } ], + "C_DEN_PORT": [ { "value": "den", "resolve_type": "generated", "usage": "all" } ], + "C_PSCLK_PORT": [ { "value": "psclk", "resolve_type": "generated", "usage": "all" } ], + "C_PSEN_PORT": [ { "value": "psen", "resolve_type": "generated", "usage": "all" } ], + "C_PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "generated", "usage": "all" } ], + "C_PSDONE_PORT": [ { "value": "psdone", "resolve_type": "generated", "usage": "all" } ], + "C_CLK_VALID_PORT": [ { "value": "CLK_VALID", "resolve_type": "generated", "usage": "all" } ], + "C_STATUS_PORT": [ { "value": "STATUS", "resolve_type": "generated", "usage": "all" } ], + "C_CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "generated", "usage": "all" } ], + "C_INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "generated", "usage": "all" } ], + "C_CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "generated", "usage": "all" } ], + "C_CLKIN1_JITTER_PS": [ { "value": "78.12", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "generated", "usage": "all" } ], + "C_SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "generated", "usage": "all" } ], + "C_SS_MOD_PERIOD": [ { "value": "4000", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_SS_MOD_TIME": [ { "value": "0.004", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_HAS_CDDC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_CDDCDONE_PORT": [ { "value": "cddcdone", "resolve_type": "generated", "usage": "all" } ], + "C_CDDCREQ_PORT": [ { "value": "cddcreq", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUTPHY_MODE": [ { "value": "VCO", "resolve_type": "generated", "usage": "all" } ], + "C_ENABLE_CLKOUTPHY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_INTERFACE_SELECTION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_S_AXI_ADDR_WIDTH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_S_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_POWER_REG": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT0_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT0_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT1_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT1_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT2_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT2_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT3_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT3_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT4_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT4_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT5_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT5_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT6_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT6_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKFBOUT_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKFBOUT_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_DIVCLK": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_LOCK_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_LOCK_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_LOCK_3": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_FILTER_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_FILTER_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_DIVIDE1_AUTO": [ { "value": "1", "resolve_type": "generated", "usage": "all" } ], + "C_DIVIDE2_AUTO": [ { "value": "1.3333333333333333", "resolve_type": "generated", "usage": "all" } ], + "C_DIVIDE3_AUTO": [ { "value": "0.06349206349206349", "resolve_type": "generated", "usage": "all" } ], + "C_DIVIDE4_AUTO": [ { "value": "0.06349206349206349", "resolve_type": "generated", "usage": "all" } ], + "C_DIVIDE5_AUTO": [ { "value": "0.06349206349206349", "resolve_type": "generated", "usage": "all" } ], + "C_DIVIDE6_AUTO": [ { "value": "0.06349206349206349", "resolve_type": "generated", "usage": "all" } ], + "C_DIVIDE7_AUTO": [ { "value": "0.06349206349206349", "resolve_type": "generated", "usage": "all" } ], + "C_PLLBUFGCEDIV": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_MMCMBUFGCEDIV": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_PLLBUFGCEDIV1": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_PLLBUFGCEDIV2": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_PLLBUFGCEDIV3": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_PLLBUFGCEDIV4": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_MMCMBUFGCEDIV1": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_MMCMBUFGCEDIV2": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_MMCMBUFGCEDIV3": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_MMCMBUFGCEDIV4": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_MMCMBUFGCEDIV5": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_MMCMBUFGCEDIV6": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_MMCMBUFGCEDIV7": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT1_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT2_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT3_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT4_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT0_ACTUAL_FREQ": [ { "value": "64.00000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT1_ACTUAL_FREQ": [ { "value": "48.00000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT2_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT3_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT4_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT5_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT6_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ], + "C_M_MAX": [ { "value": "64.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_M_MIN": [ { "value": "2.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_D_MAX": [ { "value": "93.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_D_MIN": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_O_MAX": [ { "value": "128.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_O_MIN": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_VCO_MIN": [ { "value": "600.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_VCO_MAX": [ { "value": "1440.000", "resolve_type": "generated", "format": "float", "usage": "all" } ] + }, + "project_parameters": { + "ARCHITECTURE": [ { "value": "zynq" } ], + "BASE_BOARD_PART": [ { "value": "xilinx.com:zc706:part0:1.4" } ], + "BOARD_CONNECTIONS": [ { "value": "" } ], + "DEVICE": [ { "value": "xc7z045" } ], + "NEXTGEN_VERSAL": [ { "value": "0" } ], + "PACKAGE": [ { "value": "ffg900" } ], + "PREFHDL": [ { "value": "VERILOG" } ], + "SILICON_REVISION": [ { "value": "" } ], + "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], + "SPEEDGRADE": [ { "value": "-2" } ], + "STATIC_POWER": [ { "value": "" } ], + "TEMPERATURE_GRADE": [ { "value": "" } ] + }, + "runtime_parameters": { + "IPCONTEXT": [ { "value": "IP_Flow" } ], + "IPREVISION": [ { "value": "14" } ], + "MANAGED": [ { "value": "TRUE" } ], + "OUTPUTDIR": [ { "value": "../../../../zc706_cx9261a_demo.gen/sources_1/ip/sys_clk_gen" } ], + "SELECTEDSIMMODEL": [ { "value": "" } ], + "SHAREDDIR": [ { "value": "." } ], + "SWVERSION": [ { "value": "2024.1" } ], + "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ] + } + }, + "boundary": { + "ports": { + "clk_in1": [ { "direction": "in" } ], + "clk_out1": [ { "direction": "out" } ], + "clk_out2": [ { "direction": "out" } ], + "locked": [ { "direction": "out" } ] + }, + "interfaces": { + "clock_CLK_IN1": { + "vlnv": "xilinx.com:signal:clock:1.0", + "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", + "mode": "slave", + "parameters": { + "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ], + "BOARD.ASSOCIATED_PARAM": [ { "value": "CLK_IN1_BOARD_INTERFACE", "usage": "all", "is_static_object": false } ] + }, + "port_maps": { + "CLK_IN1": [ { "physical_name": "clk_in1" } ] + } + }, + "clock_CLK_OUT1": { + "vlnv": "xilinx.com:signal:clock:1.0", + "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", + "mode": "master", + "parameters": { + "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "CLK_OUT1": [ { "physical_name": "clk_out1" } ] + } + }, + "clock_CLK_OUT2": { + "vlnv": "xilinx.com:signal:clock:1.0", + "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", + "mode": "master", + "parameters": { + "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "CLK_OUT2": [ { "physical_name": "clk_out2" } ] + } + } + } + } + } +} \ No newline at end of file diff --git a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/new/system_top.v b/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/new/system_top.v index 6907e5a..053cb8f 100644 --- a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/new/system_top.v +++ b/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/new/system_top.v @@ -197,24 +197,24 @@ system_bd_wrapper system_bd //////////////////////////////////////////////////////////////////////////////// ////////////////////////////// CX9261A Interface /////////////////////////////// //////////////////////////////////////////////////////////////////////////////// -wire data_clk; -wire data_valid; -wire data_clk2; -wire data_valid2; -wire data_clk3; -wire data_valid3; -wire [15:0] rx1_data_i; -wire [15:0] rx1_data_q; -wire [15:0] rx2_data_i; -wire [15:0] rx2_data_q; -wire [15:0] rx3_data_i; -wire [15:0] rx3_data_q; -wire [15:0] tx1_data_i; -wire [15:0] tx1_data_q; -wire [15:0] tx2_data_i; -wire [15:0] tx2_data_q; -wire tx_data_ready; -wire tx_data_ready2; +wire cx9261a_data_clk; +wire cx9261a_data_valid; +wire cx9261a_data_clk2; +wire cx9261a_data_valid2; +wire cx9261a_data_clk3; +wire cx9261a_data_valid3; +wire [15:0] cx9261a_rx1_data_i; +wire [15:0] cx9261a_rx1_data_q; +wire [15:0] cx9261a_rx2_data_i; +wire [15:0] cx9261a_rx2_data_q; +wire [15:0] cx9261a_rx3_data_i; +wire [15:0] cx9261a_rx3_data_q; +wire [15:0] cx9261a_tx1_data_i; +wire [15:0] cx9261a_tx1_data_q; +wire [15:0] cx9261a_tx2_data_i; +wire [15:0] cx9261a_tx2_data_q; +wire cx9261a_tx_data_ready; +wire cx9261a_tx_data_ready2; wire cx9261a_mclk1; wire cx9261a_mclk2; @@ -251,24 +251,24 @@ cx9261a_if cx9261a_if_cmos .tdd_fdd_sel (cx9261a_tdd_fdd_sel ), // PS GPIO控制 tdd:1; fdd:0 保持芯片接口模式配置一致; .r1t1_r2t2_sel (cx9261a_r1t1_r2t2_sel ), // PS GPIO控制 r2t2:1; r1t1:0 保持芯片接口模式配置一致; //基带数据接口 - .data_clk (data_clk ), // f(data_clk) = f(RX1_MCLK_IN_N); - .data_valid (data_valid ), // 任一接口模式下，data_valid可使rx1_i/q_data数据速率和ADC1采样率（无抽取）保持一致 - .data_clk2 (data_clk2 ), // f(data_clk2) = f(RX2_MCLK_IN_P); - .data_valid2 (data_valid2 ), // 任一接口模式下，data_valid2可使rx2_i/q_data数据速率和ADC2采样率（无抽取）保持一致 - .data_clk3 (data_clk3 ), // f(data_clk3) = f(RXFB_MCLK_IN); - .data_valid3 (data_valid3 ), // 任一接口模式下，data_valid3可使rx3_i/q_data数据速率和ADC3采样率（无抽取）保持一致 - .rx1_i_data (rx1_data_i ), // \---------------------------------------------------------------------------------------- - .rx1_q_data (rx1_data_q ), // \eg.：fadc = 64MSPS,fdac = 256MSPS,dac采样率固定是dac采样率的4倍。 - .rx2_i_data (rx2_data_i ), // \发射数字插值倍数保持是接收数字抽取倍数4倍,则基带接收数据速率等于发射数据速率。 - .rx2_q_data (rx2_data_q ), // \在FDD/singleport/r1t1、TDD/singleport/r2t2、FDD/dualport/r2t2三种数据接口模式下， - .rx3_i_data (rx3_data_i ), // \数据随路时钟MCLK fmclk = 2 * fadc，其余接口模式 fmclk = 2 * fadc。 - .rx3_q_data (rx3_data_q ), // \rx1/2/3_i/q_data数据 和 tx1/2_i/q_data数据 对应处于 data_clk/2/3（速率等于MCLK）时钟域 - .tx1_i_data (tx1_data_i ), // \为了保证基带接收数据速率等于发射数据速率,在上述三种三种数据接口模式下 - .tx1_q_data (tx1_data_q ), // \data_valid/2/3实际是data_clk/2的两分频，其余接口模式 tx_data_ready常高; - .tx2_i_data (tx2_data_i ), // \tx_data_ready实际是data_clk/2的两分频，其余接口模式 tx_data_ready常高。 - .tx2_q_data (tx2_data_q ), // \---------------------------------------------------------------------------------------- - .tx_data_ready (tx_data_ready ), // 任一接口模式下，tx_data_ready可使tx1_i/q_data数据速率（4倍插值后）和DAC1采样率保持一致 - .tx_data_ready2 (tx_data_ready2 ), // 任一接口模式下，tx_data_ready2可使tx2_i/q_data数据速率（4倍插值后）和DAC2采样率保持一致 + .data_clk (cx9261a_data_clk ), // f(data_clk) = f(RX1_MCLK_IN_N); + .data_valid (cx9261a_data_valid ), // 任一接口模式下，data_valid可使rx1_i/q_data数据速率和ADC1采样率（无抽取）保持一致 + .data_clk2 (cx9261a_data_clk2 ), // f(data_clk2) = f(RX2_MCLK_IN_P); + .data_valid2 (cx9261a_data_valid2 ), // 任一接口模式下，data_valid2可使rx2_i/q_data数据速率和ADC2采样率（无抽取）保持一致 + .data_clk3 (cx9261a_data_clk3 ), // f(data_clk3) = f(RXFB_MCLK_IN); + .data_valid3 (cx9261a_data_valid3 ), // 任一接口模式下，data_valid3可使rx3_i/q_data数据速率和ADC3采样率（无抽取）保持一致 + .rx1_i_data (cx9261a_rx1_data_i ), // \---------------------------------------------------------------------------------------- + .rx1_q_data (cx9261a_rx1_data_q ), // \eg.：fadc = 64MSPS,fdac = 256MSPS,dac采样率固定是dac采样率的4倍。 + .rx2_i_data (cx9261a_rx2_data_i ), // \发射数字插值倍数保持是接收数字抽取倍数4倍,则基带接收数据速率等于发射数据速率。 + .rx2_q_data (cx9261a_rx2_data_q ), // \在FDD/singleport/r1t1、TDD/singleport/r2t2、FDD/dualport/r2t2三种数据接口模式下， + .rx3_i_data (cx9261a_rx3_data_i ), // \数据随路时钟MCLK fmclk = 2 * fadc，其余接口模式 fmclk = 2 * fadc。 + .rx3_q_data (cx9261a_rx3_data_q ), // \rx1/2/3_i/q_data数据 和 tx1/2_i/q_data数据 对应处于 data_clk/2/3（速率等于MCLK）时钟域 + .tx1_i_data (cx9261a_tx1_data_i ), // \为了保证基带接收数据速率等于发射数据速率,在上述三种三种数据接口模式下 + .tx1_q_data (cx9261a_tx1_data_q ), // \data_valid/2/3实际是data_clk/2的两分频，其余接口模式 tx_data_ready常高; + .tx2_i_data (cx9261a_tx2_data_i ), // \tx_data_ready实际是data_clk/2的两分频，其余接口模式 tx_data_ready常高。 + .tx2_q_data (cx9261a_tx2_data_q ), // \---------------------------------------------------------------------------------------- + .tx_data_ready (cx9261a_tx_data_ready ), // 任一接口模式下，tx_data_ready可使tx1_i/q_data数据速率（4倍插值后）和DAC1采样率保持一致 + .tx_data_ready2 (cx9261a_tx_data_ready2 ), // 任一接口模式下，tx_data_ready2可使tx2_i/q_data数据速率（4倍插值后）和DAC2采样率保持一致 //芯片数据接口 \---------------------------------------------------------------------------------------- .RX1_FRAME_N (cx9261a_rx1_frame ), // \争对客户板上数据时序异常情况，可通过IDELAYE2原语对RX1_MCLK_IN_N进行延时调节，其输出为MCLK1； .RX1_MCLK_IN_N (cx9261a_mclk1 ), // \RX2_MCLK_IN_P延时调节，其输出为MCLK2；RXFB_MCLK_IN延时调节，其输出为MCLK3。 @@ -293,56 +293,110 @@ cx9261a_if cx9261a_if_cmos // <---------------------------------------------------------------------------> // <--------------------- insert transmitter logic below ----------------------> // <---------------------------------------------------------------------------> -wire [ 1:0] waveform_sel_1; -wire sweep_on_1 ; -wire [31:0] freq_set_1 ; -wire [ 1:0] iq_sel_1 ; -wire [ 3:0] bb_rshift_1 ; +wire sys_clk_64M; +wire sys_clk_48M; +wire sys_rstn; -tx_qpsk #( - .BIT_DATA (1024'b0000000100100010000011001001101000010010101000011110101110101101101100000000110000011011001100001010110101110001101111110001000111100111101101101000000010100001011010101000111110111100100101100000100110010001010001101101110000001111000111011111110010000110001011011101000011010101100111100101101100100000100010010011000000101100010100111011001110001011111101010001011101101011000011001101101010000011101001111010011010100100111000001111100111001101111010001010101101111100001001110100011101011111011010010000100001010010101100011100111111101100001000110100111001001111000011011101100011000111101111101001001010000001101000110010111010010110100010001011001101001010010001100001110110111100000101110010101110011101110111001100111010101110111101100101000100110110001000011100101111100101001100110010101010011111100110001101011110011010110100110001001011100001011110101010101111111101000001010100101111000101011110111010100110111001000111000111111111100000001110000111111011100010011111000110011111010110010110010010010000000001), - .BIT_DATA_LEN (1024), +sys_clk_gen u_sys_clk_gen +( + // Clock out ports + .clk_out1 (sys_clk_64M ), // output clk_out1 + .clk_out2 (sys_clk_48M ), // output clk_out2 + // Status and control signals + .locked (sys_rstn ), // output locked + // Clock in ports + .clk_in1 (cx9261a_data_clk ) // input clk_in1 +); + +wire [15:0] tx_data_i, tx_data_q; +wire [1:0] waveform_sel; +wire sweep_on; +wire [31:0] freq_set; +wire [1:0] iq_sel; +wire [3:0] bb_rshift; + +tx_qpsk_v1 #( + .BIT_DATA (1023'b000000100100010000011001001101000010010101000011110101110101101101100000000110000011011001100001010110101110001101111110001000111100111101101101000000010100001011010101000111110111100100101100000100110010001010001101101110000001111000111011111110010000110001011011101000011010101100111100101101100100000100010010011000000101100010100111011001110001011111101010001011101101011000011001101101010000011101001111010011010100100111000001111100111001101111010001010101101111100001001110100011101011111011010010000100001010010101100011100111111101100001000110100111001001111000011011101100011000111101111101001001010000001101000110010111010010110100010001011001101001010010001100001110110111100000101110010101110011101110111001100111010101110111101100101000100110110001000011100101111100101001100110010101010011111100110001101011110011010110100110001001011100001011110101010101111111101000001010100101111000101011110111010100110111001000111000111111111100000001110000111111011100010011111000110011111010110010110010010010000000001), + .BIT_DATA_LEN (1023), .CLK_FREQ (48000000), .DATA_WIDTH (16) ) u_tx1_qpsk ( - .clk (data_clk ), // input clk - .rst (1'b0 ), // input rst - .tx_data_i (tx1_data_i ), // output [11:0] tx_data_i - .tx_data_q (tx1_data_q ), // output [11:0] tx_data_q + .clk (sys_clk_64M ), // input clk + .rst (~sys_rstn ), // input rst + .tx_data_i (tx_data_i ), // output [11:0] tx_data_i + .tx_data_q (tx_data_q ), // output [11:0] tx_data_q // debug ports - .waveform_sel (waveform_sel_1[1:0]), // input [ 1:0] waveform_sel - .sweep_on (sweep_on_1 ), // input sweep_on - .freq_set (freq_set_1 ), // input [31:0] freq_set - .iq_sel (iq_sel_1 ), // input [ 1:0] iq_sel - .bb_rshift (bb_rshift_1 ) // input [ 3:0] bb_rshift + .waveform_sel (waveform_sel ), // input [ 1:0] waveform_sel + .sweep_on (sweep_on ), // input sweep_on + .freq_set (freq_set ), // input [31:0] freq_set + .iq_sel (iq_sel ), // input [ 1:0] iq_sel + .bb_rshift (bb_rshift ) // input [ 3:0] bb_rshift ); -wire [ 1:0] waveform_sel_2; -wire sweep_on_2 ; -wire [31:0] freq_set_2 ; -wire [ 1:0] iq_sel_2 ; -wire [ 3:0] bb_rshift_2 ; - -tx_qpsk #( - .BIT_DATA (1024'b0000000100100010000011001001101000010010101000011110101110101101101100000000110000011011001100001010110101110001101111110001000111100111101101101000000010100001011010101000111110111100100101100000100110010001010001101101110000001111000111011111110010000110001011011101000011010101100111100101101100100000100010010011000000101100010100111011001110001011111101010001011101101011000011001101101010000011101001111010011010100100111000001111100111001101111010001010101101111100001001110100011101011111011010010000100001010010101100011100111111101100001000110100111001001111000011011101100011000111101111101001001010000001101000110010111010010110100010001011001101001010010001100001110110111100000101110010101110011101110111001100111010101110111101100101000100110110001000011100101111100101001100110010101010011111100110001101011110011010110100110001001011100001011110101010101111111101000001010100101111000101011110111010100110111001000111000111111111100000001110000111111011100010011111000110011111010110010110010010010000000001), - .BIT_DATA_LEN (1024), - .CLK_FREQ (48000000), - .DATA_WIDTH (16) -) u_tx2_qpsk +cx9261a_fifo cx9261a_fifo_tx1 ( - .clk (data_clk2 ), // input clk - .rst (1'b0 ), // input rst - .tx_data_i (tx2_data_i ), // output [11:0] tx_data_i - .tx_data_q (tx2_data_q ), // output [11:0] tx_data_q - // debug ports - .waveform_sel (waveform_sel_2[1:0]), // input [ 1:0] waveform_sel - .sweep_on (sweep_on_2 ), // input sweep_on - .freq_set (freq_set_2 ), // input [31:0] freq_set - .iq_sel (iq_sel_2 ), // input [ 1:0] iq_sel - .bb_rshift (bb_rshift_2 ) // input [ 3:0] bb_rshift + .wr_clk (sys_clk_64M ), // input wire wr_clk + .rd_clk (cx9261a_data_clk ), // input wire rd_clk + .din ({tx_data_q,tx_data_i} ), // input wire [15 : 0] din + .wr_en (1'b1 ), // input wire wr_en + .rd_en (cx9261a_tx_data_ready ), // input wire rd_en + .dout ({cx9261a_tx1_data_q,cx9261a_tx1_data_i}), // output wire [15 : 0] dout + .full ( ), // output wire full + .empty ( ) // output wire empty ); +cx9261a_fifo cx9261a_fifo_tx2 +( + .wr_clk (sys_clk_64M ), // input wire wr_clk + .rd_clk (cx9261a_data_clk2 ), // input wire rd_clk + .din ({tx_data_q,tx_data_i} ), // input wire [15 : 0] din + .wr_en (1'b1 ), // input wire wr_en + .rd_en (cx9261a_tx_data_ready2 ), // input wire rd_en + .dout ({cx9261a_tx2_data_q,cx9261a_tx2_data_i}), // output wire [15 : 0] dout + .full ( ), // output wire full + .empty ( ) // output wire empty +); + +wire [15:0] rx1_data_i, rx1_data_q; +wire [15:0] rx2_data_i, rx2_data_q; +wire [15:0] rx3_data_i, rx3_data_q; + +cx9261a_fifo cx9261a_fifo_rx1 +( + .wr_clk (cx9261a_data_clk ), // input wire wr_clk + .rd_clk (sys_clk_64M ) , // input wire rd_clk + .din ({cx9261a_rx1_data_q,cx9261a_rx1_data_i}), // input wire [15 : 0] din + .wr_en (cx9261a_data_valid ), // input wire wr_en + .rd_en (1'b1 ), // input wire rd_en + .dout ({rx1_data_q,rx1_data_i} ), // output wire [15 : 0] dout + .full ( ), // output wire full + .empty ( ) // output wire empty +); + +cx9261a_fifo cx9261a_fifo_rx2 +( + .wr_clk (cx9261a_data_clk2 ), // input wire wr_clk + .rd_clk (sys_clk_64M ) , // input wire rd_clk + .din ({cx9261a_rx2_data_q,cx9261a_rx2_data_i}), // input wire [15 : 0] din + .wr_en (cx9261a_data_valid2 ), // input wire wr_en + .rd_en (1'b1 ), // input wire rd_en + .dout ({rx2_data_q,rx2_data_i} ), // output wire [15 : 0] dout + .full ( ), // output wire full + .empty ( ) // output wire empty +); + +cx9261a_fifo cx9261a_fifo_rx3 +( + .wr_clk (cx9261a_data_clk3 ), // input wire wr_clk + .rd_clk (sys_clk_64M ) , // input wire rd_clk + .din ({cx9261a_rx3_data_q,cx9261a_rx3_data_i}), // input wire [15 : 0] din + .wr_en (cx9261a_data_valid3 ), // input wire wr_en + .rd_en (1'b1 ), // input wire rd_en + .dout ({rx3_data_q,rx3_data_i} ), // output wire [15 : 0] dout + .full ( ), // output wire full + .empty ( ) // output wire empty +); //////////////////////////////////////////////////////////////////////////////// ////////////////////////////// Simple Hop Control ////////////////////////////// @@ -357,79 +411,57 @@ reg hop_trig_d = 'b0; assign hop_flag = hop_flag_buf; -always @(posedge data_clk) begin - hop_trig_d <= hop_trig; - - if (hop_en) begin - hop_cnt <= (hop_cnt == hop_inter) ? 'b0 : hop_cnt + 1'b1; - hop_flag_buf <= (hop_cnt == hop_inter) ? ~hop_flag_buf : hop_flag_buf; +always @(posedge sys_clk_64M or negedge sys_rstn) begin + if (!sys_rstn) begin + hop_cnt <= 'b0; + hop_flag_buf <= 'b0; + hop_trig_d <= 'b0; end else begin - hop_cnt <= 'b0; - hop_flag_buf <= (hop_trig_d & ~hop_trig) ? ~hop_flag_buf : hop_flag_buf; + hop_trig_d <= hop_trig; + + if (hop_en) begin + hop_cnt <= (hop_cnt >= hop_inter - 1) ? 'b0 : hop_cnt + 1'b1; + hop_flag_buf <= (hop_cnt == hop_inter - 1) ? ~hop_flag_buf : hop_flag_buf; + end + else begin + hop_cnt <= 'b0; + hop_flag_buf <= (hop_trig_d & ~hop_trig) ? ~hop_flag_buf : hop_flag_buf; + end end end //////////////////////////////////////////////////////////////////////////////// //////////////////////////////// ILAs and VIOs ///////////////////////////////// //////////////////////////////////////////////////////////////////////////////// -vio_hop u_vio_hop ( - .clk (data_clk ), // input wire clk +vio_hop u_vio_hop +( + .clk (sys_clk_64M), // input wire clk .probe_out0 (hop_inter ), // output wire [31 : 0] probe_out0 .probe_out1 (hop_en ), // output wire [0 : 0] probe_out1 .probe_out2 (hop_trig ) // output wire [0 : 0] probe_out2 ); -ila_trx u_ila_trx1 +ila_trx u_ila_trx ( - .clk (data_clk ), // input wire clk - .probe0 (data_valid ), // input wire [0:0] probe0 - .probe1 (rx1_data_i ), // input wire [11:0] probe1 - .probe2 (rx1_data_q ), // input wire [11:0] probe2 - .probe3 (tx_data_ready ), // input wire [0:0] probe3 - .probe4 (tx1_data_i ), // input wire [11:0] probe4 - .probe5 (tx1_data_q ), // input wire [11:0] probe5 - .probe6 (hop_flag ) // input wire [0:0] probe6 + .clk (sys_clk_64M), // input wire clk + .probe0 (hop_flag ), // input wire [15:0] probe0 + .probe1 (tx_data_i ), // input wire [15:0] probe1 + .probe2 (tx_data_q ), // input wire [15:0] probe2 + .probe3 (rx1_data_i ), // input wire [15:0] probe3 + .probe4 (rx1_data_q ), // input wire [15:0] probe4 + .probe5 (rx2_data_i ), // input wire [15:0] probe5 + .probe6 (rx2_data_q ) // input wire [15:0] probe6 ); -ila_trx u_ila_trx2 +vio_manual_ctrl u_vio_manual_ctrl ( - .clk (data_clk2 ), // input wire clk - .probe0 (data_valid2 ), // input wire [0:0] probe0 - .probe1 (rx2_data_i ), // input wire [11:0] probe1 - .probe2 (rx2_data_q ), // input wire [11:0] probe2 - .probe3 (tx_data_ready2 ), // input wire [0:0] probe3 - .probe4 (tx2_data_i ), // input wire [11:0] probe4 - .probe5 (tx2_data_q ), // input wire [11:0] probe5 - .probe6 (hop_flag ) // input wire [0:0] probe6 -); - -ila_trx_fb u_ila_rx_fb -( - .clk (data_clk3 ), // input wire clk - .probe0 (data_valid3), // input wire [0:0] probe0 - .probe1 (rx3_data_i ), // input wire [11:0] probe1 - .probe2 (rx3_data_q ) // input wire [11:0] probe2 -); - -vio_manual_ctrl u_vio_manual_ctrl_1 -( - .clk (data_clk ), // input wire clk - .probe_out0 (waveform_sel_1 ), // output wire [1 : 0] probe_out0 - .probe_out1 (sweep_on_1 ), // output wire [0 : 0] probe_out1 - .probe_out2 (freq_set_1 ), // output wire [31 : 0] probe_out2 - .probe_out3 (iq_sel_1 ), // output wire [1 : 0] probe_out3 - .probe_out4 (bb_rshift_1 ) // output wire [3 : 0] probe_out4 -); - -vio_manual_ctrl u_vio_manual_ctrl_2 -( - .clk (data_clk2 ), // input wire clk - .probe_out0 (waveform_sel_2 ), // output wire [1 : 0] probe_out0 - .probe_out1 (sweep_on_2 ), // output wire [0 : 0] probe_out1 - .probe_out2 (freq_set_2 ), // output wire [31 : 0] probe_out2 - .probe_out3 (iq_sel_2 ), // output wire [1 : 0] probe_out3 - .probe_out4 (bb_rshift_2 ) // output wire [3 : 0] probe_out4 + .clk (sys_clk_64M ), // input wire clk + .probe_out0 (waveform_sel ), // output wire [1 : 0] probe_out0 + .probe_out1 (sweep_on ), // output wire [0 : 0] probe_out1 + .probe_out2 (freq_set ), // output wire [31 : 0] probe_out2 + .probe_out3 (iq_sel ), // output wire [1 : 0] probe_out3 + .probe_out4 (bb_rshift ) // output wire [3 : 0] probe_out4 ); endmodule diff --git a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/new/tx_qpsk_v1.v b/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/new/tx_qpsk_v1.v new file mode 100644 index 0000000..bdd3afd --- /dev/null +++ b/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/new/tx_qpsk_v1.v @@ -0,0 +1,523 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// _ _ ____ +// | | ___ ___| |__ / ___| __ _ ___ +// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \ +// | |_| | (_) \__ \ | | | | |_| | (_| | (_) | +// \___/ \___/|___/_| |_| \____|\__,_|\___/ +// +// Create Date: 2022/03/23 20:17:56 +// Last Modified Date: 2023/03/10 15:41 +// Design Name: +// Module Name: tx_qpsk +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// 20230228-1541 - 修改不扫频、无基带频偏时 [baseband_i/q] 的数据输出，原来从 +// 乘法器引出，会导致频率为 0 时输出数据错误，现在直接从基带数据引出。 +// 20230310-1542 - 增加输入参数，发送数据更改为直接由参数输入，发送方波改为 8 +// 倍过采样，发送双音信号中 1MHz 信号的频率控制字可以根据参数中的时钟频率计 +// 算得出。 +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module tx_qpsk_v1 +#( + parameter DATA_WIDTH = 12, // need to be <= 16 + parameter BIT_DATA = 128'b00000011000010100011110010001011001110101001111101000011100010010011011010110111101100011010010111011100110010101011111110000001, // inverse pseudorandom bit sequence, [0,flip(PRSB7)] + parameter BIT_DATA_LEN = 128, + parameter SQUARE_INTERP = 1, + parameter CLK_FREQ = 245760000 // in Hertz +) +( + input clk , + input rst , + output [DATA_WIDTH-1:0] tx_data_i , + output [DATA_WIDTH-1:0] tx_data_q , + // debug ports + input [ 1:0] waveform_sel , + input sweep_on , + input [31:0] freq_set , + input [ 1:0] iq_sel , + input [ 3:0] bb_rshift +); + +localparam RCOS_INTERP = 1; +localparam INTERP = (RCOS_INTERP > SQUARE_INTERP) ? RCOS_INTERP : SQUARE_INTERP; +localparam FREQ_WORD_1M = 64'd2**64'd32*64'd1000000/CLK_FREQ; + +//////////////////////////////////////////////////////////////////////////////// +///////////////////////////////// Data Counter ///////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +// symbol & interpolation counter +reg [$clog2(INTERP*BIT_DATA_LEN)-1 : 0] cnt = 'b0; + +always @(posedge clk) begin + if (rst) begin + cnt <= 'b0; + end + else begin + cnt <= (cnt == INTERP*BIT_DATA_LEN - 1) ? 'b0 : cnt + 16'b1; + end +end + +//////////////////////////////////////////////////////////////////////////////// +////////////////////// Root-Rasied Cosine Shaping Filter /////////////////////// +//////////////////////////////////////////////////////////////////////////////// +// address +reg [$clog2(BIT_DATA_LEN)-1 : 0] hrc_data_addr_i = 'b0; +reg [$clog2(BIT_DATA_LEN)-1 : 0] hrc_data_addr_q = 'b1; + +always @(posedge clk) begin + if (rst) begin + hrc_data_addr_i <= 'b0; + hrc_data_addr_q <= 'b1; + end + else begin + hrc_data_addr_i <= {cnt[$clog2(RCOS_INTERP) +: ($clog2(BIT_DATA_LEN)-1)],1'b0}; + hrc_data_addr_q <= {cnt[$clog2(RCOS_INTERP) +: ($clog2(BIT_DATA_LEN)-1)],1'b1}; + end +end + +// bit data +reg hrc_data_i = 'b0; +reg hrc_data_q = 'b0; + +always @(posedge clk) begin + if (rst) begin + hrc_data_i <= 'b0; + hrc_data_q <= 'b0; + end + else begin + hrc_data_i <= BIT_DATA[hrc_data_addr_i]; + hrc_data_q <= BIT_DATA[hrc_data_addr_q]; + end +end + +// polarization +wire [ 7:0] hrc_data_polar_i; +wire [ 7:0] hrc_data_polar_q; + +assign hrc_data_polar_i = {{7{hrc_data_i}},1'b1}; +assign hrc_data_polar_q = {{7{hrc_data_q}},1'b1}; + +/* // root raised cosine shaping-filter +wire [23:0] hrc_wave_i; +wire [23:0] hrc_wave_q; + +hrc_64_12_025 u_hrc_i ( + .aclk (clk ), // input wire aclk + .s_axis_data_tvalid (~rst ), // input wire s_axis_data_tvalid + .s_axis_data_tready ( ), // output wire s_axis_data_tready + .s_axis_data_tdata (hrc_data_polar_i ), // input wire [7 : 0] s_axis_data_tdata + .m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid + .m_axis_data_tdata (hrc_wave_i ) // output wire [23 : 0] m_axis_data_tdata +); + +hrc_64_12_025 u_hrc_q ( + .aclk (clk ), // input wire aclk + .s_axis_data_tvalid (~rst ), // input wire s_axis_data_tvalid + .s_axis_data_tready ( ), // output wire s_axis_data_tready + .s_axis_data_tdata (hrc_data_polar_q ), // input wire [7 : 0] s_axis_data_tdata + .m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid + .m_axis_data_tdata (hrc_wave_q ) // output wire [23 : 0] m_axis_data_tdata +); */ + +wire [23:0] hrc_wave_i_48; +wire [23:0] hrc_wave_q_48; +hrc_4_12_03 i_hrc_4_12_03 ( + .aclk (clk ), // input wire aclk + .s_axis_data_tvalid (~rst ), // input wire s_axis_data_tvalid + .s_axis_data_tready ( ), // output wire s_axis_data_tready + .s_axis_data_tdata (hrc_data_polar_i ), // input wire [7 : 0] s_axis_data_tdata + .m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid + .m_axis_data_tdata (hrc_wave_i_48 ) // output wire [23 : 0] m_axis_data_tdata +); +hrc_4_12_03 q_hrc_4_12_03 ( + .aclk (clk ), // input wire aclk + .s_axis_data_tvalid (~rst ), // input wire s_axis_data_tvalid + .s_axis_data_tready ( ), // output wire s_axis_data_tready + .s_axis_data_tdata (hrc_data_polar_q ), // input wire [7 : 0] s_axis_data_tdata + .m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid + .m_axis_data_tdata (hrc_wave_q_48 ) // output wire [23 : 0] m_axis_data_tdata +); + +wire [23:0] hrc_wave_i_12; +wire [23:0] hrc_wave_q_12; +hrc_16_12_03 i_hrc_16_12_03 ( + .aclk (clk ), // input wire aclk + .s_axis_data_tvalid (~rst ), // input wire s_axis_data_tvalid + .s_axis_data_tready ( ), // output wire s_axis_data_tready + .s_axis_data_tdata (hrc_data_polar_i ), // input wire [7 : 0] s_axis_data_tdata + .m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid + .m_axis_data_tdata (hrc_wave_i_12 ) // output wire [23 : 0] m_axis_data_tdata +); +hrc_16_12_03 q_hrc_16_12_03 ( + .aclk (clk ), // input wire aclk + .s_axis_data_tvalid (~rst ), // input wire s_axis_data_tvalid + .s_axis_data_tready ( ), // output wire s_axis_data_tready + .s_axis_data_tdata (hrc_data_polar_q ), // input wire [7 : 0] s_axis_data_tdata + .m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid + .m_axis_data_tdata (hrc_wave_q_12 ) // output wire [23 : 0] m_axis_data_tdata +); + +wire [23:0] hrc_wave_i_1p5; +wire [23:0] hrc_wave_q_1p5; +hrc_128_12_03 i_hrc_128_12_03 ( + .aclk (clk ), // input wire aclk + .s_axis_data_tvalid (~rst ), // input wire s_axis_data_tvalid + .s_axis_data_tready ( ), // output wire s_axis_data_tready + .s_axis_data_tdata (hrc_data_polar_i ), // input wire [7 : 0] s_axis_data_tdata + .m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid + .m_axis_data_tdata (hrc_wave_i_1p5 ) // output wire [23 : 0] m_axis_data_tdata +); +hrc_128_12_03 q_hrc_128_12_03 ( + .aclk (clk ), // input wire aclk + .s_axis_data_tvalid (~rst ), // input wire s_axis_data_tvalid + .s_axis_data_tready ( ), // output wire s_axis_data_tready + .s_axis_data_tdata (hrc_data_polar_q ), // input wire [7 : 0] s_axis_data_tdata + .m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid + .m_axis_data_tdata (hrc_wave_q_1p5 ) // output wire [23 : 0] m_axis_data_tdata +); + + +//////////////////////////////////////////////////////////////////////////////// +///////////////////// Waveform Selection & Hopping Control ///////////////////// +//////////////////////////////////////////////////////////////////////////////// +// baseband signal select +reg [17:0] baseband_sel_i = 'b0; +reg [17:0] baseband_sel_q = 'b0; + +always @(posedge clk) begin + if (rst) begin + baseband_sel_i <= 'b0; + baseband_sel_q <= 'b0; + end + else begin + case (waveform_sel[1:0]) + 2'd0: begin + baseband_sel_i <= {hrc_wave_i_48[16:0],1'b0}; + baseband_sel_q <= {hrc_wave_q_48[16:0],1'b0}; + end + 2'd1: begin + baseband_sel_i <= {hrc_wave_i_12[16:0],1'b0}; + baseband_sel_q <= {hrc_wave_q_12[16:0],1'b0}; + end + 2'd2: begin + baseband_sel_i <= {hrc_wave_i_1p5[16:0],1'b0}; + baseband_sel_q <= {hrc_wave_q_1p5[16:0],1'b0}; + end + 2'd3: begin + baseband_sel_i <= 18'b01_1111_1111_1111_1111; + baseband_sel_q <= 18'b0; + end + default: begin + baseband_sel_i <= {hrc_wave_i_48[16:0],1'b0}; + baseband_sel_q <= {hrc_wave_q_48[16:0],1'b0}; + end + endcase + end +end + +// hopping control, 3750hop/s +reg [23:0] sweep_rom_addr = 'b0; +wire [31:0] freq_sweep; + +always @(posedge clk) begin + if (rst) begin + sweep_rom_addr <= 'b0; + end + else if (sweep_on) begin + sweep_rom_addr <= sweep_rom_addr + 24'b1; + end + else begin + sweep_rom_addr <= 'b0; + end +end + +hop_rom u_sweep_rom +( + .clka (clk ), // input wire clka + .addra (sweep_rom_addr[23:16] ), // input wire [7 : 0] addra + .douta (freq_sweep ) // output wire [31 : 0] douta +); + +// choose the actual frequency word +reg [31:0] freq_word = 'b0; + +always @(posedge clk) begin + if (rst) begin + freq_word <= 'b0; + end + else if (sweep_on) begin + // frequency sweep + freq_word <= freq_sweep; + end + else begin + // normal operation + freq_word <= freq_set; + end +end + +// baseband frequency shift carrier generation +wire [ 7:0] cos_dds; +wire [ 7:0] sin_dds; +reg [ 7:0] cos = 'b0; +reg [ 7:0] sin = 'b0; + +dds_32b_8b u_dds_bb_shift ( + .aclk (clk ), // input wire aclk + .s_axis_config_tvalid (~rst ), // input wire s_axis_config_tvalid + .s_axis_config_tdata (freq_word ), // input wire [31 : 0] s_axis_config_tdata + .m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid + .m_axis_data_tdata ({sin_dds,cos_dds}) // output wire [31 : 0] m_axis_data_tdata +); + +always @(posedge clk) begin + if (rst) begin + cos <= 'b0; + sin <= 'b0; + end + else if (freq_word == 'b0) begin + // to make sure the carriers stay at the right position when freq = 0 + cos <= 8'b0111_1111; + sin <= 8'b0111_1111; + end + else begin + cos <= cos_dds; + sin <= sin_dds; + end +end + +// baseband frequency shift modulation +wire [47:0] mod_cmpy_a; +wire [15:0] mod_cmpy_b; +wire [63:0] mod_cmpy_out; + +wire [26:0] baseband_mult_i; +wire [26:0] baseband_mult_q; + +assign mod_cmpy_a = {6'b0,baseband_sel_q,6'b0,baseband_sel_i}; +assign mod_cmpy_b = {-sin,cos}; + +assign baseband_mult_i = mod_cmpy_out[58:32]; +assign baseband_mult_q = mod_cmpy_out[26: 0]; + +cmpy_18x8 u_cmpy_18x8 +( + .aclk (clk ), // input wire aclk + .s_axis_a_tvalid (1'b1 ), // input wire s_axis_a_tvalid + .s_axis_a_tdata (mod_cmpy_a ), // input wire [47 : 0] s_axis_a_tdata + .s_axis_b_tvalid (1'b1 ), // input wire s_axis_b_tvalid + .s_axis_b_tdata (mod_cmpy_b ), // input wire [15 : 0] s_axis_b_tdata + .m_axis_dout_tvalid ( ), // output wire m_axis_dout_tvalid + .m_axis_dout_tdata (mod_cmpy_out ) // output wire [63 : 0] m_axis_dout_tdata +); + +// truncate to 16-bit +reg signed [15:0] baseband_i = 'b0; +reg signed [15:0] baseband_q = 'b0; + +always @(posedge clk) begin + if (rst) begin + baseband_i <= 'b0; + baseband_q <= 'b0; + end + else begin + case (waveform_sel[1:0]) + 2'd0: begin + // scale rasied-cosine-shaped bpsk signal by 1.125 or 1.625 + baseband_i <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_i[17 -: 16] : baseband_mult_i[25:10]; + baseband_q <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_q[17 -: 16] : baseband_mult_q[25:10]; + end + 2'd1: begin + baseband_i <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_i[17 -: 16] : baseband_mult_i[25:10]; + baseband_q <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_q[17 -: 16] : baseband_mult_q[25:10]; + end + 2'd2: begin + baseband_i <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_i[17 -: 16] : baseband_mult_i[25:10]; + baseband_q <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_q[17 -: 16] : baseband_mult_q[25:10]; + end + 2'd3: begin + baseband_i <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_i[17 -: 16] : baseband_mult_i[24:9]; + baseband_q <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_q[17 -: 16] : baseband_mult_q[24:9]; + end + default: begin + // scale rasied-cosine-shaped bpsk signal by 1.125 + baseband_i <= baseband_mult_i[25:10]; + baseband_q <= baseband_mult_q[25:10]; + end + endcase + end +end + +// iq selection & baseband right shift +reg signed [15:0] baseband_data_i = 'b0; +reg signed [15:0] baseband_data_q = 'b0; + +always @(posedge clk) begin + if (rst) begin + baseband_data_i <= 'b0; + baseband_data_q <= 'b0; + end + else begin + // inphase selection + if (iq_sel[1]) begin + baseband_data_i <= baseband_i >>> bb_rshift; + end + else begin + baseband_data_i <= 'b0; + end + // quadrature selection + if (iq_sel[0]) begin + baseband_data_q <= baseband_q >>> bb_rshift; + end + else begin + baseband_data_q <= 'b0; + end + end +end + +// output data to ports +assign tx_data_i = baseband_data_i[15 -: DATA_WIDTH]; +assign tx_data_q = baseband_data_q[15 -: DATA_WIDTH]; + +endmodule + + +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2020/12/08 12:43:46 +// Design Name: +// Module Name: tb_tx_qpsk +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +// module tb_tx_qpsk; + +// reg clk = 1'b0 ; +// reg rst = 1'b1 ; +// reg tx_on = 1'b1 ; +// reg [31:0] freq_set ; +// reg [ 1:0] waveform_sel = 2'b00; +// reg [ 1:0] iq_sel = 2'b11 ; +// wire [11:0] tx_data_i ; +// wire [11:0] tx_data_q ; +// reg [ 3:0] bb_rshift = 5'b0 ; + +// tx_qpsk u_tx_qpsk +// ( +// .clk (clk ), +// .rst (rst ), +// .tx_data_i (tx_data_i ), +// .tx_data_q (tx_data_q ), +// .waveform_sel (waveform_sel ), +// .sweep_on (1'b0 ), +// // .freq_set (32'd447392426 ), +// .freq_set (32'd0 ), +// .iq_sel (iq_sel ), +// .bb_rshift (bb_rshift ) +// ); + +// initial begin +// #102 +// rst = 1'b0; +// // freq_set = 32'd873813333; +// // waveform_sel = 2'b00; +// // bb_rshift = 5'd0; +// // #5000 +// // bb_rshift = 5'd1; +// // #5000 +// // bb_rshift = 5'd2; +// // #5000 +// // bb_rshift = 5'd3; +// // #5000 +// // bb_rshift = 5'd4; +// // #5000 +// // bb_rshift = 5'd5; +// // #5000 +// // bb_rshift = 5'd6; +// // #5000 +// // bb_rshift = 5'd7; +// // #5000 +// // bb_rshift = 5'd8; +// // #5000 +// // bb_rshift = 5'd9; +// // #5000 +// // bb_rshift = 5'd14; +// // #5000 +// // bb_rshift = 5'd15; +// // #5000 +// // bb_rshift = 5'd16; +// // freq_set = 32'd0; +// // func_sel = 3'b010; +// // #7777 +// // freq_set = 32'd536870912; +// // func_sel = 3'b100; +// // #7777 +// // freq_set = 32'd0; +// // func_sel = 3'b100; +// // #7777 +// // freq_set = 32'd536870912; +// // func_sel = 3'b010; +// // #7777 +// // freq_set = 32'd0; +// // func_sel = 3'b010; +// // freq_set = 32'd536870912; +// // iq_sel = 2'b00; +// // #7777 +// // freq_set = 32'd536870912; +// // iq_sel = 2'b01; +// // #7777 +// // freq_set = 32'd536870912; +// // iq_sel = 2'b10; +// // #7777 +// // freq_set = 32'd536870912; +// // iq_sel = 2'b11; +// end + +// always #5 clk = ~clk; + +// // integer i; +// // integer w_file; + +// // initial begin +// // w_file = $fopen("D:\\qpsk_josh.txt","w"); +// // for (i = 0; i <= 35000; i = i + 1) begin +// // wait(clk); +// // #10; +// // $fdisplay(w_file,"%d %d",$signed(tx_data_i), +// // $signed(tx_data_q)); +// // if (i == 35000) begin +// // $fclose(w_file); +// // $stop; +// // end +// // end +// // end + +// endmodule + diff --git a/zc706_cx9261a_demo/zc706_cx9261a_demo.xpr b/zc706_cx9261a_demo/zc706_cx9261a_demo.xpr index 679896c..d62f3f2 100644 --- a/zc706_cx9261a_demo/zc706_cx9261a_demo.xpr +++ b/zc706_cx9261a_demo/zc706_cx9261a_demo.xpr @@ -67,13 +67,13 @@