fix:upgrade ips,修改ip repo中ip的makefile,原来的makefile会导致windows上编译失败
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+26
-14
@@ -5,22 +5,34 @@ COMPILER_FLAGS=
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EXTRA_COMPILER_FLAGS=
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LIB=libxil.a
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RELEASEDIR=../../../lib
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INCLUDEDIR=../../../include
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INCLUDES=-I./. -I${INCLUDEDIR}
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CC_FLAGS = $(COMPILER_FLAGS)
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ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
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INCLUDEFILES=*.h
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LIBSOURCES=*.c
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OUTS = *.o
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RELEASEDIR=../../../lib/
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INCLUDEDIR=../../../include/
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INCLUDES=-I./. -I$(INCLUDEDIR)
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libs:
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echo "Compiling Axis_adc_data_packer..."
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$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
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$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
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make clean
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SRCFILES:=$(wildcard *.c)
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include:
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${CP} $(INCLUDEFILES) $(INCLUDEDIR)
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OBJECTS = $(addprefix $(RELEASEDIR), $(addsuffix .o, $(basename $(wildcard *.c))))
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libs: $(OBJECTS)
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DEPFILES := $(SRCFILES:%.c=$(RELEASEDIR)%.d)
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include $(wildcard $(DEPFILES))
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include $(wildcard ../../../../dep.mk)
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$(RELEASEDIR)%.o: %.c
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${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $(DEPENDENCY_FLAGS) $< -o $@
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.PHONY: include
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include: $(addprefix $(INCLUDEDIR),$(wildcard *.h))
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$(INCLUDEDIR)%.h: %.h
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$(CP) $< $@
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clean:
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rm -rf ${OUTS}
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rm -rf ${OBJECTS}
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rm -rf $(DEPFILES)
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+2
-2
@@ -1,8 +1,8 @@
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//Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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//Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
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//--------------------------------------------------------------------------------
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//Tool Version: Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
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//Date : Thu Oct 31 11:29:13 2024
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//Tool Version: Vivado v.2024.1.2 (lin64) Build 5164865 Thu Sep 5 14:36:28 MDT 2024
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//Date : Sun Nov 3 15:49:22 2024
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//Host : gatsby-dev running 64-bit Red Hat Enterprise Linux release 8.10 (Ootpa)
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//Command : generate_target system_top_wrapper.bd
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//Design : system_top_wrapper
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+15
-15
@@ -1,5 +1,5 @@
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
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<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Thu Oct 31 11:29:40 2024" VIVADOVERSION="2024.1">
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<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Sun Nov 3 15:50:04 2024" VIVADOVERSION="2024.1.2">
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<SYSTEMINFO ARCH="zynq" BOARD="xilinx.com:zc706:part0:1.4" DEVICE="7z045" NAME="system_top" PACKAGE="ffg900" SPEEDGRADE="-2"/>
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@@ -81,7 +81,7 @@
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<CONNECTION INSTANCE="processing_system7_0" PORT="DDR_RAS_n"/>
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</CONNECTIONS>
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</PORT>
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<PORT DIR="IO" NAME="DDR_reset_n" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="processing_system7_0_DDR_DRSTB">
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<PORT DIR="IO" NAME="DDR_reset_n" SIGIS="rst" SIGNAME="processing_system7_0_DDR_DRSTB">
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<CONNECTIONS>
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<CONNECTION INSTANCE="processing_system7_0" PORT="DDR_DRSTB"/>
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</CONNECTIONS>
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@@ -473,7 +473,7 @@
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<CONNECTION INSTANCE="mig_7series_0" PORT="ddr3_ras_n"/>
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</CONNECTIONS>
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</PORT>
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<PORT DIR="O" NAME="ddr3_sdram_reset_n" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="mig_7series_0_ddr3_reset_n">
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<PORT DIR="O" NAME="ddr3_sdram_reset_n" SIGIS="rst" SIGNAME="mig_7series_0_ddr3_reset_n">
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<CONNECTIONS>
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<CONNECTION INSTANCE="mig_7series_0" PORT="ddr3_reset_n"/>
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</CONNECTIONS>
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@@ -3283,7 +3283,7 @@
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</BUSINTERFACE>
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</BUSINTERFACES>
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</MODULE>
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<MODULE COREREVISION="32" FULLNAME="/axi_dma_0" HWVERSION="7.1" INSTANCE="axi_dma_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axi_dma" VLNV="xilinx.com:ip:axi_dma:7.1">
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<MODULE COREREVISION="33" FULLNAME="/axi_dma_0" HWVERSION="7.1" INSTANCE="axi_dma_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axi_dma" VLNV="xilinx.com:ip:axi_dma:7.1">
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<DOCUMENTS>
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<DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_dma;v=v7_1;d=pg021_axi_dma.pdf"/>
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</DOCUMENTS>
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@@ -4497,7 +4497,7 @@
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<PERIPHERAL INSTANCE="mig_7series_0"/>
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</PERIPHERALS>
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</MODULE>
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<MODULE COREREVISION="32" FULLNAME="/axi_dma_1" HWVERSION="7.1" INSTANCE="axi_dma_1" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axi_dma" VLNV="xilinx.com:ip:axi_dma:7.1">
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<MODULE COREREVISION="33" FULLNAME="/axi_dma_1" HWVERSION="7.1" INSTANCE="axi_dma_1" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axi_dma" VLNV="xilinx.com:ip:axi_dma:7.1">
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<DOCUMENTS>
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<DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_dma;v=v7_1;d=pg021_axi_dma.pdf"/>
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</DOCUMENTS>
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@@ -5711,7 +5711,7 @@
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<PERIPHERAL INSTANCE="mig_7series_0"/>
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</PERIPHERALS>
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</MODULE>
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<MODULE COREREVISION="32" FULLNAME="/axi_dma_2" HWVERSION="7.1" INSTANCE="axi_dma_2" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axi_dma" VLNV="xilinx.com:ip:axi_dma:7.1">
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<MODULE COREREVISION="33" FULLNAME="/axi_dma_2" HWVERSION="7.1" INSTANCE="axi_dma_2" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axi_dma" VLNV="xilinx.com:ip:axi_dma:7.1">
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<DOCUMENTS>
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<DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_dma;v=v7_1;d=pg021_axi_dma.pdf"/>
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</DOCUMENTS>
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@@ -6925,7 +6925,7 @@
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<PERIPHERAL INSTANCE="mig_7series_0"/>
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</PERIPHERALS>
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</MODULE>
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<MODULE COREREVISION="33" FULLNAME="/axi_gpio_0" HWVERSION="2.0" INSTANCE="axi_gpio_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axi_gpio" VLNV="xilinx.com:ip:axi_gpio:2.0">
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<MODULE COREREVISION="34" FULLNAME="/axi_gpio_0" HWVERSION="2.0" INSTANCE="axi_gpio_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axi_gpio" VLNV="xilinx.com:ip:axi_gpio:2.0">
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<DOCUMENTS>
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<DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_gpio;v=v2_0;d=pg144-axi-gpio.pdf"/>
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</DOCUMENTS>
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@@ -7298,7 +7298,7 @@
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</BUSINTERFACE>
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</BUSINTERFACES>
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</MODULE>
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<MODULE BD="system_top_axi_smc_0" BDTYPE="SBD" COREREVISION="23" DRIVERMODE="CORE" FULLNAME="/axi_smc" HWVERSION="1.0" INSTANCE="axi_smc" IPTYPE="BUS" IS_ENABLE="1" MODCLASS="BUS" MODTYPE="smartconnect" SIM_BD="system_top_axi_smc_0" VLNV="xilinx.com:ip:smartconnect:1.0">
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<MODULE BD="system_top_axi_smc_0" BDTYPE="SBD" COREREVISION="24" DRIVERMODE="CORE" FULLNAME="/axi_smc" HWVERSION="1.0" INSTANCE="axi_smc" IPTYPE="BUS" IS_ENABLE="1" MODCLASS="BUS" MODTYPE="smartconnect" SIM_BD="system_top_axi_smc_0" VLNV="xilinx.com:ip:smartconnect:1.0">
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<DOCUMENTS>
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<DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=smartconnect;v=v1_0;d=pg247-smartconnect.pdf"/>
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</DOCUMENTS>
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@@ -9433,7 +9433,7 @@
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</BUSINTERFACE>
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</BUSINTERFACES>
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</MODULE>
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<MODULE BD="system_top_axi_smc1_0" BDTYPE="SBD" COREREVISION="23" DRIVERMODE="CORE" FULLNAME="/axi_smc1" HWVERSION="1.0" INSTANCE="axi_smc1" IPTYPE="BUS" IS_ENABLE="1" MODCLASS="BUS" MODTYPE="smartconnect" SIM_BD="system_top_axi_smc1_0" VLNV="xilinx.com:ip:smartconnect:1.0">
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<MODULE BD="system_top_axi_smc1_0" BDTYPE="SBD" COREREVISION="24" DRIVERMODE="CORE" FULLNAME="/axi_smc1" HWVERSION="1.0" INSTANCE="axi_smc1" IPTYPE="BUS" IS_ENABLE="1" MODCLASS="BUS" MODTYPE="smartconnect" SIM_BD="system_top_axi_smc1_0" VLNV="xilinx.com:ip:smartconnect:1.0">
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<DOCUMENTS>
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<DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=smartconnect;v=v1_0;d=pg247-smartconnect.pdf"/>
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</DOCUMENTS>
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@@ -13900,14 +13900,14 @@
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<CONNECTIONS>
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<CONNECTION INSTANCE="External_Ports" PORT="ui_clk"/>
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<CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP1_ACLK"/>
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<CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_aclk"/>
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<CONNECTION INSTANCE="axi_dma_1" PORT="m_axi_s2mm_aclk"/>
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<CONNECTION INSTANCE="axi_dma_2" PORT="m_axi_s2mm_aclk"/>
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<CONNECTION INSTANCE="axi_smc1" PORT="aclk"/>
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<CONNECTION INSTANCE="fifo_generator_0" PORT="m_aclk"/>
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<CONNECTION INSTANCE="fifo_generator_1" PORT="m_aclk"/>
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<CONNECTION INSTANCE="fifo_generator_2" PORT="m_aclk"/>
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<CONNECTION INSTANCE="proc_sys_reset_0" PORT="slowest_sync_clk"/>
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<CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_aclk"/>
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<CONNECTION INSTANCE="axi_dma_1" PORT="m_axi_s2mm_aclk"/>
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<CONNECTION INSTANCE="axi_dma_2" PORT="m_axi_s2mm_aclk"/>
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<CONNECTION INSTANCE="axi_smc1" PORT="aclk"/>
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</CONNECTIONS>
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</PORT>
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<PORT DIR="O" NAME="ui_clk_sync_rst" POLARITY="ACTIVE_HIGH" SIGIS="rst"/>
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@@ -15108,12 +15108,12 @@
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<CONNECTION INSTANCE="axi4_lite_spi_1" PORT="s_axi_aclk"/>
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<CONNECTION INSTANCE="axi_bram_ctrl_0" PORT="s_axi_aclk"/>
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<CONNECTION INSTANCE="axi_bram_ctrl_1" PORT="s_axi_aclk"/>
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<CONNECTION INSTANCE="rst_ps7_0_200M" PORT="slowest_sync_clk"/>
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<CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_aclk"/>
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<CONNECTION INSTANCE="axi_dma_1" PORT="s_axi_lite_aclk"/>
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<CONNECTION INSTANCE="axi_dma_2" PORT="s_axi_lite_aclk"/>
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<CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_aclk"/>
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<CONNECTION INSTANCE="axi_smc" PORT="aclk"/>
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<CONNECTION INSTANCE="rst_ps7_0_200M" PORT="slowest_sync_clk"/>
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<CONNECTION INSTANCE="system_ila_0" PORT="clk"/>
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</CONNECTIONS>
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</PORT>
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@@ -15941,7 +15941,7 @@
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</PORTS>
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<BUSINTERFACES/>
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</MODULE>
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<MODULE BD="system_top_system_ila_0_2" BDTYPE="SBD" COREREVISION="17" DRIVERMODE="MIXED" FULLNAME="/system_ila_0" HWVERSION="1.1" INSTANCE="system_ila_0" IPTYPE="MONITOR" IS_ENABLE="1" MODCLASS="MONITOR" MODTYPE="system_ila" SIM_BD="system_top_system_ila_0_2" VLNV="xilinx.com:ip:system_ila:1.1">
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<MODULE BD="system_top_system_ila_0_2" BDTYPE="SBD" COREREVISION="18" DRIVERMODE="MIXED" FULLNAME="/system_ila_0" HWVERSION="1.1" INSTANCE="system_ila_0" IPTYPE="MONITOR" IS_ENABLE="1" MODCLASS="MONITOR" MODTYPE="system_ila" SIM_BD="system_top_system_ila_0_2" VLNV="xilinx.com:ip:system_ila:1.1">
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<DOCUMENTS>
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<DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=system_ila;v=v1_1;d=pg261-system-ila.pdf"/>
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</DOCUMENTS>
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+26
-14
@@ -5,22 +5,34 @@ COMPILER_FLAGS=
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EXTRA_COMPILER_FLAGS=
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LIB=libxil.a
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RELEASEDIR=../../../lib
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INCLUDEDIR=../../../include
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INCLUDES=-I./. -I${INCLUDEDIR}
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CC_FLAGS = $(COMPILER_FLAGS)
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ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
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INCLUDEFILES=*.h
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LIBSOURCES=*.c
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OUTS = *.o
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RELEASEDIR=../../../lib/
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INCLUDEDIR=../../../include/
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INCLUDES=-I./. -I$(INCLUDEDIR)
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libs:
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echo "Compiling Axis_adc_data_packer..."
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$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
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$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
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make clean
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SRCFILES:=$(wildcard *.c)
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include:
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${CP} $(INCLUDEFILES) $(INCLUDEDIR)
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OBJECTS = $(addprefix $(RELEASEDIR), $(addsuffix .o, $(basename $(wildcard *.c))))
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libs: $(OBJECTS)
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DEPFILES := $(SRCFILES:%.c=$(RELEASEDIR)%.d)
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include $(wildcard $(DEPFILES))
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include $(wildcard ../../../../dep.mk)
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$(RELEASEDIR)%.o: %.c
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${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $(DEPENDENCY_FLAGS) $< -o $@
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.PHONY: include
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include: $(addprefix $(INCLUDEDIR),$(wildcard *.h))
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$(INCLUDEDIR)%.h: %.h
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$(CP) $< $@
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clean:
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rm -rf ${OUTS}
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rm -rf ${OBJECTS}
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rm -rf $(DEPFILES)
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+197
@@ -0,0 +1,197 @@
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// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
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||||
//
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||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
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||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
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// IP VLNV: labnet.com:user:Axis_adc_data_packer:1.0
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// IP Revision: 9
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`timescale 1ns/1ps
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(* DowngradeIPIdentifiedWarnings = "yes" *)
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module system_top_Axis_adc_data_packer_0_0 (
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aclk,
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aresetn,
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axis_tvalid,
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axis_tlast,
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axis_ready,
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axis_tdata,
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m_axis_tvalid,
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m_axis_tlast,
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m_axis_ready,
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m_axis_tdata,
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s00_axi_awaddr,
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s00_axi_awprot,
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s00_axi_awvalid,
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s00_axi_awready,
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s00_axi_wdata,
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||||
s00_axi_wstrb,
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s00_axi_wvalid,
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s00_axi_wready,
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||||
s00_axi_bresp,
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s00_axi_bvalid,
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s00_axi_bready,
|
||||
s00_axi_araddr,
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s00_axi_arprot,
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||||
s00_axi_arvalid,
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s00_axi_arready,
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s00_axi_rdata,
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s00_axi_rresp,
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s00_axi_rvalid,
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s00_axi_rready,
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s00_axi_aclk,
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s00_axi_aresetn
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);
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(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF axis:m_axis, ASSOCIATED_RESET aresetn, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN system_top_data_clk, INSERT_VIP 0" *)
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(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk CLK" *)
|
||||
input wire aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 aresetn RST" *)
|
||||
input wire aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 axis TVALID" *)
|
||||
input wire axis_tvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 axis TLAST" *)
|
||||
input wire axis_tlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 axis TREADY" *)
|
||||
output wire axis_ready;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME axis, TDATA_NUM_BYTES 8, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN system_top_data_clk, LAYERED_METADATA undef, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 axis TDATA" *)
|
||||
input wire [63 : 0] axis_tdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis TVALID" *)
|
||||
output wire m_axis_tvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis TLAST" *)
|
||||
output wire m_axis_tlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis TREADY" *)
|
||||
input wire m_axis_ready;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_axis, TDATA_NUM_BYTES 8, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN system_top_data_clk, LAYERED_METADATA undef, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis TDATA" *)
|
||||
output wire [63 : 0] m_axis_tdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR" *)
|
||||
input wire [3 : 0] s00_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT" *)
|
||||
input wire [2 : 0] s00_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID" *)
|
||||
input wire s00_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY" *)
|
||||
output wire s00_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA" *)
|
||||
input wire [31 : 0] s00_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB" *)
|
||||
input wire [3 : 0] s00_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID" *)
|
||||
input wire s00_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY" *)
|
||||
output wire s00_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP" *)
|
||||
output wire [1 : 0] s00_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID" *)
|
||||
output wire s00_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY" *)
|
||||
input wire s00_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR" *)
|
||||
input wire [3 : 0] s00_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT" *)
|
||||
input wire [2 : 0] s00_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID" *)
|
||||
input wire s00_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY" *)
|
||||
output wire s00_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA" *)
|
||||
output wire [31 : 0] s00_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP" *)
|
||||
output wire [1 : 0] s00_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID" *)
|
||||
output wire s00_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI, WIZ_DATA_WIDTH 32, WIZ_NUM_REG 4, SUPPORTS_NARROW_BURST 0, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 4, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN system_top_processing_syste\
|
||||
m7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *)
|
||||
input wire s00_axi_rready;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI_CLK, ASSOCIATED_BUSIF S00_AXI, ASSOCIATED_RESET s00_axi_aresetn, FREQ_HZ 1e+08, PHASE 0.000, CLK_DOMAIN system_top_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 S00_AXI_CLK CLK" *)
|
||||
input wire s00_axi_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 S00_AXI_RST RST" *)
|
||||
input wire s00_axi_aresetn;
|
||||
|
||||
Axis_adc_data_packer_v1_0 #(
|
||||
.C_S00_AXI_DATA_WIDTH(32), // Width of S_AXI data bus
|
||||
.C_S00_AXI_ADDR_WIDTH(4) // Width of S_AXI address bus
|
||||
) inst (
|
||||
.aclk(aclk),
|
||||
.aresetn(aresetn),
|
||||
.axis_tvalid(axis_tvalid),
|
||||
.axis_tlast(axis_tlast),
|
||||
.axis_ready(axis_ready),
|
||||
.axis_tdata(axis_tdata),
|
||||
.m_axis_tvalid(m_axis_tvalid),
|
||||
.m_axis_tlast(m_axis_tlast),
|
||||
.m_axis_ready(m_axis_ready),
|
||||
.m_axis_tdata(m_axis_tdata),
|
||||
.s00_axi_awaddr(s00_axi_awaddr),
|
||||
.s00_axi_awprot(s00_axi_awprot),
|
||||
.s00_axi_awvalid(s00_axi_awvalid),
|
||||
.s00_axi_awready(s00_axi_awready),
|
||||
.s00_axi_wdata(s00_axi_wdata),
|
||||
.s00_axi_wstrb(s00_axi_wstrb),
|
||||
.s00_axi_wvalid(s00_axi_wvalid),
|
||||
.s00_axi_wready(s00_axi_wready),
|
||||
.s00_axi_bresp(s00_axi_bresp),
|
||||
.s00_axi_bvalid(s00_axi_bvalid),
|
||||
.s00_axi_bready(s00_axi_bready),
|
||||
.s00_axi_araddr(s00_axi_araddr),
|
||||
.s00_axi_arprot(s00_axi_arprot),
|
||||
.s00_axi_arvalid(s00_axi_arvalid),
|
||||
.s00_axi_arready(s00_axi_arready),
|
||||
.s00_axi_rdata(s00_axi_rdata),
|
||||
.s00_axi_rresp(s00_axi_rresp),
|
||||
.s00_axi_rvalid(s00_axi_rvalid),
|
||||
.s00_axi_rready(s00_axi_rready),
|
||||
.s00_axi_aclk(s00_axi_aclk),
|
||||
.s00_axi_aresetn(s00_axi_aresetn)
|
||||
);
|
||||
endmodule
|
||||
+1
-1
@@ -50,7 +50,7 @@
|
||||
// IP VLNV: labnet.com:user:Axis_adc_data_packer:1.0
|
||||
// IP Revision: 9
|
||||
|
||||
(* X_CORE_INFO = "Axis_adc_data_packer_v1_0,Vivado 2024.1" *)
|
||||
(* X_CORE_INFO = "Axis_adc_data_packer_v1_0,Vivado 2024.1.2" *)
|
||||
(* CHECK_LICENSE_TYPE = "system_top_Axis_adc_data_packer_0_0,Axis_adc_data_packer_v1_0,{}" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module system_top_Axis_adc_data_packer_0_0 (
|
||||
|
||||
+1
-1
@@ -39,7 +39,7 @@
|
||||
"OUTPUTDIR": [ { "value": "." } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2024.1" } ],
|
||||
"SWVERSION": [ { "value": "2024.1.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
|
||||
+97
-3
@@ -990,7 +990,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Oct 31 03:29:29 UTC 2024</spirit:value>
|
||||
<spirit:value>Sun Nov 03 07:49:49 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -1009,6 +1009,46 @@
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_verilogbehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Verilog Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:language>verilog</spirit:language>
|
||||
<spirit:modelName>Axis_adc_data_packer_v1_0</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_verilogbehavioralsimulation_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Nov 03 07:49:49 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:24fe4614</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_verilogsimulationwrapper</spirit:name>
|
||||
<spirit:displayName>Verilog Simulation Wrapper</spirit:displayName>
|
||||
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
|
||||
<spirit:language>verilog</spirit:language>
|
||||
<spirit:modelName>system_top_Axis_adc_data_packer_0_0</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_verilogsimulationwrapper_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Nov 03 07:49:49 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:24fe4614</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_verilogsynthesis</spirit:name>
|
||||
<spirit:displayName>Verilog Synthesis</spirit:displayName>
|
||||
@@ -1021,7 +1061,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Oct 31 03:29:29 UTC 2024</spirit:value>
|
||||
<spirit:value>Sun Nov 03 07:49:49 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -1041,7 +1081,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Oct 31 03:29:29 UTC 2024</spirit:value>
|
||||
<spirit:value>Sun Nov 03 07:49:49 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -1059,6 +1099,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1071,6 +1112,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1083,6 +1125,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1095,6 +1138,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1110,6 +1154,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1126,6 +1171,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1141,6 +1187,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1153,6 +1200,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1165,6 +1213,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1181,6 +1230,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1197,6 +1247,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1213,6 +1264,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1225,6 +1277,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1237,6 +1290,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1253,6 +1307,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1269,6 +1324,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1281,6 +1337,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1293,6 +1350,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1309,6 +1367,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1321,6 +1380,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1333,6 +1393,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1349,6 +1410,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1365,6 +1427,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1377,6 +1440,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1389,6 +1453,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1405,6 +1470,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1421,6 +1487,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1433,6 +1500,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1445,6 +1513,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1457,6 +1526,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1469,6 +1539,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1533,6 +1604,29 @@
|
||||
<spirit:fileType>cSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_verilogbehavioralsimulation_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>../../ipshared/9971/hdl/Axis_adc_data_packer_v1_0_S00_AXI.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../ipshared/9971/hdl/axis_adc_data_packer.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../ipshared/9971/hdl/Axis_adc_data_packer_v1_0.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_verilogsimulationwrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>sim/system_top_Axis_adc_data_packer_0_0.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_verilogsynthesis_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
|
||||
+26
-14
@@ -5,22 +5,34 @@ COMPILER_FLAGS=
|
||||
EXTRA_COMPILER_FLAGS=
|
||||
LIB=libxil.a
|
||||
|
||||
RELEASEDIR=../../../lib
|
||||
INCLUDEDIR=../../../include
|
||||
INCLUDES=-I./. -I${INCLUDEDIR}
|
||||
CC_FLAGS = $(COMPILER_FLAGS)
|
||||
ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
|
||||
|
||||
INCLUDEFILES=*.h
|
||||
LIBSOURCES=*.c
|
||||
OUTS = *.o
|
||||
RELEASEDIR=../../../lib/
|
||||
INCLUDEDIR=../../../include/
|
||||
INCLUDES=-I./. -I$(INCLUDEDIR)
|
||||
|
||||
libs:
|
||||
echo "Compiling Axis_adc_data_packer..."
|
||||
$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
|
||||
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
|
||||
make clean
|
||||
SRCFILES:=$(wildcard *.c)
|
||||
|
||||
include:
|
||||
${CP} $(INCLUDEFILES) $(INCLUDEDIR)
|
||||
OBJECTS = $(addprefix $(RELEASEDIR), $(addsuffix .o, $(basename $(wildcard *.c))))
|
||||
|
||||
libs: $(OBJECTS)
|
||||
|
||||
DEPFILES := $(SRCFILES:%.c=$(RELEASEDIR)%.d)
|
||||
|
||||
include $(wildcard $(DEPFILES))
|
||||
|
||||
include $(wildcard ../../../../dep.mk)
|
||||
|
||||
$(RELEASEDIR)%.o: %.c
|
||||
${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $(DEPENDENCY_FLAGS) $< -o $@
|
||||
|
||||
.PHONY: include
|
||||
include: $(addprefix $(INCLUDEDIR),$(wildcard *.h))
|
||||
|
||||
$(INCLUDEDIR)%.h: %.h
|
||||
$(CP) $< $@
|
||||
|
||||
clean:
|
||||
rm -rf ${OUTS}
|
||||
rm -rf ${OBJECTS}
|
||||
rm -rf $(DEPFILES)
|
||||
|
||||
+197
@@ -0,0 +1,197 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: labnet.com:user:Axis_adc_data_packer:1.0
|
||||
// IP Revision: 9
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module system_top_Axis_adc_data_packer_1_0 (
|
||||
aclk,
|
||||
aresetn,
|
||||
axis_tvalid,
|
||||
axis_tlast,
|
||||
axis_ready,
|
||||
axis_tdata,
|
||||
m_axis_tvalid,
|
||||
m_axis_tlast,
|
||||
m_axis_ready,
|
||||
m_axis_tdata,
|
||||
s00_axi_awaddr,
|
||||
s00_axi_awprot,
|
||||
s00_axi_awvalid,
|
||||
s00_axi_awready,
|
||||
s00_axi_wdata,
|
||||
s00_axi_wstrb,
|
||||
s00_axi_wvalid,
|
||||
s00_axi_wready,
|
||||
s00_axi_bresp,
|
||||
s00_axi_bvalid,
|
||||
s00_axi_bready,
|
||||
s00_axi_araddr,
|
||||
s00_axi_arprot,
|
||||
s00_axi_arvalid,
|
||||
s00_axi_arready,
|
||||
s00_axi_rdata,
|
||||
s00_axi_rresp,
|
||||
s00_axi_rvalid,
|
||||
s00_axi_rready,
|
||||
s00_axi_aclk,
|
||||
s00_axi_aresetn
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF axis:m_axis, ASSOCIATED_RESET aresetn, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN system_top_data_clk_1, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk CLK" *)
|
||||
input wire aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 aresetn RST" *)
|
||||
input wire aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 axis TVALID" *)
|
||||
input wire axis_tvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 axis TLAST" *)
|
||||
input wire axis_tlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 axis TREADY" *)
|
||||
output wire axis_ready;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME axis, TDATA_NUM_BYTES 8, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN system_top_data_clk_1, LAYERED_METADATA undef, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 axis TDATA" *)
|
||||
input wire [63 : 0] axis_tdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis TVALID" *)
|
||||
output wire m_axis_tvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis TLAST" *)
|
||||
output wire m_axis_tlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis TREADY" *)
|
||||
input wire m_axis_ready;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_axis, TDATA_NUM_BYTES 8, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN system_top_data_clk_1, LAYERED_METADATA undef, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis TDATA" *)
|
||||
output wire [63 : 0] m_axis_tdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR" *)
|
||||
input wire [3 : 0] s00_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT" *)
|
||||
input wire [2 : 0] s00_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID" *)
|
||||
input wire s00_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY" *)
|
||||
output wire s00_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA" *)
|
||||
input wire [31 : 0] s00_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB" *)
|
||||
input wire [3 : 0] s00_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID" *)
|
||||
input wire s00_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY" *)
|
||||
output wire s00_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP" *)
|
||||
output wire [1 : 0] s00_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID" *)
|
||||
output wire s00_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY" *)
|
||||
input wire s00_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR" *)
|
||||
input wire [3 : 0] s00_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT" *)
|
||||
input wire [2 : 0] s00_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID" *)
|
||||
input wire s00_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY" *)
|
||||
output wire s00_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA" *)
|
||||
output wire [31 : 0] s00_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP" *)
|
||||
output wire [1 : 0] s00_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID" *)
|
||||
output wire s00_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI, WIZ_DATA_WIDTH 32, WIZ_NUM_REG 4, SUPPORTS_NARROW_BURST 0, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 4, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN system_top_processing_syste\
|
||||
m7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *)
|
||||
input wire s00_axi_rready;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI_CLK, ASSOCIATED_BUSIF S00_AXI, ASSOCIATED_RESET s00_axi_aresetn, FREQ_HZ 1e+08, PHASE 0.000, CLK_DOMAIN system_top_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 S00_AXI_CLK CLK" *)
|
||||
input wire s00_axi_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 S00_AXI_RST RST" *)
|
||||
input wire s00_axi_aresetn;
|
||||
|
||||
Axis_adc_data_packer_v1_0 #(
|
||||
.C_S00_AXI_DATA_WIDTH(32), // Width of S_AXI data bus
|
||||
.C_S00_AXI_ADDR_WIDTH(4) // Width of S_AXI address bus
|
||||
) inst (
|
||||
.aclk(aclk),
|
||||
.aresetn(aresetn),
|
||||
.axis_tvalid(axis_tvalid),
|
||||
.axis_tlast(axis_tlast),
|
||||
.axis_ready(axis_ready),
|
||||
.axis_tdata(axis_tdata),
|
||||
.m_axis_tvalid(m_axis_tvalid),
|
||||
.m_axis_tlast(m_axis_tlast),
|
||||
.m_axis_ready(m_axis_ready),
|
||||
.m_axis_tdata(m_axis_tdata),
|
||||
.s00_axi_awaddr(s00_axi_awaddr),
|
||||
.s00_axi_awprot(s00_axi_awprot),
|
||||
.s00_axi_awvalid(s00_axi_awvalid),
|
||||
.s00_axi_awready(s00_axi_awready),
|
||||
.s00_axi_wdata(s00_axi_wdata),
|
||||
.s00_axi_wstrb(s00_axi_wstrb),
|
||||
.s00_axi_wvalid(s00_axi_wvalid),
|
||||
.s00_axi_wready(s00_axi_wready),
|
||||
.s00_axi_bresp(s00_axi_bresp),
|
||||
.s00_axi_bvalid(s00_axi_bvalid),
|
||||
.s00_axi_bready(s00_axi_bready),
|
||||
.s00_axi_araddr(s00_axi_araddr),
|
||||
.s00_axi_arprot(s00_axi_arprot),
|
||||
.s00_axi_arvalid(s00_axi_arvalid),
|
||||
.s00_axi_arready(s00_axi_arready),
|
||||
.s00_axi_rdata(s00_axi_rdata),
|
||||
.s00_axi_rresp(s00_axi_rresp),
|
||||
.s00_axi_rvalid(s00_axi_rvalid),
|
||||
.s00_axi_rready(s00_axi_rready),
|
||||
.s00_axi_aclk(s00_axi_aclk),
|
||||
.s00_axi_aresetn(s00_axi_aresetn)
|
||||
);
|
||||
endmodule
|
||||
+1
-1
@@ -50,7 +50,7 @@
|
||||
// IP VLNV: labnet.com:user:Axis_adc_data_packer:1.0
|
||||
// IP Revision: 9
|
||||
|
||||
(* X_CORE_INFO = "Axis_adc_data_packer_v1_0,Vivado 2024.1" *)
|
||||
(* X_CORE_INFO = "Axis_adc_data_packer_v1_0,Vivado 2024.1.2" *)
|
||||
(* CHECK_LICENSE_TYPE = "system_top_Axis_adc_data_packer_1_0,Axis_adc_data_packer_v1_0,{}" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module system_top_Axis_adc_data_packer_1_0 (
|
||||
|
||||
+1
-1
@@ -39,7 +39,7 @@
|
||||
"OUTPUTDIR": [ { "value": "." } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2024.1" } ],
|
||||
"SWVERSION": [ { "value": "2024.1.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
|
||||
+97
-3
@@ -990,7 +990,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Oct 31 03:29:29 UTC 2024</spirit:value>
|
||||
<spirit:value>Sun Nov 03 07:49:49 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -1009,6 +1009,46 @@
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_verilogbehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Verilog Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:language>verilog</spirit:language>
|
||||
<spirit:modelName>Axis_adc_data_packer_v1_0</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_verilogbehavioralsimulation_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Nov 03 07:49:49 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:4b0781e0</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_verilogsimulationwrapper</spirit:name>
|
||||
<spirit:displayName>Verilog Simulation Wrapper</spirit:displayName>
|
||||
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
|
||||
<spirit:language>verilog</spirit:language>
|
||||
<spirit:modelName>system_top_Axis_adc_data_packer_1_0</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_verilogsimulationwrapper_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Nov 03 07:49:49 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:4b0781e0</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_verilogsynthesis</spirit:name>
|
||||
<spirit:displayName>Verilog Synthesis</spirit:displayName>
|
||||
@@ -1021,7 +1061,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Oct 31 03:29:29 UTC 2024</spirit:value>
|
||||
<spirit:value>Sun Nov 03 07:49:49 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -1041,7 +1081,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Oct 31 03:29:29 UTC 2024</spirit:value>
|
||||
<spirit:value>Sun Nov 03 07:49:49 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -1059,6 +1099,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1071,6 +1112,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1083,6 +1125,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1095,6 +1138,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1110,6 +1154,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1126,6 +1171,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1141,6 +1187,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1153,6 +1200,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1165,6 +1213,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1181,6 +1230,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1197,6 +1247,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1213,6 +1264,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1225,6 +1277,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1237,6 +1290,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1253,6 +1307,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1269,6 +1324,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1281,6 +1337,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1293,6 +1350,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1309,6 +1367,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1321,6 +1380,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1333,6 +1393,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1349,6 +1410,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1365,6 +1427,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1377,6 +1440,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1389,6 +1453,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1405,6 +1470,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1421,6 +1487,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1433,6 +1500,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1445,6 +1513,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1457,6 +1526,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1469,6 +1539,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1533,6 +1604,29 @@
|
||||
<spirit:fileType>cSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_verilogbehavioralsimulation_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>../../ipshared/9971/hdl/Axis_adc_data_packer_v1_0_S00_AXI.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../ipshared/9971/hdl/axis_adc_data_packer.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../ipshared/9971/hdl/Axis_adc_data_packer_v1_0.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_verilogsimulationwrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>sim/system_top_Axis_adc_data_packer_1_0.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_verilogsynthesis_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
|
||||
+26
-14
@@ -5,22 +5,34 @@ COMPILER_FLAGS=
|
||||
EXTRA_COMPILER_FLAGS=
|
||||
LIB=libxil.a
|
||||
|
||||
RELEASEDIR=../../../lib
|
||||
INCLUDEDIR=../../../include
|
||||
INCLUDES=-I./. -I${INCLUDEDIR}
|
||||
CC_FLAGS = $(COMPILER_FLAGS)
|
||||
ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
|
||||
|
||||
INCLUDEFILES=*.h
|
||||
LIBSOURCES=*.c
|
||||
OUTS = *.o
|
||||
RELEASEDIR=../../../lib/
|
||||
INCLUDEDIR=../../../include/
|
||||
INCLUDES=-I./. -I$(INCLUDEDIR)
|
||||
|
||||
libs:
|
||||
echo "Compiling Axis_adc_data_packer..."
|
||||
$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
|
||||
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
|
||||
make clean
|
||||
SRCFILES:=$(wildcard *.c)
|
||||
|
||||
include:
|
||||
${CP} $(INCLUDEFILES) $(INCLUDEDIR)
|
||||
OBJECTS = $(addprefix $(RELEASEDIR), $(addsuffix .o, $(basename $(wildcard *.c))))
|
||||
|
||||
libs: $(OBJECTS)
|
||||
|
||||
DEPFILES := $(SRCFILES:%.c=$(RELEASEDIR)%.d)
|
||||
|
||||
include $(wildcard $(DEPFILES))
|
||||
|
||||
include $(wildcard ../../../../dep.mk)
|
||||
|
||||
$(RELEASEDIR)%.o: %.c
|
||||
${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $(DEPENDENCY_FLAGS) $< -o $@
|
||||
|
||||
.PHONY: include
|
||||
include: $(addprefix $(INCLUDEDIR),$(wildcard *.h))
|
||||
|
||||
$(INCLUDEDIR)%.h: %.h
|
||||
$(CP) $< $@
|
||||
|
||||
clean:
|
||||
rm -rf ${OUTS}
|
||||
rm -rf ${OBJECTS}
|
||||
rm -rf $(DEPFILES)
|
||||
|
||||
+197
@@ -0,0 +1,197 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: labnet.com:user:Axis_adc_data_packer:1.0
|
||||
// IP Revision: 9
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module system_top_Axis_adc_data_packer_2_0 (
|
||||
aclk,
|
||||
aresetn,
|
||||
axis_tvalid,
|
||||
axis_tlast,
|
||||
axis_ready,
|
||||
axis_tdata,
|
||||
m_axis_tvalid,
|
||||
m_axis_tlast,
|
||||
m_axis_ready,
|
||||
m_axis_tdata,
|
||||
s00_axi_awaddr,
|
||||
s00_axi_awprot,
|
||||
s00_axi_awvalid,
|
||||
s00_axi_awready,
|
||||
s00_axi_wdata,
|
||||
s00_axi_wstrb,
|
||||
s00_axi_wvalid,
|
||||
s00_axi_wready,
|
||||
s00_axi_bresp,
|
||||
s00_axi_bvalid,
|
||||
s00_axi_bready,
|
||||
s00_axi_araddr,
|
||||
s00_axi_arprot,
|
||||
s00_axi_arvalid,
|
||||
s00_axi_arready,
|
||||
s00_axi_rdata,
|
||||
s00_axi_rresp,
|
||||
s00_axi_rvalid,
|
||||
s00_axi_rready,
|
||||
s00_axi_aclk,
|
||||
s00_axi_aresetn
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF axis:m_axis, ASSOCIATED_RESET aresetn, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN system_top_data_clk_2, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk CLK" *)
|
||||
input wire aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 aresetn RST" *)
|
||||
input wire aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 axis TVALID" *)
|
||||
input wire axis_tvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 axis TLAST" *)
|
||||
input wire axis_tlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 axis TREADY" *)
|
||||
output wire axis_ready;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME axis, TDATA_NUM_BYTES 8, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN system_top_data_clk_2, LAYERED_METADATA undef, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 axis TDATA" *)
|
||||
input wire [63 : 0] axis_tdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis TVALID" *)
|
||||
output wire m_axis_tvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis TLAST" *)
|
||||
output wire m_axis_tlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis TREADY" *)
|
||||
input wire m_axis_ready;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_axis, TDATA_NUM_BYTES 8, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN system_top_data_clk_2, LAYERED_METADATA undef, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis TDATA" *)
|
||||
output wire [63 : 0] m_axis_tdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR" *)
|
||||
input wire [3 : 0] s00_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT" *)
|
||||
input wire [2 : 0] s00_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID" *)
|
||||
input wire s00_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY" *)
|
||||
output wire s00_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA" *)
|
||||
input wire [31 : 0] s00_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB" *)
|
||||
input wire [3 : 0] s00_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID" *)
|
||||
input wire s00_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY" *)
|
||||
output wire s00_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP" *)
|
||||
output wire [1 : 0] s00_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID" *)
|
||||
output wire s00_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY" *)
|
||||
input wire s00_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR" *)
|
||||
input wire [3 : 0] s00_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT" *)
|
||||
input wire [2 : 0] s00_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID" *)
|
||||
input wire s00_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY" *)
|
||||
output wire s00_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA" *)
|
||||
output wire [31 : 0] s00_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP" *)
|
||||
output wire [1 : 0] s00_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID" *)
|
||||
output wire s00_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI, WIZ_DATA_WIDTH 32, WIZ_NUM_REG 4, SUPPORTS_NARROW_BURST 0, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 4, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN system_top_processing_syste\
|
||||
m7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *)
|
||||
input wire s00_axi_rready;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI_CLK, ASSOCIATED_BUSIF S00_AXI, ASSOCIATED_RESET s00_axi_aresetn, FREQ_HZ 1e+08, PHASE 0.000, CLK_DOMAIN system_top_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 S00_AXI_CLK CLK" *)
|
||||
input wire s00_axi_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 S00_AXI_RST RST" *)
|
||||
input wire s00_axi_aresetn;
|
||||
|
||||
Axis_adc_data_packer_v1_0 #(
|
||||
.C_S00_AXI_DATA_WIDTH(32), // Width of S_AXI data bus
|
||||
.C_S00_AXI_ADDR_WIDTH(4) // Width of S_AXI address bus
|
||||
) inst (
|
||||
.aclk(aclk),
|
||||
.aresetn(aresetn),
|
||||
.axis_tvalid(axis_tvalid),
|
||||
.axis_tlast(axis_tlast),
|
||||
.axis_ready(axis_ready),
|
||||
.axis_tdata(axis_tdata),
|
||||
.m_axis_tvalid(m_axis_tvalid),
|
||||
.m_axis_tlast(m_axis_tlast),
|
||||
.m_axis_ready(m_axis_ready),
|
||||
.m_axis_tdata(m_axis_tdata),
|
||||
.s00_axi_awaddr(s00_axi_awaddr),
|
||||
.s00_axi_awprot(s00_axi_awprot),
|
||||
.s00_axi_awvalid(s00_axi_awvalid),
|
||||
.s00_axi_awready(s00_axi_awready),
|
||||
.s00_axi_wdata(s00_axi_wdata),
|
||||
.s00_axi_wstrb(s00_axi_wstrb),
|
||||
.s00_axi_wvalid(s00_axi_wvalid),
|
||||
.s00_axi_wready(s00_axi_wready),
|
||||
.s00_axi_bresp(s00_axi_bresp),
|
||||
.s00_axi_bvalid(s00_axi_bvalid),
|
||||
.s00_axi_bready(s00_axi_bready),
|
||||
.s00_axi_araddr(s00_axi_araddr),
|
||||
.s00_axi_arprot(s00_axi_arprot),
|
||||
.s00_axi_arvalid(s00_axi_arvalid),
|
||||
.s00_axi_arready(s00_axi_arready),
|
||||
.s00_axi_rdata(s00_axi_rdata),
|
||||
.s00_axi_rresp(s00_axi_rresp),
|
||||
.s00_axi_rvalid(s00_axi_rvalid),
|
||||
.s00_axi_rready(s00_axi_rready),
|
||||
.s00_axi_aclk(s00_axi_aclk),
|
||||
.s00_axi_aresetn(s00_axi_aresetn)
|
||||
);
|
||||
endmodule
|
||||
+1
-1
@@ -50,7 +50,7 @@
|
||||
// IP VLNV: labnet.com:user:Axis_adc_data_packer:1.0
|
||||
// IP Revision: 9
|
||||
|
||||
(* X_CORE_INFO = "Axis_adc_data_packer_v1_0,Vivado 2024.1" *)
|
||||
(* X_CORE_INFO = "Axis_adc_data_packer_v1_0,Vivado 2024.1.2" *)
|
||||
(* CHECK_LICENSE_TYPE = "system_top_Axis_adc_data_packer_2_0,Axis_adc_data_packer_v1_0,{}" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module system_top_Axis_adc_data_packer_2_0 (
|
||||
|
||||
+1
-1
@@ -39,7 +39,7 @@
|
||||
"OUTPUTDIR": [ { "value": "." } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2024.1" } ],
|
||||
"SWVERSION": [ { "value": "2024.1.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
|
||||
+97
-3
@@ -990,7 +990,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Oct 31 03:29:29 UTC 2024</spirit:value>
|
||||
<spirit:value>Sun Nov 03 07:49:49 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -1009,6 +1009,46 @@
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_verilogbehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Verilog Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:language>verilog</spirit:language>
|
||||
<spirit:modelName>Axis_adc_data_packer_v1_0</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_verilogbehavioralsimulation_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Nov 03 07:49:49 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:fb0dc9fc</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_verilogsimulationwrapper</spirit:name>
|
||||
<spirit:displayName>Verilog Simulation Wrapper</spirit:displayName>
|
||||
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
|
||||
<spirit:language>verilog</spirit:language>
|
||||
<spirit:modelName>system_top_Axis_adc_data_packer_2_0</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_verilogsimulationwrapper_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Nov 03 07:49:49 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:fb0dc9fc</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_verilogsynthesis</spirit:name>
|
||||
<spirit:displayName>Verilog Synthesis</spirit:displayName>
|
||||
@@ -1021,7 +1061,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Oct 31 03:29:29 UTC 2024</spirit:value>
|
||||
<spirit:value>Sun Nov 03 07:49:49 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -1041,7 +1081,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Oct 31 03:29:29 UTC 2024</spirit:value>
|
||||
<spirit:value>Sun Nov 03 07:49:49 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -1059,6 +1099,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1071,6 +1112,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1083,6 +1125,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1095,6 +1138,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1110,6 +1154,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1126,6 +1171,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1141,6 +1187,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1153,6 +1200,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1165,6 +1213,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1181,6 +1230,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1197,6 +1247,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1213,6 +1264,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1225,6 +1277,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1237,6 +1290,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1253,6 +1307,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1269,6 +1324,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1281,6 +1337,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1293,6 +1350,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1309,6 +1367,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1321,6 +1380,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1333,6 +1393,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1349,6 +1410,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1365,6 +1427,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1377,6 +1440,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1389,6 +1453,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1405,6 +1470,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1421,6 +1487,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1433,6 +1500,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1445,6 +1513,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1457,6 +1526,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1469,6 +1539,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1533,6 +1604,29 @@
|
||||
<spirit:fileType>cSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_verilogbehavioralsimulation_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>../../ipshared/9971/hdl/Axis_adc_data_packer_v1_0_S00_AXI.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../ipshared/9971/hdl/axis_adc_data_packer.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../ipshared/9971/hdl/Axis_adc_data_packer_v1_0.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_verilogsimulationwrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>sim/system_top_Axis_adc_data_packer_2_0.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_verilogsynthesis_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
|
||||
+167
@@ -0,0 +1,167 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: cxkj.com:user:axi4_lite_spi:1.0
|
||||
// IP Revision: 2
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* IP_DEFINITION_SOURCE = "package_project" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module system_top_axi4_lite_spi_0_0 (
|
||||
s_axi_aclk,
|
||||
s_axi_aresetn,
|
||||
s_axi_awaddr,
|
||||
s_axi_awvalid,
|
||||
s_axi_awready,
|
||||
s_axi_wdata,
|
||||
s_axi_wstrb,
|
||||
s_axi_wvalid,
|
||||
s_axi_wready,
|
||||
s_axi_bresp,
|
||||
s_axi_bvalid,
|
||||
s_axi_bready,
|
||||
s_axi_araddr,
|
||||
s_axi_arvalid,
|
||||
s_axi_arready,
|
||||
s_axi_rdata,
|
||||
s_axi_rresp,
|
||||
s_axi_rvalid,
|
||||
s_axi_rready,
|
||||
sclk_o,
|
||||
ssn_o,
|
||||
miso_i,
|
||||
mosi_o,
|
||||
sdio
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi_aclk, ASSOCIATED_BUSIF s_axi, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 1e+08, PHASE 0.000, CLK_DOMAIN system_top_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 s_axi_aclk CLK" *)
|
||||
input wire s_axi_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 s_axi_aresetn RST" *)
|
||||
input wire s_axi_aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWADDR" *)
|
||||
input wire [31 : 0] s_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWVALID" *)
|
||||
input wire s_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWREADY" *)
|
||||
output wire s_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WDATA" *)
|
||||
input wire [31 : 0] s_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WSTRB" *)
|
||||
input wire [3 : 0] s_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WVALID" *)
|
||||
input wire s_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WREADY" *)
|
||||
output wire s_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BRESP" *)
|
||||
output wire [1 : 0] s_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BVALID" *)
|
||||
output wire s_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BREADY" *)
|
||||
input wire s_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARADDR" *)
|
||||
input wire [31 : 0] s_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARVALID" *)
|
||||
input wire s_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARREADY" *)
|
||||
output wire s_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RDATA" *)
|
||||
output wire [31 : 0] s_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RRESP" *)
|
||||
output wire [1 : 0] s_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RVALID" *)
|
||||
output wire s_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN system_top_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS \
|
||||
1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RREADY" *)
|
||||
input wire s_axi_rready;
|
||||
output wire sclk_o;
|
||||
output wire ssn_o;
|
||||
input wire miso_i;
|
||||
output wire mosi_o;
|
||||
inout wire sdio;
|
||||
|
||||
axi4_lite_spi #(
|
||||
.C_S_AXI_ADDR_WIDTH(32),
|
||||
.C_S_AXI_DATA_WIDTH(32),
|
||||
.REGS_SIZE(24),
|
||||
.SPI_CONFIG(7'B1011101),
|
||||
.BAUD_RATE(16'H0002),
|
||||
.REG_WIDTH(8),
|
||||
.CHIP_ADDR_WIDTH(12),
|
||||
.FOUR_WIRE_SPI("false")
|
||||
) inst (
|
||||
.s_axi_aclk(s_axi_aclk),
|
||||
.s_axi_aresetn(s_axi_aresetn),
|
||||
.s_axi_awaddr(s_axi_awaddr),
|
||||
.s_axi_awvalid(s_axi_awvalid),
|
||||
.s_axi_awready(s_axi_awready),
|
||||
.s_axi_wdata(s_axi_wdata),
|
||||
.s_axi_wstrb(s_axi_wstrb),
|
||||
.s_axi_wvalid(s_axi_wvalid),
|
||||
.s_axi_wready(s_axi_wready),
|
||||
.s_axi_bresp(s_axi_bresp),
|
||||
.s_axi_bvalid(s_axi_bvalid),
|
||||
.s_axi_bready(s_axi_bready),
|
||||
.s_axi_araddr(s_axi_araddr),
|
||||
.s_axi_arvalid(s_axi_arvalid),
|
||||
.s_axi_arready(s_axi_arready),
|
||||
.s_axi_rdata(s_axi_rdata),
|
||||
.s_axi_rresp(s_axi_rresp),
|
||||
.s_axi_rvalid(s_axi_rvalid),
|
||||
.s_axi_rready(s_axi_rready),
|
||||
.sclk_o(sclk_o),
|
||||
.ssn_o(ssn_o),
|
||||
.miso_i(miso_i),
|
||||
.mosi_o(mosi_o),
|
||||
.sdio(sdio)
|
||||
);
|
||||
endmodule
|
||||
+1
-1
@@ -50,7 +50,7 @@
|
||||
// IP VLNV: cxkj.com:user:axi4_lite_spi:1.0
|
||||
// IP Revision: 2
|
||||
|
||||
(* X_CORE_INFO = "axi4_lite_spi,Vivado 2024.1" *)
|
||||
(* X_CORE_INFO = "axi4_lite_spi,Vivado 2024.1.2" *)
|
||||
(* CHECK_LICENSE_TYPE = "system_top_axi4_lite_spi_0_0,axi4_lite_spi,{}" *)
|
||||
(* IP_DEFINITION_SOURCE = "package_project" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
|
||||
+1
-1
@@ -49,7 +49,7 @@
|
||||
"OUTPUTDIR": [ { "value": "." } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2024.1" } ],
|
||||
"SWVERSION": [ { "value": "2024.1.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
|
||||
+92
-2
@@ -540,6 +540,25 @@
|
||||
</spirit:memoryMaps>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:modelName>axi4_lite_spi</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Nov 03 07:50:02 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:4deb1464</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
|
||||
<spirit:displayName>Synthesis</spirit:displayName>
|
||||
@@ -551,7 +570,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Oct 31 03:29:38 UTC 2024</spirit:value>
|
||||
<spirit:value>Sun Nov 03 07:50:02 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -570,6 +589,26 @@
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_verilogsimulationwrapper</spirit:name>
|
||||
<spirit:displayName>Verilog Simulation Wrapper</spirit:displayName>
|
||||
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
|
||||
<spirit:language>verilog</spirit:language>
|
||||
<spirit:modelName>system_top_axi4_lite_spi_0_0</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_verilogsimulationwrapper_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Nov 03 07:50:02 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:4deb1464</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_verilogsynthesiswrapper</spirit:name>
|
||||
<spirit:displayName>Verilog Synthesis Wrapper</spirit:displayName>
|
||||
@@ -582,7 +621,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Oct 31 03:29:38 UTC 2024</spirit:value>
|
||||
<spirit:value>Sun Nov 03 07:50:02 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -600,6 +639,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -612,6 +652,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -628,6 +669,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -643,6 +685,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -658,6 +701,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -674,6 +718,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -693,6 +738,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -708,6 +754,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -723,6 +770,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -739,6 +787,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -751,6 +800,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -763,6 +813,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -782,6 +833,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -797,6 +849,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -812,6 +865,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -828,6 +882,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -844,6 +899,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -856,6 +912,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -868,6 +925,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -883,6 +941,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -895,6 +954,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -907,6 +967,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -919,6 +980,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -931,6 +993,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -987,6 +1050,25 @@
|
||||
</spirit:choice>
|
||||
</spirit:choices>
|
||||
<spirit:fileSets>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>../../ipshared/cb12/rtl/axi4_lite_wrapper.sv</spirit:name>
|
||||
<spirit:fileType>systemVerilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../ipshared/cb12/rtl/spi_master.sv</spirit:name>
|
||||
<spirit:fileType>systemVerilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../ipshared/cb12/rtl/sync_one_stage.sv</spirit:name>
|
||||
<spirit:fileType>systemVerilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../ipshared/cb12/rtl/axi4_lite_spi.sv</spirit:name>
|
||||
<spirit:fileType>systemVerilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
@@ -1006,6 +1088,14 @@
|
||||
<spirit:fileType>systemVerilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_verilogsimulationwrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>sim/system_top_axi4_lite_spi_0_0.sv</spirit:name>
|
||||
<spirit:fileType>systemVerilogSource</spirit:fileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_verilogsynthesiswrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
|
||||
+167
@@ -0,0 +1,167 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: cxkj.com:user:axi4_lite_spi:1.0
|
||||
// IP Revision: 2
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* IP_DEFINITION_SOURCE = "package_project" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module system_top_axi4_lite_spi_0_1 (
|
||||
s_axi_aclk,
|
||||
s_axi_aresetn,
|
||||
s_axi_awaddr,
|
||||
s_axi_awvalid,
|
||||
s_axi_awready,
|
||||
s_axi_wdata,
|
||||
s_axi_wstrb,
|
||||
s_axi_wvalid,
|
||||
s_axi_wready,
|
||||
s_axi_bresp,
|
||||
s_axi_bvalid,
|
||||
s_axi_bready,
|
||||
s_axi_araddr,
|
||||
s_axi_arvalid,
|
||||
s_axi_arready,
|
||||
s_axi_rdata,
|
||||
s_axi_rresp,
|
||||
s_axi_rvalid,
|
||||
s_axi_rready,
|
||||
sclk_o,
|
||||
ssn_o,
|
||||
miso_i,
|
||||
mosi_o,
|
||||
sdio
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi_aclk, ASSOCIATED_BUSIF s_axi, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 1e+08, PHASE 0.000, CLK_DOMAIN system_top_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 s_axi_aclk CLK" *)
|
||||
input wire s_axi_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 s_axi_aresetn RST" *)
|
||||
input wire s_axi_aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWADDR" *)
|
||||
input wire [31 : 0] s_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWVALID" *)
|
||||
input wire s_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWREADY" *)
|
||||
output wire s_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WDATA" *)
|
||||
input wire [31 : 0] s_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WSTRB" *)
|
||||
input wire [3 : 0] s_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WVALID" *)
|
||||
input wire s_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WREADY" *)
|
||||
output wire s_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BRESP" *)
|
||||
output wire [1 : 0] s_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BVALID" *)
|
||||
output wire s_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BREADY" *)
|
||||
input wire s_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARADDR" *)
|
||||
input wire [31 : 0] s_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARVALID" *)
|
||||
input wire s_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARREADY" *)
|
||||
output wire s_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RDATA" *)
|
||||
output wire [31 : 0] s_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RRESP" *)
|
||||
output wire [1 : 0] s_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RVALID" *)
|
||||
output wire s_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN system_top_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS \
|
||||
1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RREADY" *)
|
||||
input wire s_axi_rready;
|
||||
output wire sclk_o;
|
||||
output wire ssn_o;
|
||||
input wire miso_i;
|
||||
output wire mosi_o;
|
||||
inout wire sdio;
|
||||
|
||||
axi4_lite_spi #(
|
||||
.C_S_AXI_ADDR_WIDTH(32),
|
||||
.C_S_AXI_DATA_WIDTH(32),
|
||||
.REGS_SIZE(24),
|
||||
.SPI_CONFIG(7'B1011101),
|
||||
.BAUD_RATE(16'H0002),
|
||||
.REG_WIDTH(8),
|
||||
.CHIP_ADDR_WIDTH(13),
|
||||
.FOUR_WIRE_SPI("true")
|
||||
) inst (
|
||||
.s_axi_aclk(s_axi_aclk),
|
||||
.s_axi_aresetn(s_axi_aresetn),
|
||||
.s_axi_awaddr(s_axi_awaddr),
|
||||
.s_axi_awvalid(s_axi_awvalid),
|
||||
.s_axi_awready(s_axi_awready),
|
||||
.s_axi_wdata(s_axi_wdata),
|
||||
.s_axi_wstrb(s_axi_wstrb),
|
||||
.s_axi_wvalid(s_axi_wvalid),
|
||||
.s_axi_wready(s_axi_wready),
|
||||
.s_axi_bresp(s_axi_bresp),
|
||||
.s_axi_bvalid(s_axi_bvalid),
|
||||
.s_axi_bready(s_axi_bready),
|
||||
.s_axi_araddr(s_axi_araddr),
|
||||
.s_axi_arvalid(s_axi_arvalid),
|
||||
.s_axi_arready(s_axi_arready),
|
||||
.s_axi_rdata(s_axi_rdata),
|
||||
.s_axi_rresp(s_axi_rresp),
|
||||
.s_axi_rvalid(s_axi_rvalid),
|
||||
.s_axi_rready(s_axi_rready),
|
||||
.sclk_o(sclk_o),
|
||||
.ssn_o(ssn_o),
|
||||
.miso_i(miso_i),
|
||||
.mosi_o(mosi_o),
|
||||
.sdio(sdio)
|
||||
);
|
||||
endmodule
|
||||
+1
-1
@@ -50,7 +50,7 @@
|
||||
// IP VLNV: cxkj.com:user:axi4_lite_spi:1.0
|
||||
// IP Revision: 2
|
||||
|
||||
(* X_CORE_INFO = "axi4_lite_spi,Vivado 2024.1" *)
|
||||
(* X_CORE_INFO = "axi4_lite_spi,Vivado 2024.1.2" *)
|
||||
(* CHECK_LICENSE_TYPE = "system_top_axi4_lite_spi_0_1,axi4_lite_spi,{}" *)
|
||||
(* IP_DEFINITION_SOURCE = "package_project" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
|
||||
+1
-1
@@ -49,7 +49,7 @@
|
||||
"OUTPUTDIR": [ { "value": "." } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2024.1" } ],
|
||||
"SWVERSION": [ { "value": "2024.1.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
|
||||
+92
-2
@@ -540,6 +540,25 @@
|
||||
</spirit:memoryMaps>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:modelName>axi4_lite_spi</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Nov 03 07:50:02 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:92904f2b</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
|
||||
<spirit:displayName>Synthesis</spirit:displayName>
|
||||
@@ -551,7 +570,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Oct 31 03:29:38 UTC 2024</spirit:value>
|
||||
<spirit:value>Sun Nov 03 07:50:02 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -570,6 +589,26 @@
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_verilogsimulationwrapper</spirit:name>
|
||||
<spirit:displayName>Verilog Simulation Wrapper</spirit:displayName>
|
||||
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
|
||||
<spirit:language>verilog</spirit:language>
|
||||
<spirit:modelName>system_top_axi4_lite_spi_0_1</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_verilogsimulationwrapper_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Nov 03 07:50:03 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:92904f2b</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_verilogsynthesiswrapper</spirit:name>
|
||||
<spirit:displayName>Verilog Synthesis Wrapper</spirit:displayName>
|
||||
@@ -582,7 +621,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Oct 31 03:29:40 UTC 2024</spirit:value>
|
||||
<spirit:value>Sun Nov 03 07:50:03 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -600,6 +639,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -612,6 +652,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -628,6 +669,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -643,6 +685,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -658,6 +701,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -674,6 +718,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -693,6 +738,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -708,6 +754,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -723,6 +770,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -739,6 +787,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -751,6 +800,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -763,6 +813,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -782,6 +833,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -797,6 +849,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -812,6 +865,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -828,6 +882,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -844,6 +899,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -856,6 +912,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -868,6 +925,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -883,6 +941,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -895,6 +954,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -907,6 +967,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -919,6 +980,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -931,6 +993,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -987,6 +1050,25 @@
|
||||
</spirit:choice>
|
||||
</spirit:choices>
|
||||
<spirit:fileSets>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>../../ipshared/cb12/rtl/axi4_lite_wrapper.sv</spirit:name>
|
||||
<spirit:fileType>systemVerilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../ipshared/cb12/rtl/spi_master.sv</spirit:name>
|
||||
<spirit:fileType>systemVerilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../ipshared/cb12/rtl/sync_one_stage.sv</spirit:name>
|
||||
<spirit:fileType>systemVerilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../ipshared/cb12/rtl/axi4_lite_spi.sv</spirit:name>
|
||||
<spirit:fileType>systemVerilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
@@ -1006,6 +1088,14 @@
|
||||
<spirit:fileType>systemVerilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_verilogsimulationwrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>sim/system_top_axi4_lite_spi_0_1.sv</spirit:name>
|
||||
<spirit:fileType>systemVerilogSource</spirit:fileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_verilogsynthesiswrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
|
||||
+677
@@ -0,0 +1,677 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
#include "system_top_axi_bram_ctrl_0_0_sc.h"
|
||||
|
||||
#include "system_top_axi_bram_ctrl_0_0.h"
|
||||
|
||||
#include "axi_bram_ctrl.h"
|
||||
|
||||
#include <map>
|
||||
#include <string>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef XILINX_SIMULATOR
|
||||
system_top_axi_bram_ctrl_0_0::system_top_axi_bram_ctrl_0_0(const sc_core::sc_module_name& nm) : system_top_axi_bram_ctrl_0_0_sc(nm), s_axi_aclk("s_axi_aclk"), s_axi_aresetn("s_axi_aresetn"), s_axi_awaddr("s_axi_awaddr"), s_axi_awlen("s_axi_awlen"), s_axi_awsize("s_axi_awsize"), s_axi_awburst("s_axi_awburst"), s_axi_awlock("s_axi_awlock"), s_axi_awcache("s_axi_awcache"), s_axi_awprot("s_axi_awprot"), s_axi_awvalid("s_axi_awvalid"), s_axi_awready("s_axi_awready"), s_axi_wdata("s_axi_wdata"), s_axi_wstrb("s_axi_wstrb"), s_axi_wlast("s_axi_wlast"), s_axi_wvalid("s_axi_wvalid"), s_axi_wready("s_axi_wready"), s_axi_bresp("s_axi_bresp"), s_axi_bvalid("s_axi_bvalid"), s_axi_bready("s_axi_bready"), s_axi_araddr("s_axi_araddr"), s_axi_arlen("s_axi_arlen"), s_axi_arsize("s_axi_arsize"), s_axi_arburst("s_axi_arburst"), s_axi_arlock("s_axi_arlock"), s_axi_arcache("s_axi_arcache"), s_axi_arprot("s_axi_arprot"), s_axi_arvalid("s_axi_arvalid"), s_axi_arready("s_axi_arready"), s_axi_rdata("s_axi_rdata"), s_axi_rresp("s_axi_rresp"), s_axi_rlast("s_axi_rlast"), s_axi_rvalid("s_axi_rvalid"), s_axi_rready("s_axi_rready"), bram_rst_a("bram_rst_a"), bram_clk_a("bram_clk_a"), bram_en_a("bram_en_a"), bram_we_a("bram_we_a"), bram_addr_a("bram_addr_a"), bram_wrdata_a("bram_wrdata_a"), bram_rddata_a("bram_rddata_a")
|
||||
{
|
||||
|
||||
// initialize pins
|
||||
mp_impl->s_axi_aclk(s_axi_aclk);
|
||||
mp_impl->s_axi_aresetn(s_axi_aresetn);
|
||||
mp_impl->bram_rst_a(bram_rst_a);
|
||||
mp_impl->bram_clk_a(bram_clk_a);
|
||||
mp_impl->bram_en_a(bram_en_a);
|
||||
mp_impl->bram_we_a(bram_we_a);
|
||||
mp_impl->bram_addr_a(bram_addr_a);
|
||||
mp_impl->bram_wrdata_a(bram_wrdata_a);
|
||||
mp_impl->bram_rddata_a(bram_rddata_a);
|
||||
|
||||
// initialize transactors
|
||||
mp_S_AXI_transactor = NULL;
|
||||
|
||||
// initialize socket stubs
|
||||
|
||||
}
|
||||
|
||||
void system_top_axi_bram_ctrl_0_0::before_end_of_elaboration()
|
||||
{
|
||||
// configure 'S_AXI' transactor
|
||||
|
||||
if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("system_top_axi_bram_ctrl_0_0", "S_AXI_TLM_MODE") != 1)
|
||||
{
|
||||
// Instantiate Socket Stubs
|
||||
|
||||
// 'S_AXI' transactor parameters
|
||||
xsc::common_cpp::properties S_AXI_transactor_param_props;
|
||||
S_AXI_transactor_param_props.addLong("DATA_WIDTH", "32");
|
||||
S_AXI_transactor_param_props.addLong("FREQ_HZ", "1e+08");
|
||||
S_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("ADDR_WIDTH", "15");
|
||||
S_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_BURST", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_PROT", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_QOS", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_REGION", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
|
||||
S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
|
||||
S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
|
||||
S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
|
||||
S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "16");
|
||||
S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
|
||||
S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
|
||||
S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
|
||||
S_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_RESET", "1");
|
||||
S_AXI_transactor_param_props.addFloat("PHASE", "0.000");
|
||||
S_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
|
||||
S_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
|
||||
S_AXI_transactor_param_props.addString("CLK_DOMAIN", "system_top_processing_system7_0_0_FCLK_CLK0");
|
||||
|
||||
mp_S_AXI_transactor = new xtlm::xaximm_pin2xtlm_t<32,15,1,1,1,1,1,1>("S_AXI_transactor", S_AXI_transactor_param_props);
|
||||
|
||||
// S_AXI' transactor ports
|
||||
|
||||
mp_S_AXI_transactor->ARADDR(s_axi_araddr);
|
||||
mp_S_AXI_transactor->ARBURST(s_axi_arburst);
|
||||
mp_S_AXI_transactor->ARCACHE(s_axi_arcache);
|
||||
mp_S_AXI_transactor->ARLEN(s_axi_arlen);
|
||||
mp_S_AXI_transactor->ARLOCK(s_axi_arlock);
|
||||
mp_S_AXI_transactor->ARPROT(s_axi_arprot);
|
||||
mp_S_AXI_transactor->ARREADY(s_axi_arready);
|
||||
mp_S_AXI_transactor->ARSIZE(s_axi_arsize);
|
||||
mp_S_AXI_transactor->ARVALID(s_axi_arvalid);
|
||||
mp_S_AXI_transactor->AWADDR(s_axi_awaddr);
|
||||
mp_S_AXI_transactor->AWBURST(s_axi_awburst);
|
||||
mp_S_AXI_transactor->AWCACHE(s_axi_awcache);
|
||||
mp_S_AXI_transactor->AWLEN(s_axi_awlen);
|
||||
mp_S_AXI_transactor->AWLOCK(s_axi_awlock);
|
||||
mp_S_AXI_transactor->AWPROT(s_axi_awprot);
|
||||
mp_S_AXI_transactor->AWREADY(s_axi_awready);
|
||||
mp_S_AXI_transactor->AWSIZE(s_axi_awsize);
|
||||
mp_S_AXI_transactor->AWVALID(s_axi_awvalid);
|
||||
mp_S_AXI_transactor->BREADY(s_axi_bready);
|
||||
mp_S_AXI_transactor->BRESP(s_axi_bresp);
|
||||
mp_S_AXI_transactor->BVALID(s_axi_bvalid);
|
||||
mp_S_AXI_transactor->RDATA(s_axi_rdata);
|
||||
mp_S_AXI_transactor->RLAST(s_axi_rlast);
|
||||
mp_S_AXI_transactor->RREADY(s_axi_rready);
|
||||
mp_S_AXI_transactor->RRESP(s_axi_rresp);
|
||||
mp_S_AXI_transactor->RVALID(s_axi_rvalid);
|
||||
mp_S_AXI_transactor->WDATA(s_axi_wdata);
|
||||
mp_S_AXI_transactor->WLAST(s_axi_wlast);
|
||||
mp_S_AXI_transactor->WREADY(s_axi_wready);
|
||||
mp_S_AXI_transactor->WSTRB(s_axi_wstrb);
|
||||
mp_S_AXI_transactor->WVALID(s_axi_wvalid);
|
||||
mp_S_AXI_transactor->CLK(s_axi_aclk);
|
||||
mp_S_AXI_transactor->RST(s_axi_aresetn);
|
||||
|
||||
// S_AXI' transactor sockets
|
||||
|
||||
mp_impl->target_0_rd_socket->bind(*(mp_S_AXI_transactor->rd_socket));
|
||||
mp_impl->target_0_wr_socket->bind(*(mp_S_AXI_transactor->wr_socket));
|
||||
}
|
||||
else
|
||||
{
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
#endif // XILINX_SIMULATOR
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef XM_SYSTEMC
|
||||
system_top_axi_bram_ctrl_0_0::system_top_axi_bram_ctrl_0_0(const sc_core::sc_module_name& nm) : system_top_axi_bram_ctrl_0_0_sc(nm), s_axi_aclk("s_axi_aclk"), s_axi_aresetn("s_axi_aresetn"), s_axi_awaddr("s_axi_awaddr"), s_axi_awlen("s_axi_awlen"), s_axi_awsize("s_axi_awsize"), s_axi_awburst("s_axi_awburst"), s_axi_awlock("s_axi_awlock"), s_axi_awcache("s_axi_awcache"), s_axi_awprot("s_axi_awprot"), s_axi_awvalid("s_axi_awvalid"), s_axi_awready("s_axi_awready"), s_axi_wdata("s_axi_wdata"), s_axi_wstrb("s_axi_wstrb"), s_axi_wlast("s_axi_wlast"), s_axi_wvalid("s_axi_wvalid"), s_axi_wready("s_axi_wready"), s_axi_bresp("s_axi_bresp"), s_axi_bvalid("s_axi_bvalid"), s_axi_bready("s_axi_bready"), s_axi_araddr("s_axi_araddr"), s_axi_arlen("s_axi_arlen"), s_axi_arsize("s_axi_arsize"), s_axi_arburst("s_axi_arburst"), s_axi_arlock("s_axi_arlock"), s_axi_arcache("s_axi_arcache"), s_axi_arprot("s_axi_arprot"), s_axi_arvalid("s_axi_arvalid"), s_axi_arready("s_axi_arready"), s_axi_rdata("s_axi_rdata"), s_axi_rresp("s_axi_rresp"), s_axi_rlast("s_axi_rlast"), s_axi_rvalid("s_axi_rvalid"), s_axi_rready("s_axi_rready"), bram_rst_a("bram_rst_a"), bram_clk_a("bram_clk_a"), bram_en_a("bram_en_a"), bram_we_a("bram_we_a"), bram_addr_a("bram_addr_a"), bram_wrdata_a("bram_wrdata_a"), bram_rddata_a("bram_rddata_a")
|
||||
{
|
||||
|
||||
// initialize pins
|
||||
mp_impl->s_axi_aclk(s_axi_aclk);
|
||||
mp_impl->s_axi_aresetn(s_axi_aresetn);
|
||||
mp_impl->bram_rst_a(bram_rst_a);
|
||||
mp_impl->bram_clk_a(bram_clk_a);
|
||||
mp_impl->bram_en_a(bram_en_a);
|
||||
mp_impl->bram_we_a(bram_we_a);
|
||||
mp_impl->bram_addr_a(bram_addr_a);
|
||||
mp_impl->bram_wrdata_a(bram_wrdata_a);
|
||||
mp_impl->bram_rddata_a(bram_rddata_a);
|
||||
|
||||
// initialize transactors
|
||||
mp_S_AXI_transactor = NULL;
|
||||
|
||||
// initialize socket stubs
|
||||
|
||||
}
|
||||
|
||||
void system_top_axi_bram_ctrl_0_0::before_end_of_elaboration()
|
||||
{
|
||||
// configure 'S_AXI' transactor
|
||||
|
||||
if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("system_top_axi_bram_ctrl_0_0", "S_AXI_TLM_MODE") != 1)
|
||||
{
|
||||
// Instantiate Socket Stubs
|
||||
|
||||
// 'S_AXI' transactor parameters
|
||||
xsc::common_cpp::properties S_AXI_transactor_param_props;
|
||||
S_AXI_transactor_param_props.addLong("DATA_WIDTH", "32");
|
||||
S_AXI_transactor_param_props.addLong("FREQ_HZ", "1e+08");
|
||||
S_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("ADDR_WIDTH", "15");
|
||||
S_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_BURST", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_PROT", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_QOS", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_REGION", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
|
||||
S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
|
||||
S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
|
||||
S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
|
||||
S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "16");
|
||||
S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
|
||||
S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
|
||||
S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
|
||||
S_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_RESET", "1");
|
||||
S_AXI_transactor_param_props.addFloat("PHASE", "0.000");
|
||||
S_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
|
||||
S_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
|
||||
S_AXI_transactor_param_props.addString("CLK_DOMAIN", "system_top_processing_system7_0_0_FCLK_CLK0");
|
||||
|
||||
mp_S_AXI_transactor = new xtlm::xaximm_pin2xtlm_t<32,15,1,1,1,1,1,1>("S_AXI_transactor", S_AXI_transactor_param_props);
|
||||
|
||||
// S_AXI' transactor ports
|
||||
|
||||
mp_S_AXI_transactor->ARADDR(s_axi_araddr);
|
||||
mp_S_AXI_transactor->ARBURST(s_axi_arburst);
|
||||
mp_S_AXI_transactor->ARCACHE(s_axi_arcache);
|
||||
mp_S_AXI_transactor->ARLEN(s_axi_arlen);
|
||||
mp_S_AXI_transactor->ARLOCK(s_axi_arlock);
|
||||
mp_S_AXI_transactor->ARPROT(s_axi_arprot);
|
||||
mp_S_AXI_transactor->ARREADY(s_axi_arready);
|
||||
mp_S_AXI_transactor->ARSIZE(s_axi_arsize);
|
||||
mp_S_AXI_transactor->ARVALID(s_axi_arvalid);
|
||||
mp_S_AXI_transactor->AWADDR(s_axi_awaddr);
|
||||
mp_S_AXI_transactor->AWBURST(s_axi_awburst);
|
||||
mp_S_AXI_transactor->AWCACHE(s_axi_awcache);
|
||||
mp_S_AXI_transactor->AWLEN(s_axi_awlen);
|
||||
mp_S_AXI_transactor->AWLOCK(s_axi_awlock);
|
||||
mp_S_AXI_transactor->AWPROT(s_axi_awprot);
|
||||
mp_S_AXI_transactor->AWREADY(s_axi_awready);
|
||||
mp_S_AXI_transactor->AWSIZE(s_axi_awsize);
|
||||
mp_S_AXI_transactor->AWVALID(s_axi_awvalid);
|
||||
mp_S_AXI_transactor->BREADY(s_axi_bready);
|
||||
mp_S_AXI_transactor->BRESP(s_axi_bresp);
|
||||
mp_S_AXI_transactor->BVALID(s_axi_bvalid);
|
||||
mp_S_AXI_transactor->RDATA(s_axi_rdata);
|
||||
mp_S_AXI_transactor->RLAST(s_axi_rlast);
|
||||
mp_S_AXI_transactor->RREADY(s_axi_rready);
|
||||
mp_S_AXI_transactor->RRESP(s_axi_rresp);
|
||||
mp_S_AXI_transactor->RVALID(s_axi_rvalid);
|
||||
mp_S_AXI_transactor->WDATA(s_axi_wdata);
|
||||
mp_S_AXI_transactor->WLAST(s_axi_wlast);
|
||||
mp_S_AXI_transactor->WREADY(s_axi_wready);
|
||||
mp_S_AXI_transactor->WSTRB(s_axi_wstrb);
|
||||
mp_S_AXI_transactor->WVALID(s_axi_wvalid);
|
||||
mp_S_AXI_transactor->CLK(s_axi_aclk);
|
||||
mp_S_AXI_transactor->RST(s_axi_aresetn);
|
||||
|
||||
// S_AXI' transactor sockets
|
||||
|
||||
mp_impl->target_0_rd_socket->bind(*(mp_S_AXI_transactor->rd_socket));
|
||||
mp_impl->target_0_wr_socket->bind(*(mp_S_AXI_transactor->wr_socket));
|
||||
}
|
||||
else
|
||||
{
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
#endif // XM_SYSTEMC
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef RIVIERA
|
||||
system_top_axi_bram_ctrl_0_0::system_top_axi_bram_ctrl_0_0(const sc_core::sc_module_name& nm) : system_top_axi_bram_ctrl_0_0_sc(nm), s_axi_aclk("s_axi_aclk"), s_axi_aresetn("s_axi_aresetn"), s_axi_awaddr("s_axi_awaddr"), s_axi_awlen("s_axi_awlen"), s_axi_awsize("s_axi_awsize"), s_axi_awburst("s_axi_awburst"), s_axi_awlock("s_axi_awlock"), s_axi_awcache("s_axi_awcache"), s_axi_awprot("s_axi_awprot"), s_axi_awvalid("s_axi_awvalid"), s_axi_awready("s_axi_awready"), s_axi_wdata("s_axi_wdata"), s_axi_wstrb("s_axi_wstrb"), s_axi_wlast("s_axi_wlast"), s_axi_wvalid("s_axi_wvalid"), s_axi_wready("s_axi_wready"), s_axi_bresp("s_axi_bresp"), s_axi_bvalid("s_axi_bvalid"), s_axi_bready("s_axi_bready"), s_axi_araddr("s_axi_araddr"), s_axi_arlen("s_axi_arlen"), s_axi_arsize("s_axi_arsize"), s_axi_arburst("s_axi_arburst"), s_axi_arlock("s_axi_arlock"), s_axi_arcache("s_axi_arcache"), s_axi_arprot("s_axi_arprot"), s_axi_arvalid("s_axi_arvalid"), s_axi_arready("s_axi_arready"), s_axi_rdata("s_axi_rdata"), s_axi_rresp("s_axi_rresp"), s_axi_rlast("s_axi_rlast"), s_axi_rvalid("s_axi_rvalid"), s_axi_rready("s_axi_rready"), bram_rst_a("bram_rst_a"), bram_clk_a("bram_clk_a"), bram_en_a("bram_en_a"), bram_we_a("bram_we_a"), bram_addr_a("bram_addr_a"), bram_wrdata_a("bram_wrdata_a"), bram_rddata_a("bram_rddata_a")
|
||||
{
|
||||
|
||||
// initialize pins
|
||||
mp_impl->s_axi_aclk(s_axi_aclk);
|
||||
mp_impl->s_axi_aresetn(s_axi_aresetn);
|
||||
mp_impl->bram_rst_a(bram_rst_a);
|
||||
mp_impl->bram_clk_a(bram_clk_a);
|
||||
mp_impl->bram_en_a(bram_en_a);
|
||||
mp_impl->bram_we_a(bram_we_a);
|
||||
mp_impl->bram_addr_a(bram_addr_a);
|
||||
mp_impl->bram_wrdata_a(bram_wrdata_a);
|
||||
mp_impl->bram_rddata_a(bram_rddata_a);
|
||||
|
||||
// initialize transactors
|
||||
mp_S_AXI_transactor = NULL;
|
||||
|
||||
// initialize socket stubs
|
||||
|
||||
}
|
||||
|
||||
void system_top_axi_bram_ctrl_0_0::before_end_of_elaboration()
|
||||
{
|
||||
// configure 'S_AXI' transactor
|
||||
|
||||
if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("system_top_axi_bram_ctrl_0_0", "S_AXI_TLM_MODE") != 1)
|
||||
{
|
||||
// Instantiate Socket Stubs
|
||||
|
||||
// 'S_AXI' transactor parameters
|
||||
xsc::common_cpp::properties S_AXI_transactor_param_props;
|
||||
S_AXI_transactor_param_props.addLong("DATA_WIDTH", "32");
|
||||
S_AXI_transactor_param_props.addLong("FREQ_HZ", "1e+08");
|
||||
S_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("ADDR_WIDTH", "15");
|
||||
S_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_BURST", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_PROT", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_QOS", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_REGION", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
|
||||
S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
|
||||
S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
|
||||
S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
|
||||
S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "16");
|
||||
S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
|
||||
S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
|
||||
S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
|
||||
S_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_RESET", "1");
|
||||
S_AXI_transactor_param_props.addFloat("PHASE", "0.000");
|
||||
S_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
|
||||
S_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
|
||||
S_AXI_transactor_param_props.addString("CLK_DOMAIN", "system_top_processing_system7_0_0_FCLK_CLK0");
|
||||
|
||||
mp_S_AXI_transactor = new xtlm::xaximm_pin2xtlm_t<32,15,1,1,1,1,1,1>("S_AXI_transactor", S_AXI_transactor_param_props);
|
||||
|
||||
// S_AXI' transactor ports
|
||||
|
||||
mp_S_AXI_transactor->ARADDR(s_axi_araddr);
|
||||
mp_S_AXI_transactor->ARBURST(s_axi_arburst);
|
||||
mp_S_AXI_transactor->ARCACHE(s_axi_arcache);
|
||||
mp_S_AXI_transactor->ARLEN(s_axi_arlen);
|
||||
mp_S_AXI_transactor->ARLOCK(s_axi_arlock);
|
||||
mp_S_AXI_transactor->ARPROT(s_axi_arprot);
|
||||
mp_S_AXI_transactor->ARREADY(s_axi_arready);
|
||||
mp_S_AXI_transactor->ARSIZE(s_axi_arsize);
|
||||
mp_S_AXI_transactor->ARVALID(s_axi_arvalid);
|
||||
mp_S_AXI_transactor->AWADDR(s_axi_awaddr);
|
||||
mp_S_AXI_transactor->AWBURST(s_axi_awburst);
|
||||
mp_S_AXI_transactor->AWCACHE(s_axi_awcache);
|
||||
mp_S_AXI_transactor->AWLEN(s_axi_awlen);
|
||||
mp_S_AXI_transactor->AWLOCK(s_axi_awlock);
|
||||
mp_S_AXI_transactor->AWPROT(s_axi_awprot);
|
||||
mp_S_AXI_transactor->AWREADY(s_axi_awready);
|
||||
mp_S_AXI_transactor->AWSIZE(s_axi_awsize);
|
||||
mp_S_AXI_transactor->AWVALID(s_axi_awvalid);
|
||||
mp_S_AXI_transactor->BREADY(s_axi_bready);
|
||||
mp_S_AXI_transactor->BRESP(s_axi_bresp);
|
||||
mp_S_AXI_transactor->BVALID(s_axi_bvalid);
|
||||
mp_S_AXI_transactor->RDATA(s_axi_rdata);
|
||||
mp_S_AXI_transactor->RLAST(s_axi_rlast);
|
||||
mp_S_AXI_transactor->RREADY(s_axi_rready);
|
||||
mp_S_AXI_transactor->RRESP(s_axi_rresp);
|
||||
mp_S_AXI_transactor->RVALID(s_axi_rvalid);
|
||||
mp_S_AXI_transactor->WDATA(s_axi_wdata);
|
||||
mp_S_AXI_transactor->WLAST(s_axi_wlast);
|
||||
mp_S_AXI_transactor->WREADY(s_axi_wready);
|
||||
mp_S_AXI_transactor->WSTRB(s_axi_wstrb);
|
||||
mp_S_AXI_transactor->WVALID(s_axi_wvalid);
|
||||
mp_S_AXI_transactor->CLK(s_axi_aclk);
|
||||
mp_S_AXI_transactor->RST(s_axi_aresetn);
|
||||
|
||||
// S_AXI' transactor sockets
|
||||
|
||||
mp_impl->target_0_rd_socket->bind(*(mp_S_AXI_transactor->rd_socket));
|
||||
mp_impl->target_0_wr_socket->bind(*(mp_S_AXI_transactor->wr_socket));
|
||||
}
|
||||
else
|
||||
{
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
#endif // RIVIERA
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef VCSSYSTEMC
|
||||
system_top_axi_bram_ctrl_0_0::system_top_axi_bram_ctrl_0_0(const sc_core::sc_module_name& nm) : system_top_axi_bram_ctrl_0_0_sc(nm), s_axi_aclk("s_axi_aclk"), s_axi_aresetn("s_axi_aresetn"), s_axi_awaddr("s_axi_awaddr"), s_axi_awlen("s_axi_awlen"), s_axi_awsize("s_axi_awsize"), s_axi_awburst("s_axi_awburst"), s_axi_awlock("s_axi_awlock"), s_axi_awcache("s_axi_awcache"), s_axi_awprot("s_axi_awprot"), s_axi_awvalid("s_axi_awvalid"), s_axi_awready("s_axi_awready"), s_axi_wdata("s_axi_wdata"), s_axi_wstrb("s_axi_wstrb"), s_axi_wlast("s_axi_wlast"), s_axi_wvalid("s_axi_wvalid"), s_axi_wready("s_axi_wready"), s_axi_bresp("s_axi_bresp"), s_axi_bvalid("s_axi_bvalid"), s_axi_bready("s_axi_bready"), s_axi_araddr("s_axi_araddr"), s_axi_arlen("s_axi_arlen"), s_axi_arsize("s_axi_arsize"), s_axi_arburst("s_axi_arburst"), s_axi_arlock("s_axi_arlock"), s_axi_arcache("s_axi_arcache"), s_axi_arprot("s_axi_arprot"), s_axi_arvalid("s_axi_arvalid"), s_axi_arready("s_axi_arready"), s_axi_rdata("s_axi_rdata"), s_axi_rresp("s_axi_rresp"), s_axi_rlast("s_axi_rlast"), s_axi_rvalid("s_axi_rvalid"), s_axi_rready("s_axi_rready"), bram_rst_a("bram_rst_a"), bram_clk_a("bram_clk_a"), bram_en_a("bram_en_a"), bram_we_a("bram_we_a"), bram_addr_a("bram_addr_a"), bram_wrdata_a("bram_wrdata_a"), bram_rddata_a("bram_rddata_a")
|
||||
{
|
||||
// initialize pins
|
||||
mp_impl->s_axi_aclk(s_axi_aclk);
|
||||
mp_impl->s_axi_aresetn(s_axi_aresetn);
|
||||
mp_impl->bram_rst_a(bram_rst_a);
|
||||
mp_impl->bram_clk_a(bram_clk_a);
|
||||
mp_impl->bram_en_a(bram_en_a);
|
||||
mp_impl->bram_we_a(bram_we_a);
|
||||
mp_impl->bram_addr_a(bram_addr_a);
|
||||
mp_impl->bram_wrdata_a(bram_wrdata_a);
|
||||
mp_impl->bram_rddata_a(bram_rddata_a);
|
||||
|
||||
// initialize transactors
|
||||
mp_S_AXI_transactor = NULL;
|
||||
|
||||
// Instantiate Socket Stubs
|
||||
|
||||
// configure S_AXI_transactor
|
||||
xsc::common_cpp::properties S_AXI_transactor_param_props;
|
||||
S_AXI_transactor_param_props.addLong("DATA_WIDTH", "32");
|
||||
S_AXI_transactor_param_props.addLong("FREQ_HZ", "1e+08");
|
||||
S_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("ADDR_WIDTH", "15");
|
||||
S_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_BURST", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_PROT", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_QOS", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_REGION", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
|
||||
S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
|
||||
S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
|
||||
S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
|
||||
S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "16");
|
||||
S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
|
||||
S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
|
||||
S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
|
||||
S_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_RESET", "1");
|
||||
S_AXI_transactor_param_props.addFloat("PHASE", "0.000");
|
||||
S_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
|
||||
S_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
|
||||
S_AXI_transactor_param_props.addString("CLK_DOMAIN", "system_top_processing_system7_0_0_FCLK_CLK0");
|
||||
|
||||
mp_S_AXI_transactor = new xtlm::xaximm_pin2xtlm_t<32,15,1,1,1,1,1,1>("S_AXI_transactor", S_AXI_transactor_param_props);
|
||||
mp_S_AXI_transactor->ARADDR(s_axi_araddr);
|
||||
mp_S_AXI_transactor->ARBURST(s_axi_arburst);
|
||||
mp_S_AXI_transactor->ARCACHE(s_axi_arcache);
|
||||
mp_S_AXI_transactor->ARLEN(s_axi_arlen);
|
||||
mp_S_AXI_transactor->ARLOCK(s_axi_arlock);
|
||||
mp_S_AXI_transactor->ARPROT(s_axi_arprot);
|
||||
mp_S_AXI_transactor->ARREADY(s_axi_arready);
|
||||
mp_S_AXI_transactor->ARSIZE(s_axi_arsize);
|
||||
mp_S_AXI_transactor->ARVALID(s_axi_arvalid);
|
||||
mp_S_AXI_transactor->AWADDR(s_axi_awaddr);
|
||||
mp_S_AXI_transactor->AWBURST(s_axi_awburst);
|
||||
mp_S_AXI_transactor->AWCACHE(s_axi_awcache);
|
||||
mp_S_AXI_transactor->AWLEN(s_axi_awlen);
|
||||
mp_S_AXI_transactor->AWLOCK(s_axi_awlock);
|
||||
mp_S_AXI_transactor->AWPROT(s_axi_awprot);
|
||||
mp_S_AXI_transactor->AWREADY(s_axi_awready);
|
||||
mp_S_AXI_transactor->AWSIZE(s_axi_awsize);
|
||||
mp_S_AXI_transactor->AWVALID(s_axi_awvalid);
|
||||
mp_S_AXI_transactor->BREADY(s_axi_bready);
|
||||
mp_S_AXI_transactor->BRESP(s_axi_bresp);
|
||||
mp_S_AXI_transactor->BVALID(s_axi_bvalid);
|
||||
mp_S_AXI_transactor->RDATA(s_axi_rdata);
|
||||
mp_S_AXI_transactor->RLAST(s_axi_rlast);
|
||||
mp_S_AXI_transactor->RREADY(s_axi_rready);
|
||||
mp_S_AXI_transactor->RRESP(s_axi_rresp);
|
||||
mp_S_AXI_transactor->RVALID(s_axi_rvalid);
|
||||
mp_S_AXI_transactor->WDATA(s_axi_wdata);
|
||||
mp_S_AXI_transactor->WLAST(s_axi_wlast);
|
||||
mp_S_AXI_transactor->WREADY(s_axi_wready);
|
||||
mp_S_AXI_transactor->WSTRB(s_axi_wstrb);
|
||||
mp_S_AXI_transactor->WVALID(s_axi_wvalid);
|
||||
mp_S_AXI_transactor->CLK(s_axi_aclk);
|
||||
mp_S_AXI_transactor->RST(s_axi_aresetn);
|
||||
|
||||
// initialize transactors stubs
|
||||
S_AXI_transactor_target_wr_socket_stub = nullptr;
|
||||
S_AXI_transactor_target_rd_socket_stub = nullptr;
|
||||
|
||||
}
|
||||
|
||||
void system_top_axi_bram_ctrl_0_0::before_end_of_elaboration()
|
||||
{
|
||||
// configure 'S_AXI' transactor
|
||||
if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("system_top_axi_bram_ctrl_0_0", "S_AXI_TLM_MODE") != 1)
|
||||
{
|
||||
mp_impl->target_0_rd_socket->bind(*(mp_S_AXI_transactor->rd_socket));
|
||||
mp_impl->target_0_wr_socket->bind(*(mp_S_AXI_transactor->wr_socket));
|
||||
|
||||
}
|
||||
else
|
||||
{
|
||||
S_AXI_transactor_target_wr_socket_stub = new xtlm::xtlm_aximm_target_stub("wr_socket",0);
|
||||
S_AXI_transactor_target_wr_socket_stub->bind(*(mp_S_AXI_transactor->wr_socket));
|
||||
S_AXI_transactor_target_rd_socket_stub = new xtlm::xtlm_aximm_target_stub("rd_socket",0);
|
||||
S_AXI_transactor_target_rd_socket_stub->bind(*(mp_S_AXI_transactor->rd_socket));
|
||||
mp_S_AXI_transactor->disable_transactor();
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
#endif // VCSSYSTEMC
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef MTI_SYSTEMC
|
||||
system_top_axi_bram_ctrl_0_0::system_top_axi_bram_ctrl_0_0(const sc_core::sc_module_name& nm) : system_top_axi_bram_ctrl_0_0_sc(nm), s_axi_aclk("s_axi_aclk"), s_axi_aresetn("s_axi_aresetn"), s_axi_awaddr("s_axi_awaddr"), s_axi_awlen("s_axi_awlen"), s_axi_awsize("s_axi_awsize"), s_axi_awburst("s_axi_awburst"), s_axi_awlock("s_axi_awlock"), s_axi_awcache("s_axi_awcache"), s_axi_awprot("s_axi_awprot"), s_axi_awvalid("s_axi_awvalid"), s_axi_awready("s_axi_awready"), s_axi_wdata("s_axi_wdata"), s_axi_wstrb("s_axi_wstrb"), s_axi_wlast("s_axi_wlast"), s_axi_wvalid("s_axi_wvalid"), s_axi_wready("s_axi_wready"), s_axi_bresp("s_axi_bresp"), s_axi_bvalid("s_axi_bvalid"), s_axi_bready("s_axi_bready"), s_axi_araddr("s_axi_araddr"), s_axi_arlen("s_axi_arlen"), s_axi_arsize("s_axi_arsize"), s_axi_arburst("s_axi_arburst"), s_axi_arlock("s_axi_arlock"), s_axi_arcache("s_axi_arcache"), s_axi_arprot("s_axi_arprot"), s_axi_arvalid("s_axi_arvalid"), s_axi_arready("s_axi_arready"), s_axi_rdata("s_axi_rdata"), s_axi_rresp("s_axi_rresp"), s_axi_rlast("s_axi_rlast"), s_axi_rvalid("s_axi_rvalid"), s_axi_rready("s_axi_rready"), bram_rst_a("bram_rst_a"), bram_clk_a("bram_clk_a"), bram_en_a("bram_en_a"), bram_we_a("bram_we_a"), bram_addr_a("bram_addr_a"), bram_wrdata_a("bram_wrdata_a"), bram_rddata_a("bram_rddata_a")
|
||||
{
|
||||
// initialize pins
|
||||
mp_impl->s_axi_aclk(s_axi_aclk);
|
||||
mp_impl->s_axi_aresetn(s_axi_aresetn);
|
||||
mp_impl->bram_rst_a(bram_rst_a);
|
||||
mp_impl->bram_clk_a(bram_clk_a);
|
||||
mp_impl->bram_en_a(bram_en_a);
|
||||
mp_impl->bram_we_a(bram_we_a);
|
||||
mp_impl->bram_addr_a(bram_addr_a);
|
||||
mp_impl->bram_wrdata_a(bram_wrdata_a);
|
||||
mp_impl->bram_rddata_a(bram_rddata_a);
|
||||
|
||||
// initialize transactors
|
||||
mp_S_AXI_transactor = NULL;
|
||||
|
||||
// Instantiate Socket Stubs
|
||||
|
||||
// configure S_AXI_transactor
|
||||
xsc::common_cpp::properties S_AXI_transactor_param_props;
|
||||
S_AXI_transactor_param_props.addLong("DATA_WIDTH", "32");
|
||||
S_AXI_transactor_param_props.addLong("FREQ_HZ", "1e+08");
|
||||
S_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("ADDR_WIDTH", "15");
|
||||
S_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_BURST", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_PROT", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_QOS", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_REGION", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
|
||||
S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
|
||||
S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
|
||||
S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
|
||||
S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "16");
|
||||
S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
|
||||
S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
|
||||
S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
|
||||
S_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_RESET", "1");
|
||||
S_AXI_transactor_param_props.addFloat("PHASE", "0.000");
|
||||
S_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
|
||||
S_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
|
||||
S_AXI_transactor_param_props.addString("CLK_DOMAIN", "system_top_processing_system7_0_0_FCLK_CLK0");
|
||||
|
||||
mp_S_AXI_transactor = new xtlm::xaximm_pin2xtlm_t<32,15,1,1,1,1,1,1>("S_AXI_transactor", S_AXI_transactor_param_props);
|
||||
mp_S_AXI_transactor->ARADDR(s_axi_araddr);
|
||||
mp_S_AXI_transactor->ARBURST(s_axi_arburst);
|
||||
mp_S_AXI_transactor->ARCACHE(s_axi_arcache);
|
||||
mp_S_AXI_transactor->ARLEN(s_axi_arlen);
|
||||
mp_S_AXI_transactor->ARLOCK(s_axi_arlock);
|
||||
mp_S_AXI_transactor->ARPROT(s_axi_arprot);
|
||||
mp_S_AXI_transactor->ARREADY(s_axi_arready);
|
||||
mp_S_AXI_transactor->ARSIZE(s_axi_arsize);
|
||||
mp_S_AXI_transactor->ARVALID(s_axi_arvalid);
|
||||
mp_S_AXI_transactor->AWADDR(s_axi_awaddr);
|
||||
mp_S_AXI_transactor->AWBURST(s_axi_awburst);
|
||||
mp_S_AXI_transactor->AWCACHE(s_axi_awcache);
|
||||
mp_S_AXI_transactor->AWLEN(s_axi_awlen);
|
||||
mp_S_AXI_transactor->AWLOCK(s_axi_awlock);
|
||||
mp_S_AXI_transactor->AWPROT(s_axi_awprot);
|
||||
mp_S_AXI_transactor->AWREADY(s_axi_awready);
|
||||
mp_S_AXI_transactor->AWSIZE(s_axi_awsize);
|
||||
mp_S_AXI_transactor->AWVALID(s_axi_awvalid);
|
||||
mp_S_AXI_transactor->BREADY(s_axi_bready);
|
||||
mp_S_AXI_transactor->BRESP(s_axi_bresp);
|
||||
mp_S_AXI_transactor->BVALID(s_axi_bvalid);
|
||||
mp_S_AXI_transactor->RDATA(s_axi_rdata);
|
||||
mp_S_AXI_transactor->RLAST(s_axi_rlast);
|
||||
mp_S_AXI_transactor->RREADY(s_axi_rready);
|
||||
mp_S_AXI_transactor->RRESP(s_axi_rresp);
|
||||
mp_S_AXI_transactor->RVALID(s_axi_rvalid);
|
||||
mp_S_AXI_transactor->WDATA(s_axi_wdata);
|
||||
mp_S_AXI_transactor->WLAST(s_axi_wlast);
|
||||
mp_S_AXI_transactor->WREADY(s_axi_wready);
|
||||
mp_S_AXI_transactor->WSTRB(s_axi_wstrb);
|
||||
mp_S_AXI_transactor->WVALID(s_axi_wvalid);
|
||||
mp_S_AXI_transactor->CLK(s_axi_aclk);
|
||||
mp_S_AXI_transactor->RST(s_axi_aresetn);
|
||||
|
||||
// initialize transactors stubs
|
||||
S_AXI_transactor_target_wr_socket_stub = nullptr;
|
||||
S_AXI_transactor_target_rd_socket_stub = nullptr;
|
||||
|
||||
}
|
||||
|
||||
void system_top_axi_bram_ctrl_0_0::before_end_of_elaboration()
|
||||
{
|
||||
// configure 'S_AXI' transactor
|
||||
if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("system_top_axi_bram_ctrl_0_0", "S_AXI_TLM_MODE") != 1)
|
||||
{
|
||||
mp_impl->target_0_rd_socket->bind(*(mp_S_AXI_transactor->rd_socket));
|
||||
mp_impl->target_0_wr_socket->bind(*(mp_S_AXI_transactor->wr_socket));
|
||||
|
||||
}
|
||||
else
|
||||
{
|
||||
S_AXI_transactor_target_wr_socket_stub = new xtlm::xtlm_aximm_target_stub("wr_socket",0);
|
||||
S_AXI_transactor_target_wr_socket_stub->bind(*(mp_S_AXI_transactor->wr_socket));
|
||||
S_AXI_transactor_target_rd_socket_stub = new xtlm::xtlm_aximm_target_stub("rd_socket",0);
|
||||
S_AXI_transactor_target_rd_socket_stub->bind(*(mp_S_AXI_transactor->rd_socket));
|
||||
mp_S_AXI_transactor->disable_transactor();
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
#endif // MTI_SYSTEMC
|
||||
|
||||
|
||||
|
||||
|
||||
system_top_axi_bram_ctrl_0_0::~system_top_axi_bram_ctrl_0_0()
|
||||
{
|
||||
delete mp_S_AXI_transactor;
|
||||
|
||||
}
|
||||
|
||||
#ifdef MTI_SYSTEMC
|
||||
SC_MODULE_EXPORT(system_top_axi_bram_ctrl_0_0);
|
||||
#endif
|
||||
|
||||
#ifdef XM_SYSTEMC
|
||||
XMSC_MODULE_EXPORT(system_top_axi_bram_ctrl_0_0);
|
||||
#endif
|
||||
|
||||
#ifdef RIVIERA
|
||||
SC_MODULE_EXPORT(system_top_axi_bram_ctrl_0_0);
|
||||
#endif
|
||||
|
||||
+425
@@ -0,0 +1,425 @@
|
||||
#ifndef IP_SYSTEM_TOP_AXI_BRAM_CTRL_0_0_H_
|
||||
#define IP_SYSTEM_TOP_AXI_BRAM_CTRL_0_0_H_
|
||||
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
#ifndef XTLM
|
||||
#include "xtlm.h"
|
||||
#endif
|
||||
#ifndef SYSTEMC_INCLUDED
|
||||
#include <systemc>
|
||||
#endif
|
||||
|
||||
#if defined(_MSC_VER)
|
||||
#define DllExport __declspec(dllexport)
|
||||
#elif defined(__GNUC__)
|
||||
#define DllExport __attribute__ ((visibility("default")))
|
||||
#else
|
||||
#define DllExport
|
||||
#endif
|
||||
|
||||
#include "system_top_axi_bram_ctrl_0_0_sc.h"
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef XILINX_SIMULATOR
|
||||
class DllExport system_top_axi_bram_ctrl_0_0 : public system_top_axi_bram_ctrl_0_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
system_top_axi_bram_ctrl_0_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~system_top_axi_bram_ctrl_0_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< bool > s_axi_aclk;
|
||||
sc_core::sc_in< bool > s_axi_aresetn;
|
||||
sc_core::sc_in< sc_dt::sc_bv<15> > s_axi_awaddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||
sc_core::sc_in< bool > s_axi_awlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||
sc_core::sc_in< bool > s_axi_awvalid;
|
||||
sc_core::sc_out< bool > s_axi_awready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
|
||||
sc_core::sc_in< bool > s_axi_wlast;
|
||||
sc_core::sc_in< bool > s_axi_wvalid;
|
||||
sc_core::sc_out< bool > s_axi_wready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||
sc_core::sc_out< bool > s_axi_bvalid;
|
||||
sc_core::sc_in< bool > s_axi_bready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<15> > s_axi_araddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||
sc_core::sc_in< bool > s_axi_arlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||
sc_core::sc_in< bool > s_axi_arvalid;
|
||||
sc_core::sc_out< bool > s_axi_arready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||
sc_core::sc_out< bool > s_axi_rlast;
|
||||
sc_core::sc_out< bool > s_axi_rvalid;
|
||||
sc_core::sc_in< bool > s_axi_rready;
|
||||
sc_core::sc_out< bool > bram_rst_a;
|
||||
sc_core::sc_out< bool > bram_clk_a;
|
||||
sc_core::sc_out< bool > bram_en_a;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > bram_we_a;
|
||||
sc_core::sc_out< sc_dt::sc_bv<15> > bram_addr_a;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > bram_wrdata_a;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > bram_rddata_a;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_pin2xtlm_t<32,15,1,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||
|
||||
};
|
||||
#endif // XILINX_SIMULATOR
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef XM_SYSTEMC
|
||||
class DllExport system_top_axi_bram_ctrl_0_0 : public system_top_axi_bram_ctrl_0_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
system_top_axi_bram_ctrl_0_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~system_top_axi_bram_ctrl_0_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< bool > s_axi_aclk;
|
||||
sc_core::sc_in< bool > s_axi_aresetn;
|
||||
sc_core::sc_in< sc_dt::sc_bv<15> > s_axi_awaddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||
sc_core::sc_in< bool > s_axi_awlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||
sc_core::sc_in< bool > s_axi_awvalid;
|
||||
sc_core::sc_out< bool > s_axi_awready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
|
||||
sc_core::sc_in< bool > s_axi_wlast;
|
||||
sc_core::sc_in< bool > s_axi_wvalid;
|
||||
sc_core::sc_out< bool > s_axi_wready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||
sc_core::sc_out< bool > s_axi_bvalid;
|
||||
sc_core::sc_in< bool > s_axi_bready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<15> > s_axi_araddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||
sc_core::sc_in< bool > s_axi_arlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||
sc_core::sc_in< bool > s_axi_arvalid;
|
||||
sc_core::sc_out< bool > s_axi_arready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||
sc_core::sc_out< bool > s_axi_rlast;
|
||||
sc_core::sc_out< bool > s_axi_rvalid;
|
||||
sc_core::sc_in< bool > s_axi_rready;
|
||||
sc_core::sc_out< bool > bram_rst_a;
|
||||
sc_core::sc_out< bool > bram_clk_a;
|
||||
sc_core::sc_out< bool > bram_en_a;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > bram_we_a;
|
||||
sc_core::sc_out< sc_dt::sc_bv<15> > bram_addr_a;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > bram_wrdata_a;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > bram_rddata_a;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_pin2xtlm_t<32,15,1,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||
|
||||
};
|
||||
#endif // XM_SYSTEMC
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef RIVIERA
|
||||
class DllExport system_top_axi_bram_ctrl_0_0 : public system_top_axi_bram_ctrl_0_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
system_top_axi_bram_ctrl_0_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~system_top_axi_bram_ctrl_0_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< bool > s_axi_aclk;
|
||||
sc_core::sc_in< bool > s_axi_aresetn;
|
||||
sc_core::sc_in< sc_dt::sc_bv<15> > s_axi_awaddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||
sc_core::sc_in< bool > s_axi_awlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||
sc_core::sc_in< bool > s_axi_awvalid;
|
||||
sc_core::sc_out< bool > s_axi_awready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
|
||||
sc_core::sc_in< bool > s_axi_wlast;
|
||||
sc_core::sc_in< bool > s_axi_wvalid;
|
||||
sc_core::sc_out< bool > s_axi_wready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||
sc_core::sc_out< bool > s_axi_bvalid;
|
||||
sc_core::sc_in< bool > s_axi_bready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<15> > s_axi_araddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||
sc_core::sc_in< bool > s_axi_arlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||
sc_core::sc_in< bool > s_axi_arvalid;
|
||||
sc_core::sc_out< bool > s_axi_arready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||
sc_core::sc_out< bool > s_axi_rlast;
|
||||
sc_core::sc_out< bool > s_axi_rvalid;
|
||||
sc_core::sc_in< bool > s_axi_rready;
|
||||
sc_core::sc_out< bool > bram_rst_a;
|
||||
sc_core::sc_out< bool > bram_clk_a;
|
||||
sc_core::sc_out< bool > bram_en_a;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > bram_we_a;
|
||||
sc_core::sc_out< sc_dt::sc_bv<15> > bram_addr_a;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > bram_wrdata_a;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > bram_rddata_a;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_pin2xtlm_t<32,15,1,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||
|
||||
};
|
||||
#endif // RIVIERA
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef VCSSYSTEMC
|
||||
#include "utils/xtlm_aximm_target_stub.h"
|
||||
|
||||
class DllExport system_top_axi_bram_ctrl_0_0 : public system_top_axi_bram_ctrl_0_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
system_top_axi_bram_ctrl_0_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~system_top_axi_bram_ctrl_0_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< bool > s_axi_aclk;
|
||||
sc_core::sc_in< bool > s_axi_aresetn;
|
||||
sc_core::sc_in< sc_dt::sc_bv<15> > s_axi_awaddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||
sc_core::sc_in< bool > s_axi_awlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||
sc_core::sc_in< bool > s_axi_awvalid;
|
||||
sc_core::sc_out< bool > s_axi_awready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
|
||||
sc_core::sc_in< bool > s_axi_wlast;
|
||||
sc_core::sc_in< bool > s_axi_wvalid;
|
||||
sc_core::sc_out< bool > s_axi_wready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||
sc_core::sc_out< bool > s_axi_bvalid;
|
||||
sc_core::sc_in< bool > s_axi_bready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<15> > s_axi_araddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||
sc_core::sc_in< bool > s_axi_arlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||
sc_core::sc_in< bool > s_axi_arvalid;
|
||||
sc_core::sc_out< bool > s_axi_arready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||
sc_core::sc_out< bool > s_axi_rlast;
|
||||
sc_core::sc_out< bool > s_axi_rvalid;
|
||||
sc_core::sc_in< bool > s_axi_rready;
|
||||
sc_core::sc_out< bool > bram_rst_a;
|
||||
sc_core::sc_out< bool > bram_clk_a;
|
||||
sc_core::sc_out< bool > bram_en_a;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > bram_we_a;
|
||||
sc_core::sc_out< sc_dt::sc_bv<15> > bram_addr_a;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > bram_wrdata_a;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > bram_rddata_a;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_pin2xtlm_t<32,15,1,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||
|
||||
// Transactor stubs
|
||||
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_rd_socket_stub;
|
||||
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_wr_socket_stub;
|
||||
|
||||
// Socket stubs
|
||||
|
||||
};
|
||||
#endif // VCSSYSTEMC
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef MTI_SYSTEMC
|
||||
#include "utils/xtlm_aximm_target_stub.h"
|
||||
|
||||
class DllExport system_top_axi_bram_ctrl_0_0 : public system_top_axi_bram_ctrl_0_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
system_top_axi_bram_ctrl_0_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~system_top_axi_bram_ctrl_0_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< bool > s_axi_aclk;
|
||||
sc_core::sc_in< bool > s_axi_aresetn;
|
||||
sc_core::sc_in< sc_dt::sc_bv<15> > s_axi_awaddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||
sc_core::sc_in< bool > s_axi_awlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||
sc_core::sc_in< bool > s_axi_awvalid;
|
||||
sc_core::sc_out< bool > s_axi_awready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
|
||||
sc_core::sc_in< bool > s_axi_wlast;
|
||||
sc_core::sc_in< bool > s_axi_wvalid;
|
||||
sc_core::sc_out< bool > s_axi_wready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||
sc_core::sc_out< bool > s_axi_bvalid;
|
||||
sc_core::sc_in< bool > s_axi_bready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<15> > s_axi_araddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||
sc_core::sc_in< bool > s_axi_arlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||
sc_core::sc_in< bool > s_axi_arvalid;
|
||||
sc_core::sc_out< bool > s_axi_arready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||
sc_core::sc_out< bool > s_axi_rlast;
|
||||
sc_core::sc_out< bool > s_axi_rvalid;
|
||||
sc_core::sc_in< bool > s_axi_rready;
|
||||
sc_core::sc_out< bool > bram_rst_a;
|
||||
sc_core::sc_out< bool > bram_clk_a;
|
||||
sc_core::sc_out< bool > bram_en_a;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > bram_we_a;
|
||||
sc_core::sc_out< sc_dt::sc_bv<15> > bram_addr_a;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > bram_wrdata_a;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > bram_rddata_a;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_pin2xtlm_t<32,15,1,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||
|
||||
// Transactor stubs
|
||||
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_rd_socket_stub;
|
||||
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_wr_socket_stub;
|
||||
|
||||
// Socket stubs
|
||||
|
||||
};
|
||||
#endif // MTI_SYSTEMC
|
||||
#endif // IP_SYSTEM_TOP_AXI_BRAM_CTRL_0_0_H_
|
||||
+322
@@ -0,0 +1,322 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:axi_bram_ctrl:4.1
|
||||
-- IP Revision: 10
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY axi_bram_ctrl_v4_1_10;
|
||||
USE axi_bram_ctrl_v4_1_10.axi_bram_ctrl;
|
||||
|
||||
ENTITY system_top_axi_bram_ctrl_0_0 IS
|
||||
PORT (
|
||||
s_axi_aclk : IN STD_LOGIC;
|
||||
s_axi_aresetn : IN STD_LOGIC;
|
||||
s_axi_awaddr : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
|
||||
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_awlock : IN STD_LOGIC;
|
||||
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi_awvalid : IN STD_LOGIC;
|
||||
s_axi_awready : OUT STD_LOGIC;
|
||||
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_wlast : IN STD_LOGIC;
|
||||
s_axi_wvalid : IN STD_LOGIC;
|
||||
s_axi_wready : OUT STD_LOGIC;
|
||||
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_bvalid : OUT STD_LOGIC;
|
||||
s_axi_bready : IN STD_LOGIC;
|
||||
s_axi_araddr : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
|
||||
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_arlock : IN STD_LOGIC;
|
||||
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi_arvalid : IN STD_LOGIC;
|
||||
s_axi_arready : OUT STD_LOGIC;
|
||||
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_rlast : OUT STD_LOGIC;
|
||||
s_axi_rvalid : OUT STD_LOGIC;
|
||||
s_axi_rready : IN STD_LOGIC;
|
||||
bram_rst_a : OUT STD_LOGIC;
|
||||
bram_clk_a : OUT STD_LOGIC;
|
||||
bram_en_a : OUT STD_LOGIC;
|
||||
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
bram_addr_a : OUT STD_LOGIC_VECTOR(14 DOWNTO 0);
|
||||
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
END system_top_axi_bram_ctrl_0_0;
|
||||
|
||||
ARCHITECTURE system_top_axi_bram_ctrl_0_0_arch OF system_top_axi_bram_ctrl_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_top_axi_bram_ctrl_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axi_bram_ctrl IS
|
||||
GENERIC (
|
||||
C_BRAM_INST_MODE : STRING;
|
||||
C_MEMORY_DEPTH : INTEGER;
|
||||
C_BRAM_ADDR_WIDTH : INTEGER;
|
||||
C_S_AXI_ADDR_WIDTH : INTEGER;
|
||||
C_S_AXI_DATA_WIDTH : INTEGER;
|
||||
C_S_AXI_ID_WIDTH : INTEGER;
|
||||
C_S_AXI_PROTOCOL : STRING;
|
||||
C_S_AXI_SUPPORTS_NARROW_BURST : INTEGER;
|
||||
C_SINGLE_PORT_BRAM : INTEGER;
|
||||
C_FAMILY : STRING;
|
||||
C_READ_LATENCY : INTEGER;
|
||||
C_RD_CMD_OPTIMIZATION : INTEGER;
|
||||
C_S_AXI_CTRL_ADDR_WIDTH : INTEGER;
|
||||
C_S_AXI_CTRL_DATA_WIDTH : INTEGER;
|
||||
C_ECC : INTEGER;
|
||||
C_ECC_TYPE : INTEGER;
|
||||
C_FAULT_INJECT : INTEGER;
|
||||
C_ECC_ONOFF_RESET_VALUE : INTEGER
|
||||
);
|
||||
PORT (
|
||||
s_axi_aclk : IN STD_LOGIC;
|
||||
s_axi_aresetn : IN STD_LOGIC;
|
||||
ecc_interrupt : OUT STD_LOGIC;
|
||||
ecc_ue : OUT STD_LOGIC;
|
||||
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axi_awaddr : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
|
||||
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_awlock : IN STD_LOGIC;
|
||||
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi_awvalid : IN STD_LOGIC;
|
||||
s_axi_awready : OUT STD_LOGIC;
|
||||
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_wlast : IN STD_LOGIC;
|
||||
s_axi_wvalid : IN STD_LOGIC;
|
||||
s_axi_wready : OUT STD_LOGIC;
|
||||
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_bvalid : OUT STD_LOGIC;
|
||||
s_axi_bready : IN STD_LOGIC;
|
||||
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axi_araddr : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
|
||||
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_arlock : IN STD_LOGIC;
|
||||
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi_arvalid : IN STD_LOGIC;
|
||||
s_axi_arready : OUT STD_LOGIC;
|
||||
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_rlast : OUT STD_LOGIC;
|
||||
s_axi_rvalid : OUT STD_LOGIC;
|
||||
s_axi_rready : IN STD_LOGIC;
|
||||
s_axi_ctrl_awvalid : IN STD_LOGIC;
|
||||
s_axi_ctrl_awready : OUT STD_LOGIC;
|
||||
s_axi_ctrl_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_ctrl_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_ctrl_wvalid : IN STD_LOGIC;
|
||||
s_axi_ctrl_wready : OUT STD_LOGIC;
|
||||
s_axi_ctrl_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_ctrl_bvalid : OUT STD_LOGIC;
|
||||
s_axi_ctrl_bready : IN STD_LOGIC;
|
||||
s_axi_ctrl_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_ctrl_arvalid : IN STD_LOGIC;
|
||||
s_axi_ctrl_arready : OUT STD_LOGIC;
|
||||
s_axi_ctrl_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_ctrl_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_ctrl_rvalid : OUT STD_LOGIC;
|
||||
s_axi_ctrl_rready : IN STD_LOGIC;
|
||||
bram_rst_a : OUT STD_LOGIC;
|
||||
bram_clk_a : OUT STD_LOGIC;
|
||||
bram_en_a : OUT STD_LOGIC;
|
||||
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
bram_addr_a : OUT STD_LOGIC_VECTOR(14 DOWNTO 0);
|
||||
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
bram_rst_b : OUT STD_LOGIC;
|
||||
bram_clk_b : OUT STD_LOGIC;
|
||||
bram_en_b : OUT STD_LOGIC;
|
||||
bram_we_b : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
bram_addr_b : OUT STD_LOGIC_VECTOR(14 DOWNTO 0);
|
||||
bram_wrdata_b : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
bram_rddata_b : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT axi_bram_ctrl;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bram_addr_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bram_clk_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bram_en_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bram_rddata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF bram_rst_a: SIGNAL IS "XIL_INTERFACENAME BRAM_PORTA, MASTER_TYPE BRAM_CTRL, MEM_SIZE 32768, MEM_WIDTH 32, MEM_ECC NONE, READ_WRITE_MODE READ_WRITE, READ_LATENCY 1";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bram_rst_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA RST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bram_we_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bram_wrdata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aclk: SIGNAL IS "XIL_INTERFACENAME CLKIF, ASSOCIATED_BUSIF S_AXI:S_AXI_CTRL, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 1e+08, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN system_top_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLKIF CLK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARBURST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 RSTIF RST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLEN";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARPROT";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 15, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN system_top_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, " &
|
||||
"NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWBURST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLEN";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWPROT";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
|
||||
BEGIN
|
||||
U0 : axi_bram_ctrl
|
||||
GENERIC MAP (
|
||||
C_BRAM_INST_MODE => "EXTERNAL",
|
||||
C_MEMORY_DEPTH => 8192,
|
||||
C_BRAM_ADDR_WIDTH => 13,
|
||||
C_S_AXI_ADDR_WIDTH => 15,
|
||||
C_S_AXI_DATA_WIDTH => 32,
|
||||
C_S_AXI_ID_WIDTH => 1,
|
||||
C_S_AXI_PROTOCOL => "AXI4",
|
||||
C_S_AXI_SUPPORTS_NARROW_BURST => 0,
|
||||
C_SINGLE_PORT_BRAM => 1,
|
||||
C_FAMILY => "zynq",
|
||||
C_READ_LATENCY => 1,
|
||||
C_RD_CMD_OPTIMIZATION => 0,
|
||||
C_S_AXI_CTRL_ADDR_WIDTH => 32,
|
||||
C_S_AXI_CTRL_DATA_WIDTH => 32,
|
||||
C_ECC => 0,
|
||||
C_ECC_TYPE => 0,
|
||||
C_FAULT_INJECT => 0,
|
||||
C_ECC_ONOFF_RESET_VALUE => 0
|
||||
)
|
||||
PORT MAP (
|
||||
s_axi_aclk => s_axi_aclk,
|
||||
s_axi_aresetn => s_axi_aresetn,
|
||||
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
s_axi_awaddr => s_axi_awaddr,
|
||||
s_axi_awlen => s_axi_awlen,
|
||||
s_axi_awsize => s_axi_awsize,
|
||||
s_axi_awburst => s_axi_awburst,
|
||||
s_axi_awlock => s_axi_awlock,
|
||||
s_axi_awcache => s_axi_awcache,
|
||||
s_axi_awprot => s_axi_awprot,
|
||||
s_axi_awvalid => s_axi_awvalid,
|
||||
s_axi_awready => s_axi_awready,
|
||||
s_axi_wdata => s_axi_wdata,
|
||||
s_axi_wstrb => s_axi_wstrb,
|
||||
s_axi_wlast => s_axi_wlast,
|
||||
s_axi_wvalid => s_axi_wvalid,
|
||||
s_axi_wready => s_axi_wready,
|
||||
s_axi_bresp => s_axi_bresp,
|
||||
s_axi_bvalid => s_axi_bvalid,
|
||||
s_axi_bready => s_axi_bready,
|
||||
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
s_axi_araddr => s_axi_araddr,
|
||||
s_axi_arlen => s_axi_arlen,
|
||||
s_axi_arsize => s_axi_arsize,
|
||||
s_axi_arburst => s_axi_arburst,
|
||||
s_axi_arlock => s_axi_arlock,
|
||||
s_axi_arcache => s_axi_arcache,
|
||||
s_axi_arprot => s_axi_arprot,
|
||||
s_axi_arvalid => s_axi_arvalid,
|
||||
s_axi_arready => s_axi_arready,
|
||||
s_axi_rdata => s_axi_rdata,
|
||||
s_axi_rresp => s_axi_rresp,
|
||||
s_axi_rlast => s_axi_rlast,
|
||||
s_axi_rvalid => s_axi_rvalid,
|
||||
s_axi_rready => s_axi_rready,
|
||||
s_axi_ctrl_awvalid => '0',
|
||||
s_axi_ctrl_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
s_axi_ctrl_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
s_axi_ctrl_wvalid => '0',
|
||||
s_axi_ctrl_bready => '0',
|
||||
s_axi_ctrl_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
s_axi_ctrl_arvalid => '0',
|
||||
s_axi_ctrl_rready => '0',
|
||||
bram_rst_a => bram_rst_a,
|
||||
bram_clk_a => bram_clk_a,
|
||||
bram_en_a => bram_en_a,
|
||||
bram_we_a => bram_we_a,
|
||||
bram_addr_a => bram_addr_a,
|
||||
bram_wrdata_a => bram_wrdata_a,
|
||||
bram_rddata_a => bram_rddata_a,
|
||||
bram_rddata_b => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
|
||||
);
|
||||
END system_top_axi_bram_ctrl_0_0_arch;
|
||||
+97
@@ -0,0 +1,97 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
#include "system_top_axi_bram_ctrl_0_0_sc.h"
|
||||
|
||||
#include "axi_bram_ctrl.h"
|
||||
|
||||
#include <map>
|
||||
#include <string>
|
||||
|
||||
system_top_axi_bram_ctrl_0_0_sc::system_top_axi_bram_ctrl_0_0_sc(const sc_core::sc_module_name& nm) : sc_core::sc_module(nm), mp_impl(NULL)
|
||||
{
|
||||
// configure connectivity manager
|
||||
xsc::utils::xsc_sim_manager::addInstance("system_top_axi_bram_ctrl_0_0", this);
|
||||
|
||||
// initialize module
|
||||
xsc::common_cpp::properties model_param_props;
|
||||
model_param_props.addLong("C_MEMORY_DEPTH", "8192");
|
||||
model_param_props.addLong("C_BRAM_ADDR_WIDTH", "13");
|
||||
model_param_props.addLong("C_S_AXI_ADDR_WIDTH", "15");
|
||||
model_param_props.addLong("C_S_AXI_DATA_WIDTH", "32");
|
||||
model_param_props.addLong("C_S_AXI_ID_WIDTH", "1");
|
||||
model_param_props.addLong("C_S_AXI_SUPPORTS_NARROW_BURST", "0");
|
||||
model_param_props.addLong("C_SINGLE_PORT_BRAM", "1");
|
||||
model_param_props.addLong("C_READ_LATENCY", "1");
|
||||
model_param_props.addLong("C_RD_CMD_OPTIMIZATION", "0");
|
||||
model_param_props.addLong("C_S_AXI_CTRL_ADDR_WIDTH", "32");
|
||||
model_param_props.addLong("C_S_AXI_CTRL_DATA_WIDTH", "32");
|
||||
model_param_props.addLong("C_ECC", "0");
|
||||
model_param_props.addLong("C_ECC_TYPE", "0");
|
||||
model_param_props.addLong("C_FAULT_INJECT", "0");
|
||||
model_param_props.addLong("C_ECC_ONOFF_RESET_VALUE", "0");
|
||||
model_param_props.addString("C_BRAM_INST_MODE", "EXTERNAL");
|
||||
model_param_props.addString("C_S_AXI_PROTOCOL", "AXI4");
|
||||
model_param_props.addString("C_FAMILY", "zynq");
|
||||
model_param_props.addString("COMPONENT_NAME", "system_top_axi_bram_ctrl_0_0");
|
||||
|
||||
mp_impl = new axi_bram_ctrl("inst", model_param_props);
|
||||
|
||||
// initialize AXI sockets
|
||||
target_0_rd_socket = mp_impl->target_0_rd_socket;
|
||||
target_0_wr_socket = mp_impl->target_0_wr_socket;
|
||||
}
|
||||
|
||||
system_top_axi_bram_ctrl_0_0_sc::~system_top_axi_bram_ctrl_0_0_sc()
|
||||
{
|
||||
xsc::utils::xsc_sim_manager::clean();
|
||||
|
||||
delete mp_impl;
|
||||
}
|
||||
|
||||
+96
@@ -0,0 +1,96 @@
|
||||
#ifndef IP_SYSTEM_TOP_AXI_BRAM_CTRL_0_0_SC_H_
|
||||
#define IP_SYSTEM_TOP_AXI_BRAM_CTRL_0_0_SC_H_
|
||||
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
#ifndef XTLM
|
||||
#include "xtlm.h"
|
||||
#endif
|
||||
#ifndef SYSTEMC_INCLUDED
|
||||
#include <systemc>
|
||||
#endif
|
||||
|
||||
#if defined(_MSC_VER)
|
||||
#define DllExport __declspec(dllexport)
|
||||
#elif defined(__GNUC__)
|
||||
#define DllExport __attribute__ ((visibility("default")))
|
||||
#else
|
||||
#define DllExport
|
||||
#endif
|
||||
|
||||
class axi_bram_ctrl;
|
||||
|
||||
class DllExport system_top_axi_bram_ctrl_0_0_sc : public sc_core::sc_module
|
||||
{
|
||||
public:
|
||||
|
||||
system_top_axi_bram_ctrl_0_0_sc(const sc_core::sc_module_name& nm);
|
||||
virtual ~system_top_axi_bram_ctrl_0_0_sc();
|
||||
|
||||
// module socket-to-socket AXI TLM interfaces
|
||||
|
||||
xtlm::xtlm_aximm_target_socket* target_0_rd_socket;
|
||||
xtlm::xtlm_aximm_target_socket* target_0_wr_socket;
|
||||
|
||||
// module socket-to-socket TLM interfaces
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
axi_bram_ctrl* mp_impl;
|
||||
|
||||
private:
|
||||
|
||||
system_top_axi_bram_ctrl_0_0_sc(const system_top_axi_bram_ctrl_0_0_sc&);
|
||||
const system_top_axi_bram_ctrl_0_0_sc& operator=(const system_top_axi_bram_ctrl_0_0_sc&);
|
||||
|
||||
};
|
||||
|
||||
#endif // IP_SYSTEM_TOP_AXI_BRAM_CTRL_0_0_SC_H_
|
||||
+159
@@ -0,0 +1,159 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
//------------------------------------------------------------------------------------
|
||||
// Filename: system_top_axi_bram_ctrl_0_0_stub.sv
|
||||
// Description: This HDL file is intended to be used with following simulators only:
|
||||
//
|
||||
// Vivado Simulator (XSim)
|
||||
// Cadence Xcelium Simulator
|
||||
//
|
||||
//------------------------------------------------------------------------------------
|
||||
`timescale 1ps/1ps
|
||||
|
||||
`ifdef XILINX_SIMULATOR
|
||||
|
||||
`ifndef XILINX_SIMULATOR_BITASBOOL
|
||||
`define XILINX_SIMULATOR_BITASBOOL
|
||||
typedef bit bit_as_bool;
|
||||
`endif
|
||||
|
||||
(* SC_MODULE_EXPORT *)
|
||||
module system_top_axi_bram_ctrl_0_0 (
|
||||
input bit_as_bool s_axi_aclk,
|
||||
input bit_as_bool s_axi_aresetn,
|
||||
input bit [14 : 0] s_axi_awaddr,
|
||||
input bit [7 : 0] s_axi_awlen,
|
||||
input bit [2 : 0] s_axi_awsize,
|
||||
input bit [1 : 0] s_axi_awburst,
|
||||
input bit_as_bool s_axi_awlock,
|
||||
input bit [3 : 0] s_axi_awcache,
|
||||
input bit [2 : 0] s_axi_awprot,
|
||||
input bit_as_bool s_axi_awvalid,
|
||||
output bit_as_bool s_axi_awready,
|
||||
input bit [31 : 0] s_axi_wdata,
|
||||
input bit [3 : 0] s_axi_wstrb,
|
||||
input bit_as_bool s_axi_wlast,
|
||||
input bit_as_bool s_axi_wvalid,
|
||||
output bit_as_bool s_axi_wready,
|
||||
output bit [1 : 0] s_axi_bresp,
|
||||
output bit_as_bool s_axi_bvalid,
|
||||
input bit_as_bool s_axi_bready,
|
||||
input bit [14 : 0] s_axi_araddr,
|
||||
input bit [7 : 0] s_axi_arlen,
|
||||
input bit [2 : 0] s_axi_arsize,
|
||||
input bit [1 : 0] s_axi_arburst,
|
||||
input bit_as_bool s_axi_arlock,
|
||||
input bit [3 : 0] s_axi_arcache,
|
||||
input bit [2 : 0] s_axi_arprot,
|
||||
input bit_as_bool s_axi_arvalid,
|
||||
output bit_as_bool s_axi_arready,
|
||||
output bit [31 : 0] s_axi_rdata,
|
||||
output bit [1 : 0] s_axi_rresp,
|
||||
output bit_as_bool s_axi_rlast,
|
||||
output bit_as_bool s_axi_rvalid,
|
||||
input bit_as_bool s_axi_rready,
|
||||
output bit_as_bool bram_rst_a,
|
||||
output bit_as_bool bram_clk_a,
|
||||
output bit_as_bool bram_en_a,
|
||||
output bit [3 : 0] bram_we_a,
|
||||
output bit [14 : 0] bram_addr_a,
|
||||
output bit [31 : 0] bram_wrdata_a,
|
||||
input bit [31 : 0] bram_rddata_a
|
||||
);
|
||||
endmodule
|
||||
`endif
|
||||
|
||||
`ifdef XCELIUM
|
||||
(* XMSC_MODULE_EXPORT *)
|
||||
module system_top_axi_bram_ctrl_0_0 (s_axi_aclk,s_axi_aresetn,s_axi_awaddr,s_axi_awlen,s_axi_awsize,s_axi_awburst,s_axi_awlock,s_axi_awcache,s_axi_awprot,s_axi_awvalid,s_axi_awready,s_axi_wdata,s_axi_wstrb,s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bresp,s_axi_bvalid,s_axi_bready,s_axi_araddr,s_axi_arlen,s_axi_arsize,s_axi_arburst,s_axi_arlock,s_axi_arcache,s_axi_arprot,s_axi_arvalid,s_axi_arready,s_axi_rdata,s_axi_rresp,s_axi_rlast,s_axi_rvalid,s_axi_rready,bram_rst_a,bram_clk_a,bram_en_a,bram_we_a,bram_addr_a,bram_wrdata_a,bram_rddata_a)
|
||||
(* integer foreign = "SystemC";
|
||||
*);
|
||||
input bit s_axi_aclk;
|
||||
input bit s_axi_aresetn;
|
||||
input bit [14 : 0] s_axi_awaddr;
|
||||
input bit [7 : 0] s_axi_awlen;
|
||||
input bit [2 : 0] s_axi_awsize;
|
||||
input bit [1 : 0] s_axi_awburst;
|
||||
input bit s_axi_awlock;
|
||||
input bit [3 : 0] s_axi_awcache;
|
||||
input bit [2 : 0] s_axi_awprot;
|
||||
input bit s_axi_awvalid;
|
||||
output wire s_axi_awready;
|
||||
input bit [31 : 0] s_axi_wdata;
|
||||
input bit [3 : 0] s_axi_wstrb;
|
||||
input bit s_axi_wlast;
|
||||
input bit s_axi_wvalid;
|
||||
output wire s_axi_wready;
|
||||
output wire [1 : 0] s_axi_bresp;
|
||||
output wire s_axi_bvalid;
|
||||
input bit s_axi_bready;
|
||||
input bit [14 : 0] s_axi_araddr;
|
||||
input bit [7 : 0] s_axi_arlen;
|
||||
input bit [2 : 0] s_axi_arsize;
|
||||
input bit [1 : 0] s_axi_arburst;
|
||||
input bit s_axi_arlock;
|
||||
input bit [3 : 0] s_axi_arcache;
|
||||
input bit [2 : 0] s_axi_arprot;
|
||||
input bit s_axi_arvalid;
|
||||
output wire s_axi_arready;
|
||||
output wire [31 : 0] s_axi_rdata;
|
||||
output wire [1 : 0] s_axi_rresp;
|
||||
output wire s_axi_rlast;
|
||||
output wire s_axi_rvalid;
|
||||
input bit s_axi_rready;
|
||||
output wire bram_rst_a;
|
||||
output wire bram_clk_a;
|
||||
output wire bram_en_a;
|
||||
output wire [3 : 0] bram_we_a;
|
||||
output wire [14 : 0] bram_addr_a;
|
||||
output wire [31 : 0] bram_wrdata_a;
|
||||
input bit [31 : 0] bram_rddata_a;
|
||||
endmodule
|
||||
`endif
|
||||
+134
@@ -0,0 +1,134 @@
|
||||
// (c) Copyright 1995-2021, 2023 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
////////////////////////////////////////////////////////////
|
||||
|
||||
#ifndef __P2P_XTLM_EXTENSION_HH_
|
||||
#define __P2P_XTLM_EXTENSION_HH_
|
||||
#include "xtlm.h"
|
||||
|
||||
/**
|
||||
* XTLM extension to support peer to peer buffer allocation
|
||||
* Master requests buffer allocation with a base address and size and slave responds with corresponding
|
||||
* mmaped buffer file name
|
||||
*/
|
||||
namespace xsc {
|
||||
namespace extension {
|
||||
enum TYPE {
|
||||
ALLOC_BO,
|
||||
FREE_BO,
|
||||
IMPORT_BO,
|
||||
COPY_BO
|
||||
};
|
||||
|
||||
class P2P_XTLM_extension: public xtlm::xtlm_extension<P2P_XTLM_extension> {
|
||||
|
||||
public:
|
||||
P2P_XTLM_extension() {
|
||||
m_address=0;
|
||||
m_size=0;
|
||||
m_file_name = "";
|
||||
m_resp_valid=false;
|
||||
m_resp=false;
|
||||
m_type=TYPE::ALLOC_BO;
|
||||
m_src_offset = 0;
|
||||
m_dst_offset = 0;
|
||||
}
|
||||
|
||||
~P2P_XTLM_extension(){}
|
||||
xtlm::xtlm_extension_base* clone() const {
|
||||
// Must override pure virtual clone method
|
||||
P2P_XTLM_extension* t = new P2P_XTLM_extension();
|
||||
return t;
|
||||
}
|
||||
// Must override pure virtual copy_from method
|
||||
void copy_from(xtlm::xtlm_extension_base const &ext) {
|
||||
m_address = static_cast<P2P_XTLM_extension const &>(ext).m_address;
|
||||
m_size = static_cast<P2P_XTLM_extension const &>(ext).m_size;
|
||||
m_file_name = static_cast<P2P_XTLM_extension const &>(ext).m_file_name;
|
||||
m_resp_valid = static_cast<P2P_XTLM_extension const &>(ext).m_resp_valid;
|
||||
m_resp = static_cast<P2P_XTLM_extension const &>(ext).m_resp;
|
||||
m_type = static_cast<P2P_XTLM_extension const &>(ext).m_type;
|
||||
m_src_offset = static_cast<P2P_XTLM_extension const &>(ext).m_src_offset;
|
||||
m_dst_offset = static_cast<P2P_XTLM_extension const &>(ext).m_dst_offset;
|
||||
}
|
||||
|
||||
void setAddress(uint64_t address) { m_address = address; }
|
||||
uint64_t getAddress()const { return m_address; }
|
||||
|
||||
void setSize(uint64_t size) { m_size = size; }
|
||||
uint64_t getSize()const { return m_size; }
|
||||
|
||||
void setFileName(std::string file_name) { m_file_name = file_name; }
|
||||
const std::string& getFileName()const { return m_file_name; }
|
||||
|
||||
void setIsResponseValid(bool resp_valid) { m_resp_valid = resp_valid;}
|
||||
bool getIsResponseValid() { return m_resp_valid; }
|
||||
|
||||
void setResponse(bool resp){ m_resp = resp;}
|
||||
bool getResponse() const { return m_resp;}
|
||||
|
||||
void setSrcOffset(uint64_t src_offset) { m_src_offset = src_offset; }
|
||||
uint64_t getSrcOffset() const { return m_src_offset; }
|
||||
|
||||
void setDstOffset(uint64_t dst_offset) { m_dst_offset = dst_offset; }
|
||||
uint64_t getDstOffset() const { return m_dst_offset; }
|
||||
|
||||
void setType(TYPE type) { m_type = type; }
|
||||
TYPE getType() const { return m_type;}
|
||||
|
||||
private :
|
||||
uint64_t m_address;
|
||||
uint64_t m_size;
|
||||
std::string m_file_name;
|
||||
bool m_resp_valid;
|
||||
bool m_resp;
|
||||
uint64_t m_src_offset;
|
||||
uint64_t m_dst_offset;
|
||||
TYPE m_type;
|
||||
};
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
+96
@@ -0,0 +1,96 @@
|
||||
// (c) Copyright 1995-2021, 2023 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
////////////////////////////////////////////////////////////
|
||||
|
||||
#include "axi_bram_ctrl.h"
|
||||
|
||||
axi_bram_ctrl::axi_bram_ctrl(const sc_module_name& module_name, xsc::common_cpp::properties& properties) :
|
||||
sc_module(module_name) {
|
||||
//Get Width from property
|
||||
uint64_t data_width=properties.getLongLong("C_S_AXI_DATA_WIDTH");
|
||||
uint64_t dual_port=properties.getLongLong("C_SINGLE_PORT_BRAM");
|
||||
uint64_t ecc=properties.getLongLong("C_ECC");
|
||||
target_0_rd_socket = new xtlm::xtlm_aximm_target_socket("target_0_rd_socket", data_width);
|
||||
target_0_wr_socket = new xtlm::xtlm_aximm_target_socket("target_0_wr_socket", data_width);
|
||||
m_imp=new axi_bram_memory_imp("impl",properties);
|
||||
target_0_rd_socket->bind(*(m_imp->target_0_rd_socket));
|
||||
target_0_wr_socket->bind(*(m_imp->target_0_wr_socket));
|
||||
if(ecc==1)
|
||||
{
|
||||
s_axi_ctrl_target_rd_socket = new xtlm::xtlm_aximm_target_socket("target_1_rd_socket", 32);
|
||||
s_axi_ctrl_target_wr_socket = new xtlm::xtlm_aximm_target_socket("target_1_wr_socket", 32);
|
||||
auto* stubWr = new xtlm::xtlm_aximm_target_stub("ifWrStubskt0", 32);
|
||||
s_axi_ctrl_target_wr_socket->bind(stubWr->target_socket);
|
||||
auto* stubRd = new xtlm::xtlm_aximm_target_stub("ifRdStubskt0", 32);
|
||||
s_axi_ctrl_target_rd_socket->bind(stubRd->target_socket);
|
||||
stubInitSkt.push_back(stubWr);
|
||||
stubInitSkt.push_back(stubRd);
|
||||
}
|
||||
if(dual_port==1)
|
||||
{
|
||||
bram_rst_b(bram_rst_b1);
|
||||
bram_clk_b(bram_clk_b1);
|
||||
bram_en_b(bram_en_b1);
|
||||
bram_we_b(bram_we_b1);
|
||||
bram_addr_b(bram_addr_b1);
|
||||
bram_wrdata_b(bram_wrdata_b1);
|
||||
bram_rddata_b(bram_rddata_b1);
|
||||
}
|
||||
|
||||
SC_THREAD(clock_finder);
|
||||
sensitive<< s_axi_aclk;
|
||||
dont_initialize();
|
||||
|
||||
}
|
||||
axi_bram_ctrl::~axi_bram_ctrl() {
|
||||
delete target_0_rd_socket;
|
||||
delete target_0_wr_socket;
|
||||
delete m_imp;
|
||||
}
|
||||
void axi_bram_ctrl::clock_finder() {
|
||||
sc_time clk1 = sc_time_stamp();
|
||||
wait();
|
||||
sc_time clk2= sc_time_stamp();
|
||||
}
|
||||
+100
@@ -0,0 +1,100 @@
|
||||
// (c) Copyright 1995-2021, 2023 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
////////////////////////////////////////////////////////////
|
||||
|
||||
#ifndef _SIMHBMX_H_
|
||||
#define _SIMHBMX_H_
|
||||
|
||||
#include "xtlm.h"
|
||||
#include <list>
|
||||
|
||||
#include "axi_bram_memory_imp.h"
|
||||
#include "utils/xtlm_aximm_target_stub.h"
|
||||
#include "utils/xsc_stub_port.h"
|
||||
|
||||
class axi_bram_ctrl: public sc_core::sc_module {
|
||||
public:
|
||||
axi_bram_ctrl(const sc_module_name& module_name,xsc::common_cpp::properties&);
|
||||
virtual ~axi_bram_ctrl();
|
||||
SC_HAS_PROCESS(axi_bram_ctrl);
|
||||
//Slave interface used to R/W to HBM Memory
|
||||
xtlm::xtlm_aximm_target_socket* target_0_rd_socket;
|
||||
xtlm::xtlm_aximm_target_socket* target_0_wr_socket;
|
||||
xtlm::xtlm_aximm_target_socket* s_axi_ctrl_target_rd_socket;
|
||||
xtlm::xtlm_aximm_target_socket* s_axi_ctrl_target_wr_socket;
|
||||
std::vector<xtlm::xtlm_aximm_target_stub*> stubInitSkt;
|
||||
void clock_finder();
|
||||
sc_in<bool> s_axi_aclk;
|
||||
sc_in<bool> s_axi_aresetn;
|
||||
xsc::utils::xsc_stub_port ecc_interrupt;
|
||||
xsc::utils::xsc_stub_port ecc_ue;
|
||||
xsc::utils::xsc_stub_port bram_rst_a;
|
||||
xsc::utils::xsc_stub_port bram_clk_a;
|
||||
xsc::utils::xsc_stub_port bram_en_a;
|
||||
xsc::utils::xsc_stub_port bram_we_a;
|
||||
xsc::utils::xsc_stub_port bram_addr_a;
|
||||
xsc::utils::xsc_stub_port bram_wrdata_a;
|
||||
xsc::utils::xsc_stub_port bram_rddata_a;
|
||||
xsc::utils::xsc_stub_port bram_rst_b;
|
||||
xsc::utils::xsc_stub_port bram_clk_b;
|
||||
xsc::utils::xsc_stub_port bram_en_b;
|
||||
xsc::utils::xsc_stub_port bram_we_b;
|
||||
xsc::utils::xsc_stub_port bram_addr_b;
|
||||
xsc::utils::xsc_stub_port bram_wrdata_b;
|
||||
xsc::utils::xsc_stub_port bram_rddata_b;
|
||||
sc_core::sc_signal<bool>bram_rst_b1;
|
||||
sc_core::sc_signal<bool>bram_clk_b1;
|
||||
sc_core::sc_signal<bool>bram_en_b1;
|
||||
sc_core::sc_signal<bool>bram_we_b1;
|
||||
sc_core::sc_signal<bool>bram_addr_b1;
|
||||
sc_core::sc_signal<bool>bram_wrdata_b1;
|
||||
sc_core::sc_signal<bool>bram_rddata_b1;
|
||||
|
||||
|
||||
private :
|
||||
axi_bram_memory_imp* m_imp;
|
||||
};
|
||||
|
||||
#endif /* _SIMHBMX_H_ */
|
||||
+65
@@ -0,0 +1,65 @@
|
||||
// (c) Copyright 1995-2021, 2023 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
////////////////////////////////////////////////////////////
|
||||
|
||||
#include <sys/stat.h>
|
||||
#include "axi_bram_fmodel_base.h"
|
||||
//#define DEBUGMSG
|
||||
|
||||
|
||||
axi_bram_fmodel_base::~ axi_bram_fmodel_base()
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
axi_bram_fmodel_base::axi_bram_fmodel_base(std::string p_module_name,xsc::common_cpp::report_handler* report_handler,uint64_t addr_size): module_name(p_module_name)
|
||||
{
|
||||
}
|
||||
|
||||
void axi_bram_fmodel_base::init_fmodel()
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
+95
@@ -0,0 +1,95 @@
|
||||
// (c) Copyright 1995-2021, 2023 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
////////////////////////////////////////////////////////////
|
||||
|
||||
#ifndef XTLM_SIMPLE_FMODEL_BASE__H
|
||||
#define XTLM_SIMPLE_FMODEL_BASE__H
|
||||
#include <math.h>
|
||||
#include <iostream>
|
||||
|
||||
#include <string.h> // memcpy
|
||||
#include <stdlib.h> //realloc
|
||||
#include <stdint.h>
|
||||
#include <vector>
|
||||
#include <map> //realloc
|
||||
#include <unistd.h>
|
||||
#include <sys/types.h>
|
||||
#include <sys/stat.h>
|
||||
#include <fcntl.h>
|
||||
#include <sys/mman.h>
|
||||
#include "report_handler.h"
|
||||
|
||||
#define ONE_KB (0x400)
|
||||
#define ONE_MB (ONE_KB * ONE_KB)
|
||||
#define PAGESIZE (ONE_MB)
|
||||
#define ADDRBITS (20)
|
||||
#define N_1MBARRAYS 4096
|
||||
|
||||
class axi_bram_fmodel_base {
|
||||
public:
|
||||
virtual unsigned int writeDevMem(uint64_t offset, void* src,
|
||||
unsigned int size) = 0;
|
||||
virtual unsigned int readDevMem(uint64_t offset, void* dest,
|
||||
unsigned int size) = 0;
|
||||
virtual bool createMMappedBuffer(uint64_t base_address, uint64_t size,
|
||||
std::string& buffer_filename) = 0;
|
||||
virtual bool freePage(uint64_t base_address) = 0;
|
||||
virtual unsigned char* get_page(uint64_t offset, std::string& p2pFileName,
|
||||
uint64_t size = 0) = 0;
|
||||
virtual bool copyBO(uint64_t offset, std::string dst_filename,
|
||||
uint64_t size, uint64_t src_offset, uint64_t dst_offset) = 0;
|
||||
virtual bool importBO(uint64_t offset, std::string dst_filename,
|
||||
uint64_t size) = 0;
|
||||
axi_bram_fmodel_base(std::string p_module_name,
|
||||
xsc::common_cpp::report_handler* report_handler,
|
||||
uint64_t addr_size);
|
||||
virtual ~ axi_bram_fmodel_base();
|
||||
void init_fmodel();
|
||||
virtual void reset_fmodel() = 0;
|
||||
std::string module_name;
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
+441
@@ -0,0 +1,441 @@
|
||||
// (c) Copyright 1995-2021, 2023 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
////////////////////////////////////////////////////////////
|
||||
|
||||
#include "axi_bram_fmodel_shared_memory.h"
|
||||
#include <sys/stat.h>
|
||||
#include <sstream>
|
||||
|
||||
std::map<std::string, std::tuple<uint64_t, void*, int> > axi_bram_fmodel_shared_memory::mFileFdMap;
|
||||
|
||||
axi_bram_fmodel_shared_memory::axi_bram_fmodel_shared_memory(
|
||||
std::string p_module_name,
|
||||
xsc::common_cpp::report_handler* report_handler, uint64_t addr_size) : //Mode 0
|
||||
axi_bram_fmodel_base(p_module_name, report_handler, addr_size) {
|
||||
m_report_handler = report_handler;
|
||||
if (m_report_handler->get_verbosity_level()
|
||||
== xsc::common_cpp::VERBOSITY::DEBUG) {
|
||||
std::stringstream m_ss;
|
||||
m_ss.str("");
|
||||
m_ss << module_name << std::endl;
|
||||
XSC_REPORT_INFO((*m_report_handler), "xtlmmemorymodel_shared_memory",
|
||||
m_ss.str().c_str());
|
||||
}
|
||||
}
|
||||
|
||||
void axi_bram_fmodel_shared_memory::reset_fmodel() {
|
||||
auto pageIt = mPageCache.begin();
|
||||
auto pageEnd = mPageCache.end();
|
||||
while (pageIt != pageEnd) {
|
||||
uint64_t offset = (*pageIt).first;
|
||||
|
||||
auto itr = mOffsetFileMap.find(offset);
|
||||
int fd = -1;
|
||||
if (itr != mOffsetFileMap.end()) {
|
||||
std::string sFileName = (*itr).second;
|
||||
auto itr2 = mFileFdMap.find(sFileName);
|
||||
if (itr2 != mFileFdMap.end()) {
|
||||
fd = std::get<0>((*itr2).second);
|
||||
void* pPtr = std::get<1>((*itr2).second);
|
||||
int size = std::get<2>((*itr2).second);
|
||||
munmap(pPtr, size);
|
||||
mFileFdMap.erase(itr2);
|
||||
close(fd);
|
||||
}
|
||||
}
|
||||
pageIt++;
|
||||
}
|
||||
|
||||
}
|
||||
axi_bram_fmodel_shared_memory::~axi_bram_fmodel_shared_memory() {
|
||||
}
|
||||
|
||||
unsigned int axi_bram_fmodel_shared_memory::writeDevMem(uint64_t offset,
|
||||
void* src, unsigned int size) {
|
||||
|
||||
uint64_t written_bytes = 0;
|
||||
uint64_t addr = offset;
|
||||
while (written_bytes < size) {
|
||||
uint64_t src_offset = written_bytes;
|
||||
|
||||
std::string p2pFileName("");
|
||||
unsigned char* page_ptr = get_page(addr, p2pFileName);
|
||||
uint64_t ddrAddress = getBaseDdrAddress(addr);
|
||||
if (!page_ptr) {
|
||||
std::stringstream errMsg;
|
||||
errMsg
|
||||
<< "Kernel attempting to write to memory which was never allocated ("
|
||||
<< std::hex << "0x" << offset << ")" << std::dec;
|
||||
XSC_REPORT_INFO((*m_report_handler),
|
||||
"xtlmsimplememorymodel_shared_memory",
|
||||
errMsg.str().c_str());
|
||||
return 0;
|
||||
}
|
||||
unsigned char* dest_buf_ptr = page_ptr + offset - ddrAddress;
|
||||
unsigned char* src_buf_ptr = (unsigned char*) (src) + src_offset;
|
||||
|
||||
uint64_t remaining_bytes_to_write = size - written_bytes;
|
||||
//memcpy(dest_buf_ptr,src_buf_ptr,buf_size);
|
||||
for (unsigned int i = 0; i < remaining_bytes_to_write; i++) {
|
||||
dest_buf_ptr[i] = src_buf_ptr[i];
|
||||
}
|
||||
|
||||
written_bytes += remaining_bytes_to_write;
|
||||
addr += remaining_bytes_to_write;
|
||||
}
|
||||
|
||||
if (m_report_handler->get_verbosity_level()
|
||||
== xsc::common_cpp::VERBOSITY::DEBUG) {
|
||||
std::stringstream m_ss;
|
||||
m_ss.str("");
|
||||
m_ss << "Write Operation size : " << size << std::endl;
|
||||
for (int i = 0; i < size; i++) {
|
||||
m_ss << std::hex << (unsigned int) (((unsigned char*) src)[i])
|
||||
<< " ";
|
||||
}
|
||||
m_ss << std::endl;
|
||||
m_ss << "Write : " << "Offset --> " << offset << std::endl;
|
||||
XSC_REPORT_INFO((*m_report_handler), "xtlmmemorymodel_shared_memory",
|
||||
m_ss.str().c_str());
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
unsigned int axi_bram_fmodel_shared_memory::readDevMem(uint64_t offset,
|
||||
void* dest, unsigned int size) {
|
||||
uint64_t read_bytes = 0;
|
||||
uint64_t addr = offset;
|
||||
while (read_bytes < size) {
|
||||
uint64_t dest_offset = read_bytes;
|
||||
|
||||
std::string p2pFileName("");
|
||||
unsigned char* page_ptr = get_page(addr, p2pFileName);
|
||||
uint64_t ddrAddress = getBaseDdrAddress(addr);
|
||||
|
||||
if (!page_ptr) {
|
||||
if (m_report_handler->get_verbosity_level()
|
||||
== xsc::common_cpp::VERBOSITY::DEBUG) {
|
||||
std::stringstream errMsg;
|
||||
errMsg
|
||||
<< "Kernel attempting to read to memory which was never allocated ("
|
||||
<< std::hex << "0x" << offset << ")" << std::dec;
|
||||
XSC_REPORT_INFO((*m_report_handler),
|
||||
"xtlmsimplememorymodel_shared_memory",
|
||||
errMsg.str().c_str());
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
unsigned char* src_buf_ptr = page_ptr + (offset - ddrAddress);
|
||||
unsigned char* dest_buf_ptr = (unsigned char*) (dest) + dest_offset;
|
||||
|
||||
uint64_t remaining_bytes_to_read = size - read_bytes;
|
||||
|
||||
for (uint64_t i = 0; i < remaining_bytes_to_read; i++) {
|
||||
dest_buf_ptr[i] = src_buf_ptr[i];
|
||||
}
|
||||
|
||||
read_bytes += remaining_bytes_to_read;
|
||||
addr += remaining_bytes_to_read;
|
||||
}
|
||||
|
||||
if (m_report_handler->get_verbosity_level()
|
||||
== xsc::common_cpp::VERBOSITY::DEBUG) {
|
||||
std::stringstream m_ss;
|
||||
m_ss.str("");
|
||||
m_ss << "Read Operation size : " << size << std::endl;
|
||||
for (int i = 0; i < size; i++) {
|
||||
m_ss << std::hex << (unsigned int) (((unsigned char*) dest)[i])
|
||||
<< " ";
|
||||
}
|
||||
m_ss << std::endl;
|
||||
m_ss << "Read : " << "Offset --> " << offset << std::endl;
|
||||
XSC_REPORT_INFO((*m_report_handler),
|
||||
"xtlmsimplememorymodel_shared_memory", m_ss.str().c_str());
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
unsigned char* axi_bram_fmodel_shared_memory::get_page(uint64_t offset,
|
||||
std::string& p2pFileName, uint64_t size) {
|
||||
auto pageIt = mPageCache.begin();
|
||||
auto pageEnd = mPageCache.end();
|
||||
while (pageIt != pageEnd) {
|
||||
uint64_t startAddress = (*pageIt).first;
|
||||
std::pair<unsigned char*, uint64_t> addressSizePair = (*pageIt).second;
|
||||
unsigned char* pageStartOSAddress = addressSizePair.first;
|
||||
uint64_t pageSize = addressSizePair.second;
|
||||
if (offset >= startAddress && offset < startAddress + pageSize) {
|
||||
return pageStartOSAddress;
|
||||
}
|
||||
pageIt++;
|
||||
}
|
||||
//in partial reconfiguration case, we should read the file which is stored.
|
||||
|
||||
return NULL;
|
||||
|
||||
}
|
||||
|
||||
uint64_t axi_bram_fmodel_shared_memory::getBaseDdrAddress(uint64_t offset) {
|
||||
auto pageIt = mPageCache.begin();
|
||||
auto pageEnd = mPageCache.end();
|
||||
while (pageIt != pageEnd) {
|
||||
uint64_t startAddress = (*pageIt).first;
|
||||
std::pair<unsigned char*, uint64_t> addressSizePair = (*pageIt).second;
|
||||
uint64_t pageSize = addressSizePair.second;
|
||||
if (offset >= startAddress && offset < startAddress + pageSize) {
|
||||
return startAddress;
|
||||
}
|
||||
pageIt++;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
bool axi_bram_fmodel_shared_memory::copyBO(uint64_t offset,
|
||||
std::string dst_filename, uint64_t size, uint64_t src_offset,
|
||||
uint64_t dst_offset) {
|
||||
uint64_t read_bytes = 0;
|
||||
uint64_t addr = offset;
|
||||
std::string p2pFileName("");
|
||||
unsigned char* page_ptr = get_page(addr, p2pFileName);
|
||||
uint64_t ddrAddress = getBaseDdrAddress(addr);
|
||||
unsigned char* src_buf_ptr = (unsigned char*) (page_ptr
|
||||
+ (offset - ddrAddress) + src_offset);
|
||||
auto itr = mFileFdMap.find(dst_filename);
|
||||
if (itr != mFileFdMap.end()) {
|
||||
int dst_fd = std::get<0>((*itr).second);
|
||||
if (lseek(dst_fd, dst_offset, SEEK_CUR) < 0)
|
||||
return false;
|
||||
int bytes_written = write(dst_fd, src_buf_ptr,
|
||||
size/*strlen(src_buf_ptr)*/);
|
||||
if (bytes_written < 0) {
|
||||
std::cout << "Failed to write into file " << dst_fd << std::endl;
|
||||
} else {
|
||||
std::cout << "bytes_written is " << bytes_written
|
||||
<< " is successful " << std::endl;
|
||||
}
|
||||
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
bool axi_bram_fmodel_shared_memory::importBO(uint64_t offset,
|
||||
std::string sFileName, uint64_t size) {
|
||||
int fd = -1;
|
||||
if ((fd = open(sFileName.c_str(), O_CREAT | O_RDWR,
|
||||
S_IRWXU | S_IRGRP | S_IROTH)) == -1) {
|
||||
printf("Error opening file.\n");
|
||||
};
|
||||
if (fd < 0)
|
||||
return false;
|
||||
void* pageStartOSAddressVoid = mmap(0, size,
|
||||
PROT_READ | PROT_WRITE | PROT_EXEC, MAP_SHARED, fd,
|
||||
0/*sysconf(_SC_PAGESIZE)*/);
|
||||
if (ftruncate(fd, size) < 0) {
|
||||
close(fd);
|
||||
munmap(pageStartOSAddressVoid, size);
|
||||
return false;
|
||||
}
|
||||
mFileFdMap[sFileName] = std::make_tuple(fd, pageStartOSAddressVoid, size);
|
||||
mOffsetFileMap[offset] = sFileName;
|
||||
}
|
||||
|
||||
//create a page at offset. Return if already exist
|
||||
std::string axi_bram_fmodel_shared_memory::createPage(uint64_t offset,
|
||||
uint64_t size, bool p2p) {
|
||||
std::string sFileName("");
|
||||
int fd = -1;
|
||||
auto pageIt = mPageCache.begin();
|
||||
auto pageEnd = mPageCache.end();
|
||||
while (pageIt != pageEnd) {
|
||||
uint64_t startAddress = (*pageIt).first;
|
||||
std::pair<unsigned char*, uint64_t> addressSizePair = (*pageIt).second;
|
||||
uint64_t pageSize = addressSizePair.second;
|
||||
if (offset >= startAddress && offset < startAddress + pageSize) {
|
||||
freePage(offset);
|
||||
//new offset is conflicting old addresses
|
||||
//return "";
|
||||
}
|
||||
pageIt++;
|
||||
}
|
||||
|
||||
void* pageStartOSAddressVoid = NULL;
|
||||
// TODO: DDR_BUFFER_ALIGNMENT 0x1000 (4096) this is declared in runtime shim.
|
||||
// below variable is based on it.
|
||||
size_t alignmentForBuffer = 4096; // previously sizeof(double) * 16
|
||||
|
||||
if (!p2p) {
|
||||
if (posix_memalign(&pageStartOSAddressVoid, alignmentForBuffer, size)) {
|
||||
pageStartOSAddressVoid = NULL;
|
||||
}
|
||||
} else {
|
||||
std::stringstream ssFileName;
|
||||
sFileName = get_mem_file_name(offset);
|
||||
ssFileName << sFileName << "_shared";
|
||||
sFileName = ssFileName.str(); //config::getInstance()->getDeviceDirectory() + "/" + ssFileName.str();
|
||||
if ((fd = open(sFileName.c_str(), O_CREAT | O_RDWR,
|
||||
S_IRWXU | S_IRGRP | S_IROTH)) == -1) {
|
||||
printf("Error opening file.\n");
|
||||
}
|
||||
pageStartOSAddressVoid = mmap(0, size,
|
||||
PROT_READ | PROT_WRITE | PROT_EXEC, MAP_SHARED, fd,
|
||||
0/*sysconf(_SC_PAGESIZE)*/);
|
||||
if (fd < 0) {
|
||||
munmap(pageStartOSAddressVoid, size);
|
||||
return sFileName;
|
||||
}
|
||||
|
||||
if (ftruncate(fd, size) < 0) {
|
||||
close(fd);
|
||||
munmap(pageStartOSAddressVoid, size);
|
||||
return sFileName;
|
||||
}
|
||||
}
|
||||
if (!pageStartOSAddressVoid) {
|
||||
close(fd);
|
||||
return sFileName;
|
||||
}
|
||||
|
||||
if (!sFileName.empty()) {
|
||||
mFileFdMap[sFileName] = std::make_tuple(fd, pageStartOSAddressVoid,
|
||||
size);
|
||||
mOffsetFileMap[offset] = sFileName;
|
||||
}
|
||||
|
||||
unsigned char* pageStartOSAddress = (unsigned char*) pageStartOSAddressVoid;
|
||||
mPageCache[offset] = std::make_pair(pageStartOSAddress, size);
|
||||
return sFileName;
|
||||
}
|
||||
//free page at offset. Return if already exist
|
||||
bool axi_bram_fmodel_shared_memory::freePage(uint64_t offset) {
|
||||
bool mMappedBuffer = false;
|
||||
auto itr = mOffsetFileMap.find(offset);
|
||||
int fd = -1;
|
||||
|
||||
if (itr != mOffsetFileMap.end()) {
|
||||
mMappedBuffer = true;
|
||||
std::string sFileName = (*itr).second;
|
||||
auto itr2 = mFileFdMap.find(sFileName);
|
||||
if (itr2 != mFileFdMap.end()) {
|
||||
fd = std::get<0>((*itr2).second);
|
||||
void* pPtr = std::get<1>((*itr2).second);
|
||||
int size = std::get<2>((*itr2).second);
|
||||
munmap(pPtr, size);
|
||||
mFileFdMap.erase(itr2);
|
||||
}
|
||||
}
|
||||
auto pageIt = mPageCache.find(offset);
|
||||
if (pageIt != mPageCache.end()) {
|
||||
std::pair<unsigned char*, uint64_t> addressSizePair = (*pageIt).second;
|
||||
unsigned char* osAddress = addressSizePair.first;
|
||||
uint64_t size = addressSizePair.second;
|
||||
if (osAddress) {
|
||||
if (!mMappedBuffer)
|
||||
free((void *) osAddress);
|
||||
else {
|
||||
munmap(osAddress, size);
|
||||
if (fd != -1) {
|
||||
close(fd);
|
||||
}
|
||||
}
|
||||
}
|
||||
mPageCache.erase(pageIt);
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
bool axi_bram_fmodel_shared_memory::createMMappedBuffer(
|
||||
uint64_t base_address, uint64_t size, std::string& buffer_filename) {
|
||||
buffer_filename = createPage(base_address, size, true);
|
||||
return true;
|
||||
}
|
||||
|
||||
std::string axi_bram_fmodel_shared_memory::get_mem_file_name(
|
||||
uint64_t pageIdx) //,enum fileType file_type)
|
||||
{
|
||||
std::string file_name;
|
||||
std::string socket_id;
|
||||
std::string pid;
|
||||
std::string deviceName("");
|
||||
std::string user("");
|
||||
if (getenv("EMULATION_SOCKETID")) {
|
||||
socket_id = getenv("EMULATION_SOCKETID");
|
||||
std::size_t foundLast = socket_id.find_last_of("_");
|
||||
std::size_t foundFirst = socket_id.find_first_of("_");
|
||||
if (foundLast != std::string::npos) {
|
||||
pid = socket_id.substr(foundLast + 1);
|
||||
}
|
||||
if (foundFirst != std::string::npos) {
|
||||
deviceName = socket_id.substr(0, foundFirst);
|
||||
}
|
||||
}
|
||||
|
||||
if (getenv("USER") != NULL) {
|
||||
user = getenv("USER");
|
||||
}
|
||||
std::string file_path("");
|
||||
std::string sEmRunDir("");
|
||||
|
||||
if (getenv("EMULATION_RUN_DIR")) {
|
||||
sEmRunDir = getenv("EMULATION_RUN_DIR");
|
||||
} else {
|
||||
sEmRunDir = "/tmp/" + user + "/hw_em/";
|
||||
}
|
||||
|
||||
file_path = sEmRunDir + "/" + module_name + "/";
|
||||
std::stringstream mkdirCommand;
|
||||
mkdirCommand << "mkdir -p " << file_path;
|
||||
;
|
||||
struct stat statBuf;
|
||||
if (stat(file_path.c_str(), &statBuf) == -1) {
|
||||
system(mkdirCommand.str().c_str());
|
||||
}
|
||||
file_name = file_path + module_name + "_" + std::to_string(pageIdx);
|
||||
return file_name;
|
||||
}
|
||||
|
||||
+85
@@ -0,0 +1,85 @@
|
||||
// (c) Copyright 1995-2021, 2023 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
////////////////////////////////////////////////////////////
|
||||
|
||||
#ifndef axi_bram_FMODEL_SHARED_MEMORY__H
|
||||
#define axi_bram_FMODEL_SHARED_MEMORY__H
|
||||
|
||||
#include "axi_bram_fmodel_base.h"
|
||||
#include "report_handler.h"
|
||||
|
||||
class axi_bram_fmodel_shared_memory: public axi_bram_fmodel_base {
|
||||
public:
|
||||
unsigned int writeDevMem(uint64_t offset, void* src, unsigned int size);
|
||||
unsigned int readDevMem(uint64_t offset, void* dest, unsigned int size);
|
||||
bool createMMappedBuffer(uint64_t base_address, uint64_t size,
|
||||
std::string& buffer_filename);
|
||||
unsigned char* get_page(uint64_t offset, std::string& p2pFileName,
|
||||
uint64_t size = 0);
|
||||
uint64_t getBaseDdrAddress(uint64_t offset); //get the DDR base address of offset
|
||||
bool copyBO(uint64_t offset, std::string dst_filename, uint64_t size,
|
||||
uint64_t src_offset, uint64_t dst_offset);
|
||||
bool importBO(uint64_t offset, std::string dst_filename, uint64_t size);
|
||||
std::string createPage(uint64_t offset, uint64_t size, bool p2p); //create a page of size "size" and add it in mPageCache Map.
|
||||
bool freePage(uint64_t offset); //free page and remove it from mPageCache Map.
|
||||
std::string get_mem_file_name(uint64_t pageIdx);
|
||||
|
||||
public:
|
||||
axi_bram_fmodel_shared_memory(std::string p_module_name,
|
||||
xsc::common_cpp::report_handler* report_handler,
|
||||
uint64_t addr_size);
|
||||
~ axi_bram_fmodel_shared_memory();
|
||||
void reset_fmodel();
|
||||
private:
|
||||
//Paging
|
||||
std::map<uint64_t, std::pair<unsigned char*, uint64_t> > mPageCache; // this map is used to store ddrAddress and OsAddress Mapping.
|
||||
static std::map<std::string, std::tuple<uint64_t, void*, int> > mFileFdMap; //filename and fd map
|
||||
std::map<uint64_t, std::string> mOffsetFileMap; //offset and filename map
|
||||
xsc::common_cpp::report_handler *m_report_handler;
|
||||
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
+406
@@ -0,0 +1,406 @@
|
||||
// (c) Copyright 1995-2021, 2023 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
////////////////////////////////////////////////////////////
|
||||
|
||||
#include "axi_bram_memory_imp.h"
|
||||
#include "P2P_XTLM_extension.h"
|
||||
|
||||
#include <sstream>
|
||||
#include <bitset>
|
||||
|
||||
class axi_bram_memory_imp::target_rd_util: public xtlm::xtlm_aximm_target_rd_socket_util {
|
||||
public:
|
||||
target_rd_util(sc_core::sc_module_name p_name,
|
||||
xtlm::aximm::granularity g_hint, int width_p,
|
||||
axi_bram_memory_imp* _parent) :
|
||||
xtlm::xtlm_aximm_target_rd_socket_util(p_name, g_hint, width_p) {
|
||||
this->parent = _parent;
|
||||
}
|
||||
unsigned int transport_dbg_cb(xtlm::aximm_payload& trans) {
|
||||
return parent->transport_dbg(trans);
|
||||
}
|
||||
private:
|
||||
axi_bram_memory_imp* parent;
|
||||
};
|
||||
|
||||
class axi_bram_memory_imp::target_wr_util: public xtlm::xtlm_aximm_target_wr_socket_util {
|
||||
public:
|
||||
target_wr_util(sc_core::sc_module_name p_name,
|
||||
xtlm::aximm::granularity g_hint, int width_p,
|
||||
axi_bram_memory_imp* _parent) :
|
||||
xtlm::xtlm_aximm_target_wr_socket_util(p_name, g_hint, width_p) {
|
||||
this->parent = _parent;
|
||||
}
|
||||
unsigned int transport_dbg_cb(xtlm::aximm_payload& trans) {
|
||||
return parent->transport_dbg(trans);
|
||||
}
|
||||
private:
|
||||
axi_bram_memory_imp* parent;
|
||||
};
|
||||
|
||||
axi_bram_memory_imp::axi_bram_memory_imp(
|
||||
const sc_module_name& module_name,
|
||||
xsc::common_cpp::properties& properties) :
|
||||
sc_module(module_name) {
|
||||
m_data_width = properties.getLongLong("C_S_AXI_DATA_WIDTH");
|
||||
m_mem_addr_width = properties.getLongLong("C_MEMORY_DEPTH");
|
||||
m_mem_addr_width *= m_data_width;
|
||||
|
||||
target_0_rd_socket = new xtlm::xtlm_aximm_target_socket(
|
||||
"saxi_hbmx_imp_rd_socket", m_data_width);
|
||||
target_0_wr_socket = new xtlm::xtlm_aximm_target_socket("saxi_cq_wrie_skt",
|
||||
m_data_width);
|
||||
m_target_0_rd_socket_util = new target_rd_util(
|
||||
"saxi_hbmx_imp_rd_socket_util",
|
||||
xtlm::aximm::granularity::TRANSACTION, m_data_width, this);
|
||||
m_target_0_wr_socket_util = new target_wr_util(
|
||||
"saxi_hbmx_imp_wr_socket_util",
|
||||
xtlm::aximm::granularity::TRANSACTION, m_data_width, this);
|
||||
target_0_rd_socket->bind((m_target_0_rd_socket_util->rd_socket));
|
||||
target_0_wr_socket->bind((m_target_0_wr_socket_util->wr_socket));
|
||||
std::string mod_name = name();
|
||||
m_report_handler = new xsc::common_cpp::report_handler(mod_name);
|
||||
if (!getenv("SDX_USE_SHARED_MEMORY"))
|
||||
m_mem_handler = new axi_bram_ram_fmodel(this->name(),
|
||||
m_report_handler, m_mem_addr_width); //name() returns hierarchical name of ddr systemc module instance
|
||||
else
|
||||
m_mem_handler = new axi_bram_fmodel_shared_memory(this->name(),
|
||||
m_report_handler, m_mem_addr_width); //name() returns hierarchical name of ddr systemc module instance
|
||||
|
||||
//m_mem_handler=new axi_bram_memory_fmodel_base(mod_name,m_report_handler,m_mem_addr_width);
|
||||
|
||||
SC_METHOD(methodProcessTransactionRead);
|
||||
sensitive << m_target_0_rd_socket_util->transaction_available;
|
||||
sensitive << m_target_0_rd_socket_util->data_sampled;
|
||||
dont_initialize();
|
||||
|
||||
//m_report_handler->set_verbosity_level(xsc::common_cpp::VERBOSITY::DEBUG);
|
||||
SC_METHOD(methodProcessTransactionWrite);
|
||||
sensitive << m_target_0_wr_socket_util->transaction_available;
|
||||
sensitive << m_target_0_wr_socket_util->resp_sampled;
|
||||
dont_initialize();
|
||||
}
|
||||
|
||||
axi_bram_memory_imp::~axi_bram_memory_imp() {
|
||||
delete target_0_rd_socket;
|
||||
delete target_0_wr_socket;
|
||||
delete m_target_0_rd_socket_util;
|
||||
delete m_target_0_wr_socket_util;
|
||||
delete m_report_handler;
|
||||
delete m_mem_handler;
|
||||
}
|
||||
|
||||
void axi_bram_memory_imp::methodProcessTransactionRead() {
|
||||
std::stringstream ss;
|
||||
if (m_target_0_rd_socket_util->is_trans_available()) {
|
||||
xtlm::aximm_payload* trans =
|
||||
m_target_0_rd_socket_util->get_transaction();
|
||||
sc_core::sc_time delay = SC_ZERO_TIME;
|
||||
uint64_t max_address = m_mem_addr_width;
|
||||
uint64_t address = trans->get_address() % max_address;
|
||||
uint64_t tranSize = trans->get_data_length();
|
||||
ss.clear();
|
||||
std::string des;
|
||||
if (m_report_handler->get_verbosity_level() == xsc::common_cpp::DEBUG) {
|
||||
trans->get_log(des, 1);
|
||||
ss << name() << ": Received Read Request " << des << std::endl;
|
||||
XSC_REPORT_INFO_VERB((*m_report_handler), "1", ss.str().c_str(),
|
||||
DEBUG);
|
||||
}
|
||||
if ((address + tranSize) > max_address) {
|
||||
ss.clear();
|
||||
ss << name() << ": Invalid Read Request " << std::endl << des
|
||||
<< std::endl;
|
||||
XSC_REPORT_ERROR((*m_report_handler), "1", ss.str().c_str());
|
||||
trans->set_response_status(xtlm::XTLM_ADDRESS_ERROR_RESPONSE);
|
||||
} else {
|
||||
ss.clear();
|
||||
trans->set_response_status(xtlm::XTLM_OK_RESPONSE);
|
||||
unsigned char* data_ptr = trans->get_data_ptr();
|
||||
m_mem_handler->readDevMem(address, data_ptr, tranSize);
|
||||
}
|
||||
m_rd_req_vec.push_back(trans);
|
||||
}
|
||||
if (m_rd_req_vec.empty() == false
|
||||
&& m_target_0_rd_socket_util->is_master_ready()) {
|
||||
ss.clear();
|
||||
xtlm::aximm_payload* trans = m_rd_req_vec.front();
|
||||
if (m_report_handler->get_verbosity_level() == xsc::common_cpp::DEBUG) {
|
||||
std::string des;
|
||||
trans->get_log(des, 1);
|
||||
ss << name() << ": Sending Read Response " << std::endl << des
|
||||
<< std::endl;
|
||||
XSC_REPORT_INFO_VERB((*m_report_handler), "1", ss.str().c_str(),
|
||||
DEBUG);
|
||||
}
|
||||
sc_core::sc_time delay = SC_ZERO_TIME;
|
||||
m_target_0_rd_socket_util->send_data(*trans, delay);
|
||||
m_rd_req_vec.pop_front();
|
||||
}
|
||||
}
|
||||
|
||||
void axi_bram_memory_imp::methodProcessTransactionWrite() {
|
||||
std::stringstream ss;
|
||||
if (m_target_0_wr_socket_util->is_trans_available()) {
|
||||
xtlm::aximm_payload* trans =
|
||||
m_target_0_wr_socket_util->get_transaction();
|
||||
uint64_t max_address = m_mem_addr_width;
|
||||
uint64_t address = trans->get_address() % max_address;
|
||||
uint64_t tranSize = trans->get_data_length();
|
||||
//Check for the address range
|
||||
trans->set_response_status(xtlm::XTLM_OK_RESPONSE);
|
||||
if ((address + tranSize) > max_address) {
|
||||
ss.clear();
|
||||
std::string des;
|
||||
trans->get_log(des, 1);
|
||||
ss << name() << ": Invalid Write Request " << std::endl << des
|
||||
<< std::endl;
|
||||
XSC_REPORT_ERROR((*m_report_handler), "1", ss.str().c_str());
|
||||
trans->set_response_status(xtlm::XTLM_ADDRESS_ERROR_RESPONSE);
|
||||
|
||||
} else {
|
||||
xtlm::xtlm_extension<xsc::extension::P2P_XTLM_extension>* bExt;
|
||||
trans->get_extension(bExt);
|
||||
xsc::extension::P2P_XTLM_extension * ext =
|
||||
dynamic_cast<xsc::extension::P2P_XTLM_extension *>(bExt);
|
||||
if (ext != nullptr) {
|
||||
std::string filename;
|
||||
bool ret = true;
|
||||
if (ext->getType() == xsc::extension::TYPE::ALLOC_BO)
|
||||
ret = m_mem_handler->createMMappedBuffer(
|
||||
address, ext->getSize(), filename);
|
||||
else if (ext->getType() == xsc::extension::TYPE::FREE_BO)
|
||||
ret = m_mem_handler->freePage(address);
|
||||
else if (ext->getType() == xsc::extension::TYPE::IMPORT_BO) {
|
||||
ret = m_mem_handler->importBO(address,
|
||||
ext->getFileName(), ext->getSize());
|
||||
} else if (ext->getType() == xsc::extension::TYPE::COPY_BO) {
|
||||
ret = m_mem_handler->copyBO(address,
|
||||
ext->getFileName(), ext->getSize(),
|
||||
ext->getSrcOffset(), ext->getDstOffset());
|
||||
}
|
||||
ext->setResponse(ret);
|
||||
ext->setFileName(filename);
|
||||
}
|
||||
|
||||
else if (!trans->get_byte_enable_ptr()) {
|
||||
unsigned char* data_ptr = trans->get_data_ptr();
|
||||
if (m_report_handler->get_verbosity_level()
|
||||
== xsc::common_cpp::DEBUG) {
|
||||
ss.clear();
|
||||
std::string des;
|
||||
trans->get_log(des, 1);
|
||||
ss << name() << ": Received Write Request " << std::endl
|
||||
<< des << std::endl;
|
||||
XSC_REPORT_INFO_VERB((*m_report_handler), "1",
|
||||
ss.str().c_str(), DEBUG);
|
||||
}
|
||||
|
||||
m_mem_handler->writeDevMem(address, data_ptr, tranSize);
|
||||
} else {
|
||||
if (m_report_handler->get_verbosity_level()
|
||||
== xsc::common_cpp::DEBUG) {
|
||||
ss.clear();
|
||||
std::string des;
|
||||
trans->get_log(des, 1);
|
||||
ss << name() << ": Received Write Request " << std::endl
|
||||
<< des << std::endl;
|
||||
XSC_REPORT_INFO_VERB((*m_report_handler), "1",
|
||||
ss.str().c_str(), DEBUG);
|
||||
}
|
||||
unsigned char* data_ptr = trans->get_data_ptr();
|
||||
unsigned char* byte_enable_ptr = trans->get_byte_enable_ptr();
|
||||
uint64_t byte_enable_len = trans->get_byte_enable_length();
|
||||
uint32_t index = 0;
|
||||
for (index = 1; index <= tranSize; index++) {
|
||||
bool byteEn = byte_enable_ptr[(index - 1) % byte_enable_len];
|
||||
if (byteEn) {
|
||||
m_mem_handler->writeDevMem(index + address - 1,
|
||||
data_ptr + (index - 1), 1);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
m_wr_resp_vec.push_back(trans);
|
||||
}
|
||||
if (m_wr_resp_vec.empty() == false
|
||||
&& m_target_0_wr_socket_util->is_master_ready()) {
|
||||
std::stringstream msg;
|
||||
sc_core::sc_time delay = SC_ZERO_TIME;
|
||||
xtlm::aximm_payload* trans = m_wr_resp_vec.front();
|
||||
if (m_report_handler->get_verbosity_level() == xsc::common_cpp::DEBUG) {
|
||||
ss.clear();
|
||||
std::string des;
|
||||
trans->get_log(des, 1);
|
||||
ss << name() << ": Sending Write Request " << std::endl << des
|
||||
<< std::endl;
|
||||
XSC_REPORT_INFO_VERB((*m_report_handler), "1", ss.str().c_str(),
|
||||
DEBUG);
|
||||
}
|
||||
m_target_0_wr_socket_util->send_resp(*trans, delay);
|
||||
m_wr_resp_vec.pop_front();
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
unsigned int axi_bram_memory_imp::transport_dbg(xtlm::aximm_payload& trans) {
|
||||
if (trans.get_command() == xtlm::XTLM_READ_COMMAND) {
|
||||
return transport_dbg_rd(trans);
|
||||
} else if (trans.get_command() == xtlm::XTLM_WRITE_COMMAND) {
|
||||
return transport_dbg_wr(trans);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
unsigned int axi_bram_memory_imp::transport_dbg_rd(
|
||||
xtlm::aximm_payload& trans) {
|
||||
sc_core::sc_time delay = SC_ZERO_TIME;
|
||||
uint64_t max_address = m_mem_addr_width;
|
||||
uint64_t address = trans.get_address() % max_address;
|
||||
uint64_t tranSize = trans.get_data_length();
|
||||
std::stringstream ss;
|
||||
ss.clear();
|
||||
std::string des;
|
||||
if (m_report_handler->get_verbosity_level() == xsc::common_cpp::DEBUG) {
|
||||
trans.get_log(des, 1);
|
||||
ss << name() << ": Received Debug Read Request " << des << std::endl;
|
||||
XSC_REPORT_INFO_VERB((*m_report_handler), "1", ss.str().c_str(), DEBUG);
|
||||
}
|
||||
if ((address + tranSize) > max_address) {
|
||||
ss.clear();
|
||||
ss << name() << ": Invalid Debug Read Request " << std::endl << des
|
||||
<< std::endl;
|
||||
XSC_REPORT_ERROR((*m_report_handler), "1", ss.str().c_str());
|
||||
trans.set_response_status(xtlm::XTLM_ADDRESS_ERROR_RESPONSE);
|
||||
return 0;
|
||||
} else {
|
||||
ss.clear();
|
||||
trans.set_response_status(xtlm::XTLM_OK_RESPONSE);
|
||||
unsigned char* data_ptr = trans.get_data_ptr();
|
||||
m_mem_handler->readDevMem(address, data_ptr, tranSize);
|
||||
return trans.get_data_length();
|
||||
}
|
||||
}
|
||||
|
||||
unsigned int axi_bram_memory_imp::transport_dbg_wr(
|
||||
xtlm::aximm_payload& trans) {
|
||||
std::stringstream ss;
|
||||
uint64_t max_address = m_mem_addr_width;
|
||||
uint64_t address = trans.get_address() % max_address;
|
||||
uint64_t tranSize = trans.get_data_length();
|
||||
//Check for the address range
|
||||
trans.set_response_status(xtlm::XTLM_OK_RESPONSE);
|
||||
if ((address + tranSize) > max_address) {
|
||||
ss.clear();
|
||||
std::string des;
|
||||
trans.get_log(des, 1);
|
||||
ss << name() << ": Invalid Debug Write Request " << std::endl << des
|
||||
<< std::endl;
|
||||
XSC_REPORT_ERROR((*m_report_handler), "1", ss.str().c_str());
|
||||
trans.set_response_status(xtlm::XTLM_ADDRESS_ERROR_RESPONSE);
|
||||
return 0;
|
||||
}
|
||||
xtlm::xtlm_extension<xsc::extension::P2P_XTLM_extension>* bExt;
|
||||
trans.get_extension(bExt);
|
||||
xsc::extension::P2P_XTLM_extension * ext =
|
||||
dynamic_cast<xsc::extension::P2P_XTLM_extension *>(bExt);
|
||||
if (ext != nullptr) {
|
||||
std::string filename;
|
||||
bool ret = true;
|
||||
if (ext->getType() == xsc::extension::TYPE::ALLOC_BO)
|
||||
ret = m_mem_handler->createMMappedBuffer(address,
|
||||
ext->getSize(), filename);
|
||||
else if (ext->getType() == xsc::extension::TYPE::FREE_BO)
|
||||
ret = m_mem_handler->freePage(address);
|
||||
else if (ext->getType() == xsc::extension::TYPE::IMPORT_BO) {
|
||||
ret = m_mem_handler->importBO(address,
|
||||
ext->getFileName(), ext->getSize());
|
||||
} else if (ext->getType() == xsc::extension::TYPE::COPY_BO) {
|
||||
ret = m_mem_handler->copyBO(address, ext->getFileName(),
|
||||
ext->getSize(), ext->getSrcOffset(), ext->getDstOffset());
|
||||
}
|
||||
ext->setResponse(ret);
|
||||
ext->setFileName(filename);
|
||||
return 0;
|
||||
}
|
||||
|
||||
else if (!trans.get_byte_enable_ptr()) {
|
||||
unsigned char* data_ptr = trans.get_data_ptr();
|
||||
if (m_report_handler->get_verbosity_level() == xsc::common_cpp::DEBUG) {
|
||||
ss.clear();
|
||||
std::string des;
|
||||
trans.get_log(des, 1);
|
||||
ss << name() << ": Received Debug Write Request " << std::endl
|
||||
<< des << std::endl;
|
||||
XSC_REPORT_INFO_VERB((*m_report_handler), "1", ss.str().c_str(),
|
||||
DEBUG);
|
||||
}
|
||||
m_mem_handler->writeDevMem(address, data_ptr, tranSize);
|
||||
return tranSize;
|
||||
} else {
|
||||
if (m_report_handler->get_verbosity_level() == xsc::common_cpp::DEBUG) {
|
||||
ss.clear();
|
||||
std::string des;
|
||||
trans.get_log(des, 1);
|
||||
ss << name() << ": Received Debug Write Request " << std::endl
|
||||
<< des << std::endl;
|
||||
XSC_REPORT_INFO_VERB((*m_report_handler), "1", ss.str().c_str(),
|
||||
DEBUG);
|
||||
}
|
||||
unsigned char* data_ptr = trans.get_data_ptr();
|
||||
unsigned char* byte_enable_ptr = trans.get_byte_enable_ptr();
|
||||
uint64_t byte_enable_len = trans.get_byte_enable_length();
|
||||
uint32_t index = 0;
|
||||
for (index = 1; index <= tranSize; index++) {
|
||||
bool byteEn = byte_enable_ptr[(index - 1) % byte_enable_len];
|
||||
if (byteEn) {
|
||||
m_mem_handler->writeDevMem(index + address - 1,
|
||||
data_ptr + (index - 1), 1);
|
||||
}
|
||||
}
|
||||
return tranSize;
|
||||
}
|
||||
}
|
||||
|
||||
+87
@@ -0,0 +1,87 @@
|
||||
// (c) Copyright 1995-2021, 2023 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
////////////////////////////////////////////////////////////
|
||||
|
||||
#ifndef _SIM_HBMX_IMP_H_
|
||||
#define _SIM_HBMX_IMP_H_
|
||||
|
||||
#include "xtlm.h"
|
||||
#include "report_handler.h"
|
||||
#include <list>
|
||||
#include "axi_bram_fmodel_base.h"
|
||||
#include "axi_bram_ram_fmodel.h"
|
||||
#include "axi_bram_fmodel_shared_memory.h"
|
||||
|
||||
class axi_bram_memory_imp: public sc_core::sc_module {
|
||||
public:
|
||||
//Workaround to implement Debug transport
|
||||
class target_rd_util;
|
||||
class target_wr_util;
|
||||
axi_bram_memory_imp(const sc_module_name& module_name,
|
||||
xsc::common_cpp::properties&);
|
||||
virtual ~axi_bram_memory_imp();SC_HAS_PROCESS(axi_bram_memory_imp);
|
||||
//Slave interface used to R/W to HBM Memory
|
||||
xtlm::xtlm_aximm_target_socket* target_0_rd_socket;
|
||||
xtlm::xtlm_aximm_target_socket* target_0_wr_socket;
|
||||
private:
|
||||
target_rd_util* m_target_0_rd_socket_util;
|
||||
target_wr_util* m_target_0_wr_socket_util;
|
||||
uint64_t m_mem_addr_width;
|
||||
uint64_t m_data_width;
|
||||
std::list<xtlm::aximm_payload*> m_rd_req_vec;
|
||||
std::list<xtlm::aximm_payload*> m_wr_req_vec;
|
||||
std::list<xtlm::aximm_payload*> m_wr_data_vec;
|
||||
std::list<xtlm::aximm_payload*> m_wr_resp_vec;
|
||||
void methodProcessTransactionRead();
|
||||
void methodProcessTransactionWrite();
|
||||
xsc::common_cpp::report_handler* m_report_handler;
|
||||
axi_bram_fmodel_base* m_mem_handler;
|
||||
unsigned int transport_dbg(xtlm::aximm_payload&);
|
||||
unsigned int transport_dbg_wr(xtlm::aximm_payload&);
|
||||
unsigned int transport_dbg_rd(xtlm::aximm_payload&);
|
||||
};
|
||||
|
||||
#endif /* _SIM_HBMX_IMP_H_ */
|
||||
|
||||
+308
@@ -0,0 +1,308 @@
|
||||
// (c) Copyright 1995-2021, 2023 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
////////////////////////////////////////////////////////////
|
||||
|
||||
#include "axi_bram_ram_fmodel.h"
|
||||
|
||||
#include <sys/stat.h>
|
||||
#include <sstream>
|
||||
|
||||
axi_bram_ram_fmodel::~axi_bram_ram_fmodel() {
|
||||
for (auto& mem : pageCache) {
|
||||
delete mem.second;
|
||||
}
|
||||
}
|
||||
|
||||
axi_bram_ram_fmodel::axi_bram_ram_fmodel(
|
||||
std::string p_module_name,
|
||||
xsc::common_cpp::report_handler* report_handler, uint64_t addr_size) :
|
||||
axi_bram_fmodel_base(p_module_name, report_handler, addr_size) {
|
||||
std::stringstream msg;
|
||||
msg << p_module_name << " : ";
|
||||
msg << " Initializing " << std::endl;
|
||||
|
||||
module_name = p_module_name;
|
||||
m_report_handler = report_handler;
|
||||
m_mem_addr_width = addr_size;
|
||||
report_handler->report("1", msg.str().c_str(), xsc::common_cpp::INFO,
|
||||
xsc::common_cpp::VERBOSITY::DEBUG);
|
||||
}
|
||||
|
||||
unsigned int axi_bram_ram_fmodel::writeDevMem(uint64_t offset, void* src,
|
||||
unsigned int size) {
|
||||
if (m_report_handler->get_verbosity_level() == xsc::common_cpp::DEBUG) {
|
||||
std::stringstream msg;
|
||||
msg << module_name << " : ";
|
||||
msg << " Writing Memory Address = " << offset << " Size = " << size
|
||||
<< " Data =" << std::endl;
|
||||
uint64_t counter = 0;
|
||||
for (int i = 0; i < size; i++) {
|
||||
msg << (unsigned int) (((unsigned char*) src)[i]) << " ";
|
||||
if (counter <= 16)
|
||||
counter++;
|
||||
else {
|
||||
counter = 0;
|
||||
msg << std::endl;
|
||||
}
|
||||
}
|
||||
msg << std::endl;
|
||||
m_report_handler->report("1", msg.str().c_str(), xsc::common_cpp::INFO,
|
||||
xsc::common_cpp::VERBOSITY::DEBUG);
|
||||
}
|
||||
uint64_t written_bytes = 0;
|
||||
uint64_t addr = offset;
|
||||
while (written_bytes < size) {
|
||||
uint64_t src_offset = written_bytes;
|
||||
std::string sFileName("");
|
||||
unsigned char* page_ptr = get_page(addr, sFileName);
|
||||
uint64_t page_addr = addr & ~(-1 << ADDRBITS);
|
||||
|
||||
unsigned char* dest_buf_ptr = page_ptr + page_addr;
|
||||
unsigned char* src_buf_ptr = (unsigned char*) (src) + src_offset;
|
||||
|
||||
uint64_t remaining_bytes_to_write = size - written_bytes;
|
||||
uint64_t unaligned_bytes_in_addr = (addr & ~(-1 << ADDRBITS));
|
||||
uint64_t bytes_upto_next_alignment = (0x1 << ADDRBITS)
|
||||
- unaligned_bytes_in_addr;
|
||||
|
||||
uint64_t buf_size = 0;
|
||||
if (bytes_upto_next_alignment > remaining_bytes_to_write) {
|
||||
buf_size = remaining_bytes_to_write;
|
||||
} else {
|
||||
buf_size = bytes_upto_next_alignment;
|
||||
}
|
||||
memcpy(dest_buf_ptr, src_buf_ptr, buf_size);
|
||||
written_bytes += buf_size;
|
||||
addr += buf_size;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
unsigned int axi_bram_ram_fmodel::readDevMem(uint64_t offset, void* dest,
|
||||
unsigned int size) {
|
||||
uint64_t read_bytes = 0;
|
||||
uint64_t addr = offset;
|
||||
|
||||
while (read_bytes < size) {
|
||||
uint64_t dest_offset = read_bytes;
|
||||
std::string sFileName("");
|
||||
unsigned char* page_ptr = get_page(addr, sFileName);
|
||||
uint64_t page_addr = addr & ~(-1 << ADDRBITS);
|
||||
|
||||
unsigned char* src_buf_ptr = page_ptr + page_addr;
|
||||
unsigned char* dest_buf_ptr = (unsigned char*) (dest) + dest_offset;
|
||||
|
||||
uint64_t remaining_bytes_to_read = size - read_bytes;
|
||||
uint64_t unaligned_bytes_in_addr = (addr & ~(-1 << ADDRBITS));
|
||||
uint64_t bytes_upto_next_alignment = (0x1 << ADDRBITS)
|
||||
- unaligned_bytes_in_addr;
|
||||
|
||||
uint64_t buf_size = 0;
|
||||
if (bytes_upto_next_alignment > remaining_bytes_to_read) {
|
||||
buf_size = remaining_bytes_to_read;
|
||||
} else {
|
||||
buf_size = bytes_upto_next_alignment;
|
||||
}
|
||||
memcpy(dest_buf_ptr, src_buf_ptr, buf_size);
|
||||
read_bytes += buf_size;
|
||||
addr += buf_size;
|
||||
}
|
||||
if (m_report_handler->get_verbosity_level() == xsc::common_cpp::DEBUG) {
|
||||
std::stringstream msg;
|
||||
msg << module_name << " : ";
|
||||
msg << " Reading Memory Address = " << offset << " Size = " << size
|
||||
<< " Data = " << std::endl;
|
||||
uint64_t counter = 0;
|
||||
for (int i = 0; i < size; i++) {
|
||||
msg << (unsigned int) (((unsigned char*) dest)[i]) << " ";
|
||||
if (counter <= 16)
|
||||
counter++;
|
||||
else {
|
||||
counter = 0;
|
||||
msg << std::endl;
|
||||
}
|
||||
}
|
||||
msg << std::endl;
|
||||
m_report_handler->report("1", msg.str().c_str(), xsc::common_cpp::INFO,
|
||||
xsc::common_cpp::VERBOSITY::DEBUG);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
unsigned char* axi_bram_ram_fmodel::get_page(uint64_t offset,
|
||||
std::string& p2pFileName, uint64_t size) {
|
||||
uint64_t page_idx = offset >> ADDRBITS;
|
||||
std::string file_name = get_mem_file_name(page_idx);
|
||||
if (pageCache.size() > N_1MBARRAYS) {
|
||||
std::cerr
|
||||
<< "Out of Memory. DDR model does not support this much of memory\n";
|
||||
exit(1);
|
||||
} else {
|
||||
FILE* pFile = NULL;
|
||||
if (pageCache.find(page_idx) != pageCache.end()) {
|
||||
return pageCache[page_idx];
|
||||
} else {
|
||||
|
||||
if (size != 0) {
|
||||
int fd = -1;
|
||||
p2pFileName = file_name + "_shared";
|
||||
if ((fd = open(p2pFileName.c_str(), O_CREAT | O_RDWR,
|
||||
S_IRWXU | S_IRGRP | S_IROTH)) == -1) {
|
||||
printf("Error opening file.\n");
|
||||
}
|
||||
void* pageStartOSAddressVoid = mmap(0, size,
|
||||
PROT_READ | PROT_WRITE | PROT_EXEC, MAP_SHARED, fd,
|
||||
0/*sysconf(_SC_PAGESIZE)*/);
|
||||
if (fd < 0) {
|
||||
munmap(pageStartOSAddressVoid, size);
|
||||
p2pFileName = "";
|
||||
}
|
||||
|
||||
if (ftruncate(fd, size) < 0) {
|
||||
close(fd);
|
||||
munmap(pageStartOSAddressVoid, size);
|
||||
p2pFileName = "";
|
||||
}
|
||||
if (!p2pFileName.empty()) {
|
||||
unsigned char* pagePtr =
|
||||
(unsigned char*) pageStartOSAddressVoid;
|
||||
while (size > 0) {
|
||||
pageCache[page_idx] = pagePtr;
|
||||
page_idx = page_idx + 1;
|
||||
pagePtr = pagePtr + PAGESIZE;
|
||||
if (size <= PAGESIZE)
|
||||
break;
|
||||
size = size - PAGESIZE;
|
||||
std::cout << "page_idx is " << page_idx << std::endl;
|
||||
std::cout << "size is " << size << std::endl;
|
||||
}
|
||||
return (unsigned char*) pageStartOSAddressVoid;
|
||||
}
|
||||
}
|
||||
|
||||
pageCache[page_idx] = new unsigned char[PAGESIZE];
|
||||
//for(int i = 0; i < ONE_MB;i++){
|
||||
// pageCache[page_idx][i] = 0x0;
|
||||
//}
|
||||
return pageCache[page_idx];
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void axi_bram_ram_fmodel::init_fmodel() {
|
||||
|
||||
}
|
||||
|
||||
bool axi_bram_ram_fmodel::createMMappedBuffer(uint64_t base_address,
|
||||
uint64_t size, std::string& buffer_filename) {
|
||||
return true;
|
||||
}
|
||||
|
||||
bool axi_bram_ram_fmodel::freePage(uint64_t base_address) {
|
||||
return true;
|
||||
}
|
||||
|
||||
bool axi_bram_ram_fmodel::copyBO(uint64_t offset,
|
||||
std::string dst_filename, uint64_t size, uint64_t src_offset,
|
||||
uint64_t dst_offset) {
|
||||
return true;
|
||||
|
||||
}
|
||||
|
||||
bool axi_bram_ram_fmodel::importBO(uint64_t offset,
|
||||
std::string dst_filename, uint64_t size) {
|
||||
return true;
|
||||
}
|
||||
|
||||
std::string axi_bram_ram_fmodel::get_mem_file_name(uint64_t pageIdx) //,enum fileType file_type)
|
||||
{
|
||||
std::string file_name;
|
||||
std::string socket_id;
|
||||
std::string pid;
|
||||
std::string deviceName("");
|
||||
std::string user("");
|
||||
if (getenv("EMULATION_SOCKETID")) {
|
||||
socket_id = getenv("EMULATION_SOCKETID");
|
||||
std::size_t foundLast = socket_id.find_last_of("_");
|
||||
std::size_t foundFirst = socket_id.find_first_of("_");
|
||||
if (foundLast != std::string::npos) {
|
||||
pid = socket_id.substr(foundLast + 1);
|
||||
}
|
||||
if (foundFirst != std::string::npos) {
|
||||
deviceName = socket_id.substr(0, foundFirst);
|
||||
}
|
||||
}
|
||||
|
||||
if (getenv("USER") != NULL) {
|
||||
user = getenv("USER");
|
||||
}
|
||||
std::string file_path("");
|
||||
std::string sEmRunDir("");
|
||||
|
||||
if (getenv("EMULATION_RUN_DIR")) {
|
||||
sEmRunDir = getenv("EMULATION_RUN_DIR");
|
||||
} else {
|
||||
sEmRunDir = "/tmp/" + user + "/hw_em/";
|
||||
}
|
||||
|
||||
file_path = sEmRunDir + "/" + module_name + "/";
|
||||
std::stringstream mkdirCommand;
|
||||
mkdirCommand << "mkdir -p " << file_path;
|
||||
;
|
||||
struct stat statBuf;
|
||||
if (stat(file_path.c_str(), &statBuf) == -1) {
|
||||
system(mkdirCommand.str().c_str());
|
||||
}
|
||||
file_name = file_path + module_name + "_" + std::to_string(pageIdx);
|
||||
if (m_report_handler->get_verbosity_level()
|
||||
== xsc::common_cpp::VERBOSITY::DEBUG) {
|
||||
std::stringstream m_ss;
|
||||
m_ss.str("");
|
||||
m_ss << "ddr fmodel file_name: " << file_name << std::endl;
|
||||
m_report_handler->report("1", m_ss.str().c_str(), xsc::common_cpp::INFO,
|
||||
xsc::common_cpp::VERBOSITY::DEBUG);
|
||||
}
|
||||
return file_name;
|
||||
}
|
||||
|
||||
+111
@@ -0,0 +1,111 @@
|
||||
// (c) Copyright 1995-2021, 2023 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
////////////////////////////////////////////////////////////
|
||||
|
||||
#ifndef OCL_PLATFORM_H
|
||||
#define OCL_PLATFORM_H
|
||||
#include <math.h>
|
||||
#include <iostream>
|
||||
#include "report_handler.h"
|
||||
#include "axi_bram_fmodel_base.h"
|
||||
|
||||
#include <string.h> // memcpy
|
||||
#include <stdlib.h> //realloc
|
||||
#include <stdint.h>
|
||||
#include <vector>
|
||||
#include <map> //realloc
|
||||
//Uncomment to print the latency calculation log
|
||||
//#define DEBUGMSG
|
||||
|
||||
#define ONE_KB (0x400)
|
||||
#define ONE_MB (ONE_KB * ONE_KB)
|
||||
#define PAGESIZE (ONE_MB)
|
||||
#define ADDRBITS (20)
|
||||
#define N_1MBARRAYS 4096
|
||||
|
||||
//Calculations for Strb
|
||||
//Its Array of 64bit integer
|
||||
#define STRB_SIZE 64
|
||||
#define ONE_KB_STRB (ONE_KB / STRB_SIZE)
|
||||
#define ONE_MB_STRB (ONE_KB_STRB * ONE_KB)
|
||||
|
||||
//using namespace std;
|
||||
|
||||
#define RBC 0
|
||||
#define BRC 1
|
||||
#define RCB 2
|
||||
|
||||
enum fileType {MEM,MEM_STRB};
|
||||
//Models fixed portion of the platform
|
||||
class axi_bram_ram_fmodel:public axi_bram_fmodel_base{
|
||||
public:
|
||||
unsigned int writeDevMem(uint64_t offset, void* src, unsigned int size);
|
||||
unsigned int readDevMem(uint64_t offset, void* dest, unsigned int size);
|
||||
unsigned char* get_page(uint64_t offset, std::string& p2pFileName, uint64_t size = 0);
|
||||
bool createMMappedBuffer(uint64_t base_address,uint64_t size,std::string& buffer_filename);
|
||||
bool freePage(uint64_t base_address);
|
||||
bool copyBO(uint64_t offset, std::string dst_filename, uint64_t size, uint64_t src_offset, uint64_t dst_offset);
|
||||
bool importBO(uint64_t offset, std::string dst_filename,uint64_t size);
|
||||
void reset_fmodel(){};
|
||||
std::string get_mem_file_name(uint64_t pageIdx);
|
||||
|
||||
protected:
|
||||
private:
|
||||
//unsigned char* get_page(uint64_t offset);
|
||||
//Paging
|
||||
std::map<uint64_t,unsigned char*> pageCache;
|
||||
std::map<uint64_t,unsigned char*>::iterator pageCacheItr;
|
||||
std::string module_name;
|
||||
xsc::common_cpp::report_handler* m_report_handler;
|
||||
uint64_t m_mem_addr_width;
|
||||
public:
|
||||
axi_bram_ram_fmodel(std::string p_module_name,xsc::common_cpp::report_handler* report_handler,uint64_t addr_size);
|
||||
~ axi_bram_ram_fmodel();
|
||||
void init_fmodel();
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
+3
-3
@@ -198,12 +198,12 @@ ARCHITECTURE system_top_axi_bram_ctrl_0_0_arch OF system_top_axi_bram_ctrl_0_0 I
|
||||
);
|
||||
END COMPONENT axi_bram_ctrl;
|
||||
ATTRIBUTE X_CORE_INFO : STRING;
|
||||
ATTRIBUTE X_CORE_INFO OF system_top_axi_bram_ctrl_0_0_arch: ARCHITECTURE IS "axi_bram_ctrl,Vivado 2024.1";
|
||||
ATTRIBUTE X_CORE_INFO OF system_top_axi_bram_ctrl_0_0_arch: ARCHITECTURE IS "axi_bram_ctrl,Vivado 2024.1.2";
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE OF system_top_axi_bram_ctrl_0_0_arch : ARCHITECTURE IS "system_top_axi_bram_ctrl_0_0,axi_bram_ctrl,{}";
|
||||
ATTRIBUTE CORE_GENERATION_INFO : STRING;
|
||||
ATTRIBUTE CORE_GENERATION_INFO OF system_top_axi_bram_ctrl_0_0_arch: ARCHITECTURE IS "system_top_axi_bram_ctrl_0_0,axi_bram_ctrl,{x_ipProduct=Vivado 2024.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_bram_ctrl,x_ipVersion=4.1,x_ipCoreRevision=10,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_BRAM_INST_MODE=EXTERNAL,C_MEMORY_DEPTH=8192,C_BRAM_ADDR_WIDTH=13,C_S_AXI_ADDR_WIDTH=15,C_S_AXI_DATA_WIDTH=32,C_S_AXI_ID_WIDTH=1,C_S_AXI_PROTOCOL=AXI4,C_S_AXI_SUPPORTS_NARROW_BURST=0,C_SINGLE_PORT_BRAM=1,C_FAMILY=zynq,C_READ_LATENCY=1,C_RD_CMD_OPTIMIZATION=0,C_S_AXI_CTRL_ADDR_WIDTH=32,C_S_" &
|
||||
"AXI_CTRL_DATA_WIDTH=32,C_ECC=0,C_ECC_TYPE=0,C_FAULT_INJECT=0,C_ECC_ONOFF_RESET_VALUE=0}";
|
||||
ATTRIBUTE CORE_GENERATION_INFO OF system_top_axi_bram_ctrl_0_0_arch: ARCHITECTURE IS "system_top_axi_bram_ctrl_0_0,axi_bram_ctrl,{x_ipProduct=Vivado 2024.1.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_bram_ctrl,x_ipVersion=4.1,x_ipCoreRevision=10,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_BRAM_INST_MODE=EXTERNAL,C_MEMORY_DEPTH=8192,C_BRAM_ADDR_WIDTH=13,C_S_AXI_ADDR_WIDTH=15,C_S_AXI_DATA_WIDTH=32,C_S_AXI_ID_WIDTH=1,C_S_AXI_PROTOCOL=AXI4,C_S_AXI_SUPPORTS_NARROW_BURST=0,C_SINGLE_PORT_BRAM=1,C_FAMILY=zynq,C_READ_LATENCY=1,C_RD_CMD_OPTIMIZATION=0,C_S_AXI_CTRL_ADDR_WIDTH=32,C_" &
|
||||
"S_AXI_CTRL_DATA_WIDTH=32,C_ECC=0,C_ECC_TYPE=0,C_FAULT_INJECT=0,C_ECC_ONOFF_RESET_VALUE=0}";
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bram_addr_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
|
||||
|
||||
+2
-2
@@ -64,7 +64,7 @@
|
||||
"OUTPUTDIR": [ { "value": "." } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2024.1" } ],
|
||||
"SWVERSION": [ { "value": "2024.1.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
@@ -195,7 +195,7 @@
|
||||
"MEM_ECC": [ { "value": "NONE", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_LATENCY": [ { "value": "1", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MEM_ADDRESS_MODE": [ { "value": "", "value_src": "weak", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
"MEM_ADDRESS_MODE": [ { "value": "", "value_src": "weak", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"ADDR": [ { "physical_name": "bram_addr_a" } ],
|
||||
|
||||
+258
-3
@@ -1990,6 +1990,25 @@ The register is automatically cleared after the fault has been injected.
|
||||
</spirit:memoryMaps>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:modelName>axi_bram_ctrl</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Nov 03 07:49:49 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:f39012d8</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_synthesisconstraints</spirit:name>
|
||||
<spirit:displayName>Synthesis Constraints</spirit:displayName>
|
||||
@@ -2001,6 +2020,78 @@ The register is automatically cleared after the fault has been injected.
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_systemcsimulation</spirit:name>
|
||||
<spirit:displayName>SystemC Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>systemCSource:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:language>systemc</spirit:language>
|
||||
<spirit:modelName>axi_bram_ctrl</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_systemcsimulation_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Nov 03 07:49:49 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:abcd19f7</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>sim_type</spirit:name>
|
||||
<spirit:value>tlm</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>use_subcore_outputs</spirit:name>
|
||||
<spirit:value>false</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_systemcsimulationwrapper</spirit:name>
|
||||
<spirit:displayName>SystemC Simulation Wrapper</spirit:displayName>
|
||||
<spirit:envIdentifier>systemCSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
|
||||
<spirit:language>systemc</spirit:language>
|
||||
<spirit:modelName>system_top_axi_bram_ctrl_0_0</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_systemcsimulationwrapper_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Nov 03 07:49:49 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:abcd19f7</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>sim_type</spirit:name>
|
||||
<spirit:value>tlm</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
|
||||
<spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
|
||||
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
|
||||
<spirit:language>vhdl</spirit:language>
|
||||
<spirit:modelName>system_top_axi_bram_ctrl_0_0</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Nov 03 07:49:49 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:f39012d8</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_vhdlsynthesis</spirit:name>
|
||||
<spirit:displayName>VHDL Synthesis</spirit:displayName>
|
||||
@@ -2013,7 +2104,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Oct 31 03:29:29 UTC 2024</spirit:value>
|
||||
<spirit:value>Sun Nov 03 07:49:49 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -2033,7 +2124,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Oct 31 03:29:29 UTC 2024</spirit:value>
|
||||
<spirit:value>Sun Nov 03 07:49:49 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -2051,6 +2142,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2063,6 +2155,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2075,6 +2168,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2097,6 +2191,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2123,6 +2218,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2149,6 +2245,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2168,6 +2265,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2194,6 +2292,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2220,6 +2319,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2242,6 +2342,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2268,6 +2369,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2294,6 +2396,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2309,6 +2412,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2324,6 +2428,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2340,6 +2445,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2359,6 +2465,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2374,6 +2481,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2396,6 +2504,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2411,6 +2520,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2427,6 +2537,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2450,6 +2561,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2462,6 +2574,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2474,6 +2587,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2493,6 +2607,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2519,6 +2634,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2538,6 +2654,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2564,6 +2681,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2590,6 +2708,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2612,6 +2731,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2638,6 +2758,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2664,6 +2785,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2679,6 +2801,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2694,6 +2817,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2710,6 +2834,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2733,6 +2858,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2749,6 +2875,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2761,6 +2888,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2783,6 +2911,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2795,6 +2924,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2810,6 +2940,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2832,6 +2963,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2855,6 +2987,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2881,6 +3014,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2903,6 +3037,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2925,6 +3060,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2948,6 +3084,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2967,6 +3104,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2986,6 +3124,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -3012,6 +3151,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -3034,6 +3174,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -3056,6 +3197,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3079,6 +3221,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3102,6 +3245,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3121,6 +3265,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3140,6 +3285,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -3162,6 +3308,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3181,6 +3328,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3200,6 +3348,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3223,6 +3372,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3246,6 +3396,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3269,6 +3420,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3292,6 +3444,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -3314,6 +3467,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3333,6 +3487,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3352,6 +3507,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3375,6 +3531,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3398,6 +3555,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3421,6 +3579,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3444,6 +3603,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -3722,6 +3882,101 @@ The register is automatically cleared after the fault has been injected.
|
||||
</spirit:choice>
|
||||
</spirit:choices>
|
||||
<spirit:fileSets>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>../../ipshared/14fa/hdl/axi_bram_ctrl_v4_1_rfs.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
|
||||
<spirit:logicalName>axi_bram_ctrl_v4_1_10</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_systemcsimulation_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>src/axi_bram_ctrl.h</spirit:name>
|
||||
<spirit:fileType>systemCSource</spirit:fileType>
|
||||
<spirit:isIncludeFile>true</spirit:isIncludeFile>
|
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</spirit:file>
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<spirit:file>
|
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<spirit:name>src/axi_bram_ctrl.cpp</spirit:name>
|
||||
<spirit:fileType>systemCSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>src/axi_bram_ram_fmodel.cxx</spirit:name>
|
||||
<spirit:fileType>systemCSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>src/axi_bram_ram_fmodel.h</spirit:name>
|
||||
<spirit:fileType>systemCSource</spirit:fileType>
|
||||
<spirit:isIncludeFile>true</spirit:isIncludeFile>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>src/axi_bram_memory_imp.cpp</spirit:name>
|
||||
<spirit:fileType>systemCSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>src/axi_bram_memory_imp.h</spirit:name>
|
||||
<spirit:fileType>systemCSource</spirit:fileType>
|
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<spirit:isIncludeFile>true</spirit:isIncludeFile>
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</spirit:file>
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<spirit:file>
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<spirit:name>src/axi_bram_fmodel_shared_memory.h</spirit:name>
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<spirit:fileType>systemCSource</spirit:fileType>
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<spirit:isIncludeFile>true</spirit:isIncludeFile>
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</spirit:file>
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<spirit:file>
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<spirit:name>src/axi_bram_fmodel_shared_memory.cxx</spirit:name>
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<spirit:fileType>systemCSource</spirit:fileType>
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</spirit:file>
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<spirit:file>
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<spirit:name>src/axi_bram_fmodel_base.cxx</spirit:name>
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<spirit:fileType>systemCSource</spirit:fileType>
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</spirit:file>
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<spirit:file>
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<spirit:name>src/axi_bram_fmodel_base.h</spirit:name>
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<spirit:fileType>systemCSource</spirit:fileType>
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<spirit:isIncludeFile>true</spirit:isIncludeFile>
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</spirit:file>
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<spirit:file>
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<spirit:name>src/P2P_XTLM_extension.h</spirit:name>
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<spirit:fileType>systemCSource</spirit:fileType>
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<spirit:isIncludeFile>true</spirit:isIncludeFile>
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</spirit:file>
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</spirit:fileSet>
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<spirit:fileSet>
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<spirit:name>xilinx_systemcsimulationwrapper_view_fileset</spirit:name>
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<spirit:file>
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<spirit:name>sim/system_top_axi_bram_ctrl_0_0_sc.h</spirit:name>
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<spirit:fileType>systemCSource</spirit:fileType>
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<spirit:name>sim/system_top_axi_bram_ctrl_0_0_sc.cpp</spirit:name>
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<spirit:fileType>systemCSource</spirit:fileType>
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<spirit:name>sim/system_top_axi_bram_ctrl_0_0.h</spirit:name>
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<spirit:isIncludeFile>true</spirit:isIncludeFile>
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<spirit:file>
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<spirit:name>sim/system_top_axi_bram_ctrl_0_0.cpp</spirit:name>
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<spirit:fileType>systemCSource</spirit:fileType>
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</spirit:file>
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<spirit:file>
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<spirit:name>sim/system_top_axi_bram_ctrl_0_0_stub.sv</spirit:name>
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<spirit:fileType>systemVerilogSource</spirit:fileType>
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</spirit:file>
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</spirit:fileSet>
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<spirit:fileSet>
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<spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
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<spirit:file>
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<spirit:name>sim/system_top_axi_bram_ctrl_0_0.vhd</spirit:name>
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<spirit:fileType>vhdlSource</spirit:fileType>
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<spirit:logicalName>xil_defaultlib</spirit:logicalName>
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</spirit:fileSet>
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<spirit:fileSet>
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<spirit:name>xilinx_vhdlsynthesis_view_fileset</spirit:name>
|
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<spirit:file>
|
||||
@@ -3908,7 +4163,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<xilinx:coreRevision>10</xilinx:coreRevision>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MASTER_TYPE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_ADDRESS_MODE" xilinx:valueSource="weak"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_ADDRESS_MODE" xilinx:valueSource="weak" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_ECC" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_SIZE" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
||||
|
||||
+677
@@ -0,0 +1,677 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
#include "system_top_axi_bram_ctrl_1_0_sc.h"
|
||||
|
||||
#include "system_top_axi_bram_ctrl_1_0.h"
|
||||
|
||||
#include "axi_bram_ctrl.h"
|
||||
|
||||
#include <map>
|
||||
#include <string>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef XILINX_SIMULATOR
|
||||
system_top_axi_bram_ctrl_1_0::system_top_axi_bram_ctrl_1_0(const sc_core::sc_module_name& nm) : system_top_axi_bram_ctrl_1_0_sc(nm), s_axi_aclk("s_axi_aclk"), s_axi_aresetn("s_axi_aresetn"), s_axi_awaddr("s_axi_awaddr"), s_axi_awlen("s_axi_awlen"), s_axi_awsize("s_axi_awsize"), s_axi_awburst("s_axi_awburst"), s_axi_awlock("s_axi_awlock"), s_axi_awcache("s_axi_awcache"), s_axi_awprot("s_axi_awprot"), s_axi_awvalid("s_axi_awvalid"), s_axi_awready("s_axi_awready"), s_axi_wdata("s_axi_wdata"), s_axi_wstrb("s_axi_wstrb"), s_axi_wlast("s_axi_wlast"), s_axi_wvalid("s_axi_wvalid"), s_axi_wready("s_axi_wready"), s_axi_bresp("s_axi_bresp"), s_axi_bvalid("s_axi_bvalid"), s_axi_bready("s_axi_bready"), s_axi_araddr("s_axi_araddr"), s_axi_arlen("s_axi_arlen"), s_axi_arsize("s_axi_arsize"), s_axi_arburst("s_axi_arburst"), s_axi_arlock("s_axi_arlock"), s_axi_arcache("s_axi_arcache"), s_axi_arprot("s_axi_arprot"), s_axi_arvalid("s_axi_arvalid"), s_axi_arready("s_axi_arready"), s_axi_rdata("s_axi_rdata"), s_axi_rresp("s_axi_rresp"), s_axi_rlast("s_axi_rlast"), s_axi_rvalid("s_axi_rvalid"), s_axi_rready("s_axi_rready"), bram_rst_a("bram_rst_a"), bram_clk_a("bram_clk_a"), bram_en_a("bram_en_a"), bram_we_a("bram_we_a"), bram_addr_a("bram_addr_a"), bram_wrdata_a("bram_wrdata_a"), bram_rddata_a("bram_rddata_a")
|
||||
{
|
||||
|
||||
// initialize pins
|
||||
mp_impl->s_axi_aclk(s_axi_aclk);
|
||||
mp_impl->s_axi_aresetn(s_axi_aresetn);
|
||||
mp_impl->bram_rst_a(bram_rst_a);
|
||||
mp_impl->bram_clk_a(bram_clk_a);
|
||||
mp_impl->bram_en_a(bram_en_a);
|
||||
mp_impl->bram_we_a(bram_we_a);
|
||||
mp_impl->bram_addr_a(bram_addr_a);
|
||||
mp_impl->bram_wrdata_a(bram_wrdata_a);
|
||||
mp_impl->bram_rddata_a(bram_rddata_a);
|
||||
|
||||
// initialize transactors
|
||||
mp_S_AXI_transactor = NULL;
|
||||
|
||||
// initialize socket stubs
|
||||
|
||||
}
|
||||
|
||||
void system_top_axi_bram_ctrl_1_0::before_end_of_elaboration()
|
||||
{
|
||||
// configure 'S_AXI' transactor
|
||||
|
||||
if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("system_top_axi_bram_ctrl_1_0", "S_AXI_TLM_MODE") != 1)
|
||||
{
|
||||
// Instantiate Socket Stubs
|
||||
|
||||
// 'S_AXI' transactor parameters
|
||||
xsc::common_cpp::properties S_AXI_transactor_param_props;
|
||||
S_AXI_transactor_param_props.addLong("DATA_WIDTH", "32");
|
||||
S_AXI_transactor_param_props.addLong("FREQ_HZ", "1e+08");
|
||||
S_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("ADDR_WIDTH", "15");
|
||||
S_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_BURST", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_PROT", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_QOS", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_REGION", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
|
||||
S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
|
||||
S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
|
||||
S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
|
||||
S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "16");
|
||||
S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
|
||||
S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
|
||||
S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
|
||||
S_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_RESET", "1");
|
||||
S_AXI_transactor_param_props.addFloat("PHASE", "0.000");
|
||||
S_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
|
||||
S_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
|
||||
S_AXI_transactor_param_props.addString("CLK_DOMAIN", "system_top_processing_system7_0_0_FCLK_CLK0");
|
||||
|
||||
mp_S_AXI_transactor = new xtlm::xaximm_pin2xtlm_t<32,15,1,1,1,1,1,1>("S_AXI_transactor", S_AXI_transactor_param_props);
|
||||
|
||||
// S_AXI' transactor ports
|
||||
|
||||
mp_S_AXI_transactor->ARADDR(s_axi_araddr);
|
||||
mp_S_AXI_transactor->ARBURST(s_axi_arburst);
|
||||
mp_S_AXI_transactor->ARCACHE(s_axi_arcache);
|
||||
mp_S_AXI_transactor->ARLEN(s_axi_arlen);
|
||||
mp_S_AXI_transactor->ARLOCK(s_axi_arlock);
|
||||
mp_S_AXI_transactor->ARPROT(s_axi_arprot);
|
||||
mp_S_AXI_transactor->ARREADY(s_axi_arready);
|
||||
mp_S_AXI_transactor->ARSIZE(s_axi_arsize);
|
||||
mp_S_AXI_transactor->ARVALID(s_axi_arvalid);
|
||||
mp_S_AXI_transactor->AWADDR(s_axi_awaddr);
|
||||
mp_S_AXI_transactor->AWBURST(s_axi_awburst);
|
||||
mp_S_AXI_transactor->AWCACHE(s_axi_awcache);
|
||||
mp_S_AXI_transactor->AWLEN(s_axi_awlen);
|
||||
mp_S_AXI_transactor->AWLOCK(s_axi_awlock);
|
||||
mp_S_AXI_transactor->AWPROT(s_axi_awprot);
|
||||
mp_S_AXI_transactor->AWREADY(s_axi_awready);
|
||||
mp_S_AXI_transactor->AWSIZE(s_axi_awsize);
|
||||
mp_S_AXI_transactor->AWVALID(s_axi_awvalid);
|
||||
mp_S_AXI_transactor->BREADY(s_axi_bready);
|
||||
mp_S_AXI_transactor->BRESP(s_axi_bresp);
|
||||
mp_S_AXI_transactor->BVALID(s_axi_bvalid);
|
||||
mp_S_AXI_transactor->RDATA(s_axi_rdata);
|
||||
mp_S_AXI_transactor->RLAST(s_axi_rlast);
|
||||
mp_S_AXI_transactor->RREADY(s_axi_rready);
|
||||
mp_S_AXI_transactor->RRESP(s_axi_rresp);
|
||||
mp_S_AXI_transactor->RVALID(s_axi_rvalid);
|
||||
mp_S_AXI_transactor->WDATA(s_axi_wdata);
|
||||
mp_S_AXI_transactor->WLAST(s_axi_wlast);
|
||||
mp_S_AXI_transactor->WREADY(s_axi_wready);
|
||||
mp_S_AXI_transactor->WSTRB(s_axi_wstrb);
|
||||
mp_S_AXI_transactor->WVALID(s_axi_wvalid);
|
||||
mp_S_AXI_transactor->CLK(s_axi_aclk);
|
||||
mp_S_AXI_transactor->RST(s_axi_aresetn);
|
||||
|
||||
// S_AXI' transactor sockets
|
||||
|
||||
mp_impl->target_0_rd_socket->bind(*(mp_S_AXI_transactor->rd_socket));
|
||||
mp_impl->target_0_wr_socket->bind(*(mp_S_AXI_transactor->wr_socket));
|
||||
}
|
||||
else
|
||||
{
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
#endif // XILINX_SIMULATOR
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef XM_SYSTEMC
|
||||
system_top_axi_bram_ctrl_1_0::system_top_axi_bram_ctrl_1_0(const sc_core::sc_module_name& nm) : system_top_axi_bram_ctrl_1_0_sc(nm), s_axi_aclk("s_axi_aclk"), s_axi_aresetn("s_axi_aresetn"), s_axi_awaddr("s_axi_awaddr"), s_axi_awlen("s_axi_awlen"), s_axi_awsize("s_axi_awsize"), s_axi_awburst("s_axi_awburst"), s_axi_awlock("s_axi_awlock"), s_axi_awcache("s_axi_awcache"), s_axi_awprot("s_axi_awprot"), s_axi_awvalid("s_axi_awvalid"), s_axi_awready("s_axi_awready"), s_axi_wdata("s_axi_wdata"), s_axi_wstrb("s_axi_wstrb"), s_axi_wlast("s_axi_wlast"), s_axi_wvalid("s_axi_wvalid"), s_axi_wready("s_axi_wready"), s_axi_bresp("s_axi_bresp"), s_axi_bvalid("s_axi_bvalid"), s_axi_bready("s_axi_bready"), s_axi_araddr("s_axi_araddr"), s_axi_arlen("s_axi_arlen"), s_axi_arsize("s_axi_arsize"), s_axi_arburst("s_axi_arburst"), s_axi_arlock("s_axi_arlock"), s_axi_arcache("s_axi_arcache"), s_axi_arprot("s_axi_arprot"), s_axi_arvalid("s_axi_arvalid"), s_axi_arready("s_axi_arready"), s_axi_rdata("s_axi_rdata"), s_axi_rresp("s_axi_rresp"), s_axi_rlast("s_axi_rlast"), s_axi_rvalid("s_axi_rvalid"), s_axi_rready("s_axi_rready"), bram_rst_a("bram_rst_a"), bram_clk_a("bram_clk_a"), bram_en_a("bram_en_a"), bram_we_a("bram_we_a"), bram_addr_a("bram_addr_a"), bram_wrdata_a("bram_wrdata_a"), bram_rddata_a("bram_rddata_a")
|
||||
{
|
||||
|
||||
// initialize pins
|
||||
mp_impl->s_axi_aclk(s_axi_aclk);
|
||||
mp_impl->s_axi_aresetn(s_axi_aresetn);
|
||||
mp_impl->bram_rst_a(bram_rst_a);
|
||||
mp_impl->bram_clk_a(bram_clk_a);
|
||||
mp_impl->bram_en_a(bram_en_a);
|
||||
mp_impl->bram_we_a(bram_we_a);
|
||||
mp_impl->bram_addr_a(bram_addr_a);
|
||||
mp_impl->bram_wrdata_a(bram_wrdata_a);
|
||||
mp_impl->bram_rddata_a(bram_rddata_a);
|
||||
|
||||
// initialize transactors
|
||||
mp_S_AXI_transactor = NULL;
|
||||
|
||||
// initialize socket stubs
|
||||
|
||||
}
|
||||
|
||||
void system_top_axi_bram_ctrl_1_0::before_end_of_elaboration()
|
||||
{
|
||||
// configure 'S_AXI' transactor
|
||||
|
||||
if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("system_top_axi_bram_ctrl_1_0", "S_AXI_TLM_MODE") != 1)
|
||||
{
|
||||
// Instantiate Socket Stubs
|
||||
|
||||
// 'S_AXI' transactor parameters
|
||||
xsc::common_cpp::properties S_AXI_transactor_param_props;
|
||||
S_AXI_transactor_param_props.addLong("DATA_WIDTH", "32");
|
||||
S_AXI_transactor_param_props.addLong("FREQ_HZ", "1e+08");
|
||||
S_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("ADDR_WIDTH", "15");
|
||||
S_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_BURST", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_PROT", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_QOS", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_REGION", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
|
||||
S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
|
||||
S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
|
||||
S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
|
||||
S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "16");
|
||||
S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
|
||||
S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
|
||||
S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
|
||||
S_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_RESET", "1");
|
||||
S_AXI_transactor_param_props.addFloat("PHASE", "0.000");
|
||||
S_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
|
||||
S_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
|
||||
S_AXI_transactor_param_props.addString("CLK_DOMAIN", "system_top_processing_system7_0_0_FCLK_CLK0");
|
||||
|
||||
mp_S_AXI_transactor = new xtlm::xaximm_pin2xtlm_t<32,15,1,1,1,1,1,1>("S_AXI_transactor", S_AXI_transactor_param_props);
|
||||
|
||||
// S_AXI' transactor ports
|
||||
|
||||
mp_S_AXI_transactor->ARADDR(s_axi_araddr);
|
||||
mp_S_AXI_transactor->ARBURST(s_axi_arburst);
|
||||
mp_S_AXI_transactor->ARCACHE(s_axi_arcache);
|
||||
mp_S_AXI_transactor->ARLEN(s_axi_arlen);
|
||||
mp_S_AXI_transactor->ARLOCK(s_axi_arlock);
|
||||
mp_S_AXI_transactor->ARPROT(s_axi_arprot);
|
||||
mp_S_AXI_transactor->ARREADY(s_axi_arready);
|
||||
mp_S_AXI_transactor->ARSIZE(s_axi_arsize);
|
||||
mp_S_AXI_transactor->ARVALID(s_axi_arvalid);
|
||||
mp_S_AXI_transactor->AWADDR(s_axi_awaddr);
|
||||
mp_S_AXI_transactor->AWBURST(s_axi_awburst);
|
||||
mp_S_AXI_transactor->AWCACHE(s_axi_awcache);
|
||||
mp_S_AXI_transactor->AWLEN(s_axi_awlen);
|
||||
mp_S_AXI_transactor->AWLOCK(s_axi_awlock);
|
||||
mp_S_AXI_transactor->AWPROT(s_axi_awprot);
|
||||
mp_S_AXI_transactor->AWREADY(s_axi_awready);
|
||||
mp_S_AXI_transactor->AWSIZE(s_axi_awsize);
|
||||
mp_S_AXI_transactor->AWVALID(s_axi_awvalid);
|
||||
mp_S_AXI_transactor->BREADY(s_axi_bready);
|
||||
mp_S_AXI_transactor->BRESP(s_axi_bresp);
|
||||
mp_S_AXI_transactor->BVALID(s_axi_bvalid);
|
||||
mp_S_AXI_transactor->RDATA(s_axi_rdata);
|
||||
mp_S_AXI_transactor->RLAST(s_axi_rlast);
|
||||
mp_S_AXI_transactor->RREADY(s_axi_rready);
|
||||
mp_S_AXI_transactor->RRESP(s_axi_rresp);
|
||||
mp_S_AXI_transactor->RVALID(s_axi_rvalid);
|
||||
mp_S_AXI_transactor->WDATA(s_axi_wdata);
|
||||
mp_S_AXI_transactor->WLAST(s_axi_wlast);
|
||||
mp_S_AXI_transactor->WREADY(s_axi_wready);
|
||||
mp_S_AXI_transactor->WSTRB(s_axi_wstrb);
|
||||
mp_S_AXI_transactor->WVALID(s_axi_wvalid);
|
||||
mp_S_AXI_transactor->CLK(s_axi_aclk);
|
||||
mp_S_AXI_transactor->RST(s_axi_aresetn);
|
||||
|
||||
// S_AXI' transactor sockets
|
||||
|
||||
mp_impl->target_0_rd_socket->bind(*(mp_S_AXI_transactor->rd_socket));
|
||||
mp_impl->target_0_wr_socket->bind(*(mp_S_AXI_transactor->wr_socket));
|
||||
}
|
||||
else
|
||||
{
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
#endif // XM_SYSTEMC
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef RIVIERA
|
||||
system_top_axi_bram_ctrl_1_0::system_top_axi_bram_ctrl_1_0(const sc_core::sc_module_name& nm) : system_top_axi_bram_ctrl_1_0_sc(nm), s_axi_aclk("s_axi_aclk"), s_axi_aresetn("s_axi_aresetn"), s_axi_awaddr("s_axi_awaddr"), s_axi_awlen("s_axi_awlen"), s_axi_awsize("s_axi_awsize"), s_axi_awburst("s_axi_awburst"), s_axi_awlock("s_axi_awlock"), s_axi_awcache("s_axi_awcache"), s_axi_awprot("s_axi_awprot"), s_axi_awvalid("s_axi_awvalid"), s_axi_awready("s_axi_awready"), s_axi_wdata("s_axi_wdata"), s_axi_wstrb("s_axi_wstrb"), s_axi_wlast("s_axi_wlast"), s_axi_wvalid("s_axi_wvalid"), s_axi_wready("s_axi_wready"), s_axi_bresp("s_axi_bresp"), s_axi_bvalid("s_axi_bvalid"), s_axi_bready("s_axi_bready"), s_axi_araddr("s_axi_araddr"), s_axi_arlen("s_axi_arlen"), s_axi_arsize("s_axi_arsize"), s_axi_arburst("s_axi_arburst"), s_axi_arlock("s_axi_arlock"), s_axi_arcache("s_axi_arcache"), s_axi_arprot("s_axi_arprot"), s_axi_arvalid("s_axi_arvalid"), s_axi_arready("s_axi_arready"), s_axi_rdata("s_axi_rdata"), s_axi_rresp("s_axi_rresp"), s_axi_rlast("s_axi_rlast"), s_axi_rvalid("s_axi_rvalid"), s_axi_rready("s_axi_rready"), bram_rst_a("bram_rst_a"), bram_clk_a("bram_clk_a"), bram_en_a("bram_en_a"), bram_we_a("bram_we_a"), bram_addr_a("bram_addr_a"), bram_wrdata_a("bram_wrdata_a"), bram_rddata_a("bram_rddata_a")
|
||||
{
|
||||
|
||||
// initialize pins
|
||||
mp_impl->s_axi_aclk(s_axi_aclk);
|
||||
mp_impl->s_axi_aresetn(s_axi_aresetn);
|
||||
mp_impl->bram_rst_a(bram_rst_a);
|
||||
mp_impl->bram_clk_a(bram_clk_a);
|
||||
mp_impl->bram_en_a(bram_en_a);
|
||||
mp_impl->bram_we_a(bram_we_a);
|
||||
mp_impl->bram_addr_a(bram_addr_a);
|
||||
mp_impl->bram_wrdata_a(bram_wrdata_a);
|
||||
mp_impl->bram_rddata_a(bram_rddata_a);
|
||||
|
||||
// initialize transactors
|
||||
mp_S_AXI_transactor = NULL;
|
||||
|
||||
// initialize socket stubs
|
||||
|
||||
}
|
||||
|
||||
void system_top_axi_bram_ctrl_1_0::before_end_of_elaboration()
|
||||
{
|
||||
// configure 'S_AXI' transactor
|
||||
|
||||
if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("system_top_axi_bram_ctrl_1_0", "S_AXI_TLM_MODE") != 1)
|
||||
{
|
||||
// Instantiate Socket Stubs
|
||||
|
||||
// 'S_AXI' transactor parameters
|
||||
xsc::common_cpp::properties S_AXI_transactor_param_props;
|
||||
S_AXI_transactor_param_props.addLong("DATA_WIDTH", "32");
|
||||
S_AXI_transactor_param_props.addLong("FREQ_HZ", "1e+08");
|
||||
S_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("ADDR_WIDTH", "15");
|
||||
S_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_BURST", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_PROT", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_QOS", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_REGION", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
|
||||
S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
|
||||
S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
|
||||
S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
|
||||
S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "16");
|
||||
S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
|
||||
S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
|
||||
S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
|
||||
S_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_RESET", "1");
|
||||
S_AXI_transactor_param_props.addFloat("PHASE", "0.000");
|
||||
S_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
|
||||
S_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
|
||||
S_AXI_transactor_param_props.addString("CLK_DOMAIN", "system_top_processing_system7_0_0_FCLK_CLK0");
|
||||
|
||||
mp_S_AXI_transactor = new xtlm::xaximm_pin2xtlm_t<32,15,1,1,1,1,1,1>("S_AXI_transactor", S_AXI_transactor_param_props);
|
||||
|
||||
// S_AXI' transactor ports
|
||||
|
||||
mp_S_AXI_transactor->ARADDR(s_axi_araddr);
|
||||
mp_S_AXI_transactor->ARBURST(s_axi_arburst);
|
||||
mp_S_AXI_transactor->ARCACHE(s_axi_arcache);
|
||||
mp_S_AXI_transactor->ARLEN(s_axi_arlen);
|
||||
mp_S_AXI_transactor->ARLOCK(s_axi_arlock);
|
||||
mp_S_AXI_transactor->ARPROT(s_axi_arprot);
|
||||
mp_S_AXI_transactor->ARREADY(s_axi_arready);
|
||||
mp_S_AXI_transactor->ARSIZE(s_axi_arsize);
|
||||
mp_S_AXI_transactor->ARVALID(s_axi_arvalid);
|
||||
mp_S_AXI_transactor->AWADDR(s_axi_awaddr);
|
||||
mp_S_AXI_transactor->AWBURST(s_axi_awburst);
|
||||
mp_S_AXI_transactor->AWCACHE(s_axi_awcache);
|
||||
mp_S_AXI_transactor->AWLEN(s_axi_awlen);
|
||||
mp_S_AXI_transactor->AWLOCK(s_axi_awlock);
|
||||
mp_S_AXI_transactor->AWPROT(s_axi_awprot);
|
||||
mp_S_AXI_transactor->AWREADY(s_axi_awready);
|
||||
mp_S_AXI_transactor->AWSIZE(s_axi_awsize);
|
||||
mp_S_AXI_transactor->AWVALID(s_axi_awvalid);
|
||||
mp_S_AXI_transactor->BREADY(s_axi_bready);
|
||||
mp_S_AXI_transactor->BRESP(s_axi_bresp);
|
||||
mp_S_AXI_transactor->BVALID(s_axi_bvalid);
|
||||
mp_S_AXI_transactor->RDATA(s_axi_rdata);
|
||||
mp_S_AXI_transactor->RLAST(s_axi_rlast);
|
||||
mp_S_AXI_transactor->RREADY(s_axi_rready);
|
||||
mp_S_AXI_transactor->RRESP(s_axi_rresp);
|
||||
mp_S_AXI_transactor->RVALID(s_axi_rvalid);
|
||||
mp_S_AXI_transactor->WDATA(s_axi_wdata);
|
||||
mp_S_AXI_transactor->WLAST(s_axi_wlast);
|
||||
mp_S_AXI_transactor->WREADY(s_axi_wready);
|
||||
mp_S_AXI_transactor->WSTRB(s_axi_wstrb);
|
||||
mp_S_AXI_transactor->WVALID(s_axi_wvalid);
|
||||
mp_S_AXI_transactor->CLK(s_axi_aclk);
|
||||
mp_S_AXI_transactor->RST(s_axi_aresetn);
|
||||
|
||||
// S_AXI' transactor sockets
|
||||
|
||||
mp_impl->target_0_rd_socket->bind(*(mp_S_AXI_transactor->rd_socket));
|
||||
mp_impl->target_0_wr_socket->bind(*(mp_S_AXI_transactor->wr_socket));
|
||||
}
|
||||
else
|
||||
{
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
#endif // RIVIERA
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef VCSSYSTEMC
|
||||
system_top_axi_bram_ctrl_1_0::system_top_axi_bram_ctrl_1_0(const sc_core::sc_module_name& nm) : system_top_axi_bram_ctrl_1_0_sc(nm), s_axi_aclk("s_axi_aclk"), s_axi_aresetn("s_axi_aresetn"), s_axi_awaddr("s_axi_awaddr"), s_axi_awlen("s_axi_awlen"), s_axi_awsize("s_axi_awsize"), s_axi_awburst("s_axi_awburst"), s_axi_awlock("s_axi_awlock"), s_axi_awcache("s_axi_awcache"), s_axi_awprot("s_axi_awprot"), s_axi_awvalid("s_axi_awvalid"), s_axi_awready("s_axi_awready"), s_axi_wdata("s_axi_wdata"), s_axi_wstrb("s_axi_wstrb"), s_axi_wlast("s_axi_wlast"), s_axi_wvalid("s_axi_wvalid"), s_axi_wready("s_axi_wready"), s_axi_bresp("s_axi_bresp"), s_axi_bvalid("s_axi_bvalid"), s_axi_bready("s_axi_bready"), s_axi_araddr("s_axi_araddr"), s_axi_arlen("s_axi_arlen"), s_axi_arsize("s_axi_arsize"), s_axi_arburst("s_axi_arburst"), s_axi_arlock("s_axi_arlock"), s_axi_arcache("s_axi_arcache"), s_axi_arprot("s_axi_arprot"), s_axi_arvalid("s_axi_arvalid"), s_axi_arready("s_axi_arready"), s_axi_rdata("s_axi_rdata"), s_axi_rresp("s_axi_rresp"), s_axi_rlast("s_axi_rlast"), s_axi_rvalid("s_axi_rvalid"), s_axi_rready("s_axi_rready"), bram_rst_a("bram_rst_a"), bram_clk_a("bram_clk_a"), bram_en_a("bram_en_a"), bram_we_a("bram_we_a"), bram_addr_a("bram_addr_a"), bram_wrdata_a("bram_wrdata_a"), bram_rddata_a("bram_rddata_a")
|
||||
{
|
||||
// initialize pins
|
||||
mp_impl->s_axi_aclk(s_axi_aclk);
|
||||
mp_impl->s_axi_aresetn(s_axi_aresetn);
|
||||
mp_impl->bram_rst_a(bram_rst_a);
|
||||
mp_impl->bram_clk_a(bram_clk_a);
|
||||
mp_impl->bram_en_a(bram_en_a);
|
||||
mp_impl->bram_we_a(bram_we_a);
|
||||
mp_impl->bram_addr_a(bram_addr_a);
|
||||
mp_impl->bram_wrdata_a(bram_wrdata_a);
|
||||
mp_impl->bram_rddata_a(bram_rddata_a);
|
||||
|
||||
// initialize transactors
|
||||
mp_S_AXI_transactor = NULL;
|
||||
|
||||
// Instantiate Socket Stubs
|
||||
|
||||
// configure S_AXI_transactor
|
||||
xsc::common_cpp::properties S_AXI_transactor_param_props;
|
||||
S_AXI_transactor_param_props.addLong("DATA_WIDTH", "32");
|
||||
S_AXI_transactor_param_props.addLong("FREQ_HZ", "1e+08");
|
||||
S_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("ADDR_WIDTH", "15");
|
||||
S_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_BURST", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_PROT", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_QOS", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_REGION", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
|
||||
S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
|
||||
S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
|
||||
S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
|
||||
S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "16");
|
||||
S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
|
||||
S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
|
||||
S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
|
||||
S_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_RESET", "1");
|
||||
S_AXI_transactor_param_props.addFloat("PHASE", "0.000");
|
||||
S_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
|
||||
S_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
|
||||
S_AXI_transactor_param_props.addString("CLK_DOMAIN", "system_top_processing_system7_0_0_FCLK_CLK0");
|
||||
|
||||
mp_S_AXI_transactor = new xtlm::xaximm_pin2xtlm_t<32,15,1,1,1,1,1,1>("S_AXI_transactor", S_AXI_transactor_param_props);
|
||||
mp_S_AXI_transactor->ARADDR(s_axi_araddr);
|
||||
mp_S_AXI_transactor->ARBURST(s_axi_arburst);
|
||||
mp_S_AXI_transactor->ARCACHE(s_axi_arcache);
|
||||
mp_S_AXI_transactor->ARLEN(s_axi_arlen);
|
||||
mp_S_AXI_transactor->ARLOCK(s_axi_arlock);
|
||||
mp_S_AXI_transactor->ARPROT(s_axi_arprot);
|
||||
mp_S_AXI_transactor->ARREADY(s_axi_arready);
|
||||
mp_S_AXI_transactor->ARSIZE(s_axi_arsize);
|
||||
mp_S_AXI_transactor->ARVALID(s_axi_arvalid);
|
||||
mp_S_AXI_transactor->AWADDR(s_axi_awaddr);
|
||||
mp_S_AXI_transactor->AWBURST(s_axi_awburst);
|
||||
mp_S_AXI_transactor->AWCACHE(s_axi_awcache);
|
||||
mp_S_AXI_transactor->AWLEN(s_axi_awlen);
|
||||
mp_S_AXI_transactor->AWLOCK(s_axi_awlock);
|
||||
mp_S_AXI_transactor->AWPROT(s_axi_awprot);
|
||||
mp_S_AXI_transactor->AWREADY(s_axi_awready);
|
||||
mp_S_AXI_transactor->AWSIZE(s_axi_awsize);
|
||||
mp_S_AXI_transactor->AWVALID(s_axi_awvalid);
|
||||
mp_S_AXI_transactor->BREADY(s_axi_bready);
|
||||
mp_S_AXI_transactor->BRESP(s_axi_bresp);
|
||||
mp_S_AXI_transactor->BVALID(s_axi_bvalid);
|
||||
mp_S_AXI_transactor->RDATA(s_axi_rdata);
|
||||
mp_S_AXI_transactor->RLAST(s_axi_rlast);
|
||||
mp_S_AXI_transactor->RREADY(s_axi_rready);
|
||||
mp_S_AXI_transactor->RRESP(s_axi_rresp);
|
||||
mp_S_AXI_transactor->RVALID(s_axi_rvalid);
|
||||
mp_S_AXI_transactor->WDATA(s_axi_wdata);
|
||||
mp_S_AXI_transactor->WLAST(s_axi_wlast);
|
||||
mp_S_AXI_transactor->WREADY(s_axi_wready);
|
||||
mp_S_AXI_transactor->WSTRB(s_axi_wstrb);
|
||||
mp_S_AXI_transactor->WVALID(s_axi_wvalid);
|
||||
mp_S_AXI_transactor->CLK(s_axi_aclk);
|
||||
mp_S_AXI_transactor->RST(s_axi_aresetn);
|
||||
|
||||
// initialize transactors stubs
|
||||
S_AXI_transactor_target_wr_socket_stub = nullptr;
|
||||
S_AXI_transactor_target_rd_socket_stub = nullptr;
|
||||
|
||||
}
|
||||
|
||||
void system_top_axi_bram_ctrl_1_0::before_end_of_elaboration()
|
||||
{
|
||||
// configure 'S_AXI' transactor
|
||||
if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("system_top_axi_bram_ctrl_1_0", "S_AXI_TLM_MODE") != 1)
|
||||
{
|
||||
mp_impl->target_0_rd_socket->bind(*(mp_S_AXI_transactor->rd_socket));
|
||||
mp_impl->target_0_wr_socket->bind(*(mp_S_AXI_transactor->wr_socket));
|
||||
|
||||
}
|
||||
else
|
||||
{
|
||||
S_AXI_transactor_target_wr_socket_stub = new xtlm::xtlm_aximm_target_stub("wr_socket",0);
|
||||
S_AXI_transactor_target_wr_socket_stub->bind(*(mp_S_AXI_transactor->wr_socket));
|
||||
S_AXI_transactor_target_rd_socket_stub = new xtlm::xtlm_aximm_target_stub("rd_socket",0);
|
||||
S_AXI_transactor_target_rd_socket_stub->bind(*(mp_S_AXI_transactor->rd_socket));
|
||||
mp_S_AXI_transactor->disable_transactor();
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
#endif // VCSSYSTEMC
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef MTI_SYSTEMC
|
||||
system_top_axi_bram_ctrl_1_0::system_top_axi_bram_ctrl_1_0(const sc_core::sc_module_name& nm) : system_top_axi_bram_ctrl_1_0_sc(nm), s_axi_aclk("s_axi_aclk"), s_axi_aresetn("s_axi_aresetn"), s_axi_awaddr("s_axi_awaddr"), s_axi_awlen("s_axi_awlen"), s_axi_awsize("s_axi_awsize"), s_axi_awburst("s_axi_awburst"), s_axi_awlock("s_axi_awlock"), s_axi_awcache("s_axi_awcache"), s_axi_awprot("s_axi_awprot"), s_axi_awvalid("s_axi_awvalid"), s_axi_awready("s_axi_awready"), s_axi_wdata("s_axi_wdata"), s_axi_wstrb("s_axi_wstrb"), s_axi_wlast("s_axi_wlast"), s_axi_wvalid("s_axi_wvalid"), s_axi_wready("s_axi_wready"), s_axi_bresp("s_axi_bresp"), s_axi_bvalid("s_axi_bvalid"), s_axi_bready("s_axi_bready"), s_axi_araddr("s_axi_araddr"), s_axi_arlen("s_axi_arlen"), s_axi_arsize("s_axi_arsize"), s_axi_arburst("s_axi_arburst"), s_axi_arlock("s_axi_arlock"), s_axi_arcache("s_axi_arcache"), s_axi_arprot("s_axi_arprot"), s_axi_arvalid("s_axi_arvalid"), s_axi_arready("s_axi_arready"), s_axi_rdata("s_axi_rdata"), s_axi_rresp("s_axi_rresp"), s_axi_rlast("s_axi_rlast"), s_axi_rvalid("s_axi_rvalid"), s_axi_rready("s_axi_rready"), bram_rst_a("bram_rst_a"), bram_clk_a("bram_clk_a"), bram_en_a("bram_en_a"), bram_we_a("bram_we_a"), bram_addr_a("bram_addr_a"), bram_wrdata_a("bram_wrdata_a"), bram_rddata_a("bram_rddata_a")
|
||||
{
|
||||
// initialize pins
|
||||
mp_impl->s_axi_aclk(s_axi_aclk);
|
||||
mp_impl->s_axi_aresetn(s_axi_aresetn);
|
||||
mp_impl->bram_rst_a(bram_rst_a);
|
||||
mp_impl->bram_clk_a(bram_clk_a);
|
||||
mp_impl->bram_en_a(bram_en_a);
|
||||
mp_impl->bram_we_a(bram_we_a);
|
||||
mp_impl->bram_addr_a(bram_addr_a);
|
||||
mp_impl->bram_wrdata_a(bram_wrdata_a);
|
||||
mp_impl->bram_rddata_a(bram_rddata_a);
|
||||
|
||||
// initialize transactors
|
||||
mp_S_AXI_transactor = NULL;
|
||||
|
||||
// Instantiate Socket Stubs
|
||||
|
||||
// configure S_AXI_transactor
|
||||
xsc::common_cpp::properties S_AXI_transactor_param_props;
|
||||
S_AXI_transactor_param_props.addLong("DATA_WIDTH", "32");
|
||||
S_AXI_transactor_param_props.addLong("FREQ_HZ", "1e+08");
|
||||
S_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("ADDR_WIDTH", "15");
|
||||
S_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_BURST", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_PROT", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_QOS", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_REGION", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
|
||||
S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
|
||||
S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
|
||||
S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
|
||||
S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "16");
|
||||
S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
|
||||
S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
|
||||
S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
|
||||
S_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_RESET", "1");
|
||||
S_AXI_transactor_param_props.addFloat("PHASE", "0.000");
|
||||
S_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
|
||||
S_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
|
||||
S_AXI_transactor_param_props.addString("CLK_DOMAIN", "system_top_processing_system7_0_0_FCLK_CLK0");
|
||||
|
||||
mp_S_AXI_transactor = new xtlm::xaximm_pin2xtlm_t<32,15,1,1,1,1,1,1>("S_AXI_transactor", S_AXI_transactor_param_props);
|
||||
mp_S_AXI_transactor->ARADDR(s_axi_araddr);
|
||||
mp_S_AXI_transactor->ARBURST(s_axi_arburst);
|
||||
mp_S_AXI_transactor->ARCACHE(s_axi_arcache);
|
||||
mp_S_AXI_transactor->ARLEN(s_axi_arlen);
|
||||
mp_S_AXI_transactor->ARLOCK(s_axi_arlock);
|
||||
mp_S_AXI_transactor->ARPROT(s_axi_arprot);
|
||||
mp_S_AXI_transactor->ARREADY(s_axi_arready);
|
||||
mp_S_AXI_transactor->ARSIZE(s_axi_arsize);
|
||||
mp_S_AXI_transactor->ARVALID(s_axi_arvalid);
|
||||
mp_S_AXI_transactor->AWADDR(s_axi_awaddr);
|
||||
mp_S_AXI_transactor->AWBURST(s_axi_awburst);
|
||||
mp_S_AXI_transactor->AWCACHE(s_axi_awcache);
|
||||
mp_S_AXI_transactor->AWLEN(s_axi_awlen);
|
||||
mp_S_AXI_transactor->AWLOCK(s_axi_awlock);
|
||||
mp_S_AXI_transactor->AWPROT(s_axi_awprot);
|
||||
mp_S_AXI_transactor->AWREADY(s_axi_awready);
|
||||
mp_S_AXI_transactor->AWSIZE(s_axi_awsize);
|
||||
mp_S_AXI_transactor->AWVALID(s_axi_awvalid);
|
||||
mp_S_AXI_transactor->BREADY(s_axi_bready);
|
||||
mp_S_AXI_transactor->BRESP(s_axi_bresp);
|
||||
mp_S_AXI_transactor->BVALID(s_axi_bvalid);
|
||||
mp_S_AXI_transactor->RDATA(s_axi_rdata);
|
||||
mp_S_AXI_transactor->RLAST(s_axi_rlast);
|
||||
mp_S_AXI_transactor->RREADY(s_axi_rready);
|
||||
mp_S_AXI_transactor->RRESP(s_axi_rresp);
|
||||
mp_S_AXI_transactor->RVALID(s_axi_rvalid);
|
||||
mp_S_AXI_transactor->WDATA(s_axi_wdata);
|
||||
mp_S_AXI_transactor->WLAST(s_axi_wlast);
|
||||
mp_S_AXI_transactor->WREADY(s_axi_wready);
|
||||
mp_S_AXI_transactor->WSTRB(s_axi_wstrb);
|
||||
mp_S_AXI_transactor->WVALID(s_axi_wvalid);
|
||||
mp_S_AXI_transactor->CLK(s_axi_aclk);
|
||||
mp_S_AXI_transactor->RST(s_axi_aresetn);
|
||||
|
||||
// initialize transactors stubs
|
||||
S_AXI_transactor_target_wr_socket_stub = nullptr;
|
||||
S_AXI_transactor_target_rd_socket_stub = nullptr;
|
||||
|
||||
}
|
||||
|
||||
void system_top_axi_bram_ctrl_1_0::before_end_of_elaboration()
|
||||
{
|
||||
// configure 'S_AXI' transactor
|
||||
if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("system_top_axi_bram_ctrl_1_0", "S_AXI_TLM_MODE") != 1)
|
||||
{
|
||||
mp_impl->target_0_rd_socket->bind(*(mp_S_AXI_transactor->rd_socket));
|
||||
mp_impl->target_0_wr_socket->bind(*(mp_S_AXI_transactor->wr_socket));
|
||||
|
||||
}
|
||||
else
|
||||
{
|
||||
S_AXI_transactor_target_wr_socket_stub = new xtlm::xtlm_aximm_target_stub("wr_socket",0);
|
||||
S_AXI_transactor_target_wr_socket_stub->bind(*(mp_S_AXI_transactor->wr_socket));
|
||||
S_AXI_transactor_target_rd_socket_stub = new xtlm::xtlm_aximm_target_stub("rd_socket",0);
|
||||
S_AXI_transactor_target_rd_socket_stub->bind(*(mp_S_AXI_transactor->rd_socket));
|
||||
mp_S_AXI_transactor->disable_transactor();
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
#endif // MTI_SYSTEMC
|
||||
|
||||
|
||||
|
||||
|
||||
system_top_axi_bram_ctrl_1_0::~system_top_axi_bram_ctrl_1_0()
|
||||
{
|
||||
delete mp_S_AXI_transactor;
|
||||
|
||||
}
|
||||
|
||||
#ifdef MTI_SYSTEMC
|
||||
SC_MODULE_EXPORT(system_top_axi_bram_ctrl_1_0);
|
||||
#endif
|
||||
|
||||
#ifdef XM_SYSTEMC
|
||||
XMSC_MODULE_EXPORT(system_top_axi_bram_ctrl_1_0);
|
||||
#endif
|
||||
|
||||
#ifdef RIVIERA
|
||||
SC_MODULE_EXPORT(system_top_axi_bram_ctrl_1_0);
|
||||
#endif
|
||||
|
||||
+425
@@ -0,0 +1,425 @@
|
||||
#ifndef IP_SYSTEM_TOP_AXI_BRAM_CTRL_1_0_H_
|
||||
#define IP_SYSTEM_TOP_AXI_BRAM_CTRL_1_0_H_
|
||||
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
#ifndef XTLM
|
||||
#include "xtlm.h"
|
||||
#endif
|
||||
#ifndef SYSTEMC_INCLUDED
|
||||
#include <systemc>
|
||||
#endif
|
||||
|
||||
#if defined(_MSC_VER)
|
||||
#define DllExport __declspec(dllexport)
|
||||
#elif defined(__GNUC__)
|
||||
#define DllExport __attribute__ ((visibility("default")))
|
||||
#else
|
||||
#define DllExport
|
||||
#endif
|
||||
|
||||
#include "system_top_axi_bram_ctrl_1_0_sc.h"
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef XILINX_SIMULATOR
|
||||
class DllExport system_top_axi_bram_ctrl_1_0 : public system_top_axi_bram_ctrl_1_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
system_top_axi_bram_ctrl_1_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~system_top_axi_bram_ctrl_1_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< bool > s_axi_aclk;
|
||||
sc_core::sc_in< bool > s_axi_aresetn;
|
||||
sc_core::sc_in< sc_dt::sc_bv<15> > s_axi_awaddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||
sc_core::sc_in< bool > s_axi_awlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||
sc_core::sc_in< bool > s_axi_awvalid;
|
||||
sc_core::sc_out< bool > s_axi_awready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
|
||||
sc_core::sc_in< bool > s_axi_wlast;
|
||||
sc_core::sc_in< bool > s_axi_wvalid;
|
||||
sc_core::sc_out< bool > s_axi_wready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||
sc_core::sc_out< bool > s_axi_bvalid;
|
||||
sc_core::sc_in< bool > s_axi_bready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<15> > s_axi_araddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||
sc_core::sc_in< bool > s_axi_arlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||
sc_core::sc_in< bool > s_axi_arvalid;
|
||||
sc_core::sc_out< bool > s_axi_arready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||
sc_core::sc_out< bool > s_axi_rlast;
|
||||
sc_core::sc_out< bool > s_axi_rvalid;
|
||||
sc_core::sc_in< bool > s_axi_rready;
|
||||
sc_core::sc_out< bool > bram_rst_a;
|
||||
sc_core::sc_out< bool > bram_clk_a;
|
||||
sc_core::sc_out< bool > bram_en_a;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > bram_we_a;
|
||||
sc_core::sc_out< sc_dt::sc_bv<15> > bram_addr_a;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > bram_wrdata_a;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > bram_rddata_a;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_pin2xtlm_t<32,15,1,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||
|
||||
};
|
||||
#endif // XILINX_SIMULATOR
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef XM_SYSTEMC
|
||||
class DllExport system_top_axi_bram_ctrl_1_0 : public system_top_axi_bram_ctrl_1_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
system_top_axi_bram_ctrl_1_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~system_top_axi_bram_ctrl_1_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< bool > s_axi_aclk;
|
||||
sc_core::sc_in< bool > s_axi_aresetn;
|
||||
sc_core::sc_in< sc_dt::sc_bv<15> > s_axi_awaddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||
sc_core::sc_in< bool > s_axi_awlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||
sc_core::sc_in< bool > s_axi_awvalid;
|
||||
sc_core::sc_out< bool > s_axi_awready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
|
||||
sc_core::sc_in< bool > s_axi_wlast;
|
||||
sc_core::sc_in< bool > s_axi_wvalid;
|
||||
sc_core::sc_out< bool > s_axi_wready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||
sc_core::sc_out< bool > s_axi_bvalid;
|
||||
sc_core::sc_in< bool > s_axi_bready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<15> > s_axi_araddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||
sc_core::sc_in< bool > s_axi_arlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||
sc_core::sc_in< bool > s_axi_arvalid;
|
||||
sc_core::sc_out< bool > s_axi_arready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||
sc_core::sc_out< bool > s_axi_rlast;
|
||||
sc_core::sc_out< bool > s_axi_rvalid;
|
||||
sc_core::sc_in< bool > s_axi_rready;
|
||||
sc_core::sc_out< bool > bram_rst_a;
|
||||
sc_core::sc_out< bool > bram_clk_a;
|
||||
sc_core::sc_out< bool > bram_en_a;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > bram_we_a;
|
||||
sc_core::sc_out< sc_dt::sc_bv<15> > bram_addr_a;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > bram_wrdata_a;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > bram_rddata_a;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_pin2xtlm_t<32,15,1,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||
|
||||
};
|
||||
#endif // XM_SYSTEMC
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef RIVIERA
|
||||
class DllExport system_top_axi_bram_ctrl_1_0 : public system_top_axi_bram_ctrl_1_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
system_top_axi_bram_ctrl_1_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~system_top_axi_bram_ctrl_1_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< bool > s_axi_aclk;
|
||||
sc_core::sc_in< bool > s_axi_aresetn;
|
||||
sc_core::sc_in< sc_dt::sc_bv<15> > s_axi_awaddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||
sc_core::sc_in< bool > s_axi_awlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||
sc_core::sc_in< bool > s_axi_awvalid;
|
||||
sc_core::sc_out< bool > s_axi_awready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
|
||||
sc_core::sc_in< bool > s_axi_wlast;
|
||||
sc_core::sc_in< bool > s_axi_wvalid;
|
||||
sc_core::sc_out< bool > s_axi_wready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||
sc_core::sc_out< bool > s_axi_bvalid;
|
||||
sc_core::sc_in< bool > s_axi_bready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<15> > s_axi_araddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||
sc_core::sc_in< bool > s_axi_arlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||
sc_core::sc_in< bool > s_axi_arvalid;
|
||||
sc_core::sc_out< bool > s_axi_arready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||
sc_core::sc_out< bool > s_axi_rlast;
|
||||
sc_core::sc_out< bool > s_axi_rvalid;
|
||||
sc_core::sc_in< bool > s_axi_rready;
|
||||
sc_core::sc_out< bool > bram_rst_a;
|
||||
sc_core::sc_out< bool > bram_clk_a;
|
||||
sc_core::sc_out< bool > bram_en_a;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > bram_we_a;
|
||||
sc_core::sc_out< sc_dt::sc_bv<15> > bram_addr_a;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > bram_wrdata_a;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > bram_rddata_a;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_pin2xtlm_t<32,15,1,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||
|
||||
};
|
||||
#endif // RIVIERA
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef VCSSYSTEMC
|
||||
#include "utils/xtlm_aximm_target_stub.h"
|
||||
|
||||
class DllExport system_top_axi_bram_ctrl_1_0 : public system_top_axi_bram_ctrl_1_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
system_top_axi_bram_ctrl_1_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~system_top_axi_bram_ctrl_1_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< bool > s_axi_aclk;
|
||||
sc_core::sc_in< bool > s_axi_aresetn;
|
||||
sc_core::sc_in< sc_dt::sc_bv<15> > s_axi_awaddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||
sc_core::sc_in< bool > s_axi_awlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||
sc_core::sc_in< bool > s_axi_awvalid;
|
||||
sc_core::sc_out< bool > s_axi_awready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
|
||||
sc_core::sc_in< bool > s_axi_wlast;
|
||||
sc_core::sc_in< bool > s_axi_wvalid;
|
||||
sc_core::sc_out< bool > s_axi_wready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||
sc_core::sc_out< bool > s_axi_bvalid;
|
||||
sc_core::sc_in< bool > s_axi_bready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<15> > s_axi_araddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||
sc_core::sc_in< bool > s_axi_arlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||
sc_core::sc_in< bool > s_axi_arvalid;
|
||||
sc_core::sc_out< bool > s_axi_arready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||
sc_core::sc_out< bool > s_axi_rlast;
|
||||
sc_core::sc_out< bool > s_axi_rvalid;
|
||||
sc_core::sc_in< bool > s_axi_rready;
|
||||
sc_core::sc_out< bool > bram_rst_a;
|
||||
sc_core::sc_out< bool > bram_clk_a;
|
||||
sc_core::sc_out< bool > bram_en_a;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > bram_we_a;
|
||||
sc_core::sc_out< sc_dt::sc_bv<15> > bram_addr_a;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > bram_wrdata_a;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > bram_rddata_a;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_pin2xtlm_t<32,15,1,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||
|
||||
// Transactor stubs
|
||||
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_rd_socket_stub;
|
||||
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_wr_socket_stub;
|
||||
|
||||
// Socket stubs
|
||||
|
||||
};
|
||||
#endif // VCSSYSTEMC
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef MTI_SYSTEMC
|
||||
#include "utils/xtlm_aximm_target_stub.h"
|
||||
|
||||
class DllExport system_top_axi_bram_ctrl_1_0 : public system_top_axi_bram_ctrl_1_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
system_top_axi_bram_ctrl_1_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~system_top_axi_bram_ctrl_1_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< bool > s_axi_aclk;
|
||||
sc_core::sc_in< bool > s_axi_aresetn;
|
||||
sc_core::sc_in< sc_dt::sc_bv<15> > s_axi_awaddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||
sc_core::sc_in< bool > s_axi_awlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||
sc_core::sc_in< bool > s_axi_awvalid;
|
||||
sc_core::sc_out< bool > s_axi_awready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
|
||||
sc_core::sc_in< bool > s_axi_wlast;
|
||||
sc_core::sc_in< bool > s_axi_wvalid;
|
||||
sc_core::sc_out< bool > s_axi_wready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||
sc_core::sc_out< bool > s_axi_bvalid;
|
||||
sc_core::sc_in< bool > s_axi_bready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<15> > s_axi_araddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||
sc_core::sc_in< bool > s_axi_arlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||
sc_core::sc_in< bool > s_axi_arvalid;
|
||||
sc_core::sc_out< bool > s_axi_arready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||
sc_core::sc_out< bool > s_axi_rlast;
|
||||
sc_core::sc_out< bool > s_axi_rvalid;
|
||||
sc_core::sc_in< bool > s_axi_rready;
|
||||
sc_core::sc_out< bool > bram_rst_a;
|
||||
sc_core::sc_out< bool > bram_clk_a;
|
||||
sc_core::sc_out< bool > bram_en_a;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > bram_we_a;
|
||||
sc_core::sc_out< sc_dt::sc_bv<15> > bram_addr_a;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > bram_wrdata_a;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > bram_rddata_a;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_pin2xtlm_t<32,15,1,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||
|
||||
// Transactor stubs
|
||||
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_rd_socket_stub;
|
||||
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_wr_socket_stub;
|
||||
|
||||
// Socket stubs
|
||||
|
||||
};
|
||||
#endif // MTI_SYSTEMC
|
||||
#endif // IP_SYSTEM_TOP_AXI_BRAM_CTRL_1_0_H_
|
||||
+322
@@ -0,0 +1,322 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:axi_bram_ctrl:4.1
|
||||
-- IP Revision: 10
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY axi_bram_ctrl_v4_1_10;
|
||||
USE axi_bram_ctrl_v4_1_10.axi_bram_ctrl;
|
||||
|
||||
ENTITY system_top_axi_bram_ctrl_1_0 IS
|
||||
PORT (
|
||||
s_axi_aclk : IN STD_LOGIC;
|
||||
s_axi_aresetn : IN STD_LOGIC;
|
||||
s_axi_awaddr : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
|
||||
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_awlock : IN STD_LOGIC;
|
||||
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi_awvalid : IN STD_LOGIC;
|
||||
s_axi_awready : OUT STD_LOGIC;
|
||||
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_wlast : IN STD_LOGIC;
|
||||
s_axi_wvalid : IN STD_LOGIC;
|
||||
s_axi_wready : OUT STD_LOGIC;
|
||||
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_bvalid : OUT STD_LOGIC;
|
||||
s_axi_bready : IN STD_LOGIC;
|
||||
s_axi_araddr : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
|
||||
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_arlock : IN STD_LOGIC;
|
||||
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi_arvalid : IN STD_LOGIC;
|
||||
s_axi_arready : OUT STD_LOGIC;
|
||||
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_rlast : OUT STD_LOGIC;
|
||||
s_axi_rvalid : OUT STD_LOGIC;
|
||||
s_axi_rready : IN STD_LOGIC;
|
||||
bram_rst_a : OUT STD_LOGIC;
|
||||
bram_clk_a : OUT STD_LOGIC;
|
||||
bram_en_a : OUT STD_LOGIC;
|
||||
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
bram_addr_a : OUT STD_LOGIC_VECTOR(14 DOWNTO 0);
|
||||
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
END system_top_axi_bram_ctrl_1_0;
|
||||
|
||||
ARCHITECTURE system_top_axi_bram_ctrl_1_0_arch OF system_top_axi_bram_ctrl_1_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_top_axi_bram_ctrl_1_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axi_bram_ctrl IS
|
||||
GENERIC (
|
||||
C_BRAM_INST_MODE : STRING;
|
||||
C_MEMORY_DEPTH : INTEGER;
|
||||
C_BRAM_ADDR_WIDTH : INTEGER;
|
||||
C_S_AXI_ADDR_WIDTH : INTEGER;
|
||||
C_S_AXI_DATA_WIDTH : INTEGER;
|
||||
C_S_AXI_ID_WIDTH : INTEGER;
|
||||
C_S_AXI_PROTOCOL : STRING;
|
||||
C_S_AXI_SUPPORTS_NARROW_BURST : INTEGER;
|
||||
C_SINGLE_PORT_BRAM : INTEGER;
|
||||
C_FAMILY : STRING;
|
||||
C_READ_LATENCY : INTEGER;
|
||||
C_RD_CMD_OPTIMIZATION : INTEGER;
|
||||
C_S_AXI_CTRL_ADDR_WIDTH : INTEGER;
|
||||
C_S_AXI_CTRL_DATA_WIDTH : INTEGER;
|
||||
C_ECC : INTEGER;
|
||||
C_ECC_TYPE : INTEGER;
|
||||
C_FAULT_INJECT : INTEGER;
|
||||
C_ECC_ONOFF_RESET_VALUE : INTEGER
|
||||
);
|
||||
PORT (
|
||||
s_axi_aclk : IN STD_LOGIC;
|
||||
s_axi_aresetn : IN STD_LOGIC;
|
||||
ecc_interrupt : OUT STD_LOGIC;
|
||||
ecc_ue : OUT STD_LOGIC;
|
||||
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axi_awaddr : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
|
||||
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_awlock : IN STD_LOGIC;
|
||||
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi_awvalid : IN STD_LOGIC;
|
||||
s_axi_awready : OUT STD_LOGIC;
|
||||
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_wlast : IN STD_LOGIC;
|
||||
s_axi_wvalid : IN STD_LOGIC;
|
||||
s_axi_wready : OUT STD_LOGIC;
|
||||
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_bvalid : OUT STD_LOGIC;
|
||||
s_axi_bready : IN STD_LOGIC;
|
||||
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axi_araddr : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
|
||||
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_arlock : IN STD_LOGIC;
|
||||
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi_arvalid : IN STD_LOGIC;
|
||||
s_axi_arready : OUT STD_LOGIC;
|
||||
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_rlast : OUT STD_LOGIC;
|
||||
s_axi_rvalid : OUT STD_LOGIC;
|
||||
s_axi_rready : IN STD_LOGIC;
|
||||
s_axi_ctrl_awvalid : IN STD_LOGIC;
|
||||
s_axi_ctrl_awready : OUT STD_LOGIC;
|
||||
s_axi_ctrl_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_ctrl_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_ctrl_wvalid : IN STD_LOGIC;
|
||||
s_axi_ctrl_wready : OUT STD_LOGIC;
|
||||
s_axi_ctrl_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_ctrl_bvalid : OUT STD_LOGIC;
|
||||
s_axi_ctrl_bready : IN STD_LOGIC;
|
||||
s_axi_ctrl_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_ctrl_arvalid : IN STD_LOGIC;
|
||||
s_axi_ctrl_arready : OUT STD_LOGIC;
|
||||
s_axi_ctrl_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_ctrl_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_ctrl_rvalid : OUT STD_LOGIC;
|
||||
s_axi_ctrl_rready : IN STD_LOGIC;
|
||||
bram_rst_a : OUT STD_LOGIC;
|
||||
bram_clk_a : OUT STD_LOGIC;
|
||||
bram_en_a : OUT STD_LOGIC;
|
||||
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
bram_addr_a : OUT STD_LOGIC_VECTOR(14 DOWNTO 0);
|
||||
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
bram_rst_b : OUT STD_LOGIC;
|
||||
bram_clk_b : OUT STD_LOGIC;
|
||||
bram_en_b : OUT STD_LOGIC;
|
||||
bram_we_b : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
bram_addr_b : OUT STD_LOGIC_VECTOR(14 DOWNTO 0);
|
||||
bram_wrdata_b : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
bram_rddata_b : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT axi_bram_ctrl;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bram_addr_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bram_clk_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bram_en_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bram_rddata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF bram_rst_a: SIGNAL IS "XIL_INTERFACENAME BRAM_PORTA, MASTER_TYPE BRAM_CTRL, MEM_SIZE 32768, MEM_WIDTH 32, MEM_ECC NONE, READ_WRITE_MODE READ_WRITE, READ_LATENCY 1";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bram_rst_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA RST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bram_we_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bram_wrdata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aclk: SIGNAL IS "XIL_INTERFACENAME CLKIF, ASSOCIATED_BUSIF S_AXI:S_AXI_CTRL, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 1e+08, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN system_top_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLKIF CLK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARBURST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 RSTIF RST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLEN";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARPROT";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 15, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN system_top_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, " &
|
||||
"NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWBURST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLEN";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWPROT";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
|
||||
BEGIN
|
||||
U0 : axi_bram_ctrl
|
||||
GENERIC MAP (
|
||||
C_BRAM_INST_MODE => "EXTERNAL",
|
||||
C_MEMORY_DEPTH => 8192,
|
||||
C_BRAM_ADDR_WIDTH => 13,
|
||||
C_S_AXI_ADDR_WIDTH => 15,
|
||||
C_S_AXI_DATA_WIDTH => 32,
|
||||
C_S_AXI_ID_WIDTH => 1,
|
||||
C_S_AXI_PROTOCOL => "AXI4",
|
||||
C_S_AXI_SUPPORTS_NARROW_BURST => 0,
|
||||
C_SINGLE_PORT_BRAM => 1,
|
||||
C_FAMILY => "zynq",
|
||||
C_READ_LATENCY => 1,
|
||||
C_RD_CMD_OPTIMIZATION => 0,
|
||||
C_S_AXI_CTRL_ADDR_WIDTH => 32,
|
||||
C_S_AXI_CTRL_DATA_WIDTH => 32,
|
||||
C_ECC => 0,
|
||||
C_ECC_TYPE => 0,
|
||||
C_FAULT_INJECT => 0,
|
||||
C_ECC_ONOFF_RESET_VALUE => 0
|
||||
)
|
||||
PORT MAP (
|
||||
s_axi_aclk => s_axi_aclk,
|
||||
s_axi_aresetn => s_axi_aresetn,
|
||||
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
s_axi_awaddr => s_axi_awaddr,
|
||||
s_axi_awlen => s_axi_awlen,
|
||||
s_axi_awsize => s_axi_awsize,
|
||||
s_axi_awburst => s_axi_awburst,
|
||||
s_axi_awlock => s_axi_awlock,
|
||||
s_axi_awcache => s_axi_awcache,
|
||||
s_axi_awprot => s_axi_awprot,
|
||||
s_axi_awvalid => s_axi_awvalid,
|
||||
s_axi_awready => s_axi_awready,
|
||||
s_axi_wdata => s_axi_wdata,
|
||||
s_axi_wstrb => s_axi_wstrb,
|
||||
s_axi_wlast => s_axi_wlast,
|
||||
s_axi_wvalid => s_axi_wvalid,
|
||||
s_axi_wready => s_axi_wready,
|
||||
s_axi_bresp => s_axi_bresp,
|
||||
s_axi_bvalid => s_axi_bvalid,
|
||||
s_axi_bready => s_axi_bready,
|
||||
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
s_axi_araddr => s_axi_araddr,
|
||||
s_axi_arlen => s_axi_arlen,
|
||||
s_axi_arsize => s_axi_arsize,
|
||||
s_axi_arburst => s_axi_arburst,
|
||||
s_axi_arlock => s_axi_arlock,
|
||||
s_axi_arcache => s_axi_arcache,
|
||||
s_axi_arprot => s_axi_arprot,
|
||||
s_axi_arvalid => s_axi_arvalid,
|
||||
s_axi_arready => s_axi_arready,
|
||||
s_axi_rdata => s_axi_rdata,
|
||||
s_axi_rresp => s_axi_rresp,
|
||||
s_axi_rlast => s_axi_rlast,
|
||||
s_axi_rvalid => s_axi_rvalid,
|
||||
s_axi_rready => s_axi_rready,
|
||||
s_axi_ctrl_awvalid => '0',
|
||||
s_axi_ctrl_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
s_axi_ctrl_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
s_axi_ctrl_wvalid => '0',
|
||||
s_axi_ctrl_bready => '0',
|
||||
s_axi_ctrl_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
s_axi_ctrl_arvalid => '0',
|
||||
s_axi_ctrl_rready => '0',
|
||||
bram_rst_a => bram_rst_a,
|
||||
bram_clk_a => bram_clk_a,
|
||||
bram_en_a => bram_en_a,
|
||||
bram_we_a => bram_we_a,
|
||||
bram_addr_a => bram_addr_a,
|
||||
bram_wrdata_a => bram_wrdata_a,
|
||||
bram_rddata_a => bram_rddata_a,
|
||||
bram_rddata_b => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
|
||||
);
|
||||
END system_top_axi_bram_ctrl_1_0_arch;
|
||||
+97
@@ -0,0 +1,97 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
#include "system_top_axi_bram_ctrl_1_0_sc.h"
|
||||
|
||||
#include "axi_bram_ctrl.h"
|
||||
|
||||
#include <map>
|
||||
#include <string>
|
||||
|
||||
system_top_axi_bram_ctrl_1_0_sc::system_top_axi_bram_ctrl_1_0_sc(const sc_core::sc_module_name& nm) : sc_core::sc_module(nm), mp_impl(NULL)
|
||||
{
|
||||
// configure connectivity manager
|
||||
xsc::utils::xsc_sim_manager::addInstance("system_top_axi_bram_ctrl_1_0", this);
|
||||
|
||||
// initialize module
|
||||
xsc::common_cpp::properties model_param_props;
|
||||
model_param_props.addLong("C_MEMORY_DEPTH", "8192");
|
||||
model_param_props.addLong("C_BRAM_ADDR_WIDTH", "13");
|
||||
model_param_props.addLong("C_S_AXI_ADDR_WIDTH", "15");
|
||||
model_param_props.addLong("C_S_AXI_DATA_WIDTH", "32");
|
||||
model_param_props.addLong("C_S_AXI_ID_WIDTH", "1");
|
||||
model_param_props.addLong("C_S_AXI_SUPPORTS_NARROW_BURST", "0");
|
||||
model_param_props.addLong("C_SINGLE_PORT_BRAM", "1");
|
||||
model_param_props.addLong("C_READ_LATENCY", "1");
|
||||
model_param_props.addLong("C_RD_CMD_OPTIMIZATION", "0");
|
||||
model_param_props.addLong("C_S_AXI_CTRL_ADDR_WIDTH", "32");
|
||||
model_param_props.addLong("C_S_AXI_CTRL_DATA_WIDTH", "32");
|
||||
model_param_props.addLong("C_ECC", "0");
|
||||
model_param_props.addLong("C_ECC_TYPE", "0");
|
||||
model_param_props.addLong("C_FAULT_INJECT", "0");
|
||||
model_param_props.addLong("C_ECC_ONOFF_RESET_VALUE", "0");
|
||||
model_param_props.addString("C_BRAM_INST_MODE", "EXTERNAL");
|
||||
model_param_props.addString("C_S_AXI_PROTOCOL", "AXI4");
|
||||
model_param_props.addString("C_FAMILY", "zynq");
|
||||
model_param_props.addString("COMPONENT_NAME", "system_top_axi_bram_ctrl_1_0");
|
||||
|
||||
mp_impl = new axi_bram_ctrl("inst", model_param_props);
|
||||
|
||||
// initialize AXI sockets
|
||||
target_0_rd_socket = mp_impl->target_0_rd_socket;
|
||||
target_0_wr_socket = mp_impl->target_0_wr_socket;
|
||||
}
|
||||
|
||||
system_top_axi_bram_ctrl_1_0_sc::~system_top_axi_bram_ctrl_1_0_sc()
|
||||
{
|
||||
xsc::utils::xsc_sim_manager::clean();
|
||||
|
||||
delete mp_impl;
|
||||
}
|
||||
|
||||
+96
@@ -0,0 +1,96 @@
|
||||
#ifndef IP_SYSTEM_TOP_AXI_BRAM_CTRL_1_0_SC_H_
|
||||
#define IP_SYSTEM_TOP_AXI_BRAM_CTRL_1_0_SC_H_
|
||||
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
#ifndef XTLM
|
||||
#include "xtlm.h"
|
||||
#endif
|
||||
#ifndef SYSTEMC_INCLUDED
|
||||
#include <systemc>
|
||||
#endif
|
||||
|
||||
#if defined(_MSC_VER)
|
||||
#define DllExport __declspec(dllexport)
|
||||
#elif defined(__GNUC__)
|
||||
#define DllExport __attribute__ ((visibility("default")))
|
||||
#else
|
||||
#define DllExport
|
||||
#endif
|
||||
|
||||
class axi_bram_ctrl;
|
||||
|
||||
class DllExport system_top_axi_bram_ctrl_1_0_sc : public sc_core::sc_module
|
||||
{
|
||||
public:
|
||||
|
||||
system_top_axi_bram_ctrl_1_0_sc(const sc_core::sc_module_name& nm);
|
||||
virtual ~system_top_axi_bram_ctrl_1_0_sc();
|
||||
|
||||
// module socket-to-socket AXI TLM interfaces
|
||||
|
||||
xtlm::xtlm_aximm_target_socket* target_0_rd_socket;
|
||||
xtlm::xtlm_aximm_target_socket* target_0_wr_socket;
|
||||
|
||||
// module socket-to-socket TLM interfaces
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
axi_bram_ctrl* mp_impl;
|
||||
|
||||
private:
|
||||
|
||||
system_top_axi_bram_ctrl_1_0_sc(const system_top_axi_bram_ctrl_1_0_sc&);
|
||||
const system_top_axi_bram_ctrl_1_0_sc& operator=(const system_top_axi_bram_ctrl_1_0_sc&);
|
||||
|
||||
};
|
||||
|
||||
#endif // IP_SYSTEM_TOP_AXI_BRAM_CTRL_1_0_SC_H_
|
||||
+159
@@ -0,0 +1,159 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
//------------------------------------------------------------------------------------
|
||||
// Filename: system_top_axi_bram_ctrl_1_0_stub.sv
|
||||
// Description: This HDL file is intended to be used with following simulators only:
|
||||
//
|
||||
// Vivado Simulator (XSim)
|
||||
// Cadence Xcelium Simulator
|
||||
//
|
||||
//------------------------------------------------------------------------------------
|
||||
`timescale 1ps/1ps
|
||||
|
||||
`ifdef XILINX_SIMULATOR
|
||||
|
||||
`ifndef XILINX_SIMULATOR_BITASBOOL
|
||||
`define XILINX_SIMULATOR_BITASBOOL
|
||||
typedef bit bit_as_bool;
|
||||
`endif
|
||||
|
||||
(* SC_MODULE_EXPORT *)
|
||||
module system_top_axi_bram_ctrl_1_0 (
|
||||
input bit_as_bool s_axi_aclk,
|
||||
input bit_as_bool s_axi_aresetn,
|
||||
input bit [14 : 0] s_axi_awaddr,
|
||||
input bit [7 : 0] s_axi_awlen,
|
||||
input bit [2 : 0] s_axi_awsize,
|
||||
input bit [1 : 0] s_axi_awburst,
|
||||
input bit_as_bool s_axi_awlock,
|
||||
input bit [3 : 0] s_axi_awcache,
|
||||
input bit [2 : 0] s_axi_awprot,
|
||||
input bit_as_bool s_axi_awvalid,
|
||||
output bit_as_bool s_axi_awready,
|
||||
input bit [31 : 0] s_axi_wdata,
|
||||
input bit [3 : 0] s_axi_wstrb,
|
||||
input bit_as_bool s_axi_wlast,
|
||||
input bit_as_bool s_axi_wvalid,
|
||||
output bit_as_bool s_axi_wready,
|
||||
output bit [1 : 0] s_axi_bresp,
|
||||
output bit_as_bool s_axi_bvalid,
|
||||
input bit_as_bool s_axi_bready,
|
||||
input bit [14 : 0] s_axi_araddr,
|
||||
input bit [7 : 0] s_axi_arlen,
|
||||
input bit [2 : 0] s_axi_arsize,
|
||||
input bit [1 : 0] s_axi_arburst,
|
||||
input bit_as_bool s_axi_arlock,
|
||||
input bit [3 : 0] s_axi_arcache,
|
||||
input bit [2 : 0] s_axi_arprot,
|
||||
input bit_as_bool s_axi_arvalid,
|
||||
output bit_as_bool s_axi_arready,
|
||||
output bit [31 : 0] s_axi_rdata,
|
||||
output bit [1 : 0] s_axi_rresp,
|
||||
output bit_as_bool s_axi_rlast,
|
||||
output bit_as_bool s_axi_rvalid,
|
||||
input bit_as_bool s_axi_rready,
|
||||
output bit_as_bool bram_rst_a,
|
||||
output bit_as_bool bram_clk_a,
|
||||
output bit_as_bool bram_en_a,
|
||||
output bit [3 : 0] bram_we_a,
|
||||
output bit [14 : 0] bram_addr_a,
|
||||
output bit [31 : 0] bram_wrdata_a,
|
||||
input bit [31 : 0] bram_rddata_a
|
||||
);
|
||||
endmodule
|
||||
`endif
|
||||
|
||||
`ifdef XCELIUM
|
||||
(* XMSC_MODULE_EXPORT *)
|
||||
module system_top_axi_bram_ctrl_1_0 (s_axi_aclk,s_axi_aresetn,s_axi_awaddr,s_axi_awlen,s_axi_awsize,s_axi_awburst,s_axi_awlock,s_axi_awcache,s_axi_awprot,s_axi_awvalid,s_axi_awready,s_axi_wdata,s_axi_wstrb,s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bresp,s_axi_bvalid,s_axi_bready,s_axi_araddr,s_axi_arlen,s_axi_arsize,s_axi_arburst,s_axi_arlock,s_axi_arcache,s_axi_arprot,s_axi_arvalid,s_axi_arready,s_axi_rdata,s_axi_rresp,s_axi_rlast,s_axi_rvalid,s_axi_rready,bram_rst_a,bram_clk_a,bram_en_a,bram_we_a,bram_addr_a,bram_wrdata_a,bram_rddata_a)
|
||||
(* integer foreign = "SystemC";
|
||||
*);
|
||||
input bit s_axi_aclk;
|
||||
input bit s_axi_aresetn;
|
||||
input bit [14 : 0] s_axi_awaddr;
|
||||
input bit [7 : 0] s_axi_awlen;
|
||||
input bit [2 : 0] s_axi_awsize;
|
||||
input bit [1 : 0] s_axi_awburst;
|
||||
input bit s_axi_awlock;
|
||||
input bit [3 : 0] s_axi_awcache;
|
||||
input bit [2 : 0] s_axi_awprot;
|
||||
input bit s_axi_awvalid;
|
||||
output wire s_axi_awready;
|
||||
input bit [31 : 0] s_axi_wdata;
|
||||
input bit [3 : 0] s_axi_wstrb;
|
||||
input bit s_axi_wlast;
|
||||
input bit s_axi_wvalid;
|
||||
output wire s_axi_wready;
|
||||
output wire [1 : 0] s_axi_bresp;
|
||||
output wire s_axi_bvalid;
|
||||
input bit s_axi_bready;
|
||||
input bit [14 : 0] s_axi_araddr;
|
||||
input bit [7 : 0] s_axi_arlen;
|
||||
input bit [2 : 0] s_axi_arsize;
|
||||
input bit [1 : 0] s_axi_arburst;
|
||||
input bit s_axi_arlock;
|
||||
input bit [3 : 0] s_axi_arcache;
|
||||
input bit [2 : 0] s_axi_arprot;
|
||||
input bit s_axi_arvalid;
|
||||
output wire s_axi_arready;
|
||||
output wire [31 : 0] s_axi_rdata;
|
||||
output wire [1 : 0] s_axi_rresp;
|
||||
output wire s_axi_rlast;
|
||||
output wire s_axi_rvalid;
|
||||
input bit s_axi_rready;
|
||||
output wire bram_rst_a;
|
||||
output wire bram_clk_a;
|
||||
output wire bram_en_a;
|
||||
output wire [3 : 0] bram_we_a;
|
||||
output wire [14 : 0] bram_addr_a;
|
||||
output wire [31 : 0] bram_wrdata_a;
|
||||
input bit [31 : 0] bram_rddata_a;
|
||||
endmodule
|
||||
`endif
|
||||
+134
@@ -0,0 +1,134 @@
|
||||
// (c) Copyright 1995-2021, 2023 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
////////////////////////////////////////////////////////////
|
||||
|
||||
#ifndef __P2P_XTLM_EXTENSION_HH_
|
||||
#define __P2P_XTLM_EXTENSION_HH_
|
||||
#include "xtlm.h"
|
||||
|
||||
/**
|
||||
* XTLM extension to support peer to peer buffer allocation
|
||||
* Master requests buffer allocation with a base address and size and slave responds with corresponding
|
||||
* mmaped buffer file name
|
||||
*/
|
||||
namespace xsc {
|
||||
namespace extension {
|
||||
enum TYPE {
|
||||
ALLOC_BO,
|
||||
FREE_BO,
|
||||
IMPORT_BO,
|
||||
COPY_BO
|
||||
};
|
||||
|
||||
class P2P_XTLM_extension: public xtlm::xtlm_extension<P2P_XTLM_extension> {
|
||||
|
||||
public:
|
||||
P2P_XTLM_extension() {
|
||||
m_address=0;
|
||||
m_size=0;
|
||||
m_file_name = "";
|
||||
m_resp_valid=false;
|
||||
m_resp=false;
|
||||
m_type=TYPE::ALLOC_BO;
|
||||
m_src_offset = 0;
|
||||
m_dst_offset = 0;
|
||||
}
|
||||
|
||||
~P2P_XTLM_extension(){}
|
||||
xtlm::xtlm_extension_base* clone() const {
|
||||
// Must override pure virtual clone method
|
||||
P2P_XTLM_extension* t = new P2P_XTLM_extension();
|
||||
return t;
|
||||
}
|
||||
// Must override pure virtual copy_from method
|
||||
void copy_from(xtlm::xtlm_extension_base const &ext) {
|
||||
m_address = static_cast<P2P_XTLM_extension const &>(ext).m_address;
|
||||
m_size = static_cast<P2P_XTLM_extension const &>(ext).m_size;
|
||||
m_file_name = static_cast<P2P_XTLM_extension const &>(ext).m_file_name;
|
||||
m_resp_valid = static_cast<P2P_XTLM_extension const &>(ext).m_resp_valid;
|
||||
m_resp = static_cast<P2P_XTLM_extension const &>(ext).m_resp;
|
||||
m_type = static_cast<P2P_XTLM_extension const &>(ext).m_type;
|
||||
m_src_offset = static_cast<P2P_XTLM_extension const &>(ext).m_src_offset;
|
||||
m_dst_offset = static_cast<P2P_XTLM_extension const &>(ext).m_dst_offset;
|
||||
}
|
||||
|
||||
void setAddress(uint64_t address) { m_address = address; }
|
||||
uint64_t getAddress()const { return m_address; }
|
||||
|
||||
void setSize(uint64_t size) { m_size = size; }
|
||||
uint64_t getSize()const { return m_size; }
|
||||
|
||||
void setFileName(std::string file_name) { m_file_name = file_name; }
|
||||
const std::string& getFileName()const { return m_file_name; }
|
||||
|
||||
void setIsResponseValid(bool resp_valid) { m_resp_valid = resp_valid;}
|
||||
bool getIsResponseValid() { return m_resp_valid; }
|
||||
|
||||
void setResponse(bool resp){ m_resp = resp;}
|
||||
bool getResponse() const { return m_resp;}
|
||||
|
||||
void setSrcOffset(uint64_t src_offset) { m_src_offset = src_offset; }
|
||||
uint64_t getSrcOffset() const { return m_src_offset; }
|
||||
|
||||
void setDstOffset(uint64_t dst_offset) { m_dst_offset = dst_offset; }
|
||||
uint64_t getDstOffset() const { return m_dst_offset; }
|
||||
|
||||
void setType(TYPE type) { m_type = type; }
|
||||
TYPE getType() const { return m_type;}
|
||||
|
||||
private :
|
||||
uint64_t m_address;
|
||||
uint64_t m_size;
|
||||
std::string m_file_name;
|
||||
bool m_resp_valid;
|
||||
bool m_resp;
|
||||
uint64_t m_src_offset;
|
||||
uint64_t m_dst_offset;
|
||||
TYPE m_type;
|
||||
};
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
+96
@@ -0,0 +1,96 @@
|
||||
// (c) Copyright 1995-2021, 2023 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
////////////////////////////////////////////////////////////
|
||||
|
||||
#include "axi_bram_ctrl.h"
|
||||
|
||||
axi_bram_ctrl::axi_bram_ctrl(const sc_module_name& module_name, xsc::common_cpp::properties& properties) :
|
||||
sc_module(module_name) {
|
||||
//Get Width from property
|
||||
uint64_t data_width=properties.getLongLong("C_S_AXI_DATA_WIDTH");
|
||||
uint64_t dual_port=properties.getLongLong("C_SINGLE_PORT_BRAM");
|
||||
uint64_t ecc=properties.getLongLong("C_ECC");
|
||||
target_0_rd_socket = new xtlm::xtlm_aximm_target_socket("target_0_rd_socket", data_width);
|
||||
target_0_wr_socket = new xtlm::xtlm_aximm_target_socket("target_0_wr_socket", data_width);
|
||||
m_imp=new axi_bram_memory_imp("impl",properties);
|
||||
target_0_rd_socket->bind(*(m_imp->target_0_rd_socket));
|
||||
target_0_wr_socket->bind(*(m_imp->target_0_wr_socket));
|
||||
if(ecc==1)
|
||||
{
|
||||
s_axi_ctrl_target_rd_socket = new xtlm::xtlm_aximm_target_socket("target_1_rd_socket", 32);
|
||||
s_axi_ctrl_target_wr_socket = new xtlm::xtlm_aximm_target_socket("target_1_wr_socket", 32);
|
||||
auto* stubWr = new xtlm::xtlm_aximm_target_stub("ifWrStubskt0", 32);
|
||||
s_axi_ctrl_target_wr_socket->bind(stubWr->target_socket);
|
||||
auto* stubRd = new xtlm::xtlm_aximm_target_stub("ifRdStubskt0", 32);
|
||||
s_axi_ctrl_target_rd_socket->bind(stubRd->target_socket);
|
||||
stubInitSkt.push_back(stubWr);
|
||||
stubInitSkt.push_back(stubRd);
|
||||
}
|
||||
if(dual_port==1)
|
||||
{
|
||||
bram_rst_b(bram_rst_b1);
|
||||
bram_clk_b(bram_clk_b1);
|
||||
bram_en_b(bram_en_b1);
|
||||
bram_we_b(bram_we_b1);
|
||||
bram_addr_b(bram_addr_b1);
|
||||
bram_wrdata_b(bram_wrdata_b1);
|
||||
bram_rddata_b(bram_rddata_b1);
|
||||
}
|
||||
|
||||
SC_THREAD(clock_finder);
|
||||
sensitive<< s_axi_aclk;
|
||||
dont_initialize();
|
||||
|
||||
}
|
||||
axi_bram_ctrl::~axi_bram_ctrl() {
|
||||
delete target_0_rd_socket;
|
||||
delete target_0_wr_socket;
|
||||
delete m_imp;
|
||||
}
|
||||
void axi_bram_ctrl::clock_finder() {
|
||||
sc_time clk1 = sc_time_stamp();
|
||||
wait();
|
||||
sc_time clk2= sc_time_stamp();
|
||||
}
|
||||
+100
@@ -0,0 +1,100 @@
|
||||
// (c) Copyright 1995-2021, 2023 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
////////////////////////////////////////////////////////////
|
||||
|
||||
#ifndef _SIMHBMX_H_
|
||||
#define _SIMHBMX_H_
|
||||
|
||||
#include "xtlm.h"
|
||||
#include <list>
|
||||
|
||||
#include "axi_bram_memory_imp.h"
|
||||
#include "utils/xtlm_aximm_target_stub.h"
|
||||
#include "utils/xsc_stub_port.h"
|
||||
|
||||
class axi_bram_ctrl: public sc_core::sc_module {
|
||||
public:
|
||||
axi_bram_ctrl(const sc_module_name& module_name,xsc::common_cpp::properties&);
|
||||
virtual ~axi_bram_ctrl();
|
||||
SC_HAS_PROCESS(axi_bram_ctrl);
|
||||
//Slave interface used to R/W to HBM Memory
|
||||
xtlm::xtlm_aximm_target_socket* target_0_rd_socket;
|
||||
xtlm::xtlm_aximm_target_socket* target_0_wr_socket;
|
||||
xtlm::xtlm_aximm_target_socket* s_axi_ctrl_target_rd_socket;
|
||||
xtlm::xtlm_aximm_target_socket* s_axi_ctrl_target_wr_socket;
|
||||
std::vector<xtlm::xtlm_aximm_target_stub*> stubInitSkt;
|
||||
void clock_finder();
|
||||
sc_in<bool> s_axi_aclk;
|
||||
sc_in<bool> s_axi_aresetn;
|
||||
xsc::utils::xsc_stub_port ecc_interrupt;
|
||||
xsc::utils::xsc_stub_port ecc_ue;
|
||||
xsc::utils::xsc_stub_port bram_rst_a;
|
||||
xsc::utils::xsc_stub_port bram_clk_a;
|
||||
xsc::utils::xsc_stub_port bram_en_a;
|
||||
xsc::utils::xsc_stub_port bram_we_a;
|
||||
xsc::utils::xsc_stub_port bram_addr_a;
|
||||
xsc::utils::xsc_stub_port bram_wrdata_a;
|
||||
xsc::utils::xsc_stub_port bram_rddata_a;
|
||||
xsc::utils::xsc_stub_port bram_rst_b;
|
||||
xsc::utils::xsc_stub_port bram_clk_b;
|
||||
xsc::utils::xsc_stub_port bram_en_b;
|
||||
xsc::utils::xsc_stub_port bram_we_b;
|
||||
xsc::utils::xsc_stub_port bram_addr_b;
|
||||
xsc::utils::xsc_stub_port bram_wrdata_b;
|
||||
xsc::utils::xsc_stub_port bram_rddata_b;
|
||||
sc_core::sc_signal<bool>bram_rst_b1;
|
||||
sc_core::sc_signal<bool>bram_clk_b1;
|
||||
sc_core::sc_signal<bool>bram_en_b1;
|
||||
sc_core::sc_signal<bool>bram_we_b1;
|
||||
sc_core::sc_signal<bool>bram_addr_b1;
|
||||
sc_core::sc_signal<bool>bram_wrdata_b1;
|
||||
sc_core::sc_signal<bool>bram_rddata_b1;
|
||||
|
||||
|
||||
private :
|
||||
axi_bram_memory_imp* m_imp;
|
||||
};
|
||||
|
||||
#endif /* _SIMHBMX_H_ */
|
||||
+65
@@ -0,0 +1,65 @@
|
||||
// (c) Copyright 1995-2021, 2023 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
////////////////////////////////////////////////////////////
|
||||
|
||||
#include <sys/stat.h>
|
||||
#include "axi_bram_fmodel_base.h"
|
||||
//#define DEBUGMSG
|
||||
|
||||
|
||||
axi_bram_fmodel_base::~ axi_bram_fmodel_base()
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
axi_bram_fmodel_base::axi_bram_fmodel_base(std::string p_module_name,xsc::common_cpp::report_handler* report_handler,uint64_t addr_size): module_name(p_module_name)
|
||||
{
|
||||
}
|
||||
|
||||
void axi_bram_fmodel_base::init_fmodel()
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
+95
@@ -0,0 +1,95 @@
|
||||
// (c) Copyright 1995-2021, 2023 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
////////////////////////////////////////////////////////////
|
||||
|
||||
#ifndef XTLM_SIMPLE_FMODEL_BASE__H
|
||||
#define XTLM_SIMPLE_FMODEL_BASE__H
|
||||
#include <math.h>
|
||||
#include <iostream>
|
||||
|
||||
#include <string.h> // memcpy
|
||||
#include <stdlib.h> //realloc
|
||||
#include <stdint.h>
|
||||
#include <vector>
|
||||
#include <map> //realloc
|
||||
#include <unistd.h>
|
||||
#include <sys/types.h>
|
||||
#include <sys/stat.h>
|
||||
#include <fcntl.h>
|
||||
#include <sys/mman.h>
|
||||
#include "report_handler.h"
|
||||
|
||||
#define ONE_KB (0x400)
|
||||
#define ONE_MB (ONE_KB * ONE_KB)
|
||||
#define PAGESIZE (ONE_MB)
|
||||
#define ADDRBITS (20)
|
||||
#define N_1MBARRAYS 4096
|
||||
|
||||
class axi_bram_fmodel_base {
|
||||
public:
|
||||
virtual unsigned int writeDevMem(uint64_t offset, void* src,
|
||||
unsigned int size) = 0;
|
||||
virtual unsigned int readDevMem(uint64_t offset, void* dest,
|
||||
unsigned int size) = 0;
|
||||
virtual bool createMMappedBuffer(uint64_t base_address, uint64_t size,
|
||||
std::string& buffer_filename) = 0;
|
||||
virtual bool freePage(uint64_t base_address) = 0;
|
||||
virtual unsigned char* get_page(uint64_t offset, std::string& p2pFileName,
|
||||
uint64_t size = 0) = 0;
|
||||
virtual bool copyBO(uint64_t offset, std::string dst_filename,
|
||||
uint64_t size, uint64_t src_offset, uint64_t dst_offset) = 0;
|
||||
virtual bool importBO(uint64_t offset, std::string dst_filename,
|
||||
uint64_t size) = 0;
|
||||
axi_bram_fmodel_base(std::string p_module_name,
|
||||
xsc::common_cpp::report_handler* report_handler,
|
||||
uint64_t addr_size);
|
||||
virtual ~ axi_bram_fmodel_base();
|
||||
void init_fmodel();
|
||||
virtual void reset_fmodel() = 0;
|
||||
std::string module_name;
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
+441
@@ -0,0 +1,441 @@
|
||||
// (c) Copyright 1995-2021, 2023 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
////////////////////////////////////////////////////////////
|
||||
|
||||
#include "axi_bram_fmodel_shared_memory.h"
|
||||
#include <sys/stat.h>
|
||||
#include <sstream>
|
||||
|
||||
std::map<std::string, std::tuple<uint64_t, void*, int> > axi_bram_fmodel_shared_memory::mFileFdMap;
|
||||
|
||||
axi_bram_fmodel_shared_memory::axi_bram_fmodel_shared_memory(
|
||||
std::string p_module_name,
|
||||
xsc::common_cpp::report_handler* report_handler, uint64_t addr_size) : //Mode 0
|
||||
axi_bram_fmodel_base(p_module_name, report_handler, addr_size) {
|
||||
m_report_handler = report_handler;
|
||||
if (m_report_handler->get_verbosity_level()
|
||||
== xsc::common_cpp::VERBOSITY::DEBUG) {
|
||||
std::stringstream m_ss;
|
||||
m_ss.str("");
|
||||
m_ss << module_name << std::endl;
|
||||
XSC_REPORT_INFO((*m_report_handler), "xtlmmemorymodel_shared_memory",
|
||||
m_ss.str().c_str());
|
||||
}
|
||||
}
|
||||
|
||||
void axi_bram_fmodel_shared_memory::reset_fmodel() {
|
||||
auto pageIt = mPageCache.begin();
|
||||
auto pageEnd = mPageCache.end();
|
||||
while (pageIt != pageEnd) {
|
||||
uint64_t offset = (*pageIt).first;
|
||||
|
||||
auto itr = mOffsetFileMap.find(offset);
|
||||
int fd = -1;
|
||||
if (itr != mOffsetFileMap.end()) {
|
||||
std::string sFileName = (*itr).second;
|
||||
auto itr2 = mFileFdMap.find(sFileName);
|
||||
if (itr2 != mFileFdMap.end()) {
|
||||
fd = std::get<0>((*itr2).second);
|
||||
void* pPtr = std::get<1>((*itr2).second);
|
||||
int size = std::get<2>((*itr2).second);
|
||||
munmap(pPtr, size);
|
||||
mFileFdMap.erase(itr2);
|
||||
close(fd);
|
||||
}
|
||||
}
|
||||
pageIt++;
|
||||
}
|
||||
|
||||
}
|
||||
axi_bram_fmodel_shared_memory::~axi_bram_fmodel_shared_memory() {
|
||||
}
|
||||
|
||||
unsigned int axi_bram_fmodel_shared_memory::writeDevMem(uint64_t offset,
|
||||
void* src, unsigned int size) {
|
||||
|
||||
uint64_t written_bytes = 0;
|
||||
uint64_t addr = offset;
|
||||
while (written_bytes < size) {
|
||||
uint64_t src_offset = written_bytes;
|
||||
|
||||
std::string p2pFileName("");
|
||||
unsigned char* page_ptr = get_page(addr, p2pFileName);
|
||||
uint64_t ddrAddress = getBaseDdrAddress(addr);
|
||||
if (!page_ptr) {
|
||||
std::stringstream errMsg;
|
||||
errMsg
|
||||
<< "Kernel attempting to write to memory which was never allocated ("
|
||||
<< std::hex << "0x" << offset << ")" << std::dec;
|
||||
XSC_REPORT_INFO((*m_report_handler),
|
||||
"xtlmsimplememorymodel_shared_memory",
|
||||
errMsg.str().c_str());
|
||||
return 0;
|
||||
}
|
||||
unsigned char* dest_buf_ptr = page_ptr + offset - ddrAddress;
|
||||
unsigned char* src_buf_ptr = (unsigned char*) (src) + src_offset;
|
||||
|
||||
uint64_t remaining_bytes_to_write = size - written_bytes;
|
||||
//memcpy(dest_buf_ptr,src_buf_ptr,buf_size);
|
||||
for (unsigned int i = 0; i < remaining_bytes_to_write; i++) {
|
||||
dest_buf_ptr[i] = src_buf_ptr[i];
|
||||
}
|
||||
|
||||
written_bytes += remaining_bytes_to_write;
|
||||
addr += remaining_bytes_to_write;
|
||||
}
|
||||
|
||||
if (m_report_handler->get_verbosity_level()
|
||||
== xsc::common_cpp::VERBOSITY::DEBUG) {
|
||||
std::stringstream m_ss;
|
||||
m_ss.str("");
|
||||
m_ss << "Write Operation size : " << size << std::endl;
|
||||
for (int i = 0; i < size; i++) {
|
||||
m_ss << std::hex << (unsigned int) (((unsigned char*) src)[i])
|
||||
<< " ";
|
||||
}
|
||||
m_ss << std::endl;
|
||||
m_ss << "Write : " << "Offset --> " << offset << std::endl;
|
||||
XSC_REPORT_INFO((*m_report_handler), "xtlmmemorymodel_shared_memory",
|
||||
m_ss.str().c_str());
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
unsigned int axi_bram_fmodel_shared_memory::readDevMem(uint64_t offset,
|
||||
void* dest, unsigned int size) {
|
||||
uint64_t read_bytes = 0;
|
||||
uint64_t addr = offset;
|
||||
while (read_bytes < size) {
|
||||
uint64_t dest_offset = read_bytes;
|
||||
|
||||
std::string p2pFileName("");
|
||||
unsigned char* page_ptr = get_page(addr, p2pFileName);
|
||||
uint64_t ddrAddress = getBaseDdrAddress(addr);
|
||||
|
||||
if (!page_ptr) {
|
||||
if (m_report_handler->get_verbosity_level()
|
||||
== xsc::common_cpp::VERBOSITY::DEBUG) {
|
||||
std::stringstream errMsg;
|
||||
errMsg
|
||||
<< "Kernel attempting to read to memory which was never allocated ("
|
||||
<< std::hex << "0x" << offset << ")" << std::dec;
|
||||
XSC_REPORT_INFO((*m_report_handler),
|
||||
"xtlmsimplememorymodel_shared_memory",
|
||||
errMsg.str().c_str());
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
unsigned char* src_buf_ptr = page_ptr + (offset - ddrAddress);
|
||||
unsigned char* dest_buf_ptr = (unsigned char*) (dest) + dest_offset;
|
||||
|
||||
uint64_t remaining_bytes_to_read = size - read_bytes;
|
||||
|
||||
for (uint64_t i = 0; i < remaining_bytes_to_read; i++) {
|
||||
dest_buf_ptr[i] = src_buf_ptr[i];
|
||||
}
|
||||
|
||||
read_bytes += remaining_bytes_to_read;
|
||||
addr += remaining_bytes_to_read;
|
||||
}
|
||||
|
||||
if (m_report_handler->get_verbosity_level()
|
||||
== xsc::common_cpp::VERBOSITY::DEBUG) {
|
||||
std::stringstream m_ss;
|
||||
m_ss.str("");
|
||||
m_ss << "Read Operation size : " << size << std::endl;
|
||||
for (int i = 0; i < size; i++) {
|
||||
m_ss << std::hex << (unsigned int) (((unsigned char*) dest)[i])
|
||||
<< " ";
|
||||
}
|
||||
m_ss << std::endl;
|
||||
m_ss << "Read : " << "Offset --> " << offset << std::endl;
|
||||
XSC_REPORT_INFO((*m_report_handler),
|
||||
"xtlmsimplememorymodel_shared_memory", m_ss.str().c_str());
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
unsigned char* axi_bram_fmodel_shared_memory::get_page(uint64_t offset,
|
||||
std::string& p2pFileName, uint64_t size) {
|
||||
auto pageIt = mPageCache.begin();
|
||||
auto pageEnd = mPageCache.end();
|
||||
while (pageIt != pageEnd) {
|
||||
uint64_t startAddress = (*pageIt).first;
|
||||
std::pair<unsigned char*, uint64_t> addressSizePair = (*pageIt).second;
|
||||
unsigned char* pageStartOSAddress = addressSizePair.first;
|
||||
uint64_t pageSize = addressSizePair.second;
|
||||
if (offset >= startAddress && offset < startAddress + pageSize) {
|
||||
return pageStartOSAddress;
|
||||
}
|
||||
pageIt++;
|
||||
}
|
||||
//in partial reconfiguration case, we should read the file which is stored.
|
||||
|
||||
return NULL;
|
||||
|
||||
}
|
||||
|
||||
uint64_t axi_bram_fmodel_shared_memory::getBaseDdrAddress(uint64_t offset) {
|
||||
auto pageIt = mPageCache.begin();
|
||||
auto pageEnd = mPageCache.end();
|
||||
while (pageIt != pageEnd) {
|
||||
uint64_t startAddress = (*pageIt).first;
|
||||
std::pair<unsigned char*, uint64_t> addressSizePair = (*pageIt).second;
|
||||
uint64_t pageSize = addressSizePair.second;
|
||||
if (offset >= startAddress && offset < startAddress + pageSize) {
|
||||
return startAddress;
|
||||
}
|
||||
pageIt++;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
bool axi_bram_fmodel_shared_memory::copyBO(uint64_t offset,
|
||||
std::string dst_filename, uint64_t size, uint64_t src_offset,
|
||||
uint64_t dst_offset) {
|
||||
uint64_t read_bytes = 0;
|
||||
uint64_t addr = offset;
|
||||
std::string p2pFileName("");
|
||||
unsigned char* page_ptr = get_page(addr, p2pFileName);
|
||||
uint64_t ddrAddress = getBaseDdrAddress(addr);
|
||||
unsigned char* src_buf_ptr = (unsigned char*) (page_ptr
|
||||
+ (offset - ddrAddress) + src_offset);
|
||||
auto itr = mFileFdMap.find(dst_filename);
|
||||
if (itr != mFileFdMap.end()) {
|
||||
int dst_fd = std::get<0>((*itr).second);
|
||||
if (lseek(dst_fd, dst_offset, SEEK_CUR) < 0)
|
||||
return false;
|
||||
int bytes_written = write(dst_fd, src_buf_ptr,
|
||||
size/*strlen(src_buf_ptr)*/);
|
||||
if (bytes_written < 0) {
|
||||
std::cout << "Failed to write into file " << dst_fd << std::endl;
|
||||
} else {
|
||||
std::cout << "bytes_written is " << bytes_written
|
||||
<< " is successful " << std::endl;
|
||||
}
|
||||
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
bool axi_bram_fmodel_shared_memory::importBO(uint64_t offset,
|
||||
std::string sFileName, uint64_t size) {
|
||||
int fd = -1;
|
||||
if ((fd = open(sFileName.c_str(), O_CREAT | O_RDWR,
|
||||
S_IRWXU | S_IRGRP | S_IROTH)) == -1) {
|
||||
printf("Error opening file.\n");
|
||||
};
|
||||
if (fd < 0)
|
||||
return false;
|
||||
void* pageStartOSAddressVoid = mmap(0, size,
|
||||
PROT_READ | PROT_WRITE | PROT_EXEC, MAP_SHARED, fd,
|
||||
0/*sysconf(_SC_PAGESIZE)*/);
|
||||
if (ftruncate(fd, size) < 0) {
|
||||
close(fd);
|
||||
munmap(pageStartOSAddressVoid, size);
|
||||
return false;
|
||||
}
|
||||
mFileFdMap[sFileName] = std::make_tuple(fd, pageStartOSAddressVoid, size);
|
||||
mOffsetFileMap[offset] = sFileName;
|
||||
}
|
||||
|
||||
//create a page at offset. Return if already exist
|
||||
std::string axi_bram_fmodel_shared_memory::createPage(uint64_t offset,
|
||||
uint64_t size, bool p2p) {
|
||||
std::string sFileName("");
|
||||
int fd = -1;
|
||||
auto pageIt = mPageCache.begin();
|
||||
auto pageEnd = mPageCache.end();
|
||||
while (pageIt != pageEnd) {
|
||||
uint64_t startAddress = (*pageIt).first;
|
||||
std::pair<unsigned char*, uint64_t> addressSizePair = (*pageIt).second;
|
||||
uint64_t pageSize = addressSizePair.second;
|
||||
if (offset >= startAddress && offset < startAddress + pageSize) {
|
||||
freePage(offset);
|
||||
//new offset is conflicting old addresses
|
||||
//return "";
|
||||
}
|
||||
pageIt++;
|
||||
}
|
||||
|
||||
void* pageStartOSAddressVoid = NULL;
|
||||
// TODO: DDR_BUFFER_ALIGNMENT 0x1000 (4096) this is declared in runtime shim.
|
||||
// below variable is based on it.
|
||||
size_t alignmentForBuffer = 4096; // previously sizeof(double) * 16
|
||||
|
||||
if (!p2p) {
|
||||
if (posix_memalign(&pageStartOSAddressVoid, alignmentForBuffer, size)) {
|
||||
pageStartOSAddressVoid = NULL;
|
||||
}
|
||||
} else {
|
||||
std::stringstream ssFileName;
|
||||
sFileName = get_mem_file_name(offset);
|
||||
ssFileName << sFileName << "_shared";
|
||||
sFileName = ssFileName.str(); //config::getInstance()->getDeviceDirectory() + "/" + ssFileName.str();
|
||||
if ((fd = open(sFileName.c_str(), O_CREAT | O_RDWR,
|
||||
S_IRWXU | S_IRGRP | S_IROTH)) == -1) {
|
||||
printf("Error opening file.\n");
|
||||
}
|
||||
pageStartOSAddressVoid = mmap(0, size,
|
||||
PROT_READ | PROT_WRITE | PROT_EXEC, MAP_SHARED, fd,
|
||||
0/*sysconf(_SC_PAGESIZE)*/);
|
||||
if (fd < 0) {
|
||||
munmap(pageStartOSAddressVoid, size);
|
||||
return sFileName;
|
||||
}
|
||||
|
||||
if (ftruncate(fd, size) < 0) {
|
||||
close(fd);
|
||||
munmap(pageStartOSAddressVoid, size);
|
||||
return sFileName;
|
||||
}
|
||||
}
|
||||
if (!pageStartOSAddressVoid) {
|
||||
close(fd);
|
||||
return sFileName;
|
||||
}
|
||||
|
||||
if (!sFileName.empty()) {
|
||||
mFileFdMap[sFileName] = std::make_tuple(fd, pageStartOSAddressVoid,
|
||||
size);
|
||||
mOffsetFileMap[offset] = sFileName;
|
||||
}
|
||||
|
||||
unsigned char* pageStartOSAddress = (unsigned char*) pageStartOSAddressVoid;
|
||||
mPageCache[offset] = std::make_pair(pageStartOSAddress, size);
|
||||
return sFileName;
|
||||
}
|
||||
//free page at offset. Return if already exist
|
||||
bool axi_bram_fmodel_shared_memory::freePage(uint64_t offset) {
|
||||
bool mMappedBuffer = false;
|
||||
auto itr = mOffsetFileMap.find(offset);
|
||||
int fd = -1;
|
||||
|
||||
if (itr != mOffsetFileMap.end()) {
|
||||
mMappedBuffer = true;
|
||||
std::string sFileName = (*itr).second;
|
||||
auto itr2 = mFileFdMap.find(sFileName);
|
||||
if (itr2 != mFileFdMap.end()) {
|
||||
fd = std::get<0>((*itr2).second);
|
||||
void* pPtr = std::get<1>((*itr2).second);
|
||||
int size = std::get<2>((*itr2).second);
|
||||
munmap(pPtr, size);
|
||||
mFileFdMap.erase(itr2);
|
||||
}
|
||||
}
|
||||
auto pageIt = mPageCache.find(offset);
|
||||
if (pageIt != mPageCache.end()) {
|
||||
std::pair<unsigned char*, uint64_t> addressSizePair = (*pageIt).second;
|
||||
unsigned char* osAddress = addressSizePair.first;
|
||||
uint64_t size = addressSizePair.second;
|
||||
if (osAddress) {
|
||||
if (!mMappedBuffer)
|
||||
free((void *) osAddress);
|
||||
else {
|
||||
munmap(osAddress, size);
|
||||
if (fd != -1) {
|
||||
close(fd);
|
||||
}
|
||||
}
|
||||
}
|
||||
mPageCache.erase(pageIt);
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
bool axi_bram_fmodel_shared_memory::createMMappedBuffer(
|
||||
uint64_t base_address, uint64_t size, std::string& buffer_filename) {
|
||||
buffer_filename = createPage(base_address, size, true);
|
||||
return true;
|
||||
}
|
||||
|
||||
std::string axi_bram_fmodel_shared_memory::get_mem_file_name(
|
||||
uint64_t pageIdx) //,enum fileType file_type)
|
||||
{
|
||||
std::string file_name;
|
||||
std::string socket_id;
|
||||
std::string pid;
|
||||
std::string deviceName("");
|
||||
std::string user("");
|
||||
if (getenv("EMULATION_SOCKETID")) {
|
||||
socket_id = getenv("EMULATION_SOCKETID");
|
||||
std::size_t foundLast = socket_id.find_last_of("_");
|
||||
std::size_t foundFirst = socket_id.find_first_of("_");
|
||||
if (foundLast != std::string::npos) {
|
||||
pid = socket_id.substr(foundLast + 1);
|
||||
}
|
||||
if (foundFirst != std::string::npos) {
|
||||
deviceName = socket_id.substr(0, foundFirst);
|
||||
}
|
||||
}
|
||||
|
||||
if (getenv("USER") != NULL) {
|
||||
user = getenv("USER");
|
||||
}
|
||||
std::string file_path("");
|
||||
std::string sEmRunDir("");
|
||||
|
||||
if (getenv("EMULATION_RUN_DIR")) {
|
||||
sEmRunDir = getenv("EMULATION_RUN_DIR");
|
||||
} else {
|
||||
sEmRunDir = "/tmp/" + user + "/hw_em/";
|
||||
}
|
||||
|
||||
file_path = sEmRunDir + "/" + module_name + "/";
|
||||
std::stringstream mkdirCommand;
|
||||
mkdirCommand << "mkdir -p " << file_path;
|
||||
;
|
||||
struct stat statBuf;
|
||||
if (stat(file_path.c_str(), &statBuf) == -1) {
|
||||
system(mkdirCommand.str().c_str());
|
||||
}
|
||||
file_name = file_path + module_name + "_" + std::to_string(pageIdx);
|
||||
return file_name;
|
||||
}
|
||||
|
||||
+85
@@ -0,0 +1,85 @@
|
||||
// (c) Copyright 1995-2021, 2023 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
////////////////////////////////////////////////////////////
|
||||
|
||||
#ifndef axi_bram_FMODEL_SHARED_MEMORY__H
|
||||
#define axi_bram_FMODEL_SHARED_MEMORY__H
|
||||
|
||||
#include "axi_bram_fmodel_base.h"
|
||||
#include "report_handler.h"
|
||||
|
||||
class axi_bram_fmodel_shared_memory: public axi_bram_fmodel_base {
|
||||
public:
|
||||
unsigned int writeDevMem(uint64_t offset, void* src, unsigned int size);
|
||||
unsigned int readDevMem(uint64_t offset, void* dest, unsigned int size);
|
||||
bool createMMappedBuffer(uint64_t base_address, uint64_t size,
|
||||
std::string& buffer_filename);
|
||||
unsigned char* get_page(uint64_t offset, std::string& p2pFileName,
|
||||
uint64_t size = 0);
|
||||
uint64_t getBaseDdrAddress(uint64_t offset); //get the DDR base address of offset
|
||||
bool copyBO(uint64_t offset, std::string dst_filename, uint64_t size,
|
||||
uint64_t src_offset, uint64_t dst_offset);
|
||||
bool importBO(uint64_t offset, std::string dst_filename, uint64_t size);
|
||||
std::string createPage(uint64_t offset, uint64_t size, bool p2p); //create a page of size "size" and add it in mPageCache Map.
|
||||
bool freePage(uint64_t offset); //free page and remove it from mPageCache Map.
|
||||
std::string get_mem_file_name(uint64_t pageIdx);
|
||||
|
||||
public:
|
||||
axi_bram_fmodel_shared_memory(std::string p_module_name,
|
||||
xsc::common_cpp::report_handler* report_handler,
|
||||
uint64_t addr_size);
|
||||
~ axi_bram_fmodel_shared_memory();
|
||||
void reset_fmodel();
|
||||
private:
|
||||
//Paging
|
||||
std::map<uint64_t, std::pair<unsigned char*, uint64_t> > mPageCache; // this map is used to store ddrAddress and OsAddress Mapping.
|
||||
static std::map<std::string, std::tuple<uint64_t, void*, int> > mFileFdMap; //filename and fd map
|
||||
std::map<uint64_t, std::string> mOffsetFileMap; //offset and filename map
|
||||
xsc::common_cpp::report_handler *m_report_handler;
|
||||
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
+406
@@ -0,0 +1,406 @@
|
||||
// (c) Copyright 1995-2021, 2023 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
////////////////////////////////////////////////////////////
|
||||
|
||||
#include "axi_bram_memory_imp.h"
|
||||
#include "P2P_XTLM_extension.h"
|
||||
|
||||
#include <sstream>
|
||||
#include <bitset>
|
||||
|
||||
class axi_bram_memory_imp::target_rd_util: public xtlm::xtlm_aximm_target_rd_socket_util {
|
||||
public:
|
||||
target_rd_util(sc_core::sc_module_name p_name,
|
||||
xtlm::aximm::granularity g_hint, int width_p,
|
||||
axi_bram_memory_imp* _parent) :
|
||||
xtlm::xtlm_aximm_target_rd_socket_util(p_name, g_hint, width_p) {
|
||||
this->parent = _parent;
|
||||
}
|
||||
unsigned int transport_dbg_cb(xtlm::aximm_payload& trans) {
|
||||
return parent->transport_dbg(trans);
|
||||
}
|
||||
private:
|
||||
axi_bram_memory_imp* parent;
|
||||
};
|
||||
|
||||
class axi_bram_memory_imp::target_wr_util: public xtlm::xtlm_aximm_target_wr_socket_util {
|
||||
public:
|
||||
target_wr_util(sc_core::sc_module_name p_name,
|
||||
xtlm::aximm::granularity g_hint, int width_p,
|
||||
axi_bram_memory_imp* _parent) :
|
||||
xtlm::xtlm_aximm_target_wr_socket_util(p_name, g_hint, width_p) {
|
||||
this->parent = _parent;
|
||||
}
|
||||
unsigned int transport_dbg_cb(xtlm::aximm_payload& trans) {
|
||||
return parent->transport_dbg(trans);
|
||||
}
|
||||
private:
|
||||
axi_bram_memory_imp* parent;
|
||||
};
|
||||
|
||||
axi_bram_memory_imp::axi_bram_memory_imp(
|
||||
const sc_module_name& module_name,
|
||||
xsc::common_cpp::properties& properties) :
|
||||
sc_module(module_name) {
|
||||
m_data_width = properties.getLongLong("C_S_AXI_DATA_WIDTH");
|
||||
m_mem_addr_width = properties.getLongLong("C_MEMORY_DEPTH");
|
||||
m_mem_addr_width *= m_data_width;
|
||||
|
||||
target_0_rd_socket = new xtlm::xtlm_aximm_target_socket(
|
||||
"saxi_hbmx_imp_rd_socket", m_data_width);
|
||||
target_0_wr_socket = new xtlm::xtlm_aximm_target_socket("saxi_cq_wrie_skt",
|
||||
m_data_width);
|
||||
m_target_0_rd_socket_util = new target_rd_util(
|
||||
"saxi_hbmx_imp_rd_socket_util",
|
||||
xtlm::aximm::granularity::TRANSACTION, m_data_width, this);
|
||||
m_target_0_wr_socket_util = new target_wr_util(
|
||||
"saxi_hbmx_imp_wr_socket_util",
|
||||
xtlm::aximm::granularity::TRANSACTION, m_data_width, this);
|
||||
target_0_rd_socket->bind((m_target_0_rd_socket_util->rd_socket));
|
||||
target_0_wr_socket->bind((m_target_0_wr_socket_util->wr_socket));
|
||||
std::string mod_name = name();
|
||||
m_report_handler = new xsc::common_cpp::report_handler(mod_name);
|
||||
if (!getenv("SDX_USE_SHARED_MEMORY"))
|
||||
m_mem_handler = new axi_bram_ram_fmodel(this->name(),
|
||||
m_report_handler, m_mem_addr_width); //name() returns hierarchical name of ddr systemc module instance
|
||||
else
|
||||
m_mem_handler = new axi_bram_fmodel_shared_memory(this->name(),
|
||||
m_report_handler, m_mem_addr_width); //name() returns hierarchical name of ddr systemc module instance
|
||||
|
||||
//m_mem_handler=new axi_bram_memory_fmodel_base(mod_name,m_report_handler,m_mem_addr_width);
|
||||
|
||||
SC_METHOD(methodProcessTransactionRead);
|
||||
sensitive << m_target_0_rd_socket_util->transaction_available;
|
||||
sensitive << m_target_0_rd_socket_util->data_sampled;
|
||||
dont_initialize();
|
||||
|
||||
//m_report_handler->set_verbosity_level(xsc::common_cpp::VERBOSITY::DEBUG);
|
||||
SC_METHOD(methodProcessTransactionWrite);
|
||||
sensitive << m_target_0_wr_socket_util->transaction_available;
|
||||
sensitive << m_target_0_wr_socket_util->resp_sampled;
|
||||
dont_initialize();
|
||||
}
|
||||
|
||||
axi_bram_memory_imp::~axi_bram_memory_imp() {
|
||||
delete target_0_rd_socket;
|
||||
delete target_0_wr_socket;
|
||||
delete m_target_0_rd_socket_util;
|
||||
delete m_target_0_wr_socket_util;
|
||||
delete m_report_handler;
|
||||
delete m_mem_handler;
|
||||
}
|
||||
|
||||
void axi_bram_memory_imp::methodProcessTransactionRead() {
|
||||
std::stringstream ss;
|
||||
if (m_target_0_rd_socket_util->is_trans_available()) {
|
||||
xtlm::aximm_payload* trans =
|
||||
m_target_0_rd_socket_util->get_transaction();
|
||||
sc_core::sc_time delay = SC_ZERO_TIME;
|
||||
uint64_t max_address = m_mem_addr_width;
|
||||
uint64_t address = trans->get_address() % max_address;
|
||||
uint64_t tranSize = trans->get_data_length();
|
||||
ss.clear();
|
||||
std::string des;
|
||||
if (m_report_handler->get_verbosity_level() == xsc::common_cpp::DEBUG) {
|
||||
trans->get_log(des, 1);
|
||||
ss << name() << ": Received Read Request " << des << std::endl;
|
||||
XSC_REPORT_INFO_VERB((*m_report_handler), "1", ss.str().c_str(),
|
||||
DEBUG);
|
||||
}
|
||||
if ((address + tranSize) > max_address) {
|
||||
ss.clear();
|
||||
ss << name() << ": Invalid Read Request " << std::endl << des
|
||||
<< std::endl;
|
||||
XSC_REPORT_ERROR((*m_report_handler), "1", ss.str().c_str());
|
||||
trans->set_response_status(xtlm::XTLM_ADDRESS_ERROR_RESPONSE);
|
||||
} else {
|
||||
ss.clear();
|
||||
trans->set_response_status(xtlm::XTLM_OK_RESPONSE);
|
||||
unsigned char* data_ptr = trans->get_data_ptr();
|
||||
m_mem_handler->readDevMem(address, data_ptr, tranSize);
|
||||
}
|
||||
m_rd_req_vec.push_back(trans);
|
||||
}
|
||||
if (m_rd_req_vec.empty() == false
|
||||
&& m_target_0_rd_socket_util->is_master_ready()) {
|
||||
ss.clear();
|
||||
xtlm::aximm_payload* trans = m_rd_req_vec.front();
|
||||
if (m_report_handler->get_verbosity_level() == xsc::common_cpp::DEBUG) {
|
||||
std::string des;
|
||||
trans->get_log(des, 1);
|
||||
ss << name() << ": Sending Read Response " << std::endl << des
|
||||
<< std::endl;
|
||||
XSC_REPORT_INFO_VERB((*m_report_handler), "1", ss.str().c_str(),
|
||||
DEBUG);
|
||||
}
|
||||
sc_core::sc_time delay = SC_ZERO_TIME;
|
||||
m_target_0_rd_socket_util->send_data(*trans, delay);
|
||||
m_rd_req_vec.pop_front();
|
||||
}
|
||||
}
|
||||
|
||||
void axi_bram_memory_imp::methodProcessTransactionWrite() {
|
||||
std::stringstream ss;
|
||||
if (m_target_0_wr_socket_util->is_trans_available()) {
|
||||
xtlm::aximm_payload* trans =
|
||||
m_target_0_wr_socket_util->get_transaction();
|
||||
uint64_t max_address = m_mem_addr_width;
|
||||
uint64_t address = trans->get_address() % max_address;
|
||||
uint64_t tranSize = trans->get_data_length();
|
||||
//Check for the address range
|
||||
trans->set_response_status(xtlm::XTLM_OK_RESPONSE);
|
||||
if ((address + tranSize) > max_address) {
|
||||
ss.clear();
|
||||
std::string des;
|
||||
trans->get_log(des, 1);
|
||||
ss << name() << ": Invalid Write Request " << std::endl << des
|
||||
<< std::endl;
|
||||
XSC_REPORT_ERROR((*m_report_handler), "1", ss.str().c_str());
|
||||
trans->set_response_status(xtlm::XTLM_ADDRESS_ERROR_RESPONSE);
|
||||
|
||||
} else {
|
||||
xtlm::xtlm_extension<xsc::extension::P2P_XTLM_extension>* bExt;
|
||||
trans->get_extension(bExt);
|
||||
xsc::extension::P2P_XTLM_extension * ext =
|
||||
dynamic_cast<xsc::extension::P2P_XTLM_extension *>(bExt);
|
||||
if (ext != nullptr) {
|
||||
std::string filename;
|
||||
bool ret = true;
|
||||
if (ext->getType() == xsc::extension::TYPE::ALLOC_BO)
|
||||
ret = m_mem_handler->createMMappedBuffer(
|
||||
address, ext->getSize(), filename);
|
||||
else if (ext->getType() == xsc::extension::TYPE::FREE_BO)
|
||||
ret = m_mem_handler->freePage(address);
|
||||
else if (ext->getType() == xsc::extension::TYPE::IMPORT_BO) {
|
||||
ret = m_mem_handler->importBO(address,
|
||||
ext->getFileName(), ext->getSize());
|
||||
} else if (ext->getType() == xsc::extension::TYPE::COPY_BO) {
|
||||
ret = m_mem_handler->copyBO(address,
|
||||
ext->getFileName(), ext->getSize(),
|
||||
ext->getSrcOffset(), ext->getDstOffset());
|
||||
}
|
||||
ext->setResponse(ret);
|
||||
ext->setFileName(filename);
|
||||
}
|
||||
|
||||
else if (!trans->get_byte_enable_ptr()) {
|
||||
unsigned char* data_ptr = trans->get_data_ptr();
|
||||
if (m_report_handler->get_verbosity_level()
|
||||
== xsc::common_cpp::DEBUG) {
|
||||
ss.clear();
|
||||
std::string des;
|
||||
trans->get_log(des, 1);
|
||||
ss << name() << ": Received Write Request " << std::endl
|
||||
<< des << std::endl;
|
||||
XSC_REPORT_INFO_VERB((*m_report_handler), "1",
|
||||
ss.str().c_str(), DEBUG);
|
||||
}
|
||||
|
||||
m_mem_handler->writeDevMem(address, data_ptr, tranSize);
|
||||
} else {
|
||||
if (m_report_handler->get_verbosity_level()
|
||||
== xsc::common_cpp::DEBUG) {
|
||||
ss.clear();
|
||||
std::string des;
|
||||
trans->get_log(des, 1);
|
||||
ss << name() << ": Received Write Request " << std::endl
|
||||
<< des << std::endl;
|
||||
XSC_REPORT_INFO_VERB((*m_report_handler), "1",
|
||||
ss.str().c_str(), DEBUG);
|
||||
}
|
||||
unsigned char* data_ptr = trans->get_data_ptr();
|
||||
unsigned char* byte_enable_ptr = trans->get_byte_enable_ptr();
|
||||
uint64_t byte_enable_len = trans->get_byte_enable_length();
|
||||
uint32_t index = 0;
|
||||
for (index = 1; index <= tranSize; index++) {
|
||||
bool byteEn = byte_enable_ptr[(index - 1) % byte_enable_len];
|
||||
if (byteEn) {
|
||||
m_mem_handler->writeDevMem(index + address - 1,
|
||||
data_ptr + (index - 1), 1);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
m_wr_resp_vec.push_back(trans);
|
||||
}
|
||||
if (m_wr_resp_vec.empty() == false
|
||||
&& m_target_0_wr_socket_util->is_master_ready()) {
|
||||
std::stringstream msg;
|
||||
sc_core::sc_time delay = SC_ZERO_TIME;
|
||||
xtlm::aximm_payload* trans = m_wr_resp_vec.front();
|
||||
if (m_report_handler->get_verbosity_level() == xsc::common_cpp::DEBUG) {
|
||||
ss.clear();
|
||||
std::string des;
|
||||
trans->get_log(des, 1);
|
||||
ss << name() << ": Sending Write Request " << std::endl << des
|
||||
<< std::endl;
|
||||
XSC_REPORT_INFO_VERB((*m_report_handler), "1", ss.str().c_str(),
|
||||
DEBUG);
|
||||
}
|
||||
m_target_0_wr_socket_util->send_resp(*trans, delay);
|
||||
m_wr_resp_vec.pop_front();
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
unsigned int axi_bram_memory_imp::transport_dbg(xtlm::aximm_payload& trans) {
|
||||
if (trans.get_command() == xtlm::XTLM_READ_COMMAND) {
|
||||
return transport_dbg_rd(trans);
|
||||
} else if (trans.get_command() == xtlm::XTLM_WRITE_COMMAND) {
|
||||
return transport_dbg_wr(trans);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
unsigned int axi_bram_memory_imp::transport_dbg_rd(
|
||||
xtlm::aximm_payload& trans) {
|
||||
sc_core::sc_time delay = SC_ZERO_TIME;
|
||||
uint64_t max_address = m_mem_addr_width;
|
||||
uint64_t address = trans.get_address() % max_address;
|
||||
uint64_t tranSize = trans.get_data_length();
|
||||
std::stringstream ss;
|
||||
ss.clear();
|
||||
std::string des;
|
||||
if (m_report_handler->get_verbosity_level() == xsc::common_cpp::DEBUG) {
|
||||
trans.get_log(des, 1);
|
||||
ss << name() << ": Received Debug Read Request " << des << std::endl;
|
||||
XSC_REPORT_INFO_VERB((*m_report_handler), "1", ss.str().c_str(), DEBUG);
|
||||
}
|
||||
if ((address + tranSize) > max_address) {
|
||||
ss.clear();
|
||||
ss << name() << ": Invalid Debug Read Request " << std::endl << des
|
||||
<< std::endl;
|
||||
XSC_REPORT_ERROR((*m_report_handler), "1", ss.str().c_str());
|
||||
trans.set_response_status(xtlm::XTLM_ADDRESS_ERROR_RESPONSE);
|
||||
return 0;
|
||||
} else {
|
||||
ss.clear();
|
||||
trans.set_response_status(xtlm::XTLM_OK_RESPONSE);
|
||||
unsigned char* data_ptr = trans.get_data_ptr();
|
||||
m_mem_handler->readDevMem(address, data_ptr, tranSize);
|
||||
return trans.get_data_length();
|
||||
}
|
||||
}
|
||||
|
||||
unsigned int axi_bram_memory_imp::transport_dbg_wr(
|
||||
xtlm::aximm_payload& trans) {
|
||||
std::stringstream ss;
|
||||
uint64_t max_address = m_mem_addr_width;
|
||||
uint64_t address = trans.get_address() % max_address;
|
||||
uint64_t tranSize = trans.get_data_length();
|
||||
//Check for the address range
|
||||
trans.set_response_status(xtlm::XTLM_OK_RESPONSE);
|
||||
if ((address + tranSize) > max_address) {
|
||||
ss.clear();
|
||||
std::string des;
|
||||
trans.get_log(des, 1);
|
||||
ss << name() << ": Invalid Debug Write Request " << std::endl << des
|
||||
<< std::endl;
|
||||
XSC_REPORT_ERROR((*m_report_handler), "1", ss.str().c_str());
|
||||
trans.set_response_status(xtlm::XTLM_ADDRESS_ERROR_RESPONSE);
|
||||
return 0;
|
||||
}
|
||||
xtlm::xtlm_extension<xsc::extension::P2P_XTLM_extension>* bExt;
|
||||
trans.get_extension(bExt);
|
||||
xsc::extension::P2P_XTLM_extension * ext =
|
||||
dynamic_cast<xsc::extension::P2P_XTLM_extension *>(bExt);
|
||||
if (ext != nullptr) {
|
||||
std::string filename;
|
||||
bool ret = true;
|
||||
if (ext->getType() == xsc::extension::TYPE::ALLOC_BO)
|
||||
ret = m_mem_handler->createMMappedBuffer(address,
|
||||
ext->getSize(), filename);
|
||||
else if (ext->getType() == xsc::extension::TYPE::FREE_BO)
|
||||
ret = m_mem_handler->freePage(address);
|
||||
else if (ext->getType() == xsc::extension::TYPE::IMPORT_BO) {
|
||||
ret = m_mem_handler->importBO(address,
|
||||
ext->getFileName(), ext->getSize());
|
||||
} else if (ext->getType() == xsc::extension::TYPE::COPY_BO) {
|
||||
ret = m_mem_handler->copyBO(address, ext->getFileName(),
|
||||
ext->getSize(), ext->getSrcOffset(), ext->getDstOffset());
|
||||
}
|
||||
ext->setResponse(ret);
|
||||
ext->setFileName(filename);
|
||||
return 0;
|
||||
}
|
||||
|
||||
else if (!trans.get_byte_enable_ptr()) {
|
||||
unsigned char* data_ptr = trans.get_data_ptr();
|
||||
if (m_report_handler->get_verbosity_level() == xsc::common_cpp::DEBUG) {
|
||||
ss.clear();
|
||||
std::string des;
|
||||
trans.get_log(des, 1);
|
||||
ss << name() << ": Received Debug Write Request " << std::endl
|
||||
<< des << std::endl;
|
||||
XSC_REPORT_INFO_VERB((*m_report_handler), "1", ss.str().c_str(),
|
||||
DEBUG);
|
||||
}
|
||||
m_mem_handler->writeDevMem(address, data_ptr, tranSize);
|
||||
return tranSize;
|
||||
} else {
|
||||
if (m_report_handler->get_verbosity_level() == xsc::common_cpp::DEBUG) {
|
||||
ss.clear();
|
||||
std::string des;
|
||||
trans.get_log(des, 1);
|
||||
ss << name() << ": Received Debug Write Request " << std::endl
|
||||
<< des << std::endl;
|
||||
XSC_REPORT_INFO_VERB((*m_report_handler), "1", ss.str().c_str(),
|
||||
DEBUG);
|
||||
}
|
||||
unsigned char* data_ptr = trans.get_data_ptr();
|
||||
unsigned char* byte_enable_ptr = trans.get_byte_enable_ptr();
|
||||
uint64_t byte_enable_len = trans.get_byte_enable_length();
|
||||
uint32_t index = 0;
|
||||
for (index = 1; index <= tranSize; index++) {
|
||||
bool byteEn = byte_enable_ptr[(index - 1) % byte_enable_len];
|
||||
if (byteEn) {
|
||||
m_mem_handler->writeDevMem(index + address - 1,
|
||||
data_ptr + (index - 1), 1);
|
||||
}
|
||||
}
|
||||
return tranSize;
|
||||
}
|
||||
}
|
||||
|
||||
+87
@@ -0,0 +1,87 @@
|
||||
// (c) Copyright 1995-2021, 2023 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
////////////////////////////////////////////////////////////
|
||||
|
||||
#ifndef _SIM_HBMX_IMP_H_
|
||||
#define _SIM_HBMX_IMP_H_
|
||||
|
||||
#include "xtlm.h"
|
||||
#include "report_handler.h"
|
||||
#include <list>
|
||||
#include "axi_bram_fmodel_base.h"
|
||||
#include "axi_bram_ram_fmodel.h"
|
||||
#include "axi_bram_fmodel_shared_memory.h"
|
||||
|
||||
class axi_bram_memory_imp: public sc_core::sc_module {
|
||||
public:
|
||||
//Workaround to implement Debug transport
|
||||
class target_rd_util;
|
||||
class target_wr_util;
|
||||
axi_bram_memory_imp(const sc_module_name& module_name,
|
||||
xsc::common_cpp::properties&);
|
||||
virtual ~axi_bram_memory_imp();SC_HAS_PROCESS(axi_bram_memory_imp);
|
||||
//Slave interface used to R/W to HBM Memory
|
||||
xtlm::xtlm_aximm_target_socket* target_0_rd_socket;
|
||||
xtlm::xtlm_aximm_target_socket* target_0_wr_socket;
|
||||
private:
|
||||
target_rd_util* m_target_0_rd_socket_util;
|
||||
target_wr_util* m_target_0_wr_socket_util;
|
||||
uint64_t m_mem_addr_width;
|
||||
uint64_t m_data_width;
|
||||
std::list<xtlm::aximm_payload*> m_rd_req_vec;
|
||||
std::list<xtlm::aximm_payload*> m_wr_req_vec;
|
||||
std::list<xtlm::aximm_payload*> m_wr_data_vec;
|
||||
std::list<xtlm::aximm_payload*> m_wr_resp_vec;
|
||||
void methodProcessTransactionRead();
|
||||
void methodProcessTransactionWrite();
|
||||
xsc::common_cpp::report_handler* m_report_handler;
|
||||
axi_bram_fmodel_base* m_mem_handler;
|
||||
unsigned int transport_dbg(xtlm::aximm_payload&);
|
||||
unsigned int transport_dbg_wr(xtlm::aximm_payload&);
|
||||
unsigned int transport_dbg_rd(xtlm::aximm_payload&);
|
||||
};
|
||||
|
||||
#endif /* _SIM_HBMX_IMP_H_ */
|
||||
|
||||
+308
@@ -0,0 +1,308 @@
|
||||
// (c) Copyright 1995-2021, 2023 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
////////////////////////////////////////////////////////////
|
||||
|
||||
#include "axi_bram_ram_fmodel.h"
|
||||
|
||||
#include <sys/stat.h>
|
||||
#include <sstream>
|
||||
|
||||
axi_bram_ram_fmodel::~axi_bram_ram_fmodel() {
|
||||
for (auto& mem : pageCache) {
|
||||
delete mem.second;
|
||||
}
|
||||
}
|
||||
|
||||
axi_bram_ram_fmodel::axi_bram_ram_fmodel(
|
||||
std::string p_module_name,
|
||||
xsc::common_cpp::report_handler* report_handler, uint64_t addr_size) :
|
||||
axi_bram_fmodel_base(p_module_name, report_handler, addr_size) {
|
||||
std::stringstream msg;
|
||||
msg << p_module_name << " : ";
|
||||
msg << " Initializing " << std::endl;
|
||||
|
||||
module_name = p_module_name;
|
||||
m_report_handler = report_handler;
|
||||
m_mem_addr_width = addr_size;
|
||||
report_handler->report("1", msg.str().c_str(), xsc::common_cpp::INFO,
|
||||
xsc::common_cpp::VERBOSITY::DEBUG);
|
||||
}
|
||||
|
||||
unsigned int axi_bram_ram_fmodel::writeDevMem(uint64_t offset, void* src,
|
||||
unsigned int size) {
|
||||
if (m_report_handler->get_verbosity_level() == xsc::common_cpp::DEBUG) {
|
||||
std::stringstream msg;
|
||||
msg << module_name << " : ";
|
||||
msg << " Writing Memory Address = " << offset << " Size = " << size
|
||||
<< " Data =" << std::endl;
|
||||
uint64_t counter = 0;
|
||||
for (int i = 0; i < size; i++) {
|
||||
msg << (unsigned int) (((unsigned char*) src)[i]) << " ";
|
||||
if (counter <= 16)
|
||||
counter++;
|
||||
else {
|
||||
counter = 0;
|
||||
msg << std::endl;
|
||||
}
|
||||
}
|
||||
msg << std::endl;
|
||||
m_report_handler->report("1", msg.str().c_str(), xsc::common_cpp::INFO,
|
||||
xsc::common_cpp::VERBOSITY::DEBUG);
|
||||
}
|
||||
uint64_t written_bytes = 0;
|
||||
uint64_t addr = offset;
|
||||
while (written_bytes < size) {
|
||||
uint64_t src_offset = written_bytes;
|
||||
std::string sFileName("");
|
||||
unsigned char* page_ptr = get_page(addr, sFileName);
|
||||
uint64_t page_addr = addr & ~(-1 << ADDRBITS);
|
||||
|
||||
unsigned char* dest_buf_ptr = page_ptr + page_addr;
|
||||
unsigned char* src_buf_ptr = (unsigned char*) (src) + src_offset;
|
||||
|
||||
uint64_t remaining_bytes_to_write = size - written_bytes;
|
||||
uint64_t unaligned_bytes_in_addr = (addr & ~(-1 << ADDRBITS));
|
||||
uint64_t bytes_upto_next_alignment = (0x1 << ADDRBITS)
|
||||
- unaligned_bytes_in_addr;
|
||||
|
||||
uint64_t buf_size = 0;
|
||||
if (bytes_upto_next_alignment > remaining_bytes_to_write) {
|
||||
buf_size = remaining_bytes_to_write;
|
||||
} else {
|
||||
buf_size = bytes_upto_next_alignment;
|
||||
}
|
||||
memcpy(dest_buf_ptr, src_buf_ptr, buf_size);
|
||||
written_bytes += buf_size;
|
||||
addr += buf_size;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
unsigned int axi_bram_ram_fmodel::readDevMem(uint64_t offset, void* dest,
|
||||
unsigned int size) {
|
||||
uint64_t read_bytes = 0;
|
||||
uint64_t addr = offset;
|
||||
|
||||
while (read_bytes < size) {
|
||||
uint64_t dest_offset = read_bytes;
|
||||
std::string sFileName("");
|
||||
unsigned char* page_ptr = get_page(addr, sFileName);
|
||||
uint64_t page_addr = addr & ~(-1 << ADDRBITS);
|
||||
|
||||
unsigned char* src_buf_ptr = page_ptr + page_addr;
|
||||
unsigned char* dest_buf_ptr = (unsigned char*) (dest) + dest_offset;
|
||||
|
||||
uint64_t remaining_bytes_to_read = size - read_bytes;
|
||||
uint64_t unaligned_bytes_in_addr = (addr & ~(-1 << ADDRBITS));
|
||||
uint64_t bytes_upto_next_alignment = (0x1 << ADDRBITS)
|
||||
- unaligned_bytes_in_addr;
|
||||
|
||||
uint64_t buf_size = 0;
|
||||
if (bytes_upto_next_alignment > remaining_bytes_to_read) {
|
||||
buf_size = remaining_bytes_to_read;
|
||||
} else {
|
||||
buf_size = bytes_upto_next_alignment;
|
||||
}
|
||||
memcpy(dest_buf_ptr, src_buf_ptr, buf_size);
|
||||
read_bytes += buf_size;
|
||||
addr += buf_size;
|
||||
}
|
||||
if (m_report_handler->get_verbosity_level() == xsc::common_cpp::DEBUG) {
|
||||
std::stringstream msg;
|
||||
msg << module_name << " : ";
|
||||
msg << " Reading Memory Address = " << offset << " Size = " << size
|
||||
<< " Data = " << std::endl;
|
||||
uint64_t counter = 0;
|
||||
for (int i = 0; i < size; i++) {
|
||||
msg << (unsigned int) (((unsigned char*) dest)[i]) << " ";
|
||||
if (counter <= 16)
|
||||
counter++;
|
||||
else {
|
||||
counter = 0;
|
||||
msg << std::endl;
|
||||
}
|
||||
}
|
||||
msg << std::endl;
|
||||
m_report_handler->report("1", msg.str().c_str(), xsc::common_cpp::INFO,
|
||||
xsc::common_cpp::VERBOSITY::DEBUG);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
unsigned char* axi_bram_ram_fmodel::get_page(uint64_t offset,
|
||||
std::string& p2pFileName, uint64_t size) {
|
||||
uint64_t page_idx = offset >> ADDRBITS;
|
||||
std::string file_name = get_mem_file_name(page_idx);
|
||||
if (pageCache.size() > N_1MBARRAYS) {
|
||||
std::cerr
|
||||
<< "Out of Memory. DDR model does not support this much of memory\n";
|
||||
exit(1);
|
||||
} else {
|
||||
FILE* pFile = NULL;
|
||||
if (pageCache.find(page_idx) != pageCache.end()) {
|
||||
return pageCache[page_idx];
|
||||
} else {
|
||||
|
||||
if (size != 0) {
|
||||
int fd = -1;
|
||||
p2pFileName = file_name + "_shared";
|
||||
if ((fd = open(p2pFileName.c_str(), O_CREAT | O_RDWR,
|
||||
S_IRWXU | S_IRGRP | S_IROTH)) == -1) {
|
||||
printf("Error opening file.\n");
|
||||
}
|
||||
void* pageStartOSAddressVoid = mmap(0, size,
|
||||
PROT_READ | PROT_WRITE | PROT_EXEC, MAP_SHARED, fd,
|
||||
0/*sysconf(_SC_PAGESIZE)*/);
|
||||
if (fd < 0) {
|
||||
munmap(pageStartOSAddressVoid, size);
|
||||
p2pFileName = "";
|
||||
}
|
||||
|
||||
if (ftruncate(fd, size) < 0) {
|
||||
close(fd);
|
||||
munmap(pageStartOSAddressVoid, size);
|
||||
p2pFileName = "";
|
||||
}
|
||||
if (!p2pFileName.empty()) {
|
||||
unsigned char* pagePtr =
|
||||
(unsigned char*) pageStartOSAddressVoid;
|
||||
while (size > 0) {
|
||||
pageCache[page_idx] = pagePtr;
|
||||
page_idx = page_idx + 1;
|
||||
pagePtr = pagePtr + PAGESIZE;
|
||||
if (size <= PAGESIZE)
|
||||
break;
|
||||
size = size - PAGESIZE;
|
||||
std::cout << "page_idx is " << page_idx << std::endl;
|
||||
std::cout << "size is " << size << std::endl;
|
||||
}
|
||||
return (unsigned char*) pageStartOSAddressVoid;
|
||||
}
|
||||
}
|
||||
|
||||
pageCache[page_idx] = new unsigned char[PAGESIZE];
|
||||
//for(int i = 0; i < ONE_MB;i++){
|
||||
// pageCache[page_idx][i] = 0x0;
|
||||
//}
|
||||
return pageCache[page_idx];
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void axi_bram_ram_fmodel::init_fmodel() {
|
||||
|
||||
}
|
||||
|
||||
bool axi_bram_ram_fmodel::createMMappedBuffer(uint64_t base_address,
|
||||
uint64_t size, std::string& buffer_filename) {
|
||||
return true;
|
||||
}
|
||||
|
||||
bool axi_bram_ram_fmodel::freePage(uint64_t base_address) {
|
||||
return true;
|
||||
}
|
||||
|
||||
bool axi_bram_ram_fmodel::copyBO(uint64_t offset,
|
||||
std::string dst_filename, uint64_t size, uint64_t src_offset,
|
||||
uint64_t dst_offset) {
|
||||
return true;
|
||||
|
||||
}
|
||||
|
||||
bool axi_bram_ram_fmodel::importBO(uint64_t offset,
|
||||
std::string dst_filename, uint64_t size) {
|
||||
return true;
|
||||
}
|
||||
|
||||
std::string axi_bram_ram_fmodel::get_mem_file_name(uint64_t pageIdx) //,enum fileType file_type)
|
||||
{
|
||||
std::string file_name;
|
||||
std::string socket_id;
|
||||
std::string pid;
|
||||
std::string deviceName("");
|
||||
std::string user("");
|
||||
if (getenv("EMULATION_SOCKETID")) {
|
||||
socket_id = getenv("EMULATION_SOCKETID");
|
||||
std::size_t foundLast = socket_id.find_last_of("_");
|
||||
std::size_t foundFirst = socket_id.find_first_of("_");
|
||||
if (foundLast != std::string::npos) {
|
||||
pid = socket_id.substr(foundLast + 1);
|
||||
}
|
||||
if (foundFirst != std::string::npos) {
|
||||
deviceName = socket_id.substr(0, foundFirst);
|
||||
}
|
||||
}
|
||||
|
||||
if (getenv("USER") != NULL) {
|
||||
user = getenv("USER");
|
||||
}
|
||||
std::string file_path("");
|
||||
std::string sEmRunDir("");
|
||||
|
||||
if (getenv("EMULATION_RUN_DIR")) {
|
||||
sEmRunDir = getenv("EMULATION_RUN_DIR");
|
||||
} else {
|
||||
sEmRunDir = "/tmp/" + user + "/hw_em/";
|
||||
}
|
||||
|
||||
file_path = sEmRunDir + "/" + module_name + "/";
|
||||
std::stringstream mkdirCommand;
|
||||
mkdirCommand << "mkdir -p " << file_path;
|
||||
;
|
||||
struct stat statBuf;
|
||||
if (stat(file_path.c_str(), &statBuf) == -1) {
|
||||
system(mkdirCommand.str().c_str());
|
||||
}
|
||||
file_name = file_path + module_name + "_" + std::to_string(pageIdx);
|
||||
if (m_report_handler->get_verbosity_level()
|
||||
== xsc::common_cpp::VERBOSITY::DEBUG) {
|
||||
std::stringstream m_ss;
|
||||
m_ss.str("");
|
||||
m_ss << "ddr fmodel file_name: " << file_name << std::endl;
|
||||
m_report_handler->report("1", m_ss.str().c_str(), xsc::common_cpp::INFO,
|
||||
xsc::common_cpp::VERBOSITY::DEBUG);
|
||||
}
|
||||
return file_name;
|
||||
}
|
||||
|
||||
+111
@@ -0,0 +1,111 @@
|
||||
// (c) Copyright 1995-2021, 2023 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
////////////////////////////////////////////////////////////
|
||||
|
||||
#ifndef OCL_PLATFORM_H
|
||||
#define OCL_PLATFORM_H
|
||||
#include <math.h>
|
||||
#include <iostream>
|
||||
#include "report_handler.h"
|
||||
#include "axi_bram_fmodel_base.h"
|
||||
|
||||
#include <string.h> // memcpy
|
||||
#include <stdlib.h> //realloc
|
||||
#include <stdint.h>
|
||||
#include <vector>
|
||||
#include <map> //realloc
|
||||
//Uncomment to print the latency calculation log
|
||||
//#define DEBUGMSG
|
||||
|
||||
#define ONE_KB (0x400)
|
||||
#define ONE_MB (ONE_KB * ONE_KB)
|
||||
#define PAGESIZE (ONE_MB)
|
||||
#define ADDRBITS (20)
|
||||
#define N_1MBARRAYS 4096
|
||||
|
||||
//Calculations for Strb
|
||||
//Its Array of 64bit integer
|
||||
#define STRB_SIZE 64
|
||||
#define ONE_KB_STRB (ONE_KB / STRB_SIZE)
|
||||
#define ONE_MB_STRB (ONE_KB_STRB * ONE_KB)
|
||||
|
||||
//using namespace std;
|
||||
|
||||
#define RBC 0
|
||||
#define BRC 1
|
||||
#define RCB 2
|
||||
|
||||
enum fileType {MEM,MEM_STRB};
|
||||
//Models fixed portion of the platform
|
||||
class axi_bram_ram_fmodel:public axi_bram_fmodel_base{
|
||||
public:
|
||||
unsigned int writeDevMem(uint64_t offset, void* src, unsigned int size);
|
||||
unsigned int readDevMem(uint64_t offset, void* dest, unsigned int size);
|
||||
unsigned char* get_page(uint64_t offset, std::string& p2pFileName, uint64_t size = 0);
|
||||
bool createMMappedBuffer(uint64_t base_address,uint64_t size,std::string& buffer_filename);
|
||||
bool freePage(uint64_t base_address);
|
||||
bool copyBO(uint64_t offset, std::string dst_filename, uint64_t size, uint64_t src_offset, uint64_t dst_offset);
|
||||
bool importBO(uint64_t offset, std::string dst_filename,uint64_t size);
|
||||
void reset_fmodel(){};
|
||||
std::string get_mem_file_name(uint64_t pageIdx);
|
||||
|
||||
protected:
|
||||
private:
|
||||
//unsigned char* get_page(uint64_t offset);
|
||||
//Paging
|
||||
std::map<uint64_t,unsigned char*> pageCache;
|
||||
std::map<uint64_t,unsigned char*>::iterator pageCacheItr;
|
||||
std::string module_name;
|
||||
xsc::common_cpp::report_handler* m_report_handler;
|
||||
uint64_t m_mem_addr_width;
|
||||
public:
|
||||
axi_bram_ram_fmodel(std::string p_module_name,xsc::common_cpp::report_handler* report_handler,uint64_t addr_size);
|
||||
~ axi_bram_ram_fmodel();
|
||||
void init_fmodel();
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
+3
-3
@@ -198,12 +198,12 @@ ARCHITECTURE system_top_axi_bram_ctrl_1_0_arch OF system_top_axi_bram_ctrl_1_0 I
|
||||
);
|
||||
END COMPONENT axi_bram_ctrl;
|
||||
ATTRIBUTE X_CORE_INFO : STRING;
|
||||
ATTRIBUTE X_CORE_INFO OF system_top_axi_bram_ctrl_1_0_arch: ARCHITECTURE IS "axi_bram_ctrl,Vivado 2024.1";
|
||||
ATTRIBUTE X_CORE_INFO OF system_top_axi_bram_ctrl_1_0_arch: ARCHITECTURE IS "axi_bram_ctrl,Vivado 2024.1.2";
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE OF system_top_axi_bram_ctrl_1_0_arch : ARCHITECTURE IS "system_top_axi_bram_ctrl_1_0,axi_bram_ctrl,{}";
|
||||
ATTRIBUTE CORE_GENERATION_INFO : STRING;
|
||||
ATTRIBUTE CORE_GENERATION_INFO OF system_top_axi_bram_ctrl_1_0_arch: ARCHITECTURE IS "system_top_axi_bram_ctrl_1_0,axi_bram_ctrl,{x_ipProduct=Vivado 2024.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_bram_ctrl,x_ipVersion=4.1,x_ipCoreRevision=10,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_BRAM_INST_MODE=EXTERNAL,C_MEMORY_DEPTH=8192,C_BRAM_ADDR_WIDTH=13,C_S_AXI_ADDR_WIDTH=15,C_S_AXI_DATA_WIDTH=32,C_S_AXI_ID_WIDTH=1,C_S_AXI_PROTOCOL=AXI4,C_S_AXI_SUPPORTS_NARROW_BURST=0,C_SINGLE_PORT_BRAM=1,C_FAMILY=zynq,C_READ_LATENCY=1,C_RD_CMD_OPTIMIZATION=0,C_S_AXI_CTRL_ADDR_WIDTH=32,C_S_" &
|
||||
"AXI_CTRL_DATA_WIDTH=32,C_ECC=0,C_ECC_TYPE=0,C_FAULT_INJECT=0,C_ECC_ONOFF_RESET_VALUE=0}";
|
||||
ATTRIBUTE CORE_GENERATION_INFO OF system_top_axi_bram_ctrl_1_0_arch: ARCHITECTURE IS "system_top_axi_bram_ctrl_1_0,axi_bram_ctrl,{x_ipProduct=Vivado 2024.1.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_bram_ctrl,x_ipVersion=4.1,x_ipCoreRevision=10,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_BRAM_INST_MODE=EXTERNAL,C_MEMORY_DEPTH=8192,C_BRAM_ADDR_WIDTH=13,C_S_AXI_ADDR_WIDTH=15,C_S_AXI_DATA_WIDTH=32,C_S_AXI_ID_WIDTH=1,C_S_AXI_PROTOCOL=AXI4,C_S_AXI_SUPPORTS_NARROW_BURST=0,C_SINGLE_PORT_BRAM=1,C_FAMILY=zynq,C_READ_LATENCY=1,C_RD_CMD_OPTIMIZATION=0,C_S_AXI_CTRL_ADDR_WIDTH=32,C_" &
|
||||
"S_AXI_CTRL_DATA_WIDTH=32,C_ECC=0,C_ECC_TYPE=0,C_FAULT_INJECT=0,C_ECC_ONOFF_RESET_VALUE=0}";
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bram_addr_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
|
||||
|
||||
+2
-2
@@ -64,7 +64,7 @@
|
||||
"OUTPUTDIR": [ { "value": "." } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2024.1" } ],
|
||||
"SWVERSION": [ { "value": "2024.1.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
@@ -195,7 +195,7 @@
|
||||
"MEM_ECC": [ { "value": "NONE", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_LATENCY": [ { "value": "1", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MEM_ADDRESS_MODE": [ { "value": "", "value_src": "weak", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
"MEM_ADDRESS_MODE": [ { "value": "", "value_src": "weak", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"ADDR": [ { "physical_name": "bram_addr_a" } ],
|
||||
|
||||
+258
-3
@@ -1990,6 +1990,25 @@ The register is automatically cleared after the fault has been injected.
|
||||
</spirit:memoryMaps>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:modelName>axi_bram_ctrl</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Nov 03 07:49:49 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:d7a14428</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_synthesisconstraints</spirit:name>
|
||||
<spirit:displayName>Synthesis Constraints</spirit:displayName>
|
||||
@@ -2001,6 +2020,78 @@ The register is automatically cleared after the fault has been injected.
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_systemcsimulation</spirit:name>
|
||||
<spirit:displayName>SystemC Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>systemCSource:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:language>systemc</spirit:language>
|
||||
<spirit:modelName>axi_bram_ctrl</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_systemcsimulation_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Nov 03 07:49:49 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:8ffc4f07</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>sim_type</spirit:name>
|
||||
<spirit:value>tlm</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>use_subcore_outputs</spirit:name>
|
||||
<spirit:value>false</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_systemcsimulationwrapper</spirit:name>
|
||||
<spirit:displayName>SystemC Simulation Wrapper</spirit:displayName>
|
||||
<spirit:envIdentifier>systemCSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
|
||||
<spirit:language>systemc</spirit:language>
|
||||
<spirit:modelName>system_top_axi_bram_ctrl_1_0</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_systemcsimulationwrapper_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Nov 03 07:49:49 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:8ffc4f07</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>sim_type</spirit:name>
|
||||
<spirit:value>tlm</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
|
||||
<spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
|
||||
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
|
||||
<spirit:language>vhdl</spirit:language>
|
||||
<spirit:modelName>system_top_axi_bram_ctrl_1_0</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Nov 03 07:49:49 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:d7a14428</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_vhdlsynthesis</spirit:name>
|
||||
<spirit:displayName>VHDL Synthesis</spirit:displayName>
|
||||
@@ -2013,7 +2104,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Oct 31 03:29:29 UTC 2024</spirit:value>
|
||||
<spirit:value>Sun Nov 03 07:49:49 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -2033,7 +2124,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Oct 31 03:29:29 UTC 2024</spirit:value>
|
||||
<spirit:value>Sun Nov 03 07:49:49 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -2051,6 +2142,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2063,6 +2155,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2075,6 +2168,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2097,6 +2191,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2123,6 +2218,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2149,6 +2245,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2168,6 +2265,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2194,6 +2292,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2220,6 +2319,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2242,6 +2342,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2268,6 +2369,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2294,6 +2396,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2309,6 +2412,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2324,6 +2428,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2340,6 +2445,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2359,6 +2465,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2374,6 +2481,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2396,6 +2504,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2411,6 +2520,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2427,6 +2537,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2450,6 +2561,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2462,6 +2574,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2474,6 +2587,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2493,6 +2607,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2519,6 +2634,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2538,6 +2654,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2564,6 +2681,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2590,6 +2708,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2612,6 +2731,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2638,6 +2758,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2664,6 +2785,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2679,6 +2801,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2694,6 +2817,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2710,6 +2834,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2733,6 +2858,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2749,6 +2875,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2761,6 +2888,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2783,6 +2911,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2795,6 +2924,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2810,6 +2940,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2832,6 +2963,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2855,6 +2987,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2881,6 +3014,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2903,6 +3037,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2925,6 +3060,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2948,6 +3084,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2967,6 +3104,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2986,6 +3124,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -3012,6 +3151,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -3034,6 +3174,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -3056,6 +3197,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3079,6 +3221,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3102,6 +3245,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3121,6 +3265,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3140,6 +3285,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -3162,6 +3308,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3181,6 +3328,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3200,6 +3348,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3223,6 +3372,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3246,6 +3396,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3269,6 +3420,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3292,6 +3444,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -3314,6 +3467,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3333,6 +3487,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3352,6 +3507,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3375,6 +3531,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3398,6 +3555,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3421,6 +3579,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3444,6 +3603,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -3722,6 +3882,101 @@ The register is automatically cleared after the fault has been injected.
|
||||
</spirit:choice>
|
||||
</spirit:choices>
|
||||
<spirit:fileSets>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>../../ipshared/14fa/hdl/axi_bram_ctrl_v4_1_rfs.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
|
||||
<spirit:logicalName>axi_bram_ctrl_v4_1_10</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_systemcsimulation_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>src/axi_bram_ctrl.h</spirit:name>
|
||||
<spirit:fileType>systemCSource</spirit:fileType>
|
||||
<spirit:isIncludeFile>true</spirit:isIncludeFile>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>src/axi_bram_ctrl.cpp</spirit:name>
|
||||
<spirit:fileType>systemCSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>src/axi_bram_ram_fmodel.cxx</spirit:name>
|
||||
<spirit:fileType>systemCSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>src/axi_bram_ram_fmodel.h</spirit:name>
|
||||
<spirit:fileType>systemCSource</spirit:fileType>
|
||||
<spirit:isIncludeFile>true</spirit:isIncludeFile>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>src/axi_bram_memory_imp.cpp</spirit:name>
|
||||
<spirit:fileType>systemCSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>src/axi_bram_memory_imp.h</spirit:name>
|
||||
<spirit:fileType>systemCSource</spirit:fileType>
|
||||
<spirit:isIncludeFile>true</spirit:isIncludeFile>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>src/axi_bram_fmodel_shared_memory.h</spirit:name>
|
||||
<spirit:fileType>systemCSource</spirit:fileType>
|
||||
<spirit:isIncludeFile>true</spirit:isIncludeFile>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>src/axi_bram_fmodel_shared_memory.cxx</spirit:name>
|
||||
<spirit:fileType>systemCSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>src/axi_bram_fmodel_base.cxx</spirit:name>
|
||||
<spirit:fileType>systemCSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>src/axi_bram_fmodel_base.h</spirit:name>
|
||||
<spirit:fileType>systemCSource</spirit:fileType>
|
||||
<spirit:isIncludeFile>true</spirit:isIncludeFile>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>src/P2P_XTLM_extension.h</spirit:name>
|
||||
<spirit:fileType>systemCSource</spirit:fileType>
|
||||
<spirit:isIncludeFile>true</spirit:isIncludeFile>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_systemcsimulationwrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>sim/system_top_axi_bram_ctrl_1_0_sc.h</spirit:name>
|
||||
<spirit:fileType>systemCSource</spirit:fileType>
|
||||
<spirit:isIncludeFile>true</spirit:isIncludeFile>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>sim/system_top_axi_bram_ctrl_1_0_sc.cpp</spirit:name>
|
||||
<spirit:fileType>systemCSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>sim/system_top_axi_bram_ctrl_1_0.h</spirit:name>
|
||||
<spirit:fileType>systemCSource</spirit:fileType>
|
||||
<spirit:isIncludeFile>true</spirit:isIncludeFile>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>sim/system_top_axi_bram_ctrl_1_0.cpp</spirit:name>
|
||||
<spirit:fileType>systemCSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>sim/system_top_axi_bram_ctrl_1_0_stub.sv</spirit:name>
|
||||
<spirit:fileType>systemVerilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>sim/system_top_axi_bram_ctrl_1_0.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlsynthesis_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
@@ -3908,7 +4163,7 @@ The register is automatically cleared after the fault has been injected.
|
||||
<xilinx:coreRevision>10</xilinx:coreRevision>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MASTER_TYPE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_ADDRESS_MODE" xilinx:valueSource="weak"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_ADDRESS_MODE" xilinx:valueSource="weak" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_ECC" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_SIZE" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
||||
|
||||
+424
@@ -0,0 +1,424 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:axi_dma:7.1
|
||||
-- IP Revision: 33
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY axi_dma_v7_1_33;
|
||||
USE axi_dma_v7_1_33.axi_dma;
|
||||
|
||||
ENTITY system_top_axi_dma_0_0 IS
|
||||
PORT (
|
||||
s_axi_lite_aclk : IN STD_LOGIC;
|
||||
m_axi_s2mm_aclk : IN STD_LOGIC;
|
||||
axi_resetn : IN STD_LOGIC;
|
||||
s_axi_lite_awvalid : IN STD_LOGIC;
|
||||
s_axi_lite_awready : OUT STD_LOGIC;
|
||||
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
s_axi_lite_wvalid : IN STD_LOGIC;
|
||||
s_axi_lite_wready : OUT STD_LOGIC;
|
||||
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_lite_bvalid : OUT STD_LOGIC;
|
||||
s_axi_lite_bready : IN STD_LOGIC;
|
||||
s_axi_lite_arvalid : IN STD_LOGIC;
|
||||
s_axi_lite_arready : OUT STD_LOGIC;
|
||||
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
s_axi_lite_rvalid : OUT STD_LOGIC;
|
||||
s_axi_lite_rready : IN STD_LOGIC;
|
||||
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(39 DOWNTO 0);
|
||||
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_s2mm_awvalid : OUT STD_LOGIC;
|
||||
m_axi_s2mm_awready : IN STD_LOGIC;
|
||||
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
|
||||
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_s2mm_wlast : OUT STD_LOGIC;
|
||||
m_axi_s2mm_wvalid : OUT STD_LOGIC;
|
||||
m_axi_s2mm_wready : IN STD_LOGIC;
|
||||
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_s2mm_bvalid : IN STD_LOGIC;
|
||||
m_axi_s2mm_bready : OUT STD_LOGIC;
|
||||
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
|
||||
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
|
||||
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
s_axis_s2mm_tvalid : IN STD_LOGIC;
|
||||
s_axis_s2mm_tready : OUT STD_LOGIC;
|
||||
s_axis_s2mm_tlast : IN STD_LOGIC;
|
||||
s2mm_introut : OUT STD_LOGIC;
|
||||
axi_dma_tstvec : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
END system_top_axi_dma_0_0;
|
||||
|
||||
ARCHITECTURE system_top_axi_dma_0_0_arch OF system_top_axi_dma_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_top_axi_dma_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axi_dma IS
|
||||
GENERIC (
|
||||
C_S_AXI_LITE_ADDR_WIDTH : INTEGER;
|
||||
C_S_AXI_LITE_DATA_WIDTH : INTEGER;
|
||||
C_DLYTMR_RESOLUTION : INTEGER;
|
||||
C_PRMRY_IS_ACLK_ASYNC : INTEGER;
|
||||
C_ENABLE_MULTI_CHANNEL : INTEGER;
|
||||
C_NUM_MM2S_CHANNELS : INTEGER;
|
||||
C_NUM_S2MM_CHANNELS : INTEGER;
|
||||
C_INCLUDE_SG : INTEGER;
|
||||
C_SG_INCLUDE_STSCNTRL_STRM : INTEGER;
|
||||
C_SG_USE_STSAPP_LENGTH : INTEGER;
|
||||
C_SG_LENGTH_WIDTH : INTEGER;
|
||||
C_M_AXI_SG_ADDR_WIDTH : INTEGER;
|
||||
C_M_AXI_SG_DATA_WIDTH : INTEGER;
|
||||
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : INTEGER;
|
||||
C_S_AXIS_S2MM_STS_TDATA_WIDTH : INTEGER;
|
||||
C_MICRO_DMA : INTEGER;
|
||||
C_INCLUDE_MM2S : INTEGER;
|
||||
C_INCLUDE_MM2S_SF : INTEGER;
|
||||
C_MM2S_BURST_SIZE : INTEGER;
|
||||
C_M_AXI_MM2S_ADDR_WIDTH : INTEGER;
|
||||
C_M_AXI_MM2S_DATA_WIDTH : INTEGER;
|
||||
C_M_AXIS_MM2S_TDATA_WIDTH : INTEGER;
|
||||
C_INCLUDE_MM2S_DRE : INTEGER;
|
||||
C_INCLUDE_S2MM : INTEGER;
|
||||
C_INCLUDE_S2MM_SF : INTEGER;
|
||||
C_S2MM_BURST_SIZE : INTEGER;
|
||||
C_M_AXI_S2MM_ADDR_WIDTH : INTEGER;
|
||||
C_M_AXI_S2MM_DATA_WIDTH : INTEGER;
|
||||
C_S_AXIS_S2MM_TDATA_WIDTH : INTEGER;
|
||||
C_INCLUDE_S2MM_DRE : INTEGER;
|
||||
C_INCREASE_THROUGHPUT : INTEGER;
|
||||
C_FAMILY : STRING
|
||||
);
|
||||
PORT (
|
||||
s_axi_lite_aclk : IN STD_LOGIC;
|
||||
m_axi_sg_aclk : IN STD_LOGIC;
|
||||
m_axi_mm2s_aclk : IN STD_LOGIC;
|
||||
m_axi_s2mm_aclk : IN STD_LOGIC;
|
||||
axi_resetn : IN STD_LOGIC;
|
||||
s_axi_lite_awvalid : IN STD_LOGIC;
|
||||
s_axi_lite_awready : OUT STD_LOGIC;
|
||||
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
s_axi_lite_wvalid : IN STD_LOGIC;
|
||||
s_axi_lite_wready : OUT STD_LOGIC;
|
||||
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_lite_bvalid : OUT STD_LOGIC;
|
||||
s_axi_lite_bready : IN STD_LOGIC;
|
||||
s_axi_lite_arvalid : IN STD_LOGIC;
|
||||
s_axi_lite_arready : OUT STD_LOGIC;
|
||||
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
s_axi_lite_rvalid : OUT STD_LOGIC;
|
||||
s_axi_lite_rready : IN STD_LOGIC;
|
||||
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_sg_awaddr : OUT STD_LOGIC_VECTOR(39 DOWNTO 0);
|
||||
m_axi_sg_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_sg_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_sg_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_sg_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_sg_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_sg_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_sg_awvalid : OUT STD_LOGIC;
|
||||
m_axi_sg_awready : IN STD_LOGIC;
|
||||
m_axi_sg_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_sg_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_sg_wlast : OUT STD_LOGIC;
|
||||
m_axi_sg_wvalid : OUT STD_LOGIC;
|
||||
m_axi_sg_wready : IN STD_LOGIC;
|
||||
m_axi_sg_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_sg_bvalid : IN STD_LOGIC;
|
||||
m_axi_sg_bready : OUT STD_LOGIC;
|
||||
m_axi_sg_araddr : OUT STD_LOGIC_VECTOR(39 DOWNTO 0);
|
||||
m_axi_sg_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_sg_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_sg_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_sg_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_sg_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_sg_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_sg_arvalid : OUT STD_LOGIC;
|
||||
m_axi_sg_arready : IN STD_LOGIC;
|
||||
m_axi_sg_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_sg_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_sg_rlast : IN STD_LOGIC;
|
||||
m_axi_sg_rvalid : IN STD_LOGIC;
|
||||
m_axi_sg_rready : OUT STD_LOGIC;
|
||||
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(39 DOWNTO 0);
|
||||
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_mm2s_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_mm2s_arvalid : OUT STD_LOGIC;
|
||||
m_axi_mm2s_arready : IN STD_LOGIC;
|
||||
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_mm2s_rlast : IN STD_LOGIC;
|
||||
m_axi_mm2s_rvalid : IN STD_LOGIC;
|
||||
m_axi_mm2s_rready : OUT STD_LOGIC;
|
||||
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
|
||||
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axis_mm2s_tvalid : OUT STD_LOGIC;
|
||||
m_axis_mm2s_tready : IN STD_LOGIC;
|
||||
m_axis_mm2s_tlast : OUT STD_LOGIC;
|
||||
m_axis_mm2s_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axis_mm2s_tid : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
|
||||
m_axis_mm2s_tdest : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
|
||||
mm2s_cntrl_reset_out_n : OUT STD_LOGIC;
|
||||
m_axis_mm2s_cntrl_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axis_mm2s_cntrl_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axis_mm2s_cntrl_tvalid : OUT STD_LOGIC;
|
||||
m_axis_mm2s_cntrl_tready : IN STD_LOGIC;
|
||||
m_axis_mm2s_cntrl_tlast : OUT STD_LOGIC;
|
||||
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(39 DOWNTO 0);
|
||||
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_s2mm_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_s2mm_awvalid : OUT STD_LOGIC;
|
||||
m_axi_s2mm_awready : IN STD_LOGIC;
|
||||
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
|
||||
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_s2mm_wlast : OUT STD_LOGIC;
|
||||
m_axi_s2mm_wvalid : OUT STD_LOGIC;
|
||||
m_axi_s2mm_wready : IN STD_LOGIC;
|
||||
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_s2mm_bvalid : IN STD_LOGIC;
|
||||
m_axi_s2mm_bready : OUT STD_LOGIC;
|
||||
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
|
||||
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
|
||||
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
s_axis_s2mm_tvalid : IN STD_LOGIC;
|
||||
s_axis_s2mm_tready : OUT STD_LOGIC;
|
||||
s_axis_s2mm_tlast : IN STD_LOGIC;
|
||||
s_axis_s2mm_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axis_s2mm_tid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
|
||||
s_axis_s2mm_tdest : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
|
||||
s2mm_sts_reset_out_n : OUT STD_LOGIC;
|
||||
s_axis_s2mm_sts_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axis_s2mm_sts_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axis_s2mm_sts_tvalid : IN STD_LOGIC;
|
||||
s_axis_s2mm_sts_tready : OUT STD_LOGIC;
|
||||
s_axis_s2mm_sts_tlast : IN STD_LOGIC;
|
||||
mm2s_introut : OUT STD_LOGIC;
|
||||
s2mm_introut : OUT STD_LOGIC;
|
||||
axi_dma_tstvec : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT axi_dma;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF axi_resetn: SIGNAL IS "XIL_INTERFACENAME AXI_RESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF axi_resetn: SIGNAL IS "xilinx.com:signal:reset:1.0 AXI_RESETN RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axi_s2mm_aclk: SIGNAL IS "XIL_INTERFACENAME M_AXI_S2MM_CLK, ASSOCIATED_BUSIF M_AXI_S2MM:S_AXIS_S2MM:S_AXIS_STS, ASSOCIATED_RESET s2mm_prmry_reset_out_n:s2mm_sts_reset_out_n, FREQ_HZ 200000000, FREQ_TOLERANCE_HZ 0, PHASE 0, CLK_DOMAIN system_top_mig_7series_0_0_ui_clk, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_S2MM_CLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axi_s2mm_awaddr: SIGNAL IS "XIL_INTERFACENAME M_AXI_S2MM, SUPPORTS_NARROW_BURST 0, NUM_WRITE_OUTSTANDING 16, DATA_WIDTH 64, PROTOCOL AXI4, FREQ_HZ 200000000, ID_WIDTH 0, ADDR_WIDTH 40, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, NUM_READ_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0, CLK_DOMAIN system_top_mig_7series_0_0_ui_clk, NUM_READ_THREADS 1, NUM_" &
|
||||
"WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWBURST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWCACHE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWLEN";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWPROT";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWSIZE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WSTRB";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s2mm_introut: SIGNAL IS "XIL_INTERFACENAME S2MM_INTROUT, SENSITIVITY LEVEL_HIGH, PortWidth 1";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s2mm_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 S2MM_INTROUT INTERRUPT";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s2mm_prmry_reset_out_n: SIGNAL IS "XIL_INTERFACENAME S2MM_PRMRY_RESET_OUT_N, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s2mm_prmry_reset_out_n: SIGNAL IS "xilinx.com:signal:reset:1.0 S2MM_PRMRY_RESET_OUT_N RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_lite_aclk: SIGNAL IS "XIL_INTERFACENAME S_AXI_LITE_ACLK, ASSOCIATED_BUSIF S_AXI_LITE:M_AXI, ASSOCIATED_RESET axi_resetn, FREQ_HZ 1e+08, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN system_top_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_LITE_ACLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_lite_awvalid: SIGNAL IS "XIL_INTERFACENAME S_AXI_LITE, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 10, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 0, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN system_top_processing_system7_0_0_FCLK_CLK0, NUM_READ_THR" &
|
||||
"EADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_s2mm_tdata: SIGNAL IS "XIL_INTERFACENAME S_AXIS_S2MM, TDATA_NUM_BYTES 8, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 1, HAS_TLAST 1, FREQ_HZ 200000000, PHASE 0, CLK_DOMAIN system_top_mig_7series_0_0_ui_clk, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TKEEP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TVALID";
|
||||
BEGIN
|
||||
U0 : axi_dma
|
||||
GENERIC MAP (
|
||||
C_S_AXI_LITE_ADDR_WIDTH => 10,
|
||||
C_S_AXI_LITE_DATA_WIDTH => 32,
|
||||
C_DLYTMR_RESOLUTION => 125,
|
||||
C_PRMRY_IS_ACLK_ASYNC => 1,
|
||||
C_ENABLE_MULTI_CHANNEL => 0,
|
||||
C_NUM_MM2S_CHANNELS => 1,
|
||||
C_NUM_S2MM_CHANNELS => 1,
|
||||
C_INCLUDE_SG => 0,
|
||||
C_SG_INCLUDE_STSCNTRL_STRM => 0,
|
||||
C_SG_USE_STSAPP_LENGTH => 0,
|
||||
C_SG_LENGTH_WIDTH => 26,
|
||||
C_M_AXI_SG_ADDR_WIDTH => 40,
|
||||
C_M_AXI_SG_DATA_WIDTH => 32,
|
||||
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => 32,
|
||||
C_S_AXIS_S2MM_STS_TDATA_WIDTH => 32,
|
||||
C_MICRO_DMA => 0,
|
||||
C_INCLUDE_MM2S => 0,
|
||||
C_INCLUDE_MM2S_SF => 1,
|
||||
C_MM2S_BURST_SIZE => 16,
|
||||
C_M_AXI_MM2S_ADDR_WIDTH => 40,
|
||||
C_M_AXI_MM2S_DATA_WIDTH => 32,
|
||||
C_M_AXIS_MM2S_TDATA_WIDTH => 32,
|
||||
C_INCLUDE_MM2S_DRE => 0,
|
||||
C_INCLUDE_S2MM => 1,
|
||||
C_INCLUDE_S2MM_SF => 1,
|
||||
C_S2MM_BURST_SIZE => 16,
|
||||
C_M_AXI_S2MM_ADDR_WIDTH => 40,
|
||||
C_M_AXI_S2MM_DATA_WIDTH => 64,
|
||||
C_S_AXIS_S2MM_TDATA_WIDTH => 64,
|
||||
C_INCLUDE_S2MM_DRE => 0,
|
||||
C_INCREASE_THROUGHPUT => 0,
|
||||
C_FAMILY => "zynq"
|
||||
)
|
||||
PORT MAP (
|
||||
s_axi_lite_aclk => s_axi_lite_aclk,
|
||||
m_axi_sg_aclk => '0',
|
||||
m_axi_mm2s_aclk => '0',
|
||||
m_axi_s2mm_aclk => m_axi_s2mm_aclk,
|
||||
axi_resetn => axi_resetn,
|
||||
s_axi_lite_awvalid => s_axi_lite_awvalid,
|
||||
s_axi_lite_awready => s_axi_lite_awready,
|
||||
s_axi_lite_awaddr => s_axi_lite_awaddr,
|
||||
s_axi_lite_wvalid => s_axi_lite_wvalid,
|
||||
s_axi_lite_wready => s_axi_lite_wready,
|
||||
s_axi_lite_wdata => s_axi_lite_wdata,
|
||||
s_axi_lite_bresp => s_axi_lite_bresp,
|
||||
s_axi_lite_bvalid => s_axi_lite_bvalid,
|
||||
s_axi_lite_bready => s_axi_lite_bready,
|
||||
s_axi_lite_arvalid => s_axi_lite_arvalid,
|
||||
s_axi_lite_arready => s_axi_lite_arready,
|
||||
s_axi_lite_araddr => s_axi_lite_araddr,
|
||||
s_axi_lite_rvalid => s_axi_lite_rvalid,
|
||||
s_axi_lite_rready => s_axi_lite_rready,
|
||||
s_axi_lite_rdata => s_axi_lite_rdata,
|
||||
s_axi_lite_rresp => s_axi_lite_rresp,
|
||||
m_axi_sg_awready => '0',
|
||||
m_axi_sg_wready => '0',
|
||||
m_axi_sg_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
|
||||
m_axi_sg_bvalid => '0',
|
||||
m_axi_sg_arready => '0',
|
||||
m_axi_sg_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
m_axi_sg_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
|
||||
m_axi_sg_rlast => '0',
|
||||
m_axi_sg_rvalid => '0',
|
||||
m_axi_mm2s_arready => '0',
|
||||
m_axi_mm2s_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
m_axi_mm2s_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
|
||||
m_axi_mm2s_rlast => '0',
|
||||
m_axi_mm2s_rvalid => '0',
|
||||
m_axis_mm2s_tready => '0',
|
||||
m_axis_mm2s_cntrl_tready => '0',
|
||||
m_axi_s2mm_awaddr => m_axi_s2mm_awaddr,
|
||||
m_axi_s2mm_awlen => m_axi_s2mm_awlen,
|
||||
m_axi_s2mm_awsize => m_axi_s2mm_awsize,
|
||||
m_axi_s2mm_awburst => m_axi_s2mm_awburst,
|
||||
m_axi_s2mm_awprot => m_axi_s2mm_awprot,
|
||||
m_axi_s2mm_awcache => m_axi_s2mm_awcache,
|
||||
m_axi_s2mm_awvalid => m_axi_s2mm_awvalid,
|
||||
m_axi_s2mm_awready => m_axi_s2mm_awready,
|
||||
m_axi_s2mm_wdata => m_axi_s2mm_wdata,
|
||||
m_axi_s2mm_wstrb => m_axi_s2mm_wstrb,
|
||||
m_axi_s2mm_wlast => m_axi_s2mm_wlast,
|
||||
m_axi_s2mm_wvalid => m_axi_s2mm_wvalid,
|
||||
m_axi_s2mm_wready => m_axi_s2mm_wready,
|
||||
m_axi_s2mm_bresp => m_axi_s2mm_bresp,
|
||||
m_axi_s2mm_bvalid => m_axi_s2mm_bvalid,
|
||||
m_axi_s2mm_bready => m_axi_s2mm_bready,
|
||||
s2mm_prmry_reset_out_n => s2mm_prmry_reset_out_n,
|
||||
s_axis_s2mm_tdata => s_axis_s2mm_tdata,
|
||||
s_axis_s2mm_tkeep => s_axis_s2mm_tkeep,
|
||||
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid,
|
||||
s_axis_s2mm_tready => s_axis_s2mm_tready,
|
||||
s_axis_s2mm_tlast => s_axis_s2mm_tlast,
|
||||
s_axis_s2mm_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
s_axis_s2mm_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
|
||||
s_axis_s2mm_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
|
||||
s_axis_s2mm_sts_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
s_axis_s2mm_sts_tkeep => X"F",
|
||||
s_axis_s2mm_sts_tvalid => '0',
|
||||
s_axis_s2mm_sts_tlast => '0',
|
||||
s2mm_introut => s2mm_introut,
|
||||
axi_dma_tstvec => axi_dma_tstvec
|
||||
);
|
||||
END system_top_axi_dma_0_0_arch;
|
||||
+6
-6
@@ -47,14 +47,14 @@
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:axi_dma:7.1
|
||||
-- IP Revision: 32
|
||||
-- IP Revision: 33
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY axi_dma_v7_1_32;
|
||||
USE axi_dma_v7_1_32.axi_dma;
|
||||
LIBRARY axi_dma_v7_1_33;
|
||||
USE axi_dma_v7_1_33.axi_dma;
|
||||
|
||||
ENTITY system_top_axi_dma_0_0 IS
|
||||
PORT (
|
||||
@@ -262,12 +262,12 @@ ARCHITECTURE system_top_axi_dma_0_0_arch OF system_top_axi_dma_0_0 IS
|
||||
);
|
||||
END COMPONENT axi_dma;
|
||||
ATTRIBUTE X_CORE_INFO : STRING;
|
||||
ATTRIBUTE X_CORE_INFO OF system_top_axi_dma_0_0_arch: ARCHITECTURE IS "axi_dma,Vivado 2024.1";
|
||||
ATTRIBUTE X_CORE_INFO OF system_top_axi_dma_0_0_arch: ARCHITECTURE IS "axi_dma,Vivado 2024.1.2";
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE OF system_top_axi_dma_0_0_arch : ARCHITECTURE IS "system_top_axi_dma_0_0,axi_dma,{}";
|
||||
ATTRIBUTE CORE_GENERATION_INFO : STRING;
|
||||
ATTRIBUTE CORE_GENERATION_INFO OF system_top_axi_dma_0_0_arch: ARCHITECTURE IS "system_top_axi_dma_0_0,axi_dma,{x_ipProduct=Vivado 2024.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_dma,x_ipVersion=7.1,x_ipCoreRevision=32,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_S_AXI_LITE_ADDR_WIDTH=10,C_S_AXI_LITE_DATA_WIDTH=32,C_DLYTMR_RESOLUTION=125,C_PRMRY_IS_ACLK_ASYNC=1,C_ENABLE_MULTI_CHANNEL=0,C_NUM_MM2S_CHANNELS=1,C_NUM_S2MM_CHANNELS=1,C_INCLUDE_SG=0,C_SG_INCLUDE_STSCNTRL_STRM=0,C_SG_USE_STSAPP_LENGTH=0,C_SG_LENGTH_WIDTH=26,C_M_AXI_SG_ADDR_WIDTH=40,C_M_AXI_SG_DATA_WIDTH=3" &
|
||||
"2,C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH=32,C_S_AXIS_S2MM_STS_TDATA_WIDTH=32,C_MICRO_DMA=0,C_INCLUDE_MM2S=0,C_INCLUDE_MM2S_SF=1,C_MM2S_BURST_SIZE=16,C_M_AXI_MM2S_ADDR_WIDTH=40,C_M_AXI_MM2S_DATA_WIDTH=32,C_M_AXIS_MM2S_TDATA_WIDTH=32,C_INCLUDE_MM2S_DRE=0,C_INCLUDE_S2MM=1,C_INCLUDE_S2MM_SF=1,C_S2MM_BURST_SIZE=16,C_M_AXI_S2MM_ADDR_WIDTH=40,C_M_AXI_S2MM_DATA_WIDTH=64,C_S_AXIS_S2MM_TDATA_WIDTH=64,C_INCLUDE_S2MM_DRE=0,C_INCREASE_THROUGHPUT=0,C_FAMILY=zynq}";
|
||||
ATTRIBUTE CORE_GENERATION_INFO OF system_top_axi_dma_0_0_arch: ARCHITECTURE IS "system_top_axi_dma_0_0,axi_dma,{x_ipProduct=Vivado 2024.1.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_dma,x_ipVersion=7.1,x_ipCoreRevision=33,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_S_AXI_LITE_ADDR_WIDTH=10,C_S_AXI_LITE_DATA_WIDTH=32,C_DLYTMR_RESOLUTION=125,C_PRMRY_IS_ACLK_ASYNC=1,C_ENABLE_MULTI_CHANNEL=0,C_NUM_MM2S_CHANNELS=1,C_NUM_S2MM_CHANNELS=1,C_INCLUDE_SG=0,C_SG_INCLUDE_STSCNTRL_STRM=0,C_SG_USE_STSAPP_LENGTH=0,C_SG_LENGTH_WIDTH=26,C_M_AXI_SG_ADDR_WIDTH=40,C_M_AXI_SG_DATA_WIDTH" &
|
||||
"=32,C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH=32,C_S_AXIS_S2MM_STS_TDATA_WIDTH=32,C_MICRO_DMA=0,C_INCLUDE_MM2S=0,C_INCLUDE_MM2S_SF=1,C_MM2S_BURST_SIZE=16,C_M_AXI_MM2S_ADDR_WIDTH=40,C_M_AXI_MM2S_DATA_WIDTH=32,C_M_AXIS_MM2S_TDATA_WIDTH=32,C_INCLUDE_MM2S_DRE=0,C_INCLUDE_S2MM=1,C_INCLUDE_S2MM_SF=1,C_S2MM_BURST_SIZE=16,C_M_AXI_S2MM_ADDR_WIDTH=40,C_M_AXI_S2MM_DATA_WIDTH=64,C_S_AXIS_S2MM_TDATA_WIDTH=64,C_INCLUDE_S2MM_DRE=0,C_INCREASE_THROUGHPUT=0,C_FAMILY=zynq}";
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF axi_resetn: SIGNAL IS "XIL_INTERFACENAME AXI_RESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
|
||||
+3
-3
@@ -4,7 +4,7 @@
|
||||
"xci_name": "system_top_axi_dma_0_0",
|
||||
"cell_name": "axi_dma_0",
|
||||
"component_reference": "xilinx.com:ip:axi_dma:7.1",
|
||||
"ip_revision": "32",
|
||||
"ip_revision": "33",
|
||||
"gen_directory": ".",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
@@ -85,12 +85,12 @@
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "32" } ],
|
||||
"IPREVISION": [ { "value": "33" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "." } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2024.1" } ],
|
||||
"SWVERSION": [ { "value": "2024.1.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
|
||||
+332
-13
File diff suppressed because it is too large
Load Diff
+424
@@ -0,0 +1,424 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:axi_dma:7.1
|
||||
-- IP Revision: 33
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY axi_dma_v7_1_33;
|
||||
USE axi_dma_v7_1_33.axi_dma;
|
||||
|
||||
ENTITY system_top_axi_dma_1_0 IS
|
||||
PORT (
|
||||
s_axi_lite_aclk : IN STD_LOGIC;
|
||||
m_axi_s2mm_aclk : IN STD_LOGIC;
|
||||
axi_resetn : IN STD_LOGIC;
|
||||
s_axi_lite_awvalid : IN STD_LOGIC;
|
||||
s_axi_lite_awready : OUT STD_LOGIC;
|
||||
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
s_axi_lite_wvalid : IN STD_LOGIC;
|
||||
s_axi_lite_wready : OUT STD_LOGIC;
|
||||
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_lite_bvalid : OUT STD_LOGIC;
|
||||
s_axi_lite_bready : IN STD_LOGIC;
|
||||
s_axi_lite_arvalid : IN STD_LOGIC;
|
||||
s_axi_lite_arready : OUT STD_LOGIC;
|
||||
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
s_axi_lite_rvalid : OUT STD_LOGIC;
|
||||
s_axi_lite_rready : IN STD_LOGIC;
|
||||
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(39 DOWNTO 0);
|
||||
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_s2mm_awvalid : OUT STD_LOGIC;
|
||||
m_axi_s2mm_awready : IN STD_LOGIC;
|
||||
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
|
||||
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_s2mm_wlast : OUT STD_LOGIC;
|
||||
m_axi_s2mm_wvalid : OUT STD_LOGIC;
|
||||
m_axi_s2mm_wready : IN STD_LOGIC;
|
||||
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_s2mm_bvalid : IN STD_LOGIC;
|
||||
m_axi_s2mm_bready : OUT STD_LOGIC;
|
||||
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
|
||||
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
|
||||
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
s_axis_s2mm_tvalid : IN STD_LOGIC;
|
||||
s_axis_s2mm_tready : OUT STD_LOGIC;
|
||||
s_axis_s2mm_tlast : IN STD_LOGIC;
|
||||
s2mm_introut : OUT STD_LOGIC;
|
||||
axi_dma_tstvec : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
END system_top_axi_dma_1_0;
|
||||
|
||||
ARCHITECTURE system_top_axi_dma_1_0_arch OF system_top_axi_dma_1_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_top_axi_dma_1_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axi_dma IS
|
||||
GENERIC (
|
||||
C_S_AXI_LITE_ADDR_WIDTH : INTEGER;
|
||||
C_S_AXI_LITE_DATA_WIDTH : INTEGER;
|
||||
C_DLYTMR_RESOLUTION : INTEGER;
|
||||
C_PRMRY_IS_ACLK_ASYNC : INTEGER;
|
||||
C_ENABLE_MULTI_CHANNEL : INTEGER;
|
||||
C_NUM_MM2S_CHANNELS : INTEGER;
|
||||
C_NUM_S2MM_CHANNELS : INTEGER;
|
||||
C_INCLUDE_SG : INTEGER;
|
||||
C_SG_INCLUDE_STSCNTRL_STRM : INTEGER;
|
||||
C_SG_USE_STSAPP_LENGTH : INTEGER;
|
||||
C_SG_LENGTH_WIDTH : INTEGER;
|
||||
C_M_AXI_SG_ADDR_WIDTH : INTEGER;
|
||||
C_M_AXI_SG_DATA_WIDTH : INTEGER;
|
||||
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : INTEGER;
|
||||
C_S_AXIS_S2MM_STS_TDATA_WIDTH : INTEGER;
|
||||
C_MICRO_DMA : INTEGER;
|
||||
C_INCLUDE_MM2S : INTEGER;
|
||||
C_INCLUDE_MM2S_SF : INTEGER;
|
||||
C_MM2S_BURST_SIZE : INTEGER;
|
||||
C_M_AXI_MM2S_ADDR_WIDTH : INTEGER;
|
||||
C_M_AXI_MM2S_DATA_WIDTH : INTEGER;
|
||||
C_M_AXIS_MM2S_TDATA_WIDTH : INTEGER;
|
||||
C_INCLUDE_MM2S_DRE : INTEGER;
|
||||
C_INCLUDE_S2MM : INTEGER;
|
||||
C_INCLUDE_S2MM_SF : INTEGER;
|
||||
C_S2MM_BURST_SIZE : INTEGER;
|
||||
C_M_AXI_S2MM_ADDR_WIDTH : INTEGER;
|
||||
C_M_AXI_S2MM_DATA_WIDTH : INTEGER;
|
||||
C_S_AXIS_S2MM_TDATA_WIDTH : INTEGER;
|
||||
C_INCLUDE_S2MM_DRE : INTEGER;
|
||||
C_INCREASE_THROUGHPUT : INTEGER;
|
||||
C_FAMILY : STRING
|
||||
);
|
||||
PORT (
|
||||
s_axi_lite_aclk : IN STD_LOGIC;
|
||||
m_axi_sg_aclk : IN STD_LOGIC;
|
||||
m_axi_mm2s_aclk : IN STD_LOGIC;
|
||||
m_axi_s2mm_aclk : IN STD_LOGIC;
|
||||
axi_resetn : IN STD_LOGIC;
|
||||
s_axi_lite_awvalid : IN STD_LOGIC;
|
||||
s_axi_lite_awready : OUT STD_LOGIC;
|
||||
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
s_axi_lite_wvalid : IN STD_LOGIC;
|
||||
s_axi_lite_wready : OUT STD_LOGIC;
|
||||
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_lite_bvalid : OUT STD_LOGIC;
|
||||
s_axi_lite_bready : IN STD_LOGIC;
|
||||
s_axi_lite_arvalid : IN STD_LOGIC;
|
||||
s_axi_lite_arready : OUT STD_LOGIC;
|
||||
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
s_axi_lite_rvalid : OUT STD_LOGIC;
|
||||
s_axi_lite_rready : IN STD_LOGIC;
|
||||
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_sg_awaddr : OUT STD_LOGIC_VECTOR(39 DOWNTO 0);
|
||||
m_axi_sg_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_sg_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_sg_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_sg_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_sg_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_sg_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_sg_awvalid : OUT STD_LOGIC;
|
||||
m_axi_sg_awready : IN STD_LOGIC;
|
||||
m_axi_sg_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_sg_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_sg_wlast : OUT STD_LOGIC;
|
||||
m_axi_sg_wvalid : OUT STD_LOGIC;
|
||||
m_axi_sg_wready : IN STD_LOGIC;
|
||||
m_axi_sg_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_sg_bvalid : IN STD_LOGIC;
|
||||
m_axi_sg_bready : OUT STD_LOGIC;
|
||||
m_axi_sg_araddr : OUT STD_LOGIC_VECTOR(39 DOWNTO 0);
|
||||
m_axi_sg_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_sg_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_sg_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_sg_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_sg_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_sg_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_sg_arvalid : OUT STD_LOGIC;
|
||||
m_axi_sg_arready : IN STD_LOGIC;
|
||||
m_axi_sg_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_sg_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_sg_rlast : IN STD_LOGIC;
|
||||
m_axi_sg_rvalid : IN STD_LOGIC;
|
||||
m_axi_sg_rready : OUT STD_LOGIC;
|
||||
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(39 DOWNTO 0);
|
||||
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_mm2s_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_mm2s_arvalid : OUT STD_LOGIC;
|
||||
m_axi_mm2s_arready : IN STD_LOGIC;
|
||||
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_mm2s_rlast : IN STD_LOGIC;
|
||||
m_axi_mm2s_rvalid : IN STD_LOGIC;
|
||||
m_axi_mm2s_rready : OUT STD_LOGIC;
|
||||
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
|
||||
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axis_mm2s_tvalid : OUT STD_LOGIC;
|
||||
m_axis_mm2s_tready : IN STD_LOGIC;
|
||||
m_axis_mm2s_tlast : OUT STD_LOGIC;
|
||||
m_axis_mm2s_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axis_mm2s_tid : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
|
||||
m_axis_mm2s_tdest : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
|
||||
mm2s_cntrl_reset_out_n : OUT STD_LOGIC;
|
||||
m_axis_mm2s_cntrl_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axis_mm2s_cntrl_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axis_mm2s_cntrl_tvalid : OUT STD_LOGIC;
|
||||
m_axis_mm2s_cntrl_tready : IN STD_LOGIC;
|
||||
m_axis_mm2s_cntrl_tlast : OUT STD_LOGIC;
|
||||
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(39 DOWNTO 0);
|
||||
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_s2mm_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_s2mm_awvalid : OUT STD_LOGIC;
|
||||
m_axi_s2mm_awready : IN STD_LOGIC;
|
||||
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
|
||||
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_s2mm_wlast : OUT STD_LOGIC;
|
||||
m_axi_s2mm_wvalid : OUT STD_LOGIC;
|
||||
m_axi_s2mm_wready : IN STD_LOGIC;
|
||||
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_s2mm_bvalid : IN STD_LOGIC;
|
||||
m_axi_s2mm_bready : OUT STD_LOGIC;
|
||||
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
|
||||
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
|
||||
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
s_axis_s2mm_tvalid : IN STD_LOGIC;
|
||||
s_axis_s2mm_tready : OUT STD_LOGIC;
|
||||
s_axis_s2mm_tlast : IN STD_LOGIC;
|
||||
s_axis_s2mm_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axis_s2mm_tid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
|
||||
s_axis_s2mm_tdest : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
|
||||
s2mm_sts_reset_out_n : OUT STD_LOGIC;
|
||||
s_axis_s2mm_sts_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axis_s2mm_sts_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axis_s2mm_sts_tvalid : IN STD_LOGIC;
|
||||
s_axis_s2mm_sts_tready : OUT STD_LOGIC;
|
||||
s_axis_s2mm_sts_tlast : IN STD_LOGIC;
|
||||
mm2s_introut : OUT STD_LOGIC;
|
||||
s2mm_introut : OUT STD_LOGIC;
|
||||
axi_dma_tstvec : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT axi_dma;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF axi_resetn: SIGNAL IS "XIL_INTERFACENAME AXI_RESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF axi_resetn: SIGNAL IS "xilinx.com:signal:reset:1.0 AXI_RESETN RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axi_s2mm_aclk: SIGNAL IS "XIL_INTERFACENAME M_AXI_S2MM_CLK, ASSOCIATED_BUSIF M_AXI_S2MM:S_AXIS_S2MM:S_AXIS_STS, ASSOCIATED_RESET s2mm_prmry_reset_out_n:s2mm_sts_reset_out_n, FREQ_HZ 200000000, FREQ_TOLERANCE_HZ 0, PHASE 0, CLK_DOMAIN system_top_mig_7series_0_0_ui_clk, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_S2MM_CLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axi_s2mm_awaddr: SIGNAL IS "XIL_INTERFACENAME M_AXI_S2MM, SUPPORTS_NARROW_BURST 0, NUM_WRITE_OUTSTANDING 16, DATA_WIDTH 64, PROTOCOL AXI4, FREQ_HZ 200000000, ID_WIDTH 0, ADDR_WIDTH 40, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, NUM_READ_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0, CLK_DOMAIN system_top_mig_7series_0_0_ui_clk, NUM_READ_THREADS 1, NUM_" &
|
||||
"WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWBURST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWCACHE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWLEN";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWPROT";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWSIZE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WSTRB";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s2mm_introut: SIGNAL IS "XIL_INTERFACENAME S2MM_INTROUT, SENSITIVITY LEVEL_HIGH, PortWidth 1";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s2mm_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 S2MM_INTROUT INTERRUPT";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s2mm_prmry_reset_out_n: SIGNAL IS "XIL_INTERFACENAME S2MM_PRMRY_RESET_OUT_N, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s2mm_prmry_reset_out_n: SIGNAL IS "xilinx.com:signal:reset:1.0 S2MM_PRMRY_RESET_OUT_N RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_lite_aclk: SIGNAL IS "XIL_INTERFACENAME S_AXI_LITE_ACLK, ASSOCIATED_BUSIF S_AXI_LITE:M_AXI, ASSOCIATED_RESET axi_resetn, FREQ_HZ 1e+08, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN system_top_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_LITE_ACLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_lite_awvalid: SIGNAL IS "XIL_INTERFACENAME S_AXI_LITE, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 10, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 0, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN system_top_processing_system7_0_0_FCLK_CLK0, NUM_READ_THR" &
|
||||
"EADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_s2mm_tdata: SIGNAL IS "XIL_INTERFACENAME S_AXIS_S2MM, TDATA_NUM_BYTES 8, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 1, HAS_TLAST 1, FREQ_HZ 200000000, PHASE 0, CLK_DOMAIN system_top_mig_7series_0_0_ui_clk, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TKEEP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TVALID";
|
||||
BEGIN
|
||||
U0 : axi_dma
|
||||
GENERIC MAP (
|
||||
C_S_AXI_LITE_ADDR_WIDTH => 10,
|
||||
C_S_AXI_LITE_DATA_WIDTH => 32,
|
||||
C_DLYTMR_RESOLUTION => 125,
|
||||
C_PRMRY_IS_ACLK_ASYNC => 1,
|
||||
C_ENABLE_MULTI_CHANNEL => 0,
|
||||
C_NUM_MM2S_CHANNELS => 1,
|
||||
C_NUM_S2MM_CHANNELS => 1,
|
||||
C_INCLUDE_SG => 0,
|
||||
C_SG_INCLUDE_STSCNTRL_STRM => 0,
|
||||
C_SG_USE_STSAPP_LENGTH => 0,
|
||||
C_SG_LENGTH_WIDTH => 26,
|
||||
C_M_AXI_SG_ADDR_WIDTH => 40,
|
||||
C_M_AXI_SG_DATA_WIDTH => 32,
|
||||
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => 32,
|
||||
C_S_AXIS_S2MM_STS_TDATA_WIDTH => 32,
|
||||
C_MICRO_DMA => 0,
|
||||
C_INCLUDE_MM2S => 0,
|
||||
C_INCLUDE_MM2S_SF => 1,
|
||||
C_MM2S_BURST_SIZE => 16,
|
||||
C_M_AXI_MM2S_ADDR_WIDTH => 40,
|
||||
C_M_AXI_MM2S_DATA_WIDTH => 32,
|
||||
C_M_AXIS_MM2S_TDATA_WIDTH => 32,
|
||||
C_INCLUDE_MM2S_DRE => 0,
|
||||
C_INCLUDE_S2MM => 1,
|
||||
C_INCLUDE_S2MM_SF => 1,
|
||||
C_S2MM_BURST_SIZE => 16,
|
||||
C_M_AXI_S2MM_ADDR_WIDTH => 40,
|
||||
C_M_AXI_S2MM_DATA_WIDTH => 64,
|
||||
C_S_AXIS_S2MM_TDATA_WIDTH => 64,
|
||||
C_INCLUDE_S2MM_DRE => 0,
|
||||
C_INCREASE_THROUGHPUT => 0,
|
||||
C_FAMILY => "zynq"
|
||||
)
|
||||
PORT MAP (
|
||||
s_axi_lite_aclk => s_axi_lite_aclk,
|
||||
m_axi_sg_aclk => '0',
|
||||
m_axi_mm2s_aclk => '0',
|
||||
m_axi_s2mm_aclk => m_axi_s2mm_aclk,
|
||||
axi_resetn => axi_resetn,
|
||||
s_axi_lite_awvalid => s_axi_lite_awvalid,
|
||||
s_axi_lite_awready => s_axi_lite_awready,
|
||||
s_axi_lite_awaddr => s_axi_lite_awaddr,
|
||||
s_axi_lite_wvalid => s_axi_lite_wvalid,
|
||||
s_axi_lite_wready => s_axi_lite_wready,
|
||||
s_axi_lite_wdata => s_axi_lite_wdata,
|
||||
s_axi_lite_bresp => s_axi_lite_bresp,
|
||||
s_axi_lite_bvalid => s_axi_lite_bvalid,
|
||||
s_axi_lite_bready => s_axi_lite_bready,
|
||||
s_axi_lite_arvalid => s_axi_lite_arvalid,
|
||||
s_axi_lite_arready => s_axi_lite_arready,
|
||||
s_axi_lite_araddr => s_axi_lite_araddr,
|
||||
s_axi_lite_rvalid => s_axi_lite_rvalid,
|
||||
s_axi_lite_rready => s_axi_lite_rready,
|
||||
s_axi_lite_rdata => s_axi_lite_rdata,
|
||||
s_axi_lite_rresp => s_axi_lite_rresp,
|
||||
m_axi_sg_awready => '0',
|
||||
m_axi_sg_wready => '0',
|
||||
m_axi_sg_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
|
||||
m_axi_sg_bvalid => '0',
|
||||
m_axi_sg_arready => '0',
|
||||
m_axi_sg_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
m_axi_sg_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
|
||||
m_axi_sg_rlast => '0',
|
||||
m_axi_sg_rvalid => '0',
|
||||
m_axi_mm2s_arready => '0',
|
||||
m_axi_mm2s_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
m_axi_mm2s_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
|
||||
m_axi_mm2s_rlast => '0',
|
||||
m_axi_mm2s_rvalid => '0',
|
||||
m_axis_mm2s_tready => '0',
|
||||
m_axis_mm2s_cntrl_tready => '0',
|
||||
m_axi_s2mm_awaddr => m_axi_s2mm_awaddr,
|
||||
m_axi_s2mm_awlen => m_axi_s2mm_awlen,
|
||||
m_axi_s2mm_awsize => m_axi_s2mm_awsize,
|
||||
m_axi_s2mm_awburst => m_axi_s2mm_awburst,
|
||||
m_axi_s2mm_awprot => m_axi_s2mm_awprot,
|
||||
m_axi_s2mm_awcache => m_axi_s2mm_awcache,
|
||||
m_axi_s2mm_awvalid => m_axi_s2mm_awvalid,
|
||||
m_axi_s2mm_awready => m_axi_s2mm_awready,
|
||||
m_axi_s2mm_wdata => m_axi_s2mm_wdata,
|
||||
m_axi_s2mm_wstrb => m_axi_s2mm_wstrb,
|
||||
m_axi_s2mm_wlast => m_axi_s2mm_wlast,
|
||||
m_axi_s2mm_wvalid => m_axi_s2mm_wvalid,
|
||||
m_axi_s2mm_wready => m_axi_s2mm_wready,
|
||||
m_axi_s2mm_bresp => m_axi_s2mm_bresp,
|
||||
m_axi_s2mm_bvalid => m_axi_s2mm_bvalid,
|
||||
m_axi_s2mm_bready => m_axi_s2mm_bready,
|
||||
s2mm_prmry_reset_out_n => s2mm_prmry_reset_out_n,
|
||||
s_axis_s2mm_tdata => s_axis_s2mm_tdata,
|
||||
s_axis_s2mm_tkeep => s_axis_s2mm_tkeep,
|
||||
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid,
|
||||
s_axis_s2mm_tready => s_axis_s2mm_tready,
|
||||
s_axis_s2mm_tlast => s_axis_s2mm_tlast,
|
||||
s_axis_s2mm_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
s_axis_s2mm_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
|
||||
s_axis_s2mm_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
|
||||
s_axis_s2mm_sts_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
s_axis_s2mm_sts_tkeep => X"F",
|
||||
s_axis_s2mm_sts_tvalid => '0',
|
||||
s_axis_s2mm_sts_tlast => '0',
|
||||
s2mm_introut => s2mm_introut,
|
||||
axi_dma_tstvec => axi_dma_tstvec
|
||||
);
|
||||
END system_top_axi_dma_1_0_arch;
|
||||
+6
-6
@@ -47,14 +47,14 @@
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:axi_dma:7.1
|
||||
-- IP Revision: 32
|
||||
-- IP Revision: 33
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY axi_dma_v7_1_32;
|
||||
USE axi_dma_v7_1_32.axi_dma;
|
||||
LIBRARY axi_dma_v7_1_33;
|
||||
USE axi_dma_v7_1_33.axi_dma;
|
||||
|
||||
ENTITY system_top_axi_dma_1_0 IS
|
||||
PORT (
|
||||
@@ -262,12 +262,12 @@ ARCHITECTURE system_top_axi_dma_1_0_arch OF system_top_axi_dma_1_0 IS
|
||||
);
|
||||
END COMPONENT axi_dma;
|
||||
ATTRIBUTE X_CORE_INFO : STRING;
|
||||
ATTRIBUTE X_CORE_INFO OF system_top_axi_dma_1_0_arch: ARCHITECTURE IS "axi_dma,Vivado 2024.1";
|
||||
ATTRIBUTE X_CORE_INFO OF system_top_axi_dma_1_0_arch: ARCHITECTURE IS "axi_dma,Vivado 2024.1.2";
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE OF system_top_axi_dma_1_0_arch : ARCHITECTURE IS "system_top_axi_dma_1_0,axi_dma,{}";
|
||||
ATTRIBUTE CORE_GENERATION_INFO : STRING;
|
||||
ATTRIBUTE CORE_GENERATION_INFO OF system_top_axi_dma_1_0_arch: ARCHITECTURE IS "system_top_axi_dma_1_0,axi_dma,{x_ipProduct=Vivado 2024.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_dma,x_ipVersion=7.1,x_ipCoreRevision=32,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_S_AXI_LITE_ADDR_WIDTH=10,C_S_AXI_LITE_DATA_WIDTH=32,C_DLYTMR_RESOLUTION=125,C_PRMRY_IS_ACLK_ASYNC=1,C_ENABLE_MULTI_CHANNEL=0,C_NUM_MM2S_CHANNELS=1,C_NUM_S2MM_CHANNELS=1,C_INCLUDE_SG=0,C_SG_INCLUDE_STSCNTRL_STRM=0,C_SG_USE_STSAPP_LENGTH=0,C_SG_LENGTH_WIDTH=26,C_M_AXI_SG_ADDR_WIDTH=40,C_M_AXI_SG_DATA_WIDTH=3" &
|
||||
"2,C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH=32,C_S_AXIS_S2MM_STS_TDATA_WIDTH=32,C_MICRO_DMA=0,C_INCLUDE_MM2S=0,C_INCLUDE_MM2S_SF=1,C_MM2S_BURST_SIZE=16,C_M_AXI_MM2S_ADDR_WIDTH=40,C_M_AXI_MM2S_DATA_WIDTH=32,C_M_AXIS_MM2S_TDATA_WIDTH=32,C_INCLUDE_MM2S_DRE=0,C_INCLUDE_S2MM=1,C_INCLUDE_S2MM_SF=1,C_S2MM_BURST_SIZE=16,C_M_AXI_S2MM_ADDR_WIDTH=40,C_M_AXI_S2MM_DATA_WIDTH=64,C_S_AXIS_S2MM_TDATA_WIDTH=64,C_INCLUDE_S2MM_DRE=0,C_INCREASE_THROUGHPUT=0,C_FAMILY=zynq}";
|
||||
ATTRIBUTE CORE_GENERATION_INFO OF system_top_axi_dma_1_0_arch: ARCHITECTURE IS "system_top_axi_dma_1_0,axi_dma,{x_ipProduct=Vivado 2024.1.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_dma,x_ipVersion=7.1,x_ipCoreRevision=33,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_S_AXI_LITE_ADDR_WIDTH=10,C_S_AXI_LITE_DATA_WIDTH=32,C_DLYTMR_RESOLUTION=125,C_PRMRY_IS_ACLK_ASYNC=1,C_ENABLE_MULTI_CHANNEL=0,C_NUM_MM2S_CHANNELS=1,C_NUM_S2MM_CHANNELS=1,C_INCLUDE_SG=0,C_SG_INCLUDE_STSCNTRL_STRM=0,C_SG_USE_STSAPP_LENGTH=0,C_SG_LENGTH_WIDTH=26,C_M_AXI_SG_ADDR_WIDTH=40,C_M_AXI_SG_DATA_WIDTH" &
|
||||
"=32,C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH=32,C_S_AXIS_S2MM_STS_TDATA_WIDTH=32,C_MICRO_DMA=0,C_INCLUDE_MM2S=0,C_INCLUDE_MM2S_SF=1,C_MM2S_BURST_SIZE=16,C_M_AXI_MM2S_ADDR_WIDTH=40,C_M_AXI_MM2S_DATA_WIDTH=32,C_M_AXIS_MM2S_TDATA_WIDTH=32,C_INCLUDE_MM2S_DRE=0,C_INCLUDE_S2MM=1,C_INCLUDE_S2MM_SF=1,C_S2MM_BURST_SIZE=16,C_M_AXI_S2MM_ADDR_WIDTH=40,C_M_AXI_S2MM_DATA_WIDTH=64,C_S_AXIS_S2MM_TDATA_WIDTH=64,C_INCLUDE_S2MM_DRE=0,C_INCREASE_THROUGHPUT=0,C_FAMILY=zynq}";
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF axi_resetn: SIGNAL IS "XIL_INTERFACENAME AXI_RESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
|
||||
+3
-3
@@ -4,7 +4,7 @@
|
||||
"xci_name": "system_top_axi_dma_1_0",
|
||||
"cell_name": "axi_dma_1",
|
||||
"component_reference": "xilinx.com:ip:axi_dma:7.1",
|
||||
"ip_revision": "32",
|
||||
"ip_revision": "33",
|
||||
"gen_directory": ".",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
@@ -85,12 +85,12 @@
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "32" } ],
|
||||
"IPREVISION": [ { "value": "33" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "." } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2024.1" } ],
|
||||
"SWVERSION": [ { "value": "2024.1.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
|
||||
+332
-13
File diff suppressed because it is too large
Load Diff
+424
@@ -0,0 +1,424 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:axi_dma:7.1
|
||||
-- IP Revision: 33
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY axi_dma_v7_1_33;
|
||||
USE axi_dma_v7_1_33.axi_dma;
|
||||
|
||||
ENTITY system_top_axi_dma_2_0 IS
|
||||
PORT (
|
||||
s_axi_lite_aclk : IN STD_LOGIC;
|
||||
m_axi_s2mm_aclk : IN STD_LOGIC;
|
||||
axi_resetn : IN STD_LOGIC;
|
||||
s_axi_lite_awvalid : IN STD_LOGIC;
|
||||
s_axi_lite_awready : OUT STD_LOGIC;
|
||||
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
s_axi_lite_wvalid : IN STD_LOGIC;
|
||||
s_axi_lite_wready : OUT STD_LOGIC;
|
||||
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_lite_bvalid : OUT STD_LOGIC;
|
||||
s_axi_lite_bready : IN STD_LOGIC;
|
||||
s_axi_lite_arvalid : IN STD_LOGIC;
|
||||
s_axi_lite_arready : OUT STD_LOGIC;
|
||||
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
s_axi_lite_rvalid : OUT STD_LOGIC;
|
||||
s_axi_lite_rready : IN STD_LOGIC;
|
||||
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(39 DOWNTO 0);
|
||||
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_s2mm_awvalid : OUT STD_LOGIC;
|
||||
m_axi_s2mm_awready : IN STD_LOGIC;
|
||||
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
|
||||
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_s2mm_wlast : OUT STD_LOGIC;
|
||||
m_axi_s2mm_wvalid : OUT STD_LOGIC;
|
||||
m_axi_s2mm_wready : IN STD_LOGIC;
|
||||
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_s2mm_bvalid : IN STD_LOGIC;
|
||||
m_axi_s2mm_bready : OUT STD_LOGIC;
|
||||
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
|
||||
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
|
||||
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
s_axis_s2mm_tvalid : IN STD_LOGIC;
|
||||
s_axis_s2mm_tready : OUT STD_LOGIC;
|
||||
s_axis_s2mm_tlast : IN STD_LOGIC;
|
||||
s2mm_introut : OUT STD_LOGIC;
|
||||
axi_dma_tstvec : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
END system_top_axi_dma_2_0;
|
||||
|
||||
ARCHITECTURE system_top_axi_dma_2_0_arch OF system_top_axi_dma_2_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_top_axi_dma_2_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axi_dma IS
|
||||
GENERIC (
|
||||
C_S_AXI_LITE_ADDR_WIDTH : INTEGER;
|
||||
C_S_AXI_LITE_DATA_WIDTH : INTEGER;
|
||||
C_DLYTMR_RESOLUTION : INTEGER;
|
||||
C_PRMRY_IS_ACLK_ASYNC : INTEGER;
|
||||
C_ENABLE_MULTI_CHANNEL : INTEGER;
|
||||
C_NUM_MM2S_CHANNELS : INTEGER;
|
||||
C_NUM_S2MM_CHANNELS : INTEGER;
|
||||
C_INCLUDE_SG : INTEGER;
|
||||
C_SG_INCLUDE_STSCNTRL_STRM : INTEGER;
|
||||
C_SG_USE_STSAPP_LENGTH : INTEGER;
|
||||
C_SG_LENGTH_WIDTH : INTEGER;
|
||||
C_M_AXI_SG_ADDR_WIDTH : INTEGER;
|
||||
C_M_AXI_SG_DATA_WIDTH : INTEGER;
|
||||
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : INTEGER;
|
||||
C_S_AXIS_S2MM_STS_TDATA_WIDTH : INTEGER;
|
||||
C_MICRO_DMA : INTEGER;
|
||||
C_INCLUDE_MM2S : INTEGER;
|
||||
C_INCLUDE_MM2S_SF : INTEGER;
|
||||
C_MM2S_BURST_SIZE : INTEGER;
|
||||
C_M_AXI_MM2S_ADDR_WIDTH : INTEGER;
|
||||
C_M_AXI_MM2S_DATA_WIDTH : INTEGER;
|
||||
C_M_AXIS_MM2S_TDATA_WIDTH : INTEGER;
|
||||
C_INCLUDE_MM2S_DRE : INTEGER;
|
||||
C_INCLUDE_S2MM : INTEGER;
|
||||
C_INCLUDE_S2MM_SF : INTEGER;
|
||||
C_S2MM_BURST_SIZE : INTEGER;
|
||||
C_M_AXI_S2MM_ADDR_WIDTH : INTEGER;
|
||||
C_M_AXI_S2MM_DATA_WIDTH : INTEGER;
|
||||
C_S_AXIS_S2MM_TDATA_WIDTH : INTEGER;
|
||||
C_INCLUDE_S2MM_DRE : INTEGER;
|
||||
C_INCREASE_THROUGHPUT : INTEGER;
|
||||
C_FAMILY : STRING
|
||||
);
|
||||
PORT (
|
||||
s_axi_lite_aclk : IN STD_LOGIC;
|
||||
m_axi_sg_aclk : IN STD_LOGIC;
|
||||
m_axi_mm2s_aclk : IN STD_LOGIC;
|
||||
m_axi_s2mm_aclk : IN STD_LOGIC;
|
||||
axi_resetn : IN STD_LOGIC;
|
||||
s_axi_lite_awvalid : IN STD_LOGIC;
|
||||
s_axi_lite_awready : OUT STD_LOGIC;
|
||||
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
s_axi_lite_wvalid : IN STD_LOGIC;
|
||||
s_axi_lite_wready : OUT STD_LOGIC;
|
||||
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_lite_bvalid : OUT STD_LOGIC;
|
||||
s_axi_lite_bready : IN STD_LOGIC;
|
||||
s_axi_lite_arvalid : IN STD_LOGIC;
|
||||
s_axi_lite_arready : OUT STD_LOGIC;
|
||||
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
s_axi_lite_rvalid : OUT STD_LOGIC;
|
||||
s_axi_lite_rready : IN STD_LOGIC;
|
||||
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_sg_awaddr : OUT STD_LOGIC_VECTOR(39 DOWNTO 0);
|
||||
m_axi_sg_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_sg_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_sg_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_sg_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_sg_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_sg_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_sg_awvalid : OUT STD_LOGIC;
|
||||
m_axi_sg_awready : IN STD_LOGIC;
|
||||
m_axi_sg_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_sg_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_sg_wlast : OUT STD_LOGIC;
|
||||
m_axi_sg_wvalid : OUT STD_LOGIC;
|
||||
m_axi_sg_wready : IN STD_LOGIC;
|
||||
m_axi_sg_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_sg_bvalid : IN STD_LOGIC;
|
||||
m_axi_sg_bready : OUT STD_LOGIC;
|
||||
m_axi_sg_araddr : OUT STD_LOGIC_VECTOR(39 DOWNTO 0);
|
||||
m_axi_sg_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_sg_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_sg_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_sg_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_sg_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_sg_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_sg_arvalid : OUT STD_LOGIC;
|
||||
m_axi_sg_arready : IN STD_LOGIC;
|
||||
m_axi_sg_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_sg_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_sg_rlast : IN STD_LOGIC;
|
||||
m_axi_sg_rvalid : IN STD_LOGIC;
|
||||
m_axi_sg_rready : OUT STD_LOGIC;
|
||||
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(39 DOWNTO 0);
|
||||
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_mm2s_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_mm2s_arvalid : OUT STD_LOGIC;
|
||||
m_axi_mm2s_arready : IN STD_LOGIC;
|
||||
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_mm2s_rlast : IN STD_LOGIC;
|
||||
m_axi_mm2s_rvalid : IN STD_LOGIC;
|
||||
m_axi_mm2s_rready : OUT STD_LOGIC;
|
||||
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
|
||||
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axis_mm2s_tvalid : OUT STD_LOGIC;
|
||||
m_axis_mm2s_tready : IN STD_LOGIC;
|
||||
m_axis_mm2s_tlast : OUT STD_LOGIC;
|
||||
m_axis_mm2s_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axis_mm2s_tid : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
|
||||
m_axis_mm2s_tdest : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
|
||||
mm2s_cntrl_reset_out_n : OUT STD_LOGIC;
|
||||
m_axis_mm2s_cntrl_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axis_mm2s_cntrl_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axis_mm2s_cntrl_tvalid : OUT STD_LOGIC;
|
||||
m_axis_mm2s_cntrl_tready : IN STD_LOGIC;
|
||||
m_axis_mm2s_cntrl_tlast : OUT STD_LOGIC;
|
||||
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(39 DOWNTO 0);
|
||||
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_s2mm_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_s2mm_awvalid : OUT STD_LOGIC;
|
||||
m_axi_s2mm_awready : IN STD_LOGIC;
|
||||
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
|
||||
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_s2mm_wlast : OUT STD_LOGIC;
|
||||
m_axi_s2mm_wvalid : OUT STD_LOGIC;
|
||||
m_axi_s2mm_wready : IN STD_LOGIC;
|
||||
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_s2mm_bvalid : IN STD_LOGIC;
|
||||
m_axi_s2mm_bready : OUT STD_LOGIC;
|
||||
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
|
||||
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
|
||||
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
s_axis_s2mm_tvalid : IN STD_LOGIC;
|
||||
s_axis_s2mm_tready : OUT STD_LOGIC;
|
||||
s_axis_s2mm_tlast : IN STD_LOGIC;
|
||||
s_axis_s2mm_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axis_s2mm_tid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
|
||||
s_axis_s2mm_tdest : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
|
||||
s2mm_sts_reset_out_n : OUT STD_LOGIC;
|
||||
s_axis_s2mm_sts_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axis_s2mm_sts_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axis_s2mm_sts_tvalid : IN STD_LOGIC;
|
||||
s_axis_s2mm_sts_tready : OUT STD_LOGIC;
|
||||
s_axis_s2mm_sts_tlast : IN STD_LOGIC;
|
||||
mm2s_introut : OUT STD_LOGIC;
|
||||
s2mm_introut : OUT STD_LOGIC;
|
||||
axi_dma_tstvec : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT axi_dma;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF axi_resetn: SIGNAL IS "XIL_INTERFACENAME AXI_RESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF axi_resetn: SIGNAL IS "xilinx.com:signal:reset:1.0 AXI_RESETN RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axi_s2mm_aclk: SIGNAL IS "XIL_INTERFACENAME M_AXI_S2MM_CLK, ASSOCIATED_BUSIF M_AXI_S2MM:S_AXIS_S2MM:S_AXIS_STS, ASSOCIATED_RESET s2mm_prmry_reset_out_n:s2mm_sts_reset_out_n, FREQ_HZ 200000000, FREQ_TOLERANCE_HZ 0, PHASE 0, CLK_DOMAIN system_top_mig_7series_0_0_ui_clk, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_S2MM_CLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axi_s2mm_awaddr: SIGNAL IS "XIL_INTERFACENAME M_AXI_S2MM, SUPPORTS_NARROW_BURST 0, NUM_WRITE_OUTSTANDING 16, DATA_WIDTH 64, PROTOCOL AXI4, FREQ_HZ 200000000, ID_WIDTH 0, ADDR_WIDTH 40, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, NUM_READ_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0, CLK_DOMAIN system_top_mig_7series_0_0_ui_clk, NUM_READ_THREADS 1, NUM_" &
|
||||
"WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWBURST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWCACHE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWLEN";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWPROT";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWSIZE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WSTRB";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s2mm_introut: SIGNAL IS "XIL_INTERFACENAME S2MM_INTROUT, SENSITIVITY LEVEL_HIGH, PortWidth 1";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s2mm_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 S2MM_INTROUT INTERRUPT";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s2mm_prmry_reset_out_n: SIGNAL IS "XIL_INTERFACENAME S2MM_PRMRY_RESET_OUT_N, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s2mm_prmry_reset_out_n: SIGNAL IS "xilinx.com:signal:reset:1.0 S2MM_PRMRY_RESET_OUT_N RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_lite_aclk: SIGNAL IS "XIL_INTERFACENAME S_AXI_LITE_ACLK, ASSOCIATED_BUSIF S_AXI_LITE:M_AXI, ASSOCIATED_RESET axi_resetn, FREQ_HZ 1e+08, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN system_top_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_LITE_ACLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_lite_awvalid: SIGNAL IS "XIL_INTERFACENAME S_AXI_LITE, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 10, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 0, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN system_top_processing_system7_0_0_FCLK_CLK0, NUM_READ_THR" &
|
||||
"EADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_s2mm_tdata: SIGNAL IS "XIL_INTERFACENAME S_AXIS_S2MM, TDATA_NUM_BYTES 8, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 1, HAS_TLAST 1, FREQ_HZ 200000000, PHASE 0, CLK_DOMAIN system_top_mig_7series_0_0_ui_clk, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TKEEP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TVALID";
|
||||
BEGIN
|
||||
U0 : axi_dma
|
||||
GENERIC MAP (
|
||||
C_S_AXI_LITE_ADDR_WIDTH => 10,
|
||||
C_S_AXI_LITE_DATA_WIDTH => 32,
|
||||
C_DLYTMR_RESOLUTION => 125,
|
||||
C_PRMRY_IS_ACLK_ASYNC => 1,
|
||||
C_ENABLE_MULTI_CHANNEL => 0,
|
||||
C_NUM_MM2S_CHANNELS => 1,
|
||||
C_NUM_S2MM_CHANNELS => 1,
|
||||
C_INCLUDE_SG => 0,
|
||||
C_SG_INCLUDE_STSCNTRL_STRM => 0,
|
||||
C_SG_USE_STSAPP_LENGTH => 0,
|
||||
C_SG_LENGTH_WIDTH => 26,
|
||||
C_M_AXI_SG_ADDR_WIDTH => 40,
|
||||
C_M_AXI_SG_DATA_WIDTH => 32,
|
||||
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => 32,
|
||||
C_S_AXIS_S2MM_STS_TDATA_WIDTH => 32,
|
||||
C_MICRO_DMA => 0,
|
||||
C_INCLUDE_MM2S => 0,
|
||||
C_INCLUDE_MM2S_SF => 1,
|
||||
C_MM2S_BURST_SIZE => 16,
|
||||
C_M_AXI_MM2S_ADDR_WIDTH => 40,
|
||||
C_M_AXI_MM2S_DATA_WIDTH => 32,
|
||||
C_M_AXIS_MM2S_TDATA_WIDTH => 32,
|
||||
C_INCLUDE_MM2S_DRE => 0,
|
||||
C_INCLUDE_S2MM => 1,
|
||||
C_INCLUDE_S2MM_SF => 1,
|
||||
C_S2MM_BURST_SIZE => 16,
|
||||
C_M_AXI_S2MM_ADDR_WIDTH => 40,
|
||||
C_M_AXI_S2MM_DATA_WIDTH => 64,
|
||||
C_S_AXIS_S2MM_TDATA_WIDTH => 64,
|
||||
C_INCLUDE_S2MM_DRE => 0,
|
||||
C_INCREASE_THROUGHPUT => 0,
|
||||
C_FAMILY => "zynq"
|
||||
)
|
||||
PORT MAP (
|
||||
s_axi_lite_aclk => s_axi_lite_aclk,
|
||||
m_axi_sg_aclk => '0',
|
||||
m_axi_mm2s_aclk => '0',
|
||||
m_axi_s2mm_aclk => m_axi_s2mm_aclk,
|
||||
axi_resetn => axi_resetn,
|
||||
s_axi_lite_awvalid => s_axi_lite_awvalid,
|
||||
s_axi_lite_awready => s_axi_lite_awready,
|
||||
s_axi_lite_awaddr => s_axi_lite_awaddr,
|
||||
s_axi_lite_wvalid => s_axi_lite_wvalid,
|
||||
s_axi_lite_wready => s_axi_lite_wready,
|
||||
s_axi_lite_wdata => s_axi_lite_wdata,
|
||||
s_axi_lite_bresp => s_axi_lite_bresp,
|
||||
s_axi_lite_bvalid => s_axi_lite_bvalid,
|
||||
s_axi_lite_bready => s_axi_lite_bready,
|
||||
s_axi_lite_arvalid => s_axi_lite_arvalid,
|
||||
s_axi_lite_arready => s_axi_lite_arready,
|
||||
s_axi_lite_araddr => s_axi_lite_araddr,
|
||||
s_axi_lite_rvalid => s_axi_lite_rvalid,
|
||||
s_axi_lite_rready => s_axi_lite_rready,
|
||||
s_axi_lite_rdata => s_axi_lite_rdata,
|
||||
s_axi_lite_rresp => s_axi_lite_rresp,
|
||||
m_axi_sg_awready => '0',
|
||||
m_axi_sg_wready => '0',
|
||||
m_axi_sg_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
|
||||
m_axi_sg_bvalid => '0',
|
||||
m_axi_sg_arready => '0',
|
||||
m_axi_sg_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
m_axi_sg_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
|
||||
m_axi_sg_rlast => '0',
|
||||
m_axi_sg_rvalid => '0',
|
||||
m_axi_mm2s_arready => '0',
|
||||
m_axi_mm2s_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
m_axi_mm2s_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
|
||||
m_axi_mm2s_rlast => '0',
|
||||
m_axi_mm2s_rvalid => '0',
|
||||
m_axis_mm2s_tready => '0',
|
||||
m_axis_mm2s_cntrl_tready => '0',
|
||||
m_axi_s2mm_awaddr => m_axi_s2mm_awaddr,
|
||||
m_axi_s2mm_awlen => m_axi_s2mm_awlen,
|
||||
m_axi_s2mm_awsize => m_axi_s2mm_awsize,
|
||||
m_axi_s2mm_awburst => m_axi_s2mm_awburst,
|
||||
m_axi_s2mm_awprot => m_axi_s2mm_awprot,
|
||||
m_axi_s2mm_awcache => m_axi_s2mm_awcache,
|
||||
m_axi_s2mm_awvalid => m_axi_s2mm_awvalid,
|
||||
m_axi_s2mm_awready => m_axi_s2mm_awready,
|
||||
m_axi_s2mm_wdata => m_axi_s2mm_wdata,
|
||||
m_axi_s2mm_wstrb => m_axi_s2mm_wstrb,
|
||||
m_axi_s2mm_wlast => m_axi_s2mm_wlast,
|
||||
m_axi_s2mm_wvalid => m_axi_s2mm_wvalid,
|
||||
m_axi_s2mm_wready => m_axi_s2mm_wready,
|
||||
m_axi_s2mm_bresp => m_axi_s2mm_bresp,
|
||||
m_axi_s2mm_bvalid => m_axi_s2mm_bvalid,
|
||||
m_axi_s2mm_bready => m_axi_s2mm_bready,
|
||||
s2mm_prmry_reset_out_n => s2mm_prmry_reset_out_n,
|
||||
s_axis_s2mm_tdata => s_axis_s2mm_tdata,
|
||||
s_axis_s2mm_tkeep => s_axis_s2mm_tkeep,
|
||||
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid,
|
||||
s_axis_s2mm_tready => s_axis_s2mm_tready,
|
||||
s_axis_s2mm_tlast => s_axis_s2mm_tlast,
|
||||
s_axis_s2mm_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
s_axis_s2mm_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
|
||||
s_axis_s2mm_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
|
||||
s_axis_s2mm_sts_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
s_axis_s2mm_sts_tkeep => X"F",
|
||||
s_axis_s2mm_sts_tvalid => '0',
|
||||
s_axis_s2mm_sts_tlast => '0',
|
||||
s2mm_introut => s2mm_introut,
|
||||
axi_dma_tstvec => axi_dma_tstvec
|
||||
);
|
||||
END system_top_axi_dma_2_0_arch;
|
||||
+6
-6
@@ -47,14 +47,14 @@
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:axi_dma:7.1
|
||||
-- IP Revision: 32
|
||||
-- IP Revision: 33
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY axi_dma_v7_1_32;
|
||||
USE axi_dma_v7_1_32.axi_dma;
|
||||
LIBRARY axi_dma_v7_1_33;
|
||||
USE axi_dma_v7_1_33.axi_dma;
|
||||
|
||||
ENTITY system_top_axi_dma_2_0 IS
|
||||
PORT (
|
||||
@@ -262,12 +262,12 @@ ARCHITECTURE system_top_axi_dma_2_0_arch OF system_top_axi_dma_2_0 IS
|
||||
);
|
||||
END COMPONENT axi_dma;
|
||||
ATTRIBUTE X_CORE_INFO : STRING;
|
||||
ATTRIBUTE X_CORE_INFO OF system_top_axi_dma_2_0_arch: ARCHITECTURE IS "axi_dma,Vivado 2024.1";
|
||||
ATTRIBUTE X_CORE_INFO OF system_top_axi_dma_2_0_arch: ARCHITECTURE IS "axi_dma,Vivado 2024.1.2";
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE OF system_top_axi_dma_2_0_arch : ARCHITECTURE IS "system_top_axi_dma_2_0,axi_dma,{}";
|
||||
ATTRIBUTE CORE_GENERATION_INFO : STRING;
|
||||
ATTRIBUTE CORE_GENERATION_INFO OF system_top_axi_dma_2_0_arch: ARCHITECTURE IS "system_top_axi_dma_2_0,axi_dma,{x_ipProduct=Vivado 2024.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_dma,x_ipVersion=7.1,x_ipCoreRevision=32,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_S_AXI_LITE_ADDR_WIDTH=10,C_S_AXI_LITE_DATA_WIDTH=32,C_DLYTMR_RESOLUTION=125,C_PRMRY_IS_ACLK_ASYNC=1,C_ENABLE_MULTI_CHANNEL=0,C_NUM_MM2S_CHANNELS=1,C_NUM_S2MM_CHANNELS=1,C_INCLUDE_SG=0,C_SG_INCLUDE_STSCNTRL_STRM=0,C_SG_USE_STSAPP_LENGTH=0,C_SG_LENGTH_WIDTH=26,C_M_AXI_SG_ADDR_WIDTH=40,C_M_AXI_SG_DATA_WIDTH=3" &
|
||||
"2,C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH=32,C_S_AXIS_S2MM_STS_TDATA_WIDTH=32,C_MICRO_DMA=0,C_INCLUDE_MM2S=0,C_INCLUDE_MM2S_SF=1,C_MM2S_BURST_SIZE=16,C_M_AXI_MM2S_ADDR_WIDTH=40,C_M_AXI_MM2S_DATA_WIDTH=32,C_M_AXIS_MM2S_TDATA_WIDTH=32,C_INCLUDE_MM2S_DRE=0,C_INCLUDE_S2MM=1,C_INCLUDE_S2MM_SF=1,C_S2MM_BURST_SIZE=16,C_M_AXI_S2MM_ADDR_WIDTH=40,C_M_AXI_S2MM_DATA_WIDTH=64,C_S_AXIS_S2MM_TDATA_WIDTH=64,C_INCLUDE_S2MM_DRE=0,C_INCREASE_THROUGHPUT=0,C_FAMILY=zynq}";
|
||||
ATTRIBUTE CORE_GENERATION_INFO OF system_top_axi_dma_2_0_arch: ARCHITECTURE IS "system_top_axi_dma_2_0,axi_dma,{x_ipProduct=Vivado 2024.1.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_dma,x_ipVersion=7.1,x_ipCoreRevision=33,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_S_AXI_LITE_ADDR_WIDTH=10,C_S_AXI_LITE_DATA_WIDTH=32,C_DLYTMR_RESOLUTION=125,C_PRMRY_IS_ACLK_ASYNC=1,C_ENABLE_MULTI_CHANNEL=0,C_NUM_MM2S_CHANNELS=1,C_NUM_S2MM_CHANNELS=1,C_INCLUDE_SG=0,C_SG_INCLUDE_STSCNTRL_STRM=0,C_SG_USE_STSAPP_LENGTH=0,C_SG_LENGTH_WIDTH=26,C_M_AXI_SG_ADDR_WIDTH=40,C_M_AXI_SG_DATA_WIDTH" &
|
||||
"=32,C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH=32,C_S_AXIS_S2MM_STS_TDATA_WIDTH=32,C_MICRO_DMA=0,C_INCLUDE_MM2S=0,C_INCLUDE_MM2S_SF=1,C_MM2S_BURST_SIZE=16,C_M_AXI_MM2S_ADDR_WIDTH=40,C_M_AXI_MM2S_DATA_WIDTH=32,C_M_AXIS_MM2S_TDATA_WIDTH=32,C_INCLUDE_MM2S_DRE=0,C_INCLUDE_S2MM=1,C_INCLUDE_S2MM_SF=1,C_S2MM_BURST_SIZE=16,C_M_AXI_S2MM_ADDR_WIDTH=40,C_M_AXI_S2MM_DATA_WIDTH=64,C_S_AXIS_S2MM_TDATA_WIDTH=64,C_INCLUDE_S2MM_DRE=0,C_INCREASE_THROUGHPUT=0,C_FAMILY=zynq}";
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF axi_resetn: SIGNAL IS "XIL_INTERFACENAME AXI_RESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
|
||||
+3
-3
@@ -4,7 +4,7 @@
|
||||
"xci_name": "system_top_axi_dma_2_0",
|
||||
"cell_name": "axi_dma_2",
|
||||
"component_reference": "xilinx.com:ip:axi_dma:7.1",
|
||||
"ip_revision": "32",
|
||||
"ip_revision": "33",
|
||||
"gen_directory": ".",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
@@ -85,12 +85,12 @@
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "32" } ],
|
||||
"IPREVISION": [ { "value": "33" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "." } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2024.1" } ],
|
||||
"SWVERSION": [ { "value": "2024.1.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
|
||||
+332
-13
File diff suppressed because it is too large
Load Diff
+213
@@ -0,0 +1,213 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
|
||||
-- IP Revision: 34
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY axi_gpio_v2_0_34;
|
||||
USE axi_gpio_v2_0_34.axi_gpio;
|
||||
|
||||
ENTITY system_top_axi_gpio_0_0 IS
|
||||
PORT (
|
||||
s_axi_aclk : IN STD_LOGIC;
|
||||
s_axi_aresetn : IN STD_LOGIC;
|
||||
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_awvalid : IN STD_LOGIC;
|
||||
s_axi_awready : OUT STD_LOGIC;
|
||||
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_wvalid : IN STD_LOGIC;
|
||||
s_axi_wready : OUT STD_LOGIC;
|
||||
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_bvalid : OUT STD_LOGIC;
|
||||
s_axi_bready : IN STD_LOGIC;
|
||||
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_arvalid : IN STD_LOGIC;
|
||||
s_axi_arready : OUT STD_LOGIC;
|
||||
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_rvalid : OUT STD_LOGIC;
|
||||
s_axi_rready : IN STD_LOGIC;
|
||||
ip2intc_irpt : OUT STD_LOGIC;
|
||||
gpio_io_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
gpio_io_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
gpio_io_t : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
|
||||
);
|
||||
END system_top_axi_gpio_0_0;
|
||||
|
||||
ARCHITECTURE system_top_axi_gpio_0_0_arch OF system_top_axi_gpio_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_top_axi_gpio_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axi_gpio IS
|
||||
GENERIC (
|
||||
C_FAMILY : STRING;
|
||||
C_S_AXI_ADDR_WIDTH : INTEGER;
|
||||
C_S_AXI_DATA_WIDTH : INTEGER;
|
||||
C_GPIO_WIDTH : INTEGER;
|
||||
C_GPIO2_WIDTH : INTEGER;
|
||||
C_ALL_INPUTS : INTEGER;
|
||||
C_ALL_INPUTS_2 : INTEGER;
|
||||
C_ALL_OUTPUTS : INTEGER;
|
||||
C_ALL_OUTPUTS_2 : INTEGER;
|
||||
C_INTERRUPT_PRESENT : INTEGER;
|
||||
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
C_IS_DUAL : INTEGER;
|
||||
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
PORT (
|
||||
s_axi_aclk : IN STD_LOGIC;
|
||||
s_axi_aresetn : IN STD_LOGIC;
|
||||
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_awvalid : IN STD_LOGIC;
|
||||
s_axi_awready : OUT STD_LOGIC;
|
||||
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_wvalid : IN STD_LOGIC;
|
||||
s_axi_wready : OUT STD_LOGIC;
|
||||
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_bvalid : OUT STD_LOGIC;
|
||||
s_axi_bready : IN STD_LOGIC;
|
||||
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_arvalid : IN STD_LOGIC;
|
||||
s_axi_arready : OUT STD_LOGIC;
|
||||
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_rvalid : OUT STD_LOGIC;
|
||||
s_axi_rready : IN STD_LOGIC;
|
||||
ip2intc_irpt : OUT STD_LOGIC;
|
||||
gpio_io_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
gpio_io_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
gpio_io_t : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT axi_gpio;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF gpio_io_i: SIGNAL IS "XIL_INTERFACENAME GPIO, BOARD.ASSOCIATED_PARAM GPIO_BOARD_INTERFACE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_t: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_T";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF ip2intc_irpt: SIGNAL IS "XIL_INTERFACENAME IP2INTC_IRQ, SENSITIVITY LEVEL_HIGH, PortWidth 1";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF ip2intc_irpt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 IP2INTC_IRQ INTERRUPT";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aclk: SIGNAL IS "XIL_INTERFACENAME S_AXI_ACLK, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 1e+08, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN system_top_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME S_AXI_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 9, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN system_top_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1" &
|
||||
", NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
|
||||
BEGIN
|
||||
U0 : axi_gpio
|
||||
GENERIC MAP (
|
||||
C_FAMILY => "zynq",
|
||||
C_S_AXI_ADDR_WIDTH => 9,
|
||||
C_S_AXI_DATA_WIDTH => 32,
|
||||
C_GPIO_WIDTH => 1,
|
||||
C_GPIO2_WIDTH => 32,
|
||||
C_ALL_INPUTS => 0,
|
||||
C_ALL_INPUTS_2 => 0,
|
||||
C_ALL_OUTPUTS => 0,
|
||||
C_ALL_OUTPUTS_2 => 0,
|
||||
C_INTERRUPT_PRESENT => 1,
|
||||
C_DOUT_DEFAULT => X"00000000",
|
||||
C_TRI_DEFAULT => X"FFFFFFFF",
|
||||
C_IS_DUAL => 0,
|
||||
C_DOUT_DEFAULT_2 => X"00000000",
|
||||
C_TRI_DEFAULT_2 => X"FFFFFFFF"
|
||||
)
|
||||
PORT MAP (
|
||||
s_axi_aclk => s_axi_aclk,
|
||||
s_axi_aresetn => s_axi_aresetn,
|
||||
s_axi_awaddr => s_axi_awaddr,
|
||||
s_axi_awvalid => s_axi_awvalid,
|
||||
s_axi_awready => s_axi_awready,
|
||||
s_axi_wdata => s_axi_wdata,
|
||||
s_axi_wstrb => s_axi_wstrb,
|
||||
s_axi_wvalid => s_axi_wvalid,
|
||||
s_axi_wready => s_axi_wready,
|
||||
s_axi_bresp => s_axi_bresp,
|
||||
s_axi_bvalid => s_axi_bvalid,
|
||||
s_axi_bready => s_axi_bready,
|
||||
s_axi_araddr => s_axi_araddr,
|
||||
s_axi_arvalid => s_axi_arvalid,
|
||||
s_axi_arready => s_axi_arready,
|
||||
s_axi_rdata => s_axi_rdata,
|
||||
s_axi_rresp => s_axi_rresp,
|
||||
s_axi_rvalid => s_axi_rvalid,
|
||||
s_axi_rready => s_axi_rready,
|
||||
ip2intc_irpt => ip2intc_irpt,
|
||||
gpio_io_i => gpio_io_i,
|
||||
gpio_io_o => gpio_io_o,
|
||||
gpio_io_t => gpio_io_t,
|
||||
gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
|
||||
);
|
||||
END system_top_axi_gpio_0_0_arch;
|
||||
+5
-5
@@ -47,14 +47,14 @@
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
|
||||
-- IP Revision: 33
|
||||
-- IP Revision: 34
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY axi_gpio_v2_0_33;
|
||||
USE axi_gpio_v2_0_33.axi_gpio;
|
||||
LIBRARY axi_gpio_v2_0_34;
|
||||
USE axi_gpio_v2_0_34.axi_gpio;
|
||||
|
||||
ENTITY system_top_axi_gpio_0_0 IS
|
||||
PORT (
|
||||
@@ -135,11 +135,11 @@ ARCHITECTURE system_top_axi_gpio_0_0_arch OF system_top_axi_gpio_0_0 IS
|
||||
);
|
||||
END COMPONENT axi_gpio;
|
||||
ATTRIBUTE X_CORE_INFO : STRING;
|
||||
ATTRIBUTE X_CORE_INFO OF system_top_axi_gpio_0_0_arch: ARCHITECTURE IS "axi_gpio,Vivado 2024.1";
|
||||
ATTRIBUTE X_CORE_INFO OF system_top_axi_gpio_0_0_arch: ARCHITECTURE IS "axi_gpio,Vivado 2024.1.2";
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE OF system_top_axi_gpio_0_0_arch : ARCHITECTURE IS "system_top_axi_gpio_0_0,axi_gpio,{}";
|
||||
ATTRIBUTE CORE_GENERATION_INFO : STRING;
|
||||
ATTRIBUTE CORE_GENERATION_INFO OF system_top_axi_gpio_0_0_arch: ARCHITECTURE IS "system_top_axi_gpio_0_0,axi_gpio,{x_ipProduct=Vivado 2024.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_gpio,x_ipVersion=2.0,x_ipCoreRevision=33,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_S_AXI_ADDR_WIDTH=9,C_S_AXI_DATA_WIDTH=32,C_GPIO_WIDTH=1,C_GPIO2_WIDTH=32,C_ALL_INPUTS=0,C_ALL_INPUTS_2=0,C_ALL_OUTPUTS=0,C_ALL_OUTPUTS_2=0,C_INTERRUPT_PRESENT=1,C_DOUT_DEFAULT=0x00000000,C_TRI_DEFAULT=0xFFFFFFFF,C_IS_DUAL=0,C_DOUT_DEFAULT_2=0x00000000,C_TRI_DEFAULT_2=0xFFFFFFFF}";
|
||||
ATTRIBUTE CORE_GENERATION_INFO OF system_top_axi_gpio_0_0_arch: ARCHITECTURE IS "system_top_axi_gpio_0_0,axi_gpio,{x_ipProduct=Vivado 2024.1.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_gpio,x_ipVersion=2.0,x_ipCoreRevision=34,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_S_AXI_ADDR_WIDTH=9,C_S_AXI_DATA_WIDTH=32,C_GPIO_WIDTH=1,C_GPIO2_WIDTH=32,C_ALL_INPUTS=0,C_ALL_INPUTS_2=0,C_ALL_OUTPUTS=0,C_ALL_OUTPUTS_2=0,C_INTERRUPT_PRESENT=1,C_DOUT_DEFAULT=0x00000000,C_TRI_DEFAULT=0xFFFFFFFF,C_IS_DUAL=0,C_DOUT_DEFAULT_2=0x00000000,C_TRI_DEFAULT_2=0xFFFFFFFF}";
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF gpio_io_i: SIGNAL IS "XIL_INTERFACENAME GPIO, BOARD.ASSOCIATED_PARAM GPIO_BOARD_INTERFACE";
|
||||
|
||||
+3
-3
@@ -4,7 +4,7 @@
|
||||
"xci_name": "system_top_axi_gpio_0_0",
|
||||
"cell_name": "axi_gpio_0",
|
||||
"component_reference": "xilinx.com:ip:axi_gpio:2.0",
|
||||
"ip_revision": "33",
|
||||
"ip_revision": "34",
|
||||
"gen_directory": ".",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
@@ -58,12 +58,12 @@
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "33" } ],
|
||||
"IPREVISION": [ { "value": "34" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "." } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2024.1" } ],
|
||||
"SWVERSION": [ { "value": "2024.1.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
|
||||
+152
-12
@@ -968,11 +968,11 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Oct 31 03:29:39 UTC 2024</spirit:value>
|
||||
<spirit:value>Sun Nov 03 07:50:03 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:828cf3db</spirit:value>
|
||||
<spirit:value>9:b56aaf62</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -983,7 +983,56 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:828cf3db</spirit:value>
|
||||
<spirit:value>9:b56aaf62</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_vhdlbehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>VHDL Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:language>vhdl</spirit:language>
|
||||
<spirit:modelName>axi_gpio</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_vhdlbehavioralsimulation_xilinx_com_ip_axi_lite_ipif_3_0__ref_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_vhdlbehavioralsimulation_xilinx_com_ip_lib_cdc_1_0__ref_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_vhdlbehavioralsimulation_xilinx_com_ip_interrupt_control_3_1__ref_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_vhdlbehavioralsimulation_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Nov 03 07:50:03 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:8468d3cf</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
|
||||
<spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
|
||||
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
|
||||
<spirit:language>vhdl</spirit:language>
|
||||
<spirit:modelName>system_top_axi_gpio_0_0</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Nov 03 07:50:03 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:8468d3cf</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -1008,11 +1057,11 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Oct 31 03:29:39 UTC 2024</spirit:value>
|
||||
<spirit:value>Sun Nov 03 07:50:03 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:828cf3db</spirit:value>
|
||||
<spirit:value>9:b56aaf62</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -1028,11 +1077,11 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Oct 31 03:29:39 UTC 2024</spirit:value>
|
||||
<spirit:value>Sun Nov 03 07:50:03 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:828cf3db</spirit:value>
|
||||
<spirit:value>9:b56aaf62</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -1046,6 +1095,7 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1061,6 +1111,7 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1080,6 +1131,7 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1095,6 +1147,7 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1110,6 +1163,7 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1126,6 +1180,7 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1145,6 +1200,7 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1160,6 +1216,7 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1175,6 +1232,7 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1191,6 +1249,7 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1203,6 +1262,7 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1215,6 +1275,7 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1234,6 +1295,7 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1249,6 +1311,7 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1264,6 +1327,7 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1280,6 +1344,7 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1296,6 +1361,7 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1308,6 +1374,7 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1320,6 +1387,7 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1335,6 +1403,7 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1358,6 +1427,7 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1384,6 +1454,7 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1407,6 +1478,7 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1430,6 +1502,7 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1456,6 +1529,7 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1479,6 +1553,7 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
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||||
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||||
@@ -1593,6 +1668,71 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output
|
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<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
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<spirit:file>
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<spirit:name>../../ipshared/d8cc/hdl/interrupt_control_v3_1_vh_rfs.vhd</spirit:name>
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<spirit:fileType>vhdlSource</spirit:fileType>
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<spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
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<spirit:logicalName>interrupt_control_v3_1_5</spirit:logicalName>
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</spirit:file>
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<xilinx:componentRef xilinx:vendor="xilinx.com" xilinx:library="ip" xilinx:name="interrupt_control" xilinx:version="3.1" xilinx:isGenerated="true" xilinx:checksum="f8eb3d48">
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<xilinx:mode xilinx:name="copy_mode"/>
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||||
<spirit:name>xilinx_vhdlbehavioralsimulation_view_fileset</spirit:name>
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||||
<spirit:file>
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<spirit:name>../../ipshared/376d/hdl/axi_gpio_v2_0_vh_rfs.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
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||||
<spirit:logicalName>axi_gpio_v2_0_34</spirit:logicalName>
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</spirit:file>
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</spirit:fileSet>
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<spirit:fileSet>
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<spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
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||||
<spirit:name>sim/system_top_axi_gpio_0_0.vhd</spirit:name>
|
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<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
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</spirit:file>
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||||
</spirit:fileSet>
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<spirit:fileSet>
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||||
<spirit:name>xilinx_vhdlsynthesis_xilinx_com_ip_axi_lite_ipif_3_0__ref_view_fileset</spirit:name>
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||||
<spirit:file>
|
||||
@@ -1652,9 +1792,9 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output
|
||||
<spirit:userFileType>xdc</spirit:userFileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../ipshared/4208/hdl/axi_gpio_v2_0_vh_rfs.vhd</spirit:name>
|
||||
<spirit:name>../../ipshared/376d/hdl/axi_gpio_v2_0_vh_rfs.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
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<spirit:logicalName>axi_gpio_v2_0_33</spirit:logicalName>
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<spirit:logicalName>axi_gpio_v2_0_34</spirit:logicalName>
|
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</spirit:file>
|
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</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
@@ -1861,7 +2001,7 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output
|
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<spirit:vendorExtensions>
|
||||
<xilinx:coreExtensions>
|
||||
<xilinx:displayName>AXI GPIO</xilinx:displayName>
|
||||
<xilinx:coreRevision>33</xilinx:coreRevision>
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||||
<xilinx:coreRevision>34</xilinx:coreRevision>
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||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.GPIO.BOARD.ASSOCIATED_PARAM" xilinx:valuePermission="bd"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.IP2INTC_IRQ.PortWidth" xilinx:valuePermission="bd"/>
|
||||
@@ -1910,10 +2050,10 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output
|
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</xilinx:configElementInfos>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
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||||
<xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
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<xilinx:xilinxVersion>2024.1.2</xilinx:xilinxVersion>
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<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="c44adf9c"/>
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<xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="00000000"/>
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<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="0d175444"/>
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<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="d8995b8e"/>
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<xilinx:checksum xilinx:scope="ports" xilinx:value="37568ea5"/>
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<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="534583c0"/>
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<xilinx:checksum xilinx:scope="parameters" xilinx:value="ccd9f43d"/>
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||||
+1
-1
@@ -8,7 +8,7 @@
|
||||
"rev_ctrl_bd_flag": "RevCtrlBdOff",
|
||||
"scoped": "true",
|
||||
"synth_flow_mode": "None",
|
||||
"tool_version": "2024.1",
|
||||
"tool_version": "2024.1.2",
|
||||
"validated": "true"
|
||||
},
|
||||
"design_tree": {
|
||||
|
||||
+10
-4
@@ -2,10 +2,10 @@
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||||
<Root MajorVersion="0" MinorVersion="43">
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<CompositeFile CompositeFileTopName="bd_222a" CanBeSetAsTop="true" CanDisplayChildGraph="true">
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<Description>Composite Fileset</Description>
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<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1730345378"/>
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<Generation Name="SIMULATION" State="STALE" Timestamp="1730345376"/>
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<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1730345378"/>
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||||
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1730345378"/>
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<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1730620201"/>
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<Generation Name="SIMULATION" State="GENERATED" Timestamp="1730620201"/>
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||||
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1730620201"/>
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<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1730620201"/>
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||||
<FileCollection Name="SOURCES" Type="SOURCES">
|
||||
<File Name="ip/ip_0/bd_222a_one_0.xci" Type="IP">
|
||||
<Instance HierarchyPath="clk_map/one"/>
|
||||
@@ -428,6 +428,12 @@
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
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||||
<File Name="sim/bd_222a.protoinst">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
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<UsedIn Val="SIMULATION"/>
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<ProcessingOrder Val="NORMAL"/>
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||||
</File>
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||||
</FileCollection>
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||||
</CompositeFile>
|
||||
</Root>
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||||
|
||||
+1
-1
@@ -1,5 +1,5 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Thu Oct 31 11:29:38 2024" VIVADOVERSION="2024.1">
|
||||
<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Sun Nov 3 15:50:01 2024" VIVADOVERSION="2024.1.2">
|
||||
|
||||
<SYSTEMINFO ARCH="zynq" BOARD="xilinx.com:zc706:part0:1.4" DEVICE="7z045" NAME="bd_222a" PACKAGE="ffg900" SPEEDGRADE="-2"/>
|
||||
|
||||
|
||||
+1
-1
@@ -37,7 +37,7 @@
|
||||
"OUTPUTDIR": [ { "value": "." } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../../../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2024.1" } ],
|
||||
"SWVERSION": [ { "value": "2024.1.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
|
||||
+133
-3
@@ -17,6 +17,94 @@
|
||||
</spirit:parameter>
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||||
</spirit:parameters>
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||||
</spirit:view>
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||||
<spirit:view>
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||||
<spirit:name>xilinx_systemcsimulation</spirit:name>
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||||
<spirit:displayName>SystemC Simulation</spirit:displayName>
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<spirit:envIdentifier>systemCSource:vivado.xilinx.com:simulation</spirit:envIdentifier>
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<spirit:language>systemc</spirit:language>
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||||
<spirit:modelName>xlconstant_v1_1_9</spirit:modelName>
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<spirit:fileSetRef>
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<spirit:localName>xilinx_systemcsimulation_view_fileset</spirit:localName>
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</spirit:fileSetRef>
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<spirit:parameters>
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<spirit:parameter>
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||||
<spirit:name>GENtimestamp</spirit:name>
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||||
<spirit:value>Sun Nov 03 07:49:59 UTC 2024</spirit:value>
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||||
</spirit:parameter>
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||||
<spirit:parameter>
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<spirit:name>outputProductCRC</spirit:name>
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<spirit:value>9:38a3e170</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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||||
<spirit:name>sim_type</spirit:name>
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<spirit:value>tlm</spirit:value>
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<spirit:name>xilinx_verilogbehavioralsimulation</spirit:name>
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<spirit:displayName>Verilog Simulation</spirit:displayName>
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<spirit:language>verilog</spirit:language>
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<spirit:modelName>bd_222a_one_0</spirit:modelName>
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<spirit:name>outputProductCRC</spirit:name>
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<spirit:value>9:38a3e170</spirit:value>
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||||
<spirit:name>xilinx_verilogsynthesis</spirit:name>
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||||
<spirit:displayName>Verilog Synthesis</spirit:displayName>
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||||
@@ -29,7 +117,7 @@
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||||
<spirit:parameters>
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||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
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||||
<spirit:value>Thu Oct 31 03:29:29 UTC 2024</spirit:value>
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||||
<spirit:value>Sun Nov 03 07:49:49 UTC 2024</spirit:value>
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||||
</spirit:parameter>
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||||
<spirit:parameter>
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||||
<spirit:name>outputProductCRC</spirit:name>
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@@ -49,7 +137,7 @@
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>GENtimestamp</spirit:name>
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<spirit:value>Thu Oct 31 03:29:36 UTC 2024</spirit:value>
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<spirit:value>Sun Nov 03 07:49:59 UTC 2024</spirit:value>
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||||
</spirit:parameter>
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<spirit:parameter>
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<spirit:name>outputProductCRC</spirit:name>
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@@ -71,6 +159,7 @@
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<spirit:wireTypeDef>
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||||
<spirit:typeName>std_logic_vector</spirit:typeName>
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<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
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||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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||||
</spirit:wireTypeDefs>
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||||
</spirit:wire>
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||||
@@ -90,6 +179,47 @@
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||||
</spirit:modelParameters>
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</spirit:model>
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<spirit:fileSets>
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<spirit:name>sim/xlconstant_v1_1_9.h</spirit:name>
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<spirit:fileType>systemCSource</spirit:fileType>
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<spirit:isIncludeFile>true</spirit:isIncludeFile>
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<spirit:name>xilinx_systemcsimulationwrapper_view_fileset</spirit:name>
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<spirit:fileType>systemCSource</spirit:fileType>
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<spirit:isIncludeFile>true</spirit:isIncludeFile>
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<spirit:name>sim/bd_222a_one_0.cpp</spirit:name>
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<spirit:name>xilinx_verilogbehavioralsimulation_view_fileset</spirit:name>
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<spirit:file>
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<spirit:name>../../../../../ipshared/e2d2/hdl/xlconstant_v1_1_vl_rfs.v</spirit:name>
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<spirit:fileType>verilogSource</spirit:fileType>
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<spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
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<spirit:name>xilinx_verilogsimulationwrapper_view_fileset</spirit:name>
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<spirit:fileType>verilogSource</spirit:fileType>
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<spirit:fileSet>
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<spirit:name>xilinx_verilogsynthesis_view_fileset</spirit:name>
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<spirit:file>
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@@ -130,7 +260,7 @@
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<xilinx:coreRevision>9</xilinx:coreRevision>
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</xilinx:coreExtensions>
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<xilinx:packagingInfo>
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<xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
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<xilinx:xilinxVersion>2024.1.2</xilinx:xilinxVersion>
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<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="edd4a3fb"/>
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<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="0fa77f35"/>
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+69
@@ -0,0 +1,69 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
#ifndef _bd_222a_one_0_CPP_
|
||||
#define _bd_222a_one_0_CPP_
|
||||
|
||||
#include "bd_222a_one_0.h"
|
||||
|
||||
bd_222a_one_0::bd_222a_one_0 (sc_core::sc_module_name name) :sc_module(name), mod("mod"), dout("dout") {
|
||||
mod.dout(dout);
|
||||
}
|
||||
#ifdef MTI_SYSTEMC
|
||||
SC_MODULE_EXPORT(bd_222a_one_0);
|
||||
#endif
|
||||
|
||||
#ifdef XM_SYSTEMC
|
||||
XMSC_MODULE_EXPORT(bd_222a_one_0);
|
||||
#endif
|
||||
|
||||
#ifdef RIVIERA
|
||||
SC_MODULE_EXPORT(bd_222a_one_0);
|
||||
#endif
|
||||
#endif
|
||||
+62
@@ -0,0 +1,62 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
#ifndef _bd_222a_one_0_H_
|
||||
#define _bd_222a_one_0_H_
|
||||
|
||||
#include "xlconstant_v1_1_9.h"
|
||||
#include "systemc.h"
|
||||
class bd_222a_one_0 : public sc_module {
|
||||
public:
|
||||
xlconstant_v1_1_9<1,1> mod;
|
||||
sc_out< sc_bv<1> > dout;
|
||||
bd_222a_one_0 (sc_core::sc_module_name name);
|
||||
};
|
||||
|
||||
#endif
|
||||
+68
@@ -0,0 +1,68 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:xlconstant:1.1
|
||||
// IP Revision: 9
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_222a_one_0 (
|
||||
dout
|
||||
);
|
||||
|
||||
output wire [0 : 0] dout;
|
||||
|
||||
xlconstant_v1_1_9_xlconstant #(
|
||||
.CONST_WIDTH(1),
|
||||
.CONST_VAL(1'H1)
|
||||
) inst (
|
||||
.dout(dout)
|
||||
);
|
||||
endmodule
|
||||
+77
@@ -0,0 +1,77 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
//------------------------------------------------------------------------------------
|
||||
// Filename: xl_Constant_stub.sv
|
||||
// Description: This HDL file is intended to be used with following simulators only:
|
||||
//
|
||||
// Vivado Simulator (XSim)
|
||||
// Cadence Xcelium Simulator
|
||||
//
|
||||
//------------------------------------------------------------------------------------
|
||||
`ifdef XILINX_SIMULATOR
|
||||
`ifndef XILINX_SIMULATOR_BITASBOOL
|
||||
`define XILINX_SIMULATOR_BITASBOOL
|
||||
typedef bit bit_as_bool;
|
||||
`endif
|
||||
|
||||
(* SC_MODULE_EXPORT *)
|
||||
module bd_222a_one_0 (
|
||||
output bit [0 : 0 ] dout
|
||||
);
|
||||
endmodule
|
||||
`endif
|
||||
|
||||
`ifdef XCELIUM
|
||||
(* XMSC_MODULE_EXPORT *)
|
||||
module bd_222a_one_0 (dout)
|
||||
(* integer foreign = "SystemC";
|
||||
*);
|
||||
output wire [0 : 0 ] dout;
|
||||
endmodule
|
||||
`endif
|
||||
+66
@@ -0,0 +1,66 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
#ifndef _xlconstant_v1_1_9_H_
|
||||
#define _xlconstant_v1_1_9_H_
|
||||
|
||||
#include "systemc.h"
|
||||
template<int CONST_WIDTH,long int CONST_VAL>
|
||||
SC_MODULE(xlconstant_v1_1_9) {
|
||||
public:
|
||||
sc_out< sc_bv<CONST_WIDTH> > dout;
|
||||
void init() {
|
||||
dout.write(CONST_VAL);
|
||||
}
|
||||
SC_CTOR(xlconstant_v1_1_9) {
|
||||
SC_METHOD(init);
|
||||
}
|
||||
};
|
||||
|
||||
#endif
|
||||
+2
-2
@@ -50,9 +50,9 @@
|
||||
// IP VLNV: xilinx.com:ip:xlconstant:1.1
|
||||
// IP Revision: 9
|
||||
|
||||
(* X_CORE_INFO = "xlconstant_v1_1_9_xlconstant,Vivado 2024.1" *)
|
||||
(* X_CORE_INFO = "xlconstant_v1_1_9_xlconstant,Vivado 2024.1.2" *)
|
||||
(* CHECK_LICENSE_TYPE = "bd_222a_one_0,xlconstant_v1_1_9_xlconstant,{}" *)
|
||||
(* CORE_GENERATION_INFO = "bd_222a_one_0,xlconstant_v1_1_9_xlconstant,{x_ipProduct=Vivado 2024.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconstant,x_ipVersion=1.1,x_ipCoreRevision=9,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,CONST_WIDTH=1,CONST_VAL=0x1}" *)
|
||||
(* CORE_GENERATION_INFO = "bd_222a_one_0,xlconstant_v1_1_9_xlconstant,{x_ipProduct=Vivado 2024.1.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconstant,x_ipVersion=1.1,x_ipCoreRevision=9,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,CONST_WIDTH=1,CONST_VAL=0x1}" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_222a_one_0 (
|
||||
dout
|
||||
|
||||
+1
-1
@@ -52,7 +52,7 @@
|
||||
"OUTPUTDIR": [ { "value": "." } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../../../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2024.1" } ],
|
||||
"SWVERSION": [ { "value": "2024.1.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
|
||||
+90
-4
@@ -398,7 +398,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Oct 31 03:29:36 UTC 2024</spirit:value>
|
||||
<spirit:value>Sun Nov 03 07:49:59 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -417,6 +417,49 @@
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_vhdlbehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>VHDL Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:language>vhdl</spirit:language>
|
||||
<spirit:modelName>proc_sys_reset</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_vhdlbehavioralsimulation_xilinx_com_ip_lib_cdc_1_0__ref_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_vhdlbehavioralsimulation_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Nov 03 07:49:39 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:e0fed78a</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
|
||||
<spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
|
||||
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
|
||||
<spirit:language>vhdl</spirit:language>
|
||||
<spirit:modelName>bd_222a_psr_aclk_0</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Nov 03 07:49:59 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:e0fed78a</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_vhdlsynthesis</spirit:name>
|
||||
<spirit:displayName>VHDL Synthesis</spirit:displayName>
|
||||
@@ -432,7 +475,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Oct 31 03:29:36 UTC 2024</spirit:value>
|
||||
<spirit:value>Sun Nov 03 07:49:59 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -452,7 +495,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Oct 31 03:29:36 UTC 2024</spirit:value>
|
||||
<spirit:value>Sun Nov 03 07:49:59 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -470,6 +513,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -482,6 +526,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -494,6 +539,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -509,6 +555,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -524,6 +571,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -539,6 +587,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -558,6 +607,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -577,6 +627,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -596,6 +647,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -615,6 +667,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -688,6 +741,39 @@
|
||||
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlbehavioralsimulation_xilinx_com_ip_lib_cdc_1_0__ref_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>../../../../../ipshared/2a4f/hdl/lib_cdc_v1_0_rfs.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
|
||||
<spirit:logicalName>lib_cdc_v1_0_3</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:subCoreRef>
|
||||
<xilinx:componentRef xilinx:vendor="xilinx.com" xilinx:library="ip" xilinx:name="lib_cdc" xilinx:version="1.0" xilinx:isGenerated="true" xilinx:checksum="726cb4eb">
|
||||
<xilinx:mode xilinx:name="copy_mode"/>
|
||||
</xilinx:componentRef>
|
||||
</xilinx:subCoreRef>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlbehavioralsimulation_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>../../../../../ipshared/3a26/hdl/proc_sys_reset_v5_0_vh_rfs.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
|
||||
<spirit:logicalName>proc_sys_reset_v5_0_15</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>sim/bd_222a_psr_aclk_0.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlsynthesis_xilinx_com_ip_lib_cdc_1_0__ref_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
@@ -812,7 +898,7 @@
|
||||
</xilinx:configElementInfos>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
|
||||
<xilinx:xilinxVersion>2024.1.2</xilinx:xilinxVersion>
|
||||
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="26169568"/>
|
||||
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="c4adc7a2"/>
|
||||
<xilinx:checksum xilinx:scope="ports" xilinx:value="f2ac9635"/>
|
||||
|
||||
+147
@@ -0,0 +1,147 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
|
||||
-- IP Revision: 15
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY proc_sys_reset_v5_0_15;
|
||||
USE proc_sys_reset_v5_0_15.proc_sys_reset;
|
||||
|
||||
ENTITY bd_222a_psr_aclk_0 IS
|
||||
PORT (
|
||||
slowest_sync_clk : IN STD_LOGIC;
|
||||
ext_reset_in : IN STD_LOGIC;
|
||||
aux_reset_in : IN STD_LOGIC;
|
||||
mb_debug_sys_rst : IN STD_LOGIC;
|
||||
dcm_locked : IN STD_LOGIC;
|
||||
mb_reset : OUT STD_LOGIC;
|
||||
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
|
||||
);
|
||||
END bd_222a_psr_aclk_0;
|
||||
|
||||
ARCHITECTURE bd_222a_psr_aclk_0_arch OF bd_222a_psr_aclk_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF bd_222a_psr_aclk_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT proc_sys_reset IS
|
||||
GENERIC (
|
||||
C_FAMILY : STRING;
|
||||
C_EXT_RST_WIDTH : INTEGER;
|
||||
C_AUX_RST_WIDTH : INTEGER;
|
||||
C_EXT_RESET_HIGH : STD_LOGIC;
|
||||
C_AUX_RESET_HIGH : STD_LOGIC;
|
||||
C_NUM_BUS_RST : INTEGER;
|
||||
C_NUM_PERP_RST : INTEGER;
|
||||
C_NUM_INTERCONNECT_ARESETN : INTEGER;
|
||||
C_NUM_PERP_ARESETN : INTEGER
|
||||
);
|
||||
PORT (
|
||||
slowest_sync_clk : IN STD_LOGIC;
|
||||
ext_reset_in : IN STD_LOGIC;
|
||||
aux_reset_in : IN STD_LOGIC;
|
||||
mb_debug_sys_rst : IN STD_LOGIC;
|
||||
dcm_locked : IN STD_LOGIC;
|
||||
mb_reset : OUT STD_LOGIC;
|
||||
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT proc_sys_reset;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF aux_reset_in: SIGNAL IS "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF bus_struct_reset: SIGNAL IS "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF ext_reset_in: SIGNAL IS "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF interconnect_aresetn: SIGNAL IS "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF mb_debug_sys_rst: SIGNAL IS "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF mb_reset: SIGNAL IS "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_aresetn: SIGNAL IS "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_reset: SIGNAL IS "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF slowest_sync_clk: SIGNAL IS "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 200000000, FREQ_TOLERANCE_HZ 0, PHASE 0, CLK_DOMAIN system_top_mig_7series_0_0_ui_clk, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
|
||||
BEGIN
|
||||
U0 : proc_sys_reset
|
||||
GENERIC MAP (
|
||||
C_FAMILY => "zynq",
|
||||
C_EXT_RST_WIDTH => 4,
|
||||
C_AUX_RST_WIDTH => 1,
|
||||
C_EXT_RESET_HIGH => '0',
|
||||
C_AUX_RESET_HIGH => '0',
|
||||
C_NUM_BUS_RST => 1,
|
||||
C_NUM_PERP_RST => 1,
|
||||
C_NUM_INTERCONNECT_ARESETN => 1,
|
||||
C_NUM_PERP_ARESETN => 1
|
||||
)
|
||||
PORT MAP (
|
||||
slowest_sync_clk => slowest_sync_clk,
|
||||
ext_reset_in => ext_reset_in,
|
||||
aux_reset_in => aux_reset_in,
|
||||
mb_debug_sys_rst => mb_debug_sys_rst,
|
||||
dcm_locked => dcm_locked,
|
||||
mb_reset => mb_reset,
|
||||
bus_struct_reset => bus_struct_reset,
|
||||
peripheral_reset => peripheral_reset,
|
||||
interconnect_aresetn => interconnect_aresetn,
|
||||
peripheral_aresetn => peripheral_aresetn
|
||||
);
|
||||
END bd_222a_psr_aclk_0_arch;
|
||||
+2
-2
@@ -100,11 +100,11 @@ ARCHITECTURE bd_222a_psr_aclk_0_arch OF bd_222a_psr_aclk_0 IS
|
||||
);
|
||||
END COMPONENT proc_sys_reset;
|
||||
ATTRIBUTE X_CORE_INFO : STRING;
|
||||
ATTRIBUTE X_CORE_INFO OF bd_222a_psr_aclk_0_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2024.1";
|
||||
ATTRIBUTE X_CORE_INFO OF bd_222a_psr_aclk_0_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2024.1.2";
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE OF bd_222a_psr_aclk_0_arch : ARCHITECTURE IS "bd_222a_psr_aclk_0,proc_sys_reset,{}";
|
||||
ATTRIBUTE CORE_GENERATION_INFO : STRING;
|
||||
ATTRIBUTE CORE_GENERATION_INFO OF bd_222a_psr_aclk_0_arch: ARCHITECTURE IS "bd_222a_psr_aclk_0,proc_sys_reset,{x_ipProduct=Vivado 2024.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=15,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=1,C_EXT_RESET_HIGH=0,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}";
|
||||
ATTRIBUTE CORE_GENERATION_INFO OF bd_222a_psr_aclk_0_arch: ARCHITECTURE IS "bd_222a_psr_aclk_0,proc_sys_reset,{x_ipProduct=Vivado 2024.1.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=15,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=1,C_EXT_RESET_HIGH=0,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}";
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF aux_reset_in: SIGNAL IS "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
|
||||
+1
-1
@@ -69,7 +69,7 @@
|
||||
"OUTPUTDIR": [ { "value": "." } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../../../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2024.1" } ],
|
||||
"SWVERSION": [ { "value": "2024.1.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
|
||||
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Reference in New Issue
Block a user