josh/brd_cx9261a
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fix:upgrade ips,修改ip repo中ip的makefile,原来的makefile会导致windows上编译失败

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josh
2024-11-03 16:12:11 +08:00
parent decfa6f93e
commit b04b8ee4cc
927 changed files with 1676701 additions and 1475592 deletions
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cx9261a_demo_cmos_20240513/project_fix_dac.xpr
+9 -13
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@@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2024.1 (64-bit) -->
<!-- Product Version: Vivado v2024.1.2 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. -->
@@ -67,13 +67,13 @@
<Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/>
<Option Name="WTXSimExportSim" Val="45"/>
<Option Name="WTModelSimExportSim" Val="45"/>
<Option Name="WTQuestaExportSim" Val="45"/>
<Option Name="WTXSimExportSim" Val="46"/>
<Option Name="WTModelSimExportSim" Val="46"/>
<Option Name="WTQuestaExportSim" Val="46"/>
<Option Name="WTIesExportSim" Val="39"/>
<Option Name="WTVcsExportSim" Val="45"/>
<Option Name="WTRivieraExportSim" Val="45"/>
<Option Name="WTActivehdlExportSim" Val="45"/>
<Option Name="WTVcsExportSim" Val="46"/>
<Option Name="WTRivieraExportSim" Val="46"/>
<Option Name="WTActivehdlExportSim" Val="46"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/>
@@ -637,9 +637,7 @@
</Run>
<Run Id="cx9261a_fifo_synth_1" Type="Ft3:Synth" SrcSet="cx9261a_fifo" Part="xc7z045ffg900-2" ConstrsSet="cx9261a_fifo" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/cx9261a_fifo_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/cx9261a_fifo_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/cx9261a_fifo_synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -839,9 +837,7 @@
</Run>
<Run Id="cx9261a_fifo_impl_1" Type="Ft2:EntireDesign" Part="xc7z045ffg900-2" ConstrsSet="cx9261a_fifo" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="cx9261a_fifo_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/cx9261a_fifo_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/cx9261a_fifo_impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>