From b8dda6c20b7769dab4df7aacd629769f6c871cb5 Mon Sep 17 00:00:00 2001 From: Josh Gao Date: Mon, 4 Nov 2024 15:07:16 +0800 Subject: [PATCH] =?UTF-8?q?fix:=20=E4=BF=AE=E6=94=B9spi=E6=97=B6=E9=92=9F?= =?UTF-8?q?=E9=A2=91=E7=8E=87=E5=92=8C=E6=97=B6=E9=92=9F=E6=BA=90,?= =?UTF-8?q?=E4=BF=AE=E6=94=B9=E8=B7=B3=E9=A2=91=E6=8E=A7=E5=88=B6=E6=97=B6?= =?UTF-8?q?=E9=92=9F=E6=BA=90,=E4=BF=AE=E6=94=B9=E8=B7=B3=E9=A2=91?= =?UTF-8?q?=E9=80=BB=E8=BE=91?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- zc706_cx9261a_demo/system_top.xsa | 4 +- .../source_zc706_cx9261a/hwconfig.c | 7 ++- .../impl_1/system_top.bit | 2 +- .../system_bd_auto_pc_0.xci | 6 +-- .../system_bd_axi_spi_engine_0_0.xci | 8 ++-- .../system_bd_processing_system7_0_0.xci | 18 ++++---- .../system_bd_rst_ps7_50M_0.xci | 2 +- .../system_bd_spi_engine_execution_0_1.xci | 4 +- .../system_bd_system_ila_0_0.xci | 4 +- .../system_bd_xadc_wiz_0_0.xci | 4 +- .../ip/system_bd_xbar_0/system_bd_xbar_0.xci | 12 ++--- .../sources_1/bd/system_bd/system_bd.bd | 43 +++++++++++++++--- .../sources_1/bd/system_bd/ui/bd_c6d0cb12.ui | 35 ++++++++------- .../sources_1/new/system_top.v | 6 ++- zc706_cx9261a_demo/zc706_cx9261a_demo.xpr | 44 ++++++++++++++++--- 15 files changed, 134 insertions(+), 65 deletions(-) diff --git a/zc706_cx9261a_demo/system_top.xsa b/zc706_cx9261a_demo/system_top.xsa index 0b4c889..8424355 100644 --- a/zc706_cx9261a_demo/system_top.xsa +++ b/zc706_cx9261a_demo/system_top.xsa @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:9de8cb9f1f7a377187b4f5664e3ff046cb92eee1a48b27427c11f8568eb15910 -size 1325688 +oid sha256:aad93d563329cbe830dceb62fc70ead9bce63b7fd12abed7508be1ef250e7df6 +size 1305775 diff --git a/zc706_cx9261a_demo/vitis_classic_autobuild/source_zc706_cx9261a/hwconfig.c b/zc706_cx9261a_demo/vitis_classic_autobuild/source_zc706_cx9261a/hwconfig.c index ae98d80..46f40a6 100644 --- a/zc706_cx9261a_demo/vitis_classic_autobuild/source_zc706_cx9261a/hwconfig.c +++ b/zc706_cx9261a_demo/vitis_classic_autobuild/source_zc706_cx9261a/hwconfig.c @@ -923,6 +923,7 @@ int32_t Hardware_Init(void) static int hop_cnt = 0; static int next_pll_index = 2; static double curr_freq; + static double hop_freq = MIN_FREQ + FREQ_SEP; static double next_freq = MIN_FREQ; @@ -943,7 +944,11 @@ int32_t Hardware_Init(void) } else { - next_freq = (curr_freq + FREQ_SEP > MAX_FREQ) ? MIN_FREQ : curr_freq + FREQ_SEP; + hop_freq += FREQ_SEP; + if( hop_freq > MAX_FREQ){ + hop_freq = MIN_FREQ + FREQ_SEP; + } + next_freq = hop_freq; } if (next_pll_index == 2) diff --git a/zc706_cx9261a_demo/zc706_cx9261a_demo.runs/impl_1/system_top.bit b/zc706_cx9261a_demo/zc706_cx9261a_demo.runs/impl_1/system_top.bit index cd13bed..c0751bc 100644 --- a/zc706_cx9261a_demo/zc706_cx9261a_demo.runs/impl_1/system_top.bit +++ b/zc706_cx9261a_demo/zc706_cx9261a_demo.runs/impl_1/system_top.bit @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:a40b5c6b29e751788655d2add28cb7460dad88366973e67990e333946d3a538b +oid sha256:6e42165c34d3b446b422cb5136ad47b7820d80d3aa318d6398905915833fa32c size 13321512 diff --git a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_auto_pc_0/system_bd_auto_pc_0.xci b/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_auto_pc_0/system_bd_auto_pc_0.xci index c9173b7..ce372b9 100644 --- a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_auto_pc_0/system_bd_auto_pc_0.xci +++ b/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_auto_pc_0/system_bd_auto_pc_0.xci @@ -135,7 +135,7 @@ "parameters": { "DATA_WIDTH": [ { "value": "32", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "PROTOCOL": [ { "value": "AXI3", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "FREQ_HZ": [ { "value": "5e+07", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "ID_WIDTH": [ { "value": "12", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "ADDR_WIDTH": [ { "value": "32", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], @@ -213,7 +213,7 @@ "parameters": { "DATA_WIDTH": [ { "value": "32", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "PROTOCOL": [ { "value": "AXI4LITE", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "FREQ_HZ": [ { "value": "5e+07", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "ID_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "ADDR_WIDTH": [ { "value": "32", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], @@ -272,7 +272,7 @@ "parameters": { "ASSOCIATED_BUSIF": [ { "value": "S_AXI:M_AXI", "value_src": "constant", "value_permission": "bd", "usage": "all" } ], "ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ], - "FREQ_HZ": [ { "value": "5e+07", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ], + "FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ], "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], "CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], diff --git a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0.xci b/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0.xci index c400d54..a481d13 100644 --- a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0.xci +++ b/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0.xci @@ -117,7 +117,7 @@ "parameters": { "DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], - "FREQ_HZ": [ { "value": "5e+07", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "ADDR_WIDTH": [ { "value": "16", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], @@ -225,10 +225,10 @@ "parameters": { "ASSOCIATED_BUSIF": [ { "value": "spi_engine_ctrl", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ], "ASSOCIATED_RESET": [ { "value": "spi_resetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ], - "FREQ_HZ": [ { "value": "2e+08", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], - "CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK1", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] }, @@ -255,7 +255,7 @@ "parameters": { "ASSOCIATED_BUSIF": [ { "value": "spi_engine_offload_ctrl0:s_axi", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ], "ASSOCIATED_RESET": [ { "value": "s_axi_aresetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ], - "FREQ_HZ": [ { "value": "5e+07", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], "CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], diff --git a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_processing_system7_0_0/system_bd_processing_system7_0_0.xci b/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_processing_system7_0_0/system_bd_processing_system7_0_0.xci index bcb02bd..650a8b6 100644 --- a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_processing_system7_0_0/system_bd_processing_system7_0_0.xci +++ b/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_processing_system7_0_0/system_bd_processing_system7_0_0.xci @@ -137,7 +137,7 @@ "PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ": [ { "value": "133.333333", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], "PCW_PCAP_PERIPHERAL_FREQMHZ": [ { "value": "200", "resolve_type": "user", "format": "float", "usage": "all" } ], "PCW_TPIU_PERIPHERAL_FREQMHZ": [ { "value": "200", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], - "PCW_FPGA0_PERIPHERAL_FREQMHZ": [ { "value": "50", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_FPGA0_PERIPHERAL_FREQMHZ": [ { "value": "100", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "PCW_FPGA1_PERIPHERAL_FREQMHZ": [ { "value": "200", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "PCW_FPGA2_PERIPHERAL_FREQMHZ": [ { "value": "50", "resolve_type": "user", "format": "float", "usage": "all" } ], "PCW_FPGA3_PERIPHERAL_FREQMHZ": [ { "value": "50", "resolve_type": "user", "format": "float", "usage": "all" } ], @@ -161,7 +161,7 @@ "PCW_ACT_TTC_PERIPHERAL_FREQMHZ": [ { "value": "50", "resolve_type": "user", "format": "float", "usage": "all" } ], "PCW_ACT_PCAP_PERIPHERAL_FREQMHZ": [ { "value": "200.000000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "PCW_ACT_TPIU_PERIPHERAL_FREQMHZ": [ { "value": "200.000000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], - "PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ": [ { "value": "50.000000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ": [ { "value": "100.000000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ": [ { "value": "200.000000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ": [ { "value": "10.000000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ": [ { "value": "10.000000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], @@ -171,7 +171,7 @@ "PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ": [ { "value": "111.111115", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ": [ { "value": "111.111115", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ": [ { "value": "111.111115", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], - "PCW_CLK0_FREQ": [ { "value": "50000000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_CLK0_FREQ": [ { "value": "100000000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "PCW_CLK1_FREQ": [ { "value": "200000000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "PCW_CLK2_FREQ": [ { "value": "10000000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "PCW_CLK3_FREQ": [ { "value": "10000000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], @@ -189,7 +189,7 @@ "PCW_FCLK1_PERIPHERAL_DIVISOR0": [ { "value": "5", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], "PCW_FCLK2_PERIPHERAL_DIVISOR0": [ { "value": "1", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], "PCW_FCLK3_PERIPHERAL_DIVISOR0": [ { "value": "1", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_FCLK0_PERIPHERAL_DIVISOR1": [ { "value": "4", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_FCLK0_PERIPHERAL_DIVISOR1": [ { "value": "2", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], "PCW_FCLK1_PERIPHERAL_DIVISOR1": [ { "value": "1", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], "PCW_FCLK2_PERIPHERAL_DIVISOR1": [ { "value": "1", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], "PCW_FCLK3_PERIPHERAL_DIVISOR1": [ { "value": "1", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], @@ -255,7 +255,7 @@ "PCW_USE_S_AXI_HP1": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], "PCW_USE_S_AXI_HP2": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], "PCW_USE_S_AXI_HP3": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], - "PCW_M_AXI_GP0_FREQMHZ": [ { "value": "50.0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_M_AXI_GP0_FREQMHZ": [ { "value": "100", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ], "PCW_M_AXI_GP1_FREQMHZ": [ { "value": "10", "value_permission": "bd", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], "PCW_S_AXI_GP0_FREQMHZ": [ { "value": "10", "value_permission": "bd", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], "PCW_S_AXI_GP1_FREQMHZ": [ { "value": "10", "value_permission": "bd", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], @@ -1132,7 +1132,7 @@ "NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "constant", "value_permission": "bd", "usage": "all" } ], "DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], "PROTOCOL": [ { "value": "AXI3", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ], - "FREQ_HZ": [ { "value": "5e+07", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], "ID_WIDTH": [ { "value": "12", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], "ADDR_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], @@ -1205,7 +1205,7 @@ "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", "mode": "master", "parameters": { - "FREQ_HZ": [ { "value": "5e+07", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "FREQ_HZ": [ { "value": "100000000", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "all" } ], "PHASE": [ { "value": "0.000", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ], "CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ], "ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ], @@ -1221,7 +1221,7 @@ "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", "mode": "master", "parameters": { - "FREQ_HZ": [ { "value": "2e+08", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "FREQ_HZ": [ { "value": "200000000", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "all" } ], "PHASE": [ { "value": "0.000", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ], "CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK1", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ], "ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ], @@ -1262,7 +1262,7 @@ "mode": "slave", "parameters": { "ASSOCIATED_BUSIF": [ { "value": "M_AXI_GP0", "value_src": "constant", "value_permission": "bd", "usage": "all" } ], - "FREQ_HZ": [ { "value": "5e+07", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], "PHASE": [ { "value": "0.000", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ], "CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ], "ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ], diff --git a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_rst_ps7_50M_0/system_bd_rst_ps7_50M_0.xci b/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_rst_ps7_50M_0/system_bd_rst_ps7_50M_0.xci index 51efb93..ed7abd2 100644 --- a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_rst_ps7_50M_0/system_bd_rst_ps7_50M_0.xci +++ b/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_rst_ps7_50M_0/system_bd_rst_ps7_50M_0.xci @@ -76,7 +76,7 @@ "mode": "slave", "parameters": { "ASSOCIATED_RESET": [ { "value": "mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset", "value_src": "constant", "value_permission": "bd", "usage": "all" } ], - "FREQ_HZ": [ { "value": "5e+07", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ], + "FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ], "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], "CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], diff --git a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_spi_engine_execution_0_1/system_bd_spi_engine_execution_0_1.xci b/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_spi_engine_execution_0_1/system_bd_spi_engine_execution_0_1.xci index 977333f..c4293f3 100644 --- a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_spi_engine_execution_0_1/system_bd_spi_engine_execution_0_1.xci +++ b/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_spi_engine_execution_0_1/system_bd_spi_engine_execution_0_1.xci @@ -147,10 +147,10 @@ "parameters": { "ASSOCIATED_BUSIF": [ { "value": "spi", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ], "ASSOCIATED_RESET": [ { "value": "resetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ], - "FREQ_HZ": [ { "value": "2e+08", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], - "CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK1", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] }, diff --git a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_system_ila_0_0/system_bd_system_ila_0_0.xci b/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_system_ila_0_0/system_bd_system_ila_0_0.xci index a1a0081..29c664e 100644 --- a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_system_ila_0_0/system_bd_system_ila_0_0.xci +++ b/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_system_ila_0_0/system_bd_system_ila_0_0.xci @@ -3881,10 +3881,10 @@ "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", "mode": "slave", "parameters": { - "FREQ_HZ": [ { "value": "2e+08", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], "PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ], - "CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK1", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ], "ASSOCIATED_BUSIF": [ { "value": "", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ], "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ], "ASSOCIATED_RESET": [ { "value": "", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ], diff --git a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_xadc_wiz_0_0/system_bd_xadc_wiz_0_0.xci b/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_xadc_wiz_0_0/system_bd_xadc_wiz_0_0.xci index ef64bbd..bca0f1d 100644 --- a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_xadc_wiz_0_0/system_bd_xadc_wiz_0_0.xci +++ b/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_xadc_wiz_0_0/system_bd_xadc_wiz_0_0.xci @@ -312,7 +312,7 @@ "parameters": { "DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], - "FREQ_HZ": [ { "value": "5e+07", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "ADDR_WIDTH": [ { "value": "11", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], @@ -369,7 +369,7 @@ "parameters": { "ASSOCIATED_BUSIF": [ { "value": "s_axi_lite:M_AXIS", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ], "ASSOCIATED_RESET": [ { "value": "s_axi_aresetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ], - "FREQ_HZ": [ { "value": "5e+07", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], "CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], diff --git a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_xbar_0/system_bd_xbar_0.xci b/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_xbar_0/system_bd_xbar_0.xci index 535d593..091f4a0 100644 --- a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_xbar_0/system_bd_xbar_0.xci +++ b/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_xbar_0/system_bd_xbar_0.xci @@ -2,7 +2,7 @@ "schema": "xilinx.com:schema:json_instance:1.0", "ip_inst": { "xci_name": "system_bd_xbar_0", - "cell_name": "axi_interconnect_0_upgraded_ipi/xbar", + "cell_name": "axi_interconnect_0/xbar", "component_reference": "xilinx.com:ip:axi_crossbar:2.1", "ip_revision": "33", "gen_directory": "../../../../../../zc706_cx9261a_demo.gen/sources_1/bd/system_bd/ip/system_bd_xbar_0", @@ -1316,7 +1316,7 @@ "parameters": { "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ], - "TYPE": [ { "value": "INTERCONNECT", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ] + "TYPE": [ { "value": "INTERCONNECT", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ] }, "port_maps": { "RST": [ { "physical_name": "aresetn" } ] @@ -1329,7 +1329,7 @@ "parameters": { "ASSOCIATED_BUSIF": [ { "value": "M00_AXI:M01_AXI:M02_AXI:M03_AXI:M04_AXI:M05_AXI:M06_AXI:M07_AXI:M08_AXI:M09_AXI:M10_AXI:M11_AXI:M12_AXI:M13_AXI:M14_AXI:M15_AXI:S00_AXI:S01_AXI:S02_AXI:S03_AXI:S04_AXI:S05_AXI:S06_AXI:S07_AXI:S08_AXI:S09_AXI:S10_AXI:S11_AXI:S12_AXI:S13_AXI:S14_AXI:S15_AXI", "value_src": "constant", "value_permission": "bd", "usage": "all" } ], "ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ], - "FREQ_HZ": [ { "value": "5e+07", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ], + "FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ], "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], "CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], @@ -1347,7 +1347,7 @@ "parameters": { "DATA_WIDTH": [ { "value": "32", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "PROTOCOL": [ { "value": "AXI4LITE", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "FREQ_HZ": [ { "value": "5e+07", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "ID_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "ADDR_WIDTH": [ { "value": "32", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], @@ -1406,7 +1406,7 @@ "parameters": { "DATA_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "PROTOCOL": [ { "value": "AXI4LITE", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "FREQ_HZ": [ { "value": "5e+07", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "ID_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "ADDR_WIDTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "AWUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], @@ -1465,7 +1465,7 @@ "parameters": { "DATA_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "PROTOCOL": [ { "value": "AXI4LITE", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "FREQ_HZ": [ { "value": "5e+07", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "ID_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "ADDR_WIDTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "AWUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], diff --git a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/system_bd.bd b/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/system_bd.bd index c548445..2c5ccd4 100644 --- a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/system_bd.bd +++ b/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/system_bd.bd @@ -1,7 +1,7 @@ { "design": { "design_info": { - "boundary_crc": "0xF1CD24C62BCF098C", + "boundary_crc": "0x1057130E5C906B3B", "device": "xc7z045ffg900-2", "gen_directory": "../../../../zc706_cx9261a_demo.gen/sources_1/bd/system_bd", "name": "system_bd", @@ -313,6 +313,31 @@ "direction": "I", "left": "0", "right": "0" + }, + "ps_clk_100M": { + "type": "clk", + "direction": "O", + "parameters": { + "CLK_DOMAIN": { + "value": "system_bd_processing_system7_0_0_FCLK_CLK0", + "value_src": "default_prop" + }, + "FREQ_HZ": { + "value": "100000000" + }, + "FREQ_TOLERANCE_HZ": { + "value": "0", + "value_src": "default" + }, + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "PHASE": { + "value": "0.000", + "value_src": "default" + } + } } }, "components": { @@ -339,7 +364,7 @@ "value": "10.000000" }, "PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ": { - "value": "50.000000" + "value": "100.000000" }, "PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ": { "value": "200.000000" @@ -399,7 +424,7 @@ "value": "0" }, "PCW_CLK0_FREQ": { - "value": "50000000" + "value": "100000000" }, "PCW_CLK1_FREQ": { "value": "200000000" @@ -479,6 +504,9 @@ "PCW_FCLK_CLK1_BUF": { "value": "TRUE" }, + "PCW_FPGA0_PERIPHERAL_FREQMHZ": { + "value": "100" + }, "PCW_FPGA1_PERIPHERAL_FREQMHZ": { "value": "200" }, @@ -2055,15 +2083,16 @@ "axi_interconnect_0/ACLK", "axi_interconnect_0/S00_ACLK", "axi_interconnect_0/M00_ACLK", - "axi_interconnect_0/M01_ACLK" + "axi_interconnect_0/M01_ACLK", + "ps_clk_100M", + "system_ila_spi/clk", + "axi_spi_engine/spi_clk" ] }, "processing_system7_FCLK_CLK1": { "ports": [ "processing_system7/FCLK_CLK1", - "ps_clk_200M", - "axi_spi_engine/spi_clk", - "system_ila_spi/clk" + "ps_clk_200M" ] }, "processing_system7_FCLK_RESET0_N": { diff --git a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ui/bd_c6d0cb12.ui b/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ui/bd_c6d0cb12.ui index cf2f0e7..0cdfd24 100644 --- a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ui/bd_c6d0cb12.ui +++ b/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ui/bd_c6d0cb12.ui @@ -1,7 +1,7 @@ { "ActiveEmotionalView":"Default View", - "Default View_ScaleFactor":"1.29739", - "Default View_TopLeft":"-372,-135", + "Default View_ScaleFactor":"0.798637", + "Default View_TopLeft":"-490,-19", "ExpandedHierarchyInLayout":"", "guistr":"# # String gsaved with Nlview 7.7.1 2023-07-26 3bc4126617 VDI=43 GEI=38 GUI=JA:21.0 TLS # -string -flagsOSRD @@ -11,6 +11,7 @@ preplace port Vp_Vn -pg 1 -lvl 0 -x -10 -y 590 -defaultsOSRD preplace port spi -pg 1 -lvl 3 -x 1080 -y 930 -defaultsOSRD preplace port port-id_spi_active -pg 1 -lvl 3 -x 1080 -y 70 -defaultsOSRD preplace port port-id_ps_clk_200M -pg 1 -lvl 3 -x 1080 -y 190 -defaultsOSRD +preplace port port-id_ps_clk_100M -pg 1 -lvl 3 -x 1080 -y 0 -defaultsOSRD preplace portBus gpio_i -pg 1 -lvl 3 -x 1080 -y 90 -defaultsOSRD -right preplace portBus gpio_o -pg 1 -lvl 3 -x 1080 -y 110 -defaultsOSRD preplace portBus gpio_t -pg 1 -lvl 3 -x 1080 -y 130 -defaultsOSRD @@ -23,27 +24,27 @@ preplace inst axi_interconnect_0 -pg 1 -lvl 1 -x 260 -y 740 -defaultsOSRD preplace inst xlconcat_irq -pg 1 -lvl 2 -x 770 -y 420 -defaultsOSRD -orient R180 preplace inst system_management -pg 1 -lvl 2 -x 770 -y 600 -defaultsOSRD preplace inst system_ila_spi -pg 1 -lvl 2 -x 770 -y 90 -defaultsOSRD -preplace netloc GPIO_I_0_1 1 1 2 570 710 970 -preplace netloc axi_spi_engine_active 1 1 2 580J 760 1010 +preplace netloc GPIO_I_0_1 1 1 2 580 490 980 +preplace netloc axi_spi_engine_active 1 1 2 570J 760 1020 preplace netloc axi_spi_engine_irq 1 1 2 N 970 950 -preplace netloc processing_system7_FCLK_CLK0 1 0 2 20 10 590 -preplace netloc processing_system7_FCLK_CLK1 1 0 3 10 570 490J 730 1030J -preplace netloc processing_system7_FCLK_RESET0_N 1 1 1 560 250n -preplace netloc processing_system7_GPIO_O 1 1 2 530J 720 990J -preplace netloc processing_system7_GPIO_T 1 1 2 510J 750 1020J +preplace netloc probe1_0_1 1 0 2 10J 0 500J +preplace netloc processing_system7_FCLK_CLK0 1 0 3 20 10 590 710 970 +preplace netloc processing_system7_FCLK_RESET0_N 1 1 1 550 250n +preplace netloc processing_system7_GPIO_O 1 1 2 540J 720 1000J +preplace netloc processing_system7_GPIO_T 1 1 2 520J 750 1040J +preplace netloc rst_ps7_50M_peripheral_aresetn1 1 0 3 40 580 510 740 990 preplace netloc system_management_ip2intc_irpt 1 2 1 960 410n preplace netloc xlconcat_irq_dout 1 0 2 50 420 N -preplace netloc rst_ps7_50M_peripheral_aresetn1 1 0 3 30 580 480 740 980 -preplace netloc probe1_0_1 1 0 2 10J 0 510J +preplace netloc processing_system7_FCLK_CLK1 1 1 2 530 730 1030J preplace netloc Vp_Vn_0_1 1 0 2 NJ 590 NJ preplace netloc axi_interconnect_0_M00_AXI 1 0 2 50 600 470 -preplace netloc axi_interconnect_0_M01_AXI 1 1 1 500 570n -preplace netloc axi_spi_engine_spi 1 1 2 550J 930 NJ -preplace netloc processing_system7_DDR 1 1 2 520J 0 1000 -preplace netloc processing_system7_FIXED_IO 1 1 2 540J 490 1000 -preplace netloc processing_system7_M_AXI_GP0 1 0 2 40 390 470 +preplace netloc axi_interconnect_0_M01_AXI 1 1 1 480 570n +preplace netloc axi_spi_engine_spi 1 1 2 560J 930 NJ +preplace netloc processing_system7_DDR 1 1 2 480J -10 1010 +preplace netloc processing_system7_FIXED_IO 1 1 2 530J 0 960 +preplace netloc processing_system7_M_AXI_GP0 1 0 2 30 390 480 levelinfo -pg 1 -10 260 770 1080 -pagesize -pg 1 -db -bbox -sgen -170 -10 1320 1130 +pagesize -pg 1 -db -bbox -sgen -170 -20 1320 1130 " } { diff --git a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/new/system_top.v b/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/new/system_top.v index f85e511..94e6498 100644 --- a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/new/system_top.v +++ b/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/new/system_top.v @@ -143,6 +143,7 @@ assign cx9261a_spi_mosi = spi_sdo_t ? 1'bz : spi_sdo; assign spi_sdi = spi_three_wire ? cx9261a_spi_mosi : cx9261a_spi_miso; // ps clock +wire ps_clk_100M; wire ps_clk_200M; wire ps_rstn; @@ -192,6 +193,7 @@ system_bd_wrapper system_bd .spi_active (spi_active ), // output spi_active // ps clock + .ps_clk_100M (ps_clk_100M ), // output ps_clk_100M .ps_clk_200M (ps_clk_200M ), // output ps_clk_200M .ps_rstn (ps_rstn ), // output ps_rstn @@ -416,7 +418,7 @@ reg hop_trig_d = 'b0; assign hop_flag = hop_flag_buf; -always @(posedge ps_clk_200M or negedge ps_rstn) begin +always @(posedge ps_clk_100M or negedge ps_rstn) begin if (!ps_rstn) begin hop_cnt <= 'b0; hop_flag_buf <= 'b0; @@ -441,7 +443,7 @@ end //////////////////////////////////////////////////////////////////////////////// vio_hop u_vio_hop ( - .clk (sys_clk_64M), // input wire clk + .clk (ps_clk_100M), // input wire clk .probe_out0 (hop_inter ), // output wire [31 : 0] probe_out0 .probe_out1 (hop_en ), // output wire [0 : 0] probe_out1 .probe_out2 (hop_trig ) // output wire [0 : 0] probe_out2 diff --git a/zc706_cx9261a_demo/zc706_cx9261a_demo.xpr b/zc706_cx9261a_demo/zc706_cx9261a_demo.xpr index 6839ac8..8e4f83a 100644 --- a/zc706_cx9261a_demo/zc706_cx9261a_demo.xpr +++ b/zc706_cx9261a_demo/zc706_cx9261a_demo.xpr @@ -97,6 +97,9 @@ + + + @@ -485,6 +488,12 @@