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upgrade to 2024.1.2; add hop signal to spi ila (#5); change hop control clock; add async clock domain

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This commit is contained in:
josh
2025-05-23 10:57:27 +08:00
parent 40a1fbd197
commit d3f2a27299
21 changed files with 335 additions and 499 deletions
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zc706_cx9261a_demo/system_top.xsa
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zc706_cx9261a_demo/zc706_cx9261a_demo.runs/impl_1/debug_nets.ltx
+70 -170
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@@ -2131,7 +2131,7 @@
"portIndex": 1,
"nets": [
{
"name": "system_bd/system_bd_i/system_ila_spi/inst/SLOT_0_SPI_ENGINE_sclk_1",
"name": "system_bd/system_bd_i/system_ila_spi/inst/probe1_1",
"isBus": false
}
]
@@ -2147,7 +2147,7 @@
"portIndex": 2,
"nets": [
{
"name": "system_bd/system_bd_i/system_ila_spi/inst/SLOT_0_SPI_ENGINE_sdi_1",
"name": "system_bd/system_bd_i/system_ila_spi/inst/SLOT_0_SPI_ENGINE_sclk_1",
"isBus": false
}
]
@@ -2163,7 +2163,7 @@
"portIndex": 3,
"nets": [
{
"name": "system_bd/system_bd_i/system_ila_spi/inst/SLOT_0_SPI_ENGINE_sdo_1",
"name": "system_bd/system_bd_i/system_ila_spi/inst/SLOT_0_SPI_ENGINE_sdi_1",
"isBus": false
}
]
@@ -2179,7 +2179,7 @@
"portIndex": 4,
"nets": [
{
"name": "system_bd/system_bd_i/system_ila_spi/inst/SLOT_0_SPI_ENGINE_sdo_t_1",
"name": "system_bd/system_bd_i/system_ila_spi/inst/SLOT_0_SPI_ENGINE_sdo_1",
"isBus": false
}
]
@@ -2195,7 +2195,7 @@
"portIndex": 5,
"nets": [
{
"name": "system_bd/system_bd_i/system_ila_spi/inst/SLOT_0_SPI_ENGINE_three_wire_1",
"name": "system_bd/system_bd_i/system_ila_spi/inst/SLOT_0_SPI_ENGINE_sdo_t_1",
"isBus": false
}
]
@@ -2209,6 +2209,22 @@
"leftIndex": 0,
"rightIndex": 0,
"portIndex": 6,
"nets": [
{
"name": "system_bd/system_bd_i/system_ila_spi/inst/SLOT_0_SPI_ENGINE_three_wire_1",
"isBus": false
}
]
},
{
"name": "probe7",
"id": 74,
"type": "DATA_TRIGGER",
"direction": "IN",
"isVector": false,
"leftIndex": 0,
"rightIndex": 0,
"portIndex": 7,
"nets": [
{
"name": "system_bd/system_bd_i/system_ila_spi/inst/SLOT_0_SPI_ENGINE_cs_1",
@@ -2226,23 +2242,14 @@
{
"logical_port": "cs",
"physical_pin": {
"id": 73,
"name": "probe6",
"id": 74,
"name": "probe7",
"leftBit": 0,
"width": 1
}
},
{
"logical_port": "sclk",
"physical_pin": {
"id": 68,
"name": "probe1",
"leftBit": 0,
"width": 1
}
},
{
"logical_port": "sdi",
"physical_pin": {
"id": 69,
"name": "probe2",
@@ -2251,7 +2258,7 @@
}
},
{
"logical_port": "sdo",
"logical_port": "sdi",
"physical_pin": {
"id": 70,
"name": "probe3",
@@ -2260,7 +2267,7 @@
}
},
{
"logical_port": "sdo_t",
"logical_port": "sdo",
"physical_pin": {
"id": 71,
"name": "probe4",
@@ -2269,13 +2276,22 @@
}
},
{
"logical_port": "three_wire",
"logical_port": "sdo_t",
"physical_pin": {
"id": 72,
"name": "probe5",
"leftBit": 0,
"width": 1
}
},
{
"logical_port": "three_wire",
"physical_pin": {
"id": 73,
"name": "probe6",
"leftBit": 0,
"width": 1
}
}
]
}
@@ -2296,6 +2312,22 @@
}
}
]
},
{
"name": "probe1",
"connectedBus": "hop_signal",
"protocol": "PROBE",
"port_maps": [
{
"logical_port": "probe1",
"physical_pin": {
"id": 68,
"name": "probe1",
"leftBit": 0,
"width": 1
}
}
]
}
]
},
@@ -2313,7 +2345,7 @@
"pins": [
{
"name": "probe0",
"id": 74,
"id": 75,
"type": "DATA_TRIGGER",
"direction": "IN",
"isVector": false,
@@ -2329,7 +2361,7 @@
},
{
"name": "probe1",
"id": 75,
"id": 76,
"type": "DATA_TRIGGER",
"direction": "IN",
"isVector": true,
@@ -2395,7 +2427,7 @@
},
{
"name": "probe2",
"id": 76,
"id": 77,
"type": "DATA_TRIGGER",
"direction": "IN",
"isVector": true,
@@ -2461,7 +2493,7 @@
},
{
"name": "probe3",
"id": 77,
"id": 78,
"type": "DATA_TRIGGER",
"direction": "IN",
"isVector": true,
@@ -2527,7 +2559,7 @@
},
{
"name": "probe4",
"id": 78,
"id": 79,
"type": "DATA_TRIGGER",
"direction": "IN",
"isVector": true,
@@ -2590,138 +2622,6 @@
]
}
]
},
{
"name": "probe5",
"id": 79,
"type": "DATA_TRIGGER",
"direction": "IN",
"isVector": true,
"leftIndex": 0,
"rightIndex": 15,
"portIndex": 5,
"nets": [
{
"name": "rx2_data_i",
"isBus": true,
"subnets": [
{
"name": "rx2_data_i[15]"
},
{
"name": "rx2_data_i[14]"
},
{
"name": "rx2_data_i[13]"
},
{
"name": "rx2_data_i[12]"
},
{
"name": "rx2_data_i[11]"
},
{
"name": "rx2_data_i[10]"
},
{
"name": "rx2_data_i[9]"
},
{
"name": "rx2_data_i[8]"
},
{
"name": "rx2_data_i[7]"
},
{
"name": "rx2_data_i[6]"
},
{
"name": "rx2_data_i[5]"
},
{
"name": "rx2_data_i[4]"
},
{
"name": "rx2_data_i[3]"
},
{
"name": "rx2_data_i[2]"
},
{
"name": "rx2_data_i[1]"
},
{
"name": "rx2_data_i[0]"
}
]
}
]
},
{
"name": "probe6",
"id": 80,
"type": "DATA_TRIGGER",
"direction": "IN",
"isVector": true,
"leftIndex": 0,
"rightIndex": 15,
"portIndex": 6,
"nets": [
{
"name": "rx2_data_q",
"isBus": true,
"subnets": [
{
"name": "rx2_data_q[15]"
},
{
"name": "rx2_data_q[14]"
},
{
"name": "rx2_data_q[13]"
},
{
"name": "rx2_data_q[12]"
},
{
"name": "rx2_data_q[11]"
},
{
"name": "rx2_data_q[10]"
},
{
"name": "rx2_data_q[9]"
},
{
"name": "rx2_data_q[8]"
},
{
"name": "rx2_data_q[7]"
},
{
"name": "rx2_data_q[6]"
},
{
"name": "rx2_data_q[5]"
},
{
"name": "rx2_data_q[4]"
},
{
"name": "rx2_data_q[3]"
},
{
"name": "rx2_data_q[2]"
},
{
"name": "rx2_data_q[1]"
},
{
"name": "rx2_data_q[0]"
}
]
}
]
}
]
},
@@ -2739,7 +2639,7 @@
"pins": [
{
"name": "probe_in0",
"id": 81,
"id": 80,
"type": "DATA",
"direction": "IN",
"isVector": true,
@@ -2772,7 +2672,7 @@
},
{
"name": "probe_in1",
"id": 82,
"id": 81,
"type": "DATA",
"direction": "IN",
"isVector": true,
@@ -2805,7 +2705,7 @@
},
{
"name": "probe_in2",
"id": 83,
"id": 82,
"type": "DATA",
"direction": "IN",
"isVector": true,
@@ -2838,7 +2738,7 @@
},
{
"name": "probe_out0",
"id": 84,
"id": 83,
"type": "DATA",
"direction": "OUT",
"isVector": true,
@@ -2871,7 +2771,7 @@
},
{
"name": "probe_out1",
"id": 85,
"id": 84,
"type": "DATA",
"direction": "OUT",
"isVector": true,
@@ -2904,7 +2804,7 @@
},
{
"name": "probe_out2",
"id": 86,
"id": 85,
"type": "DATA",
"direction": "OUT",
"isVector": true,
@@ -2951,7 +2851,7 @@
"pins": [
{
"name": "probe_out0",
"id": 87,
"id": 86,
"type": "DATA",
"direction": "OUT",
"isVector": true,
@@ -3065,7 +2965,7 @@
},
{
"name": "probe_out1",
"id": 88,
"id": 87,
"type": "DATA",
"direction": "OUT",
"isVector": false,
@@ -3081,7 +2981,7 @@
},
{
"name": "probe_out2",
"id": 89,
"id": 88,
"type": "DATA",
"direction": "OUT",
"isVector": false,
@@ -3111,7 +3011,7 @@
"pins": [
{
"name": "probe_out0",
"id": 90,
"id": 89,
"type": "DATA",
"direction": "OUT",
"isVector": true,
@@ -3135,7 +3035,7 @@
},
{
"name": "probe_out1",
"id": 91,
"id": 90,
"type": "DATA",
"direction": "OUT",
"isVector": false,
@@ -3151,7 +3051,7 @@
},
{
"name": "probe_out2",
"id": 92,
"id": 91,
"type": "DATA",
"direction": "OUT",
"isVector": true,
@@ -3265,7 +3165,7 @@
},
{
"name": "probe_out3",
"id": 93,
"id": 92,
"type": "DATA",
"direction": "OUT",
"isVector": true,
@@ -3289,7 +3189,7 @@
},
{
"name": "probe_out4",
"id": 94,
"id": 93,
"type": "DATA",
"direction": "OUT",
"isVector": true,
zc706_cx9261a_demo/zc706_cx9261a_demo.runs/impl_1/system_top.bit
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zc706_cx9261a_demo/zc706_cx9261a_demo.runs/impl_1/system_top.ltx
+70 -170
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@@ -2131,7 +2131,7 @@
"portIndex": 1,
"nets": [
{
"name": "system_bd/system_bd_i/system_ila_spi/inst/SLOT_0_SPI_ENGINE_sclk_1",
"name": "system_bd/system_bd_i/system_ila_spi/inst/probe1_1",
"isBus": false
}
]
@@ -2147,7 +2147,7 @@
"portIndex": 2,
"nets": [
{
"name": "system_bd/system_bd_i/system_ila_spi/inst/SLOT_0_SPI_ENGINE_sdi_1",
"name": "system_bd/system_bd_i/system_ila_spi/inst/SLOT_0_SPI_ENGINE_sclk_1",
"isBus": false
}
]
@@ -2163,7 +2163,7 @@
"portIndex": 3,
"nets": [
{
"name": "system_bd/system_bd_i/system_ila_spi/inst/SLOT_0_SPI_ENGINE_sdo_1",
"name": "system_bd/system_bd_i/system_ila_spi/inst/SLOT_0_SPI_ENGINE_sdi_1",
"isBus": false
}
]
@@ -2179,7 +2179,7 @@
"portIndex": 4,
"nets": [
{
"name": "system_bd/system_bd_i/system_ila_spi/inst/SLOT_0_SPI_ENGINE_sdo_t_1",
"name": "system_bd/system_bd_i/system_ila_spi/inst/SLOT_0_SPI_ENGINE_sdo_1",
"isBus": false
}
]
@@ -2195,7 +2195,7 @@
"portIndex": 5,
"nets": [
{
"name": "system_bd/system_bd_i/system_ila_spi/inst/SLOT_0_SPI_ENGINE_three_wire_1",
"name": "system_bd/system_bd_i/system_ila_spi/inst/SLOT_0_SPI_ENGINE_sdo_t_1",
"isBus": false
}
]
@@ -2209,6 +2209,22 @@
"leftIndex": 0,
"rightIndex": 0,
"portIndex": 6,
"nets": [
{
"name": "system_bd/system_bd_i/system_ila_spi/inst/SLOT_0_SPI_ENGINE_three_wire_1",
"isBus": false
}
]
},
{
"name": "probe7",
"id": 74,
"type": "DATA_TRIGGER",
"direction": "IN",
"isVector": false,
"leftIndex": 0,
"rightIndex": 0,
"portIndex": 7,
"nets": [
{
"name": "system_bd/system_bd_i/system_ila_spi/inst/SLOT_0_SPI_ENGINE_cs_1",
@@ -2226,23 +2242,14 @@
{
"logical_port": "cs",
"physical_pin": {
"id": 73,
"name": "probe6",
"id": 74,
"name": "probe7",
"leftBit": 0,
"width": 1
}
},
{
"logical_port": "sclk",
"physical_pin": {
"id": 68,
"name": "probe1",
"leftBit": 0,
"width": 1
}
},
{
"logical_port": "sdi",
"physical_pin": {
"id": 69,
"name": "probe2",
@@ -2251,7 +2258,7 @@
}
},
{
"logical_port": "sdo",
"logical_port": "sdi",
"physical_pin": {
"id": 70,
"name": "probe3",
@@ -2260,7 +2267,7 @@
}
},
{
"logical_port": "sdo_t",
"logical_port": "sdo",
"physical_pin": {
"id": 71,
"name": "probe4",
@@ -2269,13 +2276,22 @@
}
},
{
"logical_port": "three_wire",
"logical_port": "sdo_t",
"physical_pin": {
"id": 72,
"name": "probe5",
"leftBit": 0,
"width": 1
}
},
{
"logical_port": "three_wire",
"physical_pin": {
"id": 73,
"name": "probe6",
"leftBit": 0,
"width": 1
}
}
]
}
@@ -2296,6 +2312,22 @@
}
}
]
},
{
"name": "probe1",
"connectedBus": "hop_signal",
"protocol": "PROBE",
"port_maps": [
{
"logical_port": "probe1",
"physical_pin": {
"id": 68,
"name": "probe1",
"leftBit": 0,
"width": 1
}
}
]
}
]
},
@@ -2313,7 +2345,7 @@
"pins": [
{
"name": "probe0",
"id": 74,
"id": 75,
"type": "DATA_TRIGGER",
"direction": "IN",
"isVector": false,
@@ -2329,7 +2361,7 @@
},
{
"name": "probe1",
"id": 75,
"id": 76,
"type": "DATA_TRIGGER",
"direction": "IN",
"isVector": true,
@@ -2395,7 +2427,7 @@
},
{
"name": "probe2",
"id": 76,
"id": 77,
"type": "DATA_TRIGGER",
"direction": "IN",
"isVector": true,
@@ -2461,7 +2493,7 @@
},
{
"name": "probe3",
"id": 77,
"id": 78,
"type": "DATA_TRIGGER",
"direction": "IN",
"isVector": true,
@@ -2527,7 +2559,7 @@
},
{
"name": "probe4",
"id": 78,
"id": 79,
"type": "DATA_TRIGGER",
"direction": "IN",
"isVector": true,
@@ -2590,138 +2622,6 @@
]
}
]
},
{
"name": "probe5",
"id": 79,
"type": "DATA_TRIGGER",
"direction": "IN",
"isVector": true,
"leftIndex": 0,
"rightIndex": 15,
"portIndex": 5,
"nets": [
{
"name": "rx2_data_i",
"isBus": true,
"subnets": [
{
"name": "rx2_data_i[15]"
},
{
"name": "rx2_data_i[14]"
},
{
"name": "rx2_data_i[13]"
},
{
"name": "rx2_data_i[12]"
},
{
"name": "rx2_data_i[11]"
},
{
"name": "rx2_data_i[10]"
},
{
"name": "rx2_data_i[9]"
},
{
"name": "rx2_data_i[8]"
},
{
"name": "rx2_data_i[7]"
},
{
"name": "rx2_data_i[6]"
},
{
"name": "rx2_data_i[5]"
},
{
"name": "rx2_data_i[4]"
},
{
"name": "rx2_data_i[3]"
},
{
"name": "rx2_data_i[2]"
},
{
"name": "rx2_data_i[1]"
},
{
"name": "rx2_data_i[0]"
}
]
}
]
},
{
"name": "probe6",
"id": 80,
"type": "DATA_TRIGGER",
"direction": "IN",
"isVector": true,
"leftIndex": 0,
"rightIndex": 15,
"portIndex": 6,
"nets": [
{
"name": "rx2_data_q",
"isBus": true,
"subnets": [
{
"name": "rx2_data_q[15]"
},
{
"name": "rx2_data_q[14]"
},
{
"name": "rx2_data_q[13]"
},
{
"name": "rx2_data_q[12]"
},
{
"name": "rx2_data_q[11]"
},
{
"name": "rx2_data_q[10]"
},
{
"name": "rx2_data_q[9]"
},
{
"name": "rx2_data_q[8]"
},
{
"name": "rx2_data_q[7]"
},
{
"name": "rx2_data_q[6]"
},
{
"name": "rx2_data_q[5]"
},
{
"name": "rx2_data_q[4]"
},
{
"name": "rx2_data_q[3]"
},
{
"name": "rx2_data_q[2]"
},
{
"name": "rx2_data_q[1]"
},
{
"name": "rx2_data_q[0]"
}
]
}
]
}
]
},
@@ -2739,7 +2639,7 @@
"pins": [
{
"name": "probe_in0",
"id": 81,
"id": 80,
"type": "DATA",
"direction": "IN",
"isVector": true,
@@ -2772,7 +2672,7 @@
},
{
"name": "probe_in1",
"id": 82,
"id": 81,
"type": "DATA",
"direction": "IN",
"isVector": true,
@@ -2805,7 +2705,7 @@
},
{
"name": "probe_in2",
"id": 83,
"id": 82,
"type": "DATA",
"direction": "IN",
"isVector": true,
@@ -2838,7 +2738,7 @@
},
{
"name": "probe_out0",
"id": 84,
"id": 83,
"type": "DATA",
"direction": "OUT",
"isVector": true,
@@ -2871,7 +2771,7 @@
},
{
"name": "probe_out1",
"id": 85,
"id": 84,
"type": "DATA",
"direction": "OUT",
"isVector": true,
@@ -2904,7 +2804,7 @@
},
{
"name": "probe_out2",
"id": 86,
"id": 85,
"type": "DATA",
"direction": "OUT",
"isVector": true,
@@ -2951,7 +2851,7 @@
"pins": [
{
"name": "probe_out0",
"id": 87,
"id": 86,
"type": "DATA",
"direction": "OUT",
"isVector": true,
@@ -3065,7 +2965,7 @@
},
{
"name": "probe_out1",
"id": 88,
"id": 87,
"type": "DATA",
"direction": "OUT",
"isVector": false,
@@ -3081,7 +2981,7 @@
},
{
"name": "probe_out2",
"id": 89,
"id": 88,
"type": "DATA",
"direction": "OUT",
"isVector": false,
@@ -3111,7 +3011,7 @@
"pins": [
{
"name": "probe_out0",
"id": 90,
"id": 89,
"type": "DATA",
"direction": "OUT",
"isVector": true,
@@ -3135,7 +3035,7 @@
},
{
"name": "probe_out1",
"id": 91,
"id": 90,
"type": "DATA",
"direction": "OUT",
"isVector": false,
@@ -3151,7 +3051,7 @@
},
{
"name": "probe_out2",
"id": 92,
"id": 91,
"type": "DATA",
"direction": "OUT",
"isVector": true,
@@ -3265,7 +3165,7 @@
},
{
"name": "probe_out3",
"id": 93,
"id": 92,
"type": "DATA",
"direction": "OUT",
"isVector": true,
@@ -3289,7 +3189,7 @@
},
{
"name": "probe_out4",
"id": 94,
"id": 93,
"type": "DATA",
"direction": "OUT",
"isVector": true,
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/constrs_1/new/zc706_cx9261a_demo_physical.xdc
+1 -1
View File
@@ -94,4 +94,4 @@ create_clock -period 6.25 -name RX1_MCLK_IN_N -waveform {0.000 3.125} [get_ports
create_clock -period 6.25 -name RX2_MCLK_IN_P -waveform {0.000 3.125} [get_ports cx9261a_rx2_mclk ]
create_clock -period 6.25 -name RXFB_MCLK_IN -waveform {0.000 3.125} [get_ports cx9261a_rxfb_mclk]
set_clock_groups -asynchronous -group [get_clocks RX1_MCLK_IN_N] -group [get_clocks RX2_MCLK_IN_P] -group [get_clocks RXFB_MCLK_IN]
set_clock_groups -asynchronous -group [get_clocks RX1_MCLK_IN_N] -group [get_clocks RX2_MCLK_IN_P] -group [get_clocks RXFB_MCLK_IN] -group [get_clocks [list clk_fpga_0 clk_fpga_1 ]] -group [get_clocks -of_objects [get_pins u_sys_clk_gen/inst/mmcm_adv_inst/CLKOUT0]]
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_auto_pc_0/system_bd_auto_pc_0.xci
+3 -3
View File
@@ -4,7 +4,7 @@
"xci_name": "system_bd_auto_pc_0",
"cell_name": "axi_interconnect_0/s00_couplers/auto_pc",
"component_reference": "xilinx.com:ip:axi_protocol_converter:2.1",
"ip_revision": "31",
"ip_revision": "32",
"gen_directory": "../../../../../../zc706_cx9261a_demo.gen/sources_1/bd/system_bd/ip/system_bd_auto_pc_0",
"parameters": {
"component_parameters": {
@@ -56,12 +56,12 @@
},
"runtime_parameters": {
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
"IPREVISION": [ { "value": "31" } ],
"IPREVISION": [ { "value": "32" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "../../../../../../zc706_cx9261a_demo.gen/sources_1/bd/system_bd/ip/system_bd_auto_pc_0" } ],
"SELECTEDSIMMODEL": [ { "value": "rtl" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2024.1" } ],
"SWVERSION": [ { "value": "2024.1.2" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
}
},
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_axi_interconnect_0_0/system_bd_axi_interconnect_0_0.xci
+3 -3
View File
@@ -4,7 +4,7 @@
"xci_name": "system_bd_axi_interconnect_0_0",
"cell_name": "axi_interconnect_0",
"component_reference": "xilinx.com:ip:axi_interconnect:2.1",
"ip_revision": "32",
"ip_revision": "33",
"gen_directory": "../../../../../../zc706_cx9261a_demo.gen/sources_1/bd/system_bd/ip/system_bd_axi_interconnect_0_0",
"parameters": {
"component_parameters": {
@@ -340,12 +340,12 @@
},
"runtime_parameters": {
"IPCONTEXT": [ { "value": "IP_Integrator_AppCore" } ],
"IPREVISION": [ { "value": "32" } ],
"IPREVISION": [ { "value": "33" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "../../../../../../zc706_cx9261a_demo.gen/sources_1/bd/system_bd/ip/system_bd_axi_interconnect_0_0" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2024.1" } ],
"SWVERSION": [ { "value": "2024.1.2" } ],
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
}
}
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0.xci
+18 -18
View File
@@ -2,7 +2,7 @@
"schema": "xilinx.com:schema:json_instance:1.0",
"ip_inst": {
"xci_name": "system_bd_axi_spi_engine_0_0",
"cell_name": "axi_spi_engine",
"cell_name": "axi_spi_engine/axi_spi_engine",
"component_reference": "analog.com:user:axi_spi_engine:1.0",
"ip_revision": "1",
"gen_directory": "../../../../../../zc706_cx9261a_demo.gen/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0",
@@ -65,7 +65,7 @@
"OUTPUTDIR": [ { "value": "../../../../../../zc706_cx9261a_demo.gen/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2024.1" } ],
"SWVERSION": [ { "value": "2024.1.2" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
}
},
@@ -116,25 +116,25 @@
"memory_map_ref": "s_axi",
"parameters": {
"DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "5e+07", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ADDR_WIDTH": [ { "value": "16", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_PROT": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_WSTRB": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_BRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_RRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_PROT": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_WSTRB": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_BRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_RRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_READ_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_processing_system7_0_0/system_bd_processing_system7_0_0.xci
+1 -1
View File
@@ -966,7 +966,7 @@
"OUTPUTDIR": [ { "value": "../../../../../../zc706_cx9261a_demo.gen/sources_1/bd/system_bd/ip/system_bd_processing_system7_0_0" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2024.1" } ],
"SWVERSION": [ { "value": "2024.1.2" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
}
},
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_rst_ps7_50M_0/system_bd_rst_ps7_50M_0.xci
+1 -1
View File
@@ -52,7 +52,7 @@
"OUTPUTDIR": [ { "value": "../../../../../../zc706_cx9261a_demo.gen/sources_1/bd/system_bd/ip/system_bd_rst_ps7_50M_0" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2024.1" } ],
"SWVERSION": [ { "value": "2024.1.2" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
}
},
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_spi_engine_execution_0_1/system_bd_spi_engine_execution_0_1.xci
+1 -1
View File
@@ -49,7 +49,7 @@
"OUTPUTDIR": [ { "value": "../../../../../../zc706_cx9261a_demo.gen/sources_1/bd/system_bd/ip/system_bd_spi_engine_execution_0_1" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2024.1" } ],
"SWVERSION": [ { "value": "2024.1.2" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
}
},
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_system_ila_0_0/system_bd_system_ila_0_0.xci
+6 -5
View File
@@ -4,7 +4,7 @@
"xci_name": "system_bd_system_ila_0_0",
"cell_name": "system_ila_spi",
"component_reference": "xilinx.com:ip:system_ila:1.1",
"ip_revision": "17",
"ip_revision": "18",
"gen_directory": "../../../../../../zc706_cx9261a_demo.gen/sources_1/bd/system_bd/ip/system_bd_system_ila_0_0",
"parameters": {
"component_parameters": {
@@ -2571,8 +2571,8 @@
"C_PROBE2_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"C_PROBE1_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"C_PROBE0_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"C_DATA_DEPTH": [ { "value": "1024", "resolve_type": "user", "format": "long", "usage": "all" } ],
"C_NUM_OF_PROBES": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"C_DATA_DEPTH": [ { "value": "32768", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"C_NUM_OF_PROBES": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"C_XLNX_HW_PROBE_INFO": [ { "value": "DEFAULT", "resolve_type": "user", "usage": "all" } ],
"Component_Name": [ { "value": "system_bd_system_ila_0_0", "resolve_type": "user", "usage": "all" } ],
"C_PROBE70_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
@@ -3854,12 +3854,12 @@
},
"runtime_parameters": {
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
"IPREVISION": [ { "value": "17" } ],
"IPREVISION": [ { "value": "18" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "../../../../../../zc706_cx9261a_demo.gen/sources_1/bd/system_bd/ip/system_bd_system_ila_0_0" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2024.1" } ],
"SWVERSION": [ { "value": "2024.1.2" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
}
},
@@ -3867,6 +3867,7 @@
"ports": {
"clk": [ { "direction": "in" } ],
"probe0": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"probe1": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"SLOT_0_SPI_ENGINE_sclk": [ { "direction": "in", "driver_value": "0" } ],
"SLOT_0_SPI_ENGINE_sdo": [ { "direction": "in", "driver_value": "0" } ],
"SLOT_0_SPI_ENGINE_sdo_t": [ { "direction": "in", "driver_value": "0" } ],
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_xadc_wiz_0_0/system_bd_xadc_wiz_0_0.xci
+1 -1
View File
@@ -270,7 +270,7 @@
"OUTPUTDIR": [ { "value": "../../../../../../zc706_cx9261a_demo.gen/sources_1/bd/system_bd/ip/system_bd_xadc_wiz_0_0" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2024.1" } ],
"SWVERSION": [ { "value": "2024.1.2" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
}
},
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_xbar_0/system_bd_xbar_0.xci
+5 -5
View File
@@ -2,9 +2,9 @@
"schema": "xilinx.com:schema:json_instance:1.0",
"ip_inst": {
"xci_name": "system_bd_xbar_0",
"cell_name": "axi_interconnect_0/xbar",
"cell_name": "axi_interconnect_0_upgraded_ipi/xbar",
"component_reference": "xilinx.com:ip:axi_crossbar:2.1",
"ip_revision": "32",
"ip_revision": "33",
"gen_directory": "../../../../../../zc706_cx9261a_demo.gen/sources_1/bd/system_bd/ip/system_bd_xbar_0",
"parameters": {
"component_parameters": {
@@ -1256,12 +1256,12 @@
},
"runtime_parameters": {
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
"IPREVISION": [ { "value": "32" } ],
"IPREVISION": [ { "value": "33" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "../../../../../../zc706_cx9261a_demo.gen/sources_1/bd/system_bd/ip/system_bd_xbar_0" } ],
"SELECTEDSIMMODEL": [ { "value": "rtl" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2024.1" } ],
"SWVERSION": [ { "value": "2024.1.2" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
}
},
@@ -1316,7 +1316,7 @@
"parameters": {
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
"TYPE": [ { "value": "INTERCONNECT", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
"TYPE": [ { "value": "INTERCONNECT", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"RST": [ { "physical_name": "aresetn" } ]
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_xlconcat_0_0/system_bd_xlconcat_0_0.xci
+1 -1
View File
@@ -293,7 +293,7 @@
"OUTPUTDIR": [ { "value": "../../../../../../zc706_cx9261a_demo.gen/sources_1/bd/system_bd/ip/system_bd_xlconcat_0_0" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2024.1" } ],
"SWVERSION": [ { "value": "2024.1.2" } ],
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
}
},
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/system_bd.bd
+43 -12
View File
@@ -1,13 +1,13 @@
{
"design": {
"design_info": {
"boundary_crc": "0xFFC3C3D2D3E28C10",
"boundary_crc": "0xF1CD24C62BCF098C",
"device": "xc7z045ffg900-2",
"gen_directory": "../../../../zc706_cx9261a_demo.gen/sources_1/bd/system_bd",
"name": "system_bd",
"rev_ctrl_bd_flag": "RevCtrlBdOff",
"synth_flow_mode": "Hierarchical",
"tool_version": "2024.1",
"tool_version": "2024.1.2",
"validated": "true"
},
"design_tree": {
@@ -292,6 +292,27 @@
"direction": "O",
"left": "31",
"right": "0"
},
"ps_rstn": {
"type": "rst",
"direction": "O",
"left": "0",
"right": "0",
"parameters": {
"INSERT_VIP": {
"value": "0",
"value_src": "default"
},
"POLARITY": {
"value": "ACTIVE_LOW",
"value_src": "const_prop"
}
}
},
"hop_signal": {
"direction": "I",
"left": "0",
"right": "0"
}
},
"components": {
@@ -1545,7 +1566,7 @@
"components": {
"xbar": {
"vlnv": "xilinx.com:ip:axi_crossbar:2.1",
"ip_revision": "32",
"ip_revision": "33",
"xci_name": "system_bd_xbar_0",
"xci_path": "ip/system_bd_xbar_0/system_bd_xbar_0.xci",
"inst_hier_path": "axi_interconnect_0/xbar",
@@ -1621,7 +1642,7 @@
"components": {
"auto_pc": {
"vlnv": "xilinx.com:ip:axi_protocol_converter:2.1",
"ip_revision": "31",
"ip_revision": "32",
"xci_name": "system_bd_auto_pc_0",
"xci_path": "ip/system_bd_auto_pc_0/system_bd_auto_pc_0.xci",
"inst_hier_path": "axi_interconnect_0/s00_couplers/auto_pc",
@@ -1901,11 +1922,14 @@
},
"system_ila_spi": {
"vlnv": "xilinx.com:ip:system_ila:1.1",
"ip_revision": "17",
"ip_revision": "18",
"xci_name": "system_bd_system_ila_0_0",
"xci_path": "ip/system_bd_system_ila_0_0/system_bd_system_ila_0_0.xci",
"inst_hier_path": "system_ila_spi",
"parameters": {
"C_DATA_DEPTH": {
"value": "32768"
},
"C_MON_TYPE": {
"value": "MIX"
},
@@ -1913,7 +1937,7 @@
"value": "1"
},
"C_NUM_OF_PROBES": {
"value": "1"
"value": "2"
},
"C_PROBE0_TYPE": {
"value": "0"
@@ -2015,17 +2039,23 @@
"xlconcat_irq/In0"
]
},
"probe1_0_1": {
"ports": [
"hop_signal",
"system_ila_spi/probe1"
]
},
"processing_system7_FCLK_CLK0": {
"ports": [
"processing_system7/FCLK_CLK0",
"processing_system7/M_AXI_GP0_ACLK",
"axi_spi_engine/s_axi_aclk",
"rst_ps7_50M/slowest_sync_clk",
"system_management/s_axi_aclk",
"axi_interconnect_0/ACLK",
"axi_interconnect_0/S00_ACLK",
"axi_interconnect_0/M00_ACLK",
"axi_interconnect_0/M01_ACLK",
"rst_ps7_50M/slowest_sync_clk",
"system_management/s_axi_aclk"
"axi_interconnect_0/M01_ACLK"
]
},
"processing_system7_FCLK_CLK1": {
@@ -2054,15 +2084,16 @@
"gpio_t"
]
},
"rst_ps7_50M_peripheral_aresetn": {
"rst_ps7_50M_peripheral_aresetn1": {
"ports": [
"rst_ps7_50M/peripheral_aresetn",
"ps_rstn",
"axi_spi_engine/s_axi_aresetn",
"system_management/s_axi_aresetn",
"axi_interconnect_0/ARESETN",
"axi_interconnect_0/S00_ARESETN",
"axi_interconnect_0/M00_ARESETN",
"axi_interconnect_0/M01_ARESETN",
"system_management/s_axi_aresetn"
"axi_interconnect_0/M01_ARESETN"
]
},
"system_management_ip2intc_irpt": {
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ui/bd_c6d0cb12.ui
+34 -31
View File
@@ -1,46 +1,49 @@
{
"ActiveEmotionalView":"Default View",
"Default View_ScaleFactor":"0.798638",
"Default View_TopLeft":"-601,1",
"Default View_ScaleFactor":"1.29739",
"Default View_TopLeft":"-372,-135",
"ExpandedHierarchyInLayout":"",
"guistr":"# # String gsaved with Nlview 7.7.1 2023-07-26 3bc4126617 VDI=43 GEI=38 GUI=JA:21.0 TLS
# -string -flagsOSRD
preplace port ddr -pg 1 -lvl 3 -x 1040 -y 150 -defaultsOSRD
preplace port fixed_io -pg 1 -lvl 3 -x 1040 -y 170 -defaultsOSRD
preplace port ddr -pg 1 -lvl 3 -x 1080 -y 150 -defaultsOSRD
preplace port fixed_io -pg 1 -lvl 3 -x 1080 -y 170 -defaultsOSRD
preplace port Vp_Vn -pg 1 -lvl 0 -x -10 -y 590 -defaultsOSRD
preplace port spi -pg 1 -lvl 3 -x 1040 -y 930 -defaultsOSRD
preplace port port-id_spi_active -pg 1 -lvl 3 -x 1040 -y 70 -defaultsOSRD
preplace port port-id_ps_clk_200M -pg 1 -lvl 3 -x 1040 -y 190 -defaultsOSRD
preplace portBus gpio_i -pg 1 -lvl 3 -x 1040 -y 90 -defaultsOSRD -right
preplace portBus gpio_o -pg 1 -lvl 3 -x 1040 -y 110 -defaultsOSRD
preplace portBus gpio_t -pg 1 -lvl 3 -x 1040 -y 130 -defaultsOSRD
preplace port spi -pg 1 -lvl 3 -x 1080 -y 930 -defaultsOSRD
preplace port port-id_spi_active -pg 1 -lvl 3 -x 1080 -y 70 -defaultsOSRD
preplace port port-id_ps_clk_200M -pg 1 -lvl 3 -x 1080 -y 190 -defaultsOSRD
preplace portBus gpio_i -pg 1 -lvl 3 -x 1080 -y 90 -defaultsOSRD -right
preplace portBus gpio_o -pg 1 -lvl 3 -x 1080 -y 110 -defaultsOSRD
preplace portBus gpio_t -pg 1 -lvl 3 -x 1080 -y 130 -defaultsOSRD
preplace portBus ps_rstn -pg 1 -lvl 3 -x 1080 -y 310 -defaultsOSRD
preplace portBus hop_signal -pg 1 -lvl 0 -x -10 -y 120 -defaultsOSRD
preplace inst processing_system7 -pg 1 -lvl 1 -x 260 -y 200 -defaultsOSRD
preplace inst axi_spi_engine -pg 1 -lvl 1 -x 260 -y 950 -defaultsOSRD
preplace inst rst_ps7_50M -pg 1 -lvl 2 -x 740 -y 270 -defaultsOSRD
preplace inst rst_ps7_50M -pg 1 -lvl 2 -x 770 -y 270 -defaultsOSRD
preplace inst axi_interconnect_0 -pg 1 -lvl 1 -x 260 -y 740 -defaultsOSRD
preplace inst xlconcat_irq -pg 1 -lvl 2 -x 740 -y 420 -defaultsOSRD -orient R180
preplace inst system_management -pg 1 -lvl 2 -x 740 -y 600 -defaultsOSRD
preplace inst system_ila_spi -pg 1 -lvl 2 -x 740 -y 90 -defaultsOSRD
preplace netloc GPIO_I_0_1 1 1 2 530 490 950
preplace netloc axi_spi_engine_active 1 1 2 560J 750 970
preplace netloc axi_spi_engine_irq 1 1 2 N 970 930
preplace netloc processing_system7_FCLK_CLK0 1 0 2 10 10 480
preplace netloc processing_system7_FCLK_CLK1 1 0 3 20 570 540J 710 1000J
preplace netloc processing_system7_FCLK_RESET0_N 1 1 1 550 250n
preplace netloc processing_system7_GPIO_O 1 1 2 510J 730 980J
preplace netloc processing_system7_GPIO_T 1 1 2 500J 720 990J
preplace netloc rst_ps7_50M_peripheral_aresetn 1 0 3 40 580 490J 740 940
preplace netloc system_management_ip2intc_irpt 1 2 1 920 410n
preplace inst xlconcat_irq -pg 1 -lvl 2 -x 770 -y 420 -defaultsOSRD -orient R180
preplace inst system_management -pg 1 -lvl 2 -x 770 -y 600 -defaultsOSRD
preplace inst system_ila_spi -pg 1 -lvl 2 -x 770 -y 90 -defaultsOSRD
preplace netloc GPIO_I_0_1 1 1 2 570 710 970
preplace netloc axi_spi_engine_active 1 1 2 580J 760 1010
preplace netloc axi_spi_engine_irq 1 1 2 N 970 950
preplace netloc processing_system7_FCLK_CLK0 1 0 2 20 10 590
preplace netloc processing_system7_FCLK_CLK1 1 0 3 10 570 490J 730 1030J
preplace netloc processing_system7_FCLK_RESET0_N 1 1 1 560 250n
preplace netloc processing_system7_GPIO_O 1 1 2 530J 720 990J
preplace netloc processing_system7_GPIO_T 1 1 2 510J 750 1020J
preplace netloc system_management_ip2intc_irpt 1 2 1 960 410n
preplace netloc xlconcat_irq_dout 1 0 2 50 420 N
preplace netloc rst_ps7_50M_peripheral_aresetn1 1 0 3 30 580 480 740 980
preplace netloc probe1_0_1 1 0 2 10J 0 510J
preplace netloc Vp_Vn_0_1 1 0 2 NJ 590 NJ
preplace netloc axi_interconnect_0_M00_AXI 1 0 2 50 600 470
preplace netloc axi_interconnect_0_M01_AXI 1 1 1 550 570n
preplace netloc axi_spi_engine_spi 1 1 2 520J 930 NJ
preplace netloc processing_system7_DDR 1 1 2 490J 10 960
preplace netloc processing_system7_FIXED_IO 1 1 2 NJ 170 N
preplace netloc processing_system7_M_AXI_GP0 1 0 2 30 390 470
levelinfo -pg 1 -10 260 740 1040
pagesize -pg 1 -db -bbox -sgen -110 0 1180 1030
preplace netloc axi_interconnect_0_M01_AXI 1 1 1 500 570n
preplace netloc axi_spi_engine_spi 1 1 2 550J 930 NJ
preplace netloc processing_system7_DDR 1 1 2 520J 0 1000
preplace netloc processing_system7_FIXED_IO 1 1 2 540J 490 1000
preplace netloc processing_system7_M_AXI_GP0 1 0 2 40 390 470
levelinfo -pg 1 -10 260 770 1080
pagesize -pg 1 -db -bbox -sgen -170 -10 1320 1130
"
}
{
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/ip/ila_trx/ila_trx.xci
+9 -11
View File
@@ -2047,15 +2047,15 @@
"C_PROBE9_WIDTH": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"C_PROBE8_WIDTH": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"C_PROBE7_WIDTH": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"C_PROBE6_WIDTH": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"C_PROBE5_WIDTH": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"C_PROBE6_WIDTH": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"C_PROBE5_WIDTH": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"C_PROBE4_WIDTH": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"C_PROBE3_WIDTH": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"C_PROBE2_WIDTH": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"C_PROBE1_WIDTH": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"C_PROBE0_WIDTH": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"C_DATA_DEPTH": [ { "value": "131072", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"C_NUM_OF_PROBES": [ { "value": "7", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"C_NUM_OF_PROBES": [ { "value": "5", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"C_XLNX_HW_PROBE_INFO": [ { "value": "DEFAULT", "resolve_type": "user", "usage": "all" } ],
"Component_Name": [ { "value": "ila_trx", "resolve_type": "user", "usage": "all" } ],
"C_PROBE70_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
@@ -3134,7 +3134,7 @@
"C_SLOT_0_AXI_PROTOCOL": [ { "value": "AXI4", "resolve_type": "generated", "usage": "all" } ],
"C_NUM_MONITOR_SLOTS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_ENABLE_ILA_AXI_MON": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_NUM_OF_PROBES": [ { "value": "7", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_NUM_OF_PROBES": [ { "value": "5", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_DATA_DEPTH": [ { "value": "131072", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_MAJOR_VERSION": [ { "value": "2024", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_MINOR_VERSION": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
@@ -3149,7 +3149,7 @@
"C_RAM_STYLE": [ { "value": "SUBCORE", "usage": "all" } ],
"C_TRIGOUT_EN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_TRIGIN_EN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_SLOT_0_AXIS_TUSER_WIDTH": [ { "value": "16", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
"C_SLOT_0_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
"C_SLOT_0_AXIS_TDEST_WIDTH": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
"C_SLOT_0_AXIS_TID_WIDTH": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
"C_SLOT_0_AXI_ID_WIDTH": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
@@ -3163,8 +3163,8 @@
"C_PROBE2_WIDTH": [ { "value": "16", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
"C_PROBE3_WIDTH": [ { "value": "16", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
"C_PROBE4_WIDTH": [ { "value": "16", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
"C_PROBE5_WIDTH": [ { "value": "16", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
"C_PROBE6_WIDTH": [ { "value": "16", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
"C_PROBE5_WIDTH": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
"C_PROBE6_WIDTH": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
"C_PROBE7_WIDTH": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
"C_PROBE8_WIDTH": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
"C_PROBE9_WIDTH": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
@@ -6265,7 +6265,7 @@
"OUTPUTDIR": [ { "value": "../../../../zc706_cx9261a_demo.gen/sources_1/ip/ila_trx" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "." } ],
"SWVERSION": [ { "value": "2024.1" } ],
"SWVERSION": [ { "value": "2024.1.2" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
}
},
@@ -6276,9 +6276,7 @@
"probe1": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
"probe2": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
"probe3": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
"probe4": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
"probe5": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
"probe6": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ]
"probe4": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ]
},
"interfaces": {
"signal_clock": {
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/ip/vio_hop/vio_hop.xci
+3 -3
View File
@@ -262,7 +262,7 @@
"C_PROBE_OUT3_INIT_VAL": [ { "value": "0x0", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
"C_PROBE_OUT2_INIT_VAL": [ { "value": "0x0", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
"C_PROBE_OUT1_INIT_VAL": [ { "value": "0x0", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
"C_PROBE_OUT0_INIT_VAL": [ { "value": "0x00001388", "value_src": "user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
"C_PROBE_OUT0_INIT_VAL": [ { "value": "0x00002710", "value_src": "user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
"C_PROBE_OUT255_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"C_PROBE_OUT254_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"C_PROBE_OUT253_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
@@ -1316,7 +1316,7 @@
"C_PROBE_OUT253_WIDTH": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
"C_PROBE_OUT254_WIDTH": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
"C_PROBE_OUT255_WIDTH": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
"C_PROBE_OUT0_INIT_VAL": [ { "value": "0x00001388", "resolve_type": "dependent", "format": "bitString", "usage": "all" } ],
"C_PROBE_OUT0_INIT_VAL": [ { "value": "0x00002710", "resolve_type": "dependent", "format": "bitString", "usage": "all" } ],
"C_PROBE_OUT1_INIT_VAL": [ { "value": "0x0", "resolve_type": "dependent", "format": "bitString", "usage": "all" } ],
"C_PROBE_OUT2_INIT_VAL": [ { "value": "0x0", "resolve_type": "dependent", "format": "bitString", "usage": "all" } ],
"C_PROBE_OUT3_INIT_VAL": [ { "value": "0x0", "resolve_type": "dependent", "format": "bitString", "usage": "all" } ],
@@ -1594,7 +1594,7 @@
"OUTPUTDIR": [ { "value": "../../../../zc706_cx9261a_demo.gen/sources_1/ip/vio_hop" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "." } ],
"SWVERSION": [ { "value": "2024.1" } ],
"SWVERSION": [ { "value": "2024.1.2" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
}
},
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/new/system_top.v
+17 -14
View File
@@ -128,13 +128,13 @@ assign gpio_i[15] = hop_flag;
assign gpio_i[31:16] = gpio_o[31:16];
// spi interface
wire spi_sclk ;
wire spi_cs ;
wire spi_sdi ;
wire spi_sdo ;
wire spi_sdo_t ;
wire spi_three_wire;
wire spi_active ;
wire spi_sclk ;
wire spi_cs ;
wire spi_sdi ;
wire spi_sdo ;
wire spi_sdo_t ;
wire spi_three_wire;
wire spi_active ;
// cx9261 - three-wire spi or four-wire spi
assign cx9261a_spi_sclk = spi_sclk;
@@ -143,7 +143,8 @@ assign cx9261a_spi_mosi = spi_sdo_t ? 1'bz : spi_sdo;
assign spi_sdi = spi_three_wire ? cx9261a_spi_mosi : cx9261a_spi_miso;
// ps clock
wire ps_clk_200M;
wire ps_clk_200M;
wire ps_rstn;
system_bd_wrapper system_bd
(
@@ -191,7 +192,11 @@ system_bd_wrapper system_bd
.spi_active (spi_active ), // output spi_active
// ps clock
.ps_clk_200M (ps_clk_200M ) // output ps_clk_200M
.ps_clk_200M (ps_clk_200M ), // output ps_clk_200M
.ps_rstn (ps_rstn ), // output ps_rstn
// hop signal
.hop_signal (hop_flag ) // input hop_signal
);
////////////////////////////////////////////////////////////////////////////////
@@ -411,8 +416,8 @@ reg hop_trig_d = 'b0;
assign hop_flag = hop_flag_buf;
always @(posedge sys_clk_64M or negedge sys_rstn) begin
if (!sys_rstn) begin
always @(posedge ps_clk_200M or negedge ps_rstn) begin
if (!ps_rstn) begin
hop_cnt <= 'b0;
hop_flag_buf <= 'b0;
hop_trig_d <= 'b0;
@@ -449,9 +454,7 @@ ila_trx u_ila_trx
.probe1 (tx_data_i ), // input wire [15:0] probe1
.probe2 (tx_data_q ), // input wire [15:0] probe2
.probe3 (rx1_data_i ), // input wire [15:0] probe3
.probe4 (rx1_data_q ), // input wire [15:0] probe4
.probe5 (rx2_data_i ), // input wire [15:0] probe5
.probe6 (rx2_data_q ) // input wire [15:0] probe6
.probe4 (rx1_data_q ) // input wire [15:0] probe4
);
vio_manual_ctrl u_vio_manual_ctrl
zc706_cx9261a_demo/zc706_cx9261a_demo.xpr
+44 -44
View File
@@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2024.1 (64-bit) -->
<!-- Product Version: Vivado v2024.1.2 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. -->
@@ -67,13 +67,13 @@
<Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/>
<Option Name="WTXSimExportSim" Val="39"/>
<Option Name="WTModelSimExportSim" Val="39"/>
<Option Name="WTQuestaExportSim" Val="39"/>
<Option Name="WTXSimExportSim" Val="43"/>
<Option Name="WTModelSimExportSim" Val="43"/>
<Option Name="WTQuestaExportSim" Val="43"/>
<Option Name="WTIesExportSim" Val="27"/>
<Option Name="WTVcsExportSim" Val="39"/>
<Option Name="WTRivieraExportSim" Val="39"/>
<Option Name="WTActivehdlExportSim" Val="39"/>
<Option Name="WTVcsExportSim" Val="43"/>
<Option Name="WTRivieraExportSim" Val="43"/>
<Option Name="WTActivehdlExportSim" Val="43"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/>
@@ -402,12 +402,6 @@
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="system_bd_xbar_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_xbar_0" RelGenDir="$PGENDIR/system_bd_xbar_0">
<Config>
<Option Name="TopModule" Val="system_bd_xbar_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="hrc_4_12_03" Type="BlockSrcs" RelSrcDir="$PSRCDIR/hrc_4_12_03" RelGenDir="$PGENDIR/hrc_4_12_03">
<File Path="$PSRCDIR/sources_1/ip/hrc_4_12_03/hrc_4_12_03.xci">
<FileInfo>
@@ -473,15 +467,21 @@
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="system_bd_axi_spi_engine_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_axi_spi_engine_0_0" RelGenDir="$PGENDIR/system_bd_axi_spi_engine_0_0">
<Config>
<Option Name="TopModule" Val="system_bd_axi_spi_engine_0_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="system_bd_system_ila_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_system_ila_0_0" RelGenDir="$PGENDIR/system_bd_system_ila_0_0">
<Config>
<Option Name="TopModule" Val="system_bd_system_ila_0_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="system_bd_axi_spi_engine_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_axi_spi_engine_0_0" RelGenDir="$PGENDIR/system_bd_axi_spi_engine_0_0">
<FileSet Name="system_bd_xbar_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_xbar_0" RelGenDir="$PGENDIR/system_bd_xbar_0">
<Config>
<Option Name="TopModule" Val="system_bd_axi_spi_engine_0_0"/>
<Option Name="TopModule" Val="system_bd_xbar_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
@@ -658,16 +658,6 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="system_bd_xbar_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_xbar_0" Part="xc7z045ffg900-2" ConstrsSet="system_bd_xbar_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_xbar_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_xbar_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_xbar_0_synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="hrc_4_12_03_synth_1" Type="Ft3:Synth" SrcSet="hrc_4_12_03" Part="xc7z045ffg900-2" ConstrsSet="hrc_4_12_03" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/hrc_4_12_03_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/hrc_4_12_03_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/hrc_4_12_03_synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
@@ -718,6 +708,16 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="system_bd_axi_spi_engine_0_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_axi_spi_engine_0_0" Part="xc7z045ffg900-2" ConstrsSet="system_bd_axi_spi_engine_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_axi_spi_engine_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_axi_spi_engine_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_axi_spi_engine_0_0_synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="system_bd_system_ila_0_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_system_ila_0_0" Part="xc7z045ffg900-2" ConstrsSet="system_bd_system_ila_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_system_ila_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_system_ila_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_system_ila_0_0_synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
@@ -730,7 +730,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="system_bd_axi_spi_engine_0_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_axi_spi_engine_0_0" Part="xc7z045ffg900-2" ConstrsSet="system_bd_axi_spi_engine_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_axi_spi_engine_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_axi_spi_engine_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_axi_spi_engine_0_0_synth_1" ParallelReportGen="true">
<Run Id="system_bd_xbar_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_xbar_0" Part="xc7z045ffg900-2" ConstrsSet="system_bd_xbar_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_xbar_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_xbar_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_xbar_0_synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
<Desc>Vivado Synthesis Defaults</Desc>
@@ -998,23 +998,6 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="system_bd_xbar_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z045ffg900-2" ConstrsSet="system_bd_xbar_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_xbar_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_xbar_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_xbar_0_impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="hrc_4_12_03_impl_1" Type="Ft2:EntireDesign" Part="xc7z045ffg900-2" ConstrsSet="hrc_4_12_03" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="hrc_4_12_03_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/hrc_4_12_03_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/hrc_4_12_03_impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
@@ -1100,6 +1083,23 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="system_bd_axi_spi_engine_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z045ffg900-2" ConstrsSet="system_bd_axi_spi_engine_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_axi_spi_engine_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_axi_spi_engine_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_axi_spi_engine_0_0_impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="system_bd_system_ila_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z045ffg900-2" ConstrsSet="system_bd_system_ila_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_system_ila_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_system_ila_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_system_ila_0_0_impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
@@ -1119,7 +1119,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="system_bd_axi_spi_engine_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z045ffg900-2" ConstrsSet="system_bd_axi_spi_engine_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_axi_spi_engine_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_axi_spi_engine_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_axi_spi_engine_0_0_impl_1" ParallelReportGen="true">
<Run Id="system_bd_xbar_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z045ffg900-2" ConstrsSet="system_bd_xbar_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_xbar_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_xbar_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_xbar_0_impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
<Desc>Default settings for Implementation.</Desc>