Compare commits
2
Commits
60cf852928
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33da73a4e0
| Author | SHA1 | Date | |
|---|---|---|---|
 josh
|
33da73a4e0 | ||
|
josh
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425331337e |
@@ -0,0 +1,119 @@
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||||
################################################################################
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||||
############################### Project Specific ###############################
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||||
################################################################################
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# everything
|
||||
*
|
||||
|
||||
# git related
|
||||
!/.gitignore
|
||||
!/.gitattributes
|
||||
|
||||
# project documents
|
||||
!/*.md
|
||||
!/*.txt
|
||||
|
||||
################################################################################
|
||||
############################### Vivado Specific ################################
|
||||
################################################################################
|
||||
|
||||
# xpr: needed for recreating design
|
||||
!/*.xpr
|
||||
|
||||
# source: include everything
|
||||
!/*.srcs/
|
||||
!/*.srcs/**/*
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||||
|
||||
# runs: exclude everything but design run results
|
||||
!/*.runs/
|
||||
!/*.runs/impl_*/
|
||||
!/*.runs/impl_*/*.bit
|
||||
!/*.runs/impl_*/*.ltx
|
||||
|
||||
# xsa (Xilinx support archive): include for ps
|
||||
!/*.xsa
|
||||
|
||||
################################################################################
|
||||
################################ Vitis Specific ################################
|
||||
################################################################################
|
||||
|
||||
# include sdk directory and everything in it
|
||||
!/vitis*/
|
||||
!/vitis*/**
|
||||
/vitis*/**.log
|
||||
/vitis*/.analytics
|
||||
|
||||
# exclude some obscure hidden SDK folders
|
||||
/vitis*/.metadata/
|
||||
/vitis*/.sdk/
|
||||
/vitis*/RemoteSystemsTempFiles/
|
||||
/vitis*/webtalk/
|
||||
|
||||
# hw_platform: exclude the entire hw_platform folder, as everything can be
|
||||
# generated from the .hdf file. Make sure to include the bitstream in the .hdf
|
||||
# file when exporting from Vivado!
|
||||
/vitis*/*_hw_platform_*/
|
||||
|
||||
# BSP: only keep `.cproject`, `.project`, `.sdkproject`, `.system.mss` and
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||||
# Makefile, ps lib files are regenerated automatically
|
||||
/vitis*/*_bsp/*
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||||
!/vitis*/*_bsp/*.cproject
|
||||
!/vitis*/*_bsp/*.project
|
||||
!/vitis*/*_bsp/*.sdkproject
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||||
!/vitis*/*_bsp/system.mss
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||||
!/vitis*/*_bsp/Makefile
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||||
|
||||
# Application: ignored file patterns, exclude Debug & Release folders
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||||
/vitis*/**/*.o
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||||
/vitis*/**/*.d
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||||
/vitis*/**/*.a
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||||
/vitis*/*/Debug/
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||||
/vitis*/*/Release/
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||||
|
||||
################################################################################
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||||
############################ Vivado & Vitis Common #############################
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################################################################################
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||||
|
||||
# file patterns that should always be ignored (journal files, log files, dump
|
||||
# files that are created upon Vivado/SDK errors)
|
||||
*.jou
|
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*.log
|
||||
*.backup.jou
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||||
*.backup.log
|
||||
*.upgrade_log
|
||||
*.dmp
|
||||
*.debug
|
||||
vivado_pid*
|
||||
|
||||
# vivado workspace files
|
||||
xsim.dir/
|
||||
xvlog.pb
|
||||
|
||||
# Xilinx tools generated files
|
||||
.metadata/
|
||||
.settings/
|
||||
.wsdata/
|
||||
.Xil/
|
||||
logs/
|
||||
Packages/
|
||||
*.log*
|
||||
|
||||
# System generated files
|
||||
# -- macOS
|
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.DS_Store
|
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.AppleDouble
|
||||
.LSOverride
|
||||
._*
|
||||
|
||||
# -- Windows
|
||||
Thumbs.db
|
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ehthumbs.db
|
||||
Desktop.ini
|
||||
|
||||
# -- Linux
|
||||
*~
|
||||
|
||||
# IDEs and editors' files
|
||||
*.idea
|
||||
*.vscode
|
||||
*.sublime-workspace
|
||||
*.sublime-project
|
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Load Diff
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Load Diff
@@ -0,0 +1,143 @@
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################ 1 #CX9261A Interface PACKAGE_PIN and IOStandard constraints####################
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############CX9261A SPI and Control pin Interface##############
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set_property PACKAGE_PIN V28 [get_ports SCLK ]
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set_property PACKAGE_PIN V29 [get_ports CSB ]
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set_property PACKAGE_PIN T28 [get_ports SDO ]
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set_property PACKAGE_PIN R28 [get_ports SDIO ]
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set_property PACKAGE_PIN N27 [get_ports NRST ]
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set_property PACKAGE_PIN U26 [get_ports OSC_OUT ]
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set_property PACKAGE_PIN P26 [get_ports ENABLE_TRX2]
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set_property PACKAGE_PIN P25 [get_ports ENABLE_TRX1]
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set_property PACKAGE_PIN N26 [get_ports ENABLE_RXFB]
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set_property PACKAGE_PIN P29 [get_ports TXNRX_TRX1 ]
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set_property PACKAGE_PIN N29 [get_ports TXNRX_TRX2 ]
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set_property PACKAGE_PIN U27 [get_ports TXNRX_RXFB ]
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set_property IOSTANDARD LVCMOS25 [get_ports SCLK ]
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set_property IOSTANDARD LVCMOS25 [get_ports CSB ]
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set_property IOSTANDARD LVCMOS25 [get_ports SDO ]
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set_property IOSTANDARD LVCMOS25 [get_ports SDIO ]
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set_property IOSTANDARD LVCMOS25 [get_ports NRST ]
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set_property IOSTANDARD LVCMOS25 [get_ports OSC_OUT ]
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set_property IOSTANDARD LVCMOS25 [get_ports ENABLE_TRX1]
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set_property IOSTANDARD LVCMOS25 [get_ports ENABLE_TRX2]
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set_property IOSTANDARD LVCMOS25 [get_ports ENABLE_RXFB]
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set_property IOSTANDARD LVCMOS25 [get_ports TXNRX_TRX1 ]
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set_property IOSTANDARD LVCMOS25 [get_ports TXNRX_TRX2 ]
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set_property IOSTANDARD LVCMOS25 [get_ports TXNRX_RXFB ]
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###############################################################
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####################CX9261A data Interface#####################
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set_property PACKAGE_PIN W25 [get_ports RXFB_MCLK_IN ]
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set_property PACKAGE_PIN W26 [get_ports RXFB_FRAME_IN ]
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set_property PACKAGE_PIN AF22 [get_ports RX1_MCLK_IN_N ]
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set_property PACKAGE_PIN AE22 [get_ports RX2_MCLK_IN_P ]
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set_property PACKAGE_PIN AH24 [get_ports RX1_FRAME_IN_N ]
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set_property PACKAGE_PIN AH23 [get_ports RX2_FRAME_IN_P ]
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set_property PACKAGE_PIN R26 [get_ports TX1_FCLK_OUT_N ]
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set_property PACKAGE_PIN R25 [get_ports TX2_FCLK_OUT_P ]
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set_property PACKAGE_PIN T25 [get_ports TX1_FRAME_OUT_N ]
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set_property PACKAGE_PIN T24 [get_ports TX2_FRAME_OUT_P ]
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set_property PACKAGE_PIN P30 [get_ports {RXFB_RX_DATA[7]}]
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set_property PACKAGE_PIN R30 [get_ports {RXFB_RX_DATA[6]}]
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set_property PACKAGE_PIN P23 [get_ports {RXFB_RX_DATA[5]}]
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set_property PACKAGE_PIN P24 [get_ports {RXFB_RX_DATA[4]}]
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set_property PACKAGE_PIN P21 [get_ports {RXFB_RX_DATA[3]}]
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set_property PACKAGE_PIN R21 [get_ports {RXFB_RX_DATA[2]}]
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set_property PACKAGE_PIN W29 [get_ports {RXFB_RX_DATA[1]}]
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set_property PACKAGE_PIN W30 [get_ports {RXFB_RX_DATA[0]}]
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set_property PACKAGE_PIN U25 [get_ports {RXFB_TX_DATA[7]}]
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set_property PACKAGE_PIN V26 [get_ports {RXFB_TX_DATA[6]}]
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set_property PACKAGE_PIN V27 [get_ports {RXFB_TX_DATA[5]}]
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set_property PACKAGE_PIN W28 [get_ports {RXFB_TX_DATA[4]}]
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set_property PACKAGE_PIN T29 [get_ports {RXFB_TX_DATA[3]}]
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set_property PACKAGE_PIN U29 [get_ports {RXFB_TX_DATA[2]}]
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set_property PACKAGE_PIN T30 [get_ports {RXFB_TX_DATA[1]}]
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set_property PACKAGE_PIN U30 [get_ports {RXFB_TX_DATA[0]}]
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set_property PACKAGE_PIN AH19 [get_ports {RX1_FDD_DATA[7]}]
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set_property PACKAGE_PIN AJ19 [get_ports {RX1_FDD_DATA[6]}]
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set_property PACKAGE_PIN AF19 [get_ports {RX1_FDD_DATA[5]}]
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set_property PACKAGE_PIN AG19 [get_ports {RX1_FDD_DATA[4]}]
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set_property PACKAGE_PIN AF23 [get_ports {RX1_FDD_DATA[3]}]
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set_property PACKAGE_PIN AF24 [get_ports {RX1_FDD_DATA[2]}]
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set_property PACKAGE_PIN AA24 [get_ports {RX1_FDD_DATA[1]}]
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set_property PACKAGE_PIN AB24 [get_ports {RX1_FDD_DATA[0]}]
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set_property PACKAGE_PIN Y22 [get_ports {RX2_FDD_DATA[7]}]
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set_property PACKAGE_PIN Y23 [get_ports {RX2_FDD_DATA[6]}]
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set_property PACKAGE_PIN AC24 [get_ports {RX2_FDD_DATA[5]}]
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set_property PACKAGE_PIN AD24 [get_ports {RX2_FDD_DATA[4]}]
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set_property PACKAGE_PIN AG24 [get_ports {RX2_FDD_DATA[3]}]
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set_property PACKAGE_PIN AG25 [get_ports {RX2_FDD_DATA[2]}]
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set_property PACKAGE_PIN AF20 [get_ports {RX2_FDD_DATA[1]}]
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set_property PACKAGE_PIN AG20 [get_ports {RX2_FDD_DATA[0]}]
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set_property PACKAGE_PIN AG22 [get_ports {TX1_FDD_DATA[7]}]
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||||
set_property PACKAGE_PIN AH22 [get_ports {TX1_FDD_DATA[6]}]
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set_property PACKAGE_PIN AA22 [get_ports {TX1_FDD_DATA[5]}]
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||||
set_property PACKAGE_PIN AA23 [get_ports {TX1_FDD_DATA[4]}]
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||||
set_property PACKAGE_PIN AG21 [get_ports {TX1_FDD_DATA[3]}]
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||||
set_property PACKAGE_PIN AH21 [get_ports {TX1_FDD_DATA[2]}]
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||||
set_property PACKAGE_PIN AD21 [get_ports {TX1_FDD_DATA[1]}]
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set_property PACKAGE_PIN AE21 [get_ports {TX1_FDD_DATA[0]}]
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||||
set_property PACKAGE_PIN AK17 [get_ports {TX2_FDD_DATA[7]}]
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||||
set_property PACKAGE_PIN AK18 [get_ports {TX2_FDD_DATA[6]}]
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||||
set_property PACKAGE_PIN AJ20 [get_ports {TX2_FDD_DATA[5]}]
|
||||
set_property PACKAGE_PIN AK20 [get_ports {TX2_FDD_DATA[4]}]
|
||||
set_property PACKAGE_PIN AJ23 [get_ports {TX2_FDD_DATA[3]}]
|
||||
set_property PACKAGE_PIN AJ24 [get_ports {TX2_FDD_DATA[2]}]
|
||||
set_property PACKAGE_PIN AD23 [get_ports {TX2_FDD_DATA[1]}]
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||||
set_property PACKAGE_PIN AE23 [get_ports {TX2_FDD_DATA[0]}]
|
||||
set_property IOSTANDARD LVCMOS25 [get_ports RXFB_MCLK_IN ]
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set_property IOSTANDARD LVCMOS25 [get_ports RXFB_FRAME_IN ]
|
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set_property IOSTANDARD LVCMOS25 [get_ports RX1_MCLK_IN_N ]
|
||||
set_property IOSTANDARD LVCMOS25 [get_ports RX2_MCLK_IN_P ]
|
||||
set_property IOSTANDARD LVCMOS25 [get_ports RX1_FRAME_IN_N ]
|
||||
set_property IOSTANDARD LVCMOS25 [get_ports RX2_FRAME_IN_P ]
|
||||
set_property IOSTANDARD LVCMOS25 [get_ports TX1_FCLK_OUT_N ]
|
||||
set_property IOSTANDARD LVCMOS25 [get_ports TX2_FCLK_OUT_P ]
|
||||
set_property IOSTANDARD LVCMOS25 [get_ports TX1_FRAME_OUT_N ]
|
||||
set_property IOSTANDARD LVCMOS25 [get_ports TX2_FRAME_OUT_P ]
|
||||
set_property IOSTANDARD LVCMOS25 [get_ports {RXFB_RX_DATA[*]}]
|
||||
set_property IOSTANDARD LVCMOS25 [get_ports {RXFB_TX_DATA[*]}]
|
||||
set_property IOSTANDARD LVCMOS25 [get_ports {RX1_FDD_DATA[*]}]
|
||||
set_property IOSTANDARD LVCMOS25 [get_ports {RX2_FDD_DATA[*]}]
|
||||
set_property IOSTANDARD LVCMOS25 [get_ports {TX1_FDD_DATA[*]}]
|
||||
set_property IOSTANDARD LVCMOS25 [get_ports {TX2_FDD_DATA[*]}]
|
||||
###############################################################
|
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################################################################################################
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########### 2 #CX3E04 and Debug Interface PACKAGE_PIN and IOStandard constraints################
|
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######################CX3E04 Interface#########################
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set_property PACKAGE_PIN W23 [get_ports CX3E04_NRST ]
|
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set_property PACKAGE_PIN AJ25 [get_ports CX3E04_CSB ]
|
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set_property PACKAGE_PIN AK25 [get_ports CX3E04_SDIO ]
|
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set_property PACKAGE_PIN AK22 [get_ports CX3E04_SCLK ]
|
||||
set_property IOSTANDARD LVCMOS25 [get_ports CX3E04_NRST ]
|
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set_property IOSTANDARD LVCMOS25 [get_ports CX3E04_CSB ]
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set_property IOSTANDARD LVCMOS25 [get_ports CX3E04_SDIO ]
|
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set_property IOSTANDARD LVCMOS25 [get_ports CX3E04_SCLK ]
|
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|
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set_property PACKAGE_PIN AE28 [get_ports CX3E04_CLK_P ]
|
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set_property PACKAGE_PIN AF28 [get_ports CX3E04_CLK_N ]
|
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set_property PACKAGE_PIN AC29 [get_ports CX3E04_SYNC_P]
|
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set_property PACKAGE_PIN AD29 [get_ports CX3E04_SYNC_N]
|
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set_property IOSTANDARD LVDS_25 [get_ports CX3E04_CLK_P ]
|
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set_property IOSTANDARD LVDS_25 [get_ports CX3E04_CLK_N ]
|
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set_property IOSTANDARD LVDS_25 [get_ports CX3E04_SYNC_P]
|
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set_property IOSTANDARD LVDS_25 [get_ports CX3E04_SYNC_N]
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###############################################################
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######################Debug Interface##########################
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#set_property PACKAGE_PIN AD18 [get_ports power_on_trigger]
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#set_property IOSTANDARD LVCMOS25 [get_ports power_on_trigger]
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###############################################################
|
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################################################################################################
|
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################# 3 #clock Period/Route and hardcore Position constraints#######################
|
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create_clock -period 6.25 -name RX1_MCLK_IN_N -waveform {0.000 3.125} [get_ports RX1_MCLK_IN_N]
|
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create_clock -period 6.25 -name RX2_MCLK_IN_P -waveform {0.000 3.125} [get_ports RX2_MCLK_IN_P]
|
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create_clock -period 6.25 -name RXFB_MCLK_IN -waveform {0.000 3.125} [get_ports RXFB_MCLK_IN ]
|
||||
|
||||
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets u_mclk_delay/MCLK1]
|
||||
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets u_mclk_delay/MCLK2]
|
||||
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets u_mclk_delay/MCLK3]
|
||||
|
||||
set_property LOC IDELAYCTRL_X0Y2 [get_cells u_mclk_delay/IDELAYCTRL_RX12]
|
||||
set_property LOC IDELAYCTRL_X0Y4 [get_cells u_mclk_delay/IDELAYCTRL_RX3]
|
||||
################################################################################################
|
||||
|
||||
set_clock_groups -asynchronous -group [get_clocks RXFB_MCLK_IN] -group [get_clocks RX1_MCLK_IN_N] -group [get_clocks RX2_MCLK_IN_P] -group [get_clocks clk_fpga_0]
|
||||
@@ -0,0 +1,49 @@
|
||||
##################################### 1 #set false path########################################
|
||||
set_false_path -from [get_pins {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[7].ram.r/SAFETY_CKT_GEN.RSTB_SHFT_REG_reg[3]_srl3/CLK}] -to [get_pins {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[7].ram.r/SAFETY_CKT_GEN.RSTB_SHFT_REG_reg[4]/D}]
|
||||
set_false_path -from [get_pins {system_top_i/fifo_generator_0/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/SAFETY_CKT_GEN.RSTA_SHFT_REG_reg[3]_srl3/CLK}] -to [get_pins {system_top_i/fifo_generator_0/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/SAFETY_CKT_GEN.RSTA_SHFT_REG_reg[4]/D}]
|
||||
|
||||
set_false_path -from [get_clocks RX1_MCLK_IN_N] -to [get_clocks -of_objects [get_pins system_top_i/mig_7series_0/u_system_top_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKFBOUT]]
|
||||
set_false_path -from [get_clocks RX2_MCLK_IN_P] -to [get_clocks -of_objects [get_pins system_top_i/mig_7series_0/u_system_top_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKFBOUT]]
|
||||
|
||||
set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks RX2_MCLK_IN_P]
|
||||
################################################################################################
|
||||
#################################### 2 #CX9261A data ila########################################
|
||||
create_debug_core u_ila_0 ila
|
||||
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
|
||||
set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0]
|
||||
set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0]
|
||||
set_property C_DATA_DEPTH 16384 [get_debug_cores u_ila_0]
|
||||
set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0]
|
||||
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
|
||||
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
|
||||
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/clk]
|
||||
connect_debug_port u_ila_0/clk [get_nets [list system_top_i/processing_system7_0/inst/FCLK_CLK0]]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
|
||||
set_property port_width 24 [get_debug_ports u_ila_0/probe0]
|
||||
connect_debug_port u_ila_0/probe0 [get_nets [list {hop_intr/r_hop_cnt[0]} {hop_intr/r_hop_cnt[1]} {hop_intr/r_hop_cnt[2]} {hop_intr/r_hop_cnt[3]} {hop_intr/r_hop_cnt[4]} {hop_intr/r_hop_cnt[5]} {hop_intr/r_hop_cnt[6]} {hop_intr/r_hop_cnt[7]} {hop_intr/r_hop_cnt[8]} {hop_intr/r_hop_cnt[9]} {hop_intr/r_hop_cnt[10]} {hop_intr/r_hop_cnt[11]} {hop_intr/r_hop_cnt[12]} {hop_intr/r_hop_cnt[13]} {hop_intr/r_hop_cnt[14]} {hop_intr/r_hop_cnt[15]} {hop_intr/r_hop_cnt[16]} {hop_intr/r_hop_cnt[17]} {hop_intr/r_hop_cnt[18]} {hop_intr/r_hop_cnt[19]} {hop_intr/r_hop_cnt[20]} {hop_intr/r_hop_cnt[21]} {hop_intr/r_hop_cnt[22]} {hop_intr/r_hop_cnt[23]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe1]
|
||||
connect_debug_port u_ila_0/probe1 [get_nets [list hop_intr/hop_flag]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe2]
|
||||
connect_debug_port u_ila_0/probe2 [get_nets [list hop_intr/spi_pose_flag]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe3]
|
||||
connect_debug_port u_ila_0/probe3 [get_nets [list hop_intr/r_hop_cnt_flag]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe4]
|
||||
connect_debug_port u_ila_0/probe4 [get_nets [list hop_intr/hop_neg_flag]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe5]
|
||||
connect_debug_port u_ila_0/probe5 [get_nets [list hop_intr/hop_signal]]
|
||||
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
|
||||
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
|
||||
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
|
||||
connect_debug_port dbg_hub/clk [get_nets MCLK2]
|
||||
################################################################################################
|
||||
@@ -0,0 +1,163 @@
|
||||
set_false_path -from [get_pins {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[7].ram.r/SAFETY_CKT_GEN.RSTB_SHFT_REG_reg[3]_srl3/CLK}] -to [get_pins {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[7].ram.r/SAFETY_CKT_GEN.RSTB_SHFT_REG_reg[4]/D}]
|
||||
set_false_path -from [get_pins {system_top_i/fifo_generator_0/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/SAFETY_CKT_GEN.RSTA_SHFT_REG_reg[3]_srl3/CLK}] -to [get_pins {system_top_i/fifo_generator_0/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/SAFETY_CKT_GEN.RSTA_SHFT_REG_reg[4]/D}]
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
create_debug_core u_ila_0 ila
|
||||
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
|
||||
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
|
||||
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
|
||||
set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
|
||||
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
|
||||
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
|
||||
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
|
||||
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/clk]
|
||||
connect_debug_port u_ila_0/clk [get_nets [list cx9261a_if_cmos/u_cx9261a_if_cmos_port/mclk_g1]]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
|
||||
set_property port_width 8 [get_debug_ports u_ila_0/probe0]
|
||||
connect_debug_port u_ila_0/probe0 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA[7]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
|
||||
set_property port_width 8 [get_debug_ports u_ila_0/probe1]
|
||||
connect_debug_port u_ila_0/probe1 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA[7]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
|
||||
set_property port_width 8 [get_debug_ports u_ila_0/probe2]
|
||||
connect_debug_port u_ila_0/probe2 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA_pos_o[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA_pos_o[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA_pos_o[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA_pos_o[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA_pos_o[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA_pos_o[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA_pos_o[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA_pos_o[7]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
|
||||
set_property port_width 8 [get_debug_ports u_ila_0/probe3]
|
||||
connect_debug_port u_ila_0/probe3 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA_neg_o[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA_neg_o[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA_neg_o[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA_neg_o[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA_neg_o[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA_neg_o[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA_neg_o[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA_neg_o[7]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
|
||||
set_property port_width 8 [get_debug_ports u_ila_0/probe4]
|
||||
connect_debug_port u_ila_0/probe4 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA_pos_o[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA_pos_o[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA_pos_o[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA_pos_o[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA_pos_o[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA_pos_o[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA_pos_o[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA_pos_o[7]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
|
||||
set_property port_width 8 [get_debug_ports u_ila_0/probe5]
|
||||
connect_debug_port u_ila_0/probe5 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA_neg_o[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA_neg_o[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA_neg_o[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA_neg_o[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA_neg_o[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA_neg_o[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA_neg_o[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA_neg_o[7]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
|
||||
set_property port_width 16 [get_debug_ports u_ila_0/probe6]
|
||||
connect_debug_port u_ila_0/probe6 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_i_data[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_i_data[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_i_data[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_i_data[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_i_data[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_i_data[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_i_data[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_i_data[7]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_i_data[8]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_i_data[9]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_i_data[10]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_i_data[11]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_i_data[12]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_i_data[13]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_i_data[14]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_i_data[15]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
|
||||
set_property port_width 16 [get_debug_ports u_ila_0/probe7]
|
||||
connect_debug_port u_ila_0/probe7 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_q_data[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_q_data[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_q_data[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_q_data[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_q_data[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_q_data[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_q_data[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_q_data[7]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_q_data[8]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_q_data[9]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_q_data[10]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_q_data[11]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_q_data[12]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_q_data[13]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_q_data[14]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_q_data[15]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
|
||||
set_property port_width 16 [get_debug_ports u_ila_0/probe8]
|
||||
connect_debug_port u_ila_0/probe8 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_i_data[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_i_data[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_i_data[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_i_data[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_i_data[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_i_data[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_i_data[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_i_data[7]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_i_data[8]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_i_data[9]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_i_data[10]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_i_data[11]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_i_data[12]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_i_data[13]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_i_data[14]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_i_data[15]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
|
||||
set_property port_width 16 [get_debug_ports u_ila_0/probe9]
|
||||
connect_debug_port u_ila_0/probe9 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_q_data[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_q_data[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_q_data[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_q_data[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_q_data[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_q_data[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_q_data[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_q_data[7]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_q_data[8]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_q_data[9]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_q_data[10]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_q_data[11]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_q_data[12]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_q_data[13]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_q_data[14]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_q_data[15]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe10]
|
||||
connect_debug_port u_ila_0/probe10 [get_nets [list cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_data_valid]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe11]
|
||||
connect_debug_port u_ila_0/probe11 [get_nets [list cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_data_ready]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe12]
|
||||
connect_debug_port u_ila_0/probe12 [get_nets [list cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_frame_neg]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe13]
|
||||
connect_debug_port u_ila_0/probe13 [get_nets [list cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_frame_pos]]
|
||||
create_debug_core u_ila_1 ila
|
||||
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_1]
|
||||
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_1]
|
||||
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_1]
|
||||
set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_1]
|
||||
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_1]
|
||||
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_1]
|
||||
set_property C_TRIGIN_EN false [get_debug_cores u_ila_1]
|
||||
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_1]
|
||||
set_property port_width 1 [get_debug_ports u_ila_1/clk]
|
||||
connect_debug_port u_ila_1/clk [get_nets [list cx9261a_if_cmos/u_cx9261a_if_cmos_port/data_clk2]]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe0]
|
||||
set_property port_width 2 [get_debug_ports u_ila_1/probe0]
|
||||
connect_debug_port u_ila_1/probe0 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX_FRAME_N[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX_FRAME_N[1]}]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe1]
|
||||
set_property port_width 8 [get_debug_ports u_ila_1/probe1]
|
||||
connect_debug_port u_ila_1/probe1 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA_neg_o[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA_neg_o[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA_neg_o[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA_neg_o[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA_neg_o[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA_neg_o[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA_neg_o[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA_neg_o[7]}]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe2]
|
||||
set_property port_width 8 [get_debug_ports u_ila_1/probe2]
|
||||
connect_debug_port u_ila_1/probe2 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA[7]}]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe3]
|
||||
set_property port_width 8 [get_debug_ports u_ila_1/probe3]
|
||||
connect_debug_port u_ila_1/probe3 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA_neg_o[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA_neg_o[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA_neg_o[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA_neg_o[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA_neg_o[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA_neg_o[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA_neg_o[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA_neg_o[7]}]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe4]
|
||||
set_property port_width 8 [get_debug_ports u_ila_1/probe4]
|
||||
connect_debug_port u_ila_1/probe4 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA_pos_o[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA_pos_o[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA_pos_o[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA_pos_o[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA_pos_o[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA_pos_o[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA_pos_o[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA_pos_o[7]}]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe5]
|
||||
set_property port_width 8 [get_debug_ports u_ila_1/probe5]
|
||||
connect_debug_port u_ila_1/probe5 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA_pos_o[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA_pos_o[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA_pos_o[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA_pos_o[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA_pos_o[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA_pos_o[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA_pos_o[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA_pos_o[7]}]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe6]
|
||||
set_property port_width 8 [get_debug_ports u_ila_1/probe6]
|
||||
connect_debug_port u_ila_1/probe6 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA[7]}]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe7]
|
||||
set_property port_width 16 [get_debug_ports u_ila_1/probe7]
|
||||
connect_debug_port u_ila_1/probe7 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_q_data[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_q_data[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_q_data[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_q_data[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_q_data[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_q_data[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_q_data[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_q_data[7]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_q_data[8]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_q_data[9]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_q_data[10]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_q_data[11]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_q_data[12]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_q_data[13]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_q_data[14]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_q_data[15]}]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe8]
|
||||
set_property port_width 16 [get_debug_ports u_ila_1/probe8]
|
||||
connect_debug_port u_ila_1/probe8 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_i_data[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_i_data[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_i_data[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_i_data[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_i_data[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_i_data[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_i_data[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_i_data[7]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_i_data[8]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_i_data[9]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_i_data[10]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_i_data[11]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_i_data[12]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_i_data[13]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_i_data[14]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_i_data[15]}]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe9]
|
||||
set_property port_width 16 [get_debug_ports u_ila_1/probe9]
|
||||
connect_debug_port u_ila_1/probe9 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_i_data[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_i_data[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_i_data[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_i_data[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_i_data[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_i_data[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_i_data[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_i_data[7]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_i_data[8]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_i_data[9]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_i_data[10]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_i_data[11]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_i_data[12]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_i_data[13]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_i_data[14]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_i_data[15]}]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe10]
|
||||
set_property port_width 16 [get_debug_ports u_ila_1/probe10]
|
||||
connect_debug_port u_ila_1/probe10 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_q_data[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_q_data[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_q_data[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_q_data[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_q_data[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_q_data[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_q_data[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_q_data[7]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_q_data[8]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_q_data[9]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_q_data[10]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_q_data[11]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_q_data[12]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_q_data[13]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_q_data[14]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_q_data[15]}]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe11]
|
||||
set_property port_width 1 [get_debug_ports u_ila_1/probe11]
|
||||
connect_debug_port u_ila_1/probe11 [get_nets [list cx9261a_if_cmos/u_cx9261a_if_cmos_port/r1t1_r2t2_sel]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe12]
|
||||
set_property port_width 1 [get_debug_ports u_ila_1/probe12]
|
||||
connect_debug_port u_ila_1/probe12 [get_nets [list cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_data_valid]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe13]
|
||||
set_property port_width 1 [get_debug_ports u_ila_1/probe13]
|
||||
connect_debug_port u_ila_1/probe13 [get_nets [list cx9261a_if_cmos/u_cx9261a_if_cmos_port/sp_dp_sel]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe14]
|
||||
set_property port_width 1 [get_debug_ports u_ila_1/probe14]
|
||||
connect_debug_port u_ila_1/probe14 [get_nets [list cx9261a_if_cmos/u_cx9261a_if_cmos_port/tdd_fdd_sel]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe15]
|
||||
set_property port_width 1 [get_debug_ports u_ila_1/probe15]
|
||||
connect_debug_port u_ila_1/probe15 [get_nets [list cx9261a_if_cmos/u_cx9261a_if_cmos_port/tr_sel]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe16]
|
||||
set_property port_width 1 [get_debug_ports u_ila_1/probe16]
|
||||
connect_debug_port u_ila_1/probe16 [get_nets [list cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_data_ready]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe17]
|
||||
set_property port_width 1 [get_debug_ports u_ila_1/probe17]
|
||||
connect_debug_port u_ila_1/probe17 [get_nets [list cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_frame_neg]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe18]
|
||||
set_property port_width 1 [get_debug_ports u_ila_1/probe18]
|
||||
connect_debug_port u_ila_1/probe18 [get_nets [list cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_frame_pos]]
|
||||
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
|
||||
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
|
||||
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
|
||||
connect_debug_port dbg_hub/clk [get_nets data_clk2]
|
||||
@@ -0,0 +1,763 @@
|
||||
set_property MARK_DEBUG true [get_nets {data_i[10]}]
|
||||
set_property MARK_DEBUG true [get_nets {data_i[1]}]
|
||||
set_property MARK_DEBUG true [get_nets {data_i[4]}]
|
||||
set_property MARK_DEBUG true [get_nets {data_i[6]}]
|
||||
set_property MARK_DEBUG true [get_nets {data_i[13]}]
|
||||
set_property MARK_DEBUG true [get_nets {data_q[2]}]
|
||||
set_property MARK_DEBUG true [get_nets {data_q[6]}]
|
||||
set_property MARK_DEBUG true [get_nets {data_q[10]}]
|
||||
set_property MARK_DEBUG true [get_nets {data_q[15]}]
|
||||
set_property MARK_DEBUG true [get_nets {data_i[0]}]
|
||||
set_property MARK_DEBUG true [get_nets {data_i[5]}]
|
||||
set_property MARK_DEBUG true [get_nets {data_i[8]}]
|
||||
set_property MARK_DEBUG true [get_nets {data_i[15]}]
|
||||
set_property MARK_DEBUG true [get_nets {data_q[1]}]
|
||||
set_property MARK_DEBUG true [get_nets {data_q[5]}]
|
||||
set_property MARK_DEBUG true [get_nets {data_q[8]}]
|
||||
set_property MARK_DEBUG true [get_nets {data_q[12]}]
|
||||
set_property MARK_DEBUG true [get_nets {data_i[3]}]
|
||||
set_property MARK_DEBUG true [get_nets {data_i[7]}]
|
||||
set_property MARK_DEBUG true [get_nets {data_i[12]}]
|
||||
set_property MARK_DEBUG true [get_nets {data_q[0]}]
|
||||
set_property MARK_DEBUG true [get_nets {data_q[4]}]
|
||||
set_property MARK_DEBUG true [get_nets {data_q[7]}]
|
||||
set_property MARK_DEBUG true [get_nets {data_q[13]}]
|
||||
set_property MARK_DEBUG true [get_nets {data_i[2]}]
|
||||
set_property MARK_DEBUG true [get_nets {data_i[9]}]
|
||||
set_property MARK_DEBUG true [get_nets {data_i[11]}]
|
||||
set_property MARK_DEBUG true [get_nets {data_i[14]}]
|
||||
set_property MARK_DEBUG true [get_nets {data_q[3]}]
|
||||
set_property MARK_DEBUG true [get_nets {data_q[9]}]
|
||||
set_property MARK_DEBUG true [get_nets {data_q[11]}]
|
||||
set_property MARK_DEBUG true [get_nets {data_q[14]}]
|
||||
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_1_Q[0]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_1_Q[2]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_1_Q[4]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_1_Q[6]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_1_Q[7]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_1_Q[10]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_1_Q[12]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_1_Q[14]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_1_Q[1]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_1_Q[3]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_1_Q[5]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_1_Q[8]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_1_Q[9]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_1_Q[11]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_1_Q[13]}]
|
||||
|
||||
set_property MARK_DEBUG true [get_nets system_top_i/CE]
|
||||
set_property MARK_DEBUG true [get_nets NRST_OBUF]
|
||||
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[13]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[29]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[54]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[12]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[42]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[17]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[34]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[37]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[35]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[41]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[61]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[24]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[39]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[45]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[23]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[56]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[21]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[35]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[54]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[56]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[42]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[10]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[53]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[63]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[1]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[6]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[58]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[9]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[21]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[23]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[38]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[14]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[12]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[50]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[55]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[57]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[61]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[5]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[50]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[31]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[43]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[55]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[10]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[12]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[39]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[32]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[16]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[63]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[49]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[40]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[58]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[4]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[27]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[13]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[22]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[44]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[15]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[58]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[4]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[7]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[49]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[5]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[59]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[19]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[28]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[3]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[27]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[30]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[9]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[26]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[1]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[6]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[27]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[46]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[3]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[53]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[56]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[8]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[25]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[26]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[47]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[59]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[11]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[29]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[52]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[18]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[24]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[7]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[50]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[33]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[41]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[61]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[1]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[15]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[18]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[0]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[16]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[19]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[51]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[55]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[2]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[20]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[31]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[13]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[49]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[3]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[51]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[7]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[14]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[15]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[32]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[53]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[17]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[23]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[4]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[14]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[45]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[24]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[22]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[59]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[62]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[11]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[22]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[37]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[45]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[60]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[18]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[28]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[0]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[17]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[36]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[39]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[43]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[63]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[2]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[30]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[42]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[60]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[52]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[54]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[26]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[9]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[20]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[33]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[44]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[48]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[60]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[21]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[41]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[48]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[38]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[47]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[29]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[36]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[38]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[44]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[51]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[43]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[48]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[11]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[16]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[35]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[10]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[34]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[40]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[46]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[62]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[0]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[25]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[32]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[8]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[19]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[37]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[57]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[62]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[6]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[52]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[8]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[31]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[20]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[25]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[34]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[40]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[46]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[2]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[57]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[5]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[28]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[47]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[33]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[36]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[30]}]
|
||||
set_property MARK_DEBUG true [get_nets system_top_i/SPI_0_0_io0_t]
|
||||
set_property MARK_DEBUG true [get_nets system_top_i/SPI_0_0_io1_t]
|
||||
set_property MARK_DEBUG true [get_nets system_top_i/SPI_0_0_sck_o]
|
||||
set_property MARK_DEBUG true [get_nets system_top_i/SPI_0_0_ss_i]
|
||||
set_property MARK_DEBUG true [get_nets system_top_i/SPI_0_0_io0_i]
|
||||
set_property MARK_DEBUG true [get_nets system_top_i/SPI_0_0_sck_i]
|
||||
set_property MARK_DEBUG true [get_nets system_top_i/SPI_0_0_sck_t]
|
||||
set_property MARK_DEBUG true [get_nets system_top_i/SPI_0_0_ss1_o]
|
||||
set_property MARK_DEBUG true [get_nets system_top_i/SPI_0_0_ss2_o]
|
||||
set_property MARK_DEBUG true [get_nets system_top_i/SPI_0_0_io0_o]
|
||||
set_property MARK_DEBUG true [get_nets system_top_i/SPI_0_0_io1_i]
|
||||
set_property MARK_DEBUG true [get_nets system_top_i/SPI_0_0_io1_o]
|
||||
set_property MARK_DEBUG true [get_nets system_top_i/SPI_0_0_ss_o]
|
||||
set_property MARK_DEBUG true [get_nets system_top_i/SPI_0_0_ss_t]
|
||||
|
||||
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/addrb[3]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/addrb[5]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/addrb[7]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/addrb[10]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/addrb[11]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/addrb[12]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/addrb[14]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/addrb[2]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/addrb[4]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/addrb[6]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/addrb[8]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/addrb[9]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/addrb[13]}]
|
||||
set_property MARK_DEBUG true [get_nets system_top_i/blk_mem_gen_0/U0/rstb_busy]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[1]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[3]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[6]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[10]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[4]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[0]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[2]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[5]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[8]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[12]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[9]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[11]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[7]}]
|
||||
|
||||
set_property MARK_DEBUG true [get_nets system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/capture_cdc]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[3]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[8]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[24]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[25]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[9]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[0]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[2]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[5]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[18]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[19]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[20]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[21]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[6]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[10]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[17]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[22]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[23]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[12]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[16]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[1]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[4]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[7]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[11]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[13]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[14]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[15]}]
|
||||
#connect_debug_port dbg_hub/clk [get_nets data_clk]
|
||||
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_neg[3]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_neg[0]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_neg[1]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_neg[2]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_neg[4]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_neg[5]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_neg[6]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_neg[7]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_pos[0]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_pos[1]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_pos[2]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_pos[3]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_pos[4]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_pos[5]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_pos[6]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_pos[7]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_neg[4]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_neg[5]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_neg[7]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_neg[2]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_neg[3]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_neg[6]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_neg[0]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_neg[1]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_pos[0]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_pos[1]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_pos[2]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_pos[3]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_pos[4]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_pos[5]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_pos[6]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_pos[7]}]
|
||||
set_property MARK_DEBUG true [get_nets cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FRAME_neg]
|
||||
set_property MARK_DEBUG true [get_nets cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FRAME_pos]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_neg[2]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_pos[0]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_pos[6]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_neg[1]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_neg[5]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_pos[0]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_pos[4]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_pos[2]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_neg[3]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_neg[7]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_pos[1]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_neg[2]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_neg[6]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_pos[1]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_pos[7]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_pos[3]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_neg[0]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_neg[4]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_pos[4]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_pos[7]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_neg[3]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_pos[2]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_pos[5]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_neg[6]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_neg[1]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_neg[5]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_pos[5]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_neg[0]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_neg[4]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_neg[7]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_pos[3]}]
|
||||
set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_pos[6]}]
|
||||
set_property MARK_DEBUG true [get_nets cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FRAME_neg]
|
||||
set_property MARK_DEBUG true [get_nets cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FRAME_pos]
|
||||
|
||||
set_property MARK_DEBUG true [get_nets {rx1_q_data[1]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx1_i_data[1]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx1_i_data[8]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx1_q_data[8]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx2_i_data[8]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx2_i_data[1]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx2_q_data[1]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx2_q_data[8]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx1_i_data[4]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx1_i_data[12]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx1_q_data[4]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx2_i_data[12]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx1_q_data[12]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx2_i_data[4]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx2_q_data[4]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx2_q_data[12]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx1_q_data[11]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx1_i_data[3]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx1_i_data[11]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx1_q_data[3]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx2_i_data[3]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx2_i_data[11]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx2_q_data[3]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx2_q_data[11]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx1_i_data[9]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx1_i_data[14]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx1_q_data[6]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx1_q_data[14]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx2_i_data[6]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx2_i_data[14]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx2_q_data[6]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx2_q_data[14]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx1_i_data[5]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx1_i_data[13]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx1_q_data[5]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx1_q_data[13]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx2_i_data[5]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx2_i_data[13]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx2_q_data[5]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx2_q_data[13]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx1_q_data[7]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx1_q_data[0]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx1_i_data[6]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx1_i_data[0]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx2_i_data[7]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx2_i_data[0]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx2_q_data[0]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx2_q_data[7]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx1_i_data[7]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx1_i_data[15]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx1_q_data[9]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx1_q_data[15]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx2_i_data[15]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx2_i_data[9]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx2_q_data[9]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx2_q_data[15]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx1_q_data[2]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx1_i_data[2]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx1_i_data[10]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx1_q_data[10]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx2_i_data[2]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx2_i_data[10]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx2_q_data[2]}]
|
||||
set_property MARK_DEBUG true [get_nets {rx2_q_data[10]}]
|
||||
|
||||
set_property MARK_DEBUG true [get_nets {tx1_i_data[4]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx1_i_data[12]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx1_q_data[4]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx1_q_data[12]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx2_i_data[12]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx2_i_data[4]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx2_q_data[4]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx2_q_data[12]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx1_q_data[1]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx1_i_data[1]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx1_i_data[8]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx1_q_data[8]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx2_i_data[1]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx2_i_data[8]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx2_q_data[1]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx2_q_data[8]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx1_i_data[2]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx1_i_data[10]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx1_q_data[2]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx1_q_data[10]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx2_i_data[2]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx2_i_data[10]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx2_q_data[2]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx2_q_data[10]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx1_i_data[15]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx1_i_data[9]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx1_q_data[9]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx1_q_data[15]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx2_i_data[9]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx2_i_data[15]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx2_q_data[9]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx2_q_data[15]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx1_q_data[7]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx1_i_data[7]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx1_q_data[0]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx1_i_data[0]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx2_i_data[0]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx2_i_data[7]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx2_q_data[0]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx2_q_data[7]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx1_i_data[5]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx1_i_data[13]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx1_q_data[5]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx1_q_data[13]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx2_i_data[13]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx2_i_data[5]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx2_q_data[5]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx2_q_data[13]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx1_i_data[14]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx1_i_data[6]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx1_q_data[6]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx1_q_data[14]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx2_i_data[6]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx2_i_data[14]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx2_q_data[6]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx2_q_data[14]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx1_i_data[3]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx1_i_data[11]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx1_q_data[3]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx1_q_data[11]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx2_i_data[11]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx2_i_data[3]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx2_q_data[3]}]
|
||||
set_property MARK_DEBUG true [get_nets {tx2_q_data[11]}]
|
||||
|
||||
set_property MARK_DEBUG true [get_nets system_top_i/CE_1]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[1]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[4]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[15]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[16]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[17]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[19]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[24]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[31]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[3]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[5]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[6]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[7]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[10]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[18]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[22]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[2]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[0]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[8]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[29]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[9]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[12]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[30]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[13]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[20]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[21]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[27]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[11]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[14]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[23]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[25]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[26]}]
|
||||
set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[28]}]
|
||||
create_debug_core u_ila_0 ila
|
||||
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
|
||||
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
|
||||
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
|
||||
set_property C_DATA_DEPTH 8192 [get_debug_cores u_ila_0]
|
||||
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
|
||||
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
|
||||
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
|
||||
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/clk]
|
||||
connect_debug_port u_ila_0/clk [get_nets [list system_top_i/mig_7series_0/u_system_top_mig_7series_0_0_mig/u_ddr3_infrastructure/CLK]]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
|
||||
set_property port_width 26 [get_debug_ports u_ila_0/probe0]
|
||||
connect_debug_port u_ila_0/probe0 [get_nets [list {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[0]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[1]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[2]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[3]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[4]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[5]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[6]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[7]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[8]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[9]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[10]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[11]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[12]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[13]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[14]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[15]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[16]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[17]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[18]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[19]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[20]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[21]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[22]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[23]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[24]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[25]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
|
||||
set_property port_width 64 [get_debug_ports u_ila_0/probe1]
|
||||
connect_debug_port u_ila_0/probe1 [get_nets [list {system_top_i/GPIO_0_0_tri_o[0]} {system_top_i/GPIO_0_0_tri_o[1]} {system_top_i/GPIO_0_0_tri_o[2]} {system_top_i/GPIO_0_0_tri_o[3]} {system_top_i/GPIO_0_0_tri_o[4]} {system_top_i/GPIO_0_0_tri_o[5]} {system_top_i/GPIO_0_0_tri_o[6]} {system_top_i/GPIO_0_0_tri_o[7]} {system_top_i/GPIO_0_0_tri_o[8]} {system_top_i/GPIO_0_0_tri_o[9]} {system_top_i/GPIO_0_0_tri_o[10]} {system_top_i/GPIO_0_0_tri_o[11]} {system_top_i/GPIO_0_0_tri_o[12]} {system_top_i/GPIO_0_0_tri_o[13]} {system_top_i/GPIO_0_0_tri_o[14]} {system_top_i/GPIO_0_0_tri_o[15]} {system_top_i/GPIO_0_0_tri_o[16]} {system_top_i/GPIO_0_0_tri_o[17]} {system_top_i/GPIO_0_0_tri_o[18]} {system_top_i/GPIO_0_0_tri_o[19]} {system_top_i/GPIO_0_0_tri_o[20]} {system_top_i/GPIO_0_0_tri_o[21]} {system_top_i/GPIO_0_0_tri_o[22]} {system_top_i/GPIO_0_0_tri_o[23]} {system_top_i/GPIO_0_0_tri_o[24]} {system_top_i/GPIO_0_0_tri_o[25]} {system_top_i/GPIO_0_0_tri_o[26]} {system_top_i/GPIO_0_0_tri_o[27]} {system_top_i/GPIO_0_0_tri_o[28]} {system_top_i/GPIO_0_0_tri_o[29]} {system_top_i/GPIO_0_0_tri_o[30]} {system_top_i/GPIO_0_0_tri_o[31]} {system_top_i/GPIO_0_0_tri_o[32]} {system_top_i/GPIO_0_0_tri_o[33]} {system_top_i/GPIO_0_0_tri_o[34]} {system_top_i/GPIO_0_0_tri_o[35]} {system_top_i/GPIO_0_0_tri_o[36]} {system_top_i/GPIO_0_0_tri_o[37]} {system_top_i/GPIO_0_0_tri_o[38]} {system_top_i/GPIO_0_0_tri_o[39]} {system_top_i/GPIO_0_0_tri_o[40]} {system_top_i/GPIO_0_0_tri_o[41]} {system_top_i/GPIO_0_0_tri_o[42]} {system_top_i/GPIO_0_0_tri_o[43]} {system_top_i/GPIO_0_0_tri_o[44]} {system_top_i/GPIO_0_0_tri_o[45]} {system_top_i/GPIO_0_0_tri_o[46]} {system_top_i/GPIO_0_0_tri_o[47]} {system_top_i/GPIO_0_0_tri_o[48]} {system_top_i/GPIO_0_0_tri_o[49]} {system_top_i/GPIO_0_0_tri_o[50]} {system_top_i/GPIO_0_0_tri_o[51]} {system_top_i/GPIO_0_0_tri_o[52]} {system_top_i/GPIO_0_0_tri_o[53]} {system_top_i/GPIO_0_0_tri_o[54]} {system_top_i/GPIO_0_0_tri_o[55]} {system_top_i/GPIO_0_0_tri_o[56]} {system_top_i/GPIO_0_0_tri_o[57]} {system_top_i/GPIO_0_0_tri_o[58]} {system_top_i/GPIO_0_0_tri_o[59]} {system_top_i/GPIO_0_0_tri_o[60]} {system_top_i/GPIO_0_0_tri_o[61]} {system_top_i/GPIO_0_0_tri_o[62]} {system_top_i/GPIO_0_0_tri_o[63]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
|
||||
set_property port_width 64 [get_debug_ports u_ila_0/probe2]
|
||||
connect_debug_port u_ila_0/probe2 [get_nets [list {system_top_i/GPIO_0_0_tri_t[0]} {system_top_i/GPIO_0_0_tri_t[1]} {system_top_i/GPIO_0_0_tri_t[2]} {system_top_i/GPIO_0_0_tri_t[3]} {system_top_i/GPIO_0_0_tri_t[4]} {system_top_i/GPIO_0_0_tri_t[5]} {system_top_i/GPIO_0_0_tri_t[6]} {system_top_i/GPIO_0_0_tri_t[7]} {system_top_i/GPIO_0_0_tri_t[8]} {system_top_i/GPIO_0_0_tri_t[9]} {system_top_i/GPIO_0_0_tri_t[10]} {system_top_i/GPIO_0_0_tri_t[11]} {system_top_i/GPIO_0_0_tri_t[12]} {system_top_i/GPIO_0_0_tri_t[13]} {system_top_i/GPIO_0_0_tri_t[14]} {system_top_i/GPIO_0_0_tri_t[15]} {system_top_i/GPIO_0_0_tri_t[16]} {system_top_i/GPIO_0_0_tri_t[17]} {system_top_i/GPIO_0_0_tri_t[18]} {system_top_i/GPIO_0_0_tri_t[19]} {system_top_i/GPIO_0_0_tri_t[20]} {system_top_i/GPIO_0_0_tri_t[21]} {system_top_i/GPIO_0_0_tri_t[22]} {system_top_i/GPIO_0_0_tri_t[23]} {system_top_i/GPIO_0_0_tri_t[24]} {system_top_i/GPIO_0_0_tri_t[25]} {system_top_i/GPIO_0_0_tri_t[26]} {system_top_i/GPIO_0_0_tri_t[27]} {system_top_i/GPIO_0_0_tri_t[28]} {system_top_i/GPIO_0_0_tri_t[29]} {system_top_i/GPIO_0_0_tri_t[30]} {system_top_i/GPIO_0_0_tri_t[31]} {system_top_i/GPIO_0_0_tri_t[32]} {system_top_i/GPIO_0_0_tri_t[33]} {system_top_i/GPIO_0_0_tri_t[34]} {system_top_i/GPIO_0_0_tri_t[35]} {system_top_i/GPIO_0_0_tri_t[36]} {system_top_i/GPIO_0_0_tri_t[37]} {system_top_i/GPIO_0_0_tri_t[38]} {system_top_i/GPIO_0_0_tri_t[39]} {system_top_i/GPIO_0_0_tri_t[40]} {system_top_i/GPIO_0_0_tri_t[41]} {system_top_i/GPIO_0_0_tri_t[42]} {system_top_i/GPIO_0_0_tri_t[43]} {system_top_i/GPIO_0_0_tri_t[44]} {system_top_i/GPIO_0_0_tri_t[45]} {system_top_i/GPIO_0_0_tri_t[46]} {system_top_i/GPIO_0_0_tri_t[47]} {system_top_i/GPIO_0_0_tri_t[48]} {system_top_i/GPIO_0_0_tri_t[49]} {system_top_i/GPIO_0_0_tri_t[50]} {system_top_i/GPIO_0_0_tri_t[51]} {system_top_i/GPIO_0_0_tri_t[52]} {system_top_i/GPIO_0_0_tri_t[53]} {system_top_i/GPIO_0_0_tri_t[54]} {system_top_i/GPIO_0_0_tri_t[55]} {system_top_i/GPIO_0_0_tri_t[56]} {system_top_i/GPIO_0_0_tri_t[57]} {system_top_i/GPIO_0_0_tri_t[58]} {system_top_i/GPIO_0_0_tri_t[59]} {system_top_i/GPIO_0_0_tri_t[60]} {system_top_i/GPIO_0_0_tri_t[61]} {system_top_i/GPIO_0_0_tri_t[62]} {system_top_i/GPIO_0_0_tri_t[63]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
|
||||
set_property port_width 13 [get_debug_ports u_ila_0/probe3]
|
||||
connect_debug_port u_ila_0/probe3 [get_nets [list {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[0]} {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[1]} {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[2]} {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[3]} {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[4]} {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[5]} {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[6]} {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[7]} {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[8]} {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[9]} {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[10]} {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[11]} {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[12]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe4]
|
||||
connect_debug_port u_ila_0/probe4 [get_nets [list system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/capture_cdc]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe5]
|
||||
connect_debug_port u_ila_0/probe5 [get_nets [list NRST_OBUF]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe6]
|
||||
connect_debug_port u_ila_0/probe6 [get_nets [list system_top_i/blk_mem_gen_0/U0/rstb_busy]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe7]
|
||||
connect_debug_port u_ila_0/probe7 [get_nets [list system_top_i/SPI_0_0_io0_i]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe8]
|
||||
connect_debug_port u_ila_0/probe8 [get_nets [list system_top_i/SPI_0_0_io0_o]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe9]
|
||||
connect_debug_port u_ila_0/probe9 [get_nets [list system_top_i/SPI_0_0_io0_t]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe10]
|
||||
connect_debug_port u_ila_0/probe10 [get_nets [list system_top_i/SPI_0_0_io1_i]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe11]
|
||||
connect_debug_port u_ila_0/probe11 [get_nets [list system_top_i/SPI_0_0_io1_o]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe12]
|
||||
connect_debug_port u_ila_0/probe12 [get_nets [list system_top_i/SPI_0_0_io1_t]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe13]
|
||||
connect_debug_port u_ila_0/probe13 [get_nets [list system_top_i/SPI_0_0_sck_i]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe14]
|
||||
connect_debug_port u_ila_0/probe14 [get_nets [list system_top_i/SPI_0_0_sck_o]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe15]
|
||||
connect_debug_port u_ila_0/probe15 [get_nets [list system_top_i/SPI_0_0_sck_t]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe16]
|
||||
connect_debug_port u_ila_0/probe16 [get_nets [list system_top_i/SPI_0_0_ss1_o]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe17]
|
||||
connect_debug_port u_ila_0/probe17 [get_nets [list system_top_i/SPI_0_0_ss2_o]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe18]
|
||||
connect_debug_port u_ila_0/probe18 [get_nets [list system_top_i/SPI_0_0_ss_i]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe19]
|
||||
connect_debug_port u_ila_0/probe19 [get_nets [list system_top_i/SPI_0_0_ss_o]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe20]
|
||||
connect_debug_port u_ila_0/probe20 [get_nets [list system_top_i/SPI_0_0_ss_t]]
|
||||
create_debug_core u_ila_1 ila
|
||||
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_1]
|
||||
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_1]
|
||||
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_1]
|
||||
set_property C_DATA_DEPTH 8192 [get_debug_cores u_ila_1]
|
||||
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_1]
|
||||
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_1]
|
||||
set_property C_TRIGIN_EN false [get_debug_cores u_ila_1]
|
||||
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_1]
|
||||
set_property port_width 1 [get_debug_ports u_ila_1/clk]
|
||||
connect_debug_port u_ila_1/clk [get_nets [list cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/CLK]]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe0]
|
||||
set_property port_width 8 [get_debug_ports u_ila_1/probe0]
|
||||
connect_debug_port u_ila_1/probe0 [get_nets [list {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_neg[0]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_neg[1]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_neg[2]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_neg[3]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_neg[4]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_neg[5]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_neg[6]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_neg[7]}]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe1]
|
||||
set_property port_width 16 [get_debug_ports u_ila_1/probe1]
|
||||
connect_debug_port u_ila_1/probe1 [get_nets [list {rx1_i_data[0]} {rx1_i_data[1]} {rx1_i_data[2]} {rx1_i_data[3]} {rx1_i_data[4]} {rx1_i_data[5]} {rx1_i_data[6]} {rx1_i_data[7]} {rx1_i_data[8]} {rx1_i_data[9]} {rx1_i_data[10]} {rx1_i_data[11]} {rx1_i_data[12]} {rx1_i_data[13]} {rx1_i_data[14]} {rx1_i_data[15]}]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe2]
|
||||
set_property port_width 8 [get_debug_ports u_ila_1/probe2]
|
||||
connect_debug_port u_ila_1/probe2 [get_nets [list {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_pos[0]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_pos[1]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_pos[2]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_pos[3]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_pos[4]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_pos[5]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_pos[6]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_pos[7]}]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe3]
|
||||
set_property port_width 8 [get_debug_ports u_ila_1/probe3]
|
||||
connect_debug_port u_ila_1/probe3 [get_nets [list {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_pos[0]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_pos[1]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_pos[2]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_pos[3]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_pos[4]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_pos[5]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_pos[6]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_pos[7]}]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe4]
|
||||
set_property port_width 16 [get_debug_ports u_ila_1/probe4]
|
||||
connect_debug_port u_ila_1/probe4 [get_nets [list {tx1_i_data[0]} {tx1_i_data[1]} {tx1_i_data[2]} {tx1_i_data[3]} {tx1_i_data[4]} {tx1_i_data[5]} {tx1_i_data[6]} {tx1_i_data[7]} {tx1_i_data[8]} {tx1_i_data[9]} {tx1_i_data[10]} {tx1_i_data[11]} {tx1_i_data[12]} {tx1_i_data[13]} {tx1_i_data[14]} {tx1_i_data[15]}]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe5]
|
||||
set_property port_width 16 [get_debug_ports u_ila_1/probe5]
|
||||
connect_debug_port u_ila_1/probe5 [get_nets [list {tx1_q_data[0]} {tx1_q_data[1]} {tx1_q_data[2]} {tx1_q_data[3]} {tx1_q_data[4]} {tx1_q_data[5]} {tx1_q_data[6]} {tx1_q_data[7]} {tx1_q_data[8]} {tx1_q_data[9]} {tx1_q_data[10]} {tx1_q_data[11]} {tx1_q_data[12]} {tx1_q_data[13]} {tx1_q_data[14]} {tx1_q_data[15]}]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe6]
|
||||
set_property port_width 16 [get_debug_ports u_ila_1/probe6]
|
||||
connect_debug_port u_ila_1/probe6 [get_nets [list {rx1_q_data[0]} {rx1_q_data[1]} {rx1_q_data[2]} {rx1_q_data[3]} {rx1_q_data[4]} {rx1_q_data[5]} {rx1_q_data[6]} {rx1_q_data[7]} {rx1_q_data[8]} {rx1_q_data[9]} {rx1_q_data[10]} {rx1_q_data[11]} {rx1_q_data[12]} {rx1_q_data[13]} {rx1_q_data[14]} {rx1_q_data[15]}]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe7]
|
||||
set_property port_width 8 [get_debug_ports u_ila_1/probe7]
|
||||
connect_debug_port u_ila_1/probe7 [get_nets [list {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_neg[0]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_neg[1]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_neg[2]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_neg[3]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_neg[4]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_neg[5]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_neg[6]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_neg[7]}]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe8]
|
||||
set_property port_width 32 [get_debug_ports u_ila_1/probe8]
|
||||
connect_debug_port u_ila_1/probe8 [get_nets [list {system_top_i/c_counter_binary_1_Q[0]} {system_top_i/c_counter_binary_1_Q[1]} {system_top_i/c_counter_binary_1_Q[2]} {system_top_i/c_counter_binary_1_Q[3]} {system_top_i/c_counter_binary_1_Q[4]} {system_top_i/c_counter_binary_1_Q[5]} {system_top_i/c_counter_binary_1_Q[6]} {system_top_i/c_counter_binary_1_Q[7]} {system_top_i/c_counter_binary_1_Q[8]} {system_top_i/c_counter_binary_1_Q[9]} {system_top_i/c_counter_binary_1_Q[10]} {system_top_i/c_counter_binary_1_Q[11]} {system_top_i/c_counter_binary_1_Q[12]} {system_top_i/c_counter_binary_1_Q[13]} {system_top_i/c_counter_binary_1_Q[14]} {system_top_i/c_counter_binary_1_Q[15]} {system_top_i/c_counter_binary_1_Q[16]} {system_top_i/c_counter_binary_1_Q[17]} {system_top_i/c_counter_binary_1_Q[18]} {system_top_i/c_counter_binary_1_Q[19]} {system_top_i/c_counter_binary_1_Q[20]} {system_top_i/c_counter_binary_1_Q[21]} {system_top_i/c_counter_binary_1_Q[22]} {system_top_i/c_counter_binary_1_Q[23]} {system_top_i/c_counter_binary_1_Q[24]} {system_top_i/c_counter_binary_1_Q[25]} {system_top_i/c_counter_binary_1_Q[26]} {system_top_i/c_counter_binary_1_Q[27]} {system_top_i/c_counter_binary_1_Q[28]} {system_top_i/c_counter_binary_1_Q[29]} {system_top_i/c_counter_binary_1_Q[30]} {system_top_i/c_counter_binary_1_Q[31]}]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe9]
|
||||
set_property port_width 1 [get_debug_ports u_ila_1/probe9]
|
||||
connect_debug_port u_ila_1/probe9 [get_nets [list system_top_i/CE]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe10]
|
||||
set_property port_width 1 [get_debug_ports u_ila_1/probe10]
|
||||
connect_debug_port u_ila_1/probe10 [get_nets [list cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FRAME_neg]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe11]
|
||||
set_property port_width 1 [get_debug_ports u_ila_1/probe11]
|
||||
connect_debug_port u_ila_1/probe11 [get_nets [list cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FRAME_pos]]
|
||||
create_debug_core u_ila_2 ila
|
||||
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_2]
|
||||
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_2]
|
||||
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_2]
|
||||
set_property C_DATA_DEPTH 8192 [get_debug_cores u_ila_2]
|
||||
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_2]
|
||||
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_2]
|
||||
set_property C_TRIGIN_EN false [get_debug_cores u_ila_2]
|
||||
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_2]
|
||||
set_property port_width 1 [get_debug_ports u_ila_2/clk]
|
||||
connect_debug_port u_ila_2/clk [get_nets [list cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/CLK]]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe0]
|
||||
set_property port_width 16 [get_debug_ports u_ila_2/probe0]
|
||||
connect_debug_port u_ila_2/probe0 [get_nets [list {rx2_i_data[0]} {rx2_i_data[1]} {rx2_i_data[2]} {rx2_i_data[3]} {rx2_i_data[4]} {rx2_i_data[5]} {rx2_i_data[6]} {rx2_i_data[7]} {rx2_i_data[8]} {rx2_i_data[9]} {rx2_i_data[10]} {rx2_i_data[11]} {rx2_i_data[12]} {rx2_i_data[13]} {rx2_i_data[14]} {rx2_i_data[15]}]]
|
||||
create_debug_port u_ila_2 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe1]
|
||||
set_property port_width 8 [get_debug_ports u_ila_2/probe1]
|
||||
connect_debug_port u_ila_2/probe1 [get_nets [list {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_neg[0]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_neg[1]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_neg[2]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_neg[3]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_neg[4]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_neg[5]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_neg[6]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_neg[7]}]]
|
||||
create_debug_port u_ila_2 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe2]
|
||||
set_property port_width 8 [get_debug_ports u_ila_2/probe2]
|
||||
connect_debug_port u_ila_2/probe2 [get_nets [list {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_neg[0]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_neg[1]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_neg[2]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_neg[3]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_neg[4]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_neg[5]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_neg[6]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_neg[7]}]]
|
||||
create_debug_port u_ila_2 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe3]
|
||||
set_property port_width 16 [get_debug_ports u_ila_2/probe3]
|
||||
connect_debug_port u_ila_2/probe3 [get_nets [list {tx2_i_data[0]} {tx2_i_data[1]} {tx2_i_data[2]} {tx2_i_data[3]} {tx2_i_data[4]} {tx2_i_data[5]} {tx2_i_data[6]} {tx2_i_data[7]} {tx2_i_data[8]} {tx2_i_data[9]} {tx2_i_data[10]} {tx2_i_data[11]} {tx2_i_data[12]} {tx2_i_data[13]} {tx2_i_data[14]} {tx2_i_data[15]}]]
|
||||
create_debug_port u_ila_2 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe4]
|
||||
set_property port_width 32 [get_debug_ports u_ila_2/probe4]
|
||||
connect_debug_port u_ila_2/probe4 [get_nets [list {system_top_i/c_counter_binary_2_Q[0]} {system_top_i/c_counter_binary_2_Q[1]} {system_top_i/c_counter_binary_2_Q[2]} {system_top_i/c_counter_binary_2_Q[3]} {system_top_i/c_counter_binary_2_Q[4]} {system_top_i/c_counter_binary_2_Q[5]} {system_top_i/c_counter_binary_2_Q[6]} {system_top_i/c_counter_binary_2_Q[7]} {system_top_i/c_counter_binary_2_Q[8]} {system_top_i/c_counter_binary_2_Q[9]} {system_top_i/c_counter_binary_2_Q[10]} {system_top_i/c_counter_binary_2_Q[11]} {system_top_i/c_counter_binary_2_Q[12]} {system_top_i/c_counter_binary_2_Q[13]} {system_top_i/c_counter_binary_2_Q[14]} {system_top_i/c_counter_binary_2_Q[15]} {system_top_i/c_counter_binary_2_Q[16]} {system_top_i/c_counter_binary_2_Q[17]} {system_top_i/c_counter_binary_2_Q[18]} {system_top_i/c_counter_binary_2_Q[19]} {system_top_i/c_counter_binary_2_Q[20]} {system_top_i/c_counter_binary_2_Q[21]} {system_top_i/c_counter_binary_2_Q[22]} {system_top_i/c_counter_binary_2_Q[23]} {system_top_i/c_counter_binary_2_Q[24]} {system_top_i/c_counter_binary_2_Q[25]} {system_top_i/c_counter_binary_2_Q[26]} {system_top_i/c_counter_binary_2_Q[27]} {system_top_i/c_counter_binary_2_Q[28]} {system_top_i/c_counter_binary_2_Q[29]} {system_top_i/c_counter_binary_2_Q[30]} {system_top_i/c_counter_binary_2_Q[31]}]]
|
||||
create_debug_port u_ila_2 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe5]
|
||||
set_property port_width 16 [get_debug_ports u_ila_2/probe5]
|
||||
connect_debug_port u_ila_2/probe5 [get_nets [list {tx2_q_data[0]} {tx2_q_data[1]} {tx2_q_data[2]} {tx2_q_data[3]} {tx2_q_data[4]} {tx2_q_data[5]} {tx2_q_data[6]} {tx2_q_data[7]} {tx2_q_data[8]} {tx2_q_data[9]} {tx2_q_data[10]} {tx2_q_data[11]} {tx2_q_data[12]} {tx2_q_data[13]} {tx2_q_data[14]} {tx2_q_data[15]}]]
|
||||
create_debug_port u_ila_2 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe6]
|
||||
set_property port_width 16 [get_debug_ports u_ila_2/probe6]
|
||||
connect_debug_port u_ila_2/probe6 [get_nets [list {rx2_q_data[0]} {rx2_q_data[1]} {rx2_q_data[2]} {rx2_q_data[3]} {rx2_q_data[4]} {rx2_q_data[5]} {rx2_q_data[6]} {rx2_q_data[7]} {rx2_q_data[8]} {rx2_q_data[9]} {rx2_q_data[10]} {rx2_q_data[11]} {rx2_q_data[12]} {rx2_q_data[13]} {rx2_q_data[14]} {rx2_q_data[15]}]]
|
||||
create_debug_port u_ila_2 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe7]
|
||||
set_property port_width 8 [get_debug_ports u_ila_2/probe7]
|
||||
connect_debug_port u_ila_2/probe7 [get_nets [list {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_pos[0]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_pos[1]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_pos[2]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_pos[3]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_pos[4]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_pos[5]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_pos[6]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_pos[7]}]]
|
||||
create_debug_port u_ila_2 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe8]
|
||||
set_property port_width 8 [get_debug_ports u_ila_2/probe8]
|
||||
connect_debug_port u_ila_2/probe8 [get_nets [list {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_pos[0]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_pos[1]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_pos[2]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_pos[3]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_pos[4]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_pos[5]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_pos[6]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_pos[7]}]]
|
||||
create_debug_port u_ila_2 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe9]
|
||||
set_property port_width 1 [get_debug_ports u_ila_2/probe9]
|
||||
connect_debug_port u_ila_2/probe9 [get_nets [list system_top_i/CE_1]]
|
||||
create_debug_port u_ila_2 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe10]
|
||||
set_property port_width 1 [get_debug_ports u_ila_2/probe10]
|
||||
connect_debug_port u_ila_2/probe10 [get_nets [list cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FRAME_neg]]
|
||||
create_debug_port u_ila_2 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe11]
|
||||
set_property port_width 1 [get_debug_ports u_ila_2/probe11]
|
||||
connect_debug_port u_ila_2/probe11 [get_nets [list cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FRAME_pos]]
|
||||
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
|
||||
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
|
||||
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
|
||||
connect_debug_port dbg_hub/clk [get_nets ui_clk]
|
||||
@@ -0,0 +1,86 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2022/05/19 13:23:50
|
||||
// Design Name:
|
||||
// Module Name: tb
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module tb(
|
||||
|
||||
);
|
||||
reg aclk,S_AXI_ACLK;
|
||||
|
||||
reg[31:0] slv_reg0,slv_reg1;
|
||||
|
||||
|
||||
initial begin
|
||||
aclk = 0;
|
||||
S_AXI_ACLK = 0;
|
||||
#100 slv_reg0 = 0;
|
||||
#100 slv_reg1 = 8192;
|
||||
#100 slv_reg0 = 1;
|
||||
end
|
||||
|
||||
always #2 aclk=~aclk;
|
||||
always #1 S_AXI_ACLK=~S_AXI_ACLK;
|
||||
|
||||
|
||||
wire capture_cdc;
|
||||
wire [25:0] length_cdc;
|
||||
|
||||
xpm_cdc_array_single #(
|
||||
.DEST_SYNC_FF(4), // DECIMAL; range: 2-10
|
||||
.INIT_SYNC_FF(0), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values
|
||||
.SIM_ASSERT_CHK(0), // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
|
||||
.SRC_INPUT_REG(1), // DECIMAL; 0=do not register input, 1=register input
|
||||
.WIDTH(1) // DECIMAL; range: 1-1024
|
||||
)
|
||||
xpm_cdc_array_single_inst0 (
|
||||
.dest_out(capture_cdc), // WIDTH-bit output: src_in synchronized to the destination clock domain. This
|
||||
// output is registered.
|
||||
|
||||
.dest_clk(aclk), // 1-bit input: Clock signal for the destination clock domain.
|
||||
.src_clk(S_AXI_ACLK), // 1-bit input: optional; required when SRC_INPUT_REG = 1
|
||||
.src_in(slv_reg0[0]) // WIDTH-bit input: Input single-bit array to be synchronized to destination clock
|
||||
// domain. It is assumed that each bit of the array is unrelated to the others. This
|
||||
// is reflected in the constraints applied to this macro. To transfer a binary value
|
||||
// losslessly across the two clock domains, use the XPM_CDC_GRAY macro instead.
|
||||
|
||||
);
|
||||
|
||||
xpm_cdc_array_single #(
|
||||
.DEST_SYNC_FF(4), // DECIMAL; range: 2-10
|
||||
.INIT_SYNC_FF(0), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values
|
||||
.SIM_ASSERT_CHK(0), // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
|
||||
.SRC_INPUT_REG(1), // DECIMAL; 0=do not register input, 1=register input
|
||||
.WIDTH(26) // DECIMAL; range: 1-1024
|
||||
)
|
||||
xpm_cdc_array_single_inst1 (
|
||||
.dest_out(length_cdc), // WIDTH-bit output: src_in synchronized to the destination clock domain. This
|
||||
// output is registered.
|
||||
|
||||
.dest_clk(aclk), // 1-bit input: Clock signal for the destination clock domain.
|
||||
.src_clk(S_AXI_ACLK), // 1-bit input: optional; required when SRC_INPUT_REG = 1
|
||||
.src_in(slv_reg1[25:0]) // WIDTH-bit input: Input single-bit array to be synchronized to destination clock
|
||||
// domain. It is assumed that each bit of the array is unrelated to the others. This
|
||||
// is reflected in the constraints applied to this macro. To transfer a binary value
|
||||
// losslessly across the two clock domains, use the XPM_CDC_GRAY macro instead.
|
||||
|
||||
);
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,11 @@
|
||||
{
|
||||
"design": {
|
||||
"design_info": {
|
||||
"boundary_crc": "0x0",
|
||||
"name": "bin_rom",
|
||||
"synth_flow_mode": "Hierarchical",
|
||||
"tool_version": "2018.3"
|
||||
},
|
||||
"design_tree": {}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,11 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<Root MajorVersion="0" MinorVersion="36">
|
||||
<CompositeFile CompositeFileTopName="bin_rom" CanBeSetAsTop="false" CanDisplayChildGraph="true">
|
||||
<Description>Composite Fileset</Description>
|
||||
<Generation Name="SYNTHESIS" State="STALE" Timestamp="1700708194"/>
|
||||
<Generation Name="IMPLEMENTATION" State="STALE" Timestamp="1700708194"/>
|
||||
<Generation Name="SIMULATION" State="STALE" Timestamp="1700708194"/>
|
||||
<Generation Name="HW_HANDOFF" State="STALE" Timestamp="1700708194"/>
|
||||
<FileCollection Name="SOURCES" Type="SOURCES"/>
|
||||
</CompositeFile>
|
||||
</Root>
|
||||
+1036
File diff suppressed because it is too large
Load Diff
+19999
File diff suppressed because it is too large
Load Diff
+10
@@ -0,0 +1,10 @@
|
||||
|
||||
|
||||
OPTION psf_version = 2.1;
|
||||
|
||||
BEGIN DRIVER Axis_adc_data_packer
|
||||
OPTION supported_peripherals = (Axis_adc_data_packer);
|
||||
OPTION copyfiles = all;
|
||||
OPTION VERSION = 1.0;
|
||||
OPTION NAME = Axis_adc_data_packer;
|
||||
END DRIVER
|
||||
+5
@@ -0,0 +1,5 @@
|
||||
|
||||
|
||||
proc generate {drv_handle} {
|
||||
xdefine_include_file $drv_handle "xparameters.h" "Axis_adc_data_packer" "NUM_INSTANCES" "DEVICE_ID" "C_S00_AXI_BASEADDR" "C_S00_AXI_HIGHADDR"
|
||||
}
|
||||
+6
@@ -0,0 +1,6 @@
|
||||
|
||||
|
||||
/***************************** Include Files *******************************/
|
||||
#include "Axis_adc_data_packer.h"
|
||||
|
||||
/************************** Function Definitions ***************************/
|
||||
+79
@@ -0,0 +1,79 @@
|
||||
|
||||
#ifndef AXIS_ADC_DATA_PACKER_H
|
||||
#define AXIS_ADC_DATA_PACKER_H
|
||||
|
||||
|
||||
/****************** Include Files ********************/
|
||||
#include "xil_types.h"
|
||||
#include "xstatus.h"
|
||||
|
||||
#define AXIS_ADC_DATA_PACKER_S00_AXI_SLV_REG0_OFFSET 0
|
||||
#define AXIS_ADC_DATA_PACKER_S00_AXI_SLV_REG1_OFFSET 4
|
||||
#define AXIS_ADC_DATA_PACKER_S00_AXI_SLV_REG2_OFFSET 8
|
||||
#define AXIS_ADC_DATA_PACKER_S00_AXI_SLV_REG3_OFFSET 12
|
||||
|
||||
|
||||
/**************************** Type Definitions *****************************/
|
||||
/**
|
||||
*
|
||||
* Write a value to a AXIS_ADC_DATA_PACKER register. A 32 bit write is performed.
|
||||
* If the component is implemented in a smaller width, only the least
|
||||
* significant data is written.
|
||||
*
|
||||
* @param BaseAddress is the base address of the AXIS_ADC_DATA_PACKERdevice.
|
||||
* @param RegOffset is the register offset from the base to write to.
|
||||
* @param Data is the data written to the register.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note
|
||||
* C-style signature:
|
||||
* void AXIS_ADC_DATA_PACKER_mWriteReg(u32 BaseAddress, unsigned RegOffset, u32 Data)
|
||||
*
|
||||
*/
|
||||
#define AXIS_ADC_DATA_PACKER_mWriteReg(BaseAddress, RegOffset, Data) \
|
||||
Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data))
|
||||
|
||||
/**
|
||||
*
|
||||
* Read a value from a AXIS_ADC_DATA_PACKER register. A 32 bit read is performed.
|
||||
* If the component is implemented in a smaller width, only the least
|
||||
* significant data is read from the register. The most significant data
|
||||
* will be read as 0.
|
||||
*
|
||||
* @param BaseAddress is the base address of the AXIS_ADC_DATA_PACKER device.
|
||||
* @param RegOffset is the register offset from the base to write to.
|
||||
*
|
||||
* @return Data is the data from the register.
|
||||
*
|
||||
* @note
|
||||
* C-style signature:
|
||||
* u32 AXIS_ADC_DATA_PACKER_mReadReg(u32 BaseAddress, unsigned RegOffset)
|
||||
*
|
||||
*/
|
||||
#define AXIS_ADC_DATA_PACKER_mReadReg(BaseAddress, RegOffset) \
|
||||
Xil_In32((BaseAddress) + (RegOffset))
|
||||
|
||||
/************************** Function Prototypes ****************************/
|
||||
/**
|
||||
*
|
||||
* Run a self-test on the driver/device. Note this may be a destructive test if
|
||||
* resets of the device are performed.
|
||||
*
|
||||
* If the hardware system is not built correctly, this function may never
|
||||
* return to the caller.
|
||||
*
|
||||
* @param baseaddr_p is the base address of the AXIS_ADC_DATA_PACKER instance to be worked on.
|
||||
*
|
||||
* @return
|
||||
*
|
||||
* - XST_SUCCESS if all self-test code passed
|
||||
* - XST_FAILURE if any self-test code failed
|
||||
*
|
||||
* @note Caching must be turned off for this function to work.
|
||||
* @note Self test may fail if data memory and device are not on the same bus.
|
||||
*
|
||||
*/
|
||||
XStatus AXIS_ADC_DATA_PACKER_Reg_SelfTest(void * baseaddr_p);
|
||||
|
||||
#endif // AXIS_ADC_DATA_PACKER_H
|
||||
+60
@@ -0,0 +1,60 @@
|
||||
|
||||
/***************************** Include Files *******************************/
|
||||
#include "Axis_adc_data_packer.h"
|
||||
#include "xparameters.h"
|
||||
#include "stdio.h"
|
||||
#include "xil_io.h"
|
||||
|
||||
/************************** Constant Definitions ***************************/
|
||||
#define READ_WRITE_MUL_FACTOR 0x10
|
||||
|
||||
/************************** Function Definitions ***************************/
|
||||
/**
|
||||
*
|
||||
* Run a self-test on the driver/device. Note this may be a destructive test if
|
||||
* resets of the device are performed.
|
||||
*
|
||||
* If the hardware system is not built correctly, this function may never
|
||||
* return to the caller.
|
||||
*
|
||||
* @param baseaddr_p is the base address of the AXIS_ADC_DATA_PACKERinstance to be worked on.
|
||||
*
|
||||
* @return
|
||||
*
|
||||
* - XST_SUCCESS if all self-test code passed
|
||||
* - XST_FAILURE if any self-test code failed
|
||||
*
|
||||
* @note Caching must be turned off for this function to work.
|
||||
* @note Self test may fail if data memory and device are not on the same bus.
|
||||
*
|
||||
*/
|
||||
XStatus AXIS_ADC_DATA_PACKER_Reg_SelfTest(void * baseaddr_p)
|
||||
{
|
||||
u32 baseaddr;
|
||||
int write_loop_index;
|
||||
int read_loop_index;
|
||||
int Index;
|
||||
|
||||
baseaddr = (u32) baseaddr_p;
|
||||
|
||||
xil_printf("******************************\n\r");
|
||||
xil_printf("* User Peripheral Self Test\n\r");
|
||||
xil_printf("******************************\n\n\r");
|
||||
|
||||
/*
|
||||
* Write to user logic slave module register(s) and read back
|
||||
*/
|
||||
xil_printf("User logic slave module test...\n\r");
|
||||
|
||||
for (write_loop_index = 0 ; write_loop_index < 4; write_loop_index++)
|
||||
AXIS_ADC_DATA_PACKER_mWriteReg (baseaddr, write_loop_index*4, (write_loop_index+1)*READ_WRITE_MUL_FACTOR);
|
||||
for (read_loop_index = 0 ; read_loop_index < 4; read_loop_index++)
|
||||
if ( AXIS_ADC_DATA_PACKER_mReadReg (baseaddr, read_loop_index*4) != (read_loop_index+1)*READ_WRITE_MUL_FACTOR){
|
||||
xil_printf ("Error reading register value at address %x\n", (int)baseaddr + read_loop_index*4);
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
xil_printf(" - slave register write/read passed\n\n\r");
|
||||
|
||||
return XST_SUCCESS;
|
||||
}
|
||||
+26
@@ -0,0 +1,26 @@
|
||||
COMPILER=
|
||||
ARCHIVER=
|
||||
CP=cp
|
||||
COMPILER_FLAGS=
|
||||
EXTRA_COMPILER_FLAGS=
|
||||
LIB=libxil.a
|
||||
|
||||
RELEASEDIR=../../../lib
|
||||
INCLUDEDIR=../../../include
|
||||
INCLUDES=-I./. -I${INCLUDEDIR}
|
||||
|
||||
INCLUDEFILES=*.h
|
||||
LIBSOURCES=*.c
|
||||
OUTS = *.o
|
||||
|
||||
libs:
|
||||
echo "Compiling Axis_adc_data_packer..."
|
||||
$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
|
||||
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
|
||||
make clean
|
||||
|
||||
include:
|
||||
${CP} $(INCLUDEFILES) $(INCLUDEDIR)
|
||||
|
||||
clean:
|
||||
rm -rf ${OUTS}
|
||||
+197
@@ -0,0 +1,197 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: labnet.com:user:Axis_adc_data_packer:1.0
|
||||
// IP Revision: 9
|
||||
|
||||
(* X_CORE_INFO = "Axis_adc_data_packer_v1_0,Vivado 2024.1" *)
|
||||
(* CHECK_LICENSE_TYPE = "system_top_Axis_adc_data_packer_0_0,Axis_adc_data_packer_v1_0,{}" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module system_top_Axis_adc_data_packer_0_0 (
|
||||
aclk,
|
||||
aresetn,
|
||||
axis_tvalid,
|
||||
axis_tlast,
|
||||
axis_ready,
|
||||
axis_tdata,
|
||||
m_axis_tvalid,
|
||||
m_axis_tlast,
|
||||
m_axis_ready,
|
||||
m_axis_tdata,
|
||||
s00_axi_awaddr,
|
||||
s00_axi_awprot,
|
||||
s00_axi_awvalid,
|
||||
s00_axi_awready,
|
||||
s00_axi_wdata,
|
||||
s00_axi_wstrb,
|
||||
s00_axi_wvalid,
|
||||
s00_axi_wready,
|
||||
s00_axi_bresp,
|
||||
s00_axi_bvalid,
|
||||
s00_axi_bready,
|
||||
s00_axi_araddr,
|
||||
s00_axi_arprot,
|
||||
s00_axi_arvalid,
|
||||
s00_axi_arready,
|
||||
s00_axi_rdata,
|
||||
s00_axi_rresp,
|
||||
s00_axi_rvalid,
|
||||
s00_axi_rready,
|
||||
s00_axi_aclk,
|
||||
s00_axi_aresetn
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF axis:m_axis, ASSOCIATED_RESET aresetn, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN system_top_data_clk, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk CLK" *)
|
||||
input wire aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 aresetn RST" *)
|
||||
input wire aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 axis TVALID" *)
|
||||
input wire axis_tvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 axis TLAST" *)
|
||||
input wire axis_tlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 axis TREADY" *)
|
||||
output wire axis_ready;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME axis, TDATA_NUM_BYTES 8, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN system_top_data_clk, LAYERED_METADATA undef, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 axis TDATA" *)
|
||||
input wire [63 : 0] axis_tdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis TVALID" *)
|
||||
output wire m_axis_tvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis TLAST" *)
|
||||
output wire m_axis_tlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis TREADY" *)
|
||||
input wire m_axis_ready;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_axis, TDATA_NUM_BYTES 8, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN system_top_data_clk, LAYERED_METADATA undef, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis TDATA" *)
|
||||
output wire [63 : 0] m_axis_tdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR" *)
|
||||
input wire [3 : 0] s00_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT" *)
|
||||
input wire [2 : 0] s00_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID" *)
|
||||
input wire s00_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY" *)
|
||||
output wire s00_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA" *)
|
||||
input wire [31 : 0] s00_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB" *)
|
||||
input wire [3 : 0] s00_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID" *)
|
||||
input wire s00_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY" *)
|
||||
output wire s00_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP" *)
|
||||
output wire [1 : 0] s00_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID" *)
|
||||
output wire s00_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY" *)
|
||||
input wire s00_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR" *)
|
||||
input wire [3 : 0] s00_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT" *)
|
||||
input wire [2 : 0] s00_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID" *)
|
||||
input wire s00_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY" *)
|
||||
output wire s00_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA" *)
|
||||
output wire [31 : 0] s00_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP" *)
|
||||
output wire [1 : 0] s00_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID" *)
|
||||
output wire s00_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI, WIZ_DATA_WIDTH 32, WIZ_NUM_REG 4, SUPPORTS_NARROW_BURST 0, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 4, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN system_top_processing_syste\
|
||||
m7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *)
|
||||
input wire s00_axi_rready;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI_CLK, ASSOCIATED_BUSIF S00_AXI, ASSOCIATED_RESET s00_axi_aresetn, FREQ_HZ 1e+08, PHASE 0.000, CLK_DOMAIN system_top_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 S00_AXI_CLK CLK" *)
|
||||
input wire s00_axi_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 S00_AXI_RST RST" *)
|
||||
input wire s00_axi_aresetn;
|
||||
|
||||
Axis_adc_data_packer_v1_0 #(
|
||||
.C_S00_AXI_DATA_WIDTH(32), // Width of S_AXI data bus
|
||||
.C_S00_AXI_ADDR_WIDTH(4) // Width of S_AXI address bus
|
||||
) inst (
|
||||
.aclk(aclk),
|
||||
.aresetn(aresetn),
|
||||
.axis_tvalid(axis_tvalid),
|
||||
.axis_tlast(axis_tlast),
|
||||
.axis_ready(axis_ready),
|
||||
.axis_tdata(axis_tdata),
|
||||
.m_axis_tvalid(m_axis_tvalid),
|
||||
.m_axis_tlast(m_axis_tlast),
|
||||
.m_axis_ready(m_axis_ready),
|
||||
.m_axis_tdata(m_axis_tdata),
|
||||
.s00_axi_awaddr(s00_axi_awaddr),
|
||||
.s00_axi_awprot(s00_axi_awprot),
|
||||
.s00_axi_awvalid(s00_axi_awvalid),
|
||||
.s00_axi_awready(s00_axi_awready),
|
||||
.s00_axi_wdata(s00_axi_wdata),
|
||||
.s00_axi_wstrb(s00_axi_wstrb),
|
||||
.s00_axi_wvalid(s00_axi_wvalid),
|
||||
.s00_axi_wready(s00_axi_wready),
|
||||
.s00_axi_bresp(s00_axi_bresp),
|
||||
.s00_axi_bvalid(s00_axi_bvalid),
|
||||
.s00_axi_bready(s00_axi_bready),
|
||||
.s00_axi_araddr(s00_axi_araddr),
|
||||
.s00_axi_arprot(s00_axi_arprot),
|
||||
.s00_axi_arvalid(s00_axi_arvalid),
|
||||
.s00_axi_arready(s00_axi_arready),
|
||||
.s00_axi_rdata(s00_axi_rdata),
|
||||
.s00_axi_rresp(s00_axi_rresp),
|
||||
.s00_axi_rvalid(s00_axi_rvalid),
|
||||
.s00_axi_rready(s00_axi_rready),
|
||||
.s00_axi_aclk(s00_axi_aclk),
|
||||
.s00_axi_aresetn(s00_axi_aresetn)
|
||||
);
|
||||
endmodule
|
||||
+269
@@ -0,0 +1,269 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "system_top_Axis_adc_data_packer_0_0",
|
||||
"cell_name": "Axis_adc_data_packer_0",
|
||||
"component_reference": "labnet.com:user:Axis_adc_data_packer:1.0",
|
||||
"ip_revision": "9",
|
||||
"gen_directory": ".",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"C_S00_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_S00_AXI_ADDR_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_S00_AXI_BASEADDR": [ { "value": "0xFFFFFFFF", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||
"C_S00_AXI_HIGHADDR": [ { "value": "0x00000000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "system_top_Axis_adc_data_packer_0_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_S00_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S00_AXI_ADDR_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "xilinx.com:zc706:part0:1.4" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z045" } ],
|
||||
"NEXTGEN_VERSAL": [ { "value": "0" } ],
|
||||
"PACKAGE": [ { "value": "ffg900" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "9" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "." } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2024.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"aclk": [ { "direction": "in" } ],
|
||||
"aresetn": [ { "direction": "in" } ],
|
||||
"axis_tvalid": [ { "direction": "in" } ],
|
||||
"axis_tlast": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"axis_ready": [ { "direction": "out" } ],
|
||||
"axis_tdata": [ { "direction": "in", "size_left": "63", "size_right": "0", "driver_value": "0" } ],
|
||||
"m_axis_tvalid": [ { "direction": "out" } ],
|
||||
"m_axis_tlast": [ { "direction": "out" } ],
|
||||
"m_axis_ready": [ { "direction": "in" } ],
|
||||
"m_axis_tdata": [ { "direction": "out", "size_left": "63", "size_right": "0" } ],
|
||||
"s00_axi_awaddr": [ { "direction": "in", "size_left": "3", "size_right": "0" } ],
|
||||
"s00_axi_awprot": [ { "direction": "in", "size_left": "2", "size_right": "0" } ],
|
||||
"s00_axi_awvalid": [ { "direction": "in" } ],
|
||||
"s00_axi_awready": [ { "direction": "out" } ],
|
||||
"s00_axi_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
|
||||
"s00_axi_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0" } ],
|
||||
"s00_axi_wvalid": [ { "direction": "in" } ],
|
||||
"s00_axi_wready": [ { "direction": "out" } ],
|
||||
"s00_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s00_axi_bvalid": [ { "direction": "out" } ],
|
||||
"s00_axi_bready": [ { "direction": "in" } ],
|
||||
"s00_axi_araddr": [ { "direction": "in", "size_left": "3", "size_right": "0" } ],
|
||||
"s00_axi_arprot": [ { "direction": "in", "size_left": "2", "size_right": "0" } ],
|
||||
"s00_axi_arvalid": [ { "direction": "in" } ],
|
||||
"s00_axi_arready": [ { "direction": "out" } ],
|
||||
"s00_axi_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"s00_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s00_axi_rvalid": [ { "direction": "out" } ],
|
||||
"s00_axi_rready": [ { "direction": "in" } ],
|
||||
"s00_axi_aclk": [ { "direction": "in" } ],
|
||||
"s00_axi_aresetn": [ { "direction": "in" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"S00_AXI": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"memory_map_ref": "S00_AXI",
|
||||
"parameters": {
|
||||
"WIZ_DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
|
||||
"WIZ_NUM_REG": [ { "value": "4", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "1e+08", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "4", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"AWADDR": [ { "physical_name": "s00_axi_awaddr" } ],
|
||||
"AWPROT": [ { "physical_name": "s00_axi_awprot" } ],
|
||||
"AWVALID": [ { "physical_name": "s00_axi_awvalid" } ],
|
||||
"AWREADY": [ { "physical_name": "s00_axi_awready" } ],
|
||||
"WDATA": [ { "physical_name": "s00_axi_wdata" } ],
|
||||
"WSTRB": [ { "physical_name": "s00_axi_wstrb" } ],
|
||||
"WVALID": [ { "physical_name": "s00_axi_wvalid" } ],
|
||||
"WREADY": [ { "physical_name": "s00_axi_wready" } ],
|
||||
"BRESP": [ { "physical_name": "s00_axi_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "s00_axi_bvalid" } ],
|
||||
"BREADY": [ { "physical_name": "s00_axi_bready" } ],
|
||||
"ARADDR": [ { "physical_name": "s00_axi_araddr" } ],
|
||||
"ARPROT": [ { "physical_name": "s00_axi_arprot" } ],
|
||||
"ARVALID": [ { "physical_name": "s00_axi_arvalid" } ],
|
||||
"ARREADY": [ { "physical_name": "s00_axi_arready" } ],
|
||||
"RDATA": [ { "physical_name": "s00_axi_rdata" } ],
|
||||
"RRESP": [ { "physical_name": "s00_axi_rresp" } ],
|
||||
"RVALID": [ { "physical_name": "s00_axi_rvalid" } ],
|
||||
"RREADY": [ { "physical_name": "s00_axi_rready" } ]
|
||||
}
|
||||
},
|
||||
"S00_AXI_RST": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "s00_axi_aresetn" } ]
|
||||
}
|
||||
},
|
||||
"S00_AXI_CLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S00_AXI", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "s00_axi_aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "1e+08", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "s00_axi_aclk" } ]
|
||||
}
|
||||
},
|
||||
"m_axis": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "8", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_data_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "m_axis_tdata" } ],
|
||||
"TLAST": [ { "physical_name": "m_axis_tlast" } ],
|
||||
"TVALID": [ { "physical_name": "m_axis_tvalid" } ],
|
||||
"TREADY": [ { "physical_name": "m_axis_ready" } ]
|
||||
}
|
||||
},
|
||||
"aclk": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "axis:m_axis", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_data_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "aclk" } ]
|
||||
}
|
||||
},
|
||||
"aresetn": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "aresetn" } ]
|
||||
}
|
||||
},
|
||||
"axis": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "8", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_data_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "axis_tdata" } ],
|
||||
"TLAST": [ { "physical_name": "axis_tlast" } ],
|
||||
"TVALID": [ { "physical_name": "axis_tvalid" } ],
|
||||
"TREADY": [ { "physical_name": "axis_ready" } ]
|
||||
}
|
||||
}
|
||||
},
|
||||
"memory_maps": {
|
||||
"S00_AXI": {
|
||||
"address_blocks": {
|
||||
"S00_AXI_reg": {
|
||||
"base_address": "0",
|
||||
"range": "4096",
|
||||
"usage": "register",
|
||||
"parameters": {
|
||||
"OFFSET_BASE_PARAM": [ { "value": "C_S00_AXI_BASEADDR" } ],
|
||||
"OFFSET_HIGH_PARAM": [ { "value": "C_S00_AXI_HIGHADDR" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+1977
File diff suppressed because it is too large
Load Diff
+10
@@ -0,0 +1,10 @@
|
||||
|
||||
|
||||
OPTION psf_version = 2.1;
|
||||
|
||||
BEGIN DRIVER Axis_adc_data_packer
|
||||
OPTION supported_peripherals = (Axis_adc_data_packer);
|
||||
OPTION copyfiles = all;
|
||||
OPTION VERSION = 1.0;
|
||||
OPTION NAME = Axis_adc_data_packer;
|
||||
END DRIVER
|
||||
+5
@@ -0,0 +1,5 @@
|
||||
|
||||
|
||||
proc generate {drv_handle} {
|
||||
xdefine_include_file $drv_handle "xparameters.h" "Axis_adc_data_packer" "NUM_INSTANCES" "DEVICE_ID" "C_S00_AXI_BASEADDR" "C_S00_AXI_HIGHADDR"
|
||||
}
|
||||
+6
@@ -0,0 +1,6 @@
|
||||
|
||||
|
||||
/***************************** Include Files *******************************/
|
||||
#include "Axis_adc_data_packer.h"
|
||||
|
||||
/************************** Function Definitions ***************************/
|
||||
+79
@@ -0,0 +1,79 @@
|
||||
|
||||
#ifndef AXIS_ADC_DATA_PACKER_H
|
||||
#define AXIS_ADC_DATA_PACKER_H
|
||||
|
||||
|
||||
/****************** Include Files ********************/
|
||||
#include "xil_types.h"
|
||||
#include "xstatus.h"
|
||||
|
||||
#define AXIS_ADC_DATA_PACKER_S00_AXI_SLV_REG0_OFFSET 0
|
||||
#define AXIS_ADC_DATA_PACKER_S00_AXI_SLV_REG1_OFFSET 4
|
||||
#define AXIS_ADC_DATA_PACKER_S00_AXI_SLV_REG2_OFFSET 8
|
||||
#define AXIS_ADC_DATA_PACKER_S00_AXI_SLV_REG3_OFFSET 12
|
||||
|
||||
|
||||
/**************************** Type Definitions *****************************/
|
||||
/**
|
||||
*
|
||||
* Write a value to a AXIS_ADC_DATA_PACKER register. A 32 bit write is performed.
|
||||
* If the component is implemented in a smaller width, only the least
|
||||
* significant data is written.
|
||||
*
|
||||
* @param BaseAddress is the base address of the AXIS_ADC_DATA_PACKERdevice.
|
||||
* @param RegOffset is the register offset from the base to write to.
|
||||
* @param Data is the data written to the register.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note
|
||||
* C-style signature:
|
||||
* void AXIS_ADC_DATA_PACKER_mWriteReg(u32 BaseAddress, unsigned RegOffset, u32 Data)
|
||||
*
|
||||
*/
|
||||
#define AXIS_ADC_DATA_PACKER_mWriteReg(BaseAddress, RegOffset, Data) \
|
||||
Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data))
|
||||
|
||||
/**
|
||||
*
|
||||
* Read a value from a AXIS_ADC_DATA_PACKER register. A 32 bit read is performed.
|
||||
* If the component is implemented in a smaller width, only the least
|
||||
* significant data is read from the register. The most significant data
|
||||
* will be read as 0.
|
||||
*
|
||||
* @param BaseAddress is the base address of the AXIS_ADC_DATA_PACKER device.
|
||||
* @param RegOffset is the register offset from the base to write to.
|
||||
*
|
||||
* @return Data is the data from the register.
|
||||
*
|
||||
* @note
|
||||
* C-style signature:
|
||||
* u32 AXIS_ADC_DATA_PACKER_mReadReg(u32 BaseAddress, unsigned RegOffset)
|
||||
*
|
||||
*/
|
||||
#define AXIS_ADC_DATA_PACKER_mReadReg(BaseAddress, RegOffset) \
|
||||
Xil_In32((BaseAddress) + (RegOffset))
|
||||
|
||||
/************************** Function Prototypes ****************************/
|
||||
/**
|
||||
*
|
||||
* Run a self-test on the driver/device. Note this may be a destructive test if
|
||||
* resets of the device are performed.
|
||||
*
|
||||
* If the hardware system is not built correctly, this function may never
|
||||
* return to the caller.
|
||||
*
|
||||
* @param baseaddr_p is the base address of the AXIS_ADC_DATA_PACKER instance to be worked on.
|
||||
*
|
||||
* @return
|
||||
*
|
||||
* - XST_SUCCESS if all self-test code passed
|
||||
* - XST_FAILURE if any self-test code failed
|
||||
*
|
||||
* @note Caching must be turned off for this function to work.
|
||||
* @note Self test may fail if data memory and device are not on the same bus.
|
||||
*
|
||||
*/
|
||||
XStatus AXIS_ADC_DATA_PACKER_Reg_SelfTest(void * baseaddr_p);
|
||||
|
||||
#endif // AXIS_ADC_DATA_PACKER_H
|
||||
+60
@@ -0,0 +1,60 @@
|
||||
|
||||
/***************************** Include Files *******************************/
|
||||
#include "Axis_adc_data_packer.h"
|
||||
#include "xparameters.h"
|
||||
#include "stdio.h"
|
||||
#include "xil_io.h"
|
||||
|
||||
/************************** Constant Definitions ***************************/
|
||||
#define READ_WRITE_MUL_FACTOR 0x10
|
||||
|
||||
/************************** Function Definitions ***************************/
|
||||
/**
|
||||
*
|
||||
* Run a self-test on the driver/device. Note this may be a destructive test if
|
||||
* resets of the device are performed.
|
||||
*
|
||||
* If the hardware system is not built correctly, this function may never
|
||||
* return to the caller.
|
||||
*
|
||||
* @param baseaddr_p is the base address of the AXIS_ADC_DATA_PACKERinstance to be worked on.
|
||||
*
|
||||
* @return
|
||||
*
|
||||
* - XST_SUCCESS if all self-test code passed
|
||||
* - XST_FAILURE if any self-test code failed
|
||||
*
|
||||
* @note Caching must be turned off for this function to work.
|
||||
* @note Self test may fail if data memory and device are not on the same bus.
|
||||
*
|
||||
*/
|
||||
XStatus AXIS_ADC_DATA_PACKER_Reg_SelfTest(void * baseaddr_p)
|
||||
{
|
||||
u32 baseaddr;
|
||||
int write_loop_index;
|
||||
int read_loop_index;
|
||||
int Index;
|
||||
|
||||
baseaddr = (u32) baseaddr_p;
|
||||
|
||||
xil_printf("******************************\n\r");
|
||||
xil_printf("* User Peripheral Self Test\n\r");
|
||||
xil_printf("******************************\n\n\r");
|
||||
|
||||
/*
|
||||
* Write to user logic slave module register(s) and read back
|
||||
*/
|
||||
xil_printf("User logic slave module test...\n\r");
|
||||
|
||||
for (write_loop_index = 0 ; write_loop_index < 4; write_loop_index++)
|
||||
AXIS_ADC_DATA_PACKER_mWriteReg (baseaddr, write_loop_index*4, (write_loop_index+1)*READ_WRITE_MUL_FACTOR);
|
||||
for (read_loop_index = 0 ; read_loop_index < 4; read_loop_index++)
|
||||
if ( AXIS_ADC_DATA_PACKER_mReadReg (baseaddr, read_loop_index*4) != (read_loop_index+1)*READ_WRITE_MUL_FACTOR){
|
||||
xil_printf ("Error reading register value at address %x\n", (int)baseaddr + read_loop_index*4);
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
xil_printf(" - slave register write/read passed\n\n\r");
|
||||
|
||||
return XST_SUCCESS;
|
||||
}
|
||||
+26
@@ -0,0 +1,26 @@
|
||||
COMPILER=
|
||||
ARCHIVER=
|
||||
CP=cp
|
||||
COMPILER_FLAGS=
|
||||
EXTRA_COMPILER_FLAGS=
|
||||
LIB=libxil.a
|
||||
|
||||
RELEASEDIR=../../../lib
|
||||
INCLUDEDIR=../../../include
|
||||
INCLUDES=-I./. -I${INCLUDEDIR}
|
||||
|
||||
INCLUDEFILES=*.h
|
||||
LIBSOURCES=*.c
|
||||
OUTS = *.o
|
||||
|
||||
libs:
|
||||
echo "Compiling Axis_adc_data_packer..."
|
||||
$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
|
||||
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
|
||||
make clean
|
||||
|
||||
include:
|
||||
${CP} $(INCLUDEFILES) $(INCLUDEDIR)
|
||||
|
||||
clean:
|
||||
rm -rf ${OUTS}
|
||||
+197
@@ -0,0 +1,197 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: labnet.com:user:Axis_adc_data_packer:1.0
|
||||
// IP Revision: 9
|
||||
|
||||
(* X_CORE_INFO = "Axis_adc_data_packer_v1_0,Vivado 2024.1" *)
|
||||
(* CHECK_LICENSE_TYPE = "system_top_Axis_adc_data_packer_1_0,Axis_adc_data_packer_v1_0,{}" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module system_top_Axis_adc_data_packer_1_0 (
|
||||
aclk,
|
||||
aresetn,
|
||||
axis_tvalid,
|
||||
axis_tlast,
|
||||
axis_ready,
|
||||
axis_tdata,
|
||||
m_axis_tvalid,
|
||||
m_axis_tlast,
|
||||
m_axis_ready,
|
||||
m_axis_tdata,
|
||||
s00_axi_awaddr,
|
||||
s00_axi_awprot,
|
||||
s00_axi_awvalid,
|
||||
s00_axi_awready,
|
||||
s00_axi_wdata,
|
||||
s00_axi_wstrb,
|
||||
s00_axi_wvalid,
|
||||
s00_axi_wready,
|
||||
s00_axi_bresp,
|
||||
s00_axi_bvalid,
|
||||
s00_axi_bready,
|
||||
s00_axi_araddr,
|
||||
s00_axi_arprot,
|
||||
s00_axi_arvalid,
|
||||
s00_axi_arready,
|
||||
s00_axi_rdata,
|
||||
s00_axi_rresp,
|
||||
s00_axi_rvalid,
|
||||
s00_axi_rready,
|
||||
s00_axi_aclk,
|
||||
s00_axi_aresetn
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF axis:m_axis, ASSOCIATED_RESET aresetn, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN system_top_data_clk_1, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk CLK" *)
|
||||
input wire aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 aresetn RST" *)
|
||||
input wire aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 axis TVALID" *)
|
||||
input wire axis_tvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 axis TLAST" *)
|
||||
input wire axis_tlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 axis TREADY" *)
|
||||
output wire axis_ready;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME axis, TDATA_NUM_BYTES 8, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN system_top_data_clk_1, LAYERED_METADATA undef, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 axis TDATA" *)
|
||||
input wire [63 : 0] axis_tdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis TVALID" *)
|
||||
output wire m_axis_tvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis TLAST" *)
|
||||
output wire m_axis_tlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis TREADY" *)
|
||||
input wire m_axis_ready;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_axis, TDATA_NUM_BYTES 8, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN system_top_data_clk_1, LAYERED_METADATA undef, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis TDATA" *)
|
||||
output wire [63 : 0] m_axis_tdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR" *)
|
||||
input wire [3 : 0] s00_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT" *)
|
||||
input wire [2 : 0] s00_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID" *)
|
||||
input wire s00_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY" *)
|
||||
output wire s00_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA" *)
|
||||
input wire [31 : 0] s00_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB" *)
|
||||
input wire [3 : 0] s00_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID" *)
|
||||
input wire s00_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY" *)
|
||||
output wire s00_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP" *)
|
||||
output wire [1 : 0] s00_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID" *)
|
||||
output wire s00_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY" *)
|
||||
input wire s00_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR" *)
|
||||
input wire [3 : 0] s00_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT" *)
|
||||
input wire [2 : 0] s00_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID" *)
|
||||
input wire s00_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY" *)
|
||||
output wire s00_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA" *)
|
||||
output wire [31 : 0] s00_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP" *)
|
||||
output wire [1 : 0] s00_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID" *)
|
||||
output wire s00_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI, WIZ_DATA_WIDTH 32, WIZ_NUM_REG 4, SUPPORTS_NARROW_BURST 0, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 4, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN system_top_processing_syste\
|
||||
m7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *)
|
||||
input wire s00_axi_rready;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI_CLK, ASSOCIATED_BUSIF S00_AXI, ASSOCIATED_RESET s00_axi_aresetn, FREQ_HZ 1e+08, PHASE 0.000, CLK_DOMAIN system_top_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 S00_AXI_CLK CLK" *)
|
||||
input wire s00_axi_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 S00_AXI_RST RST" *)
|
||||
input wire s00_axi_aresetn;
|
||||
|
||||
Axis_adc_data_packer_v1_0 #(
|
||||
.C_S00_AXI_DATA_WIDTH(32), // Width of S_AXI data bus
|
||||
.C_S00_AXI_ADDR_WIDTH(4) // Width of S_AXI address bus
|
||||
) inst (
|
||||
.aclk(aclk),
|
||||
.aresetn(aresetn),
|
||||
.axis_tvalid(axis_tvalid),
|
||||
.axis_tlast(axis_tlast),
|
||||
.axis_ready(axis_ready),
|
||||
.axis_tdata(axis_tdata),
|
||||
.m_axis_tvalid(m_axis_tvalid),
|
||||
.m_axis_tlast(m_axis_tlast),
|
||||
.m_axis_ready(m_axis_ready),
|
||||
.m_axis_tdata(m_axis_tdata),
|
||||
.s00_axi_awaddr(s00_axi_awaddr),
|
||||
.s00_axi_awprot(s00_axi_awprot),
|
||||
.s00_axi_awvalid(s00_axi_awvalid),
|
||||
.s00_axi_awready(s00_axi_awready),
|
||||
.s00_axi_wdata(s00_axi_wdata),
|
||||
.s00_axi_wstrb(s00_axi_wstrb),
|
||||
.s00_axi_wvalid(s00_axi_wvalid),
|
||||
.s00_axi_wready(s00_axi_wready),
|
||||
.s00_axi_bresp(s00_axi_bresp),
|
||||
.s00_axi_bvalid(s00_axi_bvalid),
|
||||
.s00_axi_bready(s00_axi_bready),
|
||||
.s00_axi_araddr(s00_axi_araddr),
|
||||
.s00_axi_arprot(s00_axi_arprot),
|
||||
.s00_axi_arvalid(s00_axi_arvalid),
|
||||
.s00_axi_arready(s00_axi_arready),
|
||||
.s00_axi_rdata(s00_axi_rdata),
|
||||
.s00_axi_rresp(s00_axi_rresp),
|
||||
.s00_axi_rvalid(s00_axi_rvalid),
|
||||
.s00_axi_rready(s00_axi_rready),
|
||||
.s00_axi_aclk(s00_axi_aclk),
|
||||
.s00_axi_aresetn(s00_axi_aresetn)
|
||||
);
|
||||
endmodule
|
||||
+269
@@ -0,0 +1,269 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "system_top_Axis_adc_data_packer_1_0",
|
||||
"cell_name": "Axis_adc_data_packer_1",
|
||||
"component_reference": "labnet.com:user:Axis_adc_data_packer:1.0",
|
||||
"ip_revision": "9",
|
||||
"gen_directory": ".",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"C_S00_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_S00_AXI_ADDR_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_S00_AXI_BASEADDR": [ { "value": "0xFFFFFFFF", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||
"C_S00_AXI_HIGHADDR": [ { "value": "0x00000000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "system_top_Axis_adc_data_packer_1_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_S00_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S00_AXI_ADDR_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "xilinx.com:zc706:part0:1.4" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z045" } ],
|
||||
"NEXTGEN_VERSAL": [ { "value": "0" } ],
|
||||
"PACKAGE": [ { "value": "ffg900" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "9" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "." } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2024.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"aclk": [ { "direction": "in" } ],
|
||||
"aresetn": [ { "direction": "in" } ],
|
||||
"axis_tvalid": [ { "direction": "in" } ],
|
||||
"axis_tlast": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"axis_ready": [ { "direction": "out" } ],
|
||||
"axis_tdata": [ { "direction": "in", "size_left": "63", "size_right": "0", "driver_value": "0" } ],
|
||||
"m_axis_tvalid": [ { "direction": "out" } ],
|
||||
"m_axis_tlast": [ { "direction": "out" } ],
|
||||
"m_axis_ready": [ { "direction": "in" } ],
|
||||
"m_axis_tdata": [ { "direction": "out", "size_left": "63", "size_right": "0" } ],
|
||||
"s00_axi_awaddr": [ { "direction": "in", "size_left": "3", "size_right": "0" } ],
|
||||
"s00_axi_awprot": [ { "direction": "in", "size_left": "2", "size_right": "0" } ],
|
||||
"s00_axi_awvalid": [ { "direction": "in" } ],
|
||||
"s00_axi_awready": [ { "direction": "out" } ],
|
||||
"s00_axi_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
|
||||
"s00_axi_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0" } ],
|
||||
"s00_axi_wvalid": [ { "direction": "in" } ],
|
||||
"s00_axi_wready": [ { "direction": "out" } ],
|
||||
"s00_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s00_axi_bvalid": [ { "direction": "out" } ],
|
||||
"s00_axi_bready": [ { "direction": "in" } ],
|
||||
"s00_axi_araddr": [ { "direction": "in", "size_left": "3", "size_right": "0" } ],
|
||||
"s00_axi_arprot": [ { "direction": "in", "size_left": "2", "size_right": "0" } ],
|
||||
"s00_axi_arvalid": [ { "direction": "in" } ],
|
||||
"s00_axi_arready": [ { "direction": "out" } ],
|
||||
"s00_axi_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"s00_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s00_axi_rvalid": [ { "direction": "out" } ],
|
||||
"s00_axi_rready": [ { "direction": "in" } ],
|
||||
"s00_axi_aclk": [ { "direction": "in" } ],
|
||||
"s00_axi_aresetn": [ { "direction": "in" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"S00_AXI": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"memory_map_ref": "S00_AXI",
|
||||
"parameters": {
|
||||
"WIZ_DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
|
||||
"WIZ_NUM_REG": [ { "value": "4", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "1e+08", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "4", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"AWADDR": [ { "physical_name": "s00_axi_awaddr" } ],
|
||||
"AWPROT": [ { "physical_name": "s00_axi_awprot" } ],
|
||||
"AWVALID": [ { "physical_name": "s00_axi_awvalid" } ],
|
||||
"AWREADY": [ { "physical_name": "s00_axi_awready" } ],
|
||||
"WDATA": [ { "physical_name": "s00_axi_wdata" } ],
|
||||
"WSTRB": [ { "physical_name": "s00_axi_wstrb" } ],
|
||||
"WVALID": [ { "physical_name": "s00_axi_wvalid" } ],
|
||||
"WREADY": [ { "physical_name": "s00_axi_wready" } ],
|
||||
"BRESP": [ { "physical_name": "s00_axi_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "s00_axi_bvalid" } ],
|
||||
"BREADY": [ { "physical_name": "s00_axi_bready" } ],
|
||||
"ARADDR": [ { "physical_name": "s00_axi_araddr" } ],
|
||||
"ARPROT": [ { "physical_name": "s00_axi_arprot" } ],
|
||||
"ARVALID": [ { "physical_name": "s00_axi_arvalid" } ],
|
||||
"ARREADY": [ { "physical_name": "s00_axi_arready" } ],
|
||||
"RDATA": [ { "physical_name": "s00_axi_rdata" } ],
|
||||
"RRESP": [ { "physical_name": "s00_axi_rresp" } ],
|
||||
"RVALID": [ { "physical_name": "s00_axi_rvalid" } ],
|
||||
"RREADY": [ { "physical_name": "s00_axi_rready" } ]
|
||||
}
|
||||
},
|
||||
"S00_AXI_RST": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "s00_axi_aresetn" } ]
|
||||
}
|
||||
},
|
||||
"S00_AXI_CLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S00_AXI", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "s00_axi_aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "1e+08", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "s00_axi_aclk" } ]
|
||||
}
|
||||
},
|
||||
"m_axis": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "8", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_data_clk_1", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "m_axis_tdata" } ],
|
||||
"TLAST": [ { "physical_name": "m_axis_tlast" } ],
|
||||
"TVALID": [ { "physical_name": "m_axis_tvalid" } ],
|
||||
"TREADY": [ { "physical_name": "m_axis_ready" } ]
|
||||
}
|
||||
},
|
||||
"aclk": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "axis:m_axis", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_data_clk_1", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "aclk" } ]
|
||||
}
|
||||
},
|
||||
"aresetn": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "aresetn" } ]
|
||||
}
|
||||
},
|
||||
"axis": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "8", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_data_clk_1", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "axis_tdata" } ],
|
||||
"TLAST": [ { "physical_name": "axis_tlast" } ],
|
||||
"TVALID": [ { "physical_name": "axis_tvalid" } ],
|
||||
"TREADY": [ { "physical_name": "axis_ready" } ]
|
||||
}
|
||||
}
|
||||
},
|
||||
"memory_maps": {
|
||||
"S00_AXI": {
|
||||
"address_blocks": {
|
||||
"S00_AXI_reg": {
|
||||
"base_address": "0",
|
||||
"range": "4096",
|
||||
"usage": "register",
|
||||
"parameters": {
|
||||
"OFFSET_BASE_PARAM": [ { "value": "C_S00_AXI_BASEADDR" } ],
|
||||
"OFFSET_HIGH_PARAM": [ { "value": "C_S00_AXI_HIGHADDR" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+1977
File diff suppressed because it is too large
Load Diff
+10
@@ -0,0 +1,10 @@
|
||||
|
||||
|
||||
OPTION psf_version = 2.1;
|
||||
|
||||
BEGIN DRIVER Axis_adc_data_packer
|
||||
OPTION supported_peripherals = (Axis_adc_data_packer);
|
||||
OPTION copyfiles = all;
|
||||
OPTION VERSION = 1.0;
|
||||
OPTION NAME = Axis_adc_data_packer;
|
||||
END DRIVER
|
||||
+5
@@ -0,0 +1,5 @@
|
||||
|
||||
|
||||
proc generate {drv_handle} {
|
||||
xdefine_include_file $drv_handle "xparameters.h" "Axis_adc_data_packer" "NUM_INSTANCES" "DEVICE_ID" "C_S00_AXI_BASEADDR" "C_S00_AXI_HIGHADDR"
|
||||
}
|
||||
+6
@@ -0,0 +1,6 @@
|
||||
|
||||
|
||||
/***************************** Include Files *******************************/
|
||||
#include "Axis_adc_data_packer.h"
|
||||
|
||||
/************************** Function Definitions ***************************/
|
||||
+79
@@ -0,0 +1,79 @@
|
||||
|
||||
#ifndef AXIS_ADC_DATA_PACKER_H
|
||||
#define AXIS_ADC_DATA_PACKER_H
|
||||
|
||||
|
||||
/****************** Include Files ********************/
|
||||
#include "xil_types.h"
|
||||
#include "xstatus.h"
|
||||
|
||||
#define AXIS_ADC_DATA_PACKER_S00_AXI_SLV_REG0_OFFSET 0
|
||||
#define AXIS_ADC_DATA_PACKER_S00_AXI_SLV_REG1_OFFSET 4
|
||||
#define AXIS_ADC_DATA_PACKER_S00_AXI_SLV_REG2_OFFSET 8
|
||||
#define AXIS_ADC_DATA_PACKER_S00_AXI_SLV_REG3_OFFSET 12
|
||||
|
||||
|
||||
/**************************** Type Definitions *****************************/
|
||||
/**
|
||||
*
|
||||
* Write a value to a AXIS_ADC_DATA_PACKER register. A 32 bit write is performed.
|
||||
* If the component is implemented in a smaller width, only the least
|
||||
* significant data is written.
|
||||
*
|
||||
* @param BaseAddress is the base address of the AXIS_ADC_DATA_PACKERdevice.
|
||||
* @param RegOffset is the register offset from the base to write to.
|
||||
* @param Data is the data written to the register.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note
|
||||
* C-style signature:
|
||||
* void AXIS_ADC_DATA_PACKER_mWriteReg(u32 BaseAddress, unsigned RegOffset, u32 Data)
|
||||
*
|
||||
*/
|
||||
#define AXIS_ADC_DATA_PACKER_mWriteReg(BaseAddress, RegOffset, Data) \
|
||||
Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data))
|
||||
|
||||
/**
|
||||
*
|
||||
* Read a value from a AXIS_ADC_DATA_PACKER register. A 32 bit read is performed.
|
||||
* If the component is implemented in a smaller width, only the least
|
||||
* significant data is read from the register. The most significant data
|
||||
* will be read as 0.
|
||||
*
|
||||
* @param BaseAddress is the base address of the AXIS_ADC_DATA_PACKER device.
|
||||
* @param RegOffset is the register offset from the base to write to.
|
||||
*
|
||||
* @return Data is the data from the register.
|
||||
*
|
||||
* @note
|
||||
* C-style signature:
|
||||
* u32 AXIS_ADC_DATA_PACKER_mReadReg(u32 BaseAddress, unsigned RegOffset)
|
||||
*
|
||||
*/
|
||||
#define AXIS_ADC_DATA_PACKER_mReadReg(BaseAddress, RegOffset) \
|
||||
Xil_In32((BaseAddress) + (RegOffset))
|
||||
|
||||
/************************** Function Prototypes ****************************/
|
||||
/**
|
||||
*
|
||||
* Run a self-test on the driver/device. Note this may be a destructive test if
|
||||
* resets of the device are performed.
|
||||
*
|
||||
* If the hardware system is not built correctly, this function may never
|
||||
* return to the caller.
|
||||
*
|
||||
* @param baseaddr_p is the base address of the AXIS_ADC_DATA_PACKER instance to be worked on.
|
||||
*
|
||||
* @return
|
||||
*
|
||||
* - XST_SUCCESS if all self-test code passed
|
||||
* - XST_FAILURE if any self-test code failed
|
||||
*
|
||||
* @note Caching must be turned off for this function to work.
|
||||
* @note Self test may fail if data memory and device are not on the same bus.
|
||||
*
|
||||
*/
|
||||
XStatus AXIS_ADC_DATA_PACKER_Reg_SelfTest(void * baseaddr_p);
|
||||
|
||||
#endif // AXIS_ADC_DATA_PACKER_H
|
||||
+60
@@ -0,0 +1,60 @@
|
||||
|
||||
/***************************** Include Files *******************************/
|
||||
#include "Axis_adc_data_packer.h"
|
||||
#include "xparameters.h"
|
||||
#include "stdio.h"
|
||||
#include "xil_io.h"
|
||||
|
||||
/************************** Constant Definitions ***************************/
|
||||
#define READ_WRITE_MUL_FACTOR 0x10
|
||||
|
||||
/************************** Function Definitions ***************************/
|
||||
/**
|
||||
*
|
||||
* Run a self-test on the driver/device. Note this may be a destructive test if
|
||||
* resets of the device are performed.
|
||||
*
|
||||
* If the hardware system is not built correctly, this function may never
|
||||
* return to the caller.
|
||||
*
|
||||
* @param baseaddr_p is the base address of the AXIS_ADC_DATA_PACKERinstance to be worked on.
|
||||
*
|
||||
* @return
|
||||
*
|
||||
* - XST_SUCCESS if all self-test code passed
|
||||
* - XST_FAILURE if any self-test code failed
|
||||
*
|
||||
* @note Caching must be turned off for this function to work.
|
||||
* @note Self test may fail if data memory and device are not on the same bus.
|
||||
*
|
||||
*/
|
||||
XStatus AXIS_ADC_DATA_PACKER_Reg_SelfTest(void * baseaddr_p)
|
||||
{
|
||||
u32 baseaddr;
|
||||
int write_loop_index;
|
||||
int read_loop_index;
|
||||
int Index;
|
||||
|
||||
baseaddr = (u32) baseaddr_p;
|
||||
|
||||
xil_printf("******************************\n\r");
|
||||
xil_printf("* User Peripheral Self Test\n\r");
|
||||
xil_printf("******************************\n\n\r");
|
||||
|
||||
/*
|
||||
* Write to user logic slave module register(s) and read back
|
||||
*/
|
||||
xil_printf("User logic slave module test...\n\r");
|
||||
|
||||
for (write_loop_index = 0 ; write_loop_index < 4; write_loop_index++)
|
||||
AXIS_ADC_DATA_PACKER_mWriteReg (baseaddr, write_loop_index*4, (write_loop_index+1)*READ_WRITE_MUL_FACTOR);
|
||||
for (read_loop_index = 0 ; read_loop_index < 4; read_loop_index++)
|
||||
if ( AXIS_ADC_DATA_PACKER_mReadReg (baseaddr, read_loop_index*4) != (read_loop_index+1)*READ_WRITE_MUL_FACTOR){
|
||||
xil_printf ("Error reading register value at address %x\n", (int)baseaddr + read_loop_index*4);
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
xil_printf(" - slave register write/read passed\n\n\r");
|
||||
|
||||
return XST_SUCCESS;
|
||||
}
|
||||
+26
@@ -0,0 +1,26 @@
|
||||
COMPILER=
|
||||
ARCHIVER=
|
||||
CP=cp
|
||||
COMPILER_FLAGS=
|
||||
EXTRA_COMPILER_FLAGS=
|
||||
LIB=libxil.a
|
||||
|
||||
RELEASEDIR=../../../lib
|
||||
INCLUDEDIR=../../../include
|
||||
INCLUDES=-I./. -I${INCLUDEDIR}
|
||||
|
||||
INCLUDEFILES=*.h
|
||||
LIBSOURCES=*.c
|
||||
OUTS = *.o
|
||||
|
||||
libs:
|
||||
echo "Compiling Axis_adc_data_packer..."
|
||||
$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
|
||||
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
|
||||
make clean
|
||||
|
||||
include:
|
||||
${CP} $(INCLUDEFILES) $(INCLUDEDIR)
|
||||
|
||||
clean:
|
||||
rm -rf ${OUTS}
|
||||
+197
@@ -0,0 +1,197 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: labnet.com:user:Axis_adc_data_packer:1.0
|
||||
// IP Revision: 9
|
||||
|
||||
(* X_CORE_INFO = "Axis_adc_data_packer_v1_0,Vivado 2024.1" *)
|
||||
(* CHECK_LICENSE_TYPE = "system_top_Axis_adc_data_packer_2_0,Axis_adc_data_packer_v1_0,{}" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module system_top_Axis_adc_data_packer_2_0 (
|
||||
aclk,
|
||||
aresetn,
|
||||
axis_tvalid,
|
||||
axis_tlast,
|
||||
axis_ready,
|
||||
axis_tdata,
|
||||
m_axis_tvalid,
|
||||
m_axis_tlast,
|
||||
m_axis_ready,
|
||||
m_axis_tdata,
|
||||
s00_axi_awaddr,
|
||||
s00_axi_awprot,
|
||||
s00_axi_awvalid,
|
||||
s00_axi_awready,
|
||||
s00_axi_wdata,
|
||||
s00_axi_wstrb,
|
||||
s00_axi_wvalid,
|
||||
s00_axi_wready,
|
||||
s00_axi_bresp,
|
||||
s00_axi_bvalid,
|
||||
s00_axi_bready,
|
||||
s00_axi_araddr,
|
||||
s00_axi_arprot,
|
||||
s00_axi_arvalid,
|
||||
s00_axi_arready,
|
||||
s00_axi_rdata,
|
||||
s00_axi_rresp,
|
||||
s00_axi_rvalid,
|
||||
s00_axi_rready,
|
||||
s00_axi_aclk,
|
||||
s00_axi_aresetn
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF axis:m_axis, ASSOCIATED_RESET aresetn, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN system_top_data_clk_2, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk CLK" *)
|
||||
input wire aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 aresetn RST" *)
|
||||
input wire aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 axis TVALID" *)
|
||||
input wire axis_tvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 axis TLAST" *)
|
||||
input wire axis_tlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 axis TREADY" *)
|
||||
output wire axis_ready;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME axis, TDATA_NUM_BYTES 8, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN system_top_data_clk_2, LAYERED_METADATA undef, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 axis TDATA" *)
|
||||
input wire [63 : 0] axis_tdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis TVALID" *)
|
||||
output wire m_axis_tvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis TLAST" *)
|
||||
output wire m_axis_tlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis TREADY" *)
|
||||
input wire m_axis_ready;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_axis, TDATA_NUM_BYTES 8, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN system_top_data_clk_2, LAYERED_METADATA undef, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis TDATA" *)
|
||||
output wire [63 : 0] m_axis_tdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR" *)
|
||||
input wire [3 : 0] s00_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT" *)
|
||||
input wire [2 : 0] s00_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID" *)
|
||||
input wire s00_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY" *)
|
||||
output wire s00_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA" *)
|
||||
input wire [31 : 0] s00_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB" *)
|
||||
input wire [3 : 0] s00_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID" *)
|
||||
input wire s00_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY" *)
|
||||
output wire s00_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP" *)
|
||||
output wire [1 : 0] s00_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID" *)
|
||||
output wire s00_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY" *)
|
||||
input wire s00_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR" *)
|
||||
input wire [3 : 0] s00_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT" *)
|
||||
input wire [2 : 0] s00_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID" *)
|
||||
input wire s00_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY" *)
|
||||
output wire s00_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA" *)
|
||||
output wire [31 : 0] s00_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP" *)
|
||||
output wire [1 : 0] s00_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID" *)
|
||||
output wire s00_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI, WIZ_DATA_WIDTH 32, WIZ_NUM_REG 4, SUPPORTS_NARROW_BURST 0, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 4, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN system_top_processing_syste\
|
||||
m7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *)
|
||||
input wire s00_axi_rready;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI_CLK, ASSOCIATED_BUSIF S00_AXI, ASSOCIATED_RESET s00_axi_aresetn, FREQ_HZ 1e+08, PHASE 0.000, CLK_DOMAIN system_top_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 S00_AXI_CLK CLK" *)
|
||||
input wire s00_axi_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 S00_AXI_RST RST" *)
|
||||
input wire s00_axi_aresetn;
|
||||
|
||||
Axis_adc_data_packer_v1_0 #(
|
||||
.C_S00_AXI_DATA_WIDTH(32), // Width of S_AXI data bus
|
||||
.C_S00_AXI_ADDR_WIDTH(4) // Width of S_AXI address bus
|
||||
) inst (
|
||||
.aclk(aclk),
|
||||
.aresetn(aresetn),
|
||||
.axis_tvalid(axis_tvalid),
|
||||
.axis_tlast(axis_tlast),
|
||||
.axis_ready(axis_ready),
|
||||
.axis_tdata(axis_tdata),
|
||||
.m_axis_tvalid(m_axis_tvalid),
|
||||
.m_axis_tlast(m_axis_tlast),
|
||||
.m_axis_ready(m_axis_ready),
|
||||
.m_axis_tdata(m_axis_tdata),
|
||||
.s00_axi_awaddr(s00_axi_awaddr),
|
||||
.s00_axi_awprot(s00_axi_awprot),
|
||||
.s00_axi_awvalid(s00_axi_awvalid),
|
||||
.s00_axi_awready(s00_axi_awready),
|
||||
.s00_axi_wdata(s00_axi_wdata),
|
||||
.s00_axi_wstrb(s00_axi_wstrb),
|
||||
.s00_axi_wvalid(s00_axi_wvalid),
|
||||
.s00_axi_wready(s00_axi_wready),
|
||||
.s00_axi_bresp(s00_axi_bresp),
|
||||
.s00_axi_bvalid(s00_axi_bvalid),
|
||||
.s00_axi_bready(s00_axi_bready),
|
||||
.s00_axi_araddr(s00_axi_araddr),
|
||||
.s00_axi_arprot(s00_axi_arprot),
|
||||
.s00_axi_arvalid(s00_axi_arvalid),
|
||||
.s00_axi_arready(s00_axi_arready),
|
||||
.s00_axi_rdata(s00_axi_rdata),
|
||||
.s00_axi_rresp(s00_axi_rresp),
|
||||
.s00_axi_rvalid(s00_axi_rvalid),
|
||||
.s00_axi_rready(s00_axi_rready),
|
||||
.s00_axi_aclk(s00_axi_aclk),
|
||||
.s00_axi_aresetn(s00_axi_aresetn)
|
||||
);
|
||||
endmodule
|
||||
+269
@@ -0,0 +1,269 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "system_top_Axis_adc_data_packer_2_0",
|
||||
"cell_name": "Axis_adc_data_packer_2",
|
||||
"component_reference": "labnet.com:user:Axis_adc_data_packer:1.0",
|
||||
"ip_revision": "9",
|
||||
"gen_directory": ".",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"C_S00_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_S00_AXI_ADDR_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_S00_AXI_BASEADDR": [ { "value": "0xFFFFFFFF", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||
"C_S00_AXI_HIGHADDR": [ { "value": "0x00000000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "system_top_Axis_adc_data_packer_2_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_S00_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S00_AXI_ADDR_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "xilinx.com:zc706:part0:1.4" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z045" } ],
|
||||
"NEXTGEN_VERSAL": [ { "value": "0" } ],
|
||||
"PACKAGE": [ { "value": "ffg900" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "9" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "." } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2024.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"aclk": [ { "direction": "in" } ],
|
||||
"aresetn": [ { "direction": "in" } ],
|
||||
"axis_tvalid": [ { "direction": "in" } ],
|
||||
"axis_tlast": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"axis_ready": [ { "direction": "out" } ],
|
||||
"axis_tdata": [ { "direction": "in", "size_left": "63", "size_right": "0", "driver_value": "0" } ],
|
||||
"m_axis_tvalid": [ { "direction": "out" } ],
|
||||
"m_axis_tlast": [ { "direction": "out" } ],
|
||||
"m_axis_ready": [ { "direction": "in" } ],
|
||||
"m_axis_tdata": [ { "direction": "out", "size_left": "63", "size_right": "0" } ],
|
||||
"s00_axi_awaddr": [ { "direction": "in", "size_left": "3", "size_right": "0" } ],
|
||||
"s00_axi_awprot": [ { "direction": "in", "size_left": "2", "size_right": "0" } ],
|
||||
"s00_axi_awvalid": [ { "direction": "in" } ],
|
||||
"s00_axi_awready": [ { "direction": "out" } ],
|
||||
"s00_axi_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
|
||||
"s00_axi_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0" } ],
|
||||
"s00_axi_wvalid": [ { "direction": "in" } ],
|
||||
"s00_axi_wready": [ { "direction": "out" } ],
|
||||
"s00_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s00_axi_bvalid": [ { "direction": "out" } ],
|
||||
"s00_axi_bready": [ { "direction": "in" } ],
|
||||
"s00_axi_araddr": [ { "direction": "in", "size_left": "3", "size_right": "0" } ],
|
||||
"s00_axi_arprot": [ { "direction": "in", "size_left": "2", "size_right": "0" } ],
|
||||
"s00_axi_arvalid": [ { "direction": "in" } ],
|
||||
"s00_axi_arready": [ { "direction": "out" } ],
|
||||
"s00_axi_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"s00_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s00_axi_rvalid": [ { "direction": "out" } ],
|
||||
"s00_axi_rready": [ { "direction": "in" } ],
|
||||
"s00_axi_aclk": [ { "direction": "in" } ],
|
||||
"s00_axi_aresetn": [ { "direction": "in" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"S00_AXI": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"memory_map_ref": "S00_AXI",
|
||||
"parameters": {
|
||||
"WIZ_DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
|
||||
"WIZ_NUM_REG": [ { "value": "4", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "1e+08", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "4", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"AWADDR": [ { "physical_name": "s00_axi_awaddr" } ],
|
||||
"AWPROT": [ { "physical_name": "s00_axi_awprot" } ],
|
||||
"AWVALID": [ { "physical_name": "s00_axi_awvalid" } ],
|
||||
"AWREADY": [ { "physical_name": "s00_axi_awready" } ],
|
||||
"WDATA": [ { "physical_name": "s00_axi_wdata" } ],
|
||||
"WSTRB": [ { "physical_name": "s00_axi_wstrb" } ],
|
||||
"WVALID": [ { "physical_name": "s00_axi_wvalid" } ],
|
||||
"WREADY": [ { "physical_name": "s00_axi_wready" } ],
|
||||
"BRESP": [ { "physical_name": "s00_axi_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "s00_axi_bvalid" } ],
|
||||
"BREADY": [ { "physical_name": "s00_axi_bready" } ],
|
||||
"ARADDR": [ { "physical_name": "s00_axi_araddr" } ],
|
||||
"ARPROT": [ { "physical_name": "s00_axi_arprot" } ],
|
||||
"ARVALID": [ { "physical_name": "s00_axi_arvalid" } ],
|
||||
"ARREADY": [ { "physical_name": "s00_axi_arready" } ],
|
||||
"RDATA": [ { "physical_name": "s00_axi_rdata" } ],
|
||||
"RRESP": [ { "physical_name": "s00_axi_rresp" } ],
|
||||
"RVALID": [ { "physical_name": "s00_axi_rvalid" } ],
|
||||
"RREADY": [ { "physical_name": "s00_axi_rready" } ]
|
||||
}
|
||||
},
|
||||
"S00_AXI_RST": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "s00_axi_aresetn" } ]
|
||||
}
|
||||
},
|
||||
"S00_AXI_CLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S00_AXI", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "s00_axi_aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "1e+08", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "s00_axi_aclk" } ]
|
||||
}
|
||||
},
|
||||
"m_axis": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "8", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_data_clk_2", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "m_axis_tdata" } ],
|
||||
"TLAST": [ { "physical_name": "m_axis_tlast" } ],
|
||||
"TVALID": [ { "physical_name": "m_axis_tvalid" } ],
|
||||
"TREADY": [ { "physical_name": "m_axis_ready" } ]
|
||||
}
|
||||
},
|
||||
"aclk": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "axis:m_axis", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_data_clk_2", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "aclk" } ]
|
||||
}
|
||||
},
|
||||
"aresetn": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "aresetn" } ]
|
||||
}
|
||||
},
|
||||
"axis": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "8", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_data_clk_2", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "axis_tdata" } ],
|
||||
"TLAST": [ { "physical_name": "axis_tlast" } ],
|
||||
"TVALID": [ { "physical_name": "axis_tvalid" } ],
|
||||
"TREADY": [ { "physical_name": "axis_ready" } ]
|
||||
}
|
||||
}
|
||||
},
|
||||
"memory_maps": {
|
||||
"S00_AXI": {
|
||||
"address_blocks": {
|
||||
"S00_AXI_reg": {
|
||||
"base_address": "0",
|
||||
"range": "4096",
|
||||
"usage": "register",
|
||||
"parameters": {
|
||||
"OFFSET_BASE_PARAM": [ { "value": "C_S00_AXI_BASEADDR" } ],
|
||||
"OFFSET_HIGH_PARAM": [ { "value": "C_S00_AXI_HIGHADDR" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+1977
File diff suppressed because it is too large
Load Diff
+167
@@ -0,0 +1,167 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: cxkj.com:user:axi4_lite_spi:1.0
|
||||
// IP Revision: 2
|
||||
|
||||
(* X_CORE_INFO = "axi4_lite_spi,Vivado 2024.1" *)
|
||||
(* CHECK_LICENSE_TYPE = "system_top_axi4_lite_spi_0_0,axi4_lite_spi,{}" *)
|
||||
(* IP_DEFINITION_SOURCE = "package_project" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module system_top_axi4_lite_spi_0_0 (
|
||||
s_axi_aclk,
|
||||
s_axi_aresetn,
|
||||
s_axi_awaddr,
|
||||
s_axi_awvalid,
|
||||
s_axi_awready,
|
||||
s_axi_wdata,
|
||||
s_axi_wstrb,
|
||||
s_axi_wvalid,
|
||||
s_axi_wready,
|
||||
s_axi_bresp,
|
||||
s_axi_bvalid,
|
||||
s_axi_bready,
|
||||
s_axi_araddr,
|
||||
s_axi_arvalid,
|
||||
s_axi_arready,
|
||||
s_axi_rdata,
|
||||
s_axi_rresp,
|
||||
s_axi_rvalid,
|
||||
s_axi_rready,
|
||||
sclk_o,
|
||||
ssn_o,
|
||||
miso_i,
|
||||
mosi_o,
|
||||
sdio
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi_aclk, ASSOCIATED_BUSIF s_axi, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 1e+08, PHASE 0.000, CLK_DOMAIN system_top_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 s_axi_aclk CLK" *)
|
||||
input wire s_axi_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 s_axi_aresetn RST" *)
|
||||
input wire s_axi_aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWADDR" *)
|
||||
input wire [31 : 0] s_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWVALID" *)
|
||||
input wire s_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWREADY" *)
|
||||
output wire s_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WDATA" *)
|
||||
input wire [31 : 0] s_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WSTRB" *)
|
||||
input wire [3 : 0] s_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WVALID" *)
|
||||
input wire s_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WREADY" *)
|
||||
output wire s_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BRESP" *)
|
||||
output wire [1 : 0] s_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BVALID" *)
|
||||
output wire s_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BREADY" *)
|
||||
input wire s_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARADDR" *)
|
||||
input wire [31 : 0] s_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARVALID" *)
|
||||
input wire s_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARREADY" *)
|
||||
output wire s_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RDATA" *)
|
||||
output wire [31 : 0] s_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RRESP" *)
|
||||
output wire [1 : 0] s_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RVALID" *)
|
||||
output wire s_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN system_top_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS \
|
||||
1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RREADY" *)
|
||||
input wire s_axi_rready;
|
||||
output wire sclk_o;
|
||||
output wire ssn_o;
|
||||
input wire miso_i;
|
||||
output wire mosi_o;
|
||||
inout wire sdio;
|
||||
|
||||
axi4_lite_spi #(
|
||||
.C_S_AXI_ADDR_WIDTH(32),
|
||||
.C_S_AXI_DATA_WIDTH(32),
|
||||
.REGS_SIZE(24),
|
||||
.SPI_CONFIG(7'B1011101),
|
||||
.BAUD_RATE(16'H0002),
|
||||
.REG_WIDTH(8),
|
||||
.CHIP_ADDR_WIDTH(12),
|
||||
.FOUR_WIRE_SPI("false")
|
||||
) inst (
|
||||
.s_axi_aclk(s_axi_aclk),
|
||||
.s_axi_aresetn(s_axi_aresetn),
|
||||
.s_axi_awaddr(s_axi_awaddr),
|
||||
.s_axi_awvalid(s_axi_awvalid),
|
||||
.s_axi_awready(s_axi_awready),
|
||||
.s_axi_wdata(s_axi_wdata),
|
||||
.s_axi_wstrb(s_axi_wstrb),
|
||||
.s_axi_wvalid(s_axi_wvalid),
|
||||
.s_axi_wready(s_axi_wready),
|
||||
.s_axi_bresp(s_axi_bresp),
|
||||
.s_axi_bvalid(s_axi_bvalid),
|
||||
.s_axi_bready(s_axi_bready),
|
||||
.s_axi_araddr(s_axi_araddr),
|
||||
.s_axi_arvalid(s_axi_arvalid),
|
||||
.s_axi_arready(s_axi_arready),
|
||||
.s_axi_rdata(s_axi_rdata),
|
||||
.s_axi_rresp(s_axi_rresp),
|
||||
.s_axi_rvalid(s_axi_rvalid),
|
||||
.s_axi_rready(s_axi_rready),
|
||||
.sclk_o(sclk_o),
|
||||
.ssn_o(ssn_o),
|
||||
.miso_i(miso_i),
|
||||
.mosi_o(mosi_o),
|
||||
.sdio(sdio)
|
||||
);
|
||||
endmodule
|
||||
+184
@@ -0,0 +1,184 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "system_top_axi4_lite_spi_0_0",
|
||||
"cell_name": "axi4_lite_spi_0",
|
||||
"component_reference": "cxkj.com:user:axi4_lite_spi:1.0",
|
||||
"ip_revision": "2",
|
||||
"gen_directory": ".",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"C_S_AXI_ADDR_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"REGS_SIZE": [ { "value": "24", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SPI_CONFIG": [ { "value": "\"1011101\"", "value_src": "user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||
"BAUD_RATE": [ { "value": "0x0002", "value_src": "user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||
"REG_WIDTH": [ { "value": "8", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CHIP_ADDR_WIDTH": [ { "value": "12", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FOUR_WIRE_SPI": [ { "value": "false", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "system_top_axi4_lite_spi_0_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_S_AXI_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"REGS_SIZE": [ { "value": "24", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"SPI_CONFIG": [ { "value": "\"1011101\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"BAUD_RATE": [ { "value": "0x0002", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"REG_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"CHIP_ADDR_WIDTH": [ { "value": "12", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"FOUR_WIRE_SPI": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "xilinx.com:zc706:part0:1.4" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z045" } ],
|
||||
"NEXTGEN_VERSAL": [ { "value": "0" } ],
|
||||
"PACKAGE": [ { "value": "ffg900" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "2" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "." } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2024.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"s_axi_aclk": [ { "direction": "in" } ],
|
||||
"s_axi_aresetn": [ { "direction": "in" } ],
|
||||
"s_axi_awaddr": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_awvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_awready": [ { "direction": "out" } ],
|
||||
"s_axi_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "1" } ],
|
||||
"s_axi_wvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_wready": [ { "direction": "out" } ],
|
||||
"s_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s_axi_bvalid": [ { "direction": "out" } ],
|
||||
"s_axi_bready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_araddr": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_arvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_arready": [ { "direction": "out" } ],
|
||||
"s_axi_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"s_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s_axi_rvalid": [ { "direction": "out" } ],
|
||||
"s_axi_rready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"sclk_o": [ { "direction": "out" } ],
|
||||
"ssn_o": [ { "direction": "out" } ],
|
||||
"miso_i": [ { "direction": "in" } ],
|
||||
"mosi_o": [ { "direction": "out" } ],
|
||||
"sdio": [ { "direction": "inout" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"s_axi": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"memory_map_ref": "s_axi",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "1e+08", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"AWADDR": [ { "physical_name": "s_axi_awaddr" } ],
|
||||
"AWVALID": [ { "physical_name": "s_axi_awvalid" } ],
|
||||
"AWREADY": [ { "physical_name": "s_axi_awready" } ],
|
||||
"WDATA": [ { "physical_name": "s_axi_wdata" } ],
|
||||
"WSTRB": [ { "physical_name": "s_axi_wstrb" } ],
|
||||
"WVALID": [ { "physical_name": "s_axi_wvalid" } ],
|
||||
"WREADY": [ { "physical_name": "s_axi_wready" } ],
|
||||
"BRESP": [ { "physical_name": "s_axi_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "s_axi_bvalid" } ],
|
||||
"BREADY": [ { "physical_name": "s_axi_bready" } ],
|
||||
"ARADDR": [ { "physical_name": "s_axi_araddr" } ],
|
||||
"ARVALID": [ { "physical_name": "s_axi_arvalid" } ],
|
||||
"ARREADY": [ { "physical_name": "s_axi_arready" } ],
|
||||
"RDATA": [ { "physical_name": "s_axi_rdata" } ],
|
||||
"RRESP": [ { "physical_name": "s_axi_rresp" } ],
|
||||
"RVALID": [ { "physical_name": "s_axi_rvalid" } ],
|
||||
"RREADY": [ { "physical_name": "s_axi_rready" } ]
|
||||
}
|
||||
},
|
||||
"s_axi_aresetn": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "s_axi_aresetn" } ]
|
||||
}
|
||||
},
|
||||
"s_axi_aclk": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "s_axi", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "s_axi_aresetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "1e+08", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "s_axi_aclk" } ]
|
||||
}
|
||||
}
|
||||
},
|
||||
"memory_maps": {
|
||||
"s_axi": {
|
||||
"address_blocks": {
|
||||
"reg0": {
|
||||
"base_address": "0",
|
||||
"range": "4294967296",
|
||||
"usage": "register"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+1136
File diff suppressed because it is too large
Load Diff
+167
@@ -0,0 +1,167 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: cxkj.com:user:axi4_lite_spi:1.0
|
||||
// IP Revision: 2
|
||||
|
||||
(* X_CORE_INFO = "axi4_lite_spi,Vivado 2024.1" *)
|
||||
(* CHECK_LICENSE_TYPE = "system_top_axi4_lite_spi_0_1,axi4_lite_spi,{}" *)
|
||||
(* IP_DEFINITION_SOURCE = "package_project" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module system_top_axi4_lite_spi_0_1 (
|
||||
s_axi_aclk,
|
||||
s_axi_aresetn,
|
||||
s_axi_awaddr,
|
||||
s_axi_awvalid,
|
||||
s_axi_awready,
|
||||
s_axi_wdata,
|
||||
s_axi_wstrb,
|
||||
s_axi_wvalid,
|
||||
s_axi_wready,
|
||||
s_axi_bresp,
|
||||
s_axi_bvalid,
|
||||
s_axi_bready,
|
||||
s_axi_araddr,
|
||||
s_axi_arvalid,
|
||||
s_axi_arready,
|
||||
s_axi_rdata,
|
||||
s_axi_rresp,
|
||||
s_axi_rvalid,
|
||||
s_axi_rready,
|
||||
sclk_o,
|
||||
ssn_o,
|
||||
miso_i,
|
||||
mosi_o,
|
||||
sdio
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi_aclk, ASSOCIATED_BUSIF s_axi, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 1e+08, PHASE 0.000, CLK_DOMAIN system_top_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 s_axi_aclk CLK" *)
|
||||
input wire s_axi_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 s_axi_aresetn RST" *)
|
||||
input wire s_axi_aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWADDR" *)
|
||||
input wire [31 : 0] s_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWVALID" *)
|
||||
input wire s_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWREADY" *)
|
||||
output wire s_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WDATA" *)
|
||||
input wire [31 : 0] s_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WSTRB" *)
|
||||
input wire [3 : 0] s_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WVALID" *)
|
||||
input wire s_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WREADY" *)
|
||||
output wire s_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BRESP" *)
|
||||
output wire [1 : 0] s_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BVALID" *)
|
||||
output wire s_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BREADY" *)
|
||||
input wire s_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARADDR" *)
|
||||
input wire [31 : 0] s_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARVALID" *)
|
||||
input wire s_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARREADY" *)
|
||||
output wire s_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RDATA" *)
|
||||
output wire [31 : 0] s_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RRESP" *)
|
||||
output wire [1 : 0] s_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RVALID" *)
|
||||
output wire s_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN system_top_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS \
|
||||
1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RREADY" *)
|
||||
input wire s_axi_rready;
|
||||
output wire sclk_o;
|
||||
output wire ssn_o;
|
||||
input wire miso_i;
|
||||
output wire mosi_o;
|
||||
inout wire sdio;
|
||||
|
||||
axi4_lite_spi #(
|
||||
.C_S_AXI_ADDR_WIDTH(32),
|
||||
.C_S_AXI_DATA_WIDTH(32),
|
||||
.REGS_SIZE(24),
|
||||
.SPI_CONFIG(7'B1011101),
|
||||
.BAUD_RATE(16'H0002),
|
||||
.REG_WIDTH(8),
|
||||
.CHIP_ADDR_WIDTH(13),
|
||||
.FOUR_WIRE_SPI("true")
|
||||
) inst (
|
||||
.s_axi_aclk(s_axi_aclk),
|
||||
.s_axi_aresetn(s_axi_aresetn),
|
||||
.s_axi_awaddr(s_axi_awaddr),
|
||||
.s_axi_awvalid(s_axi_awvalid),
|
||||
.s_axi_awready(s_axi_awready),
|
||||
.s_axi_wdata(s_axi_wdata),
|
||||
.s_axi_wstrb(s_axi_wstrb),
|
||||
.s_axi_wvalid(s_axi_wvalid),
|
||||
.s_axi_wready(s_axi_wready),
|
||||
.s_axi_bresp(s_axi_bresp),
|
||||
.s_axi_bvalid(s_axi_bvalid),
|
||||
.s_axi_bready(s_axi_bready),
|
||||
.s_axi_araddr(s_axi_araddr),
|
||||
.s_axi_arvalid(s_axi_arvalid),
|
||||
.s_axi_arready(s_axi_arready),
|
||||
.s_axi_rdata(s_axi_rdata),
|
||||
.s_axi_rresp(s_axi_rresp),
|
||||
.s_axi_rvalid(s_axi_rvalid),
|
||||
.s_axi_rready(s_axi_rready),
|
||||
.sclk_o(sclk_o),
|
||||
.ssn_o(ssn_o),
|
||||
.miso_i(miso_i),
|
||||
.mosi_o(mosi_o),
|
||||
.sdio(sdio)
|
||||
);
|
||||
endmodule
|
||||
+184
@@ -0,0 +1,184 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "system_top_axi4_lite_spi_0_1",
|
||||
"cell_name": "axi4_lite_spi_1",
|
||||
"component_reference": "cxkj.com:user:axi4_lite_spi:1.0",
|
||||
"ip_revision": "2",
|
||||
"gen_directory": ".",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"C_S_AXI_ADDR_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"REGS_SIZE": [ { "value": "24", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SPI_CONFIG": [ { "value": "\"1011101\"", "value_src": "user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||
"BAUD_RATE": [ { "value": "0x0002", "value_src": "user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||
"REG_WIDTH": [ { "value": "8", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CHIP_ADDR_WIDTH": [ { "value": "13", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FOUR_WIRE_SPI": [ { "value": "true", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "system_top_axi4_lite_spi_0_1", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_S_AXI_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"REGS_SIZE": [ { "value": "24", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"SPI_CONFIG": [ { "value": "\"1011101\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"BAUD_RATE": [ { "value": "0x0002", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"REG_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"CHIP_ADDR_WIDTH": [ { "value": "13", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"FOUR_WIRE_SPI": [ { "value": "true", "resolve_type": "generated", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "xilinx.com:zc706:part0:1.4" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z045" } ],
|
||||
"NEXTGEN_VERSAL": [ { "value": "0" } ],
|
||||
"PACKAGE": [ { "value": "ffg900" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "2" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "." } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2024.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"s_axi_aclk": [ { "direction": "in" } ],
|
||||
"s_axi_aresetn": [ { "direction": "in" } ],
|
||||
"s_axi_awaddr": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_awvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_awready": [ { "direction": "out" } ],
|
||||
"s_axi_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "1" } ],
|
||||
"s_axi_wvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_wready": [ { "direction": "out" } ],
|
||||
"s_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s_axi_bvalid": [ { "direction": "out" } ],
|
||||
"s_axi_bready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_araddr": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_arvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_arready": [ { "direction": "out" } ],
|
||||
"s_axi_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"s_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s_axi_rvalid": [ { "direction": "out" } ],
|
||||
"s_axi_rready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"sclk_o": [ { "direction": "out" } ],
|
||||
"ssn_o": [ { "direction": "out" } ],
|
||||
"miso_i": [ { "direction": "in" } ],
|
||||
"mosi_o": [ { "direction": "out" } ],
|
||||
"sdio": [ { "direction": "inout" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"s_axi": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"memory_map_ref": "s_axi",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "1e+08", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"AWADDR": [ { "physical_name": "s_axi_awaddr" } ],
|
||||
"AWVALID": [ { "physical_name": "s_axi_awvalid" } ],
|
||||
"AWREADY": [ { "physical_name": "s_axi_awready" } ],
|
||||
"WDATA": [ { "physical_name": "s_axi_wdata" } ],
|
||||
"WSTRB": [ { "physical_name": "s_axi_wstrb" } ],
|
||||
"WVALID": [ { "physical_name": "s_axi_wvalid" } ],
|
||||
"WREADY": [ { "physical_name": "s_axi_wready" } ],
|
||||
"BRESP": [ { "physical_name": "s_axi_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "s_axi_bvalid" } ],
|
||||
"BREADY": [ { "physical_name": "s_axi_bready" } ],
|
||||
"ARADDR": [ { "physical_name": "s_axi_araddr" } ],
|
||||
"ARVALID": [ { "physical_name": "s_axi_arvalid" } ],
|
||||
"ARREADY": [ { "physical_name": "s_axi_arready" } ],
|
||||
"RDATA": [ { "physical_name": "s_axi_rdata" } ],
|
||||
"RRESP": [ { "physical_name": "s_axi_rresp" } ],
|
||||
"RVALID": [ { "physical_name": "s_axi_rvalid" } ],
|
||||
"RREADY": [ { "physical_name": "s_axi_rready" } ]
|
||||
}
|
||||
},
|
||||
"s_axi_aresetn": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "s_axi_aresetn" } ]
|
||||
}
|
||||
},
|
||||
"s_axi_aclk": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "s_axi", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "s_axi_aresetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "1e+08", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "s_axi_aclk" } ]
|
||||
}
|
||||
}
|
||||
},
|
||||
"memory_maps": {
|
||||
"s_axi": {
|
||||
"address_blocks": {
|
||||
"reg0": {
|
||||
"base_address": "0",
|
||||
"range": "4294967296",
|
||||
"usage": "register"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+1136
File diff suppressed because it is too large
Load Diff
+329
@@ -0,0 +1,329 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:axi_bram_ctrl:4.1
|
||||
-- IP Revision: 10
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY axi_bram_ctrl_v4_1_10;
|
||||
USE axi_bram_ctrl_v4_1_10.axi_bram_ctrl;
|
||||
|
||||
ENTITY system_top_axi_bram_ctrl_0_0 IS
|
||||
PORT (
|
||||
s_axi_aclk : IN STD_LOGIC;
|
||||
s_axi_aresetn : IN STD_LOGIC;
|
||||
s_axi_awaddr : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
|
||||
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_awlock : IN STD_LOGIC;
|
||||
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi_awvalid : IN STD_LOGIC;
|
||||
s_axi_awready : OUT STD_LOGIC;
|
||||
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_wlast : IN STD_LOGIC;
|
||||
s_axi_wvalid : IN STD_LOGIC;
|
||||
s_axi_wready : OUT STD_LOGIC;
|
||||
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_bvalid : OUT STD_LOGIC;
|
||||
s_axi_bready : IN STD_LOGIC;
|
||||
s_axi_araddr : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
|
||||
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_arlock : IN STD_LOGIC;
|
||||
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi_arvalid : IN STD_LOGIC;
|
||||
s_axi_arready : OUT STD_LOGIC;
|
||||
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_rlast : OUT STD_LOGIC;
|
||||
s_axi_rvalid : OUT STD_LOGIC;
|
||||
s_axi_rready : IN STD_LOGIC;
|
||||
bram_rst_a : OUT STD_LOGIC;
|
||||
bram_clk_a : OUT STD_LOGIC;
|
||||
bram_en_a : OUT STD_LOGIC;
|
||||
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
bram_addr_a : OUT STD_LOGIC_VECTOR(14 DOWNTO 0);
|
||||
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
END system_top_axi_bram_ctrl_0_0;
|
||||
|
||||
ARCHITECTURE system_top_axi_bram_ctrl_0_0_arch OF system_top_axi_bram_ctrl_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_top_axi_bram_ctrl_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axi_bram_ctrl IS
|
||||
GENERIC (
|
||||
C_BRAM_INST_MODE : STRING;
|
||||
C_MEMORY_DEPTH : INTEGER;
|
||||
C_BRAM_ADDR_WIDTH : INTEGER;
|
||||
C_S_AXI_ADDR_WIDTH : INTEGER;
|
||||
C_S_AXI_DATA_WIDTH : INTEGER;
|
||||
C_S_AXI_ID_WIDTH : INTEGER;
|
||||
C_S_AXI_PROTOCOL : STRING;
|
||||
C_S_AXI_SUPPORTS_NARROW_BURST : INTEGER;
|
||||
C_SINGLE_PORT_BRAM : INTEGER;
|
||||
C_FAMILY : STRING;
|
||||
C_READ_LATENCY : INTEGER;
|
||||
C_RD_CMD_OPTIMIZATION : INTEGER;
|
||||
C_S_AXI_CTRL_ADDR_WIDTH : INTEGER;
|
||||
C_S_AXI_CTRL_DATA_WIDTH : INTEGER;
|
||||
C_ECC : INTEGER;
|
||||
C_ECC_TYPE : INTEGER;
|
||||
C_FAULT_INJECT : INTEGER;
|
||||
C_ECC_ONOFF_RESET_VALUE : INTEGER
|
||||
);
|
||||
PORT (
|
||||
s_axi_aclk : IN STD_LOGIC;
|
||||
s_axi_aresetn : IN STD_LOGIC;
|
||||
ecc_interrupt : OUT STD_LOGIC;
|
||||
ecc_ue : OUT STD_LOGIC;
|
||||
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axi_awaddr : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
|
||||
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_awlock : IN STD_LOGIC;
|
||||
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi_awvalid : IN STD_LOGIC;
|
||||
s_axi_awready : OUT STD_LOGIC;
|
||||
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_wlast : IN STD_LOGIC;
|
||||
s_axi_wvalid : IN STD_LOGIC;
|
||||
s_axi_wready : OUT STD_LOGIC;
|
||||
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_bvalid : OUT STD_LOGIC;
|
||||
s_axi_bready : IN STD_LOGIC;
|
||||
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axi_araddr : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
|
||||
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_arlock : IN STD_LOGIC;
|
||||
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi_arvalid : IN STD_LOGIC;
|
||||
s_axi_arready : OUT STD_LOGIC;
|
||||
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_rlast : OUT STD_LOGIC;
|
||||
s_axi_rvalid : OUT STD_LOGIC;
|
||||
s_axi_rready : IN STD_LOGIC;
|
||||
s_axi_ctrl_awvalid : IN STD_LOGIC;
|
||||
s_axi_ctrl_awready : OUT STD_LOGIC;
|
||||
s_axi_ctrl_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_ctrl_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_ctrl_wvalid : IN STD_LOGIC;
|
||||
s_axi_ctrl_wready : OUT STD_LOGIC;
|
||||
s_axi_ctrl_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_ctrl_bvalid : OUT STD_LOGIC;
|
||||
s_axi_ctrl_bready : IN STD_LOGIC;
|
||||
s_axi_ctrl_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_ctrl_arvalid : IN STD_LOGIC;
|
||||
s_axi_ctrl_arready : OUT STD_LOGIC;
|
||||
s_axi_ctrl_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_ctrl_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_ctrl_rvalid : OUT STD_LOGIC;
|
||||
s_axi_ctrl_rready : IN STD_LOGIC;
|
||||
bram_rst_a : OUT STD_LOGIC;
|
||||
bram_clk_a : OUT STD_LOGIC;
|
||||
bram_en_a : OUT STD_LOGIC;
|
||||
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
bram_addr_a : OUT STD_LOGIC_VECTOR(14 DOWNTO 0);
|
||||
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
bram_rst_b : OUT STD_LOGIC;
|
||||
bram_clk_b : OUT STD_LOGIC;
|
||||
bram_en_b : OUT STD_LOGIC;
|
||||
bram_we_b : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
bram_addr_b : OUT STD_LOGIC_VECTOR(14 DOWNTO 0);
|
||||
bram_wrdata_b : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
bram_rddata_b : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT axi_bram_ctrl;
|
||||
ATTRIBUTE X_CORE_INFO : STRING;
|
||||
ATTRIBUTE X_CORE_INFO OF system_top_axi_bram_ctrl_0_0_arch: ARCHITECTURE IS "axi_bram_ctrl,Vivado 2024.1";
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE OF system_top_axi_bram_ctrl_0_0_arch : ARCHITECTURE IS "system_top_axi_bram_ctrl_0_0,axi_bram_ctrl,{}";
|
||||
ATTRIBUTE CORE_GENERATION_INFO : STRING;
|
||||
ATTRIBUTE CORE_GENERATION_INFO OF system_top_axi_bram_ctrl_0_0_arch: ARCHITECTURE IS "system_top_axi_bram_ctrl_0_0,axi_bram_ctrl,{x_ipProduct=Vivado 2024.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_bram_ctrl,x_ipVersion=4.1,x_ipCoreRevision=10,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_BRAM_INST_MODE=EXTERNAL,C_MEMORY_DEPTH=8192,C_BRAM_ADDR_WIDTH=13,C_S_AXI_ADDR_WIDTH=15,C_S_AXI_DATA_WIDTH=32,C_S_AXI_ID_WIDTH=1,C_S_AXI_PROTOCOL=AXI4,C_S_AXI_SUPPORTS_NARROW_BURST=0,C_SINGLE_PORT_BRAM=1,C_FAMILY=zynq,C_READ_LATENCY=1,C_RD_CMD_OPTIMIZATION=0,C_S_AXI_CTRL_ADDR_WIDTH=32,C_S_" &
|
||||
"AXI_CTRL_DATA_WIDTH=32,C_ECC=0,C_ECC_TYPE=0,C_FAULT_INJECT=0,C_ECC_ONOFF_RESET_VALUE=0}";
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bram_addr_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bram_clk_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bram_en_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bram_rddata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF bram_rst_a: SIGNAL IS "XIL_INTERFACENAME BRAM_PORTA, MASTER_TYPE BRAM_CTRL, MEM_SIZE 32768, MEM_WIDTH 32, MEM_ECC NONE, READ_WRITE_MODE READ_WRITE, READ_LATENCY 1";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bram_rst_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA RST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bram_we_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bram_wrdata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aclk: SIGNAL IS "XIL_INTERFACENAME CLKIF, ASSOCIATED_BUSIF S_AXI:S_AXI_CTRL, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 1e+08, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN system_top_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLKIF CLK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARBURST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 RSTIF RST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLEN";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARPROT";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 15, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN system_top_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, " &
|
||||
"NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWBURST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLEN";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWPROT";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
|
||||
BEGIN
|
||||
U0 : axi_bram_ctrl
|
||||
GENERIC MAP (
|
||||
C_BRAM_INST_MODE => "EXTERNAL",
|
||||
C_MEMORY_DEPTH => 8192,
|
||||
C_BRAM_ADDR_WIDTH => 13,
|
||||
C_S_AXI_ADDR_WIDTH => 15,
|
||||
C_S_AXI_DATA_WIDTH => 32,
|
||||
C_S_AXI_ID_WIDTH => 1,
|
||||
C_S_AXI_PROTOCOL => "AXI4",
|
||||
C_S_AXI_SUPPORTS_NARROW_BURST => 0,
|
||||
C_SINGLE_PORT_BRAM => 1,
|
||||
C_FAMILY => "zynq",
|
||||
C_READ_LATENCY => 1,
|
||||
C_RD_CMD_OPTIMIZATION => 0,
|
||||
C_S_AXI_CTRL_ADDR_WIDTH => 32,
|
||||
C_S_AXI_CTRL_DATA_WIDTH => 32,
|
||||
C_ECC => 0,
|
||||
C_ECC_TYPE => 0,
|
||||
C_FAULT_INJECT => 0,
|
||||
C_ECC_ONOFF_RESET_VALUE => 0
|
||||
)
|
||||
PORT MAP (
|
||||
s_axi_aclk => s_axi_aclk,
|
||||
s_axi_aresetn => s_axi_aresetn,
|
||||
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
s_axi_awaddr => s_axi_awaddr,
|
||||
s_axi_awlen => s_axi_awlen,
|
||||
s_axi_awsize => s_axi_awsize,
|
||||
s_axi_awburst => s_axi_awburst,
|
||||
s_axi_awlock => s_axi_awlock,
|
||||
s_axi_awcache => s_axi_awcache,
|
||||
s_axi_awprot => s_axi_awprot,
|
||||
s_axi_awvalid => s_axi_awvalid,
|
||||
s_axi_awready => s_axi_awready,
|
||||
s_axi_wdata => s_axi_wdata,
|
||||
s_axi_wstrb => s_axi_wstrb,
|
||||
s_axi_wlast => s_axi_wlast,
|
||||
s_axi_wvalid => s_axi_wvalid,
|
||||
s_axi_wready => s_axi_wready,
|
||||
s_axi_bresp => s_axi_bresp,
|
||||
s_axi_bvalid => s_axi_bvalid,
|
||||
s_axi_bready => s_axi_bready,
|
||||
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
s_axi_araddr => s_axi_araddr,
|
||||
s_axi_arlen => s_axi_arlen,
|
||||
s_axi_arsize => s_axi_arsize,
|
||||
s_axi_arburst => s_axi_arburst,
|
||||
s_axi_arlock => s_axi_arlock,
|
||||
s_axi_arcache => s_axi_arcache,
|
||||
s_axi_arprot => s_axi_arprot,
|
||||
s_axi_arvalid => s_axi_arvalid,
|
||||
s_axi_arready => s_axi_arready,
|
||||
s_axi_rdata => s_axi_rdata,
|
||||
s_axi_rresp => s_axi_rresp,
|
||||
s_axi_rlast => s_axi_rlast,
|
||||
s_axi_rvalid => s_axi_rvalid,
|
||||
s_axi_rready => s_axi_rready,
|
||||
s_axi_ctrl_awvalid => '0',
|
||||
s_axi_ctrl_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
s_axi_ctrl_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
s_axi_ctrl_wvalid => '0',
|
||||
s_axi_ctrl_bready => '0',
|
||||
s_axi_ctrl_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
s_axi_ctrl_arvalid => '0',
|
||||
s_axi_ctrl_rready => '0',
|
||||
bram_rst_a => bram_rst_a,
|
||||
bram_clk_a => bram_clk_a,
|
||||
bram_en_a => bram_en_a,
|
||||
bram_we_a => bram_we_a,
|
||||
bram_addr_a => bram_addr_a,
|
||||
bram_wrdata_a => bram_wrdata_a,
|
||||
bram_rddata_a => bram_rddata_a,
|
||||
bram_rddata_b => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
|
||||
);
|
||||
END system_top_axi_bram_ctrl_0_0_arch;
|
||||
+259
@@ -0,0 +1,259 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "system_top_axi_bram_ctrl_0_0",
|
||||
"cell_name": "axi_bram_ctrl_0",
|
||||
"component_reference": "xilinx.com:ip:axi_bram_ctrl:4.1",
|
||||
"ip_revision": "10",
|
||||
"gen_directory": ".",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PROTOCOL": [ { "value": "AXI4", "resolve_type": "user", "usage": "all" } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SINGLE_PORT_BRAM": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ECC_TYPE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"USE_ECC": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FAULT_INJECT": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"ECC_ONOFF_RESET_VALUE": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "system_top_axi_bram_ctrl_0_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"BMG_INSTANCE": [ { "value": "EXTERNAL", "value_permission": "bd", "resolve_type": "user", "usage": "all" } ],
|
||||
"MEM_DEPTH": [ { "value": "8192", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"READ_LATENCY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"RD_CMD_OPTIMIZATION": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_BRAM_INST_MODE": [ { "value": "EXTERNAL", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MEMORY_DEPTH": [ { "value": "8192", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_BRAM_ADDR_WIDTH": [ { "value": "13", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_ADDR_WIDTH": [ { "value": "15", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_ID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_PROTOCOL": [ { "value": "AXI4", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_S_AXI_SUPPORTS_NARROW_BURST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SINGLE_PORT_BRAM": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_FAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_READ_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_RD_CMD_OPTIMIZATION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_CTRL_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_CTRL_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ECC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ECC_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_FAULT_INJECT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ECC_ONOFF_RESET_VALUE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "xilinx.com:zc706:part0:1.4" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z045" } ],
|
||||
"NEXTGEN_VERSAL": [ { "value": "0" } ],
|
||||
"PACKAGE": [ { "value": "ffg900" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "10" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "." } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2024.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"s_axi_aclk": [ { "direction": "in" } ],
|
||||
"s_axi_aresetn": [ { "direction": "in" } ],
|
||||
"s_axi_awaddr": [ { "direction": "in", "size_left": "14", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_awlen": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_awsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_awburst": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_awlock": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_awcache": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_awprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_awvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_awready": [ { "direction": "out" } ],
|
||||
"s_axi_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_wlast": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_wvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_wready": [ { "direction": "out" } ],
|
||||
"s_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s_axi_bvalid": [ { "direction": "out" } ],
|
||||
"s_axi_bready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_araddr": [ { "direction": "in", "size_left": "14", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_arlen": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_arsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_arburst": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_arlock": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_arcache": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_arprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_arvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_arready": [ { "direction": "out" } ],
|
||||
"s_axi_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"s_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s_axi_rlast": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"s_axi_rvalid": [ { "direction": "out" } ],
|
||||
"s_axi_rready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"bram_rst_a": [ { "direction": "out" } ],
|
||||
"bram_clk_a": [ { "direction": "out" } ],
|
||||
"bram_en_a": [ { "direction": "out" } ],
|
||||
"bram_we_a": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||
"bram_addr_a": [ { "direction": "out", "size_left": "14", "size_right": "0" } ],
|
||||
"bram_wrdata_a": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"bram_rddata_a": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"S_AXI": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"memory_map_ref": "S_AXI",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "1e+08", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "15", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "16", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"ARADDR": [ { "physical_name": "s_axi_araddr" } ],
|
||||
"ARBURST": [ { "physical_name": "s_axi_arburst" } ],
|
||||
"ARCACHE": [ { "physical_name": "s_axi_arcache" } ],
|
||||
"ARLEN": [ { "physical_name": "s_axi_arlen" } ],
|
||||
"ARLOCK": [ { "physical_name": "s_axi_arlock" } ],
|
||||
"ARPROT": [ { "physical_name": "s_axi_arprot" } ],
|
||||
"ARREADY": [ { "physical_name": "s_axi_arready" } ],
|
||||
"ARSIZE": [ { "physical_name": "s_axi_arsize" } ],
|
||||
"ARVALID": [ { "physical_name": "s_axi_arvalid" } ],
|
||||
"AWADDR": [ { "physical_name": "s_axi_awaddr" } ],
|
||||
"AWBURST": [ { "physical_name": "s_axi_awburst" } ],
|
||||
"AWCACHE": [ { "physical_name": "s_axi_awcache" } ],
|
||||
"AWLEN": [ { "physical_name": "s_axi_awlen" } ],
|
||||
"AWLOCK": [ { "physical_name": "s_axi_awlock" } ],
|
||||
"AWPROT": [ { "physical_name": "s_axi_awprot" } ],
|
||||
"AWREADY": [ { "physical_name": "s_axi_awready" } ],
|
||||
"AWSIZE": [ { "physical_name": "s_axi_awsize" } ],
|
||||
"AWVALID": [ { "physical_name": "s_axi_awvalid" } ],
|
||||
"BREADY": [ { "physical_name": "s_axi_bready" } ],
|
||||
"BRESP": [ { "physical_name": "s_axi_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "s_axi_bvalid" } ],
|
||||
"RDATA": [ { "physical_name": "s_axi_rdata" } ],
|
||||
"RLAST": [ { "physical_name": "s_axi_rlast" } ],
|
||||
"RREADY": [ { "physical_name": "s_axi_rready" } ],
|
||||
"RRESP": [ { "physical_name": "s_axi_rresp" } ],
|
||||
"RVALID": [ { "physical_name": "s_axi_rvalid" } ],
|
||||
"WDATA": [ { "physical_name": "s_axi_wdata" } ],
|
||||
"WLAST": [ { "physical_name": "s_axi_wlast" } ],
|
||||
"WREADY": [ { "physical_name": "s_axi_wready" } ],
|
||||
"WSTRB": [ { "physical_name": "s_axi_wstrb" } ],
|
||||
"WVALID": [ { "physical_name": "s_axi_wvalid" } ]
|
||||
}
|
||||
},
|
||||
"BRAM_PORTA": {
|
||||
"vlnv": "xilinx.com:interface:bram:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:bram_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"MASTER_TYPE": [ { "value": "BRAM_CTRL", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"MEM_SIZE": [ { "value": "32768", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MEM_WIDTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MEM_ECC": [ { "value": "NONE", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_LATENCY": [ { "value": "1", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MEM_ADDRESS_MODE": [ { "value": "", "value_src": "weak", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"ADDR": [ { "physical_name": "bram_addr_a" } ],
|
||||
"CLK": [ { "physical_name": "bram_clk_a" } ],
|
||||
"DIN": [ { "physical_name": "bram_wrdata_a" } ],
|
||||
"DOUT": [ { "physical_name": "bram_rddata_a" } ],
|
||||
"EN": [ { "physical_name": "bram_en_a" } ],
|
||||
"RST": [ { "physical_name": "bram_rst_a" } ],
|
||||
"WE": [ { "physical_name": "bram_we_a" } ]
|
||||
}
|
||||
},
|
||||
"RSTIF": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "s_axi_aresetn" } ]
|
||||
}
|
||||
},
|
||||
"CLKIF": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S_AXI:S_AXI_CTRL", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "s_axi_aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "1e+08", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "s_axi_aclk" } ]
|
||||
}
|
||||
}
|
||||
},
|
||||
"memory_maps": {
|
||||
"S_AXI": {
|
||||
"display_name": "S_AXI_MEM",
|
||||
"description": "Memory Map for S_AXI",
|
||||
"address_blocks": {
|
||||
"Mem0": {
|
||||
"base_address": "0",
|
||||
"range": "4096",
|
||||
"display_name": "Mem0",
|
||||
"description": "Register Block",
|
||||
"usage": "memory",
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+3972
File diff suppressed because it is too large
Load Diff
+329
@@ -0,0 +1,329 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:axi_bram_ctrl:4.1
|
||||
-- IP Revision: 10
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY axi_bram_ctrl_v4_1_10;
|
||||
USE axi_bram_ctrl_v4_1_10.axi_bram_ctrl;
|
||||
|
||||
ENTITY system_top_axi_bram_ctrl_1_0 IS
|
||||
PORT (
|
||||
s_axi_aclk : IN STD_LOGIC;
|
||||
s_axi_aresetn : IN STD_LOGIC;
|
||||
s_axi_awaddr : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
|
||||
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_awlock : IN STD_LOGIC;
|
||||
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi_awvalid : IN STD_LOGIC;
|
||||
s_axi_awready : OUT STD_LOGIC;
|
||||
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_wlast : IN STD_LOGIC;
|
||||
s_axi_wvalid : IN STD_LOGIC;
|
||||
s_axi_wready : OUT STD_LOGIC;
|
||||
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_bvalid : OUT STD_LOGIC;
|
||||
s_axi_bready : IN STD_LOGIC;
|
||||
s_axi_araddr : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
|
||||
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_arlock : IN STD_LOGIC;
|
||||
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi_arvalid : IN STD_LOGIC;
|
||||
s_axi_arready : OUT STD_LOGIC;
|
||||
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_rlast : OUT STD_LOGIC;
|
||||
s_axi_rvalid : OUT STD_LOGIC;
|
||||
s_axi_rready : IN STD_LOGIC;
|
||||
bram_rst_a : OUT STD_LOGIC;
|
||||
bram_clk_a : OUT STD_LOGIC;
|
||||
bram_en_a : OUT STD_LOGIC;
|
||||
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
bram_addr_a : OUT STD_LOGIC_VECTOR(14 DOWNTO 0);
|
||||
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
END system_top_axi_bram_ctrl_1_0;
|
||||
|
||||
ARCHITECTURE system_top_axi_bram_ctrl_1_0_arch OF system_top_axi_bram_ctrl_1_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_top_axi_bram_ctrl_1_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axi_bram_ctrl IS
|
||||
GENERIC (
|
||||
C_BRAM_INST_MODE : STRING;
|
||||
C_MEMORY_DEPTH : INTEGER;
|
||||
C_BRAM_ADDR_WIDTH : INTEGER;
|
||||
C_S_AXI_ADDR_WIDTH : INTEGER;
|
||||
C_S_AXI_DATA_WIDTH : INTEGER;
|
||||
C_S_AXI_ID_WIDTH : INTEGER;
|
||||
C_S_AXI_PROTOCOL : STRING;
|
||||
C_S_AXI_SUPPORTS_NARROW_BURST : INTEGER;
|
||||
C_SINGLE_PORT_BRAM : INTEGER;
|
||||
C_FAMILY : STRING;
|
||||
C_READ_LATENCY : INTEGER;
|
||||
C_RD_CMD_OPTIMIZATION : INTEGER;
|
||||
C_S_AXI_CTRL_ADDR_WIDTH : INTEGER;
|
||||
C_S_AXI_CTRL_DATA_WIDTH : INTEGER;
|
||||
C_ECC : INTEGER;
|
||||
C_ECC_TYPE : INTEGER;
|
||||
C_FAULT_INJECT : INTEGER;
|
||||
C_ECC_ONOFF_RESET_VALUE : INTEGER
|
||||
);
|
||||
PORT (
|
||||
s_axi_aclk : IN STD_LOGIC;
|
||||
s_axi_aresetn : IN STD_LOGIC;
|
||||
ecc_interrupt : OUT STD_LOGIC;
|
||||
ecc_ue : OUT STD_LOGIC;
|
||||
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axi_awaddr : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
|
||||
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_awlock : IN STD_LOGIC;
|
||||
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi_awvalid : IN STD_LOGIC;
|
||||
s_axi_awready : OUT STD_LOGIC;
|
||||
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_wlast : IN STD_LOGIC;
|
||||
s_axi_wvalid : IN STD_LOGIC;
|
||||
s_axi_wready : OUT STD_LOGIC;
|
||||
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_bvalid : OUT STD_LOGIC;
|
||||
s_axi_bready : IN STD_LOGIC;
|
||||
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axi_araddr : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
|
||||
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_arlock : IN STD_LOGIC;
|
||||
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi_arvalid : IN STD_LOGIC;
|
||||
s_axi_arready : OUT STD_LOGIC;
|
||||
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_rlast : OUT STD_LOGIC;
|
||||
s_axi_rvalid : OUT STD_LOGIC;
|
||||
s_axi_rready : IN STD_LOGIC;
|
||||
s_axi_ctrl_awvalid : IN STD_LOGIC;
|
||||
s_axi_ctrl_awready : OUT STD_LOGIC;
|
||||
s_axi_ctrl_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_ctrl_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_ctrl_wvalid : IN STD_LOGIC;
|
||||
s_axi_ctrl_wready : OUT STD_LOGIC;
|
||||
s_axi_ctrl_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_ctrl_bvalid : OUT STD_LOGIC;
|
||||
s_axi_ctrl_bready : IN STD_LOGIC;
|
||||
s_axi_ctrl_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_ctrl_arvalid : IN STD_LOGIC;
|
||||
s_axi_ctrl_arready : OUT STD_LOGIC;
|
||||
s_axi_ctrl_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_ctrl_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_ctrl_rvalid : OUT STD_LOGIC;
|
||||
s_axi_ctrl_rready : IN STD_LOGIC;
|
||||
bram_rst_a : OUT STD_LOGIC;
|
||||
bram_clk_a : OUT STD_LOGIC;
|
||||
bram_en_a : OUT STD_LOGIC;
|
||||
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
bram_addr_a : OUT STD_LOGIC_VECTOR(14 DOWNTO 0);
|
||||
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
bram_rst_b : OUT STD_LOGIC;
|
||||
bram_clk_b : OUT STD_LOGIC;
|
||||
bram_en_b : OUT STD_LOGIC;
|
||||
bram_we_b : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
bram_addr_b : OUT STD_LOGIC_VECTOR(14 DOWNTO 0);
|
||||
bram_wrdata_b : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
bram_rddata_b : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT axi_bram_ctrl;
|
||||
ATTRIBUTE X_CORE_INFO : STRING;
|
||||
ATTRIBUTE X_CORE_INFO OF system_top_axi_bram_ctrl_1_0_arch: ARCHITECTURE IS "axi_bram_ctrl,Vivado 2024.1";
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE OF system_top_axi_bram_ctrl_1_0_arch : ARCHITECTURE IS "system_top_axi_bram_ctrl_1_0,axi_bram_ctrl,{}";
|
||||
ATTRIBUTE CORE_GENERATION_INFO : STRING;
|
||||
ATTRIBUTE CORE_GENERATION_INFO OF system_top_axi_bram_ctrl_1_0_arch: ARCHITECTURE IS "system_top_axi_bram_ctrl_1_0,axi_bram_ctrl,{x_ipProduct=Vivado 2024.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_bram_ctrl,x_ipVersion=4.1,x_ipCoreRevision=10,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_BRAM_INST_MODE=EXTERNAL,C_MEMORY_DEPTH=8192,C_BRAM_ADDR_WIDTH=13,C_S_AXI_ADDR_WIDTH=15,C_S_AXI_DATA_WIDTH=32,C_S_AXI_ID_WIDTH=1,C_S_AXI_PROTOCOL=AXI4,C_S_AXI_SUPPORTS_NARROW_BURST=0,C_SINGLE_PORT_BRAM=1,C_FAMILY=zynq,C_READ_LATENCY=1,C_RD_CMD_OPTIMIZATION=0,C_S_AXI_CTRL_ADDR_WIDTH=32,C_S_" &
|
||||
"AXI_CTRL_DATA_WIDTH=32,C_ECC=0,C_ECC_TYPE=0,C_FAULT_INJECT=0,C_ECC_ONOFF_RESET_VALUE=0}";
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bram_addr_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bram_clk_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bram_en_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bram_rddata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF bram_rst_a: SIGNAL IS "XIL_INTERFACENAME BRAM_PORTA, MASTER_TYPE BRAM_CTRL, MEM_SIZE 32768, MEM_WIDTH 32, MEM_ECC NONE, READ_WRITE_MODE READ_WRITE, READ_LATENCY 1";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bram_rst_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA RST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bram_we_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bram_wrdata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aclk: SIGNAL IS "XIL_INTERFACENAME CLKIF, ASSOCIATED_BUSIF S_AXI:S_AXI_CTRL, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 1e+08, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN system_top_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLKIF CLK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARBURST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 RSTIF RST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLEN";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARPROT";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 15, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN system_top_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, " &
|
||||
"NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWBURST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLEN";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWPROT";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
|
||||
BEGIN
|
||||
U0 : axi_bram_ctrl
|
||||
GENERIC MAP (
|
||||
C_BRAM_INST_MODE => "EXTERNAL",
|
||||
C_MEMORY_DEPTH => 8192,
|
||||
C_BRAM_ADDR_WIDTH => 13,
|
||||
C_S_AXI_ADDR_WIDTH => 15,
|
||||
C_S_AXI_DATA_WIDTH => 32,
|
||||
C_S_AXI_ID_WIDTH => 1,
|
||||
C_S_AXI_PROTOCOL => "AXI4",
|
||||
C_S_AXI_SUPPORTS_NARROW_BURST => 0,
|
||||
C_SINGLE_PORT_BRAM => 1,
|
||||
C_FAMILY => "zynq",
|
||||
C_READ_LATENCY => 1,
|
||||
C_RD_CMD_OPTIMIZATION => 0,
|
||||
C_S_AXI_CTRL_ADDR_WIDTH => 32,
|
||||
C_S_AXI_CTRL_DATA_WIDTH => 32,
|
||||
C_ECC => 0,
|
||||
C_ECC_TYPE => 0,
|
||||
C_FAULT_INJECT => 0,
|
||||
C_ECC_ONOFF_RESET_VALUE => 0
|
||||
)
|
||||
PORT MAP (
|
||||
s_axi_aclk => s_axi_aclk,
|
||||
s_axi_aresetn => s_axi_aresetn,
|
||||
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
s_axi_awaddr => s_axi_awaddr,
|
||||
s_axi_awlen => s_axi_awlen,
|
||||
s_axi_awsize => s_axi_awsize,
|
||||
s_axi_awburst => s_axi_awburst,
|
||||
s_axi_awlock => s_axi_awlock,
|
||||
s_axi_awcache => s_axi_awcache,
|
||||
s_axi_awprot => s_axi_awprot,
|
||||
s_axi_awvalid => s_axi_awvalid,
|
||||
s_axi_awready => s_axi_awready,
|
||||
s_axi_wdata => s_axi_wdata,
|
||||
s_axi_wstrb => s_axi_wstrb,
|
||||
s_axi_wlast => s_axi_wlast,
|
||||
s_axi_wvalid => s_axi_wvalid,
|
||||
s_axi_wready => s_axi_wready,
|
||||
s_axi_bresp => s_axi_bresp,
|
||||
s_axi_bvalid => s_axi_bvalid,
|
||||
s_axi_bready => s_axi_bready,
|
||||
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
s_axi_araddr => s_axi_araddr,
|
||||
s_axi_arlen => s_axi_arlen,
|
||||
s_axi_arsize => s_axi_arsize,
|
||||
s_axi_arburst => s_axi_arburst,
|
||||
s_axi_arlock => s_axi_arlock,
|
||||
s_axi_arcache => s_axi_arcache,
|
||||
s_axi_arprot => s_axi_arprot,
|
||||
s_axi_arvalid => s_axi_arvalid,
|
||||
s_axi_arready => s_axi_arready,
|
||||
s_axi_rdata => s_axi_rdata,
|
||||
s_axi_rresp => s_axi_rresp,
|
||||
s_axi_rlast => s_axi_rlast,
|
||||
s_axi_rvalid => s_axi_rvalid,
|
||||
s_axi_rready => s_axi_rready,
|
||||
s_axi_ctrl_awvalid => '0',
|
||||
s_axi_ctrl_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
s_axi_ctrl_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
s_axi_ctrl_wvalid => '0',
|
||||
s_axi_ctrl_bready => '0',
|
||||
s_axi_ctrl_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
s_axi_ctrl_arvalid => '0',
|
||||
s_axi_ctrl_rready => '0',
|
||||
bram_rst_a => bram_rst_a,
|
||||
bram_clk_a => bram_clk_a,
|
||||
bram_en_a => bram_en_a,
|
||||
bram_we_a => bram_we_a,
|
||||
bram_addr_a => bram_addr_a,
|
||||
bram_wrdata_a => bram_wrdata_a,
|
||||
bram_rddata_a => bram_rddata_a,
|
||||
bram_rddata_b => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
|
||||
);
|
||||
END system_top_axi_bram_ctrl_1_0_arch;
|
||||
+259
@@ -0,0 +1,259 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "system_top_axi_bram_ctrl_1_0",
|
||||
"cell_name": "axi_bram_ctrl_1",
|
||||
"component_reference": "xilinx.com:ip:axi_bram_ctrl:4.1",
|
||||
"ip_revision": "10",
|
||||
"gen_directory": ".",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PROTOCOL": [ { "value": "AXI4", "resolve_type": "user", "usage": "all" } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SINGLE_PORT_BRAM": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ECC_TYPE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"USE_ECC": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FAULT_INJECT": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"ECC_ONOFF_RESET_VALUE": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "system_top_axi_bram_ctrl_1_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"BMG_INSTANCE": [ { "value": "EXTERNAL", "value_permission": "bd", "resolve_type": "user", "usage": "all" } ],
|
||||
"MEM_DEPTH": [ { "value": "8192", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"READ_LATENCY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"RD_CMD_OPTIMIZATION": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_BRAM_INST_MODE": [ { "value": "EXTERNAL", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MEMORY_DEPTH": [ { "value": "8192", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_BRAM_ADDR_WIDTH": [ { "value": "13", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_ADDR_WIDTH": [ { "value": "15", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_ID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_PROTOCOL": [ { "value": "AXI4", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_S_AXI_SUPPORTS_NARROW_BURST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SINGLE_PORT_BRAM": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_FAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_READ_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_RD_CMD_OPTIMIZATION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_CTRL_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_CTRL_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ECC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ECC_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_FAULT_INJECT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ECC_ONOFF_RESET_VALUE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "xilinx.com:zc706:part0:1.4" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z045" } ],
|
||||
"NEXTGEN_VERSAL": [ { "value": "0" } ],
|
||||
"PACKAGE": [ { "value": "ffg900" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "10" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "." } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2024.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"s_axi_aclk": [ { "direction": "in" } ],
|
||||
"s_axi_aresetn": [ { "direction": "in" } ],
|
||||
"s_axi_awaddr": [ { "direction": "in", "size_left": "14", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_awlen": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_awsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_awburst": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_awlock": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_awcache": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_awprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_awvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_awready": [ { "direction": "out" } ],
|
||||
"s_axi_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_wlast": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_wvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_wready": [ { "direction": "out" } ],
|
||||
"s_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s_axi_bvalid": [ { "direction": "out" } ],
|
||||
"s_axi_bready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_araddr": [ { "direction": "in", "size_left": "14", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_arlen": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_arsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_arburst": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_arlock": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_arcache": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_arprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_arvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_arready": [ { "direction": "out" } ],
|
||||
"s_axi_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"s_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s_axi_rlast": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"s_axi_rvalid": [ { "direction": "out" } ],
|
||||
"s_axi_rready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"bram_rst_a": [ { "direction": "out" } ],
|
||||
"bram_clk_a": [ { "direction": "out" } ],
|
||||
"bram_en_a": [ { "direction": "out" } ],
|
||||
"bram_we_a": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||
"bram_addr_a": [ { "direction": "out", "size_left": "14", "size_right": "0" } ],
|
||||
"bram_wrdata_a": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"bram_rddata_a": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"S_AXI": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"memory_map_ref": "S_AXI",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "1e+08", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "15", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "16", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"ARADDR": [ { "physical_name": "s_axi_araddr" } ],
|
||||
"ARBURST": [ { "physical_name": "s_axi_arburst" } ],
|
||||
"ARCACHE": [ { "physical_name": "s_axi_arcache" } ],
|
||||
"ARLEN": [ { "physical_name": "s_axi_arlen" } ],
|
||||
"ARLOCK": [ { "physical_name": "s_axi_arlock" } ],
|
||||
"ARPROT": [ { "physical_name": "s_axi_arprot" } ],
|
||||
"ARREADY": [ { "physical_name": "s_axi_arready" } ],
|
||||
"ARSIZE": [ { "physical_name": "s_axi_arsize" } ],
|
||||
"ARVALID": [ { "physical_name": "s_axi_arvalid" } ],
|
||||
"AWADDR": [ { "physical_name": "s_axi_awaddr" } ],
|
||||
"AWBURST": [ { "physical_name": "s_axi_awburst" } ],
|
||||
"AWCACHE": [ { "physical_name": "s_axi_awcache" } ],
|
||||
"AWLEN": [ { "physical_name": "s_axi_awlen" } ],
|
||||
"AWLOCK": [ { "physical_name": "s_axi_awlock" } ],
|
||||
"AWPROT": [ { "physical_name": "s_axi_awprot" } ],
|
||||
"AWREADY": [ { "physical_name": "s_axi_awready" } ],
|
||||
"AWSIZE": [ { "physical_name": "s_axi_awsize" } ],
|
||||
"AWVALID": [ { "physical_name": "s_axi_awvalid" } ],
|
||||
"BREADY": [ { "physical_name": "s_axi_bready" } ],
|
||||
"BRESP": [ { "physical_name": "s_axi_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "s_axi_bvalid" } ],
|
||||
"RDATA": [ { "physical_name": "s_axi_rdata" } ],
|
||||
"RLAST": [ { "physical_name": "s_axi_rlast" } ],
|
||||
"RREADY": [ { "physical_name": "s_axi_rready" } ],
|
||||
"RRESP": [ { "physical_name": "s_axi_rresp" } ],
|
||||
"RVALID": [ { "physical_name": "s_axi_rvalid" } ],
|
||||
"WDATA": [ { "physical_name": "s_axi_wdata" } ],
|
||||
"WLAST": [ { "physical_name": "s_axi_wlast" } ],
|
||||
"WREADY": [ { "physical_name": "s_axi_wready" } ],
|
||||
"WSTRB": [ { "physical_name": "s_axi_wstrb" } ],
|
||||
"WVALID": [ { "physical_name": "s_axi_wvalid" } ]
|
||||
}
|
||||
},
|
||||
"BRAM_PORTA": {
|
||||
"vlnv": "xilinx.com:interface:bram:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:bram_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"MASTER_TYPE": [ { "value": "BRAM_CTRL", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"MEM_SIZE": [ { "value": "32768", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MEM_WIDTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MEM_ECC": [ { "value": "NONE", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_LATENCY": [ { "value": "1", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MEM_ADDRESS_MODE": [ { "value": "", "value_src": "weak", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"ADDR": [ { "physical_name": "bram_addr_a" } ],
|
||||
"CLK": [ { "physical_name": "bram_clk_a" } ],
|
||||
"DIN": [ { "physical_name": "bram_wrdata_a" } ],
|
||||
"DOUT": [ { "physical_name": "bram_rddata_a" } ],
|
||||
"EN": [ { "physical_name": "bram_en_a" } ],
|
||||
"RST": [ { "physical_name": "bram_rst_a" } ],
|
||||
"WE": [ { "physical_name": "bram_we_a" } ]
|
||||
}
|
||||
},
|
||||
"RSTIF": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "s_axi_aresetn" } ]
|
||||
}
|
||||
},
|
||||
"CLKIF": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S_AXI:S_AXI_CTRL", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "s_axi_aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "1e+08", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "s_axi_aclk" } ]
|
||||
}
|
||||
}
|
||||
},
|
||||
"memory_maps": {
|
||||
"S_AXI": {
|
||||
"display_name": "S_AXI_MEM",
|
||||
"description": "Memory Map for S_AXI",
|
||||
"address_blocks": {
|
||||
"Mem0": {
|
||||
"base_address": "0",
|
||||
"range": "4096",
|
||||
"display_name": "Mem0",
|
||||
"description": "Register Block",
|
||||
"usage": "memory",
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+3972
File diff suppressed because it is too large
Load Diff
+431
@@ -0,0 +1,431 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:axi_dma:7.1
|
||||
-- IP Revision: 32
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY axi_dma_v7_1_32;
|
||||
USE axi_dma_v7_1_32.axi_dma;
|
||||
|
||||
ENTITY system_top_axi_dma_0_0 IS
|
||||
PORT (
|
||||
s_axi_lite_aclk : IN STD_LOGIC;
|
||||
m_axi_s2mm_aclk : IN STD_LOGIC;
|
||||
axi_resetn : IN STD_LOGIC;
|
||||
s_axi_lite_awvalid : IN STD_LOGIC;
|
||||
s_axi_lite_awready : OUT STD_LOGIC;
|
||||
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
s_axi_lite_wvalid : IN STD_LOGIC;
|
||||
s_axi_lite_wready : OUT STD_LOGIC;
|
||||
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_lite_bvalid : OUT STD_LOGIC;
|
||||
s_axi_lite_bready : IN STD_LOGIC;
|
||||
s_axi_lite_arvalid : IN STD_LOGIC;
|
||||
s_axi_lite_arready : OUT STD_LOGIC;
|
||||
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
s_axi_lite_rvalid : OUT STD_LOGIC;
|
||||
s_axi_lite_rready : IN STD_LOGIC;
|
||||
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(39 DOWNTO 0);
|
||||
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_s2mm_awvalid : OUT STD_LOGIC;
|
||||
m_axi_s2mm_awready : IN STD_LOGIC;
|
||||
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
|
||||
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_s2mm_wlast : OUT STD_LOGIC;
|
||||
m_axi_s2mm_wvalid : OUT STD_LOGIC;
|
||||
m_axi_s2mm_wready : IN STD_LOGIC;
|
||||
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_s2mm_bvalid : IN STD_LOGIC;
|
||||
m_axi_s2mm_bready : OUT STD_LOGIC;
|
||||
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
|
||||
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
|
||||
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
s_axis_s2mm_tvalid : IN STD_LOGIC;
|
||||
s_axis_s2mm_tready : OUT STD_LOGIC;
|
||||
s_axis_s2mm_tlast : IN STD_LOGIC;
|
||||
s2mm_introut : OUT STD_LOGIC;
|
||||
axi_dma_tstvec : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
END system_top_axi_dma_0_0;
|
||||
|
||||
ARCHITECTURE system_top_axi_dma_0_0_arch OF system_top_axi_dma_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_top_axi_dma_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axi_dma IS
|
||||
GENERIC (
|
||||
C_S_AXI_LITE_ADDR_WIDTH : INTEGER;
|
||||
C_S_AXI_LITE_DATA_WIDTH : INTEGER;
|
||||
C_DLYTMR_RESOLUTION : INTEGER;
|
||||
C_PRMRY_IS_ACLK_ASYNC : INTEGER;
|
||||
C_ENABLE_MULTI_CHANNEL : INTEGER;
|
||||
C_NUM_MM2S_CHANNELS : INTEGER;
|
||||
C_NUM_S2MM_CHANNELS : INTEGER;
|
||||
C_INCLUDE_SG : INTEGER;
|
||||
C_SG_INCLUDE_STSCNTRL_STRM : INTEGER;
|
||||
C_SG_USE_STSAPP_LENGTH : INTEGER;
|
||||
C_SG_LENGTH_WIDTH : INTEGER;
|
||||
C_M_AXI_SG_ADDR_WIDTH : INTEGER;
|
||||
C_M_AXI_SG_DATA_WIDTH : INTEGER;
|
||||
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : INTEGER;
|
||||
C_S_AXIS_S2MM_STS_TDATA_WIDTH : INTEGER;
|
||||
C_MICRO_DMA : INTEGER;
|
||||
C_INCLUDE_MM2S : INTEGER;
|
||||
C_INCLUDE_MM2S_SF : INTEGER;
|
||||
C_MM2S_BURST_SIZE : INTEGER;
|
||||
C_M_AXI_MM2S_ADDR_WIDTH : INTEGER;
|
||||
C_M_AXI_MM2S_DATA_WIDTH : INTEGER;
|
||||
C_M_AXIS_MM2S_TDATA_WIDTH : INTEGER;
|
||||
C_INCLUDE_MM2S_DRE : INTEGER;
|
||||
C_INCLUDE_S2MM : INTEGER;
|
||||
C_INCLUDE_S2MM_SF : INTEGER;
|
||||
C_S2MM_BURST_SIZE : INTEGER;
|
||||
C_M_AXI_S2MM_ADDR_WIDTH : INTEGER;
|
||||
C_M_AXI_S2MM_DATA_WIDTH : INTEGER;
|
||||
C_S_AXIS_S2MM_TDATA_WIDTH : INTEGER;
|
||||
C_INCLUDE_S2MM_DRE : INTEGER;
|
||||
C_INCREASE_THROUGHPUT : INTEGER;
|
||||
C_FAMILY : STRING
|
||||
);
|
||||
PORT (
|
||||
s_axi_lite_aclk : IN STD_LOGIC;
|
||||
m_axi_sg_aclk : IN STD_LOGIC;
|
||||
m_axi_mm2s_aclk : IN STD_LOGIC;
|
||||
m_axi_s2mm_aclk : IN STD_LOGIC;
|
||||
axi_resetn : IN STD_LOGIC;
|
||||
s_axi_lite_awvalid : IN STD_LOGIC;
|
||||
s_axi_lite_awready : OUT STD_LOGIC;
|
||||
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
s_axi_lite_wvalid : IN STD_LOGIC;
|
||||
s_axi_lite_wready : OUT STD_LOGIC;
|
||||
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_lite_bvalid : OUT STD_LOGIC;
|
||||
s_axi_lite_bready : IN STD_LOGIC;
|
||||
s_axi_lite_arvalid : IN STD_LOGIC;
|
||||
s_axi_lite_arready : OUT STD_LOGIC;
|
||||
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
s_axi_lite_rvalid : OUT STD_LOGIC;
|
||||
s_axi_lite_rready : IN STD_LOGIC;
|
||||
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_sg_awaddr : OUT STD_LOGIC_VECTOR(39 DOWNTO 0);
|
||||
m_axi_sg_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_sg_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_sg_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_sg_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_sg_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_sg_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_sg_awvalid : OUT STD_LOGIC;
|
||||
m_axi_sg_awready : IN STD_LOGIC;
|
||||
m_axi_sg_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_sg_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_sg_wlast : OUT STD_LOGIC;
|
||||
m_axi_sg_wvalid : OUT STD_LOGIC;
|
||||
m_axi_sg_wready : IN STD_LOGIC;
|
||||
m_axi_sg_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_sg_bvalid : IN STD_LOGIC;
|
||||
m_axi_sg_bready : OUT STD_LOGIC;
|
||||
m_axi_sg_araddr : OUT STD_LOGIC_VECTOR(39 DOWNTO 0);
|
||||
m_axi_sg_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_sg_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_sg_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_sg_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_sg_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_sg_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_sg_arvalid : OUT STD_LOGIC;
|
||||
m_axi_sg_arready : IN STD_LOGIC;
|
||||
m_axi_sg_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_sg_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_sg_rlast : IN STD_LOGIC;
|
||||
m_axi_sg_rvalid : IN STD_LOGIC;
|
||||
m_axi_sg_rready : OUT STD_LOGIC;
|
||||
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(39 DOWNTO 0);
|
||||
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_mm2s_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_mm2s_arvalid : OUT STD_LOGIC;
|
||||
m_axi_mm2s_arready : IN STD_LOGIC;
|
||||
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_mm2s_rlast : IN STD_LOGIC;
|
||||
m_axi_mm2s_rvalid : IN STD_LOGIC;
|
||||
m_axi_mm2s_rready : OUT STD_LOGIC;
|
||||
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
|
||||
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axis_mm2s_tvalid : OUT STD_LOGIC;
|
||||
m_axis_mm2s_tready : IN STD_LOGIC;
|
||||
m_axis_mm2s_tlast : OUT STD_LOGIC;
|
||||
m_axis_mm2s_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axis_mm2s_tid : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
|
||||
m_axis_mm2s_tdest : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
|
||||
mm2s_cntrl_reset_out_n : OUT STD_LOGIC;
|
||||
m_axis_mm2s_cntrl_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axis_mm2s_cntrl_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axis_mm2s_cntrl_tvalid : OUT STD_LOGIC;
|
||||
m_axis_mm2s_cntrl_tready : IN STD_LOGIC;
|
||||
m_axis_mm2s_cntrl_tlast : OUT STD_LOGIC;
|
||||
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(39 DOWNTO 0);
|
||||
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_s2mm_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_s2mm_awvalid : OUT STD_LOGIC;
|
||||
m_axi_s2mm_awready : IN STD_LOGIC;
|
||||
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
|
||||
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_s2mm_wlast : OUT STD_LOGIC;
|
||||
m_axi_s2mm_wvalid : OUT STD_LOGIC;
|
||||
m_axi_s2mm_wready : IN STD_LOGIC;
|
||||
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_s2mm_bvalid : IN STD_LOGIC;
|
||||
m_axi_s2mm_bready : OUT STD_LOGIC;
|
||||
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
|
||||
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
|
||||
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
s_axis_s2mm_tvalid : IN STD_LOGIC;
|
||||
s_axis_s2mm_tready : OUT STD_LOGIC;
|
||||
s_axis_s2mm_tlast : IN STD_LOGIC;
|
||||
s_axis_s2mm_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axis_s2mm_tid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
|
||||
s_axis_s2mm_tdest : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
|
||||
s2mm_sts_reset_out_n : OUT STD_LOGIC;
|
||||
s_axis_s2mm_sts_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axis_s2mm_sts_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axis_s2mm_sts_tvalid : IN STD_LOGIC;
|
||||
s_axis_s2mm_sts_tready : OUT STD_LOGIC;
|
||||
s_axis_s2mm_sts_tlast : IN STD_LOGIC;
|
||||
mm2s_introut : OUT STD_LOGIC;
|
||||
s2mm_introut : OUT STD_LOGIC;
|
||||
axi_dma_tstvec : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT axi_dma;
|
||||
ATTRIBUTE X_CORE_INFO : STRING;
|
||||
ATTRIBUTE X_CORE_INFO OF system_top_axi_dma_0_0_arch: ARCHITECTURE IS "axi_dma,Vivado 2024.1";
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE OF system_top_axi_dma_0_0_arch : ARCHITECTURE IS "system_top_axi_dma_0_0,axi_dma,{}";
|
||||
ATTRIBUTE CORE_GENERATION_INFO : STRING;
|
||||
ATTRIBUTE CORE_GENERATION_INFO OF system_top_axi_dma_0_0_arch: ARCHITECTURE IS "system_top_axi_dma_0_0,axi_dma,{x_ipProduct=Vivado 2024.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_dma,x_ipVersion=7.1,x_ipCoreRevision=32,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_S_AXI_LITE_ADDR_WIDTH=10,C_S_AXI_LITE_DATA_WIDTH=32,C_DLYTMR_RESOLUTION=125,C_PRMRY_IS_ACLK_ASYNC=1,C_ENABLE_MULTI_CHANNEL=0,C_NUM_MM2S_CHANNELS=1,C_NUM_S2MM_CHANNELS=1,C_INCLUDE_SG=0,C_SG_INCLUDE_STSCNTRL_STRM=0,C_SG_USE_STSAPP_LENGTH=0,C_SG_LENGTH_WIDTH=26,C_M_AXI_SG_ADDR_WIDTH=40,C_M_AXI_SG_DATA_WIDTH=3" &
|
||||
"2,C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH=32,C_S_AXIS_S2MM_STS_TDATA_WIDTH=32,C_MICRO_DMA=0,C_INCLUDE_MM2S=0,C_INCLUDE_MM2S_SF=1,C_MM2S_BURST_SIZE=16,C_M_AXI_MM2S_ADDR_WIDTH=40,C_M_AXI_MM2S_DATA_WIDTH=32,C_M_AXIS_MM2S_TDATA_WIDTH=32,C_INCLUDE_MM2S_DRE=0,C_INCLUDE_S2MM=1,C_INCLUDE_S2MM_SF=1,C_S2MM_BURST_SIZE=16,C_M_AXI_S2MM_ADDR_WIDTH=40,C_M_AXI_S2MM_DATA_WIDTH=64,C_S_AXIS_S2MM_TDATA_WIDTH=64,C_INCLUDE_S2MM_DRE=0,C_INCREASE_THROUGHPUT=0,C_FAMILY=zynq}";
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF axi_resetn: SIGNAL IS "XIL_INTERFACENAME AXI_RESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF axi_resetn: SIGNAL IS "xilinx.com:signal:reset:1.0 AXI_RESETN RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axi_s2mm_aclk: SIGNAL IS "XIL_INTERFACENAME M_AXI_S2MM_CLK, ASSOCIATED_BUSIF M_AXI_S2MM:S_AXIS_S2MM:S_AXIS_STS, ASSOCIATED_RESET s2mm_prmry_reset_out_n:s2mm_sts_reset_out_n, FREQ_HZ 200000000, FREQ_TOLERANCE_HZ 0, PHASE 0, CLK_DOMAIN system_top_mig_7series_0_0_ui_clk, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_S2MM_CLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axi_s2mm_awaddr: SIGNAL IS "XIL_INTERFACENAME M_AXI_S2MM, SUPPORTS_NARROW_BURST 0, NUM_WRITE_OUTSTANDING 16, DATA_WIDTH 64, PROTOCOL AXI4, FREQ_HZ 200000000, ID_WIDTH 0, ADDR_WIDTH 40, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, NUM_READ_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0, CLK_DOMAIN system_top_mig_7series_0_0_ui_clk, NUM_READ_THREADS 1, NUM_" &
|
||||
"WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWBURST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWCACHE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWLEN";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWPROT";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWSIZE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WSTRB";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s2mm_introut: SIGNAL IS "XIL_INTERFACENAME S2MM_INTROUT, SENSITIVITY LEVEL_HIGH, PortWidth 1";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s2mm_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 S2MM_INTROUT INTERRUPT";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s2mm_prmry_reset_out_n: SIGNAL IS "XIL_INTERFACENAME S2MM_PRMRY_RESET_OUT_N, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s2mm_prmry_reset_out_n: SIGNAL IS "xilinx.com:signal:reset:1.0 S2MM_PRMRY_RESET_OUT_N RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_lite_aclk: SIGNAL IS "XIL_INTERFACENAME S_AXI_LITE_ACLK, ASSOCIATED_BUSIF S_AXI_LITE:M_AXI, ASSOCIATED_RESET axi_resetn, FREQ_HZ 1e+08, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN system_top_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_LITE_ACLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_lite_awvalid: SIGNAL IS "XIL_INTERFACENAME S_AXI_LITE, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 10, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 0, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN system_top_processing_system7_0_0_FCLK_CLK0, NUM_READ_THR" &
|
||||
"EADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_s2mm_tdata: SIGNAL IS "XIL_INTERFACENAME S_AXIS_S2MM, TDATA_NUM_BYTES 8, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 1, HAS_TLAST 1, FREQ_HZ 200000000, PHASE 0, CLK_DOMAIN system_top_mig_7series_0_0_ui_clk, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TKEEP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TVALID";
|
||||
BEGIN
|
||||
U0 : axi_dma
|
||||
GENERIC MAP (
|
||||
C_S_AXI_LITE_ADDR_WIDTH => 10,
|
||||
C_S_AXI_LITE_DATA_WIDTH => 32,
|
||||
C_DLYTMR_RESOLUTION => 125,
|
||||
C_PRMRY_IS_ACLK_ASYNC => 1,
|
||||
C_ENABLE_MULTI_CHANNEL => 0,
|
||||
C_NUM_MM2S_CHANNELS => 1,
|
||||
C_NUM_S2MM_CHANNELS => 1,
|
||||
C_INCLUDE_SG => 0,
|
||||
C_SG_INCLUDE_STSCNTRL_STRM => 0,
|
||||
C_SG_USE_STSAPP_LENGTH => 0,
|
||||
C_SG_LENGTH_WIDTH => 26,
|
||||
C_M_AXI_SG_ADDR_WIDTH => 40,
|
||||
C_M_AXI_SG_DATA_WIDTH => 32,
|
||||
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => 32,
|
||||
C_S_AXIS_S2MM_STS_TDATA_WIDTH => 32,
|
||||
C_MICRO_DMA => 0,
|
||||
C_INCLUDE_MM2S => 0,
|
||||
C_INCLUDE_MM2S_SF => 1,
|
||||
C_MM2S_BURST_SIZE => 16,
|
||||
C_M_AXI_MM2S_ADDR_WIDTH => 40,
|
||||
C_M_AXI_MM2S_DATA_WIDTH => 32,
|
||||
C_M_AXIS_MM2S_TDATA_WIDTH => 32,
|
||||
C_INCLUDE_MM2S_DRE => 0,
|
||||
C_INCLUDE_S2MM => 1,
|
||||
C_INCLUDE_S2MM_SF => 1,
|
||||
C_S2MM_BURST_SIZE => 16,
|
||||
C_M_AXI_S2MM_ADDR_WIDTH => 40,
|
||||
C_M_AXI_S2MM_DATA_WIDTH => 64,
|
||||
C_S_AXIS_S2MM_TDATA_WIDTH => 64,
|
||||
C_INCLUDE_S2MM_DRE => 0,
|
||||
C_INCREASE_THROUGHPUT => 0,
|
||||
C_FAMILY => "zynq"
|
||||
)
|
||||
PORT MAP (
|
||||
s_axi_lite_aclk => s_axi_lite_aclk,
|
||||
m_axi_sg_aclk => '0',
|
||||
m_axi_mm2s_aclk => '0',
|
||||
m_axi_s2mm_aclk => m_axi_s2mm_aclk,
|
||||
axi_resetn => axi_resetn,
|
||||
s_axi_lite_awvalid => s_axi_lite_awvalid,
|
||||
s_axi_lite_awready => s_axi_lite_awready,
|
||||
s_axi_lite_awaddr => s_axi_lite_awaddr,
|
||||
s_axi_lite_wvalid => s_axi_lite_wvalid,
|
||||
s_axi_lite_wready => s_axi_lite_wready,
|
||||
s_axi_lite_wdata => s_axi_lite_wdata,
|
||||
s_axi_lite_bresp => s_axi_lite_bresp,
|
||||
s_axi_lite_bvalid => s_axi_lite_bvalid,
|
||||
s_axi_lite_bready => s_axi_lite_bready,
|
||||
s_axi_lite_arvalid => s_axi_lite_arvalid,
|
||||
s_axi_lite_arready => s_axi_lite_arready,
|
||||
s_axi_lite_araddr => s_axi_lite_araddr,
|
||||
s_axi_lite_rvalid => s_axi_lite_rvalid,
|
||||
s_axi_lite_rready => s_axi_lite_rready,
|
||||
s_axi_lite_rdata => s_axi_lite_rdata,
|
||||
s_axi_lite_rresp => s_axi_lite_rresp,
|
||||
m_axi_sg_awready => '0',
|
||||
m_axi_sg_wready => '0',
|
||||
m_axi_sg_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
|
||||
m_axi_sg_bvalid => '0',
|
||||
m_axi_sg_arready => '0',
|
||||
m_axi_sg_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
m_axi_sg_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
|
||||
m_axi_sg_rlast => '0',
|
||||
m_axi_sg_rvalid => '0',
|
||||
m_axi_mm2s_arready => '0',
|
||||
m_axi_mm2s_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
m_axi_mm2s_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
|
||||
m_axi_mm2s_rlast => '0',
|
||||
m_axi_mm2s_rvalid => '0',
|
||||
m_axis_mm2s_tready => '0',
|
||||
m_axis_mm2s_cntrl_tready => '0',
|
||||
m_axi_s2mm_awaddr => m_axi_s2mm_awaddr,
|
||||
m_axi_s2mm_awlen => m_axi_s2mm_awlen,
|
||||
m_axi_s2mm_awsize => m_axi_s2mm_awsize,
|
||||
m_axi_s2mm_awburst => m_axi_s2mm_awburst,
|
||||
m_axi_s2mm_awprot => m_axi_s2mm_awprot,
|
||||
m_axi_s2mm_awcache => m_axi_s2mm_awcache,
|
||||
m_axi_s2mm_awvalid => m_axi_s2mm_awvalid,
|
||||
m_axi_s2mm_awready => m_axi_s2mm_awready,
|
||||
m_axi_s2mm_wdata => m_axi_s2mm_wdata,
|
||||
m_axi_s2mm_wstrb => m_axi_s2mm_wstrb,
|
||||
m_axi_s2mm_wlast => m_axi_s2mm_wlast,
|
||||
m_axi_s2mm_wvalid => m_axi_s2mm_wvalid,
|
||||
m_axi_s2mm_wready => m_axi_s2mm_wready,
|
||||
m_axi_s2mm_bresp => m_axi_s2mm_bresp,
|
||||
m_axi_s2mm_bvalid => m_axi_s2mm_bvalid,
|
||||
m_axi_s2mm_bready => m_axi_s2mm_bready,
|
||||
s2mm_prmry_reset_out_n => s2mm_prmry_reset_out_n,
|
||||
s_axis_s2mm_tdata => s_axis_s2mm_tdata,
|
||||
s_axis_s2mm_tkeep => s_axis_s2mm_tkeep,
|
||||
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid,
|
||||
s_axis_s2mm_tready => s_axis_s2mm_tready,
|
||||
s_axis_s2mm_tlast => s_axis_s2mm_tlast,
|
||||
s_axis_s2mm_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
s_axis_s2mm_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
|
||||
s_axis_s2mm_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
|
||||
s_axis_s2mm_sts_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
s_axis_s2mm_sts_tkeep => X"F",
|
||||
s_axis_s2mm_sts_tvalid => '0',
|
||||
s_axis_s2mm_sts_tlast => '0',
|
||||
s2mm_introut => s2mm_introut,
|
||||
axi_dma_tstvec => axi_dma_tstvec
|
||||
);
|
||||
END system_top_axi_dma_0_0_arch;
|
||||
+976
@@ -0,0 +1,976 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "system_top_axi_dma_0_0",
|
||||
"cell_name": "axi_dma_0",
|
||||
"component_reference": "xilinx.com:ip:axi_dma:7.1",
|
||||
"ip_revision": "32",
|
||||
"gen_directory": ".",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "system_top_axi_dma_0_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"c_include_sg": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_enable_multi_channel": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"c_num_mm2s_channels": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"c_num_s2mm_channels": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"c_sg_length_width": [ { "value": "26", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_dlytmr_resolution": [ { "value": "125", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_prmry_is_aclk_async": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_sg_include_stscntrl_strm": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"c_micro_dma": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_include_mm2s": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_m_axi_mm2s_data_width": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"c_m_axis_mm2s_tdata_width": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"c_include_mm2s_dre": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"c_include_mm2s_sf": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_mm2s_burst_size": [ { "value": "16", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"c_include_s2mm": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_sg_use_stsapp_length": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"c_m_axi_s2mm_data_width": [ { "value": "64", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_s_axis_s2mm_tdata_width": [ { "value": "64", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_include_s2mm_dre": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_include_s2mm_sf": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_s2mm_burst_size": [ { "value": "16", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_addr_width": [ { "value": "40", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_single_interface": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"c_increase_throughput": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_S_AXI_LITE_ADDR_WIDTH": [ { "value": "10", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_LITE_DATA_WIDTH": [ { "value": "32", "format": "long", "usage": "all" } ],
|
||||
"C_DLYTMR_RESOLUTION": [ { "value": "125", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PRMRY_IS_ACLK_ASYNC": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ENABLE_MULTI_CHANNEL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_MM2S_CHANNELS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_S2MM_CHANNELS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INCLUDE_SG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SG_INCLUDE_STSCNTRL_STRM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SG_USE_STSAPP_LENGTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SG_LENGTH_WIDTH": [ { "value": "26", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_AXI_SG_ADDR_WIDTH": [ { "value": "40", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_AXI_SG_DATA_WIDTH": [ { "value": "32", "format": "long", "usage": "all" } ],
|
||||
"C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_S_AXIS_S2MM_STS_TDATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_MICRO_DMA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INCLUDE_MM2S": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INCLUDE_MM2S_SF": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_MM2S_BURST_SIZE": [ { "value": "16", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_M_AXI_MM2S_ADDR_WIDTH": [ { "value": "40", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_M_AXI_MM2S_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_M_AXIS_MM2S_TDATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_INCLUDE_MM2S_DRE": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_INCLUDE_S2MM": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INCLUDE_S2MM_SF": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S2MM_BURST_SIZE": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_AXI_S2MM_ADDR_WIDTH": [ { "value": "40", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_AXI_S2MM_DATA_WIDTH": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXIS_S2MM_TDATA_WIDTH": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INCLUDE_S2MM_DRE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INCREASE_THROUGHPUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_FAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "xilinx.com:zc706:part0:1.4" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z045" } ],
|
||||
"NEXTGEN_VERSAL": [ { "value": "0" } ],
|
||||
"PACKAGE": [ { "value": "ffg900" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "32" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "." } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2024.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"s_axi_lite_aclk": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"m_axi_s2mm_aclk": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"axi_resetn": [ { "direction": "in", "driver_value": "1" } ],
|
||||
"s_axi_lite_awvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_lite_awready": [ { "direction": "out" } ],
|
||||
"s_axi_lite_awaddr": [ { "direction": "in", "size_left": "9", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_lite_wvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_lite_wready": [ { "direction": "out" } ],
|
||||
"s_axi_lite_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_lite_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s_axi_lite_bvalid": [ { "direction": "out" } ],
|
||||
"s_axi_lite_bready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_lite_arvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_lite_arready": [ { "direction": "out" } ],
|
||||
"s_axi_lite_araddr": [ { "direction": "in", "size_left": "9", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_lite_rvalid": [ { "direction": "out" } ],
|
||||
"s_axi_lite_rready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_lite_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"s_axi_lite_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"m_axi_s2mm_awaddr": [ { "direction": "out", "size_left": "39", "size_right": "0" } ],
|
||||
"m_axi_s2mm_awlen": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
|
||||
"m_axi_s2mm_awsize": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||
"m_axi_s2mm_awburst": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"m_axi_s2mm_awprot": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||
"m_axi_s2mm_awcache": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||
"m_axi_s2mm_awvalid": [ { "direction": "out" } ],
|
||||
"m_axi_s2mm_awready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"m_axi_s2mm_wdata": [ { "direction": "out", "size_left": "63", "size_right": "0" } ],
|
||||
"m_axi_s2mm_wstrb": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
|
||||
"m_axi_s2mm_wlast": [ { "direction": "out" } ],
|
||||
"m_axi_s2mm_wvalid": [ { "direction": "out" } ],
|
||||
"m_axi_s2mm_wready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"m_axi_s2mm_bresp": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"m_axi_s2mm_bvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"m_axi_s2mm_bready": [ { "direction": "out" } ],
|
||||
"s2mm_prmry_reset_out_n": [ { "direction": "out" } ],
|
||||
"s_axis_s2mm_tdata": [ { "direction": "in", "size_left": "63", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axis_s2mm_tkeep": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0xFF" } ],
|
||||
"s_axis_s2mm_tvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axis_s2mm_tready": [ { "direction": "out" } ],
|
||||
"s_axis_s2mm_tlast": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s2mm_introut": [ { "direction": "out" } ],
|
||||
"axi_dma_tstvec": [ { "direction": "out", "size_left": "31", "size_right": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"S_AXI_LITE": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"memory_map_ref": "S_AXI_LITE",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "1e+08", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "10", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"ARADDR": [ { "physical_name": "s_axi_lite_araddr" } ],
|
||||
"ARREADY": [ { "physical_name": "s_axi_lite_arready" } ],
|
||||
"ARVALID": [ { "physical_name": "s_axi_lite_arvalid" } ],
|
||||
"AWADDR": [ { "physical_name": "s_axi_lite_awaddr" } ],
|
||||
"AWREADY": [ { "physical_name": "s_axi_lite_awready" } ],
|
||||
"AWVALID": [ { "physical_name": "s_axi_lite_awvalid" } ],
|
||||
"BREADY": [ { "physical_name": "s_axi_lite_bready" } ],
|
||||
"BRESP": [ { "physical_name": "s_axi_lite_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "s_axi_lite_bvalid" } ],
|
||||
"RDATA": [ { "physical_name": "s_axi_lite_rdata" } ],
|
||||
"RREADY": [ { "physical_name": "s_axi_lite_rready" } ],
|
||||
"RRESP": [ { "physical_name": "s_axi_lite_rresp" } ],
|
||||
"RVALID": [ { "physical_name": "s_axi_lite_rvalid" } ],
|
||||
"WDATA": [ { "physical_name": "s_axi_lite_wdata" } ],
|
||||
"WREADY": [ { "physical_name": "s_axi_lite_wready" } ],
|
||||
"WVALID": [ { "physical_name": "s_axi_lite_wvalid" } ]
|
||||
}
|
||||
},
|
||||
"M_AXI_S2MM": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "master",
|
||||
"address_space_ref": "Data_S2MM",
|
||||
"parameters": {
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
|
||||
"DATA_WIDTH": [ { "value": "64", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "200000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "40", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "WRITE_ONLY", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "16", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_mig_7series_0_0_ui_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"AWADDR": [ { "physical_name": "m_axi_s2mm_awaddr" } ],
|
||||
"AWBURST": [ { "physical_name": "m_axi_s2mm_awburst" } ],
|
||||
"AWCACHE": [ { "physical_name": "m_axi_s2mm_awcache" } ],
|
||||
"AWLEN": [ { "physical_name": "m_axi_s2mm_awlen" } ],
|
||||
"AWPROT": [ { "physical_name": "m_axi_s2mm_awprot" } ],
|
||||
"AWREADY": [ { "physical_name": "m_axi_s2mm_awready" } ],
|
||||
"AWSIZE": [ { "physical_name": "m_axi_s2mm_awsize" } ],
|
||||
"AWVALID": [ { "physical_name": "m_axi_s2mm_awvalid" } ],
|
||||
"BREADY": [ { "physical_name": "m_axi_s2mm_bready" } ],
|
||||
"BRESP": [ { "physical_name": "m_axi_s2mm_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "m_axi_s2mm_bvalid" } ],
|
||||
"WDATA": [ { "physical_name": "m_axi_s2mm_wdata" } ],
|
||||
"WLAST": [ { "physical_name": "m_axi_s2mm_wlast" } ],
|
||||
"WREADY": [ { "physical_name": "m_axi_s2mm_wready" } ],
|
||||
"WSTRB": [ { "physical_name": "m_axi_s2mm_wstrb" } ],
|
||||
"WVALID": [ { "physical_name": "m_axi_s2mm_wvalid" } ]
|
||||
}
|
||||
},
|
||||
"S_AXIS_S2MM": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "8", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "200000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_mig_7series_0_0_ui_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "s_axis_s2mm_tdata" } ],
|
||||
"TKEEP": [ { "physical_name": "s_axis_s2mm_tkeep" } ],
|
||||
"TLAST": [ { "physical_name": "s_axis_s2mm_tlast" } ],
|
||||
"TREADY": [ { "physical_name": "s_axis_s2mm_tready" } ],
|
||||
"TVALID": [ { "physical_name": "s_axis_s2mm_tvalid" } ]
|
||||
}
|
||||
},
|
||||
"AXI_RESETN": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "axi_resetn" } ]
|
||||
}
|
||||
},
|
||||
"MM2S_INTROUT": {
|
||||
"vlnv": "xilinx.com:signal:interrupt:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"SENSITIVITY": [ { "value": "LEVEL_HIGH", "value_src": "constant", "usage": "all" } ],
|
||||
"PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"S2MM_INTROUT": {
|
||||
"vlnv": "xilinx.com:signal:interrupt:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"SENSITIVITY": [ { "value": "LEVEL_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"PortWidth": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"INTERRUPT": [ { "physical_name": "s2mm_introut" } ]
|
||||
}
|
||||
},
|
||||
"M_AXI_SG_CLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "M_AXI_SG", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"M_AXI_MM2S_CLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "M_AXI_MM2S:M_AXIS_MM2S:M_AXIS_CNTRL", "value_src": "constant", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "mm2s_prmry_reset_out_n:mm2s_cntrl_reset_out_n", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"M_AXI_S2MM_CLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "M_AXI_S2MM:S_AXIS_S2MM:S_AXIS_STS", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "s2mm_prmry_reset_out_n:s2mm_sts_reset_out_n", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "200000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_mig_7series_0_0_ui_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "m_axi_s2mm_aclk" } ]
|
||||
}
|
||||
},
|
||||
"S_AXI_LITE_ACLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S_AXI_LITE:M_AXI", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "axi_resetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "1e+08", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "s_axi_lite_aclk" } ]
|
||||
}
|
||||
},
|
||||
"MM2S_PRMRY_RESET_OUT_N": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"S2MM_PRMRY_RESET_OUT_N": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "s2mm_prmry_reset_out_n" } ]
|
||||
}
|
||||
},
|
||||
"MM2S_CNTRL_RESET_OUT_N": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"S2MM_STS_RESET_OUT_N": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
}
|
||||
},
|
||||
"address_spaces": {
|
||||
"Data_S2MM": {
|
||||
"range": "1099511627776",
|
||||
"width": "40"
|
||||
}
|
||||
},
|
||||
"memory_maps": {
|
||||
"S_AXI_LITE": {
|
||||
"display_name": "S_AXI_MEM",
|
||||
"description": "Memory Map for S_AXI_LITE",
|
||||
"address_blocks": {
|
||||
"Reg": {
|
||||
"base_address": "0",
|
||||
"range": "4096",
|
||||
"display_name": "Reg",
|
||||
"description": "Register Block",
|
||||
"usage": "register",
|
||||
"access": "read-write",
|
||||
"registers": {
|
||||
"MM2S_DMACR": {
|
||||
"address_offset": "0x0",
|
||||
"size": 32,
|
||||
"display_name": "MM2S DMA Control Register",
|
||||
"description": "MM2S DMA Control Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x10002",
|
||||
"fields": {
|
||||
"RS": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 1,
|
||||
"display_name": "Run/Stop Control",
|
||||
"description": "Run / Stop control for controlling running and stopping of the DMA channel.\n 0 - Stop, DMA stops when current (if any) DMA operations are complete. For Scatter / Gather Mode pending commands/transfers are flushed or completed. \n AXI4-Stream outs are potentially terminated early. Descriptors in the update queue are allowed to finish updating to remote memory before engine halt.\n For Direct Register mode pending commands/transfers are flushed or completed. AXI4-Stream outs are potentially terminated.\n The halted bit in the DMA Status register asserts to 1 when the DMA engine is halted. This bit is cleared by AXI DMA hardware when an error occurs. The CPU can also choose to clear this bit to stop DMA operations.\n 1 - Run, Start DMA operations. The halted bit in the DMA Status register deasserts to 0 when the DMA engine begins operations.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Reset": {
|
||||
"bit_offset": 2,
|
||||
"bit_width": 1,
|
||||
"display_name": "Soft Reset",
|
||||
"description": "Soft reset for resetting the AXI DMA core. Setting this bit to a 1 causes the AXI DMA to be reset. Reset is accomplished gracefully. Pending commands/transfers are flushed or completed.\nAXI4-Stream outs are potentially terminated early. Setting either MM2S_DMACR. Reset = 1 or S2MM_DMACR.Reset = 1 resets the entire AXI DMA engine. After completion of a soft reset, all registers and bits are in the Reset State. 0 - Normal operation. 1 - Reset in progress.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Keyhole": {
|
||||
"bit_offset": 3,
|
||||
"bit_width": 1,
|
||||
"display_name": "Keyhole Read",
|
||||
"description": "Keyhole Read. Setting this bit to 1 causes AXI DMA to initiate MM2S reads (AXI4read) in non-incrementing address mode (Fixed Address Burst transfer on AXI4). This bit can be updated when AXI DMA is in idle. When using keyhole operation the Max Burst Length should not exceed 16. This bit should not be set when DRE is enabled.\nThis bit is non functional when the multichannel feature is enabled or in Direct Register mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Cyclic_BD_Enable": {
|
||||
"bit_offset": 4,
|
||||
"bit_width": 1,
|
||||
"display_name": "Cyclic BD Enable",
|
||||
"description": "When set to 1, the DMA operates in Cyclic Buffer Descriptor (BD) mode without any user intervention. In this mode, the Scatter Gather module ignores the Completed bit of the BD. With this bit set, you can use the same BDs in cyclic manner without worrying about any stale descriptor errors.\nThis bit should be set/unset only when the DMA is idle or when not running. Updating this bit while the DMA is running can result in unexpected behavior.\nThis bit is non functional when DMA operates in multichannel mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"IOC_IrqEn": {
|
||||
"bit_offset": 12,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Complete (IOC) Interrupt Enable",
|
||||
"description": "Interrupt on Complete (IOC) Interrupt Enable. When set to 1, allows DMASR.IOC_Irq to generate an interrupt out for descriptors with the IOC bit set. 0 - IOC Interrupt disabled 1 - IOC Interrupt enabled\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Dly_IrqEn": {
|
||||
"bit_offset": 13,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Delay Timer Interrupt Enable",
|
||||
"description": "Interrupt on Delay Timer Interrupt Enable. When set to 1, allows DMASR.Dly_Irq to generate an interrupt out. 0 - Delay Interrupt disabled 1 - Delay Interrupt enabled Note: This field is ignored when AXI DMA is configured for Direct Register Mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Err_IrqEn": {
|
||||
"bit_offset": 14,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Error Interrupt Enable",
|
||||
"description": "Interrupt on Error Interrupt Enable.\n 0 - Error Interrupt disabled\n 1 - Error Interrupt enabled\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"IRQThreshold": {
|
||||
"bit_offset": 16,
|
||||
"bit_width": 8,
|
||||
"display_name": "Interrupt Threshold",
|
||||
"description": "Interrupt Threshold. This value is used for setting the interrupt threshold. When IOC interrupt events occur, an internal counter counts down from the Interrupt Threshold setting. When the count reaches zero, an interrupt out is generated by the DMA engine. Note: The minimum setting for the threshold is 0x01. A write of 0x00 to this register has no effect. Note: This field is ignored when AXI DMA is configured for Direct Register Mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"IRQDelay": {
|
||||
"bit_offset": 24,
|
||||
"bit_width": 8,
|
||||
"display_name": "Interrupt Delay Time Out",
|
||||
"description": "Interrupt Delay Time Out. This value is used for setting the interrupt timeout value. The interrupt timeout mechanism causes the DMA engine to generate an interrupt after the delay time period has expired. Timer begins counting at the end of a packet and resets with receipt of a new packet or a timeout event occurs.\nNote: Setting this value to zero disables the delay timer interrupt.\nNote: This field is ignored when AXI DMA is configured for Direct Register Mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"MM2S_DMASR": {
|
||||
"address_offset": "0x04",
|
||||
"size": 32,
|
||||
"display_name": "MM2S DMA Status Register",
|
||||
"description": "MM2S DMA Status Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x10000",
|
||||
"fields": {
|
||||
"Halted": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Channel Halted",
|
||||
"description": "DMA Channel Halted. Indicates the run/stop state of the DMA channel. 0 - DMA channel running. 1 - DMA channel halted. For Scatter / Gather Mode this bit gets set when DMACR.RS = 0 and DMA and SG operations have halted. For Direct Register mode (C_INCLUDE_SG = 0) this bit gets set when DMACR.RS = 0 and DMA operations have halted. There can be a lag of time between when DMACR.RS = 0 and when DMASR.Halted = 1 Note: When halted (RS= 0 and Halted = 1), writing to CURDESC_PTR or TAILDESC_PTR pointer registers has no effect on DMA operations when in Scatter Gather Mode. For Direct Register Mode, writing to the LENGTH register has no effect on DMA operations.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"Idle": {
|
||||
"bit_offset": 1,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Channel Idle",
|
||||
"description": "DMA Channel Idle. Indicates the state of AXI DMA operations.\nFor Scatter / Gather Mode when IDLE indicates the SG Engine has reached the tail pointer for the associated channel and all queued descriptors have been processed. Writing to the tail pointer register automatically restarts DMA operations.\nFor Direct Register Mode when IDLE indicates the current transfer has completed. 0 - Not Idle. For Scatter / Gather Mode, SG has not reached tail descriptor pointer and/or DMA operations in progress. For Direct Register Mode, transfer is not complete. 1 - Idle. For Scatter / Gather Mode, SG has reached tail descriptor pointer and DMA operation paused. for Direct Register Mode, DMA transfer has completed and controller is paused. Note: This bit is 0 when channel is halted (DMASR.Halted=1). This bit is also 0 prior to initial transfer when AXI DMA configured for Direct Register Mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"SGIncld": {
|
||||
"bit_offset": 3,
|
||||
"bit_width": 1,
|
||||
"display_name": "SGIncld",
|
||||
"description": "1 - Scatter Gather Enabled\n0 - Scatter Gather not enabled\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"DMAIntErr": {
|
||||
"bit_offset": 4,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Internal Error",
|
||||
"description": "DMA Internal Error. Internal error occurs if the buffer length specified in the fetched descriptor is set to 0. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Internal Errors 1 - DMA Internal Error detected. DMA Engine halts\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"DMASlvErr": {
|
||||
"bit_offset": 5,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Slave Error",
|
||||
"description": "DMA Slave Error. This error occurs if the slave read from the Memory Map interface issues a Slave Error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Slave Errors. 1 - DMA Slave Error detected. DMA Engine halts\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"DMADecErr": {
|
||||
"bit_offset": 6,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Decode Error",
|
||||
"description": "DMA Decode Error. This error occurs if the address request points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Decode Errors. 1 - DMA Decode Error detected. DMA Engine halts.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"SGIntErr": {
|
||||
"bit_offset": 8,
|
||||
"bit_width": 1,
|
||||
"display_name": "Scatter Gather Internal Error",
|
||||
"description": "Scatter Gather Internal Error. This error occurs if a descriptor with the \"Complete bit\" already set is fetched. Refer to the Scatter Gather Descriptor section for more information.This indicates to the SG Engine that the descriptor is a stale descriptor. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Internal Errors. 1 - SG Internal Error detected. DMA Engine halts. Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"SGSlvErr": {
|
||||
"bit_offset": 9,
|
||||
"bit_width": 1,
|
||||
"display_name": "Scatter Gather Slave Error",
|
||||
"description": "Scatter Gather Slave Error. This error occurs if the slave read from on the Memory Map interface issues a Slave error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Slave Errors. 1 - SG Slave Error detected. DMA Engine halts. Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode. \n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"SGDecErr": {
|
||||
"bit_offset": 10,
|
||||
"bit_width": 1,
|
||||
"display_name": "Scatter Gather Decode Error",
|
||||
"description": "Scatter Gather Decode Error. This error occurs if CURDESC_PTR and/or NXTDESC_PTR points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Decode Errors. 1 - SG Decode Error detected. DMA Engine halts. Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode. \n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"IOC_Irq": {
|
||||
"bit_offset": 12,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Complete",
|
||||
"description": "Interrupt on Complete. When set to 1 for Scatter/Gather Mode, indicates an interrupt event was generated on completion of a descriptor. This occurs for descriptors with the End of Frame (EOF) bit set. When set to 1 for Direct Register Mode, indicates an interrupt event was generated on completion of a transfer. If the corresponding bit is enabled in the MM2S_DMACR (IOC_IrqEn = 1) and if the interrupt threshold has been met, causes an interrupt out to be generated from the AXI DMA. 0 - No IOC Interrupt. 1 - IOC Interrupt detected. Writing a 1 to this bit will clear it.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Dly_Irq": {
|
||||
"bit_offset": 13,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Delay",
|
||||
"description": "Interrupt on Delay. When set to 1, indicates an interrupt event was generated on delay timer time out. If the corresponding bit is enabled in the MM2S_DMACR (Dly_IrqEn = 1), an interrupt out is generated from the AXI DMA. 0 - No Delay Interrupt. 1 - Delay Interrupt detected. Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode. \n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Err_Irq": {
|
||||
"bit_offset": 14,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Error",
|
||||
"description": "Interrupt on Error. When set to 1, indicates an interrupt event was generated on error. If the corresponding bit is enabled in the MM2S_DMACR (Err_IrqEn = 1), an interrupt out is generated from the AXI DMA.\nWriting a 1 to this bit will clear it. \n0 - No error Interrupt. \n1 - Error interrupt detected.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"IRQThresholdSts": {
|
||||
"bit_offset": 16,
|
||||
"bit_width": 8,
|
||||
"display_name": "Interrupt Threshold Status",
|
||||
"description": "Interrupt Threshold Status. Indicates current interrupt threshold value.\nNote: Applicable only when Scatter Gather is enabled.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"IRQDelaySts": {
|
||||
"bit_offset": 24,
|
||||
"bit_width": 8,
|
||||
"display_name": "Interrupt Delay Time Status",
|
||||
"description": "Interrupt Delay Time Status. Indicates current interrupt delay time value.\nNote: Applicable only when Scatter Gather is enabled.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
}
|
||||
}
|
||||
},
|
||||
"MM2S_SA": {
|
||||
"address_offset": "0x18",
|
||||
"size": 32,
|
||||
"display_name": "MM2S Source Address Register",
|
||||
"description": "MM2S Source Address Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"Source_Address": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 32,
|
||||
"display_name": "Source Address",
|
||||
"description": "Indicates the source address AXI DMA reads from to transfer data to AXI4-Stream on the MM2S Channel.\nNote: If Data Realignment Engine is included, the Source Address can be at any byte offset. If Data Realignment Engine is not included, the Source Address must be MM2S Memory Map data width aligned.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"MM2S_SA_MSB": {
|
||||
"address_offset": "0x1C",
|
||||
"size": 32,
|
||||
"display_name": "MM2S Source Address Register",
|
||||
"description": "MM2S Source Address Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"Source_Address": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 32,
|
||||
"display_name": "Source Address",
|
||||
"description": "Indicates the MSB 32 bits of the source address AXI DMA reads from to transfer data to AXI4-Stream on the MM2S Channel.\nNote: If Data Realignment Engine is included, the Source Address can be at any byte offset. If Data Realignment Engine is not included, the Source Address must be MM2S Memory Map data width aligned.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"MM2S_LENGTH": {
|
||||
"address_offset": "0x28",
|
||||
"size": 32,
|
||||
"display_name": "MM2S DMA Transfer Length Register",
|
||||
"description": "MM2S DMA Transfer Length Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"Length": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 26,
|
||||
"display_name": "Length",
|
||||
"description": "Indicates the number of bytes to transfer for the MM2S channel. Writing a non-zero value to this register starts the MM2S transfer.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"S2MM_DMACR": {
|
||||
"address_offset": "0x30",
|
||||
"size": 32,
|
||||
"display_name": "S2MM DMA Control Register",
|
||||
"description": "S2MM DMA Control Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x10002",
|
||||
"fields": {
|
||||
"RS": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 1,
|
||||
"display_name": "Run/Stop Control",
|
||||
"description": "Run / Stop control for controlling running and stopping of the DMA channel.\n 0 - Stop, DMA stops when current (if any) DMA operations are complete. For Scatter / Gather Mode pending commands/transfers are flushed or completed. \n AXI4-Stream outs are potentially terminated early. Descriptors in the update queue are allowed to finish updating to remote memory before engine halt.\n For Direct Register mode pending commands/transfers are flushed or completed. AXI4-Stream outs are potentially terminated. Data integrity on S2MM AXI4 cannot be guaranteed.\n The halted bit in the DMA Status register asserts to 1 when the DMA engine is halted. This bit is cleared by AXI DMA hardware when an error occurs. The CPU can also choose to clear this bit to stop DMA operations.\n 1 - Run, Start DMA operations. The halted bit in the DMA Status register deasserts to 0 when the DMA engine begins operations.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Reset": {
|
||||
"bit_offset": 2,
|
||||
"bit_width": 1,
|
||||
"display_name": "Soft Reset",
|
||||
"description": "Soft reset for resetting the AXI DMA core. Setting this bit to a 1 causes the AXI DMA to be reset. Reset is accomplished gracefully. Pending commands/transfers are flushed or completed.\nAXI4-Stream outs are terminated early, if necessary with associated TLAST. Setting either MM2S_DMACR.Reset = 1 or S2MM_DMACR.Reset = 1 resets the entire AXI DMA engine. After completion of a soft reset, all registers and bits are in the Reset State. 0 - Reset not in progress. Normal operation. 1 - Reset in progress\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Keyhole": {
|
||||
"bit_offset": 3,
|
||||
"bit_width": 1,
|
||||
"display_name": "Keyhole Write",
|
||||
"description": "Keyhole Write. Setting this bit to 1 causes AXI DMA to initiate S2MM writes (AXI4 Writes) in non-incrementing address mode (Fixed Address Burst transfer on AXI4). This bit can be modified when AXI DMA is in idle. When enabling Key hole operation the maximum burst length cannot be more than 16. This bit should not be set when DRE is enabled.\nThis bit is non functional when DMA is used in multichannel mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Cyclic_BD_Enable": {
|
||||
"bit_offset": 4,
|
||||
"bit_width": 1,
|
||||
"display_name": "Cyclic BD Enable",
|
||||
"description": "When set to 1, the DMA operates in Cyclic Buffer Descriptor (BD) mode without any user intervention. In this mode, the Scatter Gather module ignores the Completed bit of the BD. With this bit set, you can use the same BDs in cyclic manner without worrying about any stale descriptor errors.\nThis bit is non functional when DMA operates in Multichannel mode. or in Direct Register Mode\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"IOC_IrqEn": {
|
||||
"bit_offset": 12,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Complete (IOC) Interrupt Enable",
|
||||
"description": "Interrupt on Complete (IOC) Interrupt Enable. When set to 1, allows Interrupt On Complete events to generate an interrupt out for descriptors with the Complete bit set. 0 - IOC Interrupt disabled 1 - IOC Interrupt enabled\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Dly_IrqEn": {
|
||||
"bit_offset": 13,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Delay Timer Interrupt Enable",
|
||||
"description": "Interrupt on Delay Timer Interrupt Enable. When set to 1, allows error events to generate an interrupt out. 0 - Delay Interrupt disabled 1 - Delay Interrupt enabled Note: Applicable only when Scatter Gather is enabled.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Err_IrqEn": {
|
||||
"bit_offset": 14,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Error Interrupt Enable",
|
||||
"description": "Interrupt on Error Interrupt Enable. When set to 1, allows error events to generate an interrupt out. 0 - Error Interrupt disabled 1 - Error Interrupt enabled\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"IRQThreshold": {
|
||||
"bit_offset": 16,
|
||||
"bit_width": 8,
|
||||
"display_name": "Interrupt Threshold",
|
||||
"description": "Interrupt Threshold. This value is used for setting the interrupt threshold. When IOC interrupt events occur, an internal counter counts down from the Interrupt Threshold setting. When the count reaches zero, an interrupt out is generated by the DMA engine.\nNote: The minimum setting for the threshold is 0x01. A write of 0x00 to this register has no effect.\nNote: Applicable only when Scatter Gather is enabled.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"IRQDelay": {
|
||||
"bit_offset": 24,
|
||||
"bit_width": 8,
|
||||
"display_name": "Interrupt Delay Time Out",
|
||||
"description": "Interrupt Delay Time Out. This value is used for setting the interrupt timeout value. The interrupt timeout mechanism causes the DMA engine to generate an interrupt after the delay time period has expired. Timer begins counting at the end of a packet and resets with receipt of a new packet or a timeout event occurs.\nNote: Setting this value to zero disables the delay timer interrupt.\nNote: Applicable only when Scatter Gather is enabled.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"S2MM_DMASR": {
|
||||
"address_offset": "0x34",
|
||||
"size": 32,
|
||||
"display_name": "S2MM DMA Status Register",
|
||||
"description": "S2MM DMA Status Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x10000",
|
||||
"fields": {
|
||||
"Halted": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Channel Halted",
|
||||
"description": "DMA Channel Halted. Indicates the run/stop state of the DMA channel. 0 - DMA channel running. 1 - DMA channel halted. For Scatter/Gather Mode this bit gets set when DMACR.RS = 0 and DMA and SG operations have halted. For Direct Register Mode this bit gets set when DMACR.RS = 0 and DMA operations have halted. There can be a lag of time between when DMACR.RS = 0 and when DMASR.Halted = 1 \nNote: When halted (RS= 0 and Halted = 1), writing to CURDESC_PTR or TAILDESC_PTR pointer registers has no effect on DMA operations when in Scatter Gather Mode. For Direct Register Mode, writing to the LENGTH register has no effect on DMA operations.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"Idle": {
|
||||
"bit_offset": 1,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Channel Idle",
|
||||
"description": "DMA Channel Idle. Indicates the state of AXI DMA operations.\nFor Scatter / Gather Mode when IDLE indicates the SG Engine has reached the tail pointer for the associated channel and all queued descriptors have been processed. Writing to the tail pointer register automatically restarts DMA operations.\nFor Direct Register Mode when IDLE indicates the current transfer has completed. 0 - Not Idle. 1 - Idle. Note: This bit is 0 when channel is halted (DMASR.Halted=1). This bit is also 0 prior to initial transfer when AXI DMA configured for Direct Register Mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"SGIncld": {
|
||||
"bit_offset": 3,
|
||||
"bit_width": 1,
|
||||
"display_name": "SGIncld",
|
||||
"description": "Scatter Gather Engine Included. DMASR.SGIncld = 1 indicates the Scatter Gather engine is included and the AXI DMA is configured for Scatter Gather mode. DMASR.SGIncld = 0 indicates the Scatter Gather engine is excluded and the AXI DMA is configured for Direct Register Mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"DMAIntErr": {
|
||||
"bit_offset": 4,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Internal Error",
|
||||
"description": "DMA Internal Error. This error occurs if the buffer length specified in the fetched descriptor is set to 0. Also, when in Scatter Gather Mode and using the status app length field, this error occurs when the Status AXI4-Stream packet RxLength field does not match the S2MM packet being received by the S_AXIS_S2MM interface. When Scatter Gather is disabled, this error is flagged if any error occurs during Memory write or if the incoming packet is bigger than what is specified in the DMA length register.\nThis error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Internal Errors 1 - DMA Internal Error detected.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"DMASlvErr": {
|
||||
"bit_offset": 5,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Slave Error",
|
||||
"description": "DMA Slave Error. This error occurs if the slave read from the Memory Map interface issues a Slave Error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Slave Errors. 1 - DMA Slave Error detected.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"DMADecErr": {
|
||||
"bit_offset": 6,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Decode Error",
|
||||
"description": "DMA Decode Error. This error occurs if the address request points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Decode Errors. 1 - DMA Decode Error detected.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"SGIntErr": {
|
||||
"bit_offset": 8,
|
||||
"bit_width": 1,
|
||||
"display_name": "Scatter Gather Internal Error",
|
||||
"description": "Scatter Gather Internal Error. This error occurs if a descriptor with the \"Complete bit\" already set is fetched. This indicates to the SG Engine that the descriptor is a tail descriptor. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Internal Errors. 1 - SG Internal Error detected. Note: Applicable only when Scatter Gather is enabled. \n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"SGSlvErr": {
|
||||
"bit_offset": 9,
|
||||
"bit_width": 1,
|
||||
"display_name": "Scatter Gather Slave Error",
|
||||
"description": "Scatter Gather Slave Error. This error occurs if the slave read from on the Memory Map interface issues a Slave error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Slave Errors. 1 - SG Slave Error detected. DMA Engine halts. Note: Applicable only when Scatter Gather is enabled. \n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"SGDecErr": {
|
||||
"bit_offset": 10,
|
||||
"bit_width": 1,
|
||||
"display_name": "Scatter Gather Decode Error",
|
||||
"description": "Scatter Gather Decode Error. This error occurs if CURDESC_PTR and/or NXTDESC_PTR points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Decode Errors. 1 - SG Decode Error detected. DMA Engine halts. Note: Applicable only when Scatter Gather is enabled. \n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"IOC_Irq": {
|
||||
"bit_offset": 12,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Complete",
|
||||
"description": "Interrupt on Complete. When set to 1 for Scatter/Gather Mode, indicates an interrupt event was generated on completion of a descriptor. This occurs for descriptors with the End of Frame (EOF) bit set. When set to 1 for Direct Register Mode, indicates an interrupt event was generated on completion of a transfer. If the corresponding bit in S2MM_DMACR is enabled (IOC_IrqEn = 1) and if the interrupt threshold has been met, causes an interrupt out to be generated from the AXI DMA. 0 - No IOC Interrupt. 1 - IOC Interrupt detected. Writing a 1 to this bit will clear it.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Dly_Irq": {
|
||||
"bit_offset": 13,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Delay",
|
||||
"description": "Interrupt on Delay. When set to 1, indicates an interrupt event was generated on delay timer time out. If the corresponding bit is enabled in the S2MM_DMACR (Dly_IrqEn = 1), an interrupt out is generated from the AXI DMA. 0 - No Delay Interrupt. 1 - Delay Interrupt detected.1 = IOC Interrupt detected. Writing a 1 to this bit will clear it. Note: Applicable only when Scatter Gather is enabled. \n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Err_Irq": {
|
||||
"bit_offset": 14,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Error",
|
||||
"description": "Interrupt on Error. When set to 1, indicates an interrupt event was generated on error. If the corresponding bit is enabled in the S2MM_DMACR (Err_IrqEn = 1), an interrupt out is generated from the AXI DMA.\nWriting a 1 to this bit will clear it. 0 - No error Interrupt. 1 - Error interrupt detected.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"IRQThresholdSts": {
|
||||
"bit_offset": 16,
|
||||
"bit_width": 8,
|
||||
"display_name": "Interrupt Threshold Status",
|
||||
"description": "Interrupt Threshold Status. Indicates current interrupt threshold value.\nNote: Applicable only when Scatter Gather is enabled.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"IRQDelaySts": {
|
||||
"bit_offset": 24,
|
||||
"bit_width": 8,
|
||||
"display_name": "Interrupt Delay Time Status",
|
||||
"description": "Interrupt Delay Time Status. Indicates current interrupt delay time value.\nNote: Applicable only when Scatter Gather is enabled.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
}
|
||||
}
|
||||
},
|
||||
"S2MM_DA": {
|
||||
"address_offset": "0x48",
|
||||
"size": 32,
|
||||
"display_name": "S2MM DMA Destination Address Register",
|
||||
"description": "S2MM DMA Destination Address Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"Destination_Address": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 32,
|
||||
"display_name": "Destination Address",
|
||||
"description": "Indicates the destination address the AXI DMA writes to transfer data from AXI4-Stream on S2MM Channel.\nNote: If Data Realignment Engine is included, the Destination Address can be at any byte offset. If Data Realignment Engine is not included, the Destination Address must be S2MM Memory Map data width aligned.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"S2MM_DA_MSB": {
|
||||
"address_offset": "0x4C",
|
||||
"size": 32,
|
||||
"display_name": "S2MM Destination Address Register",
|
||||
"description": "S2MM Destination Address Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"Destination_Address": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 32,
|
||||
"display_name": "Destination Address",
|
||||
"description": "Indicates the MSB 32 bits of the Destination address AXI DMA writes to transfer data from AXI4-Stream on the S2MM Channel.\nNote: If Data Realignment Engine is included, the Destination Address can be at any byte offset. If Data Realignment Engine is not included, the Dstination Address must be S2MM Memory Map data width aligned.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"S2MM_LENGTH": {
|
||||
"address_offset": "0x58",
|
||||
"size": 32,
|
||||
"display_name": "S2MM DMA Transfer Length Register",
|
||||
"description": "S2MM DMA Transfer Length Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"Length": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 26,
|
||||
"display_name": "Length",
|
||||
"description": "Indicates the length in bytes of the S2MM buffer available to write receive data from the S2MM channel. Writing a non-zero value to this register enables S2MM channel to receive packet data.\nAt the completion of the S2MM transfer, the number of actual bytes written on the S2MM AXI4 interface is updated to the S2MM_LENGTH register.\nNote: This value must be greater than or equal to the largest expected packet to be received on S2MM AXI4-Stream. Values smaller than the received packet result in undefined behavior. \n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+65
@@ -0,0 +1,65 @@
|
||||
# file: system_top_axi_dma_0_0.xdc
|
||||
# (c) Copyright 2009 - 2023 Advanced Micro Devices, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Advanced Micro Devices, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# AMD, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) AMD shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or AMD had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# AMD products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of AMD products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
## INFO: Level CDC Crossing in AXI DMA
|
||||
|
||||
set_false_path -to [get_pins -hier *cdc_to*/D]
|
||||
|
||||
create_waiver -internal -scope -type CDC -id {CDC-1} -user "axi_dma" -tags "9601"\
|
||||
-desc "The CDC-1 warning is waived as it is safe in the context of AXI DMA. The Address and Data value does not change until AXI transaction is complete." \
|
||||
-to [get_pins -hier -quiet -filter {NAME =~*I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_ASYNC_WRITE.REG_WADDR_TO_IPCLK/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[*].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/D}]
|
||||
|
||||
create_waiver -internal -scope -type CDC -id {CDC-1} -user "axi_dma" -tags "9601"\
|
||||
-desc "The CDC-1 warning is waived as it is safe in the context of AXI DMA. The Address and Data value does not change until AXI transaction is complete." \
|
||||
-to [get_pins -hier -quiet -filter {NAME =~*I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_ASYNC_WRITE.REG_WADDR_TO_IPCLK1/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[*].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/D}]
|
||||
|
||||
# Specific to MultiChannel mode
|
||||
create_waiver -internal -scope -type CDC -id {CDC-1} -user "axi_dma" -tags "9601"\
|
||||
-desc "The CDC-1 warning is waived as it is safe in the context of AXI DMA. In multi channel mode, it is safe to ignore this." \
|
||||
-from [get_pins -hier -quiet -filter {NAME =~*MM2S_SPLIT.I_COMMAND_MM2S_SPLITTER/vsize_data_int_reg[*]/C}]
|
||||
|
||||
|
||||
+8497
File diff suppressed because it is too large
Load Diff
+46
@@ -0,0 +1,46 @@
|
||||
# file: system_top_axi_dma_0_0.xdc
|
||||
# (c) Copyright 2009 - 2023 Advanced Micro Devices, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Advanced Micro Devices, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# AMD, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) AMD shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or AMD had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# AMD products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of AMD products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
+431
@@ -0,0 +1,431 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:axi_dma:7.1
|
||||
-- IP Revision: 32
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY axi_dma_v7_1_32;
|
||||
USE axi_dma_v7_1_32.axi_dma;
|
||||
|
||||
ENTITY system_top_axi_dma_1_0 IS
|
||||
PORT (
|
||||
s_axi_lite_aclk : IN STD_LOGIC;
|
||||
m_axi_s2mm_aclk : IN STD_LOGIC;
|
||||
axi_resetn : IN STD_LOGIC;
|
||||
s_axi_lite_awvalid : IN STD_LOGIC;
|
||||
s_axi_lite_awready : OUT STD_LOGIC;
|
||||
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
s_axi_lite_wvalid : IN STD_LOGIC;
|
||||
s_axi_lite_wready : OUT STD_LOGIC;
|
||||
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_lite_bvalid : OUT STD_LOGIC;
|
||||
s_axi_lite_bready : IN STD_LOGIC;
|
||||
s_axi_lite_arvalid : IN STD_LOGIC;
|
||||
s_axi_lite_arready : OUT STD_LOGIC;
|
||||
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
s_axi_lite_rvalid : OUT STD_LOGIC;
|
||||
s_axi_lite_rready : IN STD_LOGIC;
|
||||
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(39 DOWNTO 0);
|
||||
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_s2mm_awvalid : OUT STD_LOGIC;
|
||||
m_axi_s2mm_awready : IN STD_LOGIC;
|
||||
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
|
||||
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_s2mm_wlast : OUT STD_LOGIC;
|
||||
m_axi_s2mm_wvalid : OUT STD_LOGIC;
|
||||
m_axi_s2mm_wready : IN STD_LOGIC;
|
||||
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_s2mm_bvalid : IN STD_LOGIC;
|
||||
m_axi_s2mm_bready : OUT STD_LOGIC;
|
||||
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
|
||||
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
|
||||
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
s_axis_s2mm_tvalid : IN STD_LOGIC;
|
||||
s_axis_s2mm_tready : OUT STD_LOGIC;
|
||||
s_axis_s2mm_tlast : IN STD_LOGIC;
|
||||
s2mm_introut : OUT STD_LOGIC;
|
||||
axi_dma_tstvec : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
END system_top_axi_dma_1_0;
|
||||
|
||||
ARCHITECTURE system_top_axi_dma_1_0_arch OF system_top_axi_dma_1_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_top_axi_dma_1_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axi_dma IS
|
||||
GENERIC (
|
||||
C_S_AXI_LITE_ADDR_WIDTH : INTEGER;
|
||||
C_S_AXI_LITE_DATA_WIDTH : INTEGER;
|
||||
C_DLYTMR_RESOLUTION : INTEGER;
|
||||
C_PRMRY_IS_ACLK_ASYNC : INTEGER;
|
||||
C_ENABLE_MULTI_CHANNEL : INTEGER;
|
||||
C_NUM_MM2S_CHANNELS : INTEGER;
|
||||
C_NUM_S2MM_CHANNELS : INTEGER;
|
||||
C_INCLUDE_SG : INTEGER;
|
||||
C_SG_INCLUDE_STSCNTRL_STRM : INTEGER;
|
||||
C_SG_USE_STSAPP_LENGTH : INTEGER;
|
||||
C_SG_LENGTH_WIDTH : INTEGER;
|
||||
C_M_AXI_SG_ADDR_WIDTH : INTEGER;
|
||||
C_M_AXI_SG_DATA_WIDTH : INTEGER;
|
||||
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : INTEGER;
|
||||
C_S_AXIS_S2MM_STS_TDATA_WIDTH : INTEGER;
|
||||
C_MICRO_DMA : INTEGER;
|
||||
C_INCLUDE_MM2S : INTEGER;
|
||||
C_INCLUDE_MM2S_SF : INTEGER;
|
||||
C_MM2S_BURST_SIZE : INTEGER;
|
||||
C_M_AXI_MM2S_ADDR_WIDTH : INTEGER;
|
||||
C_M_AXI_MM2S_DATA_WIDTH : INTEGER;
|
||||
C_M_AXIS_MM2S_TDATA_WIDTH : INTEGER;
|
||||
C_INCLUDE_MM2S_DRE : INTEGER;
|
||||
C_INCLUDE_S2MM : INTEGER;
|
||||
C_INCLUDE_S2MM_SF : INTEGER;
|
||||
C_S2MM_BURST_SIZE : INTEGER;
|
||||
C_M_AXI_S2MM_ADDR_WIDTH : INTEGER;
|
||||
C_M_AXI_S2MM_DATA_WIDTH : INTEGER;
|
||||
C_S_AXIS_S2MM_TDATA_WIDTH : INTEGER;
|
||||
C_INCLUDE_S2MM_DRE : INTEGER;
|
||||
C_INCREASE_THROUGHPUT : INTEGER;
|
||||
C_FAMILY : STRING
|
||||
);
|
||||
PORT (
|
||||
s_axi_lite_aclk : IN STD_LOGIC;
|
||||
m_axi_sg_aclk : IN STD_LOGIC;
|
||||
m_axi_mm2s_aclk : IN STD_LOGIC;
|
||||
m_axi_s2mm_aclk : IN STD_LOGIC;
|
||||
axi_resetn : IN STD_LOGIC;
|
||||
s_axi_lite_awvalid : IN STD_LOGIC;
|
||||
s_axi_lite_awready : OUT STD_LOGIC;
|
||||
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
s_axi_lite_wvalid : IN STD_LOGIC;
|
||||
s_axi_lite_wready : OUT STD_LOGIC;
|
||||
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_lite_bvalid : OUT STD_LOGIC;
|
||||
s_axi_lite_bready : IN STD_LOGIC;
|
||||
s_axi_lite_arvalid : IN STD_LOGIC;
|
||||
s_axi_lite_arready : OUT STD_LOGIC;
|
||||
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
s_axi_lite_rvalid : OUT STD_LOGIC;
|
||||
s_axi_lite_rready : IN STD_LOGIC;
|
||||
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_sg_awaddr : OUT STD_LOGIC_VECTOR(39 DOWNTO 0);
|
||||
m_axi_sg_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_sg_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_sg_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_sg_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_sg_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_sg_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_sg_awvalid : OUT STD_LOGIC;
|
||||
m_axi_sg_awready : IN STD_LOGIC;
|
||||
m_axi_sg_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_sg_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_sg_wlast : OUT STD_LOGIC;
|
||||
m_axi_sg_wvalid : OUT STD_LOGIC;
|
||||
m_axi_sg_wready : IN STD_LOGIC;
|
||||
m_axi_sg_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_sg_bvalid : IN STD_LOGIC;
|
||||
m_axi_sg_bready : OUT STD_LOGIC;
|
||||
m_axi_sg_araddr : OUT STD_LOGIC_VECTOR(39 DOWNTO 0);
|
||||
m_axi_sg_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_sg_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_sg_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_sg_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_sg_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_sg_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_sg_arvalid : OUT STD_LOGIC;
|
||||
m_axi_sg_arready : IN STD_LOGIC;
|
||||
m_axi_sg_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_sg_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_sg_rlast : IN STD_LOGIC;
|
||||
m_axi_sg_rvalid : IN STD_LOGIC;
|
||||
m_axi_sg_rready : OUT STD_LOGIC;
|
||||
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(39 DOWNTO 0);
|
||||
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_mm2s_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_mm2s_arvalid : OUT STD_LOGIC;
|
||||
m_axi_mm2s_arready : IN STD_LOGIC;
|
||||
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_mm2s_rlast : IN STD_LOGIC;
|
||||
m_axi_mm2s_rvalid : IN STD_LOGIC;
|
||||
m_axi_mm2s_rready : OUT STD_LOGIC;
|
||||
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
|
||||
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axis_mm2s_tvalid : OUT STD_LOGIC;
|
||||
m_axis_mm2s_tready : IN STD_LOGIC;
|
||||
m_axis_mm2s_tlast : OUT STD_LOGIC;
|
||||
m_axis_mm2s_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axis_mm2s_tid : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
|
||||
m_axis_mm2s_tdest : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
|
||||
mm2s_cntrl_reset_out_n : OUT STD_LOGIC;
|
||||
m_axis_mm2s_cntrl_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axis_mm2s_cntrl_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axis_mm2s_cntrl_tvalid : OUT STD_LOGIC;
|
||||
m_axis_mm2s_cntrl_tready : IN STD_LOGIC;
|
||||
m_axis_mm2s_cntrl_tlast : OUT STD_LOGIC;
|
||||
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(39 DOWNTO 0);
|
||||
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_s2mm_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_s2mm_awvalid : OUT STD_LOGIC;
|
||||
m_axi_s2mm_awready : IN STD_LOGIC;
|
||||
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
|
||||
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_s2mm_wlast : OUT STD_LOGIC;
|
||||
m_axi_s2mm_wvalid : OUT STD_LOGIC;
|
||||
m_axi_s2mm_wready : IN STD_LOGIC;
|
||||
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_s2mm_bvalid : IN STD_LOGIC;
|
||||
m_axi_s2mm_bready : OUT STD_LOGIC;
|
||||
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
|
||||
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
|
||||
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
s_axis_s2mm_tvalid : IN STD_LOGIC;
|
||||
s_axis_s2mm_tready : OUT STD_LOGIC;
|
||||
s_axis_s2mm_tlast : IN STD_LOGIC;
|
||||
s_axis_s2mm_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axis_s2mm_tid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
|
||||
s_axis_s2mm_tdest : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
|
||||
s2mm_sts_reset_out_n : OUT STD_LOGIC;
|
||||
s_axis_s2mm_sts_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axis_s2mm_sts_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axis_s2mm_sts_tvalid : IN STD_LOGIC;
|
||||
s_axis_s2mm_sts_tready : OUT STD_LOGIC;
|
||||
s_axis_s2mm_sts_tlast : IN STD_LOGIC;
|
||||
mm2s_introut : OUT STD_LOGIC;
|
||||
s2mm_introut : OUT STD_LOGIC;
|
||||
axi_dma_tstvec : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT axi_dma;
|
||||
ATTRIBUTE X_CORE_INFO : STRING;
|
||||
ATTRIBUTE X_CORE_INFO OF system_top_axi_dma_1_0_arch: ARCHITECTURE IS "axi_dma,Vivado 2024.1";
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE OF system_top_axi_dma_1_0_arch : ARCHITECTURE IS "system_top_axi_dma_1_0,axi_dma,{}";
|
||||
ATTRIBUTE CORE_GENERATION_INFO : STRING;
|
||||
ATTRIBUTE CORE_GENERATION_INFO OF system_top_axi_dma_1_0_arch: ARCHITECTURE IS "system_top_axi_dma_1_0,axi_dma,{x_ipProduct=Vivado 2024.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_dma,x_ipVersion=7.1,x_ipCoreRevision=32,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_S_AXI_LITE_ADDR_WIDTH=10,C_S_AXI_LITE_DATA_WIDTH=32,C_DLYTMR_RESOLUTION=125,C_PRMRY_IS_ACLK_ASYNC=1,C_ENABLE_MULTI_CHANNEL=0,C_NUM_MM2S_CHANNELS=1,C_NUM_S2MM_CHANNELS=1,C_INCLUDE_SG=0,C_SG_INCLUDE_STSCNTRL_STRM=0,C_SG_USE_STSAPP_LENGTH=0,C_SG_LENGTH_WIDTH=26,C_M_AXI_SG_ADDR_WIDTH=40,C_M_AXI_SG_DATA_WIDTH=3" &
|
||||
"2,C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH=32,C_S_AXIS_S2MM_STS_TDATA_WIDTH=32,C_MICRO_DMA=0,C_INCLUDE_MM2S=0,C_INCLUDE_MM2S_SF=1,C_MM2S_BURST_SIZE=16,C_M_AXI_MM2S_ADDR_WIDTH=40,C_M_AXI_MM2S_DATA_WIDTH=32,C_M_AXIS_MM2S_TDATA_WIDTH=32,C_INCLUDE_MM2S_DRE=0,C_INCLUDE_S2MM=1,C_INCLUDE_S2MM_SF=1,C_S2MM_BURST_SIZE=16,C_M_AXI_S2MM_ADDR_WIDTH=40,C_M_AXI_S2MM_DATA_WIDTH=64,C_S_AXIS_S2MM_TDATA_WIDTH=64,C_INCLUDE_S2MM_DRE=0,C_INCREASE_THROUGHPUT=0,C_FAMILY=zynq}";
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF axi_resetn: SIGNAL IS "XIL_INTERFACENAME AXI_RESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF axi_resetn: SIGNAL IS "xilinx.com:signal:reset:1.0 AXI_RESETN RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axi_s2mm_aclk: SIGNAL IS "XIL_INTERFACENAME M_AXI_S2MM_CLK, ASSOCIATED_BUSIF M_AXI_S2MM:S_AXIS_S2MM:S_AXIS_STS, ASSOCIATED_RESET s2mm_prmry_reset_out_n:s2mm_sts_reset_out_n, FREQ_HZ 200000000, FREQ_TOLERANCE_HZ 0, PHASE 0, CLK_DOMAIN system_top_mig_7series_0_0_ui_clk, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_S2MM_CLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axi_s2mm_awaddr: SIGNAL IS "XIL_INTERFACENAME M_AXI_S2MM, SUPPORTS_NARROW_BURST 0, NUM_WRITE_OUTSTANDING 16, DATA_WIDTH 64, PROTOCOL AXI4, FREQ_HZ 200000000, ID_WIDTH 0, ADDR_WIDTH 40, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, NUM_READ_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0, CLK_DOMAIN system_top_mig_7series_0_0_ui_clk, NUM_READ_THREADS 1, NUM_" &
|
||||
"WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWBURST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWCACHE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWLEN";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWPROT";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWSIZE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WSTRB";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s2mm_introut: SIGNAL IS "XIL_INTERFACENAME S2MM_INTROUT, SENSITIVITY LEVEL_HIGH, PortWidth 1";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s2mm_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 S2MM_INTROUT INTERRUPT";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s2mm_prmry_reset_out_n: SIGNAL IS "XIL_INTERFACENAME S2MM_PRMRY_RESET_OUT_N, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s2mm_prmry_reset_out_n: SIGNAL IS "xilinx.com:signal:reset:1.0 S2MM_PRMRY_RESET_OUT_N RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_lite_aclk: SIGNAL IS "XIL_INTERFACENAME S_AXI_LITE_ACLK, ASSOCIATED_BUSIF S_AXI_LITE:M_AXI, ASSOCIATED_RESET axi_resetn, FREQ_HZ 1e+08, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN system_top_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_LITE_ACLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_lite_awvalid: SIGNAL IS "XIL_INTERFACENAME S_AXI_LITE, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 10, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 0, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN system_top_processing_system7_0_0_FCLK_CLK0, NUM_READ_THR" &
|
||||
"EADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_s2mm_tdata: SIGNAL IS "XIL_INTERFACENAME S_AXIS_S2MM, TDATA_NUM_BYTES 8, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 1, HAS_TLAST 1, FREQ_HZ 200000000, PHASE 0, CLK_DOMAIN system_top_mig_7series_0_0_ui_clk, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TKEEP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TVALID";
|
||||
BEGIN
|
||||
U0 : axi_dma
|
||||
GENERIC MAP (
|
||||
C_S_AXI_LITE_ADDR_WIDTH => 10,
|
||||
C_S_AXI_LITE_DATA_WIDTH => 32,
|
||||
C_DLYTMR_RESOLUTION => 125,
|
||||
C_PRMRY_IS_ACLK_ASYNC => 1,
|
||||
C_ENABLE_MULTI_CHANNEL => 0,
|
||||
C_NUM_MM2S_CHANNELS => 1,
|
||||
C_NUM_S2MM_CHANNELS => 1,
|
||||
C_INCLUDE_SG => 0,
|
||||
C_SG_INCLUDE_STSCNTRL_STRM => 0,
|
||||
C_SG_USE_STSAPP_LENGTH => 0,
|
||||
C_SG_LENGTH_WIDTH => 26,
|
||||
C_M_AXI_SG_ADDR_WIDTH => 40,
|
||||
C_M_AXI_SG_DATA_WIDTH => 32,
|
||||
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => 32,
|
||||
C_S_AXIS_S2MM_STS_TDATA_WIDTH => 32,
|
||||
C_MICRO_DMA => 0,
|
||||
C_INCLUDE_MM2S => 0,
|
||||
C_INCLUDE_MM2S_SF => 1,
|
||||
C_MM2S_BURST_SIZE => 16,
|
||||
C_M_AXI_MM2S_ADDR_WIDTH => 40,
|
||||
C_M_AXI_MM2S_DATA_WIDTH => 32,
|
||||
C_M_AXIS_MM2S_TDATA_WIDTH => 32,
|
||||
C_INCLUDE_MM2S_DRE => 0,
|
||||
C_INCLUDE_S2MM => 1,
|
||||
C_INCLUDE_S2MM_SF => 1,
|
||||
C_S2MM_BURST_SIZE => 16,
|
||||
C_M_AXI_S2MM_ADDR_WIDTH => 40,
|
||||
C_M_AXI_S2MM_DATA_WIDTH => 64,
|
||||
C_S_AXIS_S2MM_TDATA_WIDTH => 64,
|
||||
C_INCLUDE_S2MM_DRE => 0,
|
||||
C_INCREASE_THROUGHPUT => 0,
|
||||
C_FAMILY => "zynq"
|
||||
)
|
||||
PORT MAP (
|
||||
s_axi_lite_aclk => s_axi_lite_aclk,
|
||||
m_axi_sg_aclk => '0',
|
||||
m_axi_mm2s_aclk => '0',
|
||||
m_axi_s2mm_aclk => m_axi_s2mm_aclk,
|
||||
axi_resetn => axi_resetn,
|
||||
s_axi_lite_awvalid => s_axi_lite_awvalid,
|
||||
s_axi_lite_awready => s_axi_lite_awready,
|
||||
s_axi_lite_awaddr => s_axi_lite_awaddr,
|
||||
s_axi_lite_wvalid => s_axi_lite_wvalid,
|
||||
s_axi_lite_wready => s_axi_lite_wready,
|
||||
s_axi_lite_wdata => s_axi_lite_wdata,
|
||||
s_axi_lite_bresp => s_axi_lite_bresp,
|
||||
s_axi_lite_bvalid => s_axi_lite_bvalid,
|
||||
s_axi_lite_bready => s_axi_lite_bready,
|
||||
s_axi_lite_arvalid => s_axi_lite_arvalid,
|
||||
s_axi_lite_arready => s_axi_lite_arready,
|
||||
s_axi_lite_araddr => s_axi_lite_araddr,
|
||||
s_axi_lite_rvalid => s_axi_lite_rvalid,
|
||||
s_axi_lite_rready => s_axi_lite_rready,
|
||||
s_axi_lite_rdata => s_axi_lite_rdata,
|
||||
s_axi_lite_rresp => s_axi_lite_rresp,
|
||||
m_axi_sg_awready => '0',
|
||||
m_axi_sg_wready => '0',
|
||||
m_axi_sg_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
|
||||
m_axi_sg_bvalid => '0',
|
||||
m_axi_sg_arready => '0',
|
||||
m_axi_sg_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
m_axi_sg_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
|
||||
m_axi_sg_rlast => '0',
|
||||
m_axi_sg_rvalid => '0',
|
||||
m_axi_mm2s_arready => '0',
|
||||
m_axi_mm2s_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
m_axi_mm2s_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
|
||||
m_axi_mm2s_rlast => '0',
|
||||
m_axi_mm2s_rvalid => '0',
|
||||
m_axis_mm2s_tready => '0',
|
||||
m_axis_mm2s_cntrl_tready => '0',
|
||||
m_axi_s2mm_awaddr => m_axi_s2mm_awaddr,
|
||||
m_axi_s2mm_awlen => m_axi_s2mm_awlen,
|
||||
m_axi_s2mm_awsize => m_axi_s2mm_awsize,
|
||||
m_axi_s2mm_awburst => m_axi_s2mm_awburst,
|
||||
m_axi_s2mm_awprot => m_axi_s2mm_awprot,
|
||||
m_axi_s2mm_awcache => m_axi_s2mm_awcache,
|
||||
m_axi_s2mm_awvalid => m_axi_s2mm_awvalid,
|
||||
m_axi_s2mm_awready => m_axi_s2mm_awready,
|
||||
m_axi_s2mm_wdata => m_axi_s2mm_wdata,
|
||||
m_axi_s2mm_wstrb => m_axi_s2mm_wstrb,
|
||||
m_axi_s2mm_wlast => m_axi_s2mm_wlast,
|
||||
m_axi_s2mm_wvalid => m_axi_s2mm_wvalid,
|
||||
m_axi_s2mm_wready => m_axi_s2mm_wready,
|
||||
m_axi_s2mm_bresp => m_axi_s2mm_bresp,
|
||||
m_axi_s2mm_bvalid => m_axi_s2mm_bvalid,
|
||||
m_axi_s2mm_bready => m_axi_s2mm_bready,
|
||||
s2mm_prmry_reset_out_n => s2mm_prmry_reset_out_n,
|
||||
s_axis_s2mm_tdata => s_axis_s2mm_tdata,
|
||||
s_axis_s2mm_tkeep => s_axis_s2mm_tkeep,
|
||||
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid,
|
||||
s_axis_s2mm_tready => s_axis_s2mm_tready,
|
||||
s_axis_s2mm_tlast => s_axis_s2mm_tlast,
|
||||
s_axis_s2mm_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
s_axis_s2mm_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
|
||||
s_axis_s2mm_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
|
||||
s_axis_s2mm_sts_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
s_axis_s2mm_sts_tkeep => X"F",
|
||||
s_axis_s2mm_sts_tvalid => '0',
|
||||
s_axis_s2mm_sts_tlast => '0',
|
||||
s2mm_introut => s2mm_introut,
|
||||
axi_dma_tstvec => axi_dma_tstvec
|
||||
);
|
||||
END system_top_axi_dma_1_0_arch;
|
||||
+976
@@ -0,0 +1,976 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "system_top_axi_dma_1_0",
|
||||
"cell_name": "axi_dma_1",
|
||||
"component_reference": "xilinx.com:ip:axi_dma:7.1",
|
||||
"ip_revision": "32",
|
||||
"gen_directory": ".",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "system_top_axi_dma_1_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"c_include_sg": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_enable_multi_channel": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"c_num_mm2s_channels": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"c_num_s2mm_channels": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"c_sg_length_width": [ { "value": "26", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_dlytmr_resolution": [ { "value": "125", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_prmry_is_aclk_async": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_sg_include_stscntrl_strm": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"c_micro_dma": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_include_mm2s": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_m_axi_mm2s_data_width": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"c_m_axis_mm2s_tdata_width": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"c_include_mm2s_dre": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"c_include_mm2s_sf": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_mm2s_burst_size": [ { "value": "16", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"c_include_s2mm": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_sg_use_stsapp_length": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"c_m_axi_s2mm_data_width": [ { "value": "64", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_s_axis_s2mm_tdata_width": [ { "value": "64", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_include_s2mm_dre": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_include_s2mm_sf": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_s2mm_burst_size": [ { "value": "16", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_addr_width": [ { "value": "40", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_single_interface": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"c_increase_throughput": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_S_AXI_LITE_ADDR_WIDTH": [ { "value": "10", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_LITE_DATA_WIDTH": [ { "value": "32", "format": "long", "usage": "all" } ],
|
||||
"C_DLYTMR_RESOLUTION": [ { "value": "125", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PRMRY_IS_ACLK_ASYNC": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ENABLE_MULTI_CHANNEL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_MM2S_CHANNELS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_S2MM_CHANNELS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INCLUDE_SG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SG_INCLUDE_STSCNTRL_STRM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SG_USE_STSAPP_LENGTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SG_LENGTH_WIDTH": [ { "value": "26", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_AXI_SG_ADDR_WIDTH": [ { "value": "40", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_AXI_SG_DATA_WIDTH": [ { "value": "32", "format": "long", "usage": "all" } ],
|
||||
"C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_S_AXIS_S2MM_STS_TDATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_MICRO_DMA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INCLUDE_MM2S": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INCLUDE_MM2S_SF": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_MM2S_BURST_SIZE": [ { "value": "16", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_M_AXI_MM2S_ADDR_WIDTH": [ { "value": "40", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_M_AXI_MM2S_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_M_AXIS_MM2S_TDATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_INCLUDE_MM2S_DRE": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_INCLUDE_S2MM": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INCLUDE_S2MM_SF": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S2MM_BURST_SIZE": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_AXI_S2MM_ADDR_WIDTH": [ { "value": "40", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_AXI_S2MM_DATA_WIDTH": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXIS_S2MM_TDATA_WIDTH": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INCLUDE_S2MM_DRE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INCREASE_THROUGHPUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_FAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "xilinx.com:zc706:part0:1.4" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z045" } ],
|
||||
"NEXTGEN_VERSAL": [ { "value": "0" } ],
|
||||
"PACKAGE": [ { "value": "ffg900" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "32" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "." } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2024.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"s_axi_lite_aclk": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"m_axi_s2mm_aclk": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"axi_resetn": [ { "direction": "in", "driver_value": "1" } ],
|
||||
"s_axi_lite_awvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_lite_awready": [ { "direction": "out" } ],
|
||||
"s_axi_lite_awaddr": [ { "direction": "in", "size_left": "9", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_lite_wvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_lite_wready": [ { "direction": "out" } ],
|
||||
"s_axi_lite_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_lite_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s_axi_lite_bvalid": [ { "direction": "out" } ],
|
||||
"s_axi_lite_bready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_lite_arvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_lite_arready": [ { "direction": "out" } ],
|
||||
"s_axi_lite_araddr": [ { "direction": "in", "size_left": "9", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_lite_rvalid": [ { "direction": "out" } ],
|
||||
"s_axi_lite_rready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_lite_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"s_axi_lite_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"m_axi_s2mm_awaddr": [ { "direction": "out", "size_left": "39", "size_right": "0" } ],
|
||||
"m_axi_s2mm_awlen": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
|
||||
"m_axi_s2mm_awsize": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||
"m_axi_s2mm_awburst": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"m_axi_s2mm_awprot": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||
"m_axi_s2mm_awcache": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||
"m_axi_s2mm_awvalid": [ { "direction": "out" } ],
|
||||
"m_axi_s2mm_awready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"m_axi_s2mm_wdata": [ { "direction": "out", "size_left": "63", "size_right": "0" } ],
|
||||
"m_axi_s2mm_wstrb": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
|
||||
"m_axi_s2mm_wlast": [ { "direction": "out" } ],
|
||||
"m_axi_s2mm_wvalid": [ { "direction": "out" } ],
|
||||
"m_axi_s2mm_wready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"m_axi_s2mm_bresp": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"m_axi_s2mm_bvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"m_axi_s2mm_bready": [ { "direction": "out" } ],
|
||||
"s2mm_prmry_reset_out_n": [ { "direction": "out" } ],
|
||||
"s_axis_s2mm_tdata": [ { "direction": "in", "size_left": "63", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axis_s2mm_tkeep": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0xFF" } ],
|
||||
"s_axis_s2mm_tvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axis_s2mm_tready": [ { "direction": "out" } ],
|
||||
"s_axis_s2mm_tlast": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s2mm_introut": [ { "direction": "out" } ],
|
||||
"axi_dma_tstvec": [ { "direction": "out", "size_left": "31", "size_right": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"S_AXI_LITE": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"memory_map_ref": "S_AXI_LITE",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "1e+08", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "10", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"ARADDR": [ { "physical_name": "s_axi_lite_araddr" } ],
|
||||
"ARREADY": [ { "physical_name": "s_axi_lite_arready" } ],
|
||||
"ARVALID": [ { "physical_name": "s_axi_lite_arvalid" } ],
|
||||
"AWADDR": [ { "physical_name": "s_axi_lite_awaddr" } ],
|
||||
"AWREADY": [ { "physical_name": "s_axi_lite_awready" } ],
|
||||
"AWVALID": [ { "physical_name": "s_axi_lite_awvalid" } ],
|
||||
"BREADY": [ { "physical_name": "s_axi_lite_bready" } ],
|
||||
"BRESP": [ { "physical_name": "s_axi_lite_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "s_axi_lite_bvalid" } ],
|
||||
"RDATA": [ { "physical_name": "s_axi_lite_rdata" } ],
|
||||
"RREADY": [ { "physical_name": "s_axi_lite_rready" } ],
|
||||
"RRESP": [ { "physical_name": "s_axi_lite_rresp" } ],
|
||||
"RVALID": [ { "physical_name": "s_axi_lite_rvalid" } ],
|
||||
"WDATA": [ { "physical_name": "s_axi_lite_wdata" } ],
|
||||
"WREADY": [ { "physical_name": "s_axi_lite_wready" } ],
|
||||
"WVALID": [ { "physical_name": "s_axi_lite_wvalid" } ]
|
||||
}
|
||||
},
|
||||
"M_AXI_S2MM": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "master",
|
||||
"address_space_ref": "Data_S2MM",
|
||||
"parameters": {
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
|
||||
"DATA_WIDTH": [ { "value": "64", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "200000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "40", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "WRITE_ONLY", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "16", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_mig_7series_0_0_ui_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"AWADDR": [ { "physical_name": "m_axi_s2mm_awaddr" } ],
|
||||
"AWBURST": [ { "physical_name": "m_axi_s2mm_awburst" } ],
|
||||
"AWCACHE": [ { "physical_name": "m_axi_s2mm_awcache" } ],
|
||||
"AWLEN": [ { "physical_name": "m_axi_s2mm_awlen" } ],
|
||||
"AWPROT": [ { "physical_name": "m_axi_s2mm_awprot" } ],
|
||||
"AWREADY": [ { "physical_name": "m_axi_s2mm_awready" } ],
|
||||
"AWSIZE": [ { "physical_name": "m_axi_s2mm_awsize" } ],
|
||||
"AWVALID": [ { "physical_name": "m_axi_s2mm_awvalid" } ],
|
||||
"BREADY": [ { "physical_name": "m_axi_s2mm_bready" } ],
|
||||
"BRESP": [ { "physical_name": "m_axi_s2mm_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "m_axi_s2mm_bvalid" } ],
|
||||
"WDATA": [ { "physical_name": "m_axi_s2mm_wdata" } ],
|
||||
"WLAST": [ { "physical_name": "m_axi_s2mm_wlast" } ],
|
||||
"WREADY": [ { "physical_name": "m_axi_s2mm_wready" } ],
|
||||
"WSTRB": [ { "physical_name": "m_axi_s2mm_wstrb" } ],
|
||||
"WVALID": [ { "physical_name": "m_axi_s2mm_wvalid" } ]
|
||||
}
|
||||
},
|
||||
"S_AXIS_S2MM": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "8", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "200000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_mig_7series_0_0_ui_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "s_axis_s2mm_tdata" } ],
|
||||
"TKEEP": [ { "physical_name": "s_axis_s2mm_tkeep" } ],
|
||||
"TLAST": [ { "physical_name": "s_axis_s2mm_tlast" } ],
|
||||
"TREADY": [ { "physical_name": "s_axis_s2mm_tready" } ],
|
||||
"TVALID": [ { "physical_name": "s_axis_s2mm_tvalid" } ]
|
||||
}
|
||||
},
|
||||
"AXI_RESETN": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "axi_resetn" } ]
|
||||
}
|
||||
},
|
||||
"MM2S_INTROUT": {
|
||||
"vlnv": "xilinx.com:signal:interrupt:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"SENSITIVITY": [ { "value": "LEVEL_HIGH", "value_src": "constant", "usage": "all" } ],
|
||||
"PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"S2MM_INTROUT": {
|
||||
"vlnv": "xilinx.com:signal:interrupt:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"SENSITIVITY": [ { "value": "LEVEL_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"PortWidth": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"INTERRUPT": [ { "physical_name": "s2mm_introut" } ]
|
||||
}
|
||||
},
|
||||
"M_AXI_SG_CLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "M_AXI_SG", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"M_AXI_MM2S_CLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "M_AXI_MM2S:M_AXIS_MM2S:M_AXIS_CNTRL", "value_src": "constant", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "mm2s_prmry_reset_out_n:mm2s_cntrl_reset_out_n", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"M_AXI_S2MM_CLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "M_AXI_S2MM:S_AXIS_S2MM:S_AXIS_STS", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "s2mm_prmry_reset_out_n:s2mm_sts_reset_out_n", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "200000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_mig_7series_0_0_ui_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "m_axi_s2mm_aclk" } ]
|
||||
}
|
||||
},
|
||||
"S_AXI_LITE_ACLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S_AXI_LITE:M_AXI", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "axi_resetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "1e+08", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "s_axi_lite_aclk" } ]
|
||||
}
|
||||
},
|
||||
"MM2S_PRMRY_RESET_OUT_N": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"S2MM_PRMRY_RESET_OUT_N": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "s2mm_prmry_reset_out_n" } ]
|
||||
}
|
||||
},
|
||||
"MM2S_CNTRL_RESET_OUT_N": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"S2MM_STS_RESET_OUT_N": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
}
|
||||
},
|
||||
"address_spaces": {
|
||||
"Data_S2MM": {
|
||||
"range": "1099511627776",
|
||||
"width": "40"
|
||||
}
|
||||
},
|
||||
"memory_maps": {
|
||||
"S_AXI_LITE": {
|
||||
"display_name": "S_AXI_MEM",
|
||||
"description": "Memory Map for S_AXI_LITE",
|
||||
"address_blocks": {
|
||||
"Reg": {
|
||||
"base_address": "0",
|
||||
"range": "4096",
|
||||
"display_name": "Reg",
|
||||
"description": "Register Block",
|
||||
"usage": "register",
|
||||
"access": "read-write",
|
||||
"registers": {
|
||||
"MM2S_DMACR": {
|
||||
"address_offset": "0x0",
|
||||
"size": 32,
|
||||
"display_name": "MM2S DMA Control Register",
|
||||
"description": "MM2S DMA Control Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x10002",
|
||||
"fields": {
|
||||
"RS": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 1,
|
||||
"display_name": "Run/Stop Control",
|
||||
"description": "Run / Stop control for controlling running and stopping of the DMA channel.\n 0 - Stop, DMA stops when current (if any) DMA operations are complete. For Scatter / Gather Mode pending commands/transfers are flushed or completed. \n AXI4-Stream outs are potentially terminated early. Descriptors in the update queue are allowed to finish updating to remote memory before engine halt.\n For Direct Register mode pending commands/transfers are flushed or completed. AXI4-Stream outs are potentially terminated.\n The halted bit in the DMA Status register asserts to 1 when the DMA engine is halted. This bit is cleared by AXI DMA hardware when an error occurs. The CPU can also choose to clear this bit to stop DMA operations.\n 1 - Run, Start DMA operations. The halted bit in the DMA Status register deasserts to 0 when the DMA engine begins operations.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Reset": {
|
||||
"bit_offset": 2,
|
||||
"bit_width": 1,
|
||||
"display_name": "Soft Reset",
|
||||
"description": "Soft reset for resetting the AXI DMA core. Setting this bit to a 1 causes the AXI DMA to be reset. Reset is accomplished gracefully. Pending commands/transfers are flushed or completed.\nAXI4-Stream outs are potentially terminated early. Setting either MM2S_DMACR. Reset = 1 or S2MM_DMACR.Reset = 1 resets the entire AXI DMA engine. After completion of a soft reset, all registers and bits are in the Reset State. 0 - Normal operation. 1 - Reset in progress.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Keyhole": {
|
||||
"bit_offset": 3,
|
||||
"bit_width": 1,
|
||||
"display_name": "Keyhole Read",
|
||||
"description": "Keyhole Read. Setting this bit to 1 causes AXI DMA to initiate MM2S reads (AXI4read) in non-incrementing address mode (Fixed Address Burst transfer on AXI4). This bit can be updated when AXI DMA is in idle. When using keyhole operation the Max Burst Length should not exceed 16. This bit should not be set when DRE is enabled.\nThis bit is non functional when the multichannel feature is enabled or in Direct Register mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Cyclic_BD_Enable": {
|
||||
"bit_offset": 4,
|
||||
"bit_width": 1,
|
||||
"display_name": "Cyclic BD Enable",
|
||||
"description": "When set to 1, the DMA operates in Cyclic Buffer Descriptor (BD) mode without any user intervention. In this mode, the Scatter Gather module ignores the Completed bit of the BD. With this bit set, you can use the same BDs in cyclic manner without worrying about any stale descriptor errors.\nThis bit should be set/unset only when the DMA is idle or when not running. Updating this bit while the DMA is running can result in unexpected behavior.\nThis bit is non functional when DMA operates in multichannel mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"IOC_IrqEn": {
|
||||
"bit_offset": 12,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Complete (IOC) Interrupt Enable",
|
||||
"description": "Interrupt on Complete (IOC) Interrupt Enable. When set to 1, allows DMASR.IOC_Irq to generate an interrupt out for descriptors with the IOC bit set. 0 - IOC Interrupt disabled 1 - IOC Interrupt enabled\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Dly_IrqEn": {
|
||||
"bit_offset": 13,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Delay Timer Interrupt Enable",
|
||||
"description": "Interrupt on Delay Timer Interrupt Enable. When set to 1, allows DMASR.Dly_Irq to generate an interrupt out. 0 - Delay Interrupt disabled 1 - Delay Interrupt enabled Note: This field is ignored when AXI DMA is configured for Direct Register Mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Err_IrqEn": {
|
||||
"bit_offset": 14,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Error Interrupt Enable",
|
||||
"description": "Interrupt on Error Interrupt Enable.\n 0 - Error Interrupt disabled\n 1 - Error Interrupt enabled\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"IRQThreshold": {
|
||||
"bit_offset": 16,
|
||||
"bit_width": 8,
|
||||
"display_name": "Interrupt Threshold",
|
||||
"description": "Interrupt Threshold. This value is used for setting the interrupt threshold. When IOC interrupt events occur, an internal counter counts down from the Interrupt Threshold setting. When the count reaches zero, an interrupt out is generated by the DMA engine. Note: The minimum setting for the threshold is 0x01. A write of 0x00 to this register has no effect. Note: This field is ignored when AXI DMA is configured for Direct Register Mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"IRQDelay": {
|
||||
"bit_offset": 24,
|
||||
"bit_width": 8,
|
||||
"display_name": "Interrupt Delay Time Out",
|
||||
"description": "Interrupt Delay Time Out. This value is used for setting the interrupt timeout value. The interrupt timeout mechanism causes the DMA engine to generate an interrupt after the delay time period has expired. Timer begins counting at the end of a packet and resets with receipt of a new packet or a timeout event occurs.\nNote: Setting this value to zero disables the delay timer interrupt.\nNote: This field is ignored when AXI DMA is configured for Direct Register Mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"MM2S_DMASR": {
|
||||
"address_offset": "0x04",
|
||||
"size": 32,
|
||||
"display_name": "MM2S DMA Status Register",
|
||||
"description": "MM2S DMA Status Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x10000",
|
||||
"fields": {
|
||||
"Halted": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Channel Halted",
|
||||
"description": "DMA Channel Halted. Indicates the run/stop state of the DMA channel. 0 - DMA channel running. 1 - DMA channel halted. For Scatter / Gather Mode this bit gets set when DMACR.RS = 0 and DMA and SG operations have halted. For Direct Register mode (C_INCLUDE_SG = 0) this bit gets set when DMACR.RS = 0 and DMA operations have halted. There can be a lag of time between when DMACR.RS = 0 and when DMASR.Halted = 1 Note: When halted (RS= 0 and Halted = 1), writing to CURDESC_PTR or TAILDESC_PTR pointer registers has no effect on DMA operations when in Scatter Gather Mode. For Direct Register Mode, writing to the LENGTH register has no effect on DMA operations.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"Idle": {
|
||||
"bit_offset": 1,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Channel Idle",
|
||||
"description": "DMA Channel Idle. Indicates the state of AXI DMA operations.\nFor Scatter / Gather Mode when IDLE indicates the SG Engine has reached the tail pointer for the associated channel and all queued descriptors have been processed. Writing to the tail pointer register automatically restarts DMA operations.\nFor Direct Register Mode when IDLE indicates the current transfer has completed. 0 - Not Idle. For Scatter / Gather Mode, SG has not reached tail descriptor pointer and/or DMA operations in progress. For Direct Register Mode, transfer is not complete. 1 - Idle. For Scatter / Gather Mode, SG has reached tail descriptor pointer and DMA operation paused. for Direct Register Mode, DMA transfer has completed and controller is paused. Note: This bit is 0 when channel is halted (DMASR.Halted=1). This bit is also 0 prior to initial transfer when AXI DMA configured for Direct Register Mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"SGIncld": {
|
||||
"bit_offset": 3,
|
||||
"bit_width": 1,
|
||||
"display_name": "SGIncld",
|
||||
"description": "1 - Scatter Gather Enabled\n0 - Scatter Gather not enabled\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"DMAIntErr": {
|
||||
"bit_offset": 4,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Internal Error",
|
||||
"description": "DMA Internal Error. Internal error occurs if the buffer length specified in the fetched descriptor is set to 0. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Internal Errors 1 - DMA Internal Error detected. DMA Engine halts\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"DMASlvErr": {
|
||||
"bit_offset": 5,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Slave Error",
|
||||
"description": "DMA Slave Error. This error occurs if the slave read from the Memory Map interface issues a Slave Error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Slave Errors. 1 - DMA Slave Error detected. DMA Engine halts\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"DMADecErr": {
|
||||
"bit_offset": 6,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Decode Error",
|
||||
"description": "DMA Decode Error. This error occurs if the address request points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Decode Errors. 1 - DMA Decode Error detected. DMA Engine halts.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"SGIntErr": {
|
||||
"bit_offset": 8,
|
||||
"bit_width": 1,
|
||||
"display_name": "Scatter Gather Internal Error",
|
||||
"description": "Scatter Gather Internal Error. This error occurs if a descriptor with the \"Complete bit\" already set is fetched. Refer to the Scatter Gather Descriptor section for more information.This indicates to the SG Engine that the descriptor is a stale descriptor. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Internal Errors. 1 - SG Internal Error detected. DMA Engine halts. Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"SGSlvErr": {
|
||||
"bit_offset": 9,
|
||||
"bit_width": 1,
|
||||
"display_name": "Scatter Gather Slave Error",
|
||||
"description": "Scatter Gather Slave Error. This error occurs if the slave read from on the Memory Map interface issues a Slave error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Slave Errors. 1 - SG Slave Error detected. DMA Engine halts. Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode. \n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"SGDecErr": {
|
||||
"bit_offset": 10,
|
||||
"bit_width": 1,
|
||||
"display_name": "Scatter Gather Decode Error",
|
||||
"description": "Scatter Gather Decode Error. This error occurs if CURDESC_PTR and/or NXTDESC_PTR points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Decode Errors. 1 - SG Decode Error detected. DMA Engine halts. Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode. \n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"IOC_Irq": {
|
||||
"bit_offset": 12,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Complete",
|
||||
"description": "Interrupt on Complete. When set to 1 for Scatter/Gather Mode, indicates an interrupt event was generated on completion of a descriptor. This occurs for descriptors with the End of Frame (EOF) bit set. When set to 1 for Direct Register Mode, indicates an interrupt event was generated on completion of a transfer. If the corresponding bit is enabled in the MM2S_DMACR (IOC_IrqEn = 1) and if the interrupt threshold has been met, causes an interrupt out to be generated from the AXI DMA. 0 - No IOC Interrupt. 1 - IOC Interrupt detected. Writing a 1 to this bit will clear it.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Dly_Irq": {
|
||||
"bit_offset": 13,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Delay",
|
||||
"description": "Interrupt on Delay. When set to 1, indicates an interrupt event was generated on delay timer time out. If the corresponding bit is enabled in the MM2S_DMACR (Dly_IrqEn = 1), an interrupt out is generated from the AXI DMA. 0 - No Delay Interrupt. 1 - Delay Interrupt detected. Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode. \n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Err_Irq": {
|
||||
"bit_offset": 14,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Error",
|
||||
"description": "Interrupt on Error. When set to 1, indicates an interrupt event was generated on error. If the corresponding bit is enabled in the MM2S_DMACR (Err_IrqEn = 1), an interrupt out is generated from the AXI DMA.\nWriting a 1 to this bit will clear it. \n0 - No error Interrupt. \n1 - Error interrupt detected.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"IRQThresholdSts": {
|
||||
"bit_offset": 16,
|
||||
"bit_width": 8,
|
||||
"display_name": "Interrupt Threshold Status",
|
||||
"description": "Interrupt Threshold Status. Indicates current interrupt threshold value.\nNote: Applicable only when Scatter Gather is enabled.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"IRQDelaySts": {
|
||||
"bit_offset": 24,
|
||||
"bit_width": 8,
|
||||
"display_name": "Interrupt Delay Time Status",
|
||||
"description": "Interrupt Delay Time Status. Indicates current interrupt delay time value.\nNote: Applicable only when Scatter Gather is enabled.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
}
|
||||
}
|
||||
},
|
||||
"MM2S_SA": {
|
||||
"address_offset": "0x18",
|
||||
"size": 32,
|
||||
"display_name": "MM2S Source Address Register",
|
||||
"description": "MM2S Source Address Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"Source_Address": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 32,
|
||||
"display_name": "Source Address",
|
||||
"description": "Indicates the source address AXI DMA reads from to transfer data to AXI4-Stream on the MM2S Channel.\nNote: If Data Realignment Engine is included, the Source Address can be at any byte offset. If Data Realignment Engine is not included, the Source Address must be MM2S Memory Map data width aligned.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"MM2S_SA_MSB": {
|
||||
"address_offset": "0x1C",
|
||||
"size": 32,
|
||||
"display_name": "MM2S Source Address Register",
|
||||
"description": "MM2S Source Address Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"Source_Address": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 32,
|
||||
"display_name": "Source Address",
|
||||
"description": "Indicates the MSB 32 bits of the source address AXI DMA reads from to transfer data to AXI4-Stream on the MM2S Channel.\nNote: If Data Realignment Engine is included, the Source Address can be at any byte offset. If Data Realignment Engine is not included, the Source Address must be MM2S Memory Map data width aligned.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"MM2S_LENGTH": {
|
||||
"address_offset": "0x28",
|
||||
"size": 32,
|
||||
"display_name": "MM2S DMA Transfer Length Register",
|
||||
"description": "MM2S DMA Transfer Length Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"Length": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 26,
|
||||
"display_name": "Length",
|
||||
"description": "Indicates the number of bytes to transfer for the MM2S channel. Writing a non-zero value to this register starts the MM2S transfer.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"S2MM_DMACR": {
|
||||
"address_offset": "0x30",
|
||||
"size": 32,
|
||||
"display_name": "S2MM DMA Control Register",
|
||||
"description": "S2MM DMA Control Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x10002",
|
||||
"fields": {
|
||||
"RS": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 1,
|
||||
"display_name": "Run/Stop Control",
|
||||
"description": "Run / Stop control for controlling running and stopping of the DMA channel.\n 0 - Stop, DMA stops when current (if any) DMA operations are complete. For Scatter / Gather Mode pending commands/transfers are flushed or completed. \n AXI4-Stream outs are potentially terminated early. Descriptors in the update queue are allowed to finish updating to remote memory before engine halt.\n For Direct Register mode pending commands/transfers are flushed or completed. AXI4-Stream outs are potentially terminated. Data integrity on S2MM AXI4 cannot be guaranteed.\n The halted bit in the DMA Status register asserts to 1 when the DMA engine is halted. This bit is cleared by AXI DMA hardware when an error occurs. The CPU can also choose to clear this bit to stop DMA operations.\n 1 - Run, Start DMA operations. The halted bit in the DMA Status register deasserts to 0 when the DMA engine begins operations.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Reset": {
|
||||
"bit_offset": 2,
|
||||
"bit_width": 1,
|
||||
"display_name": "Soft Reset",
|
||||
"description": "Soft reset for resetting the AXI DMA core. Setting this bit to a 1 causes the AXI DMA to be reset. Reset is accomplished gracefully. Pending commands/transfers are flushed or completed.\nAXI4-Stream outs are terminated early, if necessary with associated TLAST. Setting either MM2S_DMACR.Reset = 1 or S2MM_DMACR.Reset = 1 resets the entire AXI DMA engine. After completion of a soft reset, all registers and bits are in the Reset State. 0 - Reset not in progress. Normal operation. 1 - Reset in progress\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Keyhole": {
|
||||
"bit_offset": 3,
|
||||
"bit_width": 1,
|
||||
"display_name": "Keyhole Write",
|
||||
"description": "Keyhole Write. Setting this bit to 1 causes AXI DMA to initiate S2MM writes (AXI4 Writes) in non-incrementing address mode (Fixed Address Burst transfer on AXI4). This bit can be modified when AXI DMA is in idle. When enabling Key hole operation the maximum burst length cannot be more than 16. This bit should not be set when DRE is enabled.\nThis bit is non functional when DMA is used in multichannel mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Cyclic_BD_Enable": {
|
||||
"bit_offset": 4,
|
||||
"bit_width": 1,
|
||||
"display_name": "Cyclic BD Enable",
|
||||
"description": "When set to 1, the DMA operates in Cyclic Buffer Descriptor (BD) mode without any user intervention. In this mode, the Scatter Gather module ignores the Completed bit of the BD. With this bit set, you can use the same BDs in cyclic manner without worrying about any stale descriptor errors.\nThis bit is non functional when DMA operates in Multichannel mode. or in Direct Register Mode\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"IOC_IrqEn": {
|
||||
"bit_offset": 12,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Complete (IOC) Interrupt Enable",
|
||||
"description": "Interrupt on Complete (IOC) Interrupt Enable. When set to 1, allows Interrupt On Complete events to generate an interrupt out for descriptors with the Complete bit set. 0 - IOC Interrupt disabled 1 - IOC Interrupt enabled\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Dly_IrqEn": {
|
||||
"bit_offset": 13,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Delay Timer Interrupt Enable",
|
||||
"description": "Interrupt on Delay Timer Interrupt Enable. When set to 1, allows error events to generate an interrupt out. 0 - Delay Interrupt disabled 1 - Delay Interrupt enabled Note: Applicable only when Scatter Gather is enabled.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Err_IrqEn": {
|
||||
"bit_offset": 14,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Error Interrupt Enable",
|
||||
"description": "Interrupt on Error Interrupt Enable. When set to 1, allows error events to generate an interrupt out. 0 - Error Interrupt disabled 1 - Error Interrupt enabled\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"IRQThreshold": {
|
||||
"bit_offset": 16,
|
||||
"bit_width": 8,
|
||||
"display_name": "Interrupt Threshold",
|
||||
"description": "Interrupt Threshold. This value is used for setting the interrupt threshold. When IOC interrupt events occur, an internal counter counts down from the Interrupt Threshold setting. When the count reaches zero, an interrupt out is generated by the DMA engine.\nNote: The minimum setting for the threshold is 0x01. A write of 0x00 to this register has no effect.\nNote: Applicable only when Scatter Gather is enabled.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"IRQDelay": {
|
||||
"bit_offset": 24,
|
||||
"bit_width": 8,
|
||||
"display_name": "Interrupt Delay Time Out",
|
||||
"description": "Interrupt Delay Time Out. This value is used for setting the interrupt timeout value. The interrupt timeout mechanism causes the DMA engine to generate an interrupt after the delay time period has expired. Timer begins counting at the end of a packet and resets with receipt of a new packet or a timeout event occurs.\nNote: Setting this value to zero disables the delay timer interrupt.\nNote: Applicable only when Scatter Gather is enabled.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"S2MM_DMASR": {
|
||||
"address_offset": "0x34",
|
||||
"size": 32,
|
||||
"display_name": "S2MM DMA Status Register",
|
||||
"description": "S2MM DMA Status Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x10000",
|
||||
"fields": {
|
||||
"Halted": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Channel Halted",
|
||||
"description": "DMA Channel Halted. Indicates the run/stop state of the DMA channel. 0 - DMA channel running. 1 - DMA channel halted. For Scatter/Gather Mode this bit gets set when DMACR.RS = 0 and DMA and SG operations have halted. For Direct Register Mode this bit gets set when DMACR.RS = 0 and DMA operations have halted. There can be a lag of time between when DMACR.RS = 0 and when DMASR.Halted = 1 \nNote: When halted (RS= 0 and Halted = 1), writing to CURDESC_PTR or TAILDESC_PTR pointer registers has no effect on DMA operations when in Scatter Gather Mode. For Direct Register Mode, writing to the LENGTH register has no effect on DMA operations.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"Idle": {
|
||||
"bit_offset": 1,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Channel Idle",
|
||||
"description": "DMA Channel Idle. Indicates the state of AXI DMA operations.\nFor Scatter / Gather Mode when IDLE indicates the SG Engine has reached the tail pointer for the associated channel and all queued descriptors have been processed. Writing to the tail pointer register automatically restarts DMA operations.\nFor Direct Register Mode when IDLE indicates the current transfer has completed. 0 - Not Idle. 1 - Idle. Note: This bit is 0 when channel is halted (DMASR.Halted=1). This bit is also 0 prior to initial transfer when AXI DMA configured for Direct Register Mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"SGIncld": {
|
||||
"bit_offset": 3,
|
||||
"bit_width": 1,
|
||||
"display_name": "SGIncld",
|
||||
"description": "Scatter Gather Engine Included. DMASR.SGIncld = 1 indicates the Scatter Gather engine is included and the AXI DMA is configured for Scatter Gather mode. DMASR.SGIncld = 0 indicates the Scatter Gather engine is excluded and the AXI DMA is configured for Direct Register Mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"DMAIntErr": {
|
||||
"bit_offset": 4,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Internal Error",
|
||||
"description": "DMA Internal Error. This error occurs if the buffer length specified in the fetched descriptor is set to 0. Also, when in Scatter Gather Mode and using the status app length field, this error occurs when the Status AXI4-Stream packet RxLength field does not match the S2MM packet being received by the S_AXIS_S2MM interface. When Scatter Gather is disabled, this error is flagged if any error occurs during Memory write or if the incoming packet is bigger than what is specified in the DMA length register.\nThis error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Internal Errors 1 - DMA Internal Error detected.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"DMASlvErr": {
|
||||
"bit_offset": 5,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Slave Error",
|
||||
"description": "DMA Slave Error. This error occurs if the slave read from the Memory Map interface issues a Slave Error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Slave Errors. 1 - DMA Slave Error detected.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"DMADecErr": {
|
||||
"bit_offset": 6,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Decode Error",
|
||||
"description": "DMA Decode Error. This error occurs if the address request points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Decode Errors. 1 - DMA Decode Error detected.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"SGIntErr": {
|
||||
"bit_offset": 8,
|
||||
"bit_width": 1,
|
||||
"display_name": "Scatter Gather Internal Error",
|
||||
"description": "Scatter Gather Internal Error. This error occurs if a descriptor with the \"Complete bit\" already set is fetched. This indicates to the SG Engine that the descriptor is a tail descriptor. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Internal Errors. 1 - SG Internal Error detected. Note: Applicable only when Scatter Gather is enabled. \n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"SGSlvErr": {
|
||||
"bit_offset": 9,
|
||||
"bit_width": 1,
|
||||
"display_name": "Scatter Gather Slave Error",
|
||||
"description": "Scatter Gather Slave Error. This error occurs if the slave read from on the Memory Map interface issues a Slave error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Slave Errors. 1 - SG Slave Error detected. DMA Engine halts. Note: Applicable only when Scatter Gather is enabled. \n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"SGDecErr": {
|
||||
"bit_offset": 10,
|
||||
"bit_width": 1,
|
||||
"display_name": "Scatter Gather Decode Error",
|
||||
"description": "Scatter Gather Decode Error. This error occurs if CURDESC_PTR and/or NXTDESC_PTR points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Decode Errors. 1 - SG Decode Error detected. DMA Engine halts. Note: Applicable only when Scatter Gather is enabled. \n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"IOC_Irq": {
|
||||
"bit_offset": 12,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Complete",
|
||||
"description": "Interrupt on Complete. When set to 1 for Scatter/Gather Mode, indicates an interrupt event was generated on completion of a descriptor. This occurs for descriptors with the End of Frame (EOF) bit set. When set to 1 for Direct Register Mode, indicates an interrupt event was generated on completion of a transfer. If the corresponding bit in S2MM_DMACR is enabled (IOC_IrqEn = 1) and if the interrupt threshold has been met, causes an interrupt out to be generated from the AXI DMA. 0 - No IOC Interrupt. 1 - IOC Interrupt detected. Writing a 1 to this bit will clear it.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Dly_Irq": {
|
||||
"bit_offset": 13,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Delay",
|
||||
"description": "Interrupt on Delay. When set to 1, indicates an interrupt event was generated on delay timer time out. If the corresponding bit is enabled in the S2MM_DMACR (Dly_IrqEn = 1), an interrupt out is generated from the AXI DMA. 0 - No Delay Interrupt. 1 - Delay Interrupt detected.1 = IOC Interrupt detected. Writing a 1 to this bit will clear it. Note: Applicable only when Scatter Gather is enabled. \n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Err_Irq": {
|
||||
"bit_offset": 14,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Error",
|
||||
"description": "Interrupt on Error. When set to 1, indicates an interrupt event was generated on error. If the corresponding bit is enabled in the S2MM_DMACR (Err_IrqEn = 1), an interrupt out is generated from the AXI DMA.\nWriting a 1 to this bit will clear it. 0 - No error Interrupt. 1 - Error interrupt detected.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"IRQThresholdSts": {
|
||||
"bit_offset": 16,
|
||||
"bit_width": 8,
|
||||
"display_name": "Interrupt Threshold Status",
|
||||
"description": "Interrupt Threshold Status. Indicates current interrupt threshold value.\nNote: Applicable only when Scatter Gather is enabled.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"IRQDelaySts": {
|
||||
"bit_offset": 24,
|
||||
"bit_width": 8,
|
||||
"display_name": "Interrupt Delay Time Status",
|
||||
"description": "Interrupt Delay Time Status. Indicates current interrupt delay time value.\nNote: Applicable only when Scatter Gather is enabled.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
}
|
||||
}
|
||||
},
|
||||
"S2MM_DA": {
|
||||
"address_offset": "0x48",
|
||||
"size": 32,
|
||||
"display_name": "S2MM DMA Destination Address Register",
|
||||
"description": "S2MM DMA Destination Address Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"Destination_Address": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 32,
|
||||
"display_name": "Destination Address",
|
||||
"description": "Indicates the destination address the AXI DMA writes to transfer data from AXI4-Stream on S2MM Channel.\nNote: If Data Realignment Engine is included, the Destination Address can be at any byte offset. If Data Realignment Engine is not included, the Destination Address must be S2MM Memory Map data width aligned.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"S2MM_DA_MSB": {
|
||||
"address_offset": "0x4C",
|
||||
"size": 32,
|
||||
"display_name": "S2MM Destination Address Register",
|
||||
"description": "S2MM Destination Address Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"Destination_Address": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 32,
|
||||
"display_name": "Destination Address",
|
||||
"description": "Indicates the MSB 32 bits of the Destination address AXI DMA writes to transfer data from AXI4-Stream on the S2MM Channel.\nNote: If Data Realignment Engine is included, the Destination Address can be at any byte offset. If Data Realignment Engine is not included, the Dstination Address must be S2MM Memory Map data width aligned.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"S2MM_LENGTH": {
|
||||
"address_offset": "0x58",
|
||||
"size": 32,
|
||||
"display_name": "S2MM DMA Transfer Length Register",
|
||||
"description": "S2MM DMA Transfer Length Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"Length": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 26,
|
||||
"display_name": "Length",
|
||||
"description": "Indicates the length in bytes of the S2MM buffer available to write receive data from the S2MM channel. Writing a non-zero value to this register enables S2MM channel to receive packet data.\nAt the completion of the S2MM transfer, the number of actual bytes written on the S2MM AXI4 interface is updated to the S2MM_LENGTH register.\nNote: This value must be greater than or equal to the largest expected packet to be received on S2MM AXI4-Stream. Values smaller than the received packet result in undefined behavior. \n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+65
@@ -0,0 +1,65 @@
|
||||
# file: system_top_axi_dma_1_0.xdc
|
||||
# (c) Copyright 2009 - 2023 Advanced Micro Devices, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Advanced Micro Devices, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# AMD, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) AMD shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or AMD had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# AMD products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of AMD products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
## INFO: Level CDC Crossing in AXI DMA
|
||||
|
||||
set_false_path -to [get_pins -hier *cdc_to*/D]
|
||||
|
||||
create_waiver -internal -scope -type CDC -id {CDC-1} -user "axi_dma" -tags "9601"\
|
||||
-desc "The CDC-1 warning is waived as it is safe in the context of AXI DMA. The Address and Data value does not change until AXI transaction is complete." \
|
||||
-to [get_pins -hier -quiet -filter {NAME =~*I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_ASYNC_WRITE.REG_WADDR_TO_IPCLK/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[*].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/D}]
|
||||
|
||||
create_waiver -internal -scope -type CDC -id {CDC-1} -user "axi_dma" -tags "9601"\
|
||||
-desc "The CDC-1 warning is waived as it is safe in the context of AXI DMA. The Address and Data value does not change until AXI transaction is complete." \
|
||||
-to [get_pins -hier -quiet -filter {NAME =~*I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_ASYNC_WRITE.REG_WADDR_TO_IPCLK1/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[*].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/D}]
|
||||
|
||||
# Specific to MultiChannel mode
|
||||
create_waiver -internal -scope -type CDC -id {CDC-1} -user "axi_dma" -tags "9601"\
|
||||
-desc "The CDC-1 warning is waived as it is safe in the context of AXI DMA. In multi channel mode, it is safe to ignore this." \
|
||||
-from [get_pins -hier -quiet -filter {NAME =~*MM2S_SPLIT.I_COMMAND_MM2S_SPLITTER/vsize_data_int_reg[*]/C}]
|
||||
|
||||
|
||||
+8497
File diff suppressed because it is too large
Load Diff
+46
@@ -0,0 +1,46 @@
|
||||
# file: system_top_axi_dma_1_0.xdc
|
||||
# (c) Copyright 2009 - 2023 Advanced Micro Devices, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Advanced Micro Devices, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# AMD, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) AMD shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or AMD had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# AMD products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of AMD products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
+431
@@ -0,0 +1,431 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:axi_dma:7.1
|
||||
-- IP Revision: 32
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY axi_dma_v7_1_32;
|
||||
USE axi_dma_v7_1_32.axi_dma;
|
||||
|
||||
ENTITY system_top_axi_dma_2_0 IS
|
||||
PORT (
|
||||
s_axi_lite_aclk : IN STD_LOGIC;
|
||||
m_axi_s2mm_aclk : IN STD_LOGIC;
|
||||
axi_resetn : IN STD_LOGIC;
|
||||
s_axi_lite_awvalid : IN STD_LOGIC;
|
||||
s_axi_lite_awready : OUT STD_LOGIC;
|
||||
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
s_axi_lite_wvalid : IN STD_LOGIC;
|
||||
s_axi_lite_wready : OUT STD_LOGIC;
|
||||
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_lite_bvalid : OUT STD_LOGIC;
|
||||
s_axi_lite_bready : IN STD_LOGIC;
|
||||
s_axi_lite_arvalid : IN STD_LOGIC;
|
||||
s_axi_lite_arready : OUT STD_LOGIC;
|
||||
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
s_axi_lite_rvalid : OUT STD_LOGIC;
|
||||
s_axi_lite_rready : IN STD_LOGIC;
|
||||
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(39 DOWNTO 0);
|
||||
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_s2mm_awvalid : OUT STD_LOGIC;
|
||||
m_axi_s2mm_awready : IN STD_LOGIC;
|
||||
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
|
||||
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_s2mm_wlast : OUT STD_LOGIC;
|
||||
m_axi_s2mm_wvalid : OUT STD_LOGIC;
|
||||
m_axi_s2mm_wready : IN STD_LOGIC;
|
||||
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_s2mm_bvalid : IN STD_LOGIC;
|
||||
m_axi_s2mm_bready : OUT STD_LOGIC;
|
||||
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
|
||||
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
|
||||
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
s_axis_s2mm_tvalid : IN STD_LOGIC;
|
||||
s_axis_s2mm_tready : OUT STD_LOGIC;
|
||||
s_axis_s2mm_tlast : IN STD_LOGIC;
|
||||
s2mm_introut : OUT STD_LOGIC;
|
||||
axi_dma_tstvec : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
END system_top_axi_dma_2_0;
|
||||
|
||||
ARCHITECTURE system_top_axi_dma_2_0_arch OF system_top_axi_dma_2_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_top_axi_dma_2_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axi_dma IS
|
||||
GENERIC (
|
||||
C_S_AXI_LITE_ADDR_WIDTH : INTEGER;
|
||||
C_S_AXI_LITE_DATA_WIDTH : INTEGER;
|
||||
C_DLYTMR_RESOLUTION : INTEGER;
|
||||
C_PRMRY_IS_ACLK_ASYNC : INTEGER;
|
||||
C_ENABLE_MULTI_CHANNEL : INTEGER;
|
||||
C_NUM_MM2S_CHANNELS : INTEGER;
|
||||
C_NUM_S2MM_CHANNELS : INTEGER;
|
||||
C_INCLUDE_SG : INTEGER;
|
||||
C_SG_INCLUDE_STSCNTRL_STRM : INTEGER;
|
||||
C_SG_USE_STSAPP_LENGTH : INTEGER;
|
||||
C_SG_LENGTH_WIDTH : INTEGER;
|
||||
C_M_AXI_SG_ADDR_WIDTH : INTEGER;
|
||||
C_M_AXI_SG_DATA_WIDTH : INTEGER;
|
||||
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : INTEGER;
|
||||
C_S_AXIS_S2MM_STS_TDATA_WIDTH : INTEGER;
|
||||
C_MICRO_DMA : INTEGER;
|
||||
C_INCLUDE_MM2S : INTEGER;
|
||||
C_INCLUDE_MM2S_SF : INTEGER;
|
||||
C_MM2S_BURST_SIZE : INTEGER;
|
||||
C_M_AXI_MM2S_ADDR_WIDTH : INTEGER;
|
||||
C_M_AXI_MM2S_DATA_WIDTH : INTEGER;
|
||||
C_M_AXIS_MM2S_TDATA_WIDTH : INTEGER;
|
||||
C_INCLUDE_MM2S_DRE : INTEGER;
|
||||
C_INCLUDE_S2MM : INTEGER;
|
||||
C_INCLUDE_S2MM_SF : INTEGER;
|
||||
C_S2MM_BURST_SIZE : INTEGER;
|
||||
C_M_AXI_S2MM_ADDR_WIDTH : INTEGER;
|
||||
C_M_AXI_S2MM_DATA_WIDTH : INTEGER;
|
||||
C_S_AXIS_S2MM_TDATA_WIDTH : INTEGER;
|
||||
C_INCLUDE_S2MM_DRE : INTEGER;
|
||||
C_INCREASE_THROUGHPUT : INTEGER;
|
||||
C_FAMILY : STRING
|
||||
);
|
||||
PORT (
|
||||
s_axi_lite_aclk : IN STD_LOGIC;
|
||||
m_axi_sg_aclk : IN STD_LOGIC;
|
||||
m_axi_mm2s_aclk : IN STD_LOGIC;
|
||||
m_axi_s2mm_aclk : IN STD_LOGIC;
|
||||
axi_resetn : IN STD_LOGIC;
|
||||
s_axi_lite_awvalid : IN STD_LOGIC;
|
||||
s_axi_lite_awready : OUT STD_LOGIC;
|
||||
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
s_axi_lite_wvalid : IN STD_LOGIC;
|
||||
s_axi_lite_wready : OUT STD_LOGIC;
|
||||
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_lite_bvalid : OUT STD_LOGIC;
|
||||
s_axi_lite_bready : IN STD_LOGIC;
|
||||
s_axi_lite_arvalid : IN STD_LOGIC;
|
||||
s_axi_lite_arready : OUT STD_LOGIC;
|
||||
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
s_axi_lite_rvalid : OUT STD_LOGIC;
|
||||
s_axi_lite_rready : IN STD_LOGIC;
|
||||
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_sg_awaddr : OUT STD_LOGIC_VECTOR(39 DOWNTO 0);
|
||||
m_axi_sg_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_sg_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_sg_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_sg_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_sg_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_sg_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_sg_awvalid : OUT STD_LOGIC;
|
||||
m_axi_sg_awready : IN STD_LOGIC;
|
||||
m_axi_sg_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_sg_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_sg_wlast : OUT STD_LOGIC;
|
||||
m_axi_sg_wvalid : OUT STD_LOGIC;
|
||||
m_axi_sg_wready : IN STD_LOGIC;
|
||||
m_axi_sg_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_sg_bvalid : IN STD_LOGIC;
|
||||
m_axi_sg_bready : OUT STD_LOGIC;
|
||||
m_axi_sg_araddr : OUT STD_LOGIC_VECTOR(39 DOWNTO 0);
|
||||
m_axi_sg_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_sg_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_sg_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_sg_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_sg_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_sg_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_sg_arvalid : OUT STD_LOGIC;
|
||||
m_axi_sg_arready : IN STD_LOGIC;
|
||||
m_axi_sg_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_sg_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_sg_rlast : IN STD_LOGIC;
|
||||
m_axi_sg_rvalid : IN STD_LOGIC;
|
||||
m_axi_sg_rready : OUT STD_LOGIC;
|
||||
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(39 DOWNTO 0);
|
||||
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_mm2s_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_mm2s_arvalid : OUT STD_LOGIC;
|
||||
m_axi_mm2s_arready : IN STD_LOGIC;
|
||||
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_mm2s_rlast : IN STD_LOGIC;
|
||||
m_axi_mm2s_rvalid : IN STD_LOGIC;
|
||||
m_axi_mm2s_rready : OUT STD_LOGIC;
|
||||
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
|
||||
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axis_mm2s_tvalid : OUT STD_LOGIC;
|
||||
m_axis_mm2s_tready : IN STD_LOGIC;
|
||||
m_axis_mm2s_tlast : OUT STD_LOGIC;
|
||||
m_axis_mm2s_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axis_mm2s_tid : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
|
||||
m_axis_mm2s_tdest : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
|
||||
mm2s_cntrl_reset_out_n : OUT STD_LOGIC;
|
||||
m_axis_mm2s_cntrl_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axis_mm2s_cntrl_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axis_mm2s_cntrl_tvalid : OUT STD_LOGIC;
|
||||
m_axis_mm2s_cntrl_tready : IN STD_LOGIC;
|
||||
m_axis_mm2s_cntrl_tlast : OUT STD_LOGIC;
|
||||
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(39 DOWNTO 0);
|
||||
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_s2mm_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_s2mm_awvalid : OUT STD_LOGIC;
|
||||
m_axi_s2mm_awready : IN STD_LOGIC;
|
||||
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
|
||||
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_s2mm_wlast : OUT STD_LOGIC;
|
||||
m_axi_s2mm_wvalid : OUT STD_LOGIC;
|
||||
m_axi_s2mm_wready : IN STD_LOGIC;
|
||||
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_s2mm_bvalid : IN STD_LOGIC;
|
||||
m_axi_s2mm_bready : OUT STD_LOGIC;
|
||||
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
|
||||
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
|
||||
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
s_axis_s2mm_tvalid : IN STD_LOGIC;
|
||||
s_axis_s2mm_tready : OUT STD_LOGIC;
|
||||
s_axis_s2mm_tlast : IN STD_LOGIC;
|
||||
s_axis_s2mm_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axis_s2mm_tid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
|
||||
s_axis_s2mm_tdest : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
|
||||
s2mm_sts_reset_out_n : OUT STD_LOGIC;
|
||||
s_axis_s2mm_sts_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axis_s2mm_sts_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axis_s2mm_sts_tvalid : IN STD_LOGIC;
|
||||
s_axis_s2mm_sts_tready : OUT STD_LOGIC;
|
||||
s_axis_s2mm_sts_tlast : IN STD_LOGIC;
|
||||
mm2s_introut : OUT STD_LOGIC;
|
||||
s2mm_introut : OUT STD_LOGIC;
|
||||
axi_dma_tstvec : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT axi_dma;
|
||||
ATTRIBUTE X_CORE_INFO : STRING;
|
||||
ATTRIBUTE X_CORE_INFO OF system_top_axi_dma_2_0_arch: ARCHITECTURE IS "axi_dma,Vivado 2024.1";
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE OF system_top_axi_dma_2_0_arch : ARCHITECTURE IS "system_top_axi_dma_2_0,axi_dma,{}";
|
||||
ATTRIBUTE CORE_GENERATION_INFO : STRING;
|
||||
ATTRIBUTE CORE_GENERATION_INFO OF system_top_axi_dma_2_0_arch: ARCHITECTURE IS "system_top_axi_dma_2_0,axi_dma,{x_ipProduct=Vivado 2024.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_dma,x_ipVersion=7.1,x_ipCoreRevision=32,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_S_AXI_LITE_ADDR_WIDTH=10,C_S_AXI_LITE_DATA_WIDTH=32,C_DLYTMR_RESOLUTION=125,C_PRMRY_IS_ACLK_ASYNC=1,C_ENABLE_MULTI_CHANNEL=0,C_NUM_MM2S_CHANNELS=1,C_NUM_S2MM_CHANNELS=1,C_INCLUDE_SG=0,C_SG_INCLUDE_STSCNTRL_STRM=0,C_SG_USE_STSAPP_LENGTH=0,C_SG_LENGTH_WIDTH=26,C_M_AXI_SG_ADDR_WIDTH=40,C_M_AXI_SG_DATA_WIDTH=3" &
|
||||
"2,C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH=32,C_S_AXIS_S2MM_STS_TDATA_WIDTH=32,C_MICRO_DMA=0,C_INCLUDE_MM2S=0,C_INCLUDE_MM2S_SF=1,C_MM2S_BURST_SIZE=16,C_M_AXI_MM2S_ADDR_WIDTH=40,C_M_AXI_MM2S_DATA_WIDTH=32,C_M_AXIS_MM2S_TDATA_WIDTH=32,C_INCLUDE_MM2S_DRE=0,C_INCLUDE_S2MM=1,C_INCLUDE_S2MM_SF=1,C_S2MM_BURST_SIZE=16,C_M_AXI_S2MM_ADDR_WIDTH=40,C_M_AXI_S2MM_DATA_WIDTH=64,C_S_AXIS_S2MM_TDATA_WIDTH=64,C_INCLUDE_S2MM_DRE=0,C_INCREASE_THROUGHPUT=0,C_FAMILY=zynq}";
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF axi_resetn: SIGNAL IS "XIL_INTERFACENAME AXI_RESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF axi_resetn: SIGNAL IS "xilinx.com:signal:reset:1.0 AXI_RESETN RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axi_s2mm_aclk: SIGNAL IS "XIL_INTERFACENAME M_AXI_S2MM_CLK, ASSOCIATED_BUSIF M_AXI_S2MM:S_AXIS_S2MM:S_AXIS_STS, ASSOCIATED_RESET s2mm_prmry_reset_out_n:s2mm_sts_reset_out_n, FREQ_HZ 200000000, FREQ_TOLERANCE_HZ 0, PHASE 0, CLK_DOMAIN system_top_mig_7series_0_0_ui_clk, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_S2MM_CLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axi_s2mm_awaddr: SIGNAL IS "XIL_INTERFACENAME M_AXI_S2MM, SUPPORTS_NARROW_BURST 0, NUM_WRITE_OUTSTANDING 16, DATA_WIDTH 64, PROTOCOL AXI4, FREQ_HZ 200000000, ID_WIDTH 0, ADDR_WIDTH 40, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, NUM_READ_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0, CLK_DOMAIN system_top_mig_7series_0_0_ui_clk, NUM_READ_THREADS 1, NUM_" &
|
||||
"WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWBURST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWCACHE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWLEN";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWPROT";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWSIZE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WSTRB";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s2mm_introut: SIGNAL IS "XIL_INTERFACENAME S2MM_INTROUT, SENSITIVITY LEVEL_HIGH, PortWidth 1";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s2mm_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 S2MM_INTROUT INTERRUPT";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s2mm_prmry_reset_out_n: SIGNAL IS "XIL_INTERFACENAME S2MM_PRMRY_RESET_OUT_N, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s2mm_prmry_reset_out_n: SIGNAL IS "xilinx.com:signal:reset:1.0 S2MM_PRMRY_RESET_OUT_N RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_lite_aclk: SIGNAL IS "XIL_INTERFACENAME S_AXI_LITE_ACLK, ASSOCIATED_BUSIF S_AXI_LITE:M_AXI, ASSOCIATED_RESET axi_resetn, FREQ_HZ 1e+08, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN system_top_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_LITE_ACLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_lite_awvalid: SIGNAL IS "XIL_INTERFACENAME S_AXI_LITE, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 10, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 0, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN system_top_processing_system7_0_0_FCLK_CLK0, NUM_READ_THR" &
|
||||
"EADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_s2mm_tdata: SIGNAL IS "XIL_INTERFACENAME S_AXIS_S2MM, TDATA_NUM_BYTES 8, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 1, HAS_TLAST 1, FREQ_HZ 200000000, PHASE 0, CLK_DOMAIN system_top_mig_7series_0_0_ui_clk, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TKEEP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TVALID";
|
||||
BEGIN
|
||||
U0 : axi_dma
|
||||
GENERIC MAP (
|
||||
C_S_AXI_LITE_ADDR_WIDTH => 10,
|
||||
C_S_AXI_LITE_DATA_WIDTH => 32,
|
||||
C_DLYTMR_RESOLUTION => 125,
|
||||
C_PRMRY_IS_ACLK_ASYNC => 1,
|
||||
C_ENABLE_MULTI_CHANNEL => 0,
|
||||
C_NUM_MM2S_CHANNELS => 1,
|
||||
C_NUM_S2MM_CHANNELS => 1,
|
||||
C_INCLUDE_SG => 0,
|
||||
C_SG_INCLUDE_STSCNTRL_STRM => 0,
|
||||
C_SG_USE_STSAPP_LENGTH => 0,
|
||||
C_SG_LENGTH_WIDTH => 26,
|
||||
C_M_AXI_SG_ADDR_WIDTH => 40,
|
||||
C_M_AXI_SG_DATA_WIDTH => 32,
|
||||
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => 32,
|
||||
C_S_AXIS_S2MM_STS_TDATA_WIDTH => 32,
|
||||
C_MICRO_DMA => 0,
|
||||
C_INCLUDE_MM2S => 0,
|
||||
C_INCLUDE_MM2S_SF => 1,
|
||||
C_MM2S_BURST_SIZE => 16,
|
||||
C_M_AXI_MM2S_ADDR_WIDTH => 40,
|
||||
C_M_AXI_MM2S_DATA_WIDTH => 32,
|
||||
C_M_AXIS_MM2S_TDATA_WIDTH => 32,
|
||||
C_INCLUDE_MM2S_DRE => 0,
|
||||
C_INCLUDE_S2MM => 1,
|
||||
C_INCLUDE_S2MM_SF => 1,
|
||||
C_S2MM_BURST_SIZE => 16,
|
||||
C_M_AXI_S2MM_ADDR_WIDTH => 40,
|
||||
C_M_AXI_S2MM_DATA_WIDTH => 64,
|
||||
C_S_AXIS_S2MM_TDATA_WIDTH => 64,
|
||||
C_INCLUDE_S2MM_DRE => 0,
|
||||
C_INCREASE_THROUGHPUT => 0,
|
||||
C_FAMILY => "zynq"
|
||||
)
|
||||
PORT MAP (
|
||||
s_axi_lite_aclk => s_axi_lite_aclk,
|
||||
m_axi_sg_aclk => '0',
|
||||
m_axi_mm2s_aclk => '0',
|
||||
m_axi_s2mm_aclk => m_axi_s2mm_aclk,
|
||||
axi_resetn => axi_resetn,
|
||||
s_axi_lite_awvalid => s_axi_lite_awvalid,
|
||||
s_axi_lite_awready => s_axi_lite_awready,
|
||||
s_axi_lite_awaddr => s_axi_lite_awaddr,
|
||||
s_axi_lite_wvalid => s_axi_lite_wvalid,
|
||||
s_axi_lite_wready => s_axi_lite_wready,
|
||||
s_axi_lite_wdata => s_axi_lite_wdata,
|
||||
s_axi_lite_bresp => s_axi_lite_bresp,
|
||||
s_axi_lite_bvalid => s_axi_lite_bvalid,
|
||||
s_axi_lite_bready => s_axi_lite_bready,
|
||||
s_axi_lite_arvalid => s_axi_lite_arvalid,
|
||||
s_axi_lite_arready => s_axi_lite_arready,
|
||||
s_axi_lite_araddr => s_axi_lite_araddr,
|
||||
s_axi_lite_rvalid => s_axi_lite_rvalid,
|
||||
s_axi_lite_rready => s_axi_lite_rready,
|
||||
s_axi_lite_rdata => s_axi_lite_rdata,
|
||||
s_axi_lite_rresp => s_axi_lite_rresp,
|
||||
m_axi_sg_awready => '0',
|
||||
m_axi_sg_wready => '0',
|
||||
m_axi_sg_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
|
||||
m_axi_sg_bvalid => '0',
|
||||
m_axi_sg_arready => '0',
|
||||
m_axi_sg_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
m_axi_sg_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
|
||||
m_axi_sg_rlast => '0',
|
||||
m_axi_sg_rvalid => '0',
|
||||
m_axi_mm2s_arready => '0',
|
||||
m_axi_mm2s_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
m_axi_mm2s_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
|
||||
m_axi_mm2s_rlast => '0',
|
||||
m_axi_mm2s_rvalid => '0',
|
||||
m_axis_mm2s_tready => '0',
|
||||
m_axis_mm2s_cntrl_tready => '0',
|
||||
m_axi_s2mm_awaddr => m_axi_s2mm_awaddr,
|
||||
m_axi_s2mm_awlen => m_axi_s2mm_awlen,
|
||||
m_axi_s2mm_awsize => m_axi_s2mm_awsize,
|
||||
m_axi_s2mm_awburst => m_axi_s2mm_awburst,
|
||||
m_axi_s2mm_awprot => m_axi_s2mm_awprot,
|
||||
m_axi_s2mm_awcache => m_axi_s2mm_awcache,
|
||||
m_axi_s2mm_awvalid => m_axi_s2mm_awvalid,
|
||||
m_axi_s2mm_awready => m_axi_s2mm_awready,
|
||||
m_axi_s2mm_wdata => m_axi_s2mm_wdata,
|
||||
m_axi_s2mm_wstrb => m_axi_s2mm_wstrb,
|
||||
m_axi_s2mm_wlast => m_axi_s2mm_wlast,
|
||||
m_axi_s2mm_wvalid => m_axi_s2mm_wvalid,
|
||||
m_axi_s2mm_wready => m_axi_s2mm_wready,
|
||||
m_axi_s2mm_bresp => m_axi_s2mm_bresp,
|
||||
m_axi_s2mm_bvalid => m_axi_s2mm_bvalid,
|
||||
m_axi_s2mm_bready => m_axi_s2mm_bready,
|
||||
s2mm_prmry_reset_out_n => s2mm_prmry_reset_out_n,
|
||||
s_axis_s2mm_tdata => s_axis_s2mm_tdata,
|
||||
s_axis_s2mm_tkeep => s_axis_s2mm_tkeep,
|
||||
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid,
|
||||
s_axis_s2mm_tready => s_axis_s2mm_tready,
|
||||
s_axis_s2mm_tlast => s_axis_s2mm_tlast,
|
||||
s_axis_s2mm_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
s_axis_s2mm_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
|
||||
s_axis_s2mm_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
|
||||
s_axis_s2mm_sts_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
s_axis_s2mm_sts_tkeep => X"F",
|
||||
s_axis_s2mm_sts_tvalid => '0',
|
||||
s_axis_s2mm_sts_tlast => '0',
|
||||
s2mm_introut => s2mm_introut,
|
||||
axi_dma_tstvec => axi_dma_tstvec
|
||||
);
|
||||
END system_top_axi_dma_2_0_arch;
|
||||
+976
@@ -0,0 +1,976 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "system_top_axi_dma_2_0",
|
||||
"cell_name": "axi_dma_2",
|
||||
"component_reference": "xilinx.com:ip:axi_dma:7.1",
|
||||
"ip_revision": "32",
|
||||
"gen_directory": ".",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "system_top_axi_dma_2_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"c_include_sg": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_enable_multi_channel": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"c_num_mm2s_channels": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"c_num_s2mm_channels": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"c_sg_length_width": [ { "value": "26", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_dlytmr_resolution": [ { "value": "125", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_prmry_is_aclk_async": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_sg_include_stscntrl_strm": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"c_micro_dma": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_include_mm2s": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_m_axi_mm2s_data_width": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"c_m_axis_mm2s_tdata_width": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"c_include_mm2s_dre": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"c_include_mm2s_sf": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_mm2s_burst_size": [ { "value": "16", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"c_include_s2mm": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_sg_use_stsapp_length": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"c_m_axi_s2mm_data_width": [ { "value": "64", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_s_axis_s2mm_tdata_width": [ { "value": "64", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_include_s2mm_dre": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_include_s2mm_sf": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_s2mm_burst_size": [ { "value": "16", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_addr_width": [ { "value": "40", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_single_interface": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"c_increase_throughput": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_S_AXI_LITE_ADDR_WIDTH": [ { "value": "10", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_LITE_DATA_WIDTH": [ { "value": "32", "format": "long", "usage": "all" } ],
|
||||
"C_DLYTMR_RESOLUTION": [ { "value": "125", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PRMRY_IS_ACLK_ASYNC": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ENABLE_MULTI_CHANNEL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_MM2S_CHANNELS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_S2MM_CHANNELS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INCLUDE_SG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SG_INCLUDE_STSCNTRL_STRM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SG_USE_STSAPP_LENGTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SG_LENGTH_WIDTH": [ { "value": "26", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_AXI_SG_ADDR_WIDTH": [ { "value": "40", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_AXI_SG_DATA_WIDTH": [ { "value": "32", "format": "long", "usage": "all" } ],
|
||||
"C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_S_AXIS_S2MM_STS_TDATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_MICRO_DMA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INCLUDE_MM2S": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INCLUDE_MM2S_SF": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_MM2S_BURST_SIZE": [ { "value": "16", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_M_AXI_MM2S_ADDR_WIDTH": [ { "value": "40", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_M_AXI_MM2S_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_M_AXIS_MM2S_TDATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_INCLUDE_MM2S_DRE": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_INCLUDE_S2MM": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INCLUDE_S2MM_SF": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S2MM_BURST_SIZE": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_AXI_S2MM_ADDR_WIDTH": [ { "value": "40", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_AXI_S2MM_DATA_WIDTH": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXIS_S2MM_TDATA_WIDTH": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INCLUDE_S2MM_DRE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INCREASE_THROUGHPUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_FAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "xilinx.com:zc706:part0:1.4" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z045" } ],
|
||||
"NEXTGEN_VERSAL": [ { "value": "0" } ],
|
||||
"PACKAGE": [ { "value": "ffg900" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "32" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "." } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2024.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"s_axi_lite_aclk": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"m_axi_s2mm_aclk": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"axi_resetn": [ { "direction": "in", "driver_value": "1" } ],
|
||||
"s_axi_lite_awvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_lite_awready": [ { "direction": "out" } ],
|
||||
"s_axi_lite_awaddr": [ { "direction": "in", "size_left": "9", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_lite_wvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_lite_wready": [ { "direction": "out" } ],
|
||||
"s_axi_lite_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_lite_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s_axi_lite_bvalid": [ { "direction": "out" } ],
|
||||
"s_axi_lite_bready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_lite_arvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_lite_arready": [ { "direction": "out" } ],
|
||||
"s_axi_lite_araddr": [ { "direction": "in", "size_left": "9", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_lite_rvalid": [ { "direction": "out" } ],
|
||||
"s_axi_lite_rready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_lite_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"s_axi_lite_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"m_axi_s2mm_awaddr": [ { "direction": "out", "size_left": "39", "size_right": "0" } ],
|
||||
"m_axi_s2mm_awlen": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
|
||||
"m_axi_s2mm_awsize": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||
"m_axi_s2mm_awburst": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"m_axi_s2mm_awprot": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||
"m_axi_s2mm_awcache": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||
"m_axi_s2mm_awvalid": [ { "direction": "out" } ],
|
||||
"m_axi_s2mm_awready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"m_axi_s2mm_wdata": [ { "direction": "out", "size_left": "63", "size_right": "0" } ],
|
||||
"m_axi_s2mm_wstrb": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
|
||||
"m_axi_s2mm_wlast": [ { "direction": "out" } ],
|
||||
"m_axi_s2mm_wvalid": [ { "direction": "out" } ],
|
||||
"m_axi_s2mm_wready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"m_axi_s2mm_bresp": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"m_axi_s2mm_bvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"m_axi_s2mm_bready": [ { "direction": "out" } ],
|
||||
"s2mm_prmry_reset_out_n": [ { "direction": "out" } ],
|
||||
"s_axis_s2mm_tdata": [ { "direction": "in", "size_left": "63", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axis_s2mm_tkeep": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0xFF" } ],
|
||||
"s_axis_s2mm_tvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axis_s2mm_tready": [ { "direction": "out" } ],
|
||||
"s_axis_s2mm_tlast": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s2mm_introut": [ { "direction": "out" } ],
|
||||
"axi_dma_tstvec": [ { "direction": "out", "size_left": "31", "size_right": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"S_AXI_LITE": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"memory_map_ref": "S_AXI_LITE",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "1e+08", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "10", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"ARADDR": [ { "physical_name": "s_axi_lite_araddr" } ],
|
||||
"ARREADY": [ { "physical_name": "s_axi_lite_arready" } ],
|
||||
"ARVALID": [ { "physical_name": "s_axi_lite_arvalid" } ],
|
||||
"AWADDR": [ { "physical_name": "s_axi_lite_awaddr" } ],
|
||||
"AWREADY": [ { "physical_name": "s_axi_lite_awready" } ],
|
||||
"AWVALID": [ { "physical_name": "s_axi_lite_awvalid" } ],
|
||||
"BREADY": [ { "physical_name": "s_axi_lite_bready" } ],
|
||||
"BRESP": [ { "physical_name": "s_axi_lite_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "s_axi_lite_bvalid" } ],
|
||||
"RDATA": [ { "physical_name": "s_axi_lite_rdata" } ],
|
||||
"RREADY": [ { "physical_name": "s_axi_lite_rready" } ],
|
||||
"RRESP": [ { "physical_name": "s_axi_lite_rresp" } ],
|
||||
"RVALID": [ { "physical_name": "s_axi_lite_rvalid" } ],
|
||||
"WDATA": [ { "physical_name": "s_axi_lite_wdata" } ],
|
||||
"WREADY": [ { "physical_name": "s_axi_lite_wready" } ],
|
||||
"WVALID": [ { "physical_name": "s_axi_lite_wvalid" } ]
|
||||
}
|
||||
},
|
||||
"M_AXI_S2MM": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "master",
|
||||
"address_space_ref": "Data_S2MM",
|
||||
"parameters": {
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
|
||||
"DATA_WIDTH": [ { "value": "64", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "200000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "40", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "WRITE_ONLY", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "16", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_mig_7series_0_0_ui_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"AWADDR": [ { "physical_name": "m_axi_s2mm_awaddr" } ],
|
||||
"AWBURST": [ { "physical_name": "m_axi_s2mm_awburst" } ],
|
||||
"AWCACHE": [ { "physical_name": "m_axi_s2mm_awcache" } ],
|
||||
"AWLEN": [ { "physical_name": "m_axi_s2mm_awlen" } ],
|
||||
"AWPROT": [ { "physical_name": "m_axi_s2mm_awprot" } ],
|
||||
"AWREADY": [ { "physical_name": "m_axi_s2mm_awready" } ],
|
||||
"AWSIZE": [ { "physical_name": "m_axi_s2mm_awsize" } ],
|
||||
"AWVALID": [ { "physical_name": "m_axi_s2mm_awvalid" } ],
|
||||
"BREADY": [ { "physical_name": "m_axi_s2mm_bready" } ],
|
||||
"BRESP": [ { "physical_name": "m_axi_s2mm_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "m_axi_s2mm_bvalid" } ],
|
||||
"WDATA": [ { "physical_name": "m_axi_s2mm_wdata" } ],
|
||||
"WLAST": [ { "physical_name": "m_axi_s2mm_wlast" } ],
|
||||
"WREADY": [ { "physical_name": "m_axi_s2mm_wready" } ],
|
||||
"WSTRB": [ { "physical_name": "m_axi_s2mm_wstrb" } ],
|
||||
"WVALID": [ { "physical_name": "m_axi_s2mm_wvalid" } ]
|
||||
}
|
||||
},
|
||||
"S_AXIS_S2MM": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "8", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "200000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_mig_7series_0_0_ui_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "s_axis_s2mm_tdata" } ],
|
||||
"TKEEP": [ { "physical_name": "s_axis_s2mm_tkeep" } ],
|
||||
"TLAST": [ { "physical_name": "s_axis_s2mm_tlast" } ],
|
||||
"TREADY": [ { "physical_name": "s_axis_s2mm_tready" } ],
|
||||
"TVALID": [ { "physical_name": "s_axis_s2mm_tvalid" } ]
|
||||
}
|
||||
},
|
||||
"AXI_RESETN": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "axi_resetn" } ]
|
||||
}
|
||||
},
|
||||
"MM2S_INTROUT": {
|
||||
"vlnv": "xilinx.com:signal:interrupt:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"SENSITIVITY": [ { "value": "LEVEL_HIGH", "value_src": "constant", "usage": "all" } ],
|
||||
"PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"S2MM_INTROUT": {
|
||||
"vlnv": "xilinx.com:signal:interrupt:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"SENSITIVITY": [ { "value": "LEVEL_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"PortWidth": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"INTERRUPT": [ { "physical_name": "s2mm_introut" } ]
|
||||
}
|
||||
},
|
||||
"M_AXI_SG_CLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "M_AXI_SG", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"M_AXI_MM2S_CLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "M_AXI_MM2S:M_AXIS_MM2S:M_AXIS_CNTRL", "value_src": "constant", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "mm2s_prmry_reset_out_n:mm2s_cntrl_reset_out_n", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"M_AXI_S2MM_CLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "M_AXI_S2MM:S_AXIS_S2MM:S_AXIS_STS", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "s2mm_prmry_reset_out_n:s2mm_sts_reset_out_n", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "200000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_mig_7series_0_0_ui_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "m_axi_s2mm_aclk" } ]
|
||||
}
|
||||
},
|
||||
"S_AXI_LITE_ACLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S_AXI_LITE:M_AXI", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "axi_resetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "1e+08", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "s_axi_lite_aclk" } ]
|
||||
}
|
||||
},
|
||||
"MM2S_PRMRY_RESET_OUT_N": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"S2MM_PRMRY_RESET_OUT_N": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "s2mm_prmry_reset_out_n" } ]
|
||||
}
|
||||
},
|
||||
"MM2S_CNTRL_RESET_OUT_N": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"S2MM_STS_RESET_OUT_N": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
}
|
||||
},
|
||||
"address_spaces": {
|
||||
"Data_S2MM": {
|
||||
"range": "1099511627776",
|
||||
"width": "40"
|
||||
}
|
||||
},
|
||||
"memory_maps": {
|
||||
"S_AXI_LITE": {
|
||||
"display_name": "S_AXI_MEM",
|
||||
"description": "Memory Map for S_AXI_LITE",
|
||||
"address_blocks": {
|
||||
"Reg": {
|
||||
"base_address": "0",
|
||||
"range": "4096",
|
||||
"display_name": "Reg",
|
||||
"description": "Register Block",
|
||||
"usage": "register",
|
||||
"access": "read-write",
|
||||
"registers": {
|
||||
"MM2S_DMACR": {
|
||||
"address_offset": "0x0",
|
||||
"size": 32,
|
||||
"display_name": "MM2S DMA Control Register",
|
||||
"description": "MM2S DMA Control Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x10002",
|
||||
"fields": {
|
||||
"RS": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 1,
|
||||
"display_name": "Run/Stop Control",
|
||||
"description": "Run / Stop control for controlling running and stopping of the DMA channel.\n 0 - Stop, DMA stops when current (if any) DMA operations are complete. For Scatter / Gather Mode pending commands/transfers are flushed or completed. \n AXI4-Stream outs are potentially terminated early. Descriptors in the update queue are allowed to finish updating to remote memory before engine halt.\n For Direct Register mode pending commands/transfers are flushed or completed. AXI4-Stream outs are potentially terminated.\n The halted bit in the DMA Status register asserts to 1 when the DMA engine is halted. This bit is cleared by AXI DMA hardware when an error occurs. The CPU can also choose to clear this bit to stop DMA operations.\n 1 - Run, Start DMA operations. The halted bit in the DMA Status register deasserts to 0 when the DMA engine begins operations.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Reset": {
|
||||
"bit_offset": 2,
|
||||
"bit_width": 1,
|
||||
"display_name": "Soft Reset",
|
||||
"description": "Soft reset for resetting the AXI DMA core. Setting this bit to a 1 causes the AXI DMA to be reset. Reset is accomplished gracefully. Pending commands/transfers are flushed or completed.\nAXI4-Stream outs are potentially terminated early. Setting either MM2S_DMACR. Reset = 1 or S2MM_DMACR.Reset = 1 resets the entire AXI DMA engine. After completion of a soft reset, all registers and bits are in the Reset State. 0 - Normal operation. 1 - Reset in progress.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Keyhole": {
|
||||
"bit_offset": 3,
|
||||
"bit_width": 1,
|
||||
"display_name": "Keyhole Read",
|
||||
"description": "Keyhole Read. Setting this bit to 1 causes AXI DMA to initiate MM2S reads (AXI4read) in non-incrementing address mode (Fixed Address Burst transfer on AXI4). This bit can be updated when AXI DMA is in idle. When using keyhole operation the Max Burst Length should not exceed 16. This bit should not be set when DRE is enabled.\nThis bit is non functional when the multichannel feature is enabled or in Direct Register mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Cyclic_BD_Enable": {
|
||||
"bit_offset": 4,
|
||||
"bit_width": 1,
|
||||
"display_name": "Cyclic BD Enable",
|
||||
"description": "When set to 1, the DMA operates in Cyclic Buffer Descriptor (BD) mode without any user intervention. In this mode, the Scatter Gather module ignores the Completed bit of the BD. With this bit set, you can use the same BDs in cyclic manner without worrying about any stale descriptor errors.\nThis bit should be set/unset only when the DMA is idle or when not running. Updating this bit while the DMA is running can result in unexpected behavior.\nThis bit is non functional when DMA operates in multichannel mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"IOC_IrqEn": {
|
||||
"bit_offset": 12,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Complete (IOC) Interrupt Enable",
|
||||
"description": "Interrupt on Complete (IOC) Interrupt Enable. When set to 1, allows DMASR.IOC_Irq to generate an interrupt out for descriptors with the IOC bit set. 0 - IOC Interrupt disabled 1 - IOC Interrupt enabled\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Dly_IrqEn": {
|
||||
"bit_offset": 13,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Delay Timer Interrupt Enable",
|
||||
"description": "Interrupt on Delay Timer Interrupt Enable. When set to 1, allows DMASR.Dly_Irq to generate an interrupt out. 0 - Delay Interrupt disabled 1 - Delay Interrupt enabled Note: This field is ignored when AXI DMA is configured for Direct Register Mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Err_IrqEn": {
|
||||
"bit_offset": 14,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Error Interrupt Enable",
|
||||
"description": "Interrupt on Error Interrupt Enable.\n 0 - Error Interrupt disabled\n 1 - Error Interrupt enabled\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"IRQThreshold": {
|
||||
"bit_offset": 16,
|
||||
"bit_width": 8,
|
||||
"display_name": "Interrupt Threshold",
|
||||
"description": "Interrupt Threshold. This value is used for setting the interrupt threshold. When IOC interrupt events occur, an internal counter counts down from the Interrupt Threshold setting. When the count reaches zero, an interrupt out is generated by the DMA engine. Note: The minimum setting for the threshold is 0x01. A write of 0x00 to this register has no effect. Note: This field is ignored when AXI DMA is configured for Direct Register Mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"IRQDelay": {
|
||||
"bit_offset": 24,
|
||||
"bit_width": 8,
|
||||
"display_name": "Interrupt Delay Time Out",
|
||||
"description": "Interrupt Delay Time Out. This value is used for setting the interrupt timeout value. The interrupt timeout mechanism causes the DMA engine to generate an interrupt after the delay time period has expired. Timer begins counting at the end of a packet and resets with receipt of a new packet or a timeout event occurs.\nNote: Setting this value to zero disables the delay timer interrupt.\nNote: This field is ignored when AXI DMA is configured for Direct Register Mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"MM2S_DMASR": {
|
||||
"address_offset": "0x04",
|
||||
"size": 32,
|
||||
"display_name": "MM2S DMA Status Register",
|
||||
"description": "MM2S DMA Status Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x10000",
|
||||
"fields": {
|
||||
"Halted": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Channel Halted",
|
||||
"description": "DMA Channel Halted. Indicates the run/stop state of the DMA channel. 0 - DMA channel running. 1 - DMA channel halted. For Scatter / Gather Mode this bit gets set when DMACR.RS = 0 and DMA and SG operations have halted. For Direct Register mode (C_INCLUDE_SG = 0) this bit gets set when DMACR.RS = 0 and DMA operations have halted. There can be a lag of time between when DMACR.RS = 0 and when DMASR.Halted = 1 Note: When halted (RS= 0 and Halted = 1), writing to CURDESC_PTR or TAILDESC_PTR pointer registers has no effect on DMA operations when in Scatter Gather Mode. For Direct Register Mode, writing to the LENGTH register has no effect on DMA operations.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"Idle": {
|
||||
"bit_offset": 1,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Channel Idle",
|
||||
"description": "DMA Channel Idle. Indicates the state of AXI DMA operations.\nFor Scatter / Gather Mode when IDLE indicates the SG Engine has reached the tail pointer for the associated channel and all queued descriptors have been processed. Writing to the tail pointer register automatically restarts DMA operations.\nFor Direct Register Mode when IDLE indicates the current transfer has completed. 0 - Not Idle. For Scatter / Gather Mode, SG has not reached tail descriptor pointer and/or DMA operations in progress. For Direct Register Mode, transfer is not complete. 1 - Idle. For Scatter / Gather Mode, SG has reached tail descriptor pointer and DMA operation paused. for Direct Register Mode, DMA transfer has completed and controller is paused. Note: This bit is 0 when channel is halted (DMASR.Halted=1). This bit is also 0 prior to initial transfer when AXI DMA configured for Direct Register Mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"SGIncld": {
|
||||
"bit_offset": 3,
|
||||
"bit_width": 1,
|
||||
"display_name": "SGIncld",
|
||||
"description": "1 - Scatter Gather Enabled\n0 - Scatter Gather not enabled\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"DMAIntErr": {
|
||||
"bit_offset": 4,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Internal Error",
|
||||
"description": "DMA Internal Error. Internal error occurs if the buffer length specified in the fetched descriptor is set to 0. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Internal Errors 1 - DMA Internal Error detected. DMA Engine halts\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"DMASlvErr": {
|
||||
"bit_offset": 5,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Slave Error",
|
||||
"description": "DMA Slave Error. This error occurs if the slave read from the Memory Map interface issues a Slave Error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Slave Errors. 1 - DMA Slave Error detected. DMA Engine halts\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"DMADecErr": {
|
||||
"bit_offset": 6,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Decode Error",
|
||||
"description": "DMA Decode Error. This error occurs if the address request points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Decode Errors. 1 - DMA Decode Error detected. DMA Engine halts.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"SGIntErr": {
|
||||
"bit_offset": 8,
|
||||
"bit_width": 1,
|
||||
"display_name": "Scatter Gather Internal Error",
|
||||
"description": "Scatter Gather Internal Error. This error occurs if a descriptor with the \"Complete bit\" already set is fetched. Refer to the Scatter Gather Descriptor section for more information.This indicates to the SG Engine that the descriptor is a stale descriptor. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Internal Errors. 1 - SG Internal Error detected. DMA Engine halts. Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"SGSlvErr": {
|
||||
"bit_offset": 9,
|
||||
"bit_width": 1,
|
||||
"display_name": "Scatter Gather Slave Error",
|
||||
"description": "Scatter Gather Slave Error. This error occurs if the slave read from on the Memory Map interface issues a Slave error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Slave Errors. 1 - SG Slave Error detected. DMA Engine halts. Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode. \n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"SGDecErr": {
|
||||
"bit_offset": 10,
|
||||
"bit_width": 1,
|
||||
"display_name": "Scatter Gather Decode Error",
|
||||
"description": "Scatter Gather Decode Error. This error occurs if CURDESC_PTR and/or NXTDESC_PTR points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Decode Errors. 1 - SG Decode Error detected. DMA Engine halts. Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode. \n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"IOC_Irq": {
|
||||
"bit_offset": 12,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Complete",
|
||||
"description": "Interrupt on Complete. When set to 1 for Scatter/Gather Mode, indicates an interrupt event was generated on completion of a descriptor. This occurs for descriptors with the End of Frame (EOF) bit set. When set to 1 for Direct Register Mode, indicates an interrupt event was generated on completion of a transfer. If the corresponding bit is enabled in the MM2S_DMACR (IOC_IrqEn = 1) and if the interrupt threshold has been met, causes an interrupt out to be generated from the AXI DMA. 0 - No IOC Interrupt. 1 - IOC Interrupt detected. Writing a 1 to this bit will clear it.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Dly_Irq": {
|
||||
"bit_offset": 13,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Delay",
|
||||
"description": "Interrupt on Delay. When set to 1, indicates an interrupt event was generated on delay timer time out. If the corresponding bit is enabled in the MM2S_DMACR (Dly_IrqEn = 1), an interrupt out is generated from the AXI DMA. 0 - No Delay Interrupt. 1 - Delay Interrupt detected. Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode. \n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Err_Irq": {
|
||||
"bit_offset": 14,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Error",
|
||||
"description": "Interrupt on Error. When set to 1, indicates an interrupt event was generated on error. If the corresponding bit is enabled in the MM2S_DMACR (Err_IrqEn = 1), an interrupt out is generated from the AXI DMA.\nWriting a 1 to this bit will clear it. \n0 - No error Interrupt. \n1 - Error interrupt detected.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"IRQThresholdSts": {
|
||||
"bit_offset": 16,
|
||||
"bit_width": 8,
|
||||
"display_name": "Interrupt Threshold Status",
|
||||
"description": "Interrupt Threshold Status. Indicates current interrupt threshold value.\nNote: Applicable only when Scatter Gather is enabled.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"IRQDelaySts": {
|
||||
"bit_offset": 24,
|
||||
"bit_width": 8,
|
||||
"display_name": "Interrupt Delay Time Status",
|
||||
"description": "Interrupt Delay Time Status. Indicates current interrupt delay time value.\nNote: Applicable only when Scatter Gather is enabled.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
}
|
||||
}
|
||||
},
|
||||
"MM2S_SA": {
|
||||
"address_offset": "0x18",
|
||||
"size": 32,
|
||||
"display_name": "MM2S Source Address Register",
|
||||
"description": "MM2S Source Address Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"Source_Address": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 32,
|
||||
"display_name": "Source Address",
|
||||
"description": "Indicates the source address AXI DMA reads from to transfer data to AXI4-Stream on the MM2S Channel.\nNote: If Data Realignment Engine is included, the Source Address can be at any byte offset. If Data Realignment Engine is not included, the Source Address must be MM2S Memory Map data width aligned.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"MM2S_SA_MSB": {
|
||||
"address_offset": "0x1C",
|
||||
"size": 32,
|
||||
"display_name": "MM2S Source Address Register",
|
||||
"description": "MM2S Source Address Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"Source_Address": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 32,
|
||||
"display_name": "Source Address",
|
||||
"description": "Indicates the MSB 32 bits of the source address AXI DMA reads from to transfer data to AXI4-Stream on the MM2S Channel.\nNote: If Data Realignment Engine is included, the Source Address can be at any byte offset. If Data Realignment Engine is not included, the Source Address must be MM2S Memory Map data width aligned.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"MM2S_LENGTH": {
|
||||
"address_offset": "0x28",
|
||||
"size": 32,
|
||||
"display_name": "MM2S DMA Transfer Length Register",
|
||||
"description": "MM2S DMA Transfer Length Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"Length": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 26,
|
||||
"display_name": "Length",
|
||||
"description": "Indicates the number of bytes to transfer for the MM2S channel. Writing a non-zero value to this register starts the MM2S transfer.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"S2MM_DMACR": {
|
||||
"address_offset": "0x30",
|
||||
"size": 32,
|
||||
"display_name": "S2MM DMA Control Register",
|
||||
"description": "S2MM DMA Control Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x10002",
|
||||
"fields": {
|
||||
"RS": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 1,
|
||||
"display_name": "Run/Stop Control",
|
||||
"description": "Run / Stop control for controlling running and stopping of the DMA channel.\n 0 - Stop, DMA stops when current (if any) DMA operations are complete. For Scatter / Gather Mode pending commands/transfers are flushed or completed. \n AXI4-Stream outs are potentially terminated early. Descriptors in the update queue are allowed to finish updating to remote memory before engine halt.\n For Direct Register mode pending commands/transfers are flushed or completed. AXI4-Stream outs are potentially terminated. Data integrity on S2MM AXI4 cannot be guaranteed.\n The halted bit in the DMA Status register asserts to 1 when the DMA engine is halted. This bit is cleared by AXI DMA hardware when an error occurs. The CPU can also choose to clear this bit to stop DMA operations.\n 1 - Run, Start DMA operations. The halted bit in the DMA Status register deasserts to 0 when the DMA engine begins operations.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Reset": {
|
||||
"bit_offset": 2,
|
||||
"bit_width": 1,
|
||||
"display_name": "Soft Reset",
|
||||
"description": "Soft reset for resetting the AXI DMA core. Setting this bit to a 1 causes the AXI DMA to be reset. Reset is accomplished gracefully. Pending commands/transfers are flushed or completed.\nAXI4-Stream outs are terminated early, if necessary with associated TLAST. Setting either MM2S_DMACR.Reset = 1 or S2MM_DMACR.Reset = 1 resets the entire AXI DMA engine. After completion of a soft reset, all registers and bits are in the Reset State. 0 - Reset not in progress. Normal operation. 1 - Reset in progress\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Keyhole": {
|
||||
"bit_offset": 3,
|
||||
"bit_width": 1,
|
||||
"display_name": "Keyhole Write",
|
||||
"description": "Keyhole Write. Setting this bit to 1 causes AXI DMA to initiate S2MM writes (AXI4 Writes) in non-incrementing address mode (Fixed Address Burst transfer on AXI4). This bit can be modified when AXI DMA is in idle. When enabling Key hole operation the maximum burst length cannot be more than 16. This bit should not be set when DRE is enabled.\nThis bit is non functional when DMA is used in multichannel mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Cyclic_BD_Enable": {
|
||||
"bit_offset": 4,
|
||||
"bit_width": 1,
|
||||
"display_name": "Cyclic BD Enable",
|
||||
"description": "When set to 1, the DMA operates in Cyclic Buffer Descriptor (BD) mode without any user intervention. In this mode, the Scatter Gather module ignores the Completed bit of the BD. With this bit set, you can use the same BDs in cyclic manner without worrying about any stale descriptor errors.\nThis bit is non functional when DMA operates in Multichannel mode. or in Direct Register Mode\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"IOC_IrqEn": {
|
||||
"bit_offset": 12,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Complete (IOC) Interrupt Enable",
|
||||
"description": "Interrupt on Complete (IOC) Interrupt Enable. When set to 1, allows Interrupt On Complete events to generate an interrupt out for descriptors with the Complete bit set. 0 - IOC Interrupt disabled 1 - IOC Interrupt enabled\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Dly_IrqEn": {
|
||||
"bit_offset": 13,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Delay Timer Interrupt Enable",
|
||||
"description": "Interrupt on Delay Timer Interrupt Enable. When set to 1, allows error events to generate an interrupt out. 0 - Delay Interrupt disabled 1 - Delay Interrupt enabled Note: Applicable only when Scatter Gather is enabled.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Err_IrqEn": {
|
||||
"bit_offset": 14,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Error Interrupt Enable",
|
||||
"description": "Interrupt on Error Interrupt Enable. When set to 1, allows error events to generate an interrupt out. 0 - Error Interrupt disabled 1 - Error Interrupt enabled\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"IRQThreshold": {
|
||||
"bit_offset": 16,
|
||||
"bit_width": 8,
|
||||
"display_name": "Interrupt Threshold",
|
||||
"description": "Interrupt Threshold. This value is used for setting the interrupt threshold. When IOC interrupt events occur, an internal counter counts down from the Interrupt Threshold setting. When the count reaches zero, an interrupt out is generated by the DMA engine.\nNote: The minimum setting for the threshold is 0x01. A write of 0x00 to this register has no effect.\nNote: Applicable only when Scatter Gather is enabled.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"IRQDelay": {
|
||||
"bit_offset": 24,
|
||||
"bit_width": 8,
|
||||
"display_name": "Interrupt Delay Time Out",
|
||||
"description": "Interrupt Delay Time Out. This value is used for setting the interrupt timeout value. The interrupt timeout mechanism causes the DMA engine to generate an interrupt after the delay time period has expired. Timer begins counting at the end of a packet and resets with receipt of a new packet or a timeout event occurs.\nNote: Setting this value to zero disables the delay timer interrupt.\nNote: Applicable only when Scatter Gather is enabled.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"S2MM_DMASR": {
|
||||
"address_offset": "0x34",
|
||||
"size": 32,
|
||||
"display_name": "S2MM DMA Status Register",
|
||||
"description": "S2MM DMA Status Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x10000",
|
||||
"fields": {
|
||||
"Halted": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Channel Halted",
|
||||
"description": "DMA Channel Halted. Indicates the run/stop state of the DMA channel. 0 - DMA channel running. 1 - DMA channel halted. For Scatter/Gather Mode this bit gets set when DMACR.RS = 0 and DMA and SG operations have halted. For Direct Register Mode this bit gets set when DMACR.RS = 0 and DMA operations have halted. There can be a lag of time between when DMACR.RS = 0 and when DMASR.Halted = 1 \nNote: When halted (RS= 0 and Halted = 1), writing to CURDESC_PTR or TAILDESC_PTR pointer registers has no effect on DMA operations when in Scatter Gather Mode. For Direct Register Mode, writing to the LENGTH register has no effect on DMA operations.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"Idle": {
|
||||
"bit_offset": 1,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Channel Idle",
|
||||
"description": "DMA Channel Idle. Indicates the state of AXI DMA operations.\nFor Scatter / Gather Mode when IDLE indicates the SG Engine has reached the tail pointer for the associated channel and all queued descriptors have been processed. Writing to the tail pointer register automatically restarts DMA operations.\nFor Direct Register Mode when IDLE indicates the current transfer has completed. 0 - Not Idle. 1 - Idle. Note: This bit is 0 when channel is halted (DMASR.Halted=1). This bit is also 0 prior to initial transfer when AXI DMA configured for Direct Register Mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"SGIncld": {
|
||||
"bit_offset": 3,
|
||||
"bit_width": 1,
|
||||
"display_name": "SGIncld",
|
||||
"description": "Scatter Gather Engine Included. DMASR.SGIncld = 1 indicates the Scatter Gather engine is included and the AXI DMA is configured for Scatter Gather mode. DMASR.SGIncld = 0 indicates the Scatter Gather engine is excluded and the AXI DMA is configured for Direct Register Mode.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"DMAIntErr": {
|
||||
"bit_offset": 4,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Internal Error",
|
||||
"description": "DMA Internal Error. This error occurs if the buffer length specified in the fetched descriptor is set to 0. Also, when in Scatter Gather Mode and using the status app length field, this error occurs when the Status AXI4-Stream packet RxLength field does not match the S2MM packet being received by the S_AXIS_S2MM interface. When Scatter Gather is disabled, this error is flagged if any error occurs during Memory write or if the incoming packet is bigger than what is specified in the DMA length register.\nThis error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Internal Errors 1 - DMA Internal Error detected.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"DMASlvErr": {
|
||||
"bit_offset": 5,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Slave Error",
|
||||
"description": "DMA Slave Error. This error occurs if the slave read from the Memory Map interface issues a Slave Error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Slave Errors. 1 - DMA Slave Error detected.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"DMADecErr": {
|
||||
"bit_offset": 6,
|
||||
"bit_width": 1,
|
||||
"display_name": "DMA Decode Error",
|
||||
"description": "DMA Decode Error. This error occurs if the address request points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Decode Errors. 1 - DMA Decode Error detected.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"SGIntErr": {
|
||||
"bit_offset": 8,
|
||||
"bit_width": 1,
|
||||
"display_name": "Scatter Gather Internal Error",
|
||||
"description": "Scatter Gather Internal Error. This error occurs if a descriptor with the \"Complete bit\" already set is fetched. This indicates to the SG Engine that the descriptor is a tail descriptor. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Internal Errors. 1 - SG Internal Error detected. Note: Applicable only when Scatter Gather is enabled. \n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"SGSlvErr": {
|
||||
"bit_offset": 9,
|
||||
"bit_width": 1,
|
||||
"display_name": "Scatter Gather Slave Error",
|
||||
"description": "Scatter Gather Slave Error. This error occurs if the slave read from on the Memory Map interface issues a Slave error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Slave Errors. 1 - SG Slave Error detected. DMA Engine halts. Note: Applicable only when Scatter Gather is enabled. \n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"SGDecErr": {
|
||||
"bit_offset": 10,
|
||||
"bit_width": 1,
|
||||
"display_name": "Scatter Gather Decode Error",
|
||||
"description": "Scatter Gather Decode Error. This error occurs if CURDESC_PTR and/or NXTDESC_PTR points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Decode Errors. 1 - SG Decode Error detected. DMA Engine halts. Note: Applicable only when Scatter Gather is enabled. \n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"IOC_Irq": {
|
||||
"bit_offset": 12,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Complete",
|
||||
"description": "Interrupt on Complete. When set to 1 for Scatter/Gather Mode, indicates an interrupt event was generated on completion of a descriptor. This occurs for descriptors with the End of Frame (EOF) bit set. When set to 1 for Direct Register Mode, indicates an interrupt event was generated on completion of a transfer. If the corresponding bit in S2MM_DMACR is enabled (IOC_IrqEn = 1) and if the interrupt threshold has been met, causes an interrupt out to be generated from the AXI DMA. 0 - No IOC Interrupt. 1 - IOC Interrupt detected. Writing a 1 to this bit will clear it.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Dly_Irq": {
|
||||
"bit_offset": 13,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Delay",
|
||||
"description": "Interrupt on Delay. When set to 1, indicates an interrupt event was generated on delay timer time out. If the corresponding bit is enabled in the S2MM_DMACR (Dly_IrqEn = 1), an interrupt out is generated from the AXI DMA. 0 - No Delay Interrupt. 1 - Delay Interrupt detected.1 = IOC Interrupt detected. Writing a 1 to this bit will clear it. Note: Applicable only when Scatter Gather is enabled. \n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"Err_Irq": {
|
||||
"bit_offset": 14,
|
||||
"bit_width": 1,
|
||||
"display_name": "Interrupt on Error",
|
||||
"description": "Interrupt on Error. When set to 1, indicates an interrupt event was generated on error. If the corresponding bit is enabled in the S2MM_DMACR (Err_IrqEn = 1), an interrupt out is generated from the AXI DMA.\nWriting a 1 to this bit will clear it. 0 - No error Interrupt. 1 - Error interrupt detected.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"IRQThresholdSts": {
|
||||
"bit_offset": 16,
|
||||
"bit_width": 8,
|
||||
"display_name": "Interrupt Threshold Status",
|
||||
"description": "Interrupt Threshold Status. Indicates current interrupt threshold value.\nNote: Applicable only when Scatter Gather is enabled.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
},
|
||||
"IRQDelaySts": {
|
||||
"bit_offset": 24,
|
||||
"bit_width": 8,
|
||||
"display_name": "Interrupt Delay Time Status",
|
||||
"description": "Interrupt Delay Time Status. Indicates current interrupt delay time value.\nNote: Applicable only when Scatter Gather is enabled.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-only"
|
||||
}
|
||||
}
|
||||
},
|
||||
"S2MM_DA": {
|
||||
"address_offset": "0x48",
|
||||
"size": 32,
|
||||
"display_name": "S2MM DMA Destination Address Register",
|
||||
"description": "S2MM DMA Destination Address Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"Destination_Address": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 32,
|
||||
"display_name": "Destination Address",
|
||||
"description": "Indicates the destination address the AXI DMA writes to transfer data from AXI4-Stream on S2MM Channel.\nNote: If Data Realignment Engine is included, the Destination Address can be at any byte offset. If Data Realignment Engine is not included, the Destination Address must be S2MM Memory Map data width aligned.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"S2MM_DA_MSB": {
|
||||
"address_offset": "0x4C",
|
||||
"size": 32,
|
||||
"display_name": "S2MM Destination Address Register",
|
||||
"description": "S2MM Destination Address Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"Destination_Address": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 32,
|
||||
"display_name": "Destination Address",
|
||||
"description": "Indicates the MSB 32 bits of the Destination address AXI DMA writes to transfer data from AXI4-Stream on the S2MM Channel.\nNote: If Data Realignment Engine is included, the Destination Address can be at any byte offset. If Data Realignment Engine is not included, the Dstination Address must be S2MM Memory Map data width aligned.\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"S2MM_LENGTH": {
|
||||
"address_offset": "0x58",
|
||||
"size": 32,
|
||||
"display_name": "S2MM DMA Transfer Length Register",
|
||||
"description": "S2MM DMA Transfer Length Register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"Length": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 26,
|
||||
"display_name": "Length",
|
||||
"description": "Indicates the length in bytes of the S2MM buffer available to write receive data from the S2MM channel. Writing a non-zero value to this register enables S2MM channel to receive packet data.\nAt the completion of the S2MM transfer, the number of actual bytes written on the S2MM AXI4 interface is updated to the S2MM_LENGTH register.\nNote: This value must be greater than or equal to the largest expected packet to be received on S2MM AXI4-Stream. Values smaller than the received packet result in undefined behavior. \n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+65
@@ -0,0 +1,65 @@
|
||||
# file: system_top_axi_dma_2_0.xdc
|
||||
# (c) Copyright 2009 - 2023 Advanced Micro Devices, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Advanced Micro Devices, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# AMD, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) AMD shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or AMD had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# AMD products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of AMD products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
## INFO: Level CDC Crossing in AXI DMA
|
||||
|
||||
set_false_path -to [get_pins -hier *cdc_to*/D]
|
||||
|
||||
create_waiver -internal -scope -type CDC -id {CDC-1} -user "axi_dma" -tags "9601"\
|
||||
-desc "The CDC-1 warning is waived as it is safe in the context of AXI DMA. The Address and Data value does not change until AXI transaction is complete." \
|
||||
-to [get_pins -hier -quiet -filter {NAME =~*I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_ASYNC_WRITE.REG_WADDR_TO_IPCLK/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[*].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/D}]
|
||||
|
||||
create_waiver -internal -scope -type CDC -id {CDC-1} -user "axi_dma" -tags "9601"\
|
||||
-desc "The CDC-1 warning is waived as it is safe in the context of AXI DMA. The Address and Data value does not change until AXI transaction is complete." \
|
||||
-to [get_pins -hier -quiet -filter {NAME =~*I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_ASYNC_WRITE.REG_WADDR_TO_IPCLK1/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[*].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/D}]
|
||||
|
||||
# Specific to MultiChannel mode
|
||||
create_waiver -internal -scope -type CDC -id {CDC-1} -user "axi_dma" -tags "9601"\
|
||||
-desc "The CDC-1 warning is waived as it is safe in the context of AXI DMA. In multi channel mode, it is safe to ignore this." \
|
||||
-from [get_pins -hier -quiet -filter {NAME =~*MM2S_SPLIT.I_COMMAND_MM2S_SPLITTER/vsize_data_int_reg[*]/C}]
|
||||
|
||||
|
||||
+8497
File diff suppressed because it is too large
Load Diff
+46
@@ -0,0 +1,46 @@
|
||||
# file: system_top_axi_dma_2_0.xdc
|
||||
# (c) Copyright 2009 - 2023 Advanced Micro Devices, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Advanced Micro Devices, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# AMD, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) AMD shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or AMD had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# AMD products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of AMD products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
+219
@@ -0,0 +1,219 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
|
||||
-- IP Revision: 33
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY axi_gpio_v2_0_33;
|
||||
USE axi_gpio_v2_0_33.axi_gpio;
|
||||
|
||||
ENTITY system_top_axi_gpio_0_0 IS
|
||||
PORT (
|
||||
s_axi_aclk : IN STD_LOGIC;
|
||||
s_axi_aresetn : IN STD_LOGIC;
|
||||
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_awvalid : IN STD_LOGIC;
|
||||
s_axi_awready : OUT STD_LOGIC;
|
||||
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_wvalid : IN STD_LOGIC;
|
||||
s_axi_wready : OUT STD_LOGIC;
|
||||
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_bvalid : OUT STD_LOGIC;
|
||||
s_axi_bready : IN STD_LOGIC;
|
||||
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_arvalid : IN STD_LOGIC;
|
||||
s_axi_arready : OUT STD_LOGIC;
|
||||
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_rvalid : OUT STD_LOGIC;
|
||||
s_axi_rready : IN STD_LOGIC;
|
||||
ip2intc_irpt : OUT STD_LOGIC;
|
||||
gpio_io_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
gpio_io_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
gpio_io_t : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
|
||||
);
|
||||
END system_top_axi_gpio_0_0;
|
||||
|
||||
ARCHITECTURE system_top_axi_gpio_0_0_arch OF system_top_axi_gpio_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_top_axi_gpio_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axi_gpio IS
|
||||
GENERIC (
|
||||
C_FAMILY : STRING;
|
||||
C_S_AXI_ADDR_WIDTH : INTEGER;
|
||||
C_S_AXI_DATA_WIDTH : INTEGER;
|
||||
C_GPIO_WIDTH : INTEGER;
|
||||
C_GPIO2_WIDTH : INTEGER;
|
||||
C_ALL_INPUTS : INTEGER;
|
||||
C_ALL_INPUTS_2 : INTEGER;
|
||||
C_ALL_OUTPUTS : INTEGER;
|
||||
C_ALL_OUTPUTS_2 : INTEGER;
|
||||
C_INTERRUPT_PRESENT : INTEGER;
|
||||
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
C_IS_DUAL : INTEGER;
|
||||
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
PORT (
|
||||
s_axi_aclk : IN STD_LOGIC;
|
||||
s_axi_aresetn : IN STD_LOGIC;
|
||||
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_awvalid : IN STD_LOGIC;
|
||||
s_axi_awready : OUT STD_LOGIC;
|
||||
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_wvalid : IN STD_LOGIC;
|
||||
s_axi_wready : OUT STD_LOGIC;
|
||||
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_bvalid : OUT STD_LOGIC;
|
||||
s_axi_bready : IN STD_LOGIC;
|
||||
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_arvalid : IN STD_LOGIC;
|
||||
s_axi_arready : OUT STD_LOGIC;
|
||||
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_rvalid : OUT STD_LOGIC;
|
||||
s_axi_rready : IN STD_LOGIC;
|
||||
ip2intc_irpt : OUT STD_LOGIC;
|
||||
gpio_io_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
gpio_io_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
gpio_io_t : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT axi_gpio;
|
||||
ATTRIBUTE X_CORE_INFO : STRING;
|
||||
ATTRIBUTE X_CORE_INFO OF system_top_axi_gpio_0_0_arch: ARCHITECTURE IS "axi_gpio,Vivado 2024.1";
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE OF system_top_axi_gpio_0_0_arch : ARCHITECTURE IS "system_top_axi_gpio_0_0,axi_gpio,{}";
|
||||
ATTRIBUTE CORE_GENERATION_INFO : STRING;
|
||||
ATTRIBUTE CORE_GENERATION_INFO OF system_top_axi_gpio_0_0_arch: ARCHITECTURE IS "system_top_axi_gpio_0_0,axi_gpio,{x_ipProduct=Vivado 2024.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_gpio,x_ipVersion=2.0,x_ipCoreRevision=33,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_S_AXI_ADDR_WIDTH=9,C_S_AXI_DATA_WIDTH=32,C_GPIO_WIDTH=1,C_GPIO2_WIDTH=32,C_ALL_INPUTS=0,C_ALL_INPUTS_2=0,C_ALL_OUTPUTS=0,C_ALL_OUTPUTS_2=0,C_INTERRUPT_PRESENT=1,C_DOUT_DEFAULT=0x00000000,C_TRI_DEFAULT=0xFFFFFFFF,C_IS_DUAL=0,C_DOUT_DEFAULT_2=0x00000000,C_TRI_DEFAULT_2=0xFFFFFFFF}";
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF gpio_io_i: SIGNAL IS "XIL_INTERFACENAME GPIO, BOARD.ASSOCIATED_PARAM GPIO_BOARD_INTERFACE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_t: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_T";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF ip2intc_irpt: SIGNAL IS "XIL_INTERFACENAME IP2INTC_IRQ, SENSITIVITY LEVEL_HIGH, PortWidth 1";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF ip2intc_irpt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 IP2INTC_IRQ INTERRUPT";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aclk: SIGNAL IS "XIL_INTERFACENAME S_AXI_ACLK, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 1e+08, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN system_top_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME S_AXI_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 9, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN system_top_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1" &
|
||||
", NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
|
||||
BEGIN
|
||||
U0 : axi_gpio
|
||||
GENERIC MAP (
|
||||
C_FAMILY => "zynq",
|
||||
C_S_AXI_ADDR_WIDTH => 9,
|
||||
C_S_AXI_DATA_WIDTH => 32,
|
||||
C_GPIO_WIDTH => 1,
|
||||
C_GPIO2_WIDTH => 32,
|
||||
C_ALL_INPUTS => 0,
|
||||
C_ALL_INPUTS_2 => 0,
|
||||
C_ALL_OUTPUTS => 0,
|
||||
C_ALL_OUTPUTS_2 => 0,
|
||||
C_INTERRUPT_PRESENT => 1,
|
||||
C_DOUT_DEFAULT => X"00000000",
|
||||
C_TRI_DEFAULT => X"FFFFFFFF",
|
||||
C_IS_DUAL => 0,
|
||||
C_DOUT_DEFAULT_2 => X"00000000",
|
||||
C_TRI_DEFAULT_2 => X"FFFFFFFF"
|
||||
)
|
||||
PORT MAP (
|
||||
s_axi_aclk => s_axi_aclk,
|
||||
s_axi_aresetn => s_axi_aresetn,
|
||||
s_axi_awaddr => s_axi_awaddr,
|
||||
s_axi_awvalid => s_axi_awvalid,
|
||||
s_axi_awready => s_axi_awready,
|
||||
s_axi_wdata => s_axi_wdata,
|
||||
s_axi_wstrb => s_axi_wstrb,
|
||||
s_axi_wvalid => s_axi_wvalid,
|
||||
s_axi_wready => s_axi_wready,
|
||||
s_axi_bresp => s_axi_bresp,
|
||||
s_axi_bvalid => s_axi_bvalid,
|
||||
s_axi_bready => s_axi_bready,
|
||||
s_axi_araddr => s_axi_araddr,
|
||||
s_axi_arvalid => s_axi_arvalid,
|
||||
s_axi_arready => s_axi_arready,
|
||||
s_axi_rdata => s_axi_rdata,
|
||||
s_axi_rresp => s_axi_rresp,
|
||||
s_axi_rvalid => s_axi_rvalid,
|
||||
s_axi_rready => s_axi_rready,
|
||||
ip2intc_irpt => ip2intc_irpt,
|
||||
gpio_io_i => gpio_io_i,
|
||||
gpio_io_o => gpio_io_o,
|
||||
gpio_io_t => gpio_io_t,
|
||||
gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
|
||||
);
|
||||
END system_top_axi_gpio_0_0_arch;
|
||||
+380
@@ -0,0 +1,380 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "system_top_axi_gpio_0_0",
|
||||
"cell_name": "axi_gpio_0",
|
||||
"component_reference": "xilinx.com:ip:axi_gpio:2.0",
|
||||
"ip_revision": "33",
|
||||
"gen_directory": ".",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"C_TRI_DEFAULT": [ { "value": "0xFFFFFFFF", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||
"C_GPIO_WIDTH": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_GPIO2_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_IS_DUAL": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_ALL_INPUTS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_TRI_DEFAULT_2": [ { "value": "0xFFFFFFFF", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||
"C_DOUT_DEFAULT_2": [ { "value": "0x00000000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||
"C_DOUT_DEFAULT": [ { "value": "0x00000000", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||
"C_ALL_INPUTS_2": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_INTERRUPT_PRESENT": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "system_top_axi_gpio_0_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"USE_BOARD_FLOW": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"GPIO_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
|
||||
"GPIO2_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
|
||||
"C_ALL_OUTPUTS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_ALL_OUTPUTS_2": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_FAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_S_AXI_ADDR_WIDTH": [ { "value": "9", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_DATA_WIDTH": [ { "value": "32", "format": "long", "usage": "all" } ],
|
||||
"C_GPIO_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_GPIO2_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ALL_INPUTS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ALL_INPUTS_2": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ALL_OUTPUTS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ALL_OUTPUTS_2": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INTERRUPT_PRESENT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DOUT_DEFAULT": [ { "value": "0x00000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_TRI_DEFAULT": [ { "value": "0xFFFFFFFF", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_IS_DUAL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DOUT_DEFAULT_2": [ { "value": "0x00000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_TRI_DEFAULT_2": [ { "value": "0xFFFFFFFF", "resolve_type": "generated", "format": "bitString", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "xilinx.com:zc706:part0:1.4" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z045" } ],
|
||||
"NEXTGEN_VERSAL": [ { "value": "0" } ],
|
||||
"PACKAGE": [ { "value": "ffg900" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "33" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "." } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2024.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"s_axi_aclk": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_aresetn": [ { "direction": "in", "driver_value": "1" } ],
|
||||
"s_axi_awaddr": [ { "direction": "in", "size_left": "8", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_awvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_awready": [ { "direction": "out" } ],
|
||||
"s_axi_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_wvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_wready": [ { "direction": "out" } ],
|
||||
"s_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s_axi_bvalid": [ { "direction": "out" } ],
|
||||
"s_axi_bready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_araddr": [ { "direction": "in", "size_left": "8", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_arvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_arready": [ { "direction": "out" } ],
|
||||
"s_axi_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"s_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s_axi_rvalid": [ { "direction": "out" } ],
|
||||
"s_axi_rready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"ip2intc_irpt": [ { "direction": "out" } ],
|
||||
"gpio_io_i": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"gpio_io_o": [ { "direction": "out", "size_left": "0", "size_right": "0" } ],
|
||||
"gpio_io_t": [ { "direction": "out", "size_left": "0", "size_right": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"S_AXI": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"memory_map_ref": "S_AXI",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "1e+08", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "9", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"ARADDR": [ { "physical_name": "s_axi_araddr" } ],
|
||||
"ARREADY": [ { "physical_name": "s_axi_arready" } ],
|
||||
"ARVALID": [ { "physical_name": "s_axi_arvalid" } ],
|
||||
"AWADDR": [ { "physical_name": "s_axi_awaddr" } ],
|
||||
"AWREADY": [ { "physical_name": "s_axi_awready" } ],
|
||||
"AWVALID": [ { "physical_name": "s_axi_awvalid" } ],
|
||||
"BREADY": [ { "physical_name": "s_axi_bready" } ],
|
||||
"BRESP": [ { "physical_name": "s_axi_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "s_axi_bvalid" } ],
|
||||
"RDATA": [ { "physical_name": "s_axi_rdata" } ],
|
||||
"RREADY": [ { "physical_name": "s_axi_rready" } ],
|
||||
"RRESP": [ { "physical_name": "s_axi_rresp" } ],
|
||||
"RVALID": [ { "physical_name": "s_axi_rvalid" } ],
|
||||
"WDATA": [ { "physical_name": "s_axi_wdata" } ],
|
||||
"WREADY": [ { "physical_name": "s_axi_wready" } ],
|
||||
"WSTRB": [ { "physical_name": "s_axi_wstrb" } ],
|
||||
"WVALID": [ { "physical_name": "s_axi_wvalid" } ]
|
||||
}
|
||||
},
|
||||
"S_AXI_ACLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S_AXI", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "s_axi_aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "1e+08", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "s_axi_aclk" } ]
|
||||
}
|
||||
},
|
||||
"S_AXI_ARESETN": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "s_axi_aresetn" } ]
|
||||
}
|
||||
},
|
||||
"IP2INTC_IRQ": {
|
||||
"vlnv": "xilinx.com:signal:interrupt:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"SENSITIVITY": [ { "value": "LEVEL_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"PortWidth": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"INTERRUPT": [ { "physical_name": "ip2intc_irpt" } ]
|
||||
}
|
||||
},
|
||||
"GPIO": {
|
||||
"vlnv": "xilinx.com:interface:gpio:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:gpio_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"BOARD.ASSOCIATED_PARAM": [ { "value": "GPIO_BOARD_INTERFACE", "value_src": "constant", "value_permission": "bd", "usage": "all" } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TRI_I": [ { "physical_name": "gpio_io_i" } ],
|
||||
"TRI_O": [ { "physical_name": "gpio_io_o" } ],
|
||||
"TRI_T": [ { "physical_name": "gpio_io_t" } ]
|
||||
}
|
||||
}
|
||||
},
|
||||
"memory_maps": {
|
||||
"S_AXI": {
|
||||
"display_name": "S_AXI_MEM",
|
||||
"description": "Memory Map for S_AXI",
|
||||
"address_blocks": {
|
||||
"Reg": {
|
||||
"base_address": "0",
|
||||
"range": "4096",
|
||||
"display_name": "Reg",
|
||||
"description": "Register Block",
|
||||
"usage": "register",
|
||||
"access": "read-write",
|
||||
"registers": {
|
||||
"GPIO_DATA": {
|
||||
"address_offset": "0x0",
|
||||
"size": 1,
|
||||
"display_name": "Channel_1_GPIO_DATA",
|
||||
"description": "Channel-1 AXI GPIO Data register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"CH1_DATA": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 1,
|
||||
"display_name": "Channel_1_GPIO_DATA",
|
||||
"description": "AXI GPIO Data Register.\nFor each I/O bit programmed as input\n R - Reads value on the input pin.\n W - No effect.\nFor each I/O bit programmed as output\n R - Reads value on GPIO_O pins\n W - Writes value to the corresponding AXI GPIO \n data register bit and output pin\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"GPIO_TRI": {
|
||||
"address_offset": "0x4",
|
||||
"size": 1,
|
||||
"display_name": "Channel_1_GPIO_TRI",
|
||||
"description": "Channel-1 AXI GPIO 3-State Control register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"CH1_TRI": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 1,
|
||||
"display_name": "Channel_1_GPIO_DATA",
|
||||
"description": "AXI GPIO 3-State Control Register\nEach I/O pin of the AXI GPIO is individually programmable as an input or output For each of the bits 0 - I/O pin configured as output 1 - I/O pin configured as input\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"GPIO2_DATA": {
|
||||
"address_offset": "0x8",
|
||||
"size": 32,
|
||||
"display_name": "Channel_2_GPIO_DATA",
|
||||
"description": "Channel-2 AXI GPIO Data register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"CH2_DATA": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 32,
|
||||
"display_name": "Channel_2_GPIO_DATA",
|
||||
"description": "AXI GPIO Data Register.\nFor each I/O bit programmed as input\n R - Reads value on the input pin.\n W - No effect.\nFor each I/O bit programmed as output\n R - Reads value on GPIO_O pins\n W - Writes value to the corresponding AXI GPIO \n data register bit and output pin\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"GPIO2_TRI": {
|
||||
"address_offset": "0xC",
|
||||
"size": 32,
|
||||
"display_name": "Channel_2_GPIO_TRI",
|
||||
"description": "Channel-2 AXI GPIO 3-State Control register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"CH2_TRI": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 32,
|
||||
"display_name": "Channel_2_GPIO_DATA",
|
||||
"description": "AXI GPIO 3-State Control Register\nEach I/O pin of the AXI GPIO is individually programmable as an input or output For each of the bits 0 - I/O pin configured as output 1 - I/O pin configured as input\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"GIER": {
|
||||
"address_offset": "0x11C",
|
||||
"size": 32,
|
||||
"display_name": "Global_Interrupt_Enable register",
|
||||
"description": "Global_Interrupt_Enable register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"INT_EN": {
|
||||
"bit_offset": 31,
|
||||
"bit_width": 1,
|
||||
"display_name": "Global_Interrupt_Enable",
|
||||
"description": "Master enable for the device interrupt output\n 0 - Disabled\n 1 - Enabled\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"IP_IER": {
|
||||
"address_offset": "0x128",
|
||||
"size": 32,
|
||||
"display_name": "IP Interrupt Enable register",
|
||||
"description": "IP Interrupt Enable register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"CH1_INT_EN": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 1,
|
||||
"display_name": "Channel_1_Interrupt_Enable",
|
||||
"description": "Enable Channel 1 Interrupt\n 0 - Disabled (masked)\n 1 - Enabled\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"CH2_INT_EN": {
|
||||
"bit_offset": 1,
|
||||
"bit_width": 1,
|
||||
"display_name": "Channel_2_Interrupt_Enable",
|
||||
"description": "Enable Channel 2 Interrupt\n 0 - Disabled (masked)\n 1 - Enabled\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"IP_ISR": {
|
||||
"address_offset": "0x120",
|
||||
"size": 32,
|
||||
"display_name": "IP Interrupt Status register",
|
||||
"description": "IP Interrupt Status register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"CH1_INT_S": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 1,
|
||||
"display_name": "Channel_1_Interrupt_Status",
|
||||
"description": "Channel 1 Interrupt Status\n 0 - No Channel 1 input interrupt\n 1 - Channel 1 input interrupt\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
},
|
||||
"CH2_INT_S": {
|
||||
"bit_offset": 1,
|
||||
"bit_width": 1,
|
||||
"display_name": "Channel_2_Interrupt_Status",
|
||||
"description": "Channel 2 Interrupt Status\n 0 - No Channel 2 input interrupt\n 1 - Channel 2 input interrupt\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+48
@@ -0,0 +1,48 @@
|
||||
# (c) Copyright 2009 - 2013, 2023 Advanced Micro Devices Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Advanced Micro Devices, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# AMD, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) AMD shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or AMD had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# AMD products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of AMD products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
set_false_path -to [get_pins -hier *cdc_to*/D]
|
||||
|
||||
+1922
File diff suppressed because it is too large
Load Diff
+2
@@ -0,0 +1,2 @@
|
||||
#--------------------Physical Constraints-----------------
|
||||
|
||||
+62
@@ -0,0 +1,62 @@
|
||||
|
||||
################################################################################
|
||||
# (c) Copyright 2012 - 2013, 2023 Advanced Micro Devices, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Advanced Micro Devices, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# AMD, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) AMD shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or AMD had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# AMD products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of AMD products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
################################################################################
|
||||
|
||||
# This XDC is used only for OOC mode of synthesis, implementation
|
||||
# User should update the correct clock period before proceeding further
|
||||
# This constraints file contains default clock frequencies to be used during
|
||||
# out-of-context flows such as OOC Synthesis and Hierarchical Designs.
|
||||
# For best results the frequencies should be modified# to match the target
|
||||
# frequencies.
|
||||
|
||||
|
||||
create_clock -name s_axi_clk -period 10 [get_ports s_axi_aclk]
|
||||
## set_property HD.CLK_SRC BUFGCTRL_X0Y0 [get_ports s_axi_aclk]
|
||||
|
||||
################################################################################
|
||||
+7344
File diff suppressed because it is too large
Load Diff
+433
@@ -0,0 +1,433 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<Root MajorVersion="0" MinorVersion="43">
|
||||
<CompositeFile CompositeFileTopName="bd_222a" CanBeSetAsTop="true" CanDisplayChildGraph="true">
|
||||
<Description>Composite Fileset</Description>
|
||||
<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1730345378"/>
|
||||
<Generation Name="SIMULATION" State="STALE" Timestamp="1730345376"/>
|
||||
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1730345378"/>
|
||||
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1730345378"/>
|
||||
<FileCollection Name="SOURCES" Type="SOURCES">
|
||||
<File Name="ip/ip_0/bd_222a_one_0.xci" Type="IP">
|
||||
<Instance HierarchyPath="clk_map/one"/>
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="ip/ip_1/bd_222a_psr_aclk_0.xci" Type="IP">
|
||||
<Instance HierarchyPath="clk_map/psr_aclk"/>
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="ip/ip_2/bd_222a_arsw_0.xci" Type="IP">
|
||||
<Instance HierarchyPath="switchboards/ar_switchboard"/>
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="ip/ip_3/bd_222a_rsw_0.xci" Type="IP">
|
||||
<Instance HierarchyPath="switchboards/r_switchboard"/>
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="ip/ip_4/bd_222a_awsw_0.xci" Type="IP">
|
||||
<Instance HierarchyPath="switchboards/aw_switchboard"/>
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="ip/ip_5/bd_222a_wsw_0.xci" Type="IP">
|
||||
<Instance HierarchyPath="switchboards/w_switchboard"/>
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="ip/ip_6/bd_222a_bsw_0.xci" Type="IP">
|
||||
<Instance HierarchyPath="switchboards/b_switchboard"/>
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="ip/ip_7/bd_222a_s00mmu_0.xci" Type="IP">
|
||||
<Instance HierarchyPath="s00_entry_pipeline/s00_mmu"/>
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="ip/ip_8/bd_222a_s00tr_0.xci" Type="IP">
|
||||
<Instance HierarchyPath="s00_entry_pipeline/s00_transaction_regulator"/>
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="ip/ip_9/bd_222a_s00sic_0.xci" Type="IP">
|
||||
<Instance HierarchyPath="s00_entry_pipeline/s00_si_converter"/>
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="ip/ip_10/bd_222a_s00a2s_0.xci" Type="IP">
|
||||
<Instance HierarchyPath="s00_axi2sc"/>
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="ip/ip_11/bd_222a_sarn_0.xci" Type="IP">
|
||||
<Instance HierarchyPath="s00_nodes/s00_ar_node"/>
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="ip/ip_12/bd_222a_srn_0.xci" Type="IP">
|
||||
<Instance HierarchyPath="s00_nodes/s00_r_node"/>
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="ip/ip_13/bd_222a_sawn_0.xci" Type="IP">
|
||||
<Instance HierarchyPath="s00_nodes/s00_aw_node"/>
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="ip/ip_14/bd_222a_swn_0.xci" Type="IP">
|
||||
<Instance HierarchyPath="s00_nodes/s00_w_node"/>
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="ip/ip_15/bd_222a_sbn_0.xci" Type="IP">
|
||||
<Instance HierarchyPath="s00_nodes/s00_b_node"/>
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="ip/ip_16/bd_222a_s01mmu_0.xci" Type="IP">
|
||||
<Instance HierarchyPath="s01_entry_pipeline/s01_mmu"/>
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="ip/ip_17/bd_222a_s01tr_0.xci" Type="IP">
|
||||
<Instance HierarchyPath="s01_entry_pipeline/s01_transaction_regulator"/>
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="ip/ip_18/bd_222a_s01sic_0.xci" Type="IP">
|
||||
<Instance HierarchyPath="s01_entry_pipeline/s01_si_converter"/>
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="ip/ip_19/bd_222a_s01a2s_0.xci" Type="IP">
|
||||
<Instance HierarchyPath="s01_axi2sc"/>
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="ip/ip_20/bd_222a_sawn_1.xci" Type="IP">
|
||||
<Instance HierarchyPath="s01_nodes/s01_aw_node"/>
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="ip/ip_21/bd_222a_swn_1.xci" Type="IP">
|
||||
<Instance HierarchyPath="s01_nodes/s01_w_node"/>
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="ip/ip_22/bd_222a_sbn_1.xci" Type="IP">
|
||||
<Instance HierarchyPath="s01_nodes/s01_b_node"/>
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="ip/ip_23/bd_222a_s02mmu_0.xci" Type="IP">
|
||||
<Instance HierarchyPath="s02_entry_pipeline/s02_mmu"/>
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="ip/ip_24/bd_222a_s02tr_0.xci" Type="IP">
|
||||
<Instance HierarchyPath="s02_entry_pipeline/s02_transaction_regulator"/>
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="ip/ip_25/bd_222a_s02sic_0.xci" Type="IP">
|
||||
<Instance HierarchyPath="s02_entry_pipeline/s02_si_converter"/>
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="ip/ip_26/bd_222a_s02a2s_0.xci" Type="IP">
|
||||
<Instance HierarchyPath="s02_axi2sc"/>
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="ip/ip_27/bd_222a_sawn_2.xci" Type="IP">
|
||||
<Instance HierarchyPath="s02_nodes/s02_aw_node"/>
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="ip/ip_28/bd_222a_swn_2.xci" Type="IP">
|
||||
<Instance HierarchyPath="s02_nodes/s02_w_node"/>
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="ip/ip_29/bd_222a_sbn_2.xci" Type="IP">
|
||||
<Instance HierarchyPath="s02_nodes/s02_b_node"/>
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="ip/ip_30/bd_222a_s03mmu_0.xci" Type="IP">
|
||||
<Instance HierarchyPath="s03_entry_pipeline/s03_mmu"/>
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="ip/ip_31/bd_222a_s03tr_0.xci" Type="IP">
|
||||
<Instance HierarchyPath="s03_entry_pipeline/s03_transaction_regulator"/>
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="ip/ip_32/bd_222a_s03sic_0.xci" Type="IP">
|
||||
<Instance HierarchyPath="s03_entry_pipeline/s03_si_converter"/>
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="ip/ip_33/bd_222a_s03a2s_0.xci" Type="IP">
|
||||
<Instance HierarchyPath="s03_axi2sc"/>
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="ip/ip_34/bd_222a_sawn_3.xci" Type="IP">
|
||||
<Instance HierarchyPath="s03_nodes/s03_aw_node"/>
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="ip/ip_35/bd_222a_swn_3.xci" Type="IP">
|
||||
<Instance HierarchyPath="s03_nodes/s03_w_node"/>
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="ip/ip_36/bd_222a_sbn_3.xci" Type="IP">
|
||||
<Instance HierarchyPath="s03_nodes/s03_b_node"/>
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="ip/ip_37/bd_222a_m00s2a_0.xci" Type="IP">
|
||||
<Instance HierarchyPath="m00_sc2axi"/>
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="ip/ip_38/bd_222a_m00arn_0.xci" Type="IP">
|
||||
<Instance HierarchyPath="m00_nodes/m00_ar_node"/>
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="ip/ip_39/bd_222a_m00rn_0.xci" Type="IP">
|
||||
<Instance HierarchyPath="m00_nodes/m00_r_node"/>
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="ip/ip_40/bd_222a_m00awn_0.xci" Type="IP">
|
||||
<Instance HierarchyPath="m00_nodes/m00_aw_node"/>
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="ip/ip_41/bd_222a_m00wn_0.xci" Type="IP">
|
||||
<Instance HierarchyPath="m00_nodes/m00_w_node"/>
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="ip/ip_42/bd_222a_m00bn_0.xci" Type="IP">
|
||||
<Instance HierarchyPath="m00_nodes/m00_b_node"/>
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="ip/ip_43/bd_222a_m00e_0.xci" Type="IP">
|
||||
<Instance HierarchyPath="m00_exit_pipeline/m00_exit"/>
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="synth/bd_222a.v" Type="Verilog">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="sim/bd_222a.v" Type="Verilog">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="hw_handoff/system_top_axi_smc1_0.hwh" Type="HwHandoff">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="synth/system_top_axi_smc1_0.hwdef">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
</FileCollection>
|
||||
</CompositeFile>
|
||||
</Root>
|
||||
+522
@@ -0,0 +1,522 @@
|
||||
//Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
//Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
//--------------------------------------------------------------------------------
|
||||
//Command: generate_target bd_222a_wrapper.bd
|
||||
//Design : bd_222a_wrapper
|
||||
//Purpose: IP block netlist
|
||||
//--------------------------------------------------------------------------------
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module bd_222a_wrapper
|
||||
(M00_AXI_araddr,
|
||||
M00_AXI_arburst,
|
||||
M00_AXI_arcache,
|
||||
M00_AXI_arlen,
|
||||
M00_AXI_arlock,
|
||||
M00_AXI_arprot,
|
||||
M00_AXI_arqos,
|
||||
M00_AXI_arready,
|
||||
M00_AXI_arsize,
|
||||
M00_AXI_arvalid,
|
||||
M00_AXI_awaddr,
|
||||
M00_AXI_awburst,
|
||||
M00_AXI_awcache,
|
||||
M00_AXI_awlen,
|
||||
M00_AXI_awlock,
|
||||
M00_AXI_awprot,
|
||||
M00_AXI_awqos,
|
||||
M00_AXI_awready,
|
||||
M00_AXI_awsize,
|
||||
M00_AXI_awvalid,
|
||||
M00_AXI_bready,
|
||||
M00_AXI_bresp,
|
||||
M00_AXI_bvalid,
|
||||
M00_AXI_rdata,
|
||||
M00_AXI_rlast,
|
||||
M00_AXI_rready,
|
||||
M00_AXI_rresp,
|
||||
M00_AXI_rvalid,
|
||||
M00_AXI_wdata,
|
||||
M00_AXI_wlast,
|
||||
M00_AXI_wready,
|
||||
M00_AXI_wstrb,
|
||||
M00_AXI_wvalid,
|
||||
S00_AXI_araddr,
|
||||
S00_AXI_arburst,
|
||||
S00_AXI_arcache,
|
||||
S00_AXI_arid,
|
||||
S00_AXI_arlen,
|
||||
S00_AXI_arlock,
|
||||
S00_AXI_arprot,
|
||||
S00_AXI_arqos,
|
||||
S00_AXI_arready,
|
||||
S00_AXI_arsize,
|
||||
S00_AXI_arvalid,
|
||||
S00_AXI_awaddr,
|
||||
S00_AXI_awburst,
|
||||
S00_AXI_awcache,
|
||||
S00_AXI_awid,
|
||||
S00_AXI_awlen,
|
||||
S00_AXI_awlock,
|
||||
S00_AXI_awprot,
|
||||
S00_AXI_awqos,
|
||||
S00_AXI_awready,
|
||||
S00_AXI_awsize,
|
||||
S00_AXI_awvalid,
|
||||
S00_AXI_bid,
|
||||
S00_AXI_bready,
|
||||
S00_AXI_bresp,
|
||||
S00_AXI_bvalid,
|
||||
S00_AXI_rdata,
|
||||
S00_AXI_rid,
|
||||
S00_AXI_rlast,
|
||||
S00_AXI_rready,
|
||||
S00_AXI_rresp,
|
||||
S00_AXI_rvalid,
|
||||
S00_AXI_wdata,
|
||||
S00_AXI_wid,
|
||||
S00_AXI_wlast,
|
||||
S00_AXI_wready,
|
||||
S00_AXI_wstrb,
|
||||
S00_AXI_wvalid,
|
||||
S01_AXI_awaddr,
|
||||
S01_AXI_awburst,
|
||||
S01_AXI_awcache,
|
||||
S01_AXI_awlen,
|
||||
S01_AXI_awlock,
|
||||
S01_AXI_awprot,
|
||||
S01_AXI_awqos,
|
||||
S01_AXI_awready,
|
||||
S01_AXI_awsize,
|
||||
S01_AXI_awvalid,
|
||||
S01_AXI_bready,
|
||||
S01_AXI_bresp,
|
||||
S01_AXI_bvalid,
|
||||
S01_AXI_wdata,
|
||||
S01_AXI_wlast,
|
||||
S01_AXI_wready,
|
||||
S01_AXI_wstrb,
|
||||
S01_AXI_wvalid,
|
||||
S02_AXI_awaddr,
|
||||
S02_AXI_awburst,
|
||||
S02_AXI_awcache,
|
||||
S02_AXI_awlen,
|
||||
S02_AXI_awlock,
|
||||
S02_AXI_awprot,
|
||||
S02_AXI_awqos,
|
||||
S02_AXI_awready,
|
||||
S02_AXI_awsize,
|
||||
S02_AXI_awvalid,
|
||||
S02_AXI_bready,
|
||||
S02_AXI_bresp,
|
||||
S02_AXI_bvalid,
|
||||
S02_AXI_wdata,
|
||||
S02_AXI_wlast,
|
||||
S02_AXI_wready,
|
||||
S02_AXI_wstrb,
|
||||
S02_AXI_wvalid,
|
||||
S03_AXI_awaddr,
|
||||
S03_AXI_awburst,
|
||||
S03_AXI_awcache,
|
||||
S03_AXI_awlen,
|
||||
S03_AXI_awlock,
|
||||
S03_AXI_awprot,
|
||||
S03_AXI_awqos,
|
||||
S03_AXI_awready,
|
||||
S03_AXI_awsize,
|
||||
S03_AXI_awvalid,
|
||||
S03_AXI_bready,
|
||||
S03_AXI_bresp,
|
||||
S03_AXI_bvalid,
|
||||
S03_AXI_wdata,
|
||||
S03_AXI_wlast,
|
||||
S03_AXI_wready,
|
||||
S03_AXI_wstrb,
|
||||
S03_AXI_wvalid,
|
||||
aclk,
|
||||
aresetn);
|
||||
output [31:0]M00_AXI_araddr;
|
||||
output [1:0]M00_AXI_arburst;
|
||||
output [3:0]M00_AXI_arcache;
|
||||
output [7:0]M00_AXI_arlen;
|
||||
output [0:0]M00_AXI_arlock;
|
||||
output [2:0]M00_AXI_arprot;
|
||||
output [3:0]M00_AXI_arqos;
|
||||
input M00_AXI_arready;
|
||||
output [2:0]M00_AXI_arsize;
|
||||
output M00_AXI_arvalid;
|
||||
output [31:0]M00_AXI_awaddr;
|
||||
output [1:0]M00_AXI_awburst;
|
||||
output [3:0]M00_AXI_awcache;
|
||||
output [7:0]M00_AXI_awlen;
|
||||
output [0:0]M00_AXI_awlock;
|
||||
output [2:0]M00_AXI_awprot;
|
||||
output [3:0]M00_AXI_awqos;
|
||||
input M00_AXI_awready;
|
||||
output [2:0]M00_AXI_awsize;
|
||||
output M00_AXI_awvalid;
|
||||
output M00_AXI_bready;
|
||||
input [1:0]M00_AXI_bresp;
|
||||
input M00_AXI_bvalid;
|
||||
input [511:0]M00_AXI_rdata;
|
||||
input M00_AXI_rlast;
|
||||
output M00_AXI_rready;
|
||||
input [1:0]M00_AXI_rresp;
|
||||
input M00_AXI_rvalid;
|
||||
output [511:0]M00_AXI_wdata;
|
||||
output M00_AXI_wlast;
|
||||
input M00_AXI_wready;
|
||||
output [63:0]M00_AXI_wstrb;
|
||||
output M00_AXI_wvalid;
|
||||
input [31:0]S00_AXI_araddr;
|
||||
input [1:0]S00_AXI_arburst;
|
||||
input [3:0]S00_AXI_arcache;
|
||||
input [11:0]S00_AXI_arid;
|
||||
input [3:0]S00_AXI_arlen;
|
||||
input [1:0]S00_AXI_arlock;
|
||||
input [2:0]S00_AXI_arprot;
|
||||
input [3:0]S00_AXI_arqos;
|
||||
output S00_AXI_arready;
|
||||
input [2:0]S00_AXI_arsize;
|
||||
input S00_AXI_arvalid;
|
||||
input [31:0]S00_AXI_awaddr;
|
||||
input [1:0]S00_AXI_awburst;
|
||||
input [3:0]S00_AXI_awcache;
|
||||
input [11:0]S00_AXI_awid;
|
||||
input [3:0]S00_AXI_awlen;
|
||||
input [1:0]S00_AXI_awlock;
|
||||
input [2:0]S00_AXI_awprot;
|
||||
input [3:0]S00_AXI_awqos;
|
||||
output S00_AXI_awready;
|
||||
input [2:0]S00_AXI_awsize;
|
||||
input S00_AXI_awvalid;
|
||||
output [11:0]S00_AXI_bid;
|
||||
input S00_AXI_bready;
|
||||
output [1:0]S00_AXI_bresp;
|
||||
output S00_AXI_bvalid;
|
||||
output [31:0]S00_AXI_rdata;
|
||||
output [11:0]S00_AXI_rid;
|
||||
output S00_AXI_rlast;
|
||||
input S00_AXI_rready;
|
||||
output [1:0]S00_AXI_rresp;
|
||||
output S00_AXI_rvalid;
|
||||
input [31:0]S00_AXI_wdata;
|
||||
input [11:0]S00_AXI_wid;
|
||||
input S00_AXI_wlast;
|
||||
output S00_AXI_wready;
|
||||
input [3:0]S00_AXI_wstrb;
|
||||
input S00_AXI_wvalid;
|
||||
input [39:0]S01_AXI_awaddr;
|
||||
input [1:0]S01_AXI_awburst;
|
||||
input [3:0]S01_AXI_awcache;
|
||||
input [7:0]S01_AXI_awlen;
|
||||
input [0:0]S01_AXI_awlock;
|
||||
input [2:0]S01_AXI_awprot;
|
||||
input [3:0]S01_AXI_awqos;
|
||||
output S01_AXI_awready;
|
||||
input [2:0]S01_AXI_awsize;
|
||||
input S01_AXI_awvalid;
|
||||
input S01_AXI_bready;
|
||||
output [1:0]S01_AXI_bresp;
|
||||
output S01_AXI_bvalid;
|
||||
input [63:0]S01_AXI_wdata;
|
||||
input S01_AXI_wlast;
|
||||
output S01_AXI_wready;
|
||||
input [7:0]S01_AXI_wstrb;
|
||||
input S01_AXI_wvalid;
|
||||
input [39:0]S02_AXI_awaddr;
|
||||
input [1:0]S02_AXI_awburst;
|
||||
input [3:0]S02_AXI_awcache;
|
||||
input [7:0]S02_AXI_awlen;
|
||||
input [0:0]S02_AXI_awlock;
|
||||
input [2:0]S02_AXI_awprot;
|
||||
input [3:0]S02_AXI_awqos;
|
||||
output S02_AXI_awready;
|
||||
input [2:0]S02_AXI_awsize;
|
||||
input S02_AXI_awvalid;
|
||||
input S02_AXI_bready;
|
||||
output [1:0]S02_AXI_bresp;
|
||||
output S02_AXI_bvalid;
|
||||
input [63:0]S02_AXI_wdata;
|
||||
input S02_AXI_wlast;
|
||||
output S02_AXI_wready;
|
||||
input [7:0]S02_AXI_wstrb;
|
||||
input S02_AXI_wvalid;
|
||||
input [39:0]S03_AXI_awaddr;
|
||||
input [1:0]S03_AXI_awburst;
|
||||
input [3:0]S03_AXI_awcache;
|
||||
input [7:0]S03_AXI_awlen;
|
||||
input [0:0]S03_AXI_awlock;
|
||||
input [2:0]S03_AXI_awprot;
|
||||
input [3:0]S03_AXI_awqos;
|
||||
output S03_AXI_awready;
|
||||
input [2:0]S03_AXI_awsize;
|
||||
input S03_AXI_awvalid;
|
||||
input S03_AXI_bready;
|
||||
output [1:0]S03_AXI_bresp;
|
||||
output S03_AXI_bvalid;
|
||||
input [63:0]S03_AXI_wdata;
|
||||
input S03_AXI_wlast;
|
||||
output S03_AXI_wready;
|
||||
input [7:0]S03_AXI_wstrb;
|
||||
input S03_AXI_wvalid;
|
||||
input aclk;
|
||||
input aresetn;
|
||||
|
||||
wire [31:0]M00_AXI_araddr;
|
||||
wire [1:0]M00_AXI_arburst;
|
||||
wire [3:0]M00_AXI_arcache;
|
||||
wire [7:0]M00_AXI_arlen;
|
||||
wire [0:0]M00_AXI_arlock;
|
||||
wire [2:0]M00_AXI_arprot;
|
||||
wire [3:0]M00_AXI_arqos;
|
||||
wire M00_AXI_arready;
|
||||
wire [2:0]M00_AXI_arsize;
|
||||
wire M00_AXI_arvalid;
|
||||
wire [31:0]M00_AXI_awaddr;
|
||||
wire [1:0]M00_AXI_awburst;
|
||||
wire [3:0]M00_AXI_awcache;
|
||||
wire [7:0]M00_AXI_awlen;
|
||||
wire [0:0]M00_AXI_awlock;
|
||||
wire [2:0]M00_AXI_awprot;
|
||||
wire [3:0]M00_AXI_awqos;
|
||||
wire M00_AXI_awready;
|
||||
wire [2:0]M00_AXI_awsize;
|
||||
wire M00_AXI_awvalid;
|
||||
wire M00_AXI_bready;
|
||||
wire [1:0]M00_AXI_bresp;
|
||||
wire M00_AXI_bvalid;
|
||||
wire [511:0]M00_AXI_rdata;
|
||||
wire M00_AXI_rlast;
|
||||
wire M00_AXI_rready;
|
||||
wire [1:0]M00_AXI_rresp;
|
||||
wire M00_AXI_rvalid;
|
||||
wire [511:0]M00_AXI_wdata;
|
||||
wire M00_AXI_wlast;
|
||||
wire M00_AXI_wready;
|
||||
wire [63:0]M00_AXI_wstrb;
|
||||
wire M00_AXI_wvalid;
|
||||
wire [31:0]S00_AXI_araddr;
|
||||
wire [1:0]S00_AXI_arburst;
|
||||
wire [3:0]S00_AXI_arcache;
|
||||
wire [11:0]S00_AXI_arid;
|
||||
wire [3:0]S00_AXI_arlen;
|
||||
wire [1:0]S00_AXI_arlock;
|
||||
wire [2:0]S00_AXI_arprot;
|
||||
wire [3:0]S00_AXI_arqos;
|
||||
wire S00_AXI_arready;
|
||||
wire [2:0]S00_AXI_arsize;
|
||||
wire S00_AXI_arvalid;
|
||||
wire [31:0]S00_AXI_awaddr;
|
||||
wire [1:0]S00_AXI_awburst;
|
||||
wire [3:0]S00_AXI_awcache;
|
||||
wire [11:0]S00_AXI_awid;
|
||||
wire [3:0]S00_AXI_awlen;
|
||||
wire [1:0]S00_AXI_awlock;
|
||||
wire [2:0]S00_AXI_awprot;
|
||||
wire [3:0]S00_AXI_awqos;
|
||||
wire S00_AXI_awready;
|
||||
wire [2:0]S00_AXI_awsize;
|
||||
wire S00_AXI_awvalid;
|
||||
wire [11:0]S00_AXI_bid;
|
||||
wire S00_AXI_bready;
|
||||
wire [1:0]S00_AXI_bresp;
|
||||
wire S00_AXI_bvalid;
|
||||
wire [31:0]S00_AXI_rdata;
|
||||
wire [11:0]S00_AXI_rid;
|
||||
wire S00_AXI_rlast;
|
||||
wire S00_AXI_rready;
|
||||
wire [1:0]S00_AXI_rresp;
|
||||
wire S00_AXI_rvalid;
|
||||
wire [31:0]S00_AXI_wdata;
|
||||
wire [11:0]S00_AXI_wid;
|
||||
wire S00_AXI_wlast;
|
||||
wire S00_AXI_wready;
|
||||
wire [3:0]S00_AXI_wstrb;
|
||||
wire S00_AXI_wvalid;
|
||||
wire [39:0]S01_AXI_awaddr;
|
||||
wire [1:0]S01_AXI_awburst;
|
||||
wire [3:0]S01_AXI_awcache;
|
||||
wire [7:0]S01_AXI_awlen;
|
||||
wire [0:0]S01_AXI_awlock;
|
||||
wire [2:0]S01_AXI_awprot;
|
||||
wire [3:0]S01_AXI_awqos;
|
||||
wire S01_AXI_awready;
|
||||
wire [2:0]S01_AXI_awsize;
|
||||
wire S01_AXI_awvalid;
|
||||
wire S01_AXI_bready;
|
||||
wire [1:0]S01_AXI_bresp;
|
||||
wire S01_AXI_bvalid;
|
||||
wire [63:0]S01_AXI_wdata;
|
||||
wire S01_AXI_wlast;
|
||||
wire S01_AXI_wready;
|
||||
wire [7:0]S01_AXI_wstrb;
|
||||
wire S01_AXI_wvalid;
|
||||
wire [39:0]S02_AXI_awaddr;
|
||||
wire [1:0]S02_AXI_awburst;
|
||||
wire [3:0]S02_AXI_awcache;
|
||||
wire [7:0]S02_AXI_awlen;
|
||||
wire [0:0]S02_AXI_awlock;
|
||||
wire [2:0]S02_AXI_awprot;
|
||||
wire [3:0]S02_AXI_awqos;
|
||||
wire S02_AXI_awready;
|
||||
wire [2:0]S02_AXI_awsize;
|
||||
wire S02_AXI_awvalid;
|
||||
wire S02_AXI_bready;
|
||||
wire [1:0]S02_AXI_bresp;
|
||||
wire S02_AXI_bvalid;
|
||||
wire [63:0]S02_AXI_wdata;
|
||||
wire S02_AXI_wlast;
|
||||
wire S02_AXI_wready;
|
||||
wire [7:0]S02_AXI_wstrb;
|
||||
wire S02_AXI_wvalid;
|
||||
wire [39:0]S03_AXI_awaddr;
|
||||
wire [1:0]S03_AXI_awburst;
|
||||
wire [3:0]S03_AXI_awcache;
|
||||
wire [7:0]S03_AXI_awlen;
|
||||
wire [0:0]S03_AXI_awlock;
|
||||
wire [2:0]S03_AXI_awprot;
|
||||
wire [3:0]S03_AXI_awqos;
|
||||
wire S03_AXI_awready;
|
||||
wire [2:0]S03_AXI_awsize;
|
||||
wire S03_AXI_awvalid;
|
||||
wire S03_AXI_bready;
|
||||
wire [1:0]S03_AXI_bresp;
|
||||
wire S03_AXI_bvalid;
|
||||
wire [63:0]S03_AXI_wdata;
|
||||
wire S03_AXI_wlast;
|
||||
wire S03_AXI_wready;
|
||||
wire [7:0]S03_AXI_wstrb;
|
||||
wire S03_AXI_wvalid;
|
||||
wire aclk;
|
||||
wire aresetn;
|
||||
|
||||
bd_222a bd_222a_i
|
||||
(.M00_AXI_araddr(M00_AXI_araddr),
|
||||
.M00_AXI_arburst(M00_AXI_arburst),
|
||||
.M00_AXI_arcache(M00_AXI_arcache),
|
||||
.M00_AXI_arlen(M00_AXI_arlen),
|
||||
.M00_AXI_arlock(M00_AXI_arlock),
|
||||
.M00_AXI_arprot(M00_AXI_arprot),
|
||||
.M00_AXI_arqos(M00_AXI_arqos),
|
||||
.M00_AXI_arready(M00_AXI_arready),
|
||||
.M00_AXI_arsize(M00_AXI_arsize),
|
||||
.M00_AXI_arvalid(M00_AXI_arvalid),
|
||||
.M00_AXI_awaddr(M00_AXI_awaddr),
|
||||
.M00_AXI_awburst(M00_AXI_awburst),
|
||||
.M00_AXI_awcache(M00_AXI_awcache),
|
||||
.M00_AXI_awlen(M00_AXI_awlen),
|
||||
.M00_AXI_awlock(M00_AXI_awlock),
|
||||
.M00_AXI_awprot(M00_AXI_awprot),
|
||||
.M00_AXI_awqos(M00_AXI_awqos),
|
||||
.M00_AXI_awready(M00_AXI_awready),
|
||||
.M00_AXI_awsize(M00_AXI_awsize),
|
||||
.M00_AXI_awvalid(M00_AXI_awvalid),
|
||||
.M00_AXI_bready(M00_AXI_bready),
|
||||
.M00_AXI_bresp(M00_AXI_bresp),
|
||||
.M00_AXI_bvalid(M00_AXI_bvalid),
|
||||
.M00_AXI_rdata(M00_AXI_rdata),
|
||||
.M00_AXI_rlast(M00_AXI_rlast),
|
||||
.M00_AXI_rready(M00_AXI_rready),
|
||||
.M00_AXI_rresp(M00_AXI_rresp),
|
||||
.M00_AXI_rvalid(M00_AXI_rvalid),
|
||||
.M00_AXI_wdata(M00_AXI_wdata),
|
||||
.M00_AXI_wlast(M00_AXI_wlast),
|
||||
.M00_AXI_wready(M00_AXI_wready),
|
||||
.M00_AXI_wstrb(M00_AXI_wstrb),
|
||||
.M00_AXI_wvalid(M00_AXI_wvalid),
|
||||
.S00_AXI_araddr(S00_AXI_araddr),
|
||||
.S00_AXI_arburst(S00_AXI_arburst),
|
||||
.S00_AXI_arcache(S00_AXI_arcache),
|
||||
.S00_AXI_arid(S00_AXI_arid),
|
||||
.S00_AXI_arlen(S00_AXI_arlen),
|
||||
.S00_AXI_arlock(S00_AXI_arlock),
|
||||
.S00_AXI_arprot(S00_AXI_arprot),
|
||||
.S00_AXI_arqos(S00_AXI_arqos),
|
||||
.S00_AXI_arready(S00_AXI_arready),
|
||||
.S00_AXI_arsize(S00_AXI_arsize),
|
||||
.S00_AXI_arvalid(S00_AXI_arvalid),
|
||||
.S00_AXI_awaddr(S00_AXI_awaddr),
|
||||
.S00_AXI_awburst(S00_AXI_awburst),
|
||||
.S00_AXI_awcache(S00_AXI_awcache),
|
||||
.S00_AXI_awid(S00_AXI_awid),
|
||||
.S00_AXI_awlen(S00_AXI_awlen),
|
||||
.S00_AXI_awlock(S00_AXI_awlock),
|
||||
.S00_AXI_awprot(S00_AXI_awprot),
|
||||
.S00_AXI_awqos(S00_AXI_awqos),
|
||||
.S00_AXI_awready(S00_AXI_awready),
|
||||
.S00_AXI_awsize(S00_AXI_awsize),
|
||||
.S00_AXI_awvalid(S00_AXI_awvalid),
|
||||
.S00_AXI_bid(S00_AXI_bid),
|
||||
.S00_AXI_bready(S00_AXI_bready),
|
||||
.S00_AXI_bresp(S00_AXI_bresp),
|
||||
.S00_AXI_bvalid(S00_AXI_bvalid),
|
||||
.S00_AXI_rdata(S00_AXI_rdata),
|
||||
.S00_AXI_rid(S00_AXI_rid),
|
||||
.S00_AXI_rlast(S00_AXI_rlast),
|
||||
.S00_AXI_rready(S00_AXI_rready),
|
||||
.S00_AXI_rresp(S00_AXI_rresp),
|
||||
.S00_AXI_rvalid(S00_AXI_rvalid),
|
||||
.S00_AXI_wdata(S00_AXI_wdata),
|
||||
.S00_AXI_wid(S00_AXI_wid),
|
||||
.S00_AXI_wlast(S00_AXI_wlast),
|
||||
.S00_AXI_wready(S00_AXI_wready),
|
||||
.S00_AXI_wstrb(S00_AXI_wstrb),
|
||||
.S00_AXI_wvalid(S00_AXI_wvalid),
|
||||
.S01_AXI_awaddr(S01_AXI_awaddr),
|
||||
.S01_AXI_awburst(S01_AXI_awburst),
|
||||
.S01_AXI_awcache(S01_AXI_awcache),
|
||||
.S01_AXI_awlen(S01_AXI_awlen),
|
||||
.S01_AXI_awlock(S01_AXI_awlock),
|
||||
.S01_AXI_awprot(S01_AXI_awprot),
|
||||
.S01_AXI_awqos(S01_AXI_awqos),
|
||||
.S01_AXI_awready(S01_AXI_awready),
|
||||
.S01_AXI_awsize(S01_AXI_awsize),
|
||||
.S01_AXI_awvalid(S01_AXI_awvalid),
|
||||
.S01_AXI_bready(S01_AXI_bready),
|
||||
.S01_AXI_bresp(S01_AXI_bresp),
|
||||
.S01_AXI_bvalid(S01_AXI_bvalid),
|
||||
.S01_AXI_wdata(S01_AXI_wdata),
|
||||
.S01_AXI_wlast(S01_AXI_wlast),
|
||||
.S01_AXI_wready(S01_AXI_wready),
|
||||
.S01_AXI_wstrb(S01_AXI_wstrb),
|
||||
.S01_AXI_wvalid(S01_AXI_wvalid),
|
||||
.S02_AXI_awaddr(S02_AXI_awaddr),
|
||||
.S02_AXI_awburst(S02_AXI_awburst),
|
||||
.S02_AXI_awcache(S02_AXI_awcache),
|
||||
.S02_AXI_awlen(S02_AXI_awlen),
|
||||
.S02_AXI_awlock(S02_AXI_awlock),
|
||||
.S02_AXI_awprot(S02_AXI_awprot),
|
||||
.S02_AXI_awqos(S02_AXI_awqos),
|
||||
.S02_AXI_awready(S02_AXI_awready),
|
||||
.S02_AXI_awsize(S02_AXI_awsize),
|
||||
.S02_AXI_awvalid(S02_AXI_awvalid),
|
||||
.S02_AXI_bready(S02_AXI_bready),
|
||||
.S02_AXI_bresp(S02_AXI_bresp),
|
||||
.S02_AXI_bvalid(S02_AXI_bvalid),
|
||||
.S02_AXI_wdata(S02_AXI_wdata),
|
||||
.S02_AXI_wlast(S02_AXI_wlast),
|
||||
.S02_AXI_wready(S02_AXI_wready),
|
||||
.S02_AXI_wstrb(S02_AXI_wstrb),
|
||||
.S02_AXI_wvalid(S02_AXI_wvalid),
|
||||
.S03_AXI_awaddr(S03_AXI_awaddr),
|
||||
.S03_AXI_awburst(S03_AXI_awburst),
|
||||
.S03_AXI_awcache(S03_AXI_awcache),
|
||||
.S03_AXI_awlen(S03_AXI_awlen),
|
||||
.S03_AXI_awlock(S03_AXI_awlock),
|
||||
.S03_AXI_awprot(S03_AXI_awprot),
|
||||
.S03_AXI_awqos(S03_AXI_awqos),
|
||||
.S03_AXI_awready(S03_AXI_awready),
|
||||
.S03_AXI_awsize(S03_AXI_awsize),
|
||||
.S03_AXI_awvalid(S03_AXI_awvalid),
|
||||
.S03_AXI_bready(S03_AXI_bready),
|
||||
.S03_AXI_bresp(S03_AXI_bresp),
|
||||
.S03_AXI_bvalid(S03_AXI_bvalid),
|
||||
.S03_AXI_wdata(S03_AXI_wdata),
|
||||
.S03_AXI_wlast(S03_AXI_wlast),
|
||||
.S03_AXI_wready(S03_AXI_wready),
|
||||
.S03_AXI_wstrb(S03_AXI_wstrb),
|
||||
.S03_AXI_wvalid(S03_AXI_wvalid),
|
||||
.aclk(aclk),
|
||||
.aresetn(aresetn));
|
||||
endmodule
|
||||
+28699
File diff suppressed because it is too large
Load Diff
+50
@@ -0,0 +1,50 @@
|
||||
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|
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|
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"ip_revision": "9",
|
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"gen_directory": ".",
|
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"parameters": {
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|
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|
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|
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|
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|
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"model_parameters": {
|
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|
||||
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|
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|
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|
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|
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}
|
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<spirit:vendor>xilinx.com</spirit:vendor>
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<spirit:library>customized_ip</spirit:library>
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<spirit:name>bd_222a_one_0</spirit:name>
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<spirit:displayName>Verilog Synthesis</spirit:displayName>
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<spirit:modelName>bd_222a_one_0</spirit:modelName>
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<spirit:fileSetRef>
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<spirit:localName>xilinx_verilogsynthesiswrapper_view_fileset</spirit:localName>
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<spirit:parameter>
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<spirit:name>outputProductCRC</spirit:name>
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<spirit:wire>
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<spirit:displayName>Const Width</spirit:displayName>
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<spirit:displayName>Const Val</spirit:displayName>
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<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CONST_VAL" spirit:bitStringLength="1">0x1</spirit:value>
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|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
</spirit:fileSets>
|
||||
<spirit:description>Gives a constant signed value.</spirit:description>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>Component_Name</spirit:name>
|
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<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="2">bd_222a_one_0</spirit:value>
|
||||
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|
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|
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<spirit:name>CONST_WIDTH</spirit:name>
|
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<spirit:displayName>Const Width</spirit:displayName>
|
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|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CONST_VAL</spirit:name>
|
||||
<spirit:displayName>Const Val</spirit:displayName>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CONST_VAL" spirit:order="4">1</spirit:value>
|
||||
</spirit:parameter>
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|
||||
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|
||||
<xilinx:displayName>Constant</xilinx:displayName>
|
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|
||||
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|
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|
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+69
@@ -0,0 +1,69 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:xlconstant:1.1
|
||||
// IP Revision: 9
|
||||
|
||||
(* X_CORE_INFO = "xlconstant_v1_1_9_xlconstant,Vivado 2024.1" *)
|
||||
(* CHECK_LICENSE_TYPE = "bd_222a_one_0,xlconstant_v1_1_9_xlconstant,{}" *)
|
||||
(* CORE_GENERATION_INFO = "bd_222a_one_0,xlconstant_v1_1_9_xlconstant,{x_ipProduct=Vivado 2024.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconstant,x_ipVersion=1.1,x_ipCoreRevision=9,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,CONST_WIDTH=1,CONST_VAL=0x1}" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_222a_one_0 (
|
||||
dout
|
||||
);
|
||||
|
||||
output wire [0 : 0] dout;
|
||||
|
||||
xlconstant_v1_1_9_xlconstant #(
|
||||
.CONST_WIDTH(1),
|
||||
.CONST_VAL(1'H1)
|
||||
) inst (
|
||||
.dout(dout)
|
||||
);
|
||||
endmodule
|
||||
+196
@@ -0,0 +1,196 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "bd_222a_psr_aclk_0",
|
||||
"cell_name": "clk_map/psr_aclk",
|
||||
"component_reference": "xilinx.com:ip:proc_sys_reset:5.0",
|
||||
"ip_revision": "15",
|
||||
"gen_directory": ".",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"C_NUM_PERP_ARESETN": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_INTERCONNECT_ARESETN": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_PERP_RST": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_BUS_RST": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_AUX_RESET_HIGH": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_EXT_RESET_HIGH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_AUX_RST_WIDTH": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_EXT_RST_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "bd_222a_psr_aclk_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"USE_BOARD_FLOW": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"RESET_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_FAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_EXT_RST_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AUX_RST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_EXT_RESET_HIGH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AUX_RESET_HIGH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_BUS_RST": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_PERP_RST": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_INTERCONNECT_ARESETN": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_PERP_ARESETN": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "xilinx.com:zc706:part0:1.4" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z045" } ],
|
||||
"NEXTGEN_VERSAL": [ { "value": "0" } ],
|
||||
"PACKAGE": [ { "value": "ffg900" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "15" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "." } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../../../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2024.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"slowest_sync_clk": [ { "direction": "in" } ],
|
||||
"ext_reset_in": [ { "direction": "in" } ],
|
||||
"aux_reset_in": [ { "direction": "in", "driver_value": "1" } ],
|
||||
"mb_debug_sys_rst": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"dcm_locked": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"mb_reset": [ { "direction": "out", "driver_value": "0x0" } ],
|
||||
"bus_struct_reset": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"peripheral_reset": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"interconnect_aresetn": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "1" } ],
|
||||
"peripheral_aresetn": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "1" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"clock": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_RESET": [ { "value": "mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "200000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_mig_7series_0_0_ui_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "slowest_sync_clk" } ]
|
||||
}
|
||||
},
|
||||
"ext_reset": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"BOARD.ASSOCIATED_PARAM": [ { "value": "RESET_BOARD_INTERFACE", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "ext_reset_in" } ]
|
||||
}
|
||||
},
|
||||
"aux_reset": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "aux_reset_in" } ]
|
||||
}
|
||||
},
|
||||
"dbg_reset": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "mb_debug_sys_rst" } ]
|
||||
}
|
||||
},
|
||||
"mb_rst": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"TYPE": [ { "value": "PROCESSOR", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "mb_reset" } ]
|
||||
}
|
||||
},
|
||||
"bus_struct_reset": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"TYPE": [ { "value": "INTERCONNECT", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "bus_struct_reset" } ]
|
||||
}
|
||||
},
|
||||
"interconnect_low_rst": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"TYPE": [ { "value": "INTERCONNECT", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "interconnect_aresetn" } ]
|
||||
}
|
||||
},
|
||||
"peripheral_high_rst": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"TYPE": [ { "value": "PERIPHERAL", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "peripheral_reset" } ]
|
||||
}
|
||||
},
|
||||
"peripheral_low_rst": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"TYPE": [ { "value": "PERIPHERAL", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "peripheral_aresetn" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+53
@@ -0,0 +1,53 @@
|
||||
|
||||
# file: bd_222a_psr_aclk_0.xdc
|
||||
# (c) Copyright 2009 - 2013 Advanced Micro Devices, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Advanced Micro Devices, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# AMD, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) AMD shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or AMD had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# AMD products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of AMD products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
set_false_path -to [get_pins -hier *cdc_to*/D]
|
||||
create_waiver -type CDC -id {CDC-11} -user "proc_sys_reset" -desc "Timing uncritical paths" -tags "1171415" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to}]]
|
||||
|
||||
|
||||
+823
@@ -0,0 +1,823 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>customized_ip</spirit:library>
|
||||
<spirit:name>bd_222a_psr_aclk_0</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>clock</spirit:name>
|
||||
<spirit:displayName>Clock</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>slowest_sync_clk</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_RESET">mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:displayName>Slowest Sync clock frequency</spirit:displayName>
|
||||
<spirit:description>Slowest Synchronous clock frequency</spirit:description>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLOCK.FREQ_HZ">200000000</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK.FREQ_TOLERANCE_HZ">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK.PHASE">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK.CLK_DOMAIN">system_top_mig_7series_0_0_ui_clk</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_BUSIF"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_PORT</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_PORT"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLOCK.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>ext_reset</spirit:name>
|
||||
<spirit:displayName>Ext_Reset</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>ext_reset_in</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>BOARD.ASSOCIATED_PARAM</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.EXT_RESET.BOARD.ASSOCIATED_PARAM">RESET_BOARD_INTERFACE</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:enablement>
|
||||
<xilinx:presence>required</xilinx:presence>
|
||||
</xilinx:enablement>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.EXT_RESET.POLARITY">ACTIVE_LOW</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.EXT_RESET.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>aux_reset</spirit:name>
|
||||
<spirit:displayName>aux_reset</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>aux_reset_in</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AUX_RESET.POLARITY">ACTIVE_LOW</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.AUX_RESET.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>dbg_reset</spirit:name>
|
||||
<spirit:displayName>DBG_Reset</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>mb_debug_sys_rst</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.DBG_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.DBG_RESET.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>mb_rst</spirit:name>
|
||||
<spirit:displayName>MB_rst</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>mb_reset</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.MB_RST.POLARITY">ACTIVE_HIGH</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TYPE</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.MB_RST.TYPE">PROCESSOR</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.MB_RST.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>bus_struct_reset</spirit:name>
|
||||
<spirit:displayName>bus_struct_reset</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>bus_struct_reset</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.BUS_STRUCT_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TYPE</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.BUS_STRUCT_RESET.TYPE">INTERCONNECT</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.BUS_STRUCT_RESET.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>interconnect_low_rst</spirit:name>
|
||||
<spirit:displayName>interconnect_low_rst</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>interconnect_aresetn</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.INTERCONNECT_LOW_RST.POLARITY">ACTIVE_LOW</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TYPE</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.INTERCONNECT_LOW_RST.TYPE">INTERCONNECT</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.INTERCONNECT_LOW_RST.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>peripheral_high_rst</spirit:name>
|
||||
<spirit:displayName>peripheral_high_rst</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>peripheral_reset</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.PERIPHERAL_HIGH_RST.POLARITY">ACTIVE_HIGH</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TYPE</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.PERIPHERAL_HIGH_RST.TYPE">PERIPHERAL</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.PERIPHERAL_HIGH_RST.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>peripheral_low_rst</spirit:name>
|
||||
<spirit:displayName>peripheral_low_rst</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>peripheral_aresetn</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.PERIPHERAL_LOW_RST.POLARITY">ACTIVE_LOW</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TYPE</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.PERIPHERAL_LOW_RST.TYPE">PERIPHERAL</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.PERIPHERAL_LOW_RST.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
</spirit:busInterfaces>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_implementation</spirit:name>
|
||||
<spirit:displayName>Implementation</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:implementation</spirit:envIdentifier>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_implementation_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Oct 31 03:29:36 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:bc016e80</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_synthesisconstraints</spirit:name>
|
||||
<spirit:displayName>Synthesis Constraints</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:bc016e80</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_vhdlsynthesis</spirit:name>
|
||||
<spirit:displayName>VHDL Synthesis</spirit:displayName>
|
||||
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis</spirit:envIdentifier>
|
||||
<spirit:language>vhdl</spirit:language>
|
||||
<spirit:modelName>proc_sys_reset</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_vhdlsynthesis_xilinx_com_ip_lib_cdc_1_0__ref_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_vhdlsynthesis_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Oct 31 03:29:36 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:bc016e80</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_vhdlsynthesiswrapper</spirit:name>
|
||||
<spirit:displayName>VHDL Synthesis Wrapper</spirit:displayName>
|
||||
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
|
||||
<spirit:language>vhdl</spirit:language>
|
||||
<spirit:modelName>bd_222a_psr_aclk_0</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Oct 31 03:29:36 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:bc016e80</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
</spirit:views>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:name>slowest_sync_clk</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>ext_reset_in</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>aux_reset_in</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>mb_debug_sys_rst</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>dcm_locked</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x1</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>mb_reset</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>bus_struct_reset</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">0</spirit:left>
|
||||
<spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_NUM_BUS_RST')) - 1)">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>peripheral_reset</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">0</spirit:left>
|
||||
<spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_NUM_PERP_RST')) - 1)">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>interconnect_aresetn</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">0</spirit:left>
|
||||
<spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_NUM_INTERCONNECT_ARESETN')) - 1)">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>peripheral_aresetn</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">0</spirit:left>
|
||||
<spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_NUM_PERP_ARESETN')) - 1)">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
</spirit:ports>
|
||||
<spirit:modelParameters>
|
||||
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="string">
|
||||
<spirit:name>C_FAMILY</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FAMILY">zynq</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>C_EXT_RST_WIDTH</spirit:name>
|
||||
<spirit:displayName>Ext Rst Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EXT_RST_WIDTH" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>C_AUX_RST_WIDTH</spirit:name>
|
||||
<spirit:displayName>Aux Rst Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AUX_RST_WIDTH" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">1</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="std_logic">
|
||||
<spirit:name>C_EXT_RESET_HIGH</spirit:name>
|
||||
<spirit:displayName>Ext Reset High</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EXT_RESET_HIGH">0</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="std_logic">
|
||||
<spirit:name>C_AUX_RESET_HIGH</spirit:name>
|
||||
<spirit:displayName>Aux Reset High</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AUX_RESET_HIGH" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">0</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>C_NUM_BUS_RST</spirit:name>
|
||||
<spirit:displayName>No. of Bus Reset (Active High)</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_BUS_RST" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">1</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>C_NUM_PERP_RST</spirit:name>
|
||||
<spirit:displayName>No. of Peripheral Reset (Active High)</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_PERP_RST" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">1</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>C_NUM_INTERCONNECT_ARESETN</spirit:name>
|
||||
<spirit:displayName>No. of Interconnect Reset (Active Low)</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_INTERCONNECT_ARESETN" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">1</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>C_NUM_PERP_ARESETN</spirit:name>
|
||||
<spirit:displayName>No. of Peripheral Reset (Active Low)</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_PERP_ARESETN" spirit:minimum="1" spirit:maximum="31" spirit:rangeType="long">1</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
</spirit:modelParameters>
|
||||
</spirit:model>
|
||||
<spirit:choices>
|
||||
<spirit:choice>
|
||||
<spirit:name>choice_list_ce26ebdb</spirit:name>
|
||||
<spirit:enumeration>Custom</spirit:enumeration>
|
||||
<spirit:enumeration>reset</spirit:enumeration>
|
||||
</spirit:choice>
|
||||
</spirit:choices>
|
||||
<spirit:fileSets>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_implementation_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>bd_222a_psr_aclk_0_board.xdc</spirit:name>
|
||||
<spirit:userFileType>xdc</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_board</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlsynthesis_xilinx_com_ip_lib_cdc_1_0__ref_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>../../../../../ipshared/2a4f/hdl/lib_cdc_v1_0_rfs.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:logicalName>lib_cdc_v1_0_3</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:subCoreRef>
|
||||
<xilinx:componentRef xilinx:vendor="xilinx.com" xilinx:library="ip" xilinx:name="lib_cdc" xilinx:version="1.0" xilinx:isGenerated="true" xilinx:checksum="726cb4eb">
|
||||
<xilinx:mode xilinx:name="copy_mode"/>
|
||||
</xilinx:componentRef>
|
||||
</xilinx:subCoreRef>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlsynthesis_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>../../../../../ipshared/3a26/hdl/proc_sys_reset_v5_0_vh_rfs.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:logicalName>proc_sys_reset_v5_0_15</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>bd_222a_psr_aclk_0.xdc</spirit:name>
|
||||
<spirit:userFileType>xdc</spirit:userFileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>synth/bd_222a_psr_aclk_0.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
</spirit:fileSets>
|
||||
<spirit:description>Processor Reset System</spirit:description>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>C_NUM_PERP_ARESETN</spirit:name>
|
||||
<spirit:displayName>No. of Peripheral Reset (Active Low)</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_PERP_ARESETN" spirit:order="1800" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">1</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>C_NUM_INTERCONNECT_ARESETN</spirit:name>
|
||||
<spirit:displayName>No. of Interconnect Reset (Active Low)</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_INTERCONNECT_ARESETN" spirit:order="1700" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>C_NUM_PERP_RST</spirit:name>
|
||||
<spirit:displayName>No. of Peripheral Reset (Active High)</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_PERP_RST" spirit:order="1600" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">1</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>C_NUM_BUS_RST</spirit:name>
|
||||
<spirit:displayName>No. of Bus Reset (Active High)</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_BUS_RST" spirit:order="1500" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>C_AUX_RESET_HIGH</spirit:name>
|
||||
<spirit:displayName>Aux Reset High</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_AUX_RESET_HIGH" spirit:order="1400" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>C_EXT_RESET_HIGH</spirit:name>
|
||||
<spirit:displayName>Ext Reset High</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_EXT_RESET_HIGH" spirit:order="1300" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>C_AUX_RST_WIDTH</spirit:name>
|
||||
<spirit:displayName>Aux Rst Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_AUX_RST_WIDTH" spirit:order="1200" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">1</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>C_EXT_RST_WIDTH</spirit:name>
|
||||
<spirit:displayName>Ext Rst Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_EXT_RST_WIDTH" spirit:order="1100" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>Component_Name</spirit:name>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">bd_222a_psr_aclk_0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>USE_BOARD_FLOW</spirit:name>
|
||||
<spirit:displayName>Generate Board based IO Constraints</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_BOARD_FLOW" spirit:order="2">false</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>RESET_BOARD_INTERFACE</spirit:name>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RESET_BOARD_INTERFACE" spirit:choiceRef="choice_list_ce26ebdb" spirit:order="3">Custom</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:coreExtensions>
|
||||
<xilinx:displayName>Processor System Reset</xilinx:displayName>
|
||||
<xilinx:coreRevision>15</xilinx:coreRevision>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AUX_RESET.POLARITY" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BUS_STRUCT_RESET.POLARITY" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BUS_STRUCT_RESET.TYPE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_PORT" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_RESET" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.PHASE" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.DBG_RESET.POLARITY" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.EXT_RESET.BOARD.ASSOCIATED_PARAM" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.EXT_RESET.POLARITY" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.INTERCONNECT_LOW_RST.POLARITY" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.INTERCONNECT_LOW_RST.TYPE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.MB_RST.POLARITY" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.MB_RST.TYPE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.PERIPHERAL_HIGH_RST.POLARITY" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.PERIPHERAL_HIGH_RST.TYPE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.PERIPHERAL_LOW_RST.POLARITY" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.PERIPHERAL_LOW_RST.TYPE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_AUX_RESET_HIGH" xilinx:valueSource="user" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_AUX_RST_WIDTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_EXT_RESET_HIGH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
||||
</xilinx:configElementInfos>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
|
||||
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="26169568"/>
|
||||
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="c4adc7a2"/>
|
||||
<xilinx:checksum xilinx:scope="ports" xilinx:value="f2ac9635"/>
|
||||
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="404de108"/>
|
||||
<xilinx:checksum xilinx:scope="parameters" xilinx:value="8319b917"/>
|
||||
</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
+2
@@ -0,0 +1,2 @@
|
||||
#--------------------Physical Constraints-----------------
|
||||
|
||||
+153
@@ -0,0 +1,153 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
|
||||
-- IP Revision: 15
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY proc_sys_reset_v5_0_15;
|
||||
USE proc_sys_reset_v5_0_15.proc_sys_reset;
|
||||
|
||||
ENTITY bd_222a_psr_aclk_0 IS
|
||||
PORT (
|
||||
slowest_sync_clk : IN STD_LOGIC;
|
||||
ext_reset_in : IN STD_LOGIC;
|
||||
aux_reset_in : IN STD_LOGIC;
|
||||
mb_debug_sys_rst : IN STD_LOGIC;
|
||||
dcm_locked : IN STD_LOGIC;
|
||||
mb_reset : OUT STD_LOGIC;
|
||||
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
|
||||
);
|
||||
END bd_222a_psr_aclk_0;
|
||||
|
||||
ARCHITECTURE bd_222a_psr_aclk_0_arch OF bd_222a_psr_aclk_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF bd_222a_psr_aclk_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT proc_sys_reset IS
|
||||
GENERIC (
|
||||
C_FAMILY : STRING;
|
||||
C_EXT_RST_WIDTH : INTEGER;
|
||||
C_AUX_RST_WIDTH : INTEGER;
|
||||
C_EXT_RESET_HIGH : STD_LOGIC;
|
||||
C_AUX_RESET_HIGH : STD_LOGIC;
|
||||
C_NUM_BUS_RST : INTEGER;
|
||||
C_NUM_PERP_RST : INTEGER;
|
||||
C_NUM_INTERCONNECT_ARESETN : INTEGER;
|
||||
C_NUM_PERP_ARESETN : INTEGER
|
||||
);
|
||||
PORT (
|
||||
slowest_sync_clk : IN STD_LOGIC;
|
||||
ext_reset_in : IN STD_LOGIC;
|
||||
aux_reset_in : IN STD_LOGIC;
|
||||
mb_debug_sys_rst : IN STD_LOGIC;
|
||||
dcm_locked : IN STD_LOGIC;
|
||||
mb_reset : OUT STD_LOGIC;
|
||||
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT proc_sys_reset;
|
||||
ATTRIBUTE X_CORE_INFO : STRING;
|
||||
ATTRIBUTE X_CORE_INFO OF bd_222a_psr_aclk_0_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2024.1";
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE OF bd_222a_psr_aclk_0_arch : ARCHITECTURE IS "bd_222a_psr_aclk_0,proc_sys_reset,{}";
|
||||
ATTRIBUTE CORE_GENERATION_INFO : STRING;
|
||||
ATTRIBUTE CORE_GENERATION_INFO OF bd_222a_psr_aclk_0_arch: ARCHITECTURE IS "bd_222a_psr_aclk_0,proc_sys_reset,{x_ipProduct=Vivado 2024.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=15,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=1,C_EXT_RESET_HIGH=0,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}";
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF aux_reset_in: SIGNAL IS "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF bus_struct_reset: SIGNAL IS "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF ext_reset_in: SIGNAL IS "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF interconnect_aresetn: SIGNAL IS "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF mb_debug_sys_rst: SIGNAL IS "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF mb_reset: SIGNAL IS "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_aresetn: SIGNAL IS "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_reset: SIGNAL IS "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF slowest_sync_clk: SIGNAL IS "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 200000000, FREQ_TOLERANCE_HZ 0, PHASE 0, CLK_DOMAIN system_top_mig_7series_0_0_ui_clk, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
|
||||
BEGIN
|
||||
U0 : proc_sys_reset
|
||||
GENERIC MAP (
|
||||
C_FAMILY => "zynq",
|
||||
C_EXT_RST_WIDTH => 4,
|
||||
C_AUX_RST_WIDTH => 1,
|
||||
C_EXT_RESET_HIGH => '0',
|
||||
C_AUX_RESET_HIGH => '0',
|
||||
C_NUM_BUS_RST => 1,
|
||||
C_NUM_PERP_RST => 1,
|
||||
C_NUM_INTERCONNECT_ARESETN => 1,
|
||||
C_NUM_PERP_ARESETN => 1
|
||||
)
|
||||
PORT MAP (
|
||||
slowest_sync_clk => slowest_sync_clk,
|
||||
ext_reset_in => ext_reset_in,
|
||||
aux_reset_in => aux_reset_in,
|
||||
mb_debug_sys_rst => mb_debug_sys_rst,
|
||||
dcm_locked => dcm_locked,
|
||||
mb_reset => mb_reset,
|
||||
bus_struct_reset => bus_struct_reset,
|
||||
peripheral_reset => peripheral_reset,
|
||||
interconnect_aresetn => interconnect_aresetn,
|
||||
peripheral_aresetn => peripheral_aresetn
|
||||
);
|
||||
END bd_222a_psr_aclk_0_arch;
|
||||
+303
@@ -0,0 +1,303 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "bd_222a_s00a2s_0",
|
||||
"cell_name": "s00_axi2sc",
|
||||
"component_reference": "xilinx.com:ip:sc_axi2sc:1.0",
|
||||
"ip_revision": "10",
|
||||
"gen_directory": ".",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"AXI_ADDR_WIDTH": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"AXI_ID_WIDTH": [ { "value": "3", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"AXI_RDATA_WIDTH": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"AXI_WDATA_WIDTH": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SC_ADDR_WIDTH": [ { "value": "40", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SC_ID_WIDTH": [ { "value": "3", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SC_RDATA_WIDTH": [ { "value": "512", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SC_WDATA_WIDTH": [ { "value": "512", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SC_ARUSER_WIDTH": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SC_AWUSER_WIDTH": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SC_BUSER_WIDTH": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SC_WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SC_RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MSC_ROUTE_WIDTH": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SSC_ROUTE_WIDTH": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "bd_222a_s00a2s_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_AXI_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_ID_WIDTH": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_RDATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_WDATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SC_ADDR_WIDTH": [ { "value": "40", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SC_ID_WIDTH": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SC_RDATA_WIDTH": [ { "value": "512", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SC_WDATA_WIDTH": [ { "value": "512", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SC_RUSER_BITS_PER_BYTE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SC_WUSER_BITS_PER_BYTE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SC_ARUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SC_AWUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SC_BUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MSC_ROUTE_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SSC_ROUTE_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AWPAYLD_WIDTH": [ { "value": "150", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
|
||||
"C_ARPAYLD_WIDTH": [ { "value": "150", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
|
||||
"C_WPAYLD_WIDTH": [ { "value": "592", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
|
||||
"C_RPAYLD_WIDTH": [ { "value": "536", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
|
||||
"C_BPAYLD_WIDTH": [ { "value": "10", "resolve_type": "dependent", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "xilinx.com:zc706:part0:1.4" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z045" } ],
|
||||
"NEXTGEN_VERSAL": [ { "value": "0" } ],
|
||||
"PACKAGE": [ { "value": "ffg900" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "10" } ],
|
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||||
"FREQ_HZ": [ { "value": "200000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_mig_7series_0_0_ui_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "aclk" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+2689
File diff suppressed because it is too large
Load Diff
+51
@@ -0,0 +1,51 @@
|
||||
################################################################################
|
||||
# (c) Copyright 2015 Advanced Micro Devices, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Advanced micro Devices, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# AMD, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) AMD shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or AMD had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# AMD products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of AMD products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
################################################################################
|
||||
#
|
||||
# Port aclk is never used.
|
||||
#
|
||||
+344
@@ -0,0 +1,344 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:sc_axi2sc:1.0
|
||||
// IP Revision: 10
|
||||
|
||||
(* X_CORE_INFO = "sc_axi2sc_v1_0_10_top,Vivado 2024.1" *)
|
||||
(* CHECK_LICENSE_TYPE = "bd_222a_s00a2s_0,sc_axi2sc_v1_0_10_top,{}" *)
|
||||
(* CORE_GENERATION_INFO = "bd_222a_s00a2s_0,sc_axi2sc_v1_0_10_top,{x_ipProduct=Vivado 2024.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=sc_axi2sc,x_ipVersion=1.0,x_ipCoreRevision=10,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_AXI_ADDR_WIDTH=32,C_AXI_ID_WIDTH=3,C_AXI_RDATA_WIDTH=32,C_AXI_WDATA_WIDTH=32,C_SC_ADDR_WIDTH=40,C_SC_ID_WIDTH=3,C_SC_RDATA_WIDTH=512,C_SC_WDATA_WIDTH=512,C_SC_RUSER_BITS_PER_BYTE=0,C_SC_WUSER_BITS_PER_BYTE=0,C_SC_ARUSER_WIDTH=0,C_SC_AWUSER_WIDTH=0,C_SC_BUSER_WIDTH=0,C_MSC_ROUTE_WIDTH=1,C_SSC_ROUT\
|
||||
E_WIDTH=4,C_AWPAYLD_WIDTH=150,C_ARPAYLD_WIDTH=150,C_WPAYLD_WIDTH=592,C_RPAYLD_WIDTH=536,C_BPAYLD_WIDTH=10}" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_222a_s00a2s_0 (
|
||||
aclk,
|
||||
s_sc_r_req,
|
||||
s_sc_r_info,
|
||||
s_sc_r_send,
|
||||
s_sc_r_recv,
|
||||
s_sc_r_payld,
|
||||
s_sc_b_req,
|
||||
s_sc_b_info,
|
||||
s_sc_b_send,
|
||||
s_sc_b_recv,
|
||||
s_sc_b_payld,
|
||||
m_sc_ar_req,
|
||||
m_sc_ar_info,
|
||||
m_sc_ar_send,
|
||||
m_sc_ar_recv,
|
||||
m_sc_ar_payld,
|
||||
m_sc_aw_req,
|
||||
m_sc_aw_info,
|
||||
m_sc_aw_send,
|
||||
m_sc_aw_recv,
|
||||
m_sc_aw_payld,
|
||||
m_sc_w_req,
|
||||
m_sc_w_info,
|
||||
m_sc_w_send,
|
||||
m_sc_w_recv,
|
||||
m_sc_w_payld,
|
||||
s_axi_awid,
|
||||
s_axi_awaddr,
|
||||
s_axi_awlen,
|
||||
s_axi_awlock,
|
||||
s_axi_awcache,
|
||||
s_axi_awprot,
|
||||
s_axi_awqos,
|
||||
s_axi_awuser,
|
||||
s_axi_awvalid,
|
||||
s_axi_awready,
|
||||
s_axi_wdata,
|
||||
s_axi_wstrb,
|
||||
s_axi_wlast,
|
||||
s_axi_wuser,
|
||||
s_axi_wvalid,
|
||||
s_axi_wready,
|
||||
s_axi_bid,
|
||||
s_axi_bresp,
|
||||
s_axi_buser,
|
||||
s_axi_bvalid,
|
||||
s_axi_bready,
|
||||
s_axi_arid,
|
||||
s_axi_araddr,
|
||||
s_axi_arlen,
|
||||
s_axi_arlock,
|
||||
s_axi_arcache,
|
||||
s_axi_arprot,
|
||||
s_axi_arqos,
|
||||
s_axi_aruser,
|
||||
s_axi_arvalid,
|
||||
s_axi_arready,
|
||||
s_axi_rid,
|
||||
s_axi_rdata,
|
||||
s_axi_rresp,
|
||||
s_axi_rlast,
|
||||
s_axi_ruser,
|
||||
s_axi_rvalid,
|
||||
s_axi_rready
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF S_AXI:M_SC_AR:M_SC_AW:M_SC_W:S_SC_R:S_SC_B, FREQ_HZ 200000000, FREQ_TOLERANCE_HZ 0, PHASE 0, CLK_DOMAIN system_top_mig_7series_0_0_ui_clk, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk CLK" *)
|
||||
input wire aclk;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_R REQ" *)
|
||||
input wire s_sc_r_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_R INFO" *)
|
||||
input wire [0 : 0] s_sc_r_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_R SEND" *)
|
||||
input wire s_sc_r_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_R RECV" *)
|
||||
output wire s_sc_r_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_R PAYLD" *)
|
||||
input wire [535 : 0] s_sc_r_payld;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_B REQ" *)
|
||||
input wire s_sc_b_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_B INFO" *)
|
||||
input wire [0 : 0] s_sc_b_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_B SEND" *)
|
||||
input wire s_sc_b_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_B RECV" *)
|
||||
output wire s_sc_b_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_B PAYLD" *)
|
||||
input wire [9 : 0] s_sc_b_payld;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_AR REQ" *)
|
||||
output wire m_sc_ar_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_AR INFO" *)
|
||||
output wire [0 : 0] m_sc_ar_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_AR SEND" *)
|
||||
output wire m_sc_ar_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_AR RECV" *)
|
||||
input wire m_sc_ar_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_AR PAYLD" *)
|
||||
output wire [149 : 0] m_sc_ar_payld;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_AW REQ" *)
|
||||
output wire m_sc_aw_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_AW INFO" *)
|
||||
output wire [0 : 0] m_sc_aw_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_AW SEND" *)
|
||||
output wire m_sc_aw_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_AW RECV" *)
|
||||
input wire m_sc_aw_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_AW PAYLD" *)
|
||||
output wire [149 : 0] m_sc_aw_payld;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_W REQ" *)
|
||||
output wire m_sc_w_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_W INFO" *)
|
||||
output wire [0 : 0] m_sc_w_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_W SEND" *)
|
||||
output wire m_sc_w_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_W RECV" *)
|
||||
input wire m_sc_w_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_W PAYLD" *)
|
||||
output wire [591 : 0] m_sc_w_payld;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
|
||||
input wire [2 : 0] s_axi_awid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
|
||||
input wire [31 : 0] s_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
|
||||
input wire [7 : 0] s_axi_awlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
|
||||
input wire [0 : 0] s_axi_awlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
|
||||
input wire [3 : 0] s_axi_awcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
|
||||
input wire [2 : 0] s_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
|
||||
input wire [3 : 0] s_axi_awqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWUSER" *)
|
||||
input wire [1023 : 0] s_axi_awuser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
|
||||
input wire s_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
|
||||
output wire s_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
|
||||
input wire [31 : 0] s_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
|
||||
input wire [3 : 0] s_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
|
||||
input wire s_axi_wlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WUSER" *)
|
||||
input wire [1023 : 0] s_axi_wuser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
|
||||
input wire s_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
|
||||
output wire s_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
|
||||
output wire [2 : 0] s_axi_bid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
|
||||
output wire [1 : 0] s_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BUSER" *)
|
||||
output wire [1023 : 0] s_axi_buser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
|
||||
output wire s_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
|
||||
input wire s_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
|
||||
input wire [2 : 0] s_axi_arid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
|
||||
input wire [31 : 0] s_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
|
||||
input wire [7 : 0] s_axi_arlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
|
||||
input wire [0 : 0] s_axi_arlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
|
||||
input wire [3 : 0] s_axi_arcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
|
||||
input wire [2 : 0] s_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
|
||||
input wire [3 : 0] s_axi_arqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARUSER" *)
|
||||
input wire [1023 : 0] s_axi_aruser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
|
||||
input wire s_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
|
||||
output wire s_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
|
||||
output wire [2 : 0] s_axi_rid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
|
||||
output wire [31 : 0] s_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
|
||||
output wire [1 : 0] s_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
|
||||
output wire s_axi_rlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RUSER" *)
|
||||
output wire [1023 : 0] s_axi_ruser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
|
||||
output wire s_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 200000000, ID_WIDTH 3, ADDR_WIDTH 32, AWUSER_WIDTH 1024, ARUSER_WIDTH 1024, WUSER_WIDTH 1024, RUSER_WIDTH 1024, BUSER_WIDTH 1024, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0, CLK_DOMAIN system_top_mig_7series_0_0_ui_clk, NUM_READ_THREA\
|
||||
DS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
|
||||
input wire s_axi_rready;
|
||||
|
||||
sc_axi2sc_v1_0_10_top #(
|
||||
.C_AXI_ADDR_WIDTH(32),
|
||||
.C_AXI_ID_WIDTH(3),
|
||||
.C_AXI_RDATA_WIDTH(32),
|
||||
.C_AXI_WDATA_WIDTH(32),
|
||||
.C_SC_ADDR_WIDTH(40),
|
||||
.C_SC_ID_WIDTH(3),
|
||||
.C_SC_RDATA_WIDTH(512),
|
||||
.C_SC_WDATA_WIDTH(512),
|
||||
.C_SC_RUSER_BITS_PER_BYTE(0),
|
||||
.C_SC_WUSER_BITS_PER_BYTE(0),
|
||||
.C_SC_ARUSER_WIDTH(0),
|
||||
.C_SC_AWUSER_WIDTH(0),
|
||||
.C_SC_BUSER_WIDTH(0),
|
||||
.C_MSC_ROUTE_WIDTH(1),
|
||||
.C_SSC_ROUTE_WIDTH(4),
|
||||
.C_AWPAYLD_WIDTH(150),
|
||||
.C_ARPAYLD_WIDTH(150),
|
||||
.C_WPAYLD_WIDTH(592),
|
||||
.C_RPAYLD_WIDTH(536),
|
||||
.C_BPAYLD_WIDTH(10)
|
||||
) inst (
|
||||
.aclk(aclk),
|
||||
.s_sc_r_req(s_sc_r_req),
|
||||
.s_sc_r_info(s_sc_r_info),
|
||||
.s_sc_r_send(s_sc_r_send),
|
||||
.s_sc_r_recv(s_sc_r_recv),
|
||||
.s_sc_r_payld(s_sc_r_payld),
|
||||
.s_sc_b_req(s_sc_b_req),
|
||||
.s_sc_b_info(s_sc_b_info),
|
||||
.s_sc_b_send(s_sc_b_send),
|
||||
.s_sc_b_recv(s_sc_b_recv),
|
||||
.s_sc_b_payld(s_sc_b_payld),
|
||||
.m_sc_ar_req(m_sc_ar_req),
|
||||
.m_sc_ar_info(m_sc_ar_info),
|
||||
.m_sc_ar_send(m_sc_ar_send),
|
||||
.m_sc_ar_recv(m_sc_ar_recv),
|
||||
.m_sc_ar_payld(m_sc_ar_payld),
|
||||
.m_sc_aw_req(m_sc_aw_req),
|
||||
.m_sc_aw_info(m_sc_aw_info),
|
||||
.m_sc_aw_send(m_sc_aw_send),
|
||||
.m_sc_aw_recv(m_sc_aw_recv),
|
||||
.m_sc_aw_payld(m_sc_aw_payld),
|
||||
.m_sc_w_req(m_sc_w_req),
|
||||
.m_sc_w_info(m_sc_w_info),
|
||||
.m_sc_w_send(m_sc_w_send),
|
||||
.m_sc_w_recv(m_sc_w_recv),
|
||||
.m_sc_w_payld(m_sc_w_payld),
|
||||
.s_axi_awid(s_axi_awid),
|
||||
.s_axi_awaddr(s_axi_awaddr),
|
||||
.s_axi_awlen(s_axi_awlen),
|
||||
.s_axi_awlock(s_axi_awlock),
|
||||
.s_axi_awcache(s_axi_awcache),
|
||||
.s_axi_awprot(s_axi_awprot),
|
||||
.s_axi_awqos(s_axi_awqos),
|
||||
.s_axi_awuser(s_axi_awuser),
|
||||
.s_axi_awvalid(s_axi_awvalid),
|
||||
.s_axi_awready(s_axi_awready),
|
||||
.s_axi_wdata(s_axi_wdata),
|
||||
.s_axi_wstrb(s_axi_wstrb),
|
||||
.s_axi_wlast(s_axi_wlast),
|
||||
.s_axi_wuser(s_axi_wuser),
|
||||
.s_axi_wvalid(s_axi_wvalid),
|
||||
.s_axi_wready(s_axi_wready),
|
||||
.s_axi_bid(s_axi_bid),
|
||||
.s_axi_bresp(s_axi_bresp),
|
||||
.s_axi_buser(s_axi_buser),
|
||||
.s_axi_bvalid(s_axi_bvalid),
|
||||
.s_axi_bready(s_axi_bready),
|
||||
.s_axi_arid(s_axi_arid),
|
||||
.s_axi_araddr(s_axi_araddr),
|
||||
.s_axi_arlen(s_axi_arlen),
|
||||
.s_axi_arlock(s_axi_arlock),
|
||||
.s_axi_arcache(s_axi_arcache),
|
||||
.s_axi_arprot(s_axi_arprot),
|
||||
.s_axi_arqos(s_axi_arqos),
|
||||
.s_axi_aruser(s_axi_aruser),
|
||||
.s_axi_arvalid(s_axi_arvalid),
|
||||
.s_axi_arready(s_axi_arready),
|
||||
.s_axi_rid(s_axi_rid),
|
||||
.s_axi_rdata(s_axi_rdata),
|
||||
.s_axi_rresp(s_axi_rresp),
|
||||
.s_axi_rlast(s_axi_rlast),
|
||||
.s_axi_ruser(s_axi_ruser),
|
||||
.s_axi_rvalid(s_axi_rvalid),
|
||||
.s_axi_rready(s_axi_rready)
|
||||
);
|
||||
endmodule
|
||||
+249
@@ -0,0 +1,249 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "bd_222a_sarn_0",
|
||||
"cell_name": "s00_ar_node",
|
||||
"component_reference": "xilinx.com:ip:sc_node:1.0",
|
||||
"ip_revision": "16",
|
||||
"gen_directory": ".",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"DISABLE_IP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FIFO_SIZE": [ { "value": "5", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FIFO_TYPE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FIFO_IP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FIFO_OUTPUT_REG": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ENABLE_PIPELINING": [ { "value": "0x01", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||
"SYNCHRONIZATION_STAGES": [ { "value": "3", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"NUM_SI": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"NUM_MI": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CHANNEL": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"USER_BITS_PER_BYTE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MAX_PAYLD_BYTES": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ARBITER_MODE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SC_ROUTE_WIDTH": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ID_WIDTH": [ { "value": "3", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PAYLD_WIDTH": [ { "value": "150", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ADDR_WIDTH": [ { "value": "40", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"USER_WIDTH": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S_PIPELINE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M_PIPELINE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M_SEND_PIPELINE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S_LATENCY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ACLK_RELATIONSHIP": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ACLKEN_CONVERSION": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"NUM_OUTSTANDING": [ { "value": "8", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S00_NUM_BYTES": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S01_NUM_BYTES": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S02_NUM_BYTES": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S03_NUM_BYTES": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S04_NUM_BYTES": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S05_NUM_BYTES": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S06_NUM_BYTES": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S07_NUM_BYTES": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S08_NUM_BYTES": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S09_NUM_BYTES": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S10_NUM_BYTES": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S11_NUM_BYTES": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S12_NUM_BYTES": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S13_NUM_BYTES": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S14_NUM_BYTES": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S15_NUM_BYTES": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M00_NUM_BYTES": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M01_NUM_BYTES": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M02_NUM_BYTES": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M03_NUM_BYTES": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M04_NUM_BYTES": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M05_NUM_BYTES": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M06_NUM_BYTES": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M07_NUM_BYTES": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M08_NUM_BYTES": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M09_NUM_BYTES": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M10_NUM_BYTES": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M11_NUM_BYTES": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M12_NUM_BYTES": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M13_NUM_BYTES": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M14_NUM_BYTES": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M15_NUM_BYTES": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S00_PRIORITY_ARB": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S01_PRIORITY_ARB": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S02_PRIORITY_ARB": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S03_PRIORITY_ARB": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S04_PRIORITY_ARB": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S05_PRIORITY_ARB": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S06_PRIORITY_ARB": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S07_PRIORITY_ARB": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S08_PRIORITY_ARB": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S09_PRIORITY_ARB": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S10_PRIORITY_ARB": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S11_PRIORITY_ARB": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S12_PRIORITY_ARB": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S13_PRIORITY_ARB": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S14_PRIORITY_ARB": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S15_PRIORITY_ARB": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "bd_222a_sarn_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_FAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_FIFO_IP": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DISABLE_IP": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_FIFO_SIZE": [ { "value": "5", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_FIFO_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_FIFO_OUTPUT_REG": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ENABLE_PIPELINING": [ { "value": "0x01", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_SYNCHRONIZATION_STAGES": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_SI": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_MI": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CHANNEL": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PAYLD_WIDTH": [ { "value": "150", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_NUM_BYTES_ARRAY": [ { "value": "0x00000004", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_M_NUM_BYTES_ARRAY": [ { "value": "0x00000040", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_PRIORITY_ARB_ARRAY": [ { "value": "0b0", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_USER_BITS_PER_BYTE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ARBITER_MODE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SC_ROUTE_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ID_WIDTH": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ADDR_WIDTH": [ { "value": "40", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MAX_PAYLD_BYTES": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_PIPELINE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_PIPELINE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_SEND_PIPELINE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_LATENCY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_OUTSTANDING": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ACLK_RELATIONSHIP": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ACLKEN_CONVERSION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "xilinx.com:zc706:part0:1.4" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z045" } ],
|
||||
"NEXTGEN_VERSAL": [ { "value": "0" } ],
|
||||
"PACKAGE": [ { "value": "ffg900" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "16" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "." } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../../../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2024.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"s_sc_aclk": [ { "direction": "in" } ],
|
||||
"s_sc_aresetn": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"s_sc_req": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_sc_info": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_sc_send": [ { "direction": "in", "size_left": "0", "size_right": "0" } ],
|
||||
"s_sc_recv": [ { "direction": "out", "size_left": "0", "size_right": "0" } ],
|
||||
"s_sc_payld": [ { "direction": "in", "size_left": "149", "size_right": "0" } ],
|
||||
"m_sc_aclk": [ { "direction": "in" } ],
|
||||
"m_sc_aresetn": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"m_sc_recv": [ { "direction": "in", "size_left": "0", "size_right": "0" } ],
|
||||
"m_sc_send": [ { "direction": "out", "size_left": "0", "size_right": "0" } ],
|
||||
"m_sc_req": [ { "direction": "out", "size_left": "0", "size_right": "0" } ],
|
||||
"m_sc_info": [ { "direction": "out", "size_left": "0", "size_right": "0" } ],
|
||||
"m_sc_payld": [ { "direction": "out", "size_left": "149", "size_right": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"S_SC": {
|
||||
"vlnv": "xilinx.com:interface:sc:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:sc_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"port_maps": {
|
||||
"INFO": [ { "physical_name": "s_sc_info" } ],
|
||||
"PAYLD": [ { "physical_name": "s_sc_payld" } ],
|
||||
"RECV": [ { "physical_name": "s_sc_recv" } ],
|
||||
"REQ": [ { "physical_name": "s_sc_req" } ],
|
||||
"SEND": [ { "physical_name": "s_sc_send" } ]
|
||||
}
|
||||
},
|
||||
"M_SC": {
|
||||
"vlnv": "xilinx.com:interface:sc:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:sc_rtl:1.0",
|
||||
"mode": "master",
|
||||
"port_maps": {
|
||||
"INFO": [ { "physical_name": "m_sc_info" } ],
|
||||
"PAYLD": [ { "physical_name": "m_sc_payld" } ],
|
||||
"RECV": [ { "physical_name": "m_sc_recv" } ],
|
||||
"REQ": [ { "physical_name": "m_sc_req" } ],
|
||||
"SEND": [ { "physical_name": "m_sc_send" } ]
|
||||
}
|
||||
},
|
||||
"aclk": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S_AXIS_ARB:M_AXIS_ARB:S_SC", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "s_sc_aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"ASSOCIATED_CLKEN": [ { "value": "s_sc_aclken", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "200000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_mig_7series_0_0_ui_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "s_sc_aclk" } ]
|
||||
}
|
||||
},
|
||||
"aresetn": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "s_sc_aresetn" } ]
|
||||
}
|
||||
},
|
||||
"m_sc_aclk": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "M_SC", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "m_sc_aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"ASSOCIATED_CLKEN": [ { "value": "m_sc_aclken", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "200000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_mig_7series_0_0_ui_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "m_sc_aclk" } ]
|
||||
}
|
||||
},
|
||||
"m_sc_aresetn": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "m_sc_aresetn" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+1866
File diff suppressed because it is too large
Load Diff
+186
@@ -0,0 +1,186 @@
|
||||
################################################################################
|
||||
# (c) Copyright 2013 Advanced Micro Devices, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Advanced Micro Devices, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# AMD, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) AMD shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or AMD had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# AMD products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of AMD products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
################################################################################
|
||||
create_waiver -type CDC -id {CDC-1} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_reg_fifo.inst_reg_fifo/gen_single_rank.inst_cntr/*}]]
|
||||
|
||||
create_waiver -type CDC -id {CDC-1} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_reg_fifo.inst_reg_fifo/gen_single_rank.*}]]
|
||||
|
||||
create_waiver -type CDC -id {CDC-1} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-from [get_pins -quiet -filter REF_PIN_NAME=~*C -of_objects [get_cells -hierarchical -filter {NAME =~ */inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_reg_fifo.inst_reg_fifo/inst_sample_cycle_ratio/gen_sample_cycle.slow_clk_div2_reg}]] \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_reg_fifo.inst_reg_fifo/inst_sample_cycle_ratio/gen_sample_cycle.posedge_finder_*_reg}]]
|
||||
|
||||
create_waiver -type CDC -id {CDC-1} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-from [get_pins -quiet -filter REF_PIN_NAME=~*C -of_objects [get_cells -hierarchical -filter {NAME =~ */inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_reg_fifo.inst_reg_fifo/inst_sample_cycle_ratio/gen_sample_cycle.slow_clk_div2_reg}]] \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_reg_fifo.inst_reg_fifo/inst_sample_cycle_ratio/gen_sample_cycle.sample_cycle_r_reg}]]
|
||||
|
||||
create_waiver -type CDC -id {CDC-1} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*CE -of_objects [get_cells -hierarchical -filter {NAME =~ */inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/gen_single_rank.data_reg[*]}]]
|
||||
|
||||
create_waiver -type CDC -id {CDC-1} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/inst_sample_cycle_ratio/gen_sample_cycle.posedge_finder_*_reg}]]
|
||||
|
||||
|
||||
create_waiver -type CDC -id {CDC-1} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/inst_sample_cycle_ratio/gen_sample_cycle.sample_cycle_r_reg}]]
|
||||
|
||||
create_waiver -type CDC -id {CDC-1} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/gen_single_rank.full_r_reg}]]
|
||||
|
||||
create_waiver -type CDC -id {CDC-1} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/gen_single_rank.inst_cntr/count_r_reg[*]}]]
|
||||
|
||||
create_waiver -type CDC -id {CDC-1} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/gen_single_rank.inst_cntr/is_zero_r_reg}]]
|
||||
|
||||
create_waiver -type CDC -id {CDC-1} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[*]}]]
|
||||
|
||||
create_waiver -type CDC -id {CDC-4} -user "sc_node" -desc "Reads to LUTRAM are asyncronous,no synchronizer for xpm configurations" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_related_clocks.*_addr*_sync_i_reg[*]}]]
|
||||
|
||||
create_waiver -type CDC -id {CDC-4} -user "sc_node" -desc "Reads to LUTRAM are asyncronous,no synchronizer for xpm configurations" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_related_clocks.*_addr*_sync_i_reg[*]}]]
|
||||
|
||||
create_waiver -type CDC -id {CDC-2} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_related_clocks.*_addr*_sync_i_reg[*]}]]
|
||||
|
||||
create_waiver -type CDC -id {CDC-2} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_related_clocks.*_addr*_sync_i_reg[*]}]]
|
||||
|
||||
create_waiver -type CDC -id {CDC-2} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_reg_fifo.inst_reg_fifo/inst_sample_cycle_ratio/gen_sample_cycle.gen_delay[*].sample_cycle_d_reg[*]}]]
|
||||
|
||||
create_waiver -type CDC -id {CDC-2} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/inst_sample_cycle_ratio/gen_sample_cycle.gen_delay[*].sample_cycle_d_reg[*]}]]
|
||||
|
||||
|
||||
create_waiver -type CDC -id {CDC-1} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*CE -of_objects [get_cells -hierarchical -filter {NAME =~ */inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_reg_fifo.inst_reg_fifo/gen_single_rank.data_reg[*]}]]
|
||||
|
||||
create_waiver -type CDC -id {CDC-10} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_reg_fifo.inst_reg_fifo/inst_sample_cycle_ratio/gen_sample_cycle.gen_delay[*].sample_cycle_d_reg[*]}]]
|
||||
|
||||
create_waiver -type CDC -id {CDC-10} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/inst_sample_cycle_ratio/gen_sample_cycle.gen_delay[*].sample_cycle_d_reg[*]}]]
|
||||
|
||||
create_waiver -type CDC -id {CDC-1} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_related_clocks.*_addr*_sync_i_reg[*]}]]
|
||||
|
||||
create_waiver -type CDC -id {CDC-1} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_related_clocks.*_addr*_sync_i_reg[*]}]]
|
||||
|
||||
create_waiver -type CDC -id {CDC-1} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/gen_single_rank.empty_*_reg}]]
|
||||
|
||||
create_waiver -type CDC -id {CDC-13} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/inst_sample_cycle_ratio/gen_sample_cycle.gen_delay[*].sample_cycle_d_reg[*]_sr*}]]
|
||||
|
||||
create_waiver -type CDC -id {CDC-1} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst_mi_handler/gen_normal_area.gen_no_downsizer.inst_fifo_req_suppress/gen_pipe[*].pipe_reg[*][*]}]]
|
||||
|
||||
create_waiver -type CDC -id {CDC-1} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst_mi_handler/gen_normal_area.inst_fifo_node_payld_pop_pipeline/gen_pipe[*].pipe_reg[*][*]}]]
|
||||
|
||||
create_waiver -type CDC -id {CDC-13} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_reg_fifo.inst_reg_fifo/inst_sample_cycle_ratio/gen_sample_cycle.gen_delay[*].sample_cycle_d_reg[*]_sr*}]]
|
||||
|
||||
create_waiver -type CDC -id {CDC-1} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst_mi_handler/gen_normal_area.gen_no_downsizer.inst_fifo_req_suppress/gen_pipe[*].pipe_reg[*][*]}]]
|
||||
|
||||
create_waiver -type CDC -id {CDC-10} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst_mi_handler/gen_normal_area.inst_fifo_node_payld_pop_pipeline/gen_pipe[*].pipe_reg[*][*]}]]
|
||||
|
||||
create_waiver -type CDC -id {CDC-1} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst_mi_handler/gen_normal_area.gen_downsizer.inst_downsizer/active_reg}]]
|
||||
|
||||
create_waiver -type CDC -id {CDC-1} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*CE -of_objects [get_cells -hierarchical -filter {NAME =~ */inst_mi_handler/gen_normal_area.gen_downsizer.inst_downsizer/downsizer_pntr_reg[*]}]]
|
||||
|
||||
create_waiver -type CDC -id {CDC-1} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*CE -of_objects [get_cells -hierarchical -filter {NAME =~ */inst_mi_handler/gen_normal_area.gen_downsizer.inst_downsizer/downsizer_repeat_reg[*]}]]
|
||||
|
||||
create_waiver -type CDC -id {CDC-2} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst_mi_handler/gen_normal_area.inst_fifo_node_payld_pop_pipeline/gen_pipe[*].pipe_reg[*][*]}]]
|
||||
|
||||
create_waiver -type CDC -id {CDC-1} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst_mi_handler/gen_normal_area.gen_downsizer.inst_downsizer/downsizer_pntr_reg[*]}]]
|
||||
|
||||
create_waiver -type CDC -id {CDC-1} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst_mi_handler/gen_normal_area.gen_downsizer.inst_downsizer/downsizer_repeat_reg[*]}]]
|
||||
|
||||
create_waiver -type CDC -id {CDC-1} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst_mi_handler/gen_normal_area.inst_fifo_send/gen_AB_reg_slice.payld_*_reg[*]}]]
|
||||
|
||||
create_waiver -type CDC -id {CDC-10} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst_mi_handler/gen_normal_area.gen_downsizer.inst_downsizer/inst_payld_xfer_data/gen_pipe[*].pipe_reg[*][*]}]]
|
||||
|
||||
create_waiver -type CDC -id {CDC-4} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_fifo_wrapper.inst_fifo/gen_xpm_fifo_async.inst_xpm_fifo_async/gnuram_async_fifo.xpm_fifo_base_inst/gen_pntr_pf_rc.wpr_rc_reg/reg_out_i_reg[*]}]]
|
||||
|
||||
create_waiver -type CDC -id {CDC-4} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_fifo_wrapper.inst_fifo/gen_xpm_fifo_async.inst_xpm_fifo_async/gnuram_async_fifo.xpm_fifo_base_inst/gen_pntr_pf_rc.wpr_rc_reg/reg_out_i_reg[*]}]]
|
||||
|
||||
|
||||
create_waiver -type CDC -id {CDC-4} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_fifo_wrapper.inst_fifo/gen_xpm_fifo_async.inst_xpm_fifo_async/gnuram_async_fifo.xpm_fifo_base_inst/gen_pntr_pf_rc.rpw_rc_reg/reg_out_i_reg[*]}]]
|
||||
|
||||
create_waiver -type CDC -id {CDC-4} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_fifo_wrapper.inst_fifo/gen_xpm_fifo_async.inst_xpm_fifo_async/gnuram_async_fifo.xpm_fifo_base_inst/gen_pntr_pf_rc.rpw_rc_reg/reg_out_i_reg[*]}]]
|
||||
|
||||
|
||||
create_waiver -type CDC -id {CDC-1} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst_mi_handler/gen_normal_area.gen_downsizer.inst_downsizer/gen_*_payld.inst_downsizer_node_payld_pipe/gen_pipe[*].pipe_reg[*][*]}]]
|
||||
|
||||
create_waiver -type CDC -id {CDC-1} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/gen_single_rank.empty_*_reg*}]]
|
||||
|
||||
create_waiver -type CDC -id {CDC-13} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/inst_sample_cycle_ratio/gen_sample_cycle.gen_delay[*].sample_cycle_d_reg[*]_srl*}]]
|
||||
|
||||
+52
@@ -0,0 +1,52 @@
|
||||
################################################################################
|
||||
# (c) Copyright 2013 Advanced Micro Devices, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Advanced Micro Devices, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# AMD, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) AMD shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or AMD had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# AMD products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of AMD products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
################################################################################
|
||||
|
||||
create_clock -period 100.0 -name s_sc_aclk [get_ports s_sc_aclk]
|
||||
|
||||
|
||||
+162
@@ -0,0 +1,162 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:sc_node:1.0
|
||||
// IP Revision: 16
|
||||
|
||||
(* X_CORE_INFO = "sc_node_v1_0_16_top,Vivado 2024.1" *)
|
||||
(* CHECK_LICENSE_TYPE = "bd_222a_sarn_0,sc_node_v1_0_16_top,{}" *)
|
||||
(* CORE_GENERATION_INFO = "bd_222a_sarn_0,sc_node_v1_0_16_top,{x_ipProduct=Vivado 2024.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=sc_node,x_ipVersion=1.0,x_ipCoreRevision=16,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_FIFO_IP=0,C_DISABLE_IP=0,C_FIFO_SIZE=5,C_FIFO_TYPE=0,C_FIFO_OUTPUT_REG=1,C_ENABLE_PIPELINING=0x01,C_SYNCHRONIZATION_STAGES=3,C_NUM_SI=1,C_NUM_MI=1,C_CHANNEL=2,C_PAYLD_WIDTH=150,C_S_NUM_BYTES_ARRAY=0x00000004,C_M_NUM_BYTES_ARRAY=0x00000040,C_PRIORITY_ARB_ARRAY=0b0,C_USER_BITS_PER_BYTE=0,C_\
|
||||
ARBITER_MODE=1,C_SC_ROUTE_WIDTH=1,C_ID_WIDTH=3,C_ADDR_WIDTH=40,C_USER_WIDTH=0,C_MAX_PAYLD_BYTES=64,C_S_PIPELINE=0,C_M_PIPELINE=0,C_M_SEND_PIPELINE=1,C_S_LATENCY=0,C_NUM_OUTSTANDING=8,C_ACLK_RELATIONSHIP=1,C_ACLKEN_CONVERSION=0}" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_222a_sarn_0 (
|
||||
s_sc_aclk,
|
||||
s_sc_aresetn,
|
||||
s_sc_req,
|
||||
s_sc_info,
|
||||
s_sc_send,
|
||||
s_sc_recv,
|
||||
s_sc_payld,
|
||||
m_sc_aclk,
|
||||
m_sc_aresetn,
|
||||
m_sc_recv,
|
||||
m_sc_send,
|
||||
m_sc_req,
|
||||
m_sc_info,
|
||||
m_sc_payld
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF S_AXIS_ARB:M_AXIS_ARB:S_SC, ASSOCIATED_RESET s_sc_aresetn, ASSOCIATED_CLKEN s_sc_aclken, FREQ_HZ 200000000, FREQ_TOLERANCE_HZ 0, PHASE 0, CLK_DOMAIN system_top_mig_7series_0_0_ui_clk, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk CLK" *)
|
||||
input wire s_sc_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 aresetn RST" *)
|
||||
input wire s_sc_aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC REQ" *)
|
||||
input wire [0 : 0] s_sc_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC INFO" *)
|
||||
input wire [0 : 0] s_sc_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC SEND" *)
|
||||
input wire [0 : 0] s_sc_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC RECV" *)
|
||||
output wire [0 : 0] s_sc_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC PAYLD" *)
|
||||
input wire [149 : 0] s_sc_payld;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_sc_aclk, ASSOCIATED_BUSIF M_SC, ASSOCIATED_RESET m_sc_aresetn, ASSOCIATED_CLKEN m_sc_aclken, FREQ_HZ 200000000, FREQ_TOLERANCE_HZ 0, PHASE 0, CLK_DOMAIN system_top_mig_7series_0_0_ui_clk, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 m_sc_aclk CLK" *)
|
||||
input wire m_sc_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_sc_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 m_sc_aresetn RST" *)
|
||||
input wire m_sc_aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC RECV" *)
|
||||
input wire [0 : 0] m_sc_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC SEND" *)
|
||||
output wire [0 : 0] m_sc_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC REQ" *)
|
||||
output wire [0 : 0] m_sc_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC INFO" *)
|
||||
output wire [0 : 0] m_sc_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC PAYLD" *)
|
||||
output wire [149 : 0] m_sc_payld;
|
||||
|
||||
sc_node_v1_0_16_top #(
|
||||
.C_FAMILY("zynq"),
|
||||
.C_FIFO_IP(0),
|
||||
.C_DISABLE_IP(0),
|
||||
.C_FIFO_SIZE(5),
|
||||
.C_FIFO_TYPE(0),
|
||||
.C_FIFO_OUTPUT_REG(1),
|
||||
.C_ENABLE_PIPELINING(8'H01),
|
||||
.C_SYNCHRONIZATION_STAGES(3),
|
||||
.C_NUM_SI(1),
|
||||
.C_NUM_MI(1),
|
||||
.C_CHANNEL(2),
|
||||
.C_PAYLD_WIDTH(150),
|
||||
.C_S_NUM_BYTES_ARRAY(32'H00000004),
|
||||
.C_M_NUM_BYTES_ARRAY(32'H00000040),
|
||||
.C_PRIORITY_ARB_ARRAY(1'B0),
|
||||
.C_USER_BITS_PER_BYTE(0),
|
||||
.C_ARBITER_MODE(1),
|
||||
.C_SC_ROUTE_WIDTH(1),
|
||||
.C_ID_WIDTH(3),
|
||||
.C_ADDR_WIDTH(40),
|
||||
.C_USER_WIDTH(0),
|
||||
.C_MAX_PAYLD_BYTES(64),
|
||||
.C_S_PIPELINE(0),
|
||||
.C_M_PIPELINE(0),
|
||||
.C_M_SEND_PIPELINE(1),
|
||||
.C_S_LATENCY(0),
|
||||
.C_NUM_OUTSTANDING(8),
|
||||
.C_ACLK_RELATIONSHIP(1),
|
||||
.C_ACLKEN_CONVERSION(0)
|
||||
) inst (
|
||||
.s_sc_aclk(s_sc_aclk),
|
||||
.s_sc_aclken(1'H1),
|
||||
.s_sc_aresetn(s_sc_aresetn),
|
||||
.s_sc_req(s_sc_req),
|
||||
.s_sc_info(s_sc_info),
|
||||
.s_sc_send(s_sc_send),
|
||||
.s_sc_recv(s_sc_recv),
|
||||
.s_sc_payld(s_sc_payld),
|
||||
.m_sc_aclk(m_sc_aclk),
|
||||
.m_sc_aclken(1'H1),
|
||||
.m_sc_aresetn(m_sc_aresetn),
|
||||
.m_sc_recv(m_sc_recv),
|
||||
.m_sc_send(m_sc_send),
|
||||
.m_sc_req(m_sc_req),
|
||||
.m_sc_info(m_sc_info),
|
||||
.m_sc_payld(m_sc_payld),
|
||||
.m_axis_arb_tvalid(),
|
||||
.m_axis_arb_tready(1'H1),
|
||||
.m_axis_arb_tdata(),
|
||||
.s_axis_arb_tvalid(1'H0),
|
||||
.s_axis_arb_tready(),
|
||||
.s_axis_arb_tdata(16'B0)
|
||||
);
|
||||
endmodule
|
||||
+249
@@ -0,0 +1,249 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "bd_222a_srn_0",
|
||||
"cell_name": "s00_r_node",
|
||||
"component_reference": "xilinx.com:ip:sc_node:1.0",
|
||||
"ip_revision": "16",
|
||||
"gen_directory": ".",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"DISABLE_IP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FIFO_SIZE": [ { "value": "5", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FIFO_TYPE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FIFO_IP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FIFO_OUTPUT_REG": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ENABLE_PIPELINING": [ { "value": "0x01", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||
"SYNCHRONIZATION_STAGES": [ { "value": "3", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"NUM_SI": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"NUM_MI": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CHANNEL": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"USER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MAX_PAYLD_BYTES": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ARBITER_MODE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SC_ROUTE_WIDTH": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ID_WIDTH": [ { "value": "3", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PAYLD_WIDTH": [ { "value": "536", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ADDR_WIDTH": [ { "value": "40", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"USER_WIDTH": [ { "value": "512", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S_PIPELINE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M_PIPELINE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M_SEND_PIPELINE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S_LATENCY": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ACLK_RELATIONSHIP": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ACLKEN_CONVERSION": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"NUM_OUTSTANDING": [ { "value": "8", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S00_NUM_BYTES": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S01_NUM_BYTES": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S02_NUM_BYTES": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S03_NUM_BYTES": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S04_NUM_BYTES": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S05_NUM_BYTES": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S06_NUM_BYTES": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S07_NUM_BYTES": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S08_NUM_BYTES": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S09_NUM_BYTES": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S10_NUM_BYTES": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S11_NUM_BYTES": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S12_NUM_BYTES": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S13_NUM_BYTES": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S14_NUM_BYTES": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S15_NUM_BYTES": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M00_NUM_BYTES": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M01_NUM_BYTES": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M02_NUM_BYTES": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M03_NUM_BYTES": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M04_NUM_BYTES": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M05_NUM_BYTES": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M06_NUM_BYTES": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M07_NUM_BYTES": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M08_NUM_BYTES": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M09_NUM_BYTES": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M10_NUM_BYTES": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M11_NUM_BYTES": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M12_NUM_BYTES": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M13_NUM_BYTES": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M14_NUM_BYTES": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M15_NUM_BYTES": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S00_PRIORITY_ARB": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S01_PRIORITY_ARB": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S02_PRIORITY_ARB": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S03_PRIORITY_ARB": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S04_PRIORITY_ARB": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S05_PRIORITY_ARB": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S06_PRIORITY_ARB": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S07_PRIORITY_ARB": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S08_PRIORITY_ARB": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S09_PRIORITY_ARB": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S10_PRIORITY_ARB": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S11_PRIORITY_ARB": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S12_PRIORITY_ARB": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S13_PRIORITY_ARB": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S14_PRIORITY_ARB": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S15_PRIORITY_ARB": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "bd_222a_srn_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_FAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_FIFO_IP": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DISABLE_IP": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_FIFO_SIZE": [ { "value": "5", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_FIFO_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_FIFO_OUTPUT_REG": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ENABLE_PIPELINING": [ { "value": "0x01", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_SYNCHRONIZATION_STAGES": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_SI": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_MI": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CHANNEL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PAYLD_WIDTH": [ { "value": "536", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_NUM_BYTES_ARRAY": [ { "value": "0x00000040", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_M_NUM_BYTES_ARRAY": [ { "value": "0x00000004", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_PRIORITY_ARB_ARRAY": [ { "value": "0b0", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_USER_BITS_PER_BYTE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ARBITER_MODE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SC_ROUTE_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ID_WIDTH": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ADDR_WIDTH": [ { "value": "40", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USER_WIDTH": [ { "value": "512", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MAX_PAYLD_BYTES": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_PIPELINE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_PIPELINE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_SEND_PIPELINE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_OUTSTANDING": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ACLK_RELATIONSHIP": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ACLKEN_CONVERSION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "xilinx.com:zc706:part0:1.4" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z045" } ],
|
||||
"NEXTGEN_VERSAL": [ { "value": "0" } ],
|
||||
"PACKAGE": [ { "value": "ffg900" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "16" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "." } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../../../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2024.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"s_sc_aclk": [ { "direction": "in" } ],
|
||||
"s_sc_aresetn": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"s_sc_req": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_sc_info": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_sc_send": [ { "direction": "in", "size_left": "0", "size_right": "0" } ],
|
||||
"s_sc_recv": [ { "direction": "out", "size_left": "0", "size_right": "0" } ],
|
||||
"s_sc_payld": [ { "direction": "in", "size_left": "535", "size_right": "0" } ],
|
||||
"m_sc_aclk": [ { "direction": "in" } ],
|
||||
"m_sc_aresetn": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"m_sc_recv": [ { "direction": "in", "size_left": "0", "size_right": "0" } ],
|
||||
"m_sc_send": [ { "direction": "out", "size_left": "0", "size_right": "0" } ],
|
||||
"m_sc_req": [ { "direction": "out", "size_left": "0", "size_right": "0" } ],
|
||||
"m_sc_info": [ { "direction": "out", "size_left": "0", "size_right": "0" } ],
|
||||
"m_sc_payld": [ { "direction": "out", "size_left": "535", "size_right": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"S_SC": {
|
||||
"vlnv": "xilinx.com:interface:sc:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:sc_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"port_maps": {
|
||||
"INFO": [ { "physical_name": "s_sc_info" } ],
|
||||
"PAYLD": [ { "physical_name": "s_sc_payld" } ],
|
||||
"RECV": [ { "physical_name": "s_sc_recv" } ],
|
||||
"REQ": [ { "physical_name": "s_sc_req" } ],
|
||||
"SEND": [ { "physical_name": "s_sc_send" } ]
|
||||
}
|
||||
},
|
||||
"M_SC": {
|
||||
"vlnv": "xilinx.com:interface:sc:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:sc_rtl:1.0",
|
||||
"mode": "master",
|
||||
"port_maps": {
|
||||
"INFO": [ { "physical_name": "m_sc_info" } ],
|
||||
"PAYLD": [ { "physical_name": "m_sc_payld" } ],
|
||||
"RECV": [ { "physical_name": "m_sc_recv" } ],
|
||||
"REQ": [ { "physical_name": "m_sc_req" } ],
|
||||
"SEND": [ { "physical_name": "m_sc_send" } ]
|
||||
}
|
||||
},
|
||||
"aclk": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S_AXIS_ARB:M_AXIS_ARB:S_SC", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "s_sc_aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"ASSOCIATED_CLKEN": [ { "value": "s_sc_aclken", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "200000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_mig_7series_0_0_ui_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "s_sc_aclk" } ]
|
||||
}
|
||||
},
|
||||
"aresetn": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "s_sc_aresetn" } ]
|
||||
}
|
||||
},
|
||||
"m_sc_aclk": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "M_SC", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "m_sc_aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"ASSOCIATED_CLKEN": [ { "value": "m_sc_aclken", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "200000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_top_mig_7series_0_0_ui_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "m_sc_aclk" } ]
|
||||
}
|
||||
},
|
||||
"m_sc_aresetn": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "m_sc_aresetn" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+1867
File diff suppressed because it is too large
Load Diff
+186
@@ -0,0 +1,186 @@
|
||||
################################################################################
|
||||
# (c) Copyright 2013 Advanced Micro Devices, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Advanced Micro Devices, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# AMD, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) AMD shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or AMD had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# AMD products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of AMD products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
################################################################################
|
||||
create_waiver -type CDC -id {CDC-1} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_reg_fifo.inst_reg_fifo/gen_single_rank.inst_cntr/*}]]
|
||||
|
||||
create_waiver -type CDC -id {CDC-1} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_reg_fifo.inst_reg_fifo/gen_single_rank.*}]]
|
||||
|
||||
create_waiver -type CDC -id {CDC-1} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-from [get_pins -quiet -filter REF_PIN_NAME=~*C -of_objects [get_cells -hierarchical -filter {NAME =~ */inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_reg_fifo.inst_reg_fifo/inst_sample_cycle_ratio/gen_sample_cycle.slow_clk_div2_reg}]] \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_reg_fifo.inst_reg_fifo/inst_sample_cycle_ratio/gen_sample_cycle.posedge_finder_*_reg}]]
|
||||
|
||||
create_waiver -type CDC -id {CDC-1} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-from [get_pins -quiet -filter REF_PIN_NAME=~*C -of_objects [get_cells -hierarchical -filter {NAME =~ */inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_reg_fifo.inst_reg_fifo/inst_sample_cycle_ratio/gen_sample_cycle.slow_clk_div2_reg}]] \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_reg_fifo.inst_reg_fifo/inst_sample_cycle_ratio/gen_sample_cycle.sample_cycle_r_reg}]]
|
||||
|
||||
create_waiver -type CDC -id {CDC-1} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*CE -of_objects [get_cells -hierarchical -filter {NAME =~ */inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/gen_single_rank.data_reg[*]}]]
|
||||
|
||||
create_waiver -type CDC -id {CDC-1} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/inst_sample_cycle_ratio/gen_sample_cycle.posedge_finder_*_reg}]]
|
||||
|
||||
|
||||
create_waiver -type CDC -id {CDC-1} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/inst_sample_cycle_ratio/gen_sample_cycle.sample_cycle_r_reg}]]
|
||||
|
||||
create_waiver -type CDC -id {CDC-1} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/gen_single_rank.full_r_reg}]]
|
||||
|
||||
create_waiver -type CDC -id {CDC-1} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/gen_single_rank.inst_cntr/count_r_reg[*]}]]
|
||||
|
||||
create_waiver -type CDC -id {CDC-1} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/gen_single_rank.inst_cntr/is_zero_r_reg}]]
|
||||
|
||||
create_waiver -type CDC -id {CDC-1} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[*]}]]
|
||||
|
||||
create_waiver -type CDC -id {CDC-4} -user "sc_node" -desc "Reads to LUTRAM are asyncronous,no synchronizer for xpm configurations" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_related_clocks.*_addr*_sync_i_reg[*]}]]
|
||||
|
||||
create_waiver -type CDC -id {CDC-4} -user "sc_node" -desc "Reads to LUTRAM are asyncronous,no synchronizer for xpm configurations" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_related_clocks.*_addr*_sync_i_reg[*]}]]
|
||||
|
||||
create_waiver -type CDC -id {CDC-2} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_related_clocks.*_addr*_sync_i_reg[*]}]]
|
||||
|
||||
create_waiver -type CDC -id {CDC-2} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_related_clocks.*_addr*_sync_i_reg[*]}]]
|
||||
|
||||
create_waiver -type CDC -id {CDC-2} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_reg_fifo.inst_reg_fifo/inst_sample_cycle_ratio/gen_sample_cycle.gen_delay[*].sample_cycle_d_reg[*]}]]
|
||||
|
||||
create_waiver -type CDC -id {CDC-2} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/inst_sample_cycle_ratio/gen_sample_cycle.gen_delay[*].sample_cycle_d_reg[*]}]]
|
||||
|
||||
|
||||
create_waiver -type CDC -id {CDC-1} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*CE -of_objects [get_cells -hierarchical -filter {NAME =~ */inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_reg_fifo.inst_reg_fifo/gen_single_rank.data_reg[*]}]]
|
||||
|
||||
create_waiver -type CDC -id {CDC-10} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_reg_fifo.inst_reg_fifo/inst_sample_cycle_ratio/gen_sample_cycle.gen_delay[*].sample_cycle_d_reg[*]}]]
|
||||
|
||||
create_waiver -type CDC -id {CDC-10} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/inst_sample_cycle_ratio/gen_sample_cycle.gen_delay[*].sample_cycle_d_reg[*]}]]
|
||||
|
||||
create_waiver -type CDC -id {CDC-1} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_related_clocks.*_addr*_sync_i_reg[*]}]]
|
||||
|
||||
create_waiver -type CDC -id {CDC-1} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_related_clocks.*_addr*_sync_i_reg[*]}]]
|
||||
|
||||
create_waiver -type CDC -id {CDC-1} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/gen_single_rank.empty_*_reg}]]
|
||||
|
||||
create_waiver -type CDC -id {CDC-13} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/inst_sample_cycle_ratio/gen_sample_cycle.gen_delay[*].sample_cycle_d_reg[*]_sr*}]]
|
||||
|
||||
create_waiver -type CDC -id {CDC-1} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst_mi_handler/gen_normal_area.gen_no_downsizer.inst_fifo_req_suppress/gen_pipe[*].pipe_reg[*][*]}]]
|
||||
|
||||
create_waiver -type CDC -id {CDC-1} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst_mi_handler/gen_normal_area.inst_fifo_node_payld_pop_pipeline/gen_pipe[*].pipe_reg[*][*]}]]
|
||||
|
||||
create_waiver -type CDC -id {CDC-13} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_reg_fifo.inst_reg_fifo/inst_sample_cycle_ratio/gen_sample_cycle.gen_delay[*].sample_cycle_d_reg[*]_sr*}]]
|
||||
|
||||
create_waiver -type CDC -id {CDC-1} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst_mi_handler/gen_normal_area.gen_no_downsizer.inst_fifo_req_suppress/gen_pipe[*].pipe_reg[*][*]}]]
|
||||
|
||||
create_waiver -type CDC -id {CDC-10} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst_mi_handler/gen_normal_area.inst_fifo_node_payld_pop_pipeline/gen_pipe[*].pipe_reg[*][*]}]]
|
||||
|
||||
create_waiver -type CDC -id {CDC-1} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst_mi_handler/gen_normal_area.gen_downsizer.inst_downsizer/active_reg}]]
|
||||
|
||||
create_waiver -type CDC -id {CDC-1} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*CE -of_objects [get_cells -hierarchical -filter {NAME =~ */inst_mi_handler/gen_normal_area.gen_downsizer.inst_downsizer/downsizer_pntr_reg[*]}]]
|
||||
|
||||
create_waiver -type CDC -id {CDC-1} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*CE -of_objects [get_cells -hierarchical -filter {NAME =~ */inst_mi_handler/gen_normal_area.gen_downsizer.inst_downsizer/downsizer_repeat_reg[*]}]]
|
||||
|
||||
create_waiver -type CDC -id {CDC-2} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst_mi_handler/gen_normal_area.inst_fifo_node_payld_pop_pipeline/gen_pipe[*].pipe_reg[*][*]}]]
|
||||
|
||||
create_waiver -type CDC -id {CDC-1} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst_mi_handler/gen_normal_area.gen_downsizer.inst_downsizer/downsizer_pntr_reg[*]}]]
|
||||
|
||||
create_waiver -type CDC -id {CDC-1} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst_mi_handler/gen_normal_area.gen_downsizer.inst_downsizer/downsizer_repeat_reg[*]}]]
|
||||
|
||||
create_waiver -type CDC -id {CDC-1} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst_mi_handler/gen_normal_area.inst_fifo_send/gen_AB_reg_slice.payld_*_reg[*]}]]
|
||||
|
||||
create_waiver -type CDC -id {CDC-10} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst_mi_handler/gen_normal_area.gen_downsizer.inst_downsizer/inst_payld_xfer_data/gen_pipe[*].pipe_reg[*][*]}]]
|
||||
|
||||
create_waiver -type CDC -id {CDC-4} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_fifo_wrapper.inst_fifo/gen_xpm_fifo_async.inst_xpm_fifo_async/gnuram_async_fifo.xpm_fifo_base_inst/gen_pntr_pf_rc.wpr_rc_reg/reg_out_i_reg[*]}]]
|
||||
|
||||
create_waiver -type CDC -id {CDC-4} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_fifo_wrapper.inst_fifo/gen_xpm_fifo_async.inst_xpm_fifo_async/gnuram_async_fifo.xpm_fifo_base_inst/gen_pntr_pf_rc.wpr_rc_reg/reg_out_i_reg[*]}]]
|
||||
|
||||
|
||||
create_waiver -type CDC -id {CDC-4} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_fifo_wrapper.inst_fifo/gen_xpm_fifo_async.inst_xpm_fifo_async/gnuram_async_fifo.xpm_fifo_base_inst/gen_pntr_pf_rc.rpw_rc_reg/reg_out_i_reg[*]}]]
|
||||
|
||||
create_waiver -type CDC -id {CDC-4} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_fifo_wrapper.inst_fifo/gen_xpm_fifo_async.inst_xpm_fifo_async/gnuram_async_fifo.xpm_fifo_base_inst/gen_pntr_pf_rc.rpw_rc_reg/reg_out_i_reg[*]}]]
|
||||
|
||||
|
||||
create_waiver -type CDC -id {CDC-1} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst_mi_handler/gen_normal_area.gen_downsizer.inst_downsizer/gen_*_payld.inst_downsizer_node_payld_pipe/gen_pipe[*].pipe_reg[*][*]}]]
|
||||
|
||||
create_waiver -type CDC -id {CDC-1} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/gen_single_rank.empty_*_reg*}]]
|
||||
|
||||
create_waiver -type CDC -id {CDC-13} -user "sc_node" -desc "Timing uncritical paths" -tags "1166090" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/inst_sample_cycle_ratio/gen_sample_cycle.gen_delay[*].sample_cycle_d_reg[*]_srl*}]]
|
||||
|
||||
+52
@@ -0,0 +1,52 @@
|
||||
################################################################################
|
||||
# (c) Copyright 2013 Advanced Micro Devices, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Advanced Micro Devices, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# AMD, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) AMD shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or AMD had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# AMD products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of AMD products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
################################################################################
|
||||
|
||||
create_clock -period 100.0 -name s_sc_aclk [get_ports s_sc_aclk]
|
||||
|
||||
|
||||
+162
@@ -0,0 +1,162 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:sc_node:1.0
|
||||
// IP Revision: 16
|
||||
|
||||
(* X_CORE_INFO = "sc_node_v1_0_16_top,Vivado 2024.1" *)
|
||||
(* CHECK_LICENSE_TYPE = "bd_222a_srn_0,sc_node_v1_0_16_top,{}" *)
|
||||
(* CORE_GENERATION_INFO = "bd_222a_srn_0,sc_node_v1_0_16_top,{x_ipProduct=Vivado 2024.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=sc_node,x_ipVersion=1.0,x_ipCoreRevision=16,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_FIFO_IP=0,C_DISABLE_IP=0,C_FIFO_SIZE=5,C_FIFO_TYPE=0,C_FIFO_OUTPUT_REG=1,C_ENABLE_PIPELINING=0x01,C_SYNCHRONIZATION_STAGES=3,C_NUM_SI=1,C_NUM_MI=1,C_CHANNEL=0,C_PAYLD_WIDTH=536,C_S_NUM_BYTES_ARRAY=0x00000040,C_M_NUM_BYTES_ARRAY=0x00000004,C_PRIORITY_ARB_ARRAY=0b0,C_USER_BITS_PER_BYTE=0,C_A\
|
||||
RBITER_MODE=1,C_SC_ROUTE_WIDTH=4,C_ID_WIDTH=3,C_ADDR_WIDTH=40,C_USER_WIDTH=512,C_MAX_PAYLD_BYTES=64,C_S_PIPELINE=0,C_M_PIPELINE=0,C_M_SEND_PIPELINE=0,C_S_LATENCY=1,C_NUM_OUTSTANDING=8,C_ACLK_RELATIONSHIP=1,C_ACLKEN_CONVERSION=0}" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_222a_srn_0 (
|
||||
s_sc_aclk,
|
||||
s_sc_aresetn,
|
||||
s_sc_req,
|
||||
s_sc_info,
|
||||
s_sc_send,
|
||||
s_sc_recv,
|
||||
s_sc_payld,
|
||||
m_sc_aclk,
|
||||
m_sc_aresetn,
|
||||
m_sc_recv,
|
||||
m_sc_send,
|
||||
m_sc_req,
|
||||
m_sc_info,
|
||||
m_sc_payld
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF S_AXIS_ARB:M_AXIS_ARB:S_SC, ASSOCIATED_RESET s_sc_aresetn, ASSOCIATED_CLKEN s_sc_aclken, FREQ_HZ 200000000, FREQ_TOLERANCE_HZ 0, PHASE 0, CLK_DOMAIN system_top_mig_7series_0_0_ui_clk, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk CLK" *)
|
||||
input wire s_sc_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 aresetn RST" *)
|
||||
input wire s_sc_aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC REQ" *)
|
||||
input wire [0 : 0] s_sc_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC INFO" *)
|
||||
input wire [0 : 0] s_sc_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC SEND" *)
|
||||
input wire [0 : 0] s_sc_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC RECV" *)
|
||||
output wire [0 : 0] s_sc_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC PAYLD" *)
|
||||
input wire [535 : 0] s_sc_payld;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_sc_aclk, ASSOCIATED_BUSIF M_SC, ASSOCIATED_RESET m_sc_aresetn, ASSOCIATED_CLKEN m_sc_aclken, FREQ_HZ 200000000, FREQ_TOLERANCE_HZ 0, PHASE 0, CLK_DOMAIN system_top_mig_7series_0_0_ui_clk, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 m_sc_aclk CLK" *)
|
||||
input wire m_sc_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_sc_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 m_sc_aresetn RST" *)
|
||||
input wire m_sc_aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC RECV" *)
|
||||
input wire [0 : 0] m_sc_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC SEND" *)
|
||||
output wire [0 : 0] m_sc_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC REQ" *)
|
||||
output wire [0 : 0] m_sc_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC INFO" *)
|
||||
output wire [0 : 0] m_sc_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC PAYLD" *)
|
||||
output wire [535 : 0] m_sc_payld;
|
||||
|
||||
sc_node_v1_0_16_top #(
|
||||
.C_FAMILY("zynq"),
|
||||
.C_FIFO_IP(0),
|
||||
.C_DISABLE_IP(0),
|
||||
.C_FIFO_SIZE(5),
|
||||
.C_FIFO_TYPE(0),
|
||||
.C_FIFO_OUTPUT_REG(1),
|
||||
.C_ENABLE_PIPELINING(8'H01),
|
||||
.C_SYNCHRONIZATION_STAGES(3),
|
||||
.C_NUM_SI(1),
|
||||
.C_NUM_MI(1),
|
||||
.C_CHANNEL(0),
|
||||
.C_PAYLD_WIDTH(536),
|
||||
.C_S_NUM_BYTES_ARRAY(32'H00000040),
|
||||
.C_M_NUM_BYTES_ARRAY(32'H00000004),
|
||||
.C_PRIORITY_ARB_ARRAY(1'B0),
|
||||
.C_USER_BITS_PER_BYTE(0),
|
||||
.C_ARBITER_MODE(1),
|
||||
.C_SC_ROUTE_WIDTH(4),
|
||||
.C_ID_WIDTH(3),
|
||||
.C_ADDR_WIDTH(40),
|
||||
.C_USER_WIDTH(512),
|
||||
.C_MAX_PAYLD_BYTES(64),
|
||||
.C_S_PIPELINE(0),
|
||||
.C_M_PIPELINE(0),
|
||||
.C_M_SEND_PIPELINE(0),
|
||||
.C_S_LATENCY(1),
|
||||
.C_NUM_OUTSTANDING(8),
|
||||
.C_ACLK_RELATIONSHIP(1),
|
||||
.C_ACLKEN_CONVERSION(0)
|
||||
) inst (
|
||||
.s_sc_aclk(s_sc_aclk),
|
||||
.s_sc_aclken(1'H1),
|
||||
.s_sc_aresetn(s_sc_aresetn),
|
||||
.s_sc_req(s_sc_req),
|
||||
.s_sc_info(s_sc_info),
|
||||
.s_sc_send(s_sc_send),
|
||||
.s_sc_recv(s_sc_recv),
|
||||
.s_sc_payld(s_sc_payld),
|
||||
.m_sc_aclk(m_sc_aclk),
|
||||
.m_sc_aclken(1'H1),
|
||||
.m_sc_aresetn(m_sc_aresetn),
|
||||
.m_sc_recv(m_sc_recv),
|
||||
.m_sc_send(m_sc_send),
|
||||
.m_sc_req(m_sc_req),
|
||||
.m_sc_info(m_sc_info),
|
||||
.m_sc_payld(m_sc_payld),
|
||||
.m_axis_arb_tvalid(),
|
||||
.m_axis_arb_tready(1'H1),
|
||||
.m_axis_arb_tdata(),
|
||||
.s_axis_arb_tvalid(1'H0),
|
||||
.s_axis_arb_tready(),
|
||||
.s_axis_arb_tdata(16'B0)
|
||||
);
|
||||
endmodule
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user