add dj_z7045 vivado project
This commit is contained in:
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################################################################################
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############################### Project Specific ###############################
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################################################################################
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# everything
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*
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# git related
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!/.gitignore
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!/.gitattributes
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# project documents
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!/*.md
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!/*.txt
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################################################################################
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############################### Vivado Specific ################################
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################################################################################
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# xpr: needed for recreating design
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!/*.xpr
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# source: include everything
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!/*.srcs/
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!/*.srcs/**/*
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# runs: exclude everything but design run results
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!/*.runs/
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!/*.runs/impl_*/
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!/*.runs/impl_*/*.bit
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!/*.runs/impl_*/*.ltx
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# xsa (Xilinx support archive): include for ps
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!/*.xsa
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################################################################################
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################################ Vitis Specific ################################
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################################################################################
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# include sdk directory and everything in it
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!/vitis*/
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!/vitis*/**
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/vitis*/**.log
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/vitis*/.analytics
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# exclude some obscure hidden SDK folders
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/vitis*/.metadata/
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/vitis*/.sdk/
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/vitis*/RemoteSystemsTempFiles/
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/vitis*/webtalk/
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# hw_platform: exclude the entire hw_platform folder, as everything can be
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# generated from the .hdf file. Make sure to include the bitstream in the .hdf
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# file when exporting from Vivado!
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/vitis*/*_hw_platform_*/
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# BSP: only keep `.cproject`, `.project`, `.sdkproject`, `.system.mss` and
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# Makefile, ps lib files are regenerated automatically
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/vitis*/*_bsp/*
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!/vitis*/*_bsp/*.cproject
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!/vitis*/*_bsp/*.project
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!/vitis*/*_bsp/*.sdkproject
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!/vitis*/*_bsp/system.mss
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!/vitis*/*_bsp/Makefile
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# Application: ignored file patterns, exclude Debug & Release folders
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/vitis*/**/*.o
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/vitis*/**/*.d
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/vitis*/**/*.a
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/vitis*/*/Debug/
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/vitis*/*/Release/
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################################################################################
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############################ Vivado & Vitis Common #############################
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################################################################################
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# file patterns that should always be ignored (journal files, log files, dump
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# files that are created upon Vivado/SDK errors)
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*.jou
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*.log
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*.backup.jou
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*.backup.log
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*.upgrade_log
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*.dmp
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*.debug
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vivado_pid*
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# vivado workspace files
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xsim.dir/
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xvlog.pb
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# Xilinx tools generated files
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.metadata/
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.settings/
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.wsdata/
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.Xil/
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logs/
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Packages/
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*.log*
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# System generated files
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# -- macOS
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.DS_Store
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.AppleDouble
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.LSOverride
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._*
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# -- Windows
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Thumbs.db
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ehthumbs.db
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Desktop.ini
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# -- Linux
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*~
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# IDEs and editors' files
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*.idea
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*.vscode
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*.sublime-workspace
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*.sublime-project
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BIN
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# file: ibert_7series_gtx_0.xdc
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####################################################################################
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##**************************************************************************
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##
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## System clock Divider paramter values
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##
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set_property CLKFBOUT_MULT_F 20.000 [get_cells u_ibert_core/inst/SYSCLK_DIVIDER.U_GT_MMCM]
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set_property DIVCLK_DIVIDE 3 [get_cells u_ibert_core/inst/SYSCLK_DIVIDER.U_GT_MMCM]
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set_property CLKIN1_PERIOD 6.667 [get_cells u_ibert_core/inst/SYSCLK_DIVIDER.U_GT_MMCM]
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set_property CLKOUT0_DIVIDE_F 10.000 [get_cells u_ibert_core/inst/SYSCLK_DIVIDER.U_GT_MMCM]
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_pins u_ibert_core/inst/SYSCLK_DIVIDER.U_GT_MMCM/CLKIN1]
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##
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## Icon Constraints
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##
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create_clock -name J_CLK -period 30 [get_pins -of_objects [get_cells u_ibert_core/inst/bscan_inst/SERIES7_BSCAN.bscan_inst] -filter {name =~ *DRCK}]
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set_clock_groups -group [get_clocks J_CLK] -asynchronous
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##
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## Clock Constraints for MGT refclk
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##
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create_clock -name REFCLK0_0 -period 6.667 [get_ports GTREFCLK0P_I[0]]
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set_clock_groups -group [get_clocks -include_generated_clocks REFCLK0_0] -asynchronous
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create_clock -name REFCLK0_1 -period 6.667 [get_ports GTREFCLK1P_I[0]]
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set_clock_groups -group [get_clocks -include_generated_clocks REFCLK0_1] -asynchronous
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##
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## TX/RX out clock constraints
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##
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# GT X0Y4
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create_clock -name Q1_RXCLK0 -period 3.333 [get_pins {u_ibert_core/inst/QUAD[0].u_q/CH[0].u_ch/u_gtxe2_channel/RXOUTCLK}]
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set_clock_groups -group [get_clocks Q1_RXCLK0] -asynchronous
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create_clock -name Q1_TX0 -period 3.333 [get_pins {u_ibert_core/inst/QUAD[0].u_q/CH[0].u_ch/u_gtxe2_channel/TXOUTCLK}]
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set_clock_groups -group [get_clocks Q1_TX0] -asynchronous
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# GT X0Y5
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create_clock -name Q1_RXCLK1 -period 3.333 [get_pins {u_ibert_core/inst/QUAD[0].u_q/CH[1].u_ch/u_gtxe2_channel/RXOUTCLK}]
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set_clock_groups -group [get_clocks Q1_RXCLK1] -asynchronous
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# GT X0Y6
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create_clock -name Q1_RXCLK2 -period 3.333 [get_pins {u_ibert_core/inst/QUAD[0].u_q/CH[2].u_ch/u_gtxe2_channel/RXOUTCLK}]
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set_clock_groups -group [get_clocks Q1_RXCLK2] -asynchronous
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# GT X0Y7
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create_clock -name Q1_RXCLK3 -period 3.333 [get_pins {u_ibert_core/inst/QUAD[0].u_q/CH[3].u_ch/u_gtxe2_channel/RXOUTCLK}]
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set_clock_groups -group [get_clocks Q1_RXCLK3] -asynchronous
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##
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## System clock pin locs and timing constraints
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##
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##
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## GTXE2 Channel and Common Loc constraints
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##
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set_property LOC GTXE2_CHANNEL_X0Y4 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[0].u_ch/u_gtxe2_channel]
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set_property LOC GTXE2_CHANNEL_X0Y5 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[1].u_ch/u_gtxe2_channel]
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set_property LOC GTXE2_CHANNEL_X0Y6 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[2].u_ch/u_gtxe2_channel]
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set_property LOC GTXE2_CHANNEL_X0Y7 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[3].u_ch/u_gtxe2_channel]
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set_property LOC GTXE2_COMMON_X0Y1 [get_cells u_ibert_core/inst/QUAD[0].u_q/u_common/u_gtxe2_common]
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##
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## BUFH Loc constraints for TX/RX userclks
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##
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set_property LOC BUFHCE_X1Y12 [get_cells u_ibert_core/inst/QUAD[0].u_q/u_common/u_clocking/local_txusr.NON_K7.u_txusr]
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set_property LOC BUFHCE_X1Y13 [get_cells u_ibert_core/inst/QUAD[0].u_q/u_common/u_clocking/rx_ind.NON_K7.u_rxusr0]
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set_property LOC BUFHCE_X1Y14 [get_cells u_ibert_core/inst/QUAD[0].u_q/u_common/u_clocking/rx_ind.NON_K7.u_rxusr1]
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set_property LOC BUFHCE_X1Y15 [get_cells u_ibert_core/inst/QUAD[0].u_q/u_common/u_clocking/rx_ind.NON_K7.u_rxusr2]
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set_property LOC BUFHCE_X1Y16 [get_cells u_ibert_core/inst/QUAD[0].u_q/u_common/u_clocking/rx_ind.NON_K7.u_rxusr3]
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##
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## MGT reference clock BUFFERS location constraints
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##
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set_property LOC IBUFDS_GTE2_X0Y2 [get_cells u_buf_q1_clk0]
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set_property LOC IBUFDS_GTE2_X0Y3 [get_cells u_buf_q1_clk1]
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##
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## Asynchronous constraints for Userclks and systemclock clock groups
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##
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#set_clock_groups -group [get_clocks Q*_RXCLK*] -group [get_clocks Q*_TX*] -asynchronous
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#set_clock_groups -group [get_clocks D_CLK*] -group [get_clocks Q*_TX*] -asynchronous
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#set_clock_groups -group [get_clocks Q*_RXCLK*] -group [get_clocks D_CLK*] -asynchronous
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#set_clock_groups -group [get_generated_clocks -of_objects [get_pins u_ibert_core/inst/SYSCLK_DIVIDER.U_GT_MMCM/CLKOUT0]] -group [get_clocks Q*_TX*] -asynchronous
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#set_clock_groups -group [get_clocks Q*_RXCLK*] -group [get_generated_clocks -of_objects [get_pins u_ibert_core/inst/SYSCLK_DIVIDER.U_GT_MMCM/CLKOUT0]] -asynchronous
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##
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## Set Case Analysis constraints for fabric clock calculation
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##
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#MUX select QPLLREFCLKSEL:
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set_case_analysis 0 [get_pins u_ibert_core/inst/QUAD[0].u_q/u_common/U_COMPLEX_REGS/reg_202/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg[2]/Q ]
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set_case_analysis 0 [get_pins u_ibert_core/inst/QUAD[0].u_q/u_common/U_COMPLEX_REGS/reg_202/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg[1]/Q ]
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set_case_analysis 1 [get_pins u_ibert_core/inst/QUAD[0].u_q/u_common/U_COMPLEX_REGS/reg_202/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg[0]/Q ]
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#MUX select CPLLREFCLKSEL:
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set_case_analysis 0 [get_pins u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/U_CHANNEL_REGS/reg_215/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg[6]/Q ]
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set_case_analysis 0 [get_pins u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/U_CHANNEL_REGS/reg_215/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg[5]/Q ]
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set_case_analysis 1 [get_pins u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/U_CHANNEL_REGS/reg_215/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg[4]/Q ]
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#MUX select RXRATE:
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set_case_analysis 0 [get_pins u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/U_CHANNEL_REGS/reg_216/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg[5]/Q ]
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set_case_analysis 0 [get_pins u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/U_CHANNEL_REGS/reg_216/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg[4]/Q ]
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set_case_analysis 0 [get_pins u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/U_CHANNEL_REGS/reg_216/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg[3]/Q ]
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#MUX select TXRATE:
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set_case_analysis 0 [get_pins u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/U_CHANNEL_REGS/reg_217/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg[8]/Q ]
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set_case_analysis 0 [get_pins u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/U_CHANNEL_REGS/reg_217/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg[7]/Q ]
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set_case_analysis 0 [get_pins u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/U_CHANNEL_REGS/reg_217/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg[6]/Q ]
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#MUX select RXOUTCLKSEL:
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set_case_analysis 0 [get_pins u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/U_CHANNEL_REGS/reg_215/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg[15]/Q ]
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set_case_analysis 1 [get_pins u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/U_CHANNEL_REGS/reg_215/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg[14]/Q ]
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set_case_analysis 0 [get_pins u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/U_CHANNEL_REGS/reg_215/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg[13]/Q ]
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#MUX select TXOUTCLKSEL:
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set_case_analysis 0 [get_pins u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/U_CHANNEL_REGS/reg_217/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg[2]/Q ]
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set_case_analysis 1 [get_pins u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/U_CHANNEL_REGS/reg_217/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg[1]/Q ]
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set_case_analysis 0 [get_pins u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/U_CHANNEL_REGS/reg_217/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg[0]/Q ]
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##
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## Attribute values for GTXE2 Channel and Common instances
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##
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##
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## Attribute Values for QUAD[1] - Channel
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##
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##------Comma Detection and Alignment---------
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set_property ALIGN_COMMA_DOUBLE "FALSE" [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
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set_property ALIGN_COMMA_ENABLE 10'b0001111111 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
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set_property ALIGN_COMMA_WORD 1 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
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set_property ALIGN_MCOMMA_DET "TRUE" [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
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set_property ALIGN_MCOMMA_VALUE 10'b1010000011 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
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set_property ALIGN_PCOMMA_DET "TRUE" [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
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set_property ALIGN_PCOMMA_VALUE 10'b0101111100 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
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set_property DEC_MCOMMA_DETECT "FALSE" [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property DEC_PCOMMA_DETECT "FALSE" [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property DEC_VALID_COMMA_ONLY "FALSE" [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property DMONITOR_CFG 24'h000A01 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
|
||||
##--------------Channel Bonding--------------
|
||||
set_property CBCC_DATA_SOURCE_SEL "DECODED" [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property CHAN_BOND_KEEP_ALIGN "FALSE" [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property CHAN_BOND_MAX_SKEW 7 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property CHAN_BOND_SEQ_LEN 1 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property CHAN_BOND_SEQ_1_1 10'b0101111100 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property CHAN_BOND_SEQ_1_2 10'b0100000000 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property CHAN_BOND_SEQ_1_3 10'b0100000000 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property CHAN_BOND_SEQ_1_4 10'b0100000000 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property CHAN_BOND_SEQ_1_ENABLE 4'b1111 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property CHAN_BOND_SEQ_2_1 10'b0100000000 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property CHAN_BOND_SEQ_2_2 10'b0100000000 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property CHAN_BOND_SEQ_2_3 10'b0100000000 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property CHAN_BOND_SEQ_2_4 10'b0100000000 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property CHAN_BOND_SEQ_2_ENABLE 4'b1111 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property CHAN_BOND_SEQ_2_USE "FALSE" [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
|
||||
##-----------Clock Correction------------
|
||||
set_property CLK_COR_KEEP_IDLE "FALSE" [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property CLK_COR_MAX_LAT 19.0 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property CLK_COR_MIN_LAT 15.0 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property CLK_COR_PRECEDENCE "TRUE" [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property CLK_CORRECT_USE "FALSE" [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property CLK_COR_REPEAT_WAIT 0 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property CLK_COR_SEQ_LEN 1 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property CLK_COR_SEQ_1_1 10'b0100011100 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property CLK_COR_SEQ_1_2 10'b0100000000 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property CLK_COR_SEQ_1_3 10'b0100000000 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property CLK_COR_SEQ_1_4 10'b0100000000 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property CLK_COR_SEQ_1_ENABLE 4'b1111 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property CLK_COR_SEQ_2_1 10'b0100000000 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property CLK_COR_SEQ_2_2 10'b0100000000 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property CLK_COR_SEQ_2_3 10'b0100000000 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property CLK_COR_SEQ_2_4 10'b0100000000 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property CLK_COR_SEQ_2_ENABLE 4'b1111 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property CLK_COR_SEQ_2_USE "FALSE" [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
|
||||
##-----------Channel PLL----------------------
|
||||
set_property CPLL_CFG 24'hBC07DC [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property CPLL_FBDIV 1 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property CPLL_FBDIV_45 4 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property CPLL_INIT_CFG 24'h00001E [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property CPLL_LOCK_CFG 16'h01C0 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property CPLL_REFCLK_DIV 1 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property RXOUT_DIV 1 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property TXOUT_DIV 1 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
|
||||
##-----------------Eyescan--------------
|
||||
set_property ES_CONTROL 6'b000000 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property ES_ERRDET_EN "FALSE" [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property ES_EYE_SCAN_EN "TRUE" [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property ES_HORZ_OFFSET 12'h000 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property ES_PMA_CFG 10'b0000000000 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property ES_PRESCALE 5'b00000 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property ES_QUALIFIER 80'h00000000000000000000 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property ES_QUAL_MASK 80'h00000000000000000000 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property ES_SDATA_MASK 80'h00000000000000000000 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property ES_VERT_OFFSET 9'b000000000 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property FTS_DESKEW_SEQ_ENABLE 4'b1111 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property FTS_LANE_DESKEW_CFG 4'b1111 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property FTS_LANE_DESKEW_EN "FALSE" [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property GEARBOX_MODE 3'b000 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property OUTREFCLK_SEL_INV 2'b11 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property PCS_PCIE_EN "FALSE" [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property PCS_RSVD_ATTR 48'h000000000000 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property PMA_RSV 32'h001E7080 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property PMA_RSV2 16'h2070 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property PMA_RSV3 2'b00 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property RX_BIAS_CFG 12'b000000000100 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
|
||||
##-----------Rx Elastic Buffer and Phase alignment-------------
|
||||
set_property RXBUF_ADDR_MODE "FAST" [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property RXBUF_EIDLE_HI_CNT 4'b1000 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property RXBUF_EIDLE_LO_CNT 4'b0000 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property RXBUF_EN "TRUE" [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property RX_BUFFER_CFG 6'b000000 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property RXBUF_RESET_ON_CB_CHANGE "TRUE" [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property RXBUF_RESET_ON_COMMAALIGN "FALSE" [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property RXBUF_RESET_ON_EIDLE "FALSE" [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property RXBUF_RESET_ON_RATE_CHANGE "TRUE" [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property RXBUFRESET_TIME 5'b00001 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property RXBUF_THRESH_OVFLW 61 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property RXBUF_THRESH_OVRD "FALSE" [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property RXBUF_THRESH_UNDFLW 4 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property RXDLY_CFG 16'h001F [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property RXDLY_LCFG 9'h030 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property RXDLY_TAP_CFG 16'h0000 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
|
||||
##-----------RX driver, OOB signalling, Coupling and Eq., CDR------------
|
||||
set_property RXCDR_CFG 72'h0B800023FF10200020 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property RXCDRFREQRESET_TIME 5'b00001 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property RXCDR_FR_RESET_ON_EIDLE 1'b0 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property RXCDR_HOLD_DURING_EIDLE 1'b0 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property RXCDR_LOCK_CFG 6'b010101 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property RXCDR_PH_RESET_ON_EIDLE 1'b0 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property RXCDRPHRESET_TIME 5'b00001 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property RXDFELPMRESET_TIME 7'b0001111 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property RXOOB_CFG 7'b0000110 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
|
||||
##-----------------------RX Interface-------------------------
|
||||
set_property RX_INT_DATAWIDTH 1 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property RX_DATA_WIDTH 32 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property RX_CLKMUX_PD 1'b1 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property RX_CLK25_DIV 6 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property RX_CM_SEL 2'b11 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property RX_CM_TRIM 3'b100 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property RX_DDI_SEL 6'b000000 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property RX_DEBUG_CFG 12'b000000000000 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
|
||||
##------------RX Decision Feedback Equalizer(DFE)-------------
|
||||
set_property RX_DEFER_RESET_BUF_EN "TRUE" [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property RX_DFE_GAIN_CFG 23'h020FEA [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property RX_DFE_H2_CFG 12'b000000000000 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property RX_DFE_H3_CFG 12'b000001000000 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property RX_DFE_H4_CFG 11'b00011110000 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property RX_DFE_H5_CFG 11'b00011100000 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property RX_DFE_LPM_HOLD_DURING_EIDLE 1'b0 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property RX_DFE_KL_CFG 13'b0000011111110 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property RX_DFE_KL_CFG2 32'h3010D90C [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property RX_DFE_LPM_CFG 16'h0954 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property RX_OS_CFG 13'b0000010000000 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property RX_DFE_UT_CFG 17'b10001111000000000 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property RX_DFE_VP_CFG 17'b00011111100000011 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property RX_DFE_XYD_CFG 13'b0000000000000 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property RX_DISPERR_SEQ_MATCH "TRUE" [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
|
||||
##-----------------------RX Gearbox---------------------------
|
||||
set_property RXGEARBOX_EN "FALSE" [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property RXISCANRESET_TIME 5'b00001 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property RXLPM_HF_CFG 14'b00000011110000 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property RXLPM_LF_CFG 14'b00000011110000 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property RXPCSRESET_TIME 5'b00001 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property RXPH_CFG 24'h000000 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property RXPHDLY_CFG 24'h084020 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property RXPH_MONITOR_SEL 5'b00000 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property RXPMARESET_TIME 5'b00011 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
|
||||
##-----------------------PRBS Detection-----------------------
|
||||
set_property RXPRBS_ERR_LOOPBACK 1'b0 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property RX_SIG_VALID_DLY 10 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property RXSLIDE_AUTO_WAIT 7 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property RXSLIDE_MODE "off" [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property RX_XCLK_SEL "RXREC" [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
|
||||
##-----------RX Attributes for PCI Express/SATA/SAS----------
|
||||
set_property PD_TRANS_TIME_FROM_P2 12'h03c [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property PD_TRANS_TIME_NONE_P2 8'h3c [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property PD_TRANS_TIME_TO_P2 8'h64 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property SAS_MAX_COM 64 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property SAS_MIN_COM 36 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property SATA_BURST_SEQ_LEN 4'b1111 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property SATA_BURST_VAL 3'b100 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property SATA_CPLL_CFG "VCO_3000MHZ" [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property SATA_EIDLE_VAL 3'b100 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property SATA_MAX_BURST 8 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property SATA_MAX_INIT 21 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property SATA_MAX_WAKE 7 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property SATA_MIN_BURST 4 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property SATA_MIN_INIT 12 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property SATA_MIN_WAKE 4 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property SHOW_REALIGN_COMMA "TRUE" [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property TERM_RCAL_CFG 5'b10000 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property TERM_RCAL_OVRD 1'b0 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property TRANS_TIME_RATE 8'h0E [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property TST_RSV 32'h00000000 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
|
||||
##------------TX Buffering and Phase Alignment----------------
|
||||
set_property TXBUF_EN "TRUE" [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property TXBUF_RESET_ON_RATE_CHANGE "FALSE" [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
|
||||
##-----------------------TX Interface-------------------------
|
||||
set_property TX_DATA_WIDTH 32 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property TX_DEEMPH0 5'b00000 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property TX_DEEMPH1 5'b00000 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property TXDLY_CFG 16'h001F [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property TXDLY_LCFG 9'h030 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property TXDLY_TAP_CFG 16'h0000 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property TX_INT_DATAWIDTH 1 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property TX_CLKMUX_PD 1'b1 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property TX_CLK25_DIV 6 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
|
||||
##--------------TX Driver and OOB Signalling------------------
|
||||
set_property TX_EIDLE_ASSERT_DELAY 3'b110 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property TX_EIDLE_DEASSERT_DELAY 3'b100 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property TX_LOOPBACK_DRIVE_HIZ "FALSE" [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property TX_MAINCURSOR_SEL 1'b0 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property TX_DRIVE_MODE "DIRECT" [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
|
||||
##-----------------------TX Gearbox---------------------------
|
||||
set_property TXGEARBOX_EN "FALSE" [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
|
||||
##----------------TX Attributes for PCI Express---------------
|
||||
set_property TX_MARGIN_FULL_0 7'b1001110 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property TX_MARGIN_FULL_1 7'b1001001 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property TX_MARGIN_FULL_2 7'b1000101 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property TX_MARGIN_FULL_3 7'b1000010 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property TX_MARGIN_FULL_4 7'b1000000 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property TX_MARGIN_LOW_0 7'b1000110 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property TX_MARGIN_LOW_1 7'b1000100 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property TX_MARGIN_LOW_2 7'b1000010 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property TX_MARGIN_LOW_3 7'b1000000 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property TX_MARGIN_LOW_4 7'b1000000 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property TXPCSRESET_TIME 5'b00001 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property TXPH_CFG 16'h0780 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property TXPHDLY_CFG 24'h084020 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property TXPH_MONITOR_SEL 5'b00000 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property TXPMARESET_TIME 5'b00001 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property TX_PREDRIVER_MODE 1'b0 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property TX_QPI_STATUS_EN 1'b0 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property TX_RXDETECT_CFG 14'h1832 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property TX_RXDETECT_REF 3'b100 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property TX_XCLK_SEL "TXOUT" [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
set_property UCODEER_CLR 1'b0 [get_cells u_ibert_core/inst/QUAD[0].u_q/CH[*].u_ch/u_gtxe2_channel]
|
||||
##
|
||||
## Attribute Values for QUAD[1] - Common
|
||||
##
|
||||
set_property BIAS_CFG 64'h0000040000001000 [get_cells u_ibert_core/inst/QUAD[0].u_q/u_common/u_gtxe2_common]
|
||||
set_property COMMON_CFG 32'h00000000 [get_cells u_ibert_core/inst/QUAD[0].u_q/u_common/u_gtxe2_common]
|
||||
set_property QPLL_CFG 27'h0680181 [get_cells u_ibert_core/inst/QUAD[0].u_q/u_common/u_gtxe2_common]
|
||||
set_property QPLL_CLKOUT_CFG 4'b0000 [get_cells u_ibert_core/inst/QUAD[0].u_q/u_common/u_gtxe2_common]
|
||||
set_property QPLL_COARSE_FREQ_OVRD 6'b010000 [get_cells u_ibert_core/inst/QUAD[0].u_q/u_common/u_gtxe2_common]
|
||||
set_property QPLL_COARSE_FREQ_OVRD_EN 1'b0 [get_cells u_ibert_core/inst/QUAD[0].u_q/u_common/u_gtxe2_common]
|
||||
set_property QPLL_CP 10'b0000011111 [get_cells u_ibert_core/inst/QUAD[0].u_q/u_common/u_gtxe2_common]
|
||||
set_property QPLL_CP_MONITOR_EN 1'b0 [get_cells u_ibert_core/inst/QUAD[0].u_q/u_common/u_gtxe2_common]
|
||||
set_property QPLL_DMONITOR_SEL 1'b0 [get_cells u_ibert_core/inst/QUAD[0].u_q/u_common/u_gtxe2_common]
|
||||
set_property QPLL_FBDIV_MONITOR_EN 1'b1 [get_cells u_ibert_core/inst/QUAD[0].u_q/u_common/u_gtxe2_common]
|
||||
set_property QPLL_INIT_CFG 24'h000028 [get_cells u_ibert_core/inst/QUAD[0].u_q/u_common/u_gtxe2_common]
|
||||
set_property QPLL_LOCK_CFG 16'h21E8 [get_cells u_ibert_core/inst/QUAD[0].u_q/u_common/u_gtxe2_common]
|
||||
set_property QPLL_LPF 4'b1111 [get_cells u_ibert_core/inst/QUAD[0].u_q/u_common/u_gtxe2_common]
|
||||
set_property QPLL_REFCLK_DIV 1 [get_cells u_ibert_core/inst/QUAD[0].u_q/u_common/u_gtxe2_common]
|
||||
|
||||
+1263
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,533 @@
|
||||
{
|
||||
"design": {
|
||||
"design_info": {
|
||||
"boundary_crc": "0xCC6CFA53B4580162",
|
||||
"device": "xc7z045ffg900-2",
|
||||
"gen_directory": "../../../../z7045_ibert.gen/sources_1/bd/system_bd",
|
||||
"name": "system_bd",
|
||||
"rev_ctrl_bd_flag": "RevCtrlBdOff",
|
||||
"synth_flow_mode": "Hierarchical",
|
||||
"tool_version": "2024.1",
|
||||
"validated": "true"
|
||||
},
|
||||
"design_tree": {
|
||||
"processing_system7": ""
|
||||
},
|
||||
"interface_ports": {
|
||||
"DDR": {
|
||||
"mode": "Master",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:ddrx:1.0",
|
||||
"vlnv": "xilinx.com:interface:ddrx_rtl:1.0",
|
||||
"parameters": {
|
||||
"AXI_ARBITRATION_SCHEME": {
|
||||
"value": "TDM",
|
||||
"value_src": "default"
|
||||
},
|
||||
"BURST_LENGTH": {
|
||||
"value": "8",
|
||||
"value_src": "default"
|
||||
},
|
||||
"CAN_DEBUG": {
|
||||
"value": "false",
|
||||
"value_src": "default"
|
||||
},
|
||||
"CAS_LATENCY": {
|
||||
"value": "11",
|
||||
"value_src": "default"
|
||||
},
|
||||
"CAS_WRITE_LATENCY": {
|
||||
"value": "11",
|
||||
"value_src": "default"
|
||||
},
|
||||
"CS_ENABLED": {
|
||||
"value": "true",
|
||||
"value_src": "default"
|
||||
},
|
||||
"DATA_MASK_ENABLED": {
|
||||
"value": "true",
|
||||
"value_src": "default"
|
||||
},
|
||||
"DATA_WIDTH": {
|
||||
"value": "8",
|
||||
"value_src": "default"
|
||||
},
|
||||
"MEMORY_TYPE": {
|
||||
"value": "COMPONENTS",
|
||||
"value_src": "default"
|
||||
},
|
||||
"MEM_ADDR_MAP": {
|
||||
"value": "ROW_COLUMN_BANK",
|
||||
"value_src": "default"
|
||||
},
|
||||
"SLOT": {
|
||||
"value": "Single",
|
||||
"value_src": "default"
|
||||
},
|
||||
"TIMEPERIOD_PS": {
|
||||
"value": "1250",
|
||||
"value_src": "default"
|
||||
}
|
||||
},
|
||||
"port_maps": {
|
||||
"CAS_N": {
|
||||
"physical_name": "DDR_cas_n",
|
||||
"direction": "IO"
|
||||
},
|
||||
"CKE": {
|
||||
"physical_name": "DDR_cke",
|
||||
"direction": "IO"
|
||||
},
|
||||
"CK_N": {
|
||||
"physical_name": "DDR_ck_n",
|
||||
"direction": "IO"
|
||||
},
|
||||
"CK_P": {
|
||||
"physical_name": "DDR_ck_p",
|
||||
"direction": "IO"
|
||||
},
|
||||
"CS_N": {
|
||||
"physical_name": "DDR_cs_n",
|
||||
"direction": "IO"
|
||||
},
|
||||
"RESET_N": {
|
||||
"physical_name": "DDR_reset_n",
|
||||
"direction": "IO"
|
||||
},
|
||||
"ODT": {
|
||||
"physical_name": "DDR_odt",
|
||||
"direction": "IO"
|
||||
},
|
||||
"RAS_N": {
|
||||
"physical_name": "DDR_ras_n",
|
||||
"direction": "IO"
|
||||
},
|
||||
"WE_N": {
|
||||
"physical_name": "DDR_we_n",
|
||||
"direction": "IO"
|
||||
},
|
||||
"BA": {
|
||||
"physical_name": "DDR_ba",
|
||||
"direction": "IO",
|
||||
"left": "2",
|
||||
"right": "0"
|
||||
},
|
||||
"ADDR": {
|
||||
"physical_name": "DDR_addr",
|
||||
"direction": "IO",
|
||||
"left": "14",
|
||||
"right": "0"
|
||||
},
|
||||
"DM": {
|
||||
"physical_name": "DDR_dm",
|
||||
"direction": "IO",
|
||||
"left": "3",
|
||||
"right": "0"
|
||||
},
|
||||
"DQ": {
|
||||
"physical_name": "DDR_dq",
|
||||
"direction": "IO",
|
||||
"left": "31",
|
||||
"right": "0"
|
||||
},
|
||||
"DQS_N": {
|
||||
"physical_name": "DDR_dqs_n",
|
||||
"direction": "IO",
|
||||
"left": "3",
|
||||
"right": "0"
|
||||
},
|
||||
"DQS_P": {
|
||||
"physical_name": "DDR_dqs_p",
|
||||
"direction": "IO",
|
||||
"left": "3",
|
||||
"right": "0"
|
||||
}
|
||||
}
|
||||
},
|
||||
"FIXED_IO": {
|
||||
"mode": "Master",
|
||||
"vlnv_bus_definition": "xilinx.com:display_processing_system7:fixedio:1.0",
|
||||
"vlnv": "xilinx.com:display_processing_system7:fixedio_rtl:1.0",
|
||||
"parameters": {
|
||||
"CAN_DEBUG": {
|
||||
"value": "false",
|
||||
"value_src": "default"
|
||||
}
|
||||
},
|
||||
"port_maps": {
|
||||
"MIO": {
|
||||
"physical_name": "FIXED_IO_mio",
|
||||
"direction": "IO",
|
||||
"left": "53",
|
||||
"right": "0"
|
||||
},
|
||||
"DDR_VRN": {
|
||||
"physical_name": "FIXED_IO_ddr_vrn",
|
||||
"direction": "IO"
|
||||
},
|
||||
"DDR_VRP": {
|
||||
"physical_name": "FIXED_IO_ddr_vrp",
|
||||
"direction": "IO"
|
||||
},
|
||||
"PS_SRSTB": {
|
||||
"physical_name": "FIXED_IO_ps_srstb",
|
||||
"direction": "IO"
|
||||
},
|
||||
"PS_CLK": {
|
||||
"physical_name": "FIXED_IO_ps_clk",
|
||||
"direction": "IO"
|
||||
},
|
||||
"PS_PORB": {
|
||||
"physical_name": "FIXED_IO_ps_porb",
|
||||
"direction": "IO"
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"components": {
|
||||
"processing_system7": {
|
||||
"vlnv": "xilinx.com:ip:processing_system7:5.5",
|
||||
"ip_revision": "6",
|
||||
"xci_name": "system_bd_processing_system7_0_0",
|
||||
"xci_path": "ip/system_bd_processing_system7_0_0/system_bd_processing_system7_0_0.xci",
|
||||
"inst_hier_path": "processing_system7",
|
||||
"parameters": {
|
||||
"PCW_ACT_APU_PERIPHERAL_FREQMHZ": {
|
||||
"value": "666.666687"
|
||||
},
|
||||
"PCW_ACT_CAN_PERIPHERAL_FREQMHZ": {
|
||||
"value": "10.000000"
|
||||
},
|
||||
"PCW_ACT_DCI_PERIPHERAL_FREQMHZ": {
|
||||
"value": "10.158730"
|
||||
},
|
||||
"PCW_ACT_ENET0_PERIPHERAL_FREQMHZ": {
|
||||
"value": "10.000000"
|
||||
},
|
||||
"PCW_ACT_ENET1_PERIPHERAL_FREQMHZ": {
|
||||
"value": "10.000000"
|
||||
},
|
||||
"PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ": {
|
||||
"value": "50.000000"
|
||||
},
|
||||
"PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ": {
|
||||
"value": "10.000000"
|
||||
},
|
||||
"PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ": {
|
||||
"value": "10.000000"
|
||||
},
|
||||
"PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ": {
|
||||
"value": "10.000000"
|
||||
},
|
||||
"PCW_ACT_PCAP_PERIPHERAL_FREQMHZ": {
|
||||
"value": "200.000000"
|
||||
},
|
||||
"PCW_ACT_QSPI_PERIPHERAL_FREQMHZ": {
|
||||
"value": "200.000000"
|
||||
},
|
||||
"PCW_ACT_SDIO_PERIPHERAL_FREQMHZ": {
|
||||
"value": "10.000000"
|
||||
},
|
||||
"PCW_ACT_SMC_PERIPHERAL_FREQMHZ": {
|
||||
"value": "10.000000"
|
||||
},
|
||||
"PCW_ACT_SPI_PERIPHERAL_FREQMHZ": {
|
||||
"value": "10.000000"
|
||||
},
|
||||
"PCW_ACT_TPIU_PERIPHERAL_FREQMHZ": {
|
||||
"value": "200.000000"
|
||||
},
|
||||
"PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ": {
|
||||
"value": "111.111115"
|
||||
},
|
||||
"PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ": {
|
||||
"value": "111.111115"
|
||||
},
|
||||
"PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ": {
|
||||
"value": "111.111115"
|
||||
},
|
||||
"PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ": {
|
||||
"value": "111.111115"
|
||||
},
|
||||
"PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ": {
|
||||
"value": "111.111115"
|
||||
},
|
||||
"PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ": {
|
||||
"value": "111.111115"
|
||||
},
|
||||
"PCW_ACT_UART_PERIPHERAL_FREQMHZ": {
|
||||
"value": "10.000000"
|
||||
},
|
||||
"PCW_ACT_WDT_PERIPHERAL_FREQMHZ": {
|
||||
"value": "111.111115"
|
||||
},
|
||||
"PCW_CLK0_FREQ": {
|
||||
"value": "50000000"
|
||||
},
|
||||
"PCW_CLK1_FREQ": {
|
||||
"value": "10000000"
|
||||
},
|
||||
"PCW_CLK2_FREQ": {
|
||||
"value": "10000000"
|
||||
},
|
||||
"PCW_CLK3_FREQ": {
|
||||
"value": "10000000"
|
||||
},
|
||||
"PCW_DDR_RAM_HIGHADDR": {
|
||||
"value": "0x1FFFFFFF"
|
||||
},
|
||||
"PCW_EN_QSPI": {
|
||||
"value": "1"
|
||||
},
|
||||
"PCW_FPGA_FCLK0_ENABLE": {
|
||||
"value": "1"
|
||||
},
|
||||
"PCW_MIO_1_IOTYPE": {
|
||||
"value": "LVCMOS 1.8V"
|
||||
},
|
||||
"PCW_MIO_1_PULLUP": {
|
||||
"value": "enabled"
|
||||
},
|
||||
"PCW_MIO_1_SLEW": {
|
||||
"value": "slow"
|
||||
},
|
||||
"PCW_MIO_2_IOTYPE": {
|
||||
"value": "LVCMOS 1.8V"
|
||||
},
|
||||
"PCW_MIO_2_SLEW": {
|
||||
"value": "slow"
|
||||
},
|
||||
"PCW_MIO_3_IOTYPE": {
|
||||
"value": "LVCMOS 1.8V"
|
||||
},
|
||||
"PCW_MIO_3_SLEW": {
|
||||
"value": "slow"
|
||||
},
|
||||
"PCW_MIO_4_IOTYPE": {
|
||||
"value": "LVCMOS 1.8V"
|
||||
},
|
||||
"PCW_MIO_4_SLEW": {
|
||||
"value": "slow"
|
||||
},
|
||||
"PCW_MIO_5_IOTYPE": {
|
||||
"value": "LVCMOS 1.8V"
|
||||
},
|
||||
"PCW_MIO_5_SLEW": {
|
||||
"value": "slow"
|
||||
},
|
||||
"PCW_MIO_6_IOTYPE": {
|
||||
"value": "LVCMOS 1.8V"
|
||||
},
|
||||
"PCW_MIO_6_SLEW": {
|
||||
"value": "slow"
|
||||
},
|
||||
"PCW_MIO_TREE_PERIPHERALS": {
|
||||
"value": [
|
||||
"unassigned#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI",
|
||||
"Flash#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned"
|
||||
]
|
||||
},
|
||||
"PCW_MIO_TREE_SIGNALS": {
|
||||
"value": "unassigned#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned"
|
||||
},
|
||||
"PCW_PRESET_BANK0_VOLTAGE": {
|
||||
"value": "LVCMOS 1.8V"
|
||||
},
|
||||
"PCW_PRESET_BANK1_VOLTAGE": {
|
||||
"value": "LVCMOS 1.8V"
|
||||
},
|
||||
"PCW_QSPI_GRP_FBCLK_ENABLE": {
|
||||
"value": "0"
|
||||
},
|
||||
"PCW_QSPI_GRP_IO1_ENABLE": {
|
||||
"value": "0"
|
||||
},
|
||||
"PCW_QSPI_GRP_SINGLE_SS_ENABLE": {
|
||||
"value": "1"
|
||||
},
|
||||
"PCW_QSPI_GRP_SINGLE_SS_IO": {
|
||||
"value": "MIO 1 .. 6"
|
||||
},
|
||||
"PCW_QSPI_GRP_SS1_ENABLE": {
|
||||
"value": "0"
|
||||
},
|
||||
"PCW_QSPI_PERIPHERAL_ENABLE": {
|
||||
"value": "1"
|
||||
},
|
||||
"PCW_QSPI_PERIPHERAL_FREQMHZ": {
|
||||
"value": "200"
|
||||
},
|
||||
"PCW_QSPI_QSPI_IO": {
|
||||
"value": "MIO 1 .. 6"
|
||||
},
|
||||
"PCW_SINGLE_QSPI_DATA_MODE": {
|
||||
"value": "x4"
|
||||
},
|
||||
"PCW_UIPARAM_ACT_DDR_FREQ_MHZ": {
|
||||
"value": "533.333374"
|
||||
},
|
||||
"PCW_UIPARAM_DDR_BUS_WIDTH": {
|
||||
"value": "16 Bit"
|
||||
},
|
||||
"PCW_UIPARAM_DDR_ECC": {
|
||||
"value": "Disabled"
|
||||
},
|
||||
"PCW_UIPARAM_DDR_PARTNO": {
|
||||
"value": "MT41J256M16 RE-125"
|
||||
}
|
||||
},
|
||||
"interface_ports": {
|
||||
"M_AXI_GP0": {
|
||||
"vlnv": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "Master",
|
||||
"address_space_ref": "Data",
|
||||
"base_address": {
|
||||
"minimum": "0x40000000",
|
||||
"maximum": "0x7FFFFFFF",
|
||||
"width": "32"
|
||||
}
|
||||
}
|
||||
},
|
||||
"addressing": {
|
||||
"address_spaces": {
|
||||
"Data": {
|
||||
"range": "4G",
|
||||
"width": "32",
|
||||
"local_memory_map": {
|
||||
"name": "Data",
|
||||
"description": "Address Space Segments",
|
||||
"address_blocks": {
|
||||
"segment1": {
|
||||
"name": "segment1",
|
||||
"display_name": "segment1",
|
||||
"base_address": "0x00000000",
|
||||
"range": "256K",
|
||||
"width": "18",
|
||||
"usage": "register"
|
||||
},
|
||||
"segment2": {
|
||||
"name": "segment2",
|
||||
"display_name": "segment2",
|
||||
"base_address": "0x00040000",
|
||||
"range": "256K",
|
||||
"width": "19",
|
||||
"usage": "register"
|
||||
},
|
||||
"segment3": {
|
||||
"name": "segment3",
|
||||
"display_name": "segment3",
|
||||
"base_address": "0x00080000",
|
||||
"range": "512K",
|
||||
"width": "20",
|
||||
"usage": "register"
|
||||
},
|
||||
"segment4": {
|
||||
"name": "segment4",
|
||||
"display_name": "segment4",
|
||||
"base_address": "0x00100000",
|
||||
"range": "1023M",
|
||||
"width": "30",
|
||||
"usage": "register"
|
||||
},
|
||||
"M_AXI_GP0": {
|
||||
"name": "M_AXI_GP0",
|
||||
"display_name": "M_AXI_GP0",
|
||||
"base_address": "0x40000000",
|
||||
"range": "1G",
|
||||
"width": "31",
|
||||
"usage": "register"
|
||||
},
|
||||
"M_AXI_GP1": {
|
||||
"name": "M_AXI_GP1",
|
||||
"display_name": "M_AXI_GP1",
|
||||
"base_address": "0x80000000",
|
||||
"range": "1G",
|
||||
"width": "32",
|
||||
"usage": "register"
|
||||
},
|
||||
"IO_Peripheral_Registers": {
|
||||
"name": "IO_Peripheral_Registers",
|
||||
"display_name": "IO Peripheral Registers",
|
||||
"base_address": "0xE0000000",
|
||||
"range": "3M",
|
||||
"width": "32",
|
||||
"usage": "register"
|
||||
},
|
||||
"SMC_Memories": {
|
||||
"name": "SMC_Memories",
|
||||
"display_name": "SMC Memories",
|
||||
"base_address": "0xE1000000",
|
||||
"range": "80M",
|
||||
"width": "32",
|
||||
"usage": "register"
|
||||
},
|
||||
"SLCR_Registers": {
|
||||
"name": "SLCR_Registers",
|
||||
"display_name": "SLCR Registers",
|
||||
"base_address": "0xF8000000",
|
||||
"range": "3K",
|
||||
"width": "32",
|
||||
"usage": "register"
|
||||
},
|
||||
"PS_System_Registers": {
|
||||
"name": "PS_System_Registers",
|
||||
"display_name": "PS System Registers",
|
||||
"base_address": "0xF8001000",
|
||||
"range": "8252K",
|
||||
"width": "32",
|
||||
"usage": "register"
|
||||
},
|
||||
"CPU_Private_Registers": {
|
||||
"name": "CPU_Private_Registers",
|
||||
"display_name": "CPU Private Registers",
|
||||
"base_address": "0xF8900000",
|
||||
"range": "6156K",
|
||||
"width": "32",
|
||||
"usage": "register"
|
||||
},
|
||||
"segment5": {
|
||||
"name": "segment5",
|
||||
"display_name": "segment5",
|
||||
"base_address": "0xFC000000",
|
||||
"range": "32M",
|
||||
"width": "32",
|
||||
"usage": "register"
|
||||
},
|
||||
"segment6": {
|
||||
"name": "segment6",
|
||||
"display_name": "segment6",
|
||||
"base_address": "0xFFFC0000",
|
||||
"range": "256K",
|
||||
"width": "32",
|
||||
"usage": "register"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"interface_nets": {
|
||||
"processing_system7_DDR": {
|
||||
"interface_ports": [
|
||||
"DDR",
|
||||
"processing_system7/DDR"
|
||||
]
|
||||
},
|
||||
"processing_system7_FIXED_IO": {
|
||||
"interface_ports": [
|
||||
"FIXED_IO",
|
||||
"processing_system7/FIXED_IO"
|
||||
]
|
||||
}
|
||||
},
|
||||
"nets": {
|
||||
"processing_system7_FCLK_CLK0": {
|
||||
"ports": [
|
||||
"processing_system7/FCLK_CLK0",
|
||||
"processing_system7/M_AXI_GP0_ACLK"
|
||||
]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,203 @@
|
||||
{
|
||||
"graphjs": {
|
||||
"version": "1.0",
|
||||
"keys": [
|
||||
{
|
||||
"abrv": "VH",
|
||||
"name": "vert_hid",
|
||||
"type": "int",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "VM",
|
||||
"name": "vert_name",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "VT",
|
||||
"name": "vert_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "BA",
|
||||
"name": "base_addr",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "HA",
|
||||
"name": "high_addr",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "BP",
|
||||
"name": "base_param",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "HP",
|
||||
"name": "high_param",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MA",
|
||||
"name": "master_addrspace",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MX",
|
||||
"name": "master_instance",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MI",
|
||||
"name": "master_interface",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MS",
|
||||
"name": "master_segment",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MV",
|
||||
"name": "master_vlnv",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "SX",
|
||||
"name": "slave_instance",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "SI",
|
||||
"name": "slave_interface",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MM",
|
||||
"name": "slave_memmap",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "SS",
|
||||
"name": "slave_segment",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "SV",
|
||||
"name": "slave_vlnv",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "TM",
|
||||
"name": "memory_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "TU",
|
||||
"name": "usage_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "LT",
|
||||
"name": "lock_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "BT",
|
||||
"name": "boot_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "EH",
|
||||
"name": "edge_hid",
|
||||
"type": "int",
|
||||
"for": "edge"
|
||||
}
|
||||
],
|
||||
"vertice_type_order": [
|
||||
{
|
||||
"abrv": "BC",
|
||||
"desc": "Block Container"
|
||||
},
|
||||
{
|
||||
"abrv": "PR",
|
||||
"desc": "Parital Reference"
|
||||
},
|
||||
{
|
||||
"abrv": "VR",
|
||||
"desc": "Variant"
|
||||
},
|
||||
{
|
||||
"abrv": "PM",
|
||||
"desc": "Variant Permutations"
|
||||
},
|
||||
{
|
||||
"abrv": "CX",
|
||||
"desc": "Boundary Connection"
|
||||
},
|
||||
{
|
||||
"abrv": "AC",
|
||||
"desc": "Assignment Coordinate"
|
||||
},
|
||||
{
|
||||
"abrv": "ACE",
|
||||
"desc": "Excluded Assign Coordinate"
|
||||
},
|
||||
{
|
||||
"abrv": "APX",
|
||||
"desc": "Boundary Aperture"
|
||||
},
|
||||
{
|
||||
"abrv": "CIP",
|
||||
"desc": "High level Processing System"
|
||||
}
|
||||
],
|
||||
"vertices": {
|
||||
"V0": {
|
||||
"VM": "system_bd",
|
||||
"VT": "BC"
|
||||
},
|
||||
"V1": {
|
||||
"VH": "2",
|
||||
"VM": "system_bd",
|
||||
"VT": "VR"
|
||||
},
|
||||
"V2": {
|
||||
"VH": "2",
|
||||
"VT": "PM",
|
||||
"TU": "active"
|
||||
}
|
||||
},
|
||||
"edges": [
|
||||
{
|
||||
"src": "V0",
|
||||
"trg": "V1"
|
||||
},
|
||||
{
|
||||
"src": "V1",
|
||||
"trg": "V2"
|
||||
}
|
||||
]
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,20 @@
|
||||
{
|
||||
"ActiveEmotionalView":"Default View",
|
||||
"Default View_ScaleFactor":"1.0",
|
||||
"Default View_TopLeft":"-654,-663",
|
||||
"ExpandedHierarchyInLayout":"",
|
||||
"guistr":"# # String gsaved with Nlview 7.7.1 2023-07-26 3bc4126617 VDI=43 GEI=38 GUI=JA:21.0 TLS
|
||||
# -string -flagsOSRD
|
||||
preplace port DDR -pg 1 -lvl 2 -x 420 -y -300 -defaultsOSRD
|
||||
preplace port FIXED_IO -pg 1 -lvl 2 -x 420 -y -280 -defaultsOSRD
|
||||
preplace inst processing_system7 -pg 1 -lvl 1 -x 200 -y -260 -defaultsOSRD
|
||||
preplace netloc processing_system7_FCLK_CLK0 1 0 2 0 -160 400
|
||||
preplace netloc processing_system7_DDR 1 1 1 NJ -300
|
||||
preplace netloc processing_system7_FIXED_IO 1 1 1 NJ -280
|
||||
levelinfo -pg 1 -20 200 420
|
||||
pagesize -pg 1 -db -bbox -sgen -20 -360 540 200
|
||||
"
|
||||
}
|
||||
{
|
||||
"da_ps7_cnt":"1"
|
||||
}
|
||||
+571
@@ -0,0 +1,571 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "ibert_7series_gtx_0",
|
||||
"component_reference": "xilinx.com:ip:ibert_7series_gtx:3.0",
|
||||
"ip_revision": "21",
|
||||
"gen_directory": "../../../../z7045_ibert.gen/sources_1/ip/ibert_7series_gtx_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"C_ENABLE_DIFF_TERM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"C_SYSCLK_FREQUENCY": [ { "value": "150.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"C_SYSCLK_IO_PIN_LOC_N": [ { "value": "UNASSIGNED", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"C_SYSCLK_IO_PIN_LOC_P": [ { "value": "UNASSIGNED", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"C_SYSCLK_IS_DIFF": [ { "value": "\"1\"", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||
"C_DISABLE_SYSCLK_BUF": [ { "value": "\"1\"", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||
"C_SYSCLK_IO_PIN_STD": [ { "value": "DIFF_SSTL15", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"C_SYSCLK_MODE_EXTERNAL": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||
"C_SYSCLOCK_SOURCE_INT": [ { "value": "QUAD110_0", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"C_RXOUTCLK_FREQUENCY": [ { "value": "300.0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"C_RXOUTCLK_N_PIN_LOCATION": [ { "value": "UNASSIGNED", "resolve_type": "user", "usage": "all" } ],
|
||||
"C_RXOUTCLK_PIN_LOCATION": [ { "value": "UNASSIGNED", "resolve_type": "user", "usage": "all" } ],
|
||||
"C_RXOUTCLK_IS_DIFF": [ { "value": "\"1\"", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||
"C_RXOUTCLK_PIN_STD": [ { "value": "DIFF_SSTL15", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"C_RXOUTCLK_GT_LOCATION": [ { "value": "QUAD_110", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"C_ADD_RXOUTCLK_PROBES": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"C_CHANNEL_QUAD_15": [ { "value": "Channel_0", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"C_CHANNEL_QUAD_14": [ { "value": "Channel_0", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"C_CHANNEL_QUAD_13": [ { "value": "Channel_0", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"C_CHANNEL_QUAD_12": [ { "value": "Channel_0", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"C_CHANNEL_QUAD_11": [ { "value": "Channel_0", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"C_CHANNEL_QUAD_10": [ { "value": "Channel_0", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"C_CHANNEL_QUAD_9": [ { "value": "Channel_0", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"C_CHANNEL_QUAD_8": [ { "value": "Channel_0", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"C_CHANNEL_QUAD_7": [ { "value": "Channel_0", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"C_CHANNEL_QUAD_6": [ { "value": "Channel_0", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"C_CHANNEL_QUAD_5": [ { "value": "Channel_0", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"C_CHANNEL_QUAD_4": [ { "value": "Channel_0", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"C_CHANNEL_QUAD_3": [ { "value": "Channel_0", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"C_CHANNEL_QUAD_2": [ { "value": "Channel_0", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"C_CHANNEL_QUAD_1": [ { "value": "Channel_0", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"C_CHANNEL_QUAD_0": [ { "value": "Channel_0", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"C_REFCLK_SOURCE_QUAD_15": [ { "value": "None", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"C_REFCLK_SOURCE_QUAD_14": [ { "value": "None", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"C_REFCLK_SOURCE_QUAD_13": [ { "value": "None", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"C_REFCLK_SOURCE_QUAD_12": [ { "value": "None", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"C_REFCLK_SOURCE_QUAD_11": [ { "value": "None", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"C_REFCLK_SOURCE_QUAD_10": [ { "value": "None", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"C_REFCLK_SOURCE_QUAD_9": [ { "value": "None", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"C_REFCLK_SOURCE_QUAD_8": [ { "value": "None", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"C_REFCLK_SOURCE_QUAD_7": [ { "value": "None", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"C_REFCLK_SOURCE_QUAD_6": [ { "value": "None", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"C_REFCLK_SOURCE_QUAD_5": [ { "value": "None", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"C_REFCLK_SOURCE_QUAD_4": [ { "value": "None", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"C_REFCLK_SOURCE_QUAD_3": [ { "value": "None", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"C_REFCLK_SOURCE_QUAD_2": [ { "value": "None", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"C_REFCLK_SOURCE_QUAD_1": [ { "value": "MGTREFCLK0_110", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"C_REFCLK_SOURCE_QUAD_0": [ { "value": "None", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"C_PROTOCOL_QUAD15": [ { "value": "None", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"C_PROTOCOL_QUAD14": [ { "value": "None", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"C_PROTOCOL_QUAD13": [ { "value": "None", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"C_PROTOCOL_QUAD12": [ { "value": "None", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"C_PROTOCOL_QUAD11": [ { "value": "None", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"C_PROTOCOL_QUAD10": [ { "value": "None", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"C_PROTOCOL_QUAD9": [ { "value": "None", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"C_PROTOCOL_QUAD8": [ { "value": "None", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"C_PROTOCOL_QUAD7": [ { "value": "None", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"C_PROTOCOL_QUAD6": [ { "value": "None", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"C_PROTOCOL_QUAD5": [ { "value": "None", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"C_PROTOCOL_QUAD4": [ { "value": "None", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"C_PROTOCOL_QUAD3": [ { "value": "None", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"C_PROTOCOL_QUAD2": [ { "value": "None", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"C_PROTOCOL_QUAD1": [ { "value": "Custom_1_/_9.6_Gbps", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"C_PROTOCOL_QUAD0": [ { "value": "None", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"C_GT_CORRECT": [ { "value": "\"1\"", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||
"C_CHECK_REFCLK_SOURCES": [ { "value": "\"1\"", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||
"C_PROTOCOL_GT_COUNT_3": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROTOCOL_GT_COUNT_2": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROTOCOL_GT_COUNT_1": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROTOCOL_RXREFCLK_FREQUENCY_3": [ { "value": "125.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"C_PROTOCOL_RXREFCLK_FREQUENCY_2": [ { "value": "125.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"C_PROTOCOL_RXREFCLK_FREQUENCY_1": [ { "value": "150.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"C_PROTOCOL_MAXLINERATE_3": [ { "value": "3.125", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"C_PROTOCOL_MAXLINERATE_2": [ { "value": "3.125", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"C_PROTOCOL_MAXLINERATE_1": [ { "value": "9.6", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"C_PROTOCOL_DATAWIDTH_3": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROTOCOL_DATAWIDTH_2": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROTOCOL_DATAWIDTH_1": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROTOCOL_3": [ { "value": "Custom_3", "resolve_type": "user", "usage": "all" } ],
|
||||
"C_PROTOCOL_2": [ { "value": "Custom_2", "resolve_type": "user", "usage": "all" } ],
|
||||
"C_PROTOCOL_1": [ { "value": "Custom_1", "resolve_type": "user", "usage": "all" } ],
|
||||
"C_PROTOCOL_USE_QUAD_PLL_3": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"C_PROTOCOL_USE_QUAD_PLL_2": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"C_PROTOCOL_USE_QUAD_PLL_1": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"C_PROTOCOL_COUNT": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_SI_VER": [ { "value": "General_ES/Production", "resolve_type": "user", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "ibert_7series_gtx_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_COMPONENT_NAME": [ { "value": "ibert_7series_gtx_0", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_SI_VER": [ { "value": "0x0300", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_PROTOCOL_COUNT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROTOCOL_1": [ { "value": "Custom_1", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PROTOCOL_2": [ { "value": "Custom_2", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PROTOCOL_3": [ { "value": "Custom_3", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PROTOCOL_MAXLINERATE_1": [ { "value": "9.6", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PROTOCOL_MAXLINERATE_2": [ { "value": "3.125", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PROTOCOL_MAXLINERATE_3": [ { "value": "3.125", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PROTOCOL_DATAWIDTH_1": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROTOCOL_DATAWIDTH_2": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROTOCOL_DATAWIDTH_3": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROTOCOL_RXREFCLK_FREQUENCY_1": [ { "value": "150.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PROTOCOL_RXREFCLK_FREQUENCY_2": [ { "value": "125.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PROTOCOL_RXREFCLK_FREQUENCY_3": [ { "value": "125.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PROTOCOL_GT_COUNT_1": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROTOCOL_GT_COUNT_2": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROTOCOL_GT_COUNT_3": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROTOCOL_USE_QUAD_PLL_1": [ { "value": "1", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_PROTOCOL_USE_QUAD_PLL_2": [ { "value": "1", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_PROTOCOL_USE_QUAD_PLL_3": [ { "value": "1", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_CHECK_REFCLK_SOURCES": [ { "value": "1", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_GT_CORRECT": [ { "value": "1", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_PROTOCOL_QUAD0": [ { "value": "None", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PROTOCOL_QUAD1": [ { "value": "Custom_1_/_9.6_Gbps", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PROTOCOL_QUAD2": [ { "value": "None", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PROTOCOL_QUAD3": [ { "value": "None", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PROTOCOL_QUAD4": [ { "value": "None", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PROTOCOL_QUAD5": [ { "value": "None", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PROTOCOL_QUAD6": [ { "value": "None", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PROTOCOL_QUAD7": [ { "value": "None", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PROTOCOL_QUAD8": [ { "value": "None", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PROTOCOL_QUAD9": [ { "value": "None", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PROTOCOL_QUAD10": [ { "value": "None", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PROTOCOL_QUAD11": [ { "value": "None", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PROTOCOL_QUAD12": [ { "value": "None", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PROTOCOL_QUAD13": [ { "value": "None", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PROTOCOL_QUAD14": [ { "value": "None", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PROTOCOL_QUAD15": [ { "value": "None", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_REFCLK_SOURCE_QUAD_0": [ { "value": "None", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_REFCLK_SOURCE_QUAD_1": [ { "value": "MGTREFCLK0_110", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_REFCLK_SOURCE_QUAD_2": [ { "value": "None", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_REFCLK_SOURCE_QUAD_3": [ { "value": "None", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_REFCLK_SOURCE_QUAD_4": [ { "value": "None", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_REFCLK_SOURCE_QUAD_5": [ { "value": "None", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_REFCLK_SOURCE_QUAD_6": [ { "value": "None", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_REFCLK_SOURCE_QUAD_7": [ { "value": "None", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_REFCLK_SOURCE_QUAD_8": [ { "value": "None", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_REFCLK_SOURCE_QUAD_9": [ { "value": "None", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_REFCLK_SOURCE_QUAD_10": [ { "value": "None", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_REFCLK_SOURCE_QUAD_11": [ { "value": "None", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_REFCLK_SOURCE_QUAD_12": [ { "value": "None", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_REFCLK_SOURCE_QUAD_13": [ { "value": "None", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_REFCLK_SOURCE_QUAD_14": [ { "value": "None", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_REFCLK_SOURCE_QUAD_15": [ { "value": "None", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CHANNEL_QUAD_0": [ { "value": "Channel_0", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CHANNEL_QUAD_1": [ { "value": "Channel_0", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CHANNEL_QUAD_2": [ { "value": "Channel_0", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CHANNEL_QUAD_3": [ { "value": "Channel_0", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CHANNEL_QUAD_4": [ { "value": "Channel_0", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CHANNEL_QUAD_5": [ { "value": "Channel_0", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CHANNEL_QUAD_6": [ { "value": "Channel_0", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CHANNEL_QUAD_7": [ { "value": "Channel_0", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CHANNEL_QUAD_8": [ { "value": "Channel_0", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CHANNEL_QUAD_9": [ { "value": "Channel_0", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CHANNEL_QUAD_10": [ { "value": "Channel_0", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CHANNEL_QUAD_11": [ { "value": "Channel_0", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CHANNEL_QUAD_12": [ { "value": "Channel_0", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CHANNEL_QUAD_13": [ { "value": "Channel_0", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CHANNEL_QUAD_14": [ { "value": "Channel_0", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CHANNEL_QUAD_15": [ { "value": "Channel_0", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_ADD_RXOUTCLK_PROBES": [ { "value": "0", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_RXOUTCLK_GT_LOCATION": [ { "value": "QUAD_110", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_RXOUTCLK_PIN_STD": [ { "value": "DIFF_SSTL15", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_RXOUTCLK_IS_DIFF": [ { "value": "1", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_RXOUTCLK_PIN_LOCATION": [ { "value": "UNASSIGNED", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_RXOUTCLK_N_PIN_LOCATION": [ { "value": "UNASSIGNED", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_RXOUTCLK_FREQUENCY": [ { "value": "300.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_SYSCLOCK_SOURCE_INT": [ { "value": "QUAD110_0", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_SYSCLK_MODE_EXTERNAL": [ { "value": "0", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_SYSCLK_IO_PIN_STD": [ { "value": "DIFF_SSTL15", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DISABLE_SYSCLK_BUF": [ { "value": "0", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_SYSCLK_IS_DIFF": [ { "value": "1", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_SYSCLK_IO_PIN_LOC_P": [ { "value": "UNASSIGNED", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_SYSCLK_IO_PIN_LOC_N": [ { "value": "UNASSIGNED", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_SYSCLK_FREQUENCY": [ { "value": "150.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_NUM_QUADS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ENABLE_DIFF_TERM": [ { "value": "0", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_XDEVICE": [ { "value": "xc7z045", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_FAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_XSPEEDGRADE": [ { "value": "-2", "resolve_type": "generated", "usage": "all" } ],
|
||||
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"C_SHARE_SOUTH_CLK0_Q12": [ { "value": "\"0\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_SHARE_SOUTH_CLK0_Q13": [ { "value": "\"0\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_SHARE_SOUTH_CLK0_Q14": [ { "value": "\"0\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_SHARE_SOUTH_CLK0_Q15": [ { "value": "\"0\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_SHARE_SOUTH_CLK1_Q0": [ { "value": "0", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_SHARE_SOUTH_CLK1_Q1": [ { "value": "0", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_SHARE_SOUTH_CLK1_Q2": [ { "value": "\"0\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_SHARE_SOUTH_CLK1_Q3": [ { "value": "\"0\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_SHARE_SOUTH_CLK1_Q4": [ { "value": "\"0\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_SHARE_SOUTH_CLK1_Q5": [ { "value": "\"0\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_SHARE_SOUTH_CLK1_Q6": [ { "value": "\"0\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_SHARE_SOUTH_CLK1_Q7": [ { "value": "\"0\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_SHARE_SOUTH_CLK1_Q8": [ { "value": "\"0\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_SHARE_SOUTH_CLK1_Q9": [ { "value": "\"0\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_SHARE_SOUTH_CLK1_Q10": [ { "value": "\"0\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_SHARE_SOUTH_CLK1_Q11": [ { "value": "\"0\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_SHARE_SOUTH_CLK1_Q12": [ { "value": "\"0\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_SHARE_SOUTH_CLK1_Q13": [ { "value": "\"0\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_SHARE_SOUTH_CLK1_Q14": [ { "value": "\"0\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_SHARE_SOUTH_CLK1_Q15": [ { "value": "\"0\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_MMCM_MULT": [ { "value": "20.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT0_DIVIDE": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_DIVCLK_DIVIDE": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_RXOUTCLK_SOURCE_VALUE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SYSCLOCK_REFCLK0_SOURCE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SYSCLOCK_REFCLK1_SOURCE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SYSCLOCK_SOURCE_VALUE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SYSCLK_DIVIDER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_XSDB_PERIOD_FRC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_XSDB_PERIOD_INT": [ { "value": "10", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ALL_DATA_WIDTHS": [ { "value": "0", "format": "long", "usage": "all" } ],
|
||||
"C_DMON_TRACE": [ { "value": "0", "format": "long", "usage": "all" } ],
|
||||
"C_DEVICE_FAMILY": [ { "value": "\"0000000000000101\"", "format": "bitString", "usage": "all" } ],
|
||||
"C_DEVICE_TYPE": [ { "value": "\"0000000000001000\"", "format": "bitString", "usage": "all" } ],
|
||||
"C_DEVICE_PACKAGE": [ { "value": "\"0000000000000010\"", "format": "bitString", "usage": "all" } ],
|
||||
"C_MAJOR_VERSION": [ { "value": "2013", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MINOR_VERSION": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_BUILD_REVISION": [ { "value": "0", "format": "long", "usage": "all" } ],
|
||||
"C_CORE_MAJOR_VER": [ { "value": "3", "format": "long", "usage": "all" } ],
|
||||
"C_CORE_MINOR_VER": [ { "value": "0", "format": "long", "usage": "all" } ],
|
||||
"C_CORE_MINOR_ALPHA_VER": [ { "value": "97", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z045" } ],
|
||||
"NEXTGEN_VERSAL": [ { "value": "0" } ],
|
||||
"PACKAGE": [ { "value": "ffg900" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Flow" } ],
|
||||
"IPREVISION": [ { "value": "21" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../z7045_ibert.gen/sources_1/ip/ibert_7series_gtx_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2024.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"TXN_O": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||
"TXP_O": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||
"RXOUTCLK_O": [ { "direction": "out" } ],
|
||||
"RXN_I": [ { "direction": "in", "size_left": "3", "size_right": "0" } ],
|
||||
"RXP_I": [ { "direction": "in", "size_left": "3", "size_right": "0" } ],
|
||||
"GTREFCLK0_I": [ { "direction": "in", "size_left": "0", "size_right": "0" } ],
|
||||
"GTREFCLK1_I": [ { "direction": "in", "size_left": "0", "size_right": "0" } ],
|
||||
"SYSCLK_I": [ { "direction": "in" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,168 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 07/02/2024 10:34:10 AM
|
||||
// Design Name:
|
||||
// Module Name: system_top
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`define C_NUM_QUADS 1
|
||||
`define C_REFCLKS_USED 1
|
||||
|
||||
module system_top
|
||||
(
|
||||
// GT ports
|
||||
TXN_O,
|
||||
TXP_O,
|
||||
RXN_I,
|
||||
RXP_I,
|
||||
GTREFCLK0P_I,
|
||||
GTREFCLK0N_I,
|
||||
GTREFCLK1P_I,
|
||||
GTREFCLK1N_I,
|
||||
|
||||
// PS ports
|
||||
DDR_addr,
|
||||
DDR_ba,
|
||||
DDR_cas_n,
|
||||
DDR_ck_n,
|
||||
DDR_ck_p,
|
||||
DDR_cke,
|
||||
DDR_cs_n,
|
||||
DDR_dm,
|
||||
DDR_dq,
|
||||
DDR_dqs_n,
|
||||
DDR_dqs_p,
|
||||
DDR_odt,
|
||||
DDR_ras_n,
|
||||
DDR_reset_n,
|
||||
DDR_we_n,
|
||||
FIXED_IO_ddr_vrn,
|
||||
FIXED_IO_ddr_vrp,
|
||||
FIXED_IO_mio,
|
||||
FIXED_IO_ps_clk,
|
||||
FIXED_IO_ps_porb,
|
||||
FIXED_IO_ps_srstb
|
||||
);
|
||||
|
||||
// GT ports
|
||||
output [(4*`C_NUM_QUADS)-1:0] TXN_O;
|
||||
output [(4*`C_NUM_QUADS)-1:0] TXP_O;
|
||||
input [(4*`C_NUM_QUADS)-1:0] RXN_I;
|
||||
input [(4*`C_NUM_QUADS)-1:0] RXP_I;
|
||||
input [`C_REFCLKS_USED-1:0] GTREFCLK0P_I;
|
||||
input [`C_REFCLKS_USED-1:0] GTREFCLK0N_I;
|
||||
input [`C_REFCLKS_USED-1:0] GTREFCLK1P_I;
|
||||
input [`C_REFCLKS_USED-1:0] GTREFCLK1N_I;
|
||||
|
||||
// PS ports
|
||||
inout [14:0]DDR_addr;
|
||||
inout [2:0]DDR_ba;
|
||||
inout DDR_cas_n;
|
||||
inout DDR_ck_n;
|
||||
inout DDR_ck_p;
|
||||
inout DDR_cke;
|
||||
inout DDR_cs_n;
|
||||
inout [3:0]DDR_dm;
|
||||
inout [31:0]DDR_dq;
|
||||
inout [3:0]DDR_dqs_n;
|
||||
inout [3:0]DDR_dqs_p;
|
||||
inout DDR_odt;
|
||||
inout DDR_ras_n;
|
||||
inout DDR_reset_n;
|
||||
inout DDR_we_n;
|
||||
inout FIXED_IO_ddr_vrn;
|
||||
inout FIXED_IO_ddr_vrp;
|
||||
inout [53:0]FIXED_IO_mio;
|
||||
inout FIXED_IO_ps_clk;
|
||||
inout FIXED_IO_ps_porb;
|
||||
inout FIXED_IO_ps_srstb;
|
||||
|
||||
system_bd_wrapper u_system_bd_wrapper
|
||||
(
|
||||
.DDR_addr (DDR_addr ),
|
||||
.DDR_ba (DDR_ba ),
|
||||
.DDR_cas_n (DDR_cas_n ),
|
||||
.DDR_ck_n (DDR_ck_n ),
|
||||
.DDR_ck_p (DDR_ck_p ),
|
||||
.DDR_cke (DDR_cke ),
|
||||
.DDR_cs_n (DDR_cs_n ),
|
||||
.DDR_dm (DDR_dm ),
|
||||
.DDR_dq (DDR_dq ),
|
||||
.DDR_dqs_n (DDR_dqs_n ),
|
||||
.DDR_dqs_p (DDR_dqs_p ),
|
||||
.DDR_odt (DDR_odt ),
|
||||
.DDR_ras_n (DDR_ras_n ),
|
||||
.DDR_reset_n (DDR_reset_n ),
|
||||
.DDR_we_n (DDR_we_n ),
|
||||
.FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn ),
|
||||
.FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp ),
|
||||
.FIXED_IO_mio (FIXED_IO_mio ),
|
||||
.FIXED_IO_ps_clk (FIXED_IO_ps_clk ),
|
||||
.FIXED_IO_ps_porb (FIXED_IO_ps_porb ),
|
||||
.FIXED_IO_ps_srstb (FIXED_IO_ps_srstb )
|
||||
);
|
||||
|
||||
|
||||
//
|
||||
// Ibert refclk internal signals
|
||||
//
|
||||
wire [`C_NUM_QUADS-1:0] gtrefclk0_i;
|
||||
wire [`C_NUM_QUADS-1:0] gtrefclk1_i;
|
||||
wire [`C_REFCLKS_USED-1:0] refclk0_i;
|
||||
wire [`C_REFCLKS_USED-1:0] refclk1_i;
|
||||
|
||||
//
|
||||
// Refclk IBUFDS instantiations
|
||||
//
|
||||
IBUFDS_GTE2 u_buf_q1_clk0
|
||||
(
|
||||
.O (refclk0_i[0] ),
|
||||
.ODIV2 ( ),
|
||||
.CEB (1'b0 ),
|
||||
.I (GTREFCLK0P_I[0]),
|
||||
.IB (GTREFCLK0N_I[0])
|
||||
);
|
||||
|
||||
IBUFDS_GTE2 u_buf_q1_clk1
|
||||
(
|
||||
.O (refclk1_i[0] ),
|
||||
.ODIV2 ( ),
|
||||
.CEB (1'b0 ),
|
||||
.I (GTREFCLK1P_I[0]),
|
||||
.IB (GTREFCLK1N_I[0])
|
||||
);
|
||||
|
||||
//
|
||||
// Refclk connection from each IBUFDS to respective quads depending on the source selected in gui
|
||||
//
|
||||
assign gtrefclk0_i[0] = refclk0_i[0];
|
||||
assign gtrefclk1_i[0] = refclk1_i[0];
|
||||
|
||||
//
|
||||
// IBERT core instantiation
|
||||
//
|
||||
ibert_7series_gtx_0 u_ibert_core
|
||||
(
|
||||
.TXN_O (TXN_O ),
|
||||
.TXP_O (TXP_O ),
|
||||
.RXN_I (RXN_I ),
|
||||
.RXP_I (RXP_I ),
|
||||
.GTREFCLK0_I(gtrefclk0_i),
|
||||
.GTREFCLK1_I(gtrefclk1_i)
|
||||
);
|
||||
|
||||
endmodule
|
||||
Binary file not shown.
@@ -0,0 +1,287 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2024.1 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
|
||||
<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Workspace/vivado/vivado_pub/projects/dj_47dr_z7045/z7045_ibert/z7045_ibert.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="3d32858e705a43cd88f5df0a8756955f"/>
|
||||
<Option Name="Part" Val="xc7z045ffg900-2"/>
|
||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||
<Option Name="SimulatorInstallDirModelSim" Val=""/>
|
||||
<Option Name="SimulatorInstallDirQuesta" Val=""/>
|
||||
<Option Name="SimulatorInstallDirXcelium" Val=""/>
|
||||
<Option Name="SimulatorInstallDirVCS" Val=""/>
|
||||
<Option Name="SimulatorInstallDirRiviera" Val=""/>
|
||||
<Option Name="SimulatorInstallDirActiveHdl" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirModelSim" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirQuesta" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirXcelium" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
|
||||
<Option Name="SimulatorVersionXsim" Val="2024.1"/>
|
||||
<Option Name="SimulatorVersionModelSim" Val="2023.2"/>
|
||||
<Option Name="SimulatorVersionQuesta" Val="2023.2"/>
|
||||
<Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
|
||||
<Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
|
||||
<Option Name="SimulatorVersionRiviera" Val="2023.04"/>
|
||||
<Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
|
||||
<Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
|
||||
<Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
|
||||
<Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
|
||||
<Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
|
||||
<Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
|
||||
<Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
|
||||
<Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
|
||||
<Option Name="BoardPart" Val=""/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
|
||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||
<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
|
||||
<Option Name="IPCachePermission" Val="read"/>
|
||||
<Option Name="IPCachePermission" Val="write"/>
|
||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||
<Option Name="EnableResourceEstimation" Val="FALSE"/>
|
||||
<Option Name="SimCompileState" Val="TRUE"/>
|
||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="5"/>
|
||||
<Option Name="WTModelSimExportSim" Val="5"/>
|
||||
<Option Name="WTQuestaExportSim" Val="5"/>
|
||||
<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="5"/>
|
||||
<Option Name="WTRivieraExportSim" Val="5"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="5"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
<Option Name="SimTypes" Val="rtl"/>
|
||||
<Option Name="SimTypes" Val="bfm"/>
|
||||
<Option Name="SimTypes" Val="tlm"/>
|
||||
<Option Name="SimTypes" Val="tlm_dpi"/>
|
||||
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
||||
<Option Name="DcpsUptoDate" Val="TRUE"/>
|
||||
<Option Name="ClassicSocBoot" Val="FALSE"/>
|
||||
<Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
|
||||
</Configuration>
|
||||
<FileSets Version="1" Minor="32">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PSRCDIR/sources_1/ip/ibert_7series_gtx_0/ibert_7series_gtx_0.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/bd/system_bd/system_bd.bd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
<CompFileExtendedInfo CompFileName="system_bd.bd" FileRelPathName="ip/system_bd_processing_system7_0_0/system_bd_processing_system7_0_0.xci">
|
||||
<Proxy FileSetName="system_bd_processing_system7_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
</File>
|
||||
<File Path="$PGENDIR/sources_1/bd/system_bd/hdl/system_bd_wrapper.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/system_top.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="system_top"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<File Path="$PSRCDIR/constrs_1/new/ibert_7series_gtx_0.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="system_top"/>
|
||||
<Option Name="TopLib" Val="xil_defaultlib"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SelectedSimModel" Val="rtl"/>
|
||||
<Option Name="PamDesignTestbench" Val=""/>
|
||||
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
|
||||
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
|
||||
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<File Path="$PSRCDIR/utils_1/imports/synth_1/system_top.dcp">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedInSteps" Val="synth_1"/>
|
||||
<Attr Name="AutoDcp" Val="1"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="system_bd_processing_system7_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_processing_system7_0_0" RelGenDir="$PGENDIR/system_bd_processing_system7_0_0">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="system_bd_processing_system7_0_0"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
<Option Name="Description" Val="Vivado Simulator"/>
|
||||
<Option Name="CompiledLib" Val="0"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ModelSim">
|
||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Questa">
|
||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Xcelium">
|
||||
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="VCS">
|
||||
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Riviera">
|
||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="22">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z045ffg900-2" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/system_top.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="system_bd_processing_system7_0_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_processing_system7_0_0" Part="xc7z045ffg900-2" ConstrsSet="system_bd_processing_system7_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_processing_system7_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_processing_system7_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_processing_system7_0_0_synth_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z045ffg900-2" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 18 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="system_bd_processing_system7_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z045ffg900-2" ConstrsSet="system_bd_processing_system7_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_processing_system7_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_processing_system7_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_processing_system7_0_0_impl_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<Board/>
|
||||
<DashboardSummary Version="1" Minor="0">
|
||||
<Dashboards>
|
||||
<Dashboard Name="default_dashboard">
|
||||
<Gadgets>
|
||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||
</Gadget>
|
||||
</Gadgets>
|
||||
</Dashboard>
|
||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||
</Dashboards>
|
||||
</DashboardSummary>
|
||||
</Project>
|
||||
Reference in New Issue
Block a user