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add dj_z7045 vivado project

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josh
2024-10-28 15:49:37 +08:00
parent 9d7e061dea
commit 55712526f7
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z7045_ibert/z7045_ibert.srcs/sources_1/bd/system_bd/ip/system_bd_processing_system7_0_0/system_bd_processing_system7_0_0.xci
+1263
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z7045_ibert/z7045_ibert.srcs/sources_1/bd/system_bd/system_bd.bd
+533
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{
"design": {
"design_info": {
"boundary_crc": "0xCC6CFA53B4580162",
"device": "xc7z045ffg900-2",
"gen_directory": "../../../../z7045_ibert.gen/sources_1/bd/system_bd",
"name": "system_bd",
"rev_ctrl_bd_flag": "RevCtrlBdOff",
"synth_flow_mode": "Hierarchical",
"tool_version": "2024.1",
"validated": "true"
},
"design_tree": {
"processing_system7": ""
},
"interface_ports": {
"DDR": {
"mode": "Master",
"vlnv_bus_definition": "xilinx.com:interface:ddrx:1.0",
"vlnv": "xilinx.com:interface:ddrx_rtl:1.0",
"parameters": {
"AXI_ARBITRATION_SCHEME": {
"value": "TDM",
"value_src": "default"
},
"BURST_LENGTH": {
"value": "8",
"value_src": "default"
},
"CAN_DEBUG": {
"value": "false",
"value_src": "default"
},
"CAS_LATENCY": {
"value": "11",
"value_src": "default"
},
"CAS_WRITE_LATENCY": {
"value": "11",
"value_src": "default"
},
"CS_ENABLED": {
"value": "true",
"value_src": "default"
},
"DATA_MASK_ENABLED": {
"value": "true",
"value_src": "default"
},
"DATA_WIDTH": {
"value": "8",
"value_src": "default"
},
"MEMORY_TYPE": {
"value": "COMPONENTS",
"value_src": "default"
},
"MEM_ADDR_MAP": {
"value": "ROW_COLUMN_BANK",
"value_src": "default"
},
"SLOT": {
"value": "Single",
"value_src": "default"
},
"TIMEPERIOD_PS": {
"value": "1250",
"value_src": "default"
}
},
"port_maps": {
"CAS_N": {
"physical_name": "DDR_cas_n",
"direction": "IO"
},
"CKE": {
"physical_name": "DDR_cke",
"direction": "IO"
},
"CK_N": {
"physical_name": "DDR_ck_n",
"direction": "IO"
},
"CK_P": {
"physical_name": "DDR_ck_p",
"direction": "IO"
},
"CS_N": {
"physical_name": "DDR_cs_n",
"direction": "IO"
},
"RESET_N": {
"physical_name": "DDR_reset_n",
"direction": "IO"
},
"ODT": {
"physical_name": "DDR_odt",
"direction": "IO"
},
"RAS_N": {
"physical_name": "DDR_ras_n",
"direction": "IO"
},
"WE_N": {
"physical_name": "DDR_we_n",
"direction": "IO"
},
"BA": {
"physical_name": "DDR_ba",
"direction": "IO",
"left": "2",
"right": "0"
},
"ADDR": {
"physical_name": "DDR_addr",
"direction": "IO",
"left": "14",
"right": "0"
},
"DM": {
"physical_name": "DDR_dm",
"direction": "IO",
"left": "3",
"right": "0"
},
"DQ": {
"physical_name": "DDR_dq",
"direction": "IO",
"left": "31",
"right": "0"
},
"DQS_N": {
"physical_name": "DDR_dqs_n",
"direction": "IO",
"left": "3",
"right": "0"
},
"DQS_P": {
"physical_name": "DDR_dqs_p",
"direction": "IO",
"left": "3",
"right": "0"
}
}
},
"FIXED_IO": {
"mode": "Master",
"vlnv_bus_definition": "xilinx.com:display_processing_system7:fixedio:1.0",
"vlnv": "xilinx.com:display_processing_system7:fixedio_rtl:1.0",
"parameters": {
"CAN_DEBUG": {
"value": "false",
"value_src": "default"
}
},
"port_maps": {
"MIO": {
"physical_name": "FIXED_IO_mio",
"direction": "IO",
"left": "53",
"right": "0"
},
"DDR_VRN": {
"physical_name": "FIXED_IO_ddr_vrn",
"direction": "IO"
},
"DDR_VRP": {
"physical_name": "FIXED_IO_ddr_vrp",
"direction": "IO"
},
"PS_SRSTB": {
"physical_name": "FIXED_IO_ps_srstb",
"direction": "IO"
},
"PS_CLK": {
"physical_name": "FIXED_IO_ps_clk",
"direction": "IO"
},
"PS_PORB": {
"physical_name": "FIXED_IO_ps_porb",
"direction": "IO"
}
}
}
},
"components": {
"processing_system7": {
"vlnv": "xilinx.com:ip:processing_system7:5.5",
"ip_revision": "6",
"xci_name": "system_bd_processing_system7_0_0",
"xci_path": "ip/system_bd_processing_system7_0_0/system_bd_processing_system7_0_0.xci",
"inst_hier_path": "processing_system7",
"parameters": {
"PCW_ACT_APU_PERIPHERAL_FREQMHZ": {
"value": "666.666687"
},
"PCW_ACT_CAN_PERIPHERAL_FREQMHZ": {
"value": "10.000000"
},
"PCW_ACT_DCI_PERIPHERAL_FREQMHZ": {
"value": "10.158730"
},
"PCW_ACT_ENET0_PERIPHERAL_FREQMHZ": {
"value": "10.000000"
},
"PCW_ACT_ENET1_PERIPHERAL_FREQMHZ": {
"value": "10.000000"
},
"PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ": {
"value": "50.000000"
},
"PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ": {
"value": "10.000000"
},
"PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ": {
"value": "10.000000"
},
"PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ": {
"value": "10.000000"
},
"PCW_ACT_PCAP_PERIPHERAL_FREQMHZ": {
"value": "200.000000"
},
"PCW_ACT_QSPI_PERIPHERAL_FREQMHZ": {
"value": "200.000000"
},
"PCW_ACT_SDIO_PERIPHERAL_FREQMHZ": {
"value": "10.000000"
},
"PCW_ACT_SMC_PERIPHERAL_FREQMHZ": {
"value": "10.000000"
},
"PCW_ACT_SPI_PERIPHERAL_FREQMHZ": {
"value": "10.000000"
},
"PCW_ACT_TPIU_PERIPHERAL_FREQMHZ": {
"value": "200.000000"
},
"PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ": {
"value": "111.111115"
},
"PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ": {
"value": "111.111115"
},
"PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ": {
"value": "111.111115"
},
"PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ": {
"value": "111.111115"
},
"PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ": {
"value": "111.111115"
},
"PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ": {
"value": "111.111115"
},
"PCW_ACT_UART_PERIPHERAL_FREQMHZ": {
"value": "10.000000"
},
"PCW_ACT_WDT_PERIPHERAL_FREQMHZ": {
"value": "111.111115"
},
"PCW_CLK0_FREQ": {
"value": "50000000"
},
"PCW_CLK1_FREQ": {
"value": "10000000"
},
"PCW_CLK2_FREQ": {
"value": "10000000"
},
"PCW_CLK3_FREQ": {
"value": "10000000"
},
"PCW_DDR_RAM_HIGHADDR": {
"value": "0x1FFFFFFF"
},
"PCW_EN_QSPI": {
"value": "1"
},
"PCW_FPGA_FCLK0_ENABLE": {
"value": "1"
},
"PCW_MIO_1_IOTYPE": {
"value": "LVCMOS 1.8V"
},
"PCW_MIO_1_PULLUP": {
"value": "enabled"
},
"PCW_MIO_1_SLEW": {
"value": "slow"
},
"PCW_MIO_2_IOTYPE": {
"value": "LVCMOS 1.8V"
},
"PCW_MIO_2_SLEW": {
"value": "slow"
},
"PCW_MIO_3_IOTYPE": {
"value": "LVCMOS 1.8V"
},
"PCW_MIO_3_SLEW": {
"value": "slow"
},
"PCW_MIO_4_IOTYPE": {
"value": "LVCMOS 1.8V"
},
"PCW_MIO_4_SLEW": {
"value": "slow"
},
"PCW_MIO_5_IOTYPE": {
"value": "LVCMOS 1.8V"
},
"PCW_MIO_5_SLEW": {
"value": "slow"
},
"PCW_MIO_6_IOTYPE": {
"value": "LVCMOS 1.8V"
},
"PCW_MIO_6_SLEW": {
"value": "slow"
},
"PCW_MIO_TREE_PERIPHERALS": {
"value": [
"unassigned#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI",
"Flash#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned"
]
},
"PCW_MIO_TREE_SIGNALS": {
"value": "unassigned#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned"
},
"PCW_PRESET_BANK0_VOLTAGE": {
"value": "LVCMOS 1.8V"
},
"PCW_PRESET_BANK1_VOLTAGE": {
"value": "LVCMOS 1.8V"
},
"PCW_QSPI_GRP_FBCLK_ENABLE": {
"value": "0"
},
"PCW_QSPI_GRP_IO1_ENABLE": {
"value": "0"
},
"PCW_QSPI_GRP_SINGLE_SS_ENABLE": {
"value": "1"
},
"PCW_QSPI_GRP_SINGLE_SS_IO": {
"value": "MIO 1 .. 6"
},
"PCW_QSPI_GRP_SS1_ENABLE": {
"value": "0"
},
"PCW_QSPI_PERIPHERAL_ENABLE": {
"value": "1"
},
"PCW_QSPI_PERIPHERAL_FREQMHZ": {
"value": "200"
},
"PCW_QSPI_QSPI_IO": {
"value": "MIO 1 .. 6"
},
"PCW_SINGLE_QSPI_DATA_MODE": {
"value": "x4"
},
"PCW_UIPARAM_ACT_DDR_FREQ_MHZ": {
"value": "533.333374"
},
"PCW_UIPARAM_DDR_BUS_WIDTH": {
"value": "16 Bit"
},
"PCW_UIPARAM_DDR_ECC": {
"value": "Disabled"
},
"PCW_UIPARAM_DDR_PARTNO": {
"value": "MT41J256M16 RE-125"
}
},
"interface_ports": {
"M_AXI_GP0": {
"vlnv": "xilinx.com:interface:aximm_rtl:1.0",
"mode": "Master",
"address_space_ref": "Data",
"base_address": {
"minimum": "0x40000000",
"maximum": "0x7FFFFFFF",
"width": "32"
}
}
},
"addressing": {
"address_spaces": {
"Data": {
"range": "4G",
"width": "32",
"local_memory_map": {
"name": "Data",
"description": "Address Space Segments",
"address_blocks": {
"segment1": {
"name": "segment1",
"display_name": "segment1",
"base_address": "0x00000000",
"range": "256K",
"width": "18",
"usage": "register"
},
"segment2": {
"name": "segment2",
"display_name": "segment2",
"base_address": "0x00040000",
"range": "256K",
"width": "19",
"usage": "register"
},
"segment3": {
"name": "segment3",
"display_name": "segment3",
"base_address": "0x00080000",
"range": "512K",
"width": "20",
"usage": "register"
},
"segment4": {
"name": "segment4",
"display_name": "segment4",
"base_address": "0x00100000",
"range": "1023M",
"width": "30",
"usage": "register"
},
"M_AXI_GP0": {
"name": "M_AXI_GP0",
"display_name": "M_AXI_GP0",
"base_address": "0x40000000",
"range": "1G",
"width": "31",
"usage": "register"
},
"M_AXI_GP1": {
"name": "M_AXI_GP1",
"display_name": "M_AXI_GP1",
"base_address": "0x80000000",
"range": "1G",
"width": "32",
"usage": "register"
},
"IO_Peripheral_Registers": {
"name": "IO_Peripheral_Registers",
"display_name": "IO Peripheral Registers",
"base_address": "0xE0000000",
"range": "3M",
"width": "32",
"usage": "register"
},
"SMC_Memories": {
"name": "SMC_Memories",
"display_name": "SMC Memories",
"base_address": "0xE1000000",
"range": "80M",
"width": "32",
"usage": "register"
},
"SLCR_Registers": {
"name": "SLCR_Registers",
"display_name": "SLCR Registers",
"base_address": "0xF8000000",
"range": "3K",
"width": "32",
"usage": "register"
},
"PS_System_Registers": {
"name": "PS_System_Registers",
"display_name": "PS System Registers",
"base_address": "0xF8001000",
"range": "8252K",
"width": "32",
"usage": "register"
},
"CPU_Private_Registers": {
"name": "CPU_Private_Registers",
"display_name": "CPU Private Registers",
"base_address": "0xF8900000",
"range": "6156K",
"width": "32",
"usage": "register"
},
"segment5": {
"name": "segment5",
"display_name": "segment5",
"base_address": "0xFC000000",
"range": "32M",
"width": "32",
"usage": "register"
},
"segment6": {
"name": "segment6",
"display_name": "segment6",
"base_address": "0xFFFC0000",
"range": "256K",
"width": "32",
"usage": "register"
}
}
}
}
}
}
}
},
"interface_nets": {
"processing_system7_DDR": {
"interface_ports": [
"DDR",
"processing_system7/DDR"
]
},
"processing_system7_FIXED_IO": {
"interface_ports": [
"FIXED_IO",
"processing_system7/FIXED_IO"
]
}
},
"nets": {
"processing_system7_FCLK_CLK0": {
"ports": [
"processing_system7/FCLK_CLK0",
"processing_system7/M_AXI_GP0_ACLK"
]
}
}
}
}
z7045_ibert/z7045_ibert.srcs/sources_1/bd/system_bd/system_bd.bda
+203
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{
"graphjs": {
"version": "1.0",
"keys": [
{
"abrv": "VH",
"name": "vert_hid",
"type": "int",
"for": "node"
},
{
"abrv": "VM",
"name": "vert_name",
"type": "string",
"for": "node"
},
{
"abrv": "VT",
"name": "vert_type",
"type": "string",
"for": "node"
},
{
"abrv": "BA",
"name": "base_addr",
"type": "string",
"for": "node"
},
{
"abrv": "HA",
"name": "high_addr",
"type": "string",
"for": "node"
},
{
"abrv": "BP",
"name": "base_param",
"type": "string",
"for": "node"
},
{
"abrv": "HP",
"name": "high_param",
"type": "string",
"for": "node"
},
{
"abrv": "MA",
"name": "master_addrspace",
"type": "string",
"for": "node"
},
{
"abrv": "MX",
"name": "master_instance",
"type": "string",
"for": "node"
},
{
"abrv": "MI",
"name": "master_interface",
"type": "string",
"for": "node"
},
{
"abrv": "MS",
"name": "master_segment",
"type": "string",
"for": "node"
},
{
"abrv": "MV",
"name": "master_vlnv",
"type": "string",
"for": "node"
},
{
"abrv": "SX",
"name": "slave_instance",
"type": "string",
"for": "node"
},
{
"abrv": "SI",
"name": "slave_interface",
"type": "string",
"for": "node"
},
{
"abrv": "MM",
"name": "slave_memmap",
"type": "string",
"for": "node"
},
{
"abrv": "SS",
"name": "slave_segment",
"type": "string",
"for": "node"
},
{
"abrv": "SV",
"name": "slave_vlnv",
"type": "string",
"for": "node"
},
{
"abrv": "TM",
"name": "memory_type",
"type": "string",
"for": "node"
},
{
"abrv": "TU",
"name": "usage_type",
"type": "string",
"for": "node"
},
{
"abrv": "LT",
"name": "lock_type",
"type": "string",
"for": "node"
},
{
"abrv": "BT",
"name": "boot_type",
"type": "string",
"for": "node"
},
{
"abrv": "EH",
"name": "edge_hid",
"type": "int",
"for": "edge"
}
],
"vertice_type_order": [
{
"abrv": "BC",
"desc": "Block Container"
},
{
"abrv": "PR",
"desc": "Parital Reference"
},
{
"abrv": "VR",
"desc": "Variant"
},
{
"abrv": "PM",
"desc": "Variant Permutations"
},
{
"abrv": "CX",
"desc": "Boundary Connection"
},
{
"abrv": "AC",
"desc": "Assignment Coordinate"
},
{
"abrv": "ACE",
"desc": "Excluded Assign Coordinate"
},
{
"abrv": "APX",
"desc": "Boundary Aperture"
},
{
"abrv": "CIP",
"desc": "High level Processing System"
}
],
"vertices": {
"V0": {
"VM": "system_bd",
"VT": "BC"
},
"V1": {
"VH": "2",
"VM": "system_bd",
"VT": "VR"
},
"V2": {
"VH": "2",
"VT": "PM",
"TU": "active"
}
},
"edges": [
{
"src": "V0",
"trg": "V1"
},
{
"src": "V1",
"trg": "V2"
}
]
}
}
z7045_ibert/z7045_ibert.srcs/sources_1/bd/system_bd/ui/bd_c6d0cb12.ui
+20
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@@ -0,0 +1,20 @@
{
"ActiveEmotionalView":"Default View",
"Default View_ScaleFactor":"1.0",
"Default View_TopLeft":"-654,-663",
"ExpandedHierarchyInLayout":"",
"guistr":"# # String gsaved with Nlview 7.7.1 2023-07-26 3bc4126617 VDI=43 GEI=38 GUI=JA:21.0 TLS
# -string -flagsOSRD
preplace port DDR -pg 1 -lvl 2 -x 420 -y -300 -defaultsOSRD
preplace port FIXED_IO -pg 1 -lvl 2 -x 420 -y -280 -defaultsOSRD
preplace inst processing_system7 -pg 1 -lvl 1 -x 200 -y -260 -defaultsOSRD
preplace netloc processing_system7_FCLK_CLK0 1 0 2 0 -160 400
preplace netloc processing_system7_DDR 1 1 1 NJ -300
preplace netloc processing_system7_FIXED_IO 1 1 1 NJ -280
levelinfo -pg 1 -20 200 420
pagesize -pg 1 -db -bbox -sgen -20 -360 540 200
"
}
{
"da_ps7_cnt":"1"
}
z7045_ibert/z7045_ibert.srcs/sources_1/ip/ibert_7series_gtx_0/ibert_7series_gtx_0.xci
+571
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@@ -0,0 +1,571 @@
{
"schema": "xilinx.com:schema:json_instance:1.0",
"ip_inst": {
"xci_name": "ibert_7series_gtx_0",
"component_reference": "xilinx.com:ip:ibert_7series_gtx:3.0",
"ip_revision": "21",
"gen_directory": "../../../../z7045_ibert.gen/sources_1/ip/ibert_7series_gtx_0",
"parameters": {
"component_parameters": {
"C_ENABLE_DIFF_TERM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"C_SYSCLK_FREQUENCY": [ { "value": "150.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"C_SYSCLK_IO_PIN_LOC_N": [ { "value": "UNASSIGNED", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"C_SYSCLK_IO_PIN_LOC_P": [ { "value": "UNASSIGNED", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"C_SYSCLK_IS_DIFF": [ { "value": "\"1\"", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
"C_DISABLE_SYSCLK_BUF": [ { "value": "\"1\"", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
"C_SYSCLK_IO_PIN_STD": [ { "value": "DIFF_SSTL15", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"C_SYSCLK_MODE_EXTERNAL": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
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},
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"BASE_BOARD_PART": [ { "value": "" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xc7z045" } ],
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"TEMPERATURE_GRADE": [ { "value": "" } ]
},
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"IPREVISION": [ { "value": "21" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "../../../../z7045_ibert.gen/sources_1/ip/ibert_7series_gtx_0" } ],
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"SHAREDDIR": [ { "value": "." } ],
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"GTREFCLK1_I": [ { "direction": "in", "size_left": "0", "size_right": "0" } ],
"SYSCLK_I": [ { "direction": "in" } ]
}
}
}
}
z7045_ibert/z7045_ibert.srcs/sources_1/new/system_top.v
+168
View File
@@ -0,0 +1,168 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 07/02/2024 10:34:10 AM
// Design Name:
// Module Name: system_top
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`define C_NUM_QUADS 1
`define C_REFCLKS_USED 1
module system_top
(
// GT ports
TXN_O,
TXP_O,
RXN_I,
RXP_I,
GTREFCLK0P_I,
GTREFCLK0N_I,
GTREFCLK1P_I,
GTREFCLK1N_I,
// PS ports
DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb
);
// GT ports
output [(4*`C_NUM_QUADS)-1:0] TXN_O;
output [(4*`C_NUM_QUADS)-1:0] TXP_O;
input [(4*`C_NUM_QUADS)-1:0] RXN_I;
input [(4*`C_NUM_QUADS)-1:0] RXP_I;
input [`C_REFCLKS_USED-1:0] GTREFCLK0P_I;
input [`C_REFCLKS_USED-1:0] GTREFCLK0N_I;
input [`C_REFCLKS_USED-1:0] GTREFCLK1P_I;
input [`C_REFCLKS_USED-1:0] GTREFCLK1N_I;
// PS ports
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
system_bd_wrapper u_system_bd_wrapper
(
.DDR_addr (DDR_addr ),
.DDR_ba (DDR_ba ),
.DDR_cas_n (DDR_cas_n ),
.DDR_ck_n (DDR_ck_n ),
.DDR_ck_p (DDR_ck_p ),
.DDR_cke (DDR_cke ),
.DDR_cs_n (DDR_cs_n ),
.DDR_dm (DDR_dm ),
.DDR_dq (DDR_dq ),
.DDR_dqs_n (DDR_dqs_n ),
.DDR_dqs_p (DDR_dqs_p ),
.DDR_odt (DDR_odt ),
.DDR_ras_n (DDR_ras_n ),
.DDR_reset_n (DDR_reset_n ),
.DDR_we_n (DDR_we_n ),
.FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn ),
.FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp ),
.FIXED_IO_mio (FIXED_IO_mio ),
.FIXED_IO_ps_clk (FIXED_IO_ps_clk ),
.FIXED_IO_ps_porb (FIXED_IO_ps_porb ),
.FIXED_IO_ps_srstb (FIXED_IO_ps_srstb )
);
//
// Ibert refclk internal signals
//
wire [`C_NUM_QUADS-1:0] gtrefclk0_i;
wire [`C_NUM_QUADS-1:0] gtrefclk1_i;
wire [`C_REFCLKS_USED-1:0] refclk0_i;
wire [`C_REFCLKS_USED-1:0] refclk1_i;
//
// Refclk IBUFDS instantiations
//
IBUFDS_GTE2 u_buf_q1_clk0
(
.O (refclk0_i[0] ),
.ODIV2 ( ),
.CEB (1'b0 ),
.I (GTREFCLK0P_I[0]),
.IB (GTREFCLK0N_I[0])
);
IBUFDS_GTE2 u_buf_q1_clk1
(
.O (refclk1_i[0] ),
.ODIV2 ( ),
.CEB (1'b0 ),
.I (GTREFCLK1P_I[0]),
.IB (GTREFCLK1N_I[0])
);
//
// Refclk connection from each IBUFDS to respective quads depending on the source selected in gui
//
assign gtrefclk0_i[0] = refclk0_i[0];
assign gtrefclk1_i[0] = refclk1_i[0];
//
// IBERT core instantiation
//
ibert_7series_gtx_0 u_ibert_core
(
.TXN_O (TXN_O ),
.TXP_O (TXP_O ),
.RXN_I (RXN_I ),
.RXP_I (RXP_I ),
.GTREFCLK0_I(gtrefclk0_i),
.GTREFCLK1_I(gtrefclk1_i)
);
endmodule