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add dj_47dr_ibert vitis classic project

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josh
2024-10-28 15:44:11 +08:00
parent 8fce3b4839
commit 9d7e061dea
4743 changed files with 1594840 additions and 0 deletions
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dj_47dr_ibert/vitis_classic/system_top/.cproject
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
<storageModule moduleId="org.eclipse.cdt.core.settings">
<cconfiguration id="org.eclipse.cdt.core.default.config.1443200959">
<storageModule buildSystemId="org.eclipse.cdt.core.defaultConfigDataProvider" id="org.eclipse.cdt.core.default.config.1443200959" moduleId="org.eclipse.cdt.core.settings" name="Configuration">
<externalSettings/>
<extensions/>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
</cconfiguration>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
</cproject>
dj_47dr_ibert/vitis_classic/system_top/.gitignore
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/export/
*.o
*.d
dj_47dr_ibert/vitis_classic/system_top/.project
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<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>system_top</name>
<comment>Created by Vitis v2024.1</comment>
<projects>
</projects>
<buildSpec>
<buildCommand>
<name>com.xilinx.sdx.scw.PlatformProjectBuilder</name>
<arguments>
</arguments>
</buildCommand>
</buildSpec>
<natures>
<nature>com.xilinx.sdx.scw.platformProject</nature>
<nature>org.eclipse.cdt.core.cnature</nature>
</natures>
</projectDescription>
dj_47dr_ibert/vitis_classic/system_top/hw/psu_init.c
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dj_47dr_ibert/vitis_classic/system_top/hw/psu_init.h
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dj_47dr_ibert/vitis_classic/system_top/hw/psu_init.html
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dj_47dr_ibert/vitis_classic/system_top/hw/psu_init.tcl
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dj_47dr_ibert/vitis_classic/system_top/hw/psu_init_gpl.c
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dj_47dr_ibert/vitis_classic/system_top/hw/psu_init_gpl.h
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dj_47dr_ibert/vitis_classic/system_top/hw/system_top.bit
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dj_47dr_ibert/vitis_classic/system_top/hw/system_top.xsa
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dj_47dr_ibert/vitis_classic/system_top/platform.spr
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{"platformName":"system_top","sprVersion":"2.0","mode":"gui","dsaType":"Fixed","platformDesc":"system_top","platHandOff":"/home/josh/dj_47dr_ibert/system_top.xsa","platIntHandOff":"<platformDir>/hw/system_top.xsa","deviceType":"zynqMP","platIsPrebuiltAutogen":"false","platIsNoBootBsp":"false","platFsblTarget":"psu_cortexa53_0","hasFsblMakeHasChanges":"false","hasPmufwMakeHasChanges":"false","fsblExtraCompilerFlags":"-MMD -MP -Wall -fmessage-length=0 -DARMA53_64 -Os -flto -ffat-lto-objects ","pmufwExtraCompilerFlags":"-MMD -MP -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mcpu=v9.2 -mxl-soft-mul -Os -flto -ffat-lto-objects ","platPreBuiltFlag":false,"platformSamplesDir":"","platActiveSys":"system_top","systems":[{"systemName":"system_top","systemDesc":"system_top","sysIsBootAutoGen":"true","systemDispName":"system_top","sysActiveDom":"standalone_psu_cortexa53_0","sysDefaultDom":"standalone_psu_cortexa53_0","domains":[{"domainName":"zynqmp_fsbl","domainDispName":"zynqmp_fsbl","domainDesc":"FSBL Application BSP - Auto Generated.","processors":"psu_cortexa53_0","os":"standalone","sdxOs":"standalone","debugEnable":"","domRuntimes":["cpp"],"swRepo":"","mssOsVer":"9.1","mssFile":"","md5Digest":"aa0403ecc96b493b46451bd1df82fc201","compatibleApp":"zynqmp_fsbl","domType":"bootDomain","arch":"64-bit","appSettings":{"appCompilerFlags":"","appLinkerFlags":""},"addedLibs":["xilffs:5.2","xilsecure:5.3","xilpm:5.2"],"libOptions":{"standalone":{"zynqmp_fsbl_bsp":"true","libOptionNames":["zynqmp_fsbl_bsp"]},"xilffs":{"read_only":"true","use_mkfs":"false","libOptionNames":["read_only","use_mkfs"]},"xilsecure":{"tpm_support":"true","libOptionNames":["tpm_support"]},"libsContainingOptions":["standalone","xilffs","xilsecure"]},"prebuiltLibs":{"prebuiltIncPath":[],"prebuiltLibPath":[]},"isolation":{}},{"domainName":"zynqmp_pmufw","domainDispName":"zynqmp_pmufw","domainDesc":"PMUFW Application BSP - Auto Generated.","processors":"psu_pmu_0","os":"standalone","sdxOs":"standalone","debugEnable":"","domRuntimes":["cpp"],"swRepo":"","mssOsVer":"9.1","mssFile":"","md5Digest":"73b6b202eb9eb62280586e95f9c5a9c61","compatibleApp":"zynqmp_pmufw","domType":"bootDomain","arch":"32-bit","appSettings":{"appCompilerFlags":"","appLinkerFlags":""},"addedLibs":["xilfpga:6.6","xilsecure:5.3","xilskey:7.6"],"libOptions":{"psu_pmu_0":{"extra_compiler_flags":"-g -ffunction-sections -fdata-sections -Wall -Wextra -fno-tree-loop-distribute-patterns -Os -flto -ffat-lto-objects","libOptionNames":["extra_compiler_flags"]},"libsContainingOptions":["psu_pmu_0"]},"prebuiltLibs":{"prebuiltIncPath":[],"prebuiltLibPath":[]},"isolation":{}},{"domainName":"standalone_psu_cortexa53_0","domainDispName":"standalone_psu_cortexa53_0","domainDesc":"standalone_psu_cortexa53_0","processors":"psu_cortexa53_0","os":"standalone","sdxOs":"standalone","qemuArgs":"<platformDir>/resources/system_top/standalone_psu_cortexa53_0/qemu_args.txt","qemuData":"<platformDir>/resources/system_top/standalone_psu_cortexa53_0/qemu","pmuQemuArgs":"<platformDir>/resources/system_top/standalone_psu_cortexa53_0/pmu_args.txt","debugEnable":"False","domRuntimes":["cpp"],"swRepo":"","mssOsVer":"9.1","mssFile":"","md5Digest":"95602ffcf523057eb4ed533b1a9f297a","compatibleApp":"","domType":"mssDomain","arch":"64-bit","appSettings":{"appCompilerFlags":"","appLinkerFlags":""},"addedLibs":[],"libOptions":{"standalone":{"stdin":"psu_coresight_0","stdout":"psu_coresight_0","libOptionNames":["stdin","stdout"]},"libsContainingOptions":["standalone"]},"prebuiltLibs":{"prebuiltIncPath":[],"prebuiltLibPath":[]},"isolation":{}}]}]}
dj_47dr_ibert/vitis_classic/system_top/platform.tcl
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#
# Usage: To re-create this platform project launch xsct with below options.
# xsct /home/josh/dj_47dr_ibert/vitis_classic/system_top/platform.tcl
#
# OR launch xsct and run below command.
# source /home/josh/dj_47dr_ibert/vitis_classic/system_top/platform.tcl
#
# To create the platform in a different location, modify the -out option of "platform create" command.
# -out option specifies the output directory of the platform project.
platform create -name {system_top}\
-hw {/home/josh/dj_47dr_ibert/system_top.xsa}\
-arch {64-bit} -fsbl-target {psu_cortexa53_0} -out {/home/josh/dj_47dr_ibert/vitis_classic}
platform write
domain create -name {standalone_psu_cortexa53_0} -display-name {standalone_psu_cortexa53_0} -os {standalone} -proc {psu_cortexa53_0} -runtime {cpp} -arch {64-bit} -support-app {hello_world}
platform generate -domains
platform active {system_top}
domain active {zynqmp_fsbl}
domain active {zynqmp_pmufw}
domain active {standalone_psu_cortexa53_0}
platform generate -quick
platform generate
platform config -updatehw {/home/josh/dj_47dr_ibert/system_top.xsa}
platform generate -domains
bsp reload
bsp config stdin "psu_coresight_0"
bsp config stdout "psu_coresight_0"
bsp write
bsp reload
catch {bsp regenerate}
platform generate -domains standalone_psu_cortexa53_0
platform active {system_top}
platform config -updatehw {/home/josh/dj_47dr_ibert/system_top.xsa}
platform generate -domains
platform active {system_top}
bsp reload
bsp config stdin "psu_coresight_0"
bsp reload
platform generate -domains
platform active {system_top}
platform generate -domains
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/Makefile
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# Makefile generated by Xilinx.
DRIVER_LIB_VERSION = 1.0
PROCESSOR = psu_cortexa53_0
LIBRARIES = ${PROCESSOR}/lib/libxil.a
BSP_MAKEFILES := $(wildcard $(PROCESSOR)/libsrc/*/src/Makefile)
SUBDIRS := $(patsubst %/Makefile, %, $(BSP_MAKEFILES))
BSP_SEQUENTIAL_MAKEFILES := psu_cortexa53_0/libsrc/libmetal_v2_7/src/Makefile
BSP_PARALLEL_MAKEFILES := $(filter-out $(BSP_SEQUENTIAL_MAKEFILES),$(BSP_MAKEFILES))
SEQ_SUBDIRS := $(patsubst %/Makefile, %, $(BSP_SEQUENTIAL_MAKEFILES))
PAR_SUBDIRS := $(patsubst %/Makefile, %, $(BSP_PARALLEL_MAKEFILES))
ifneq (,$(findstring win,$(RDI_PLATFORM)))
SHELL = CMD
endif
all:
$(MAKE) --no-print-directory seq_libs
$(MAKE) -j 18 --no-print-directory par_libs
$(MAKE) --no-print-directory archive
@echo 'Finished building libraries'
include: $(addsuffix /make.include,$(SUBDIRS))
seq_libs: $(addsuffix /make.libs,$(SEQ_SUBDIRS))
@echo 'Finished building libraries sequentially.'
par_libs: $(addsuffix /make.libs,$(PAR_SUBDIRS))
@echo 'Finished building libraries parallelly.'
archive:
aarch64-none-elf-ar -r $(LIBRARIES) $(sort $(wildcard $(PROCESSOR)/lib/*.o))
clean: $(addsuffix /make.clean,$(SUBDIRS))
rm -f ${PROCESSOR}/lib/libxil.a
$(PROCESSOR)/lib/libxil.a: $(PROCESSOR)/lib/libxil_init.a
cp -f $< $@
%/make.include: $(if $(wildcard $(PROCESSOR)/lib/libxil_init.a),$(PROCESSOR)/lib/libxil.a,)
@echo "Running Make include in $(subst /make.include,,$@)"
$(MAKE) -C $(subst /make.include,,$@) -s include "SHELL=$(SHELL)" "COMPILER=aarch64-none-elf-gcc" "ASSEMBLER=aarch64-none-elf-as" "ARCHIVER=aarch64-none-elf-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-g -Wall -Wextra -fno-tree-loop-distribute-patterns"
%/make.libs: include
@echo "Running Make libs in $(subst /make.libs,,$@)"
$(MAKE) -C $(subst /make.libs,,$@) -s libs "SHELL=$(SHELL)" "COMPILER=aarch64-none-elf-gcc" "ASSEMBLER=aarch64-none-elf-as" "ARCHIVER=aarch64-none-elf-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-g -Wall -Wextra -fno-tree-loop-distribute-patterns"
%/make.clean:
$(MAKE) -C $(subst /make.clean,,$@) -s clean
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/dep.mk
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# generated by Xilinx.
DEPENDENCY_FLAGS= -MMD -MP
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/bspconfig.h
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/*******************************************************************
*
* CAUTION: This file is automatically generated by HSI.
* Version: 2024.1
* DO NOT EDIT.
*
* Copyright (C) 2010-2024 Xilinx, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
*
* Description: Configurations for Standalone BSP
*
*******************************************************************/
#ifndef BSPCONFIG_H /* prevent circular inclusions */
#define BSPCONFIG_H /* by using protection macros */
#define MICROBLAZE_PVR_NONE
#define EL3 1
#define EL1_NONSECURE 0
#define HYP_GUEST 0
#endif /*end of __BSPCONFIG_H_*/
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/metal/alloc.h
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/*
* Copyright (c) 2016-2022 Xilinx, Inc. and Contributors. All rights reserved.
* Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* @file alloc.h
* @brief Memory allocation handling primitives for libmetal.
*/
#ifndef __METAL_ALLOC__H__
#define __METAL_ALLOC__H__
#include <metal/system/generic/alloc.h>
#ifdef __cplusplus
extern "C" {
#endif
/** \defgroup Memory Allocation Interfaces
* @{
*/
/**
* @brief allocate requested memory size
* return a pointer to the allocated memory
*
* @param[in] size size in byte of requested memory
* @return memory pointer, or 0 if it failed to allocate
*/
static inline void *metal_allocate_memory(unsigned int size)
{
return __metal_allocate_memory(size);
}
/**
* @brief free the memory previously allocated
*
* @param[in] ptr pointer to memory
*/
static inline void metal_free_memory(void *ptr)
{
__metal_free_memory(ptr);
}
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* __METAL_ALLOC__H__ */
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/metal/assert.h
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/*
* Copyright (c) 2018, Xilinx Inc. and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* @file assert.h
* @brief Assertion support.
*/
#ifndef __METAL_ASSERT__H__
#define __METAL_ASSERT__H__
#include <metal/system/generic/assert.h>
/**
* @brief Assertion macro.
* @param cond Condition to test.
*/
#define metal_assert(cond) metal_sys_assert(cond)
#endif /* __METAL_ASSERT_H__ */
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/metal/atomic.h
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/*
* Copyright (c) 2015-2022, Xilinx Inc. and Contributors. All rights reserved.
* Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* @file atomic.h
* @brief Atomic primitives for libmetal.
*/
#ifndef __METAL_ATOMIC__H__
#define __METAL_ATOMIC__H__
#include <metal/config.h>
#if defined(__cplusplus)
# include <cstdint>
/*
* <atomic> has the same functionality as <stdatomic.h> but all members are only
* accessible in the std namespace. As the rest of libmetal is pure C, it does
* not know about namespaces, even when compiled as part of a C++ file. So we
* just export the members of <atomic> into the global namespace.
*/
# include <atomic>
using std::atomic_flag;
using std::memory_order;
using std::memory_order_relaxed;
using std::memory_order_consume;
using std::memory_order_acquire;
using std::memory_order_release;
using std::memory_order_acq_rel;
using std::memory_order_seq_cst;
using std::atomic_bool;
using std::atomic_char;
using std::atomic_schar;
using std::atomic_uchar;
using std::atomic_short;
using std::atomic_ushort;
using std::atomic_int;
using std::atomic_uint;
using std::atomic_long;
using std::atomic_ulong;
using std::atomic_llong;
using std::atomic_ullong;
using std::atomic_char16_t;
using std::atomic_char32_t;
using std::atomic_wchar_t;
using std::atomic_int_least8_t;
using std::atomic_uint_least8_t;
using std::atomic_int_least16_t;
using std::atomic_uint_least16_t;
using std::atomic_int_least32_t;
using std::atomic_uint_least32_t;
using std::atomic_int_least64_t;
using std::atomic_uint_least64_t;
using std::atomic_int_fast8_t;
using std::atomic_uint_fast8_t;
using std::atomic_int_fast16_t;
using std::atomic_uint_fast16_t;
using std::atomic_int_fast32_t;
using std::atomic_uint_fast32_t;
using std::atomic_int_fast64_t;
using std::atomic_uint_fast64_t;
using std::atomic_intptr_t;
using std::atomic_uintptr_t;
using std::atomic_size_t;
using std::atomic_ptrdiff_t;
using std::atomic_intmax_t;
using std::atomic_uintmax_t;
using std::atomic_flag_test_and_set;
using std::atomic_flag_test_and_set_explicit;
using std::atomic_flag_clear;
using std::atomic_flag_clear_explicit;
using std::atomic_init;
using std::atomic_is_lock_free;
using std::atomic_store;
using std::atomic_store_explicit;
using std::atomic_load;
using std::atomic_load_explicit;
using std::atomic_exchange;
using std::atomic_exchange_explicit;
using std::atomic_compare_exchange_strong;
using std::atomic_compare_exchange_strong_explicit;
using std::atomic_compare_exchange_weak;
using std::atomic_compare_exchange_weak_explicit;
using std::atomic_fetch_add;
using std::atomic_fetch_add_explicit;
using std::atomic_fetch_sub;
using std::atomic_fetch_sub_explicit;
using std::atomic_fetch_or;
using std::atomic_fetch_or_explicit;
using std::atomic_fetch_xor;
using std::atomic_fetch_xor_explicit;
using std::atomic_fetch_and;
using std::atomic_fetch_and_explicit;
using std::atomic_thread_fence;
using std::atomic_signal_fence;
#elif defined(HAVE_STDATOMIC_H) && !defined(__CC_ARM) && \
!defined(__STDC_NO_ATOMICS__)
# include <stdint.h>
# include <stdatomic.h>
#elif defined(__GNUC__)
# include <metal/compiler/gcc/atomic.h>
#else
# include <metal/processor/arm/atomic.h>
#endif
#endif /* __METAL_ATOMIC__H__ */
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/metal/cache.h
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/*
* Copyright (c) 2016, Xilinx Inc. and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* @file cache.h
* @brief CACHE operation primitives for libmetal.
*/
#ifndef __METAL_CACHE__H__
#define __METAL_CACHE__H__
#include <metal/system/generic/cache.h>
#ifdef __cplusplus
extern "C" {
#endif
/** \defgroup cache CACHE Interfaces
* @{
*/
/**
* @brief flush specified data cache
*
* @param[in] addr start memory logical address
* @param[in] len length of memory
* If addr is NULL, and len is 0,
* It will flush the whole data cache.
*/
static inline void metal_cache_flush(void *addr, unsigned int len)
{
__metal_cache_flush(addr, len);
}
/**
* @brief invalidate specified data cache
*
* @param[in] addr start memory logical address
* @param[in] len length of memory
* If addr is NULL, and len is 0,
* It will invalidate the whole data cache.
*/
static inline void metal_cache_invalidate(void *addr, unsigned int len)
{
__metal_cache_invalidate(addr, len);
}
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* __METAL_CACHE__H__ */
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/metal/compiler.h
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/*
* Copyright (c) 2015-2022 Xilinx, Inc. and Contributors. All rights reserved.
* Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* @file compiler.h
* @brief Compiler specific primitives for libmetal.
*/
#ifndef __METAL_COMPILER__H__
#define __METAL_COMPILER__H__
#if defined(__GNUC__)
# include <metal/compiler/gcc/compiler.h>
#elif defined(__ICCARM__)
# include <metal/compiler/iar/compiler.h>
#elif defined(__CC_ARM)
# error "MDK-ARM ARMCC compiler requires the GNU extensions to work correctly"
#else
# error "Missing compiler support"
#endif
#endif /* __METAL_COMPILER__H__ */
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/metal/compiler/armcc/errno.h
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/*-
* Copyright (c) 2020 STMicroelectronics. All rights reserved.
*
* Copyright (c) 1982, 1986, 1989, 1993
* The Regents of the University of California. All rights reserved.
* (c) UNIX System Laboratories, Inc.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __METAL_ARMCC_ERRNO__H__
#define __METAL_ARMCC_ERRNO__H__
#include <errno.h>
#ifdef __cplusplus
extern "C" {
#endif
#define LIBMETAL_ERR_BASE 100
#define EPERM (LIBMETAL_ERR_BASE + 1) /* Operation not permitted */
#define ENOENT (LIBMETAL_ERR_BASE + 2) /* No such file or directory */
#define ESRCH (LIBMETAL_ERR_BASE + 3) /* No such process */
#define EINTR (LIBMETAL_ERR_BASE + 4) /* Interrupted system call */
#define EIO (LIBMETAL_ERR_BASE + 5) /* Input/output error */
#define ENXIO (LIBMETAL_ERR_BASE + 6) /* Device not configured */
#define E2BIG (LIBMETAL_ERR_BASE + 7) /* Argument list too long */
#define ENOEXEC (LIBMETAL_ERR_BASE + 8) /* Exec format error */
#define EBADF (LIBMETAL_ERR_BASE + 9) /* Bad file descriptor */
#define ECHILD (LIBMETAL_ERR_BASE + 10) /* No child processes */
#define EDEADLK (LIBMETAL_ERR_BASE + 11) /* Resource deadlock avoided */
#define EACCES (LIBMETAL_ERR_BASE + 13) /* Permission denied */
#define EFAULT (LIBMETAL_ERR_BASE + 14) /* Bad address */
#define ENOTBLK (LIBMETAL_ERR_BASE + 15) /* Block device required */
#define EBUSY (LIBMETAL_ERR_BASE + 16) /* Device busy */
#define EEXIST (LIBMETAL_ERR_BASE + 17) /* File exists */
#define EXDEV (LIBMETAL_ERR_BASE + 18) /* Cross-device link */
#define ENODEV (LIBMETAL_ERR_BASE + 19) /* Operation not supported by device */
#define ENOTDIR (LIBMETAL_ERR_BASE + 20) /* Not a directory */
#define EISDIR (LIBMETAL_ERR_BASE + 21) /* Is a directory */
#define ENFILE (LIBMETAL_ERR_BASE + 23) /* Too many open files in system */
#define EMFILE (LIBMETAL_ERR_BASE + 24) /* Too many open files */
#define ENOTTY (LIBMETAL_ERR_BASE + 25) /* Inappropriate ioctl for device */
#define ETXTBSY (LIBMETAL_ERR_BASE + 26) /* Text file busy */
#define EFBIG (LIBMETAL_ERR_BASE + 27) /* File too large */
#define ENOSPC (LIBMETAL_ERR_BASE + 28) /* No space left on device */
#define ESPIPE (LIBMETAL_ERR_BASE + 29) /* Illegal seek */
#define EROFS (LIBMETAL_ERR_BASE + 30) /* Read-only filesystem */
#define EMLINK (LIBMETAL_ERR_BASE + 31) /* Too many links */
#define EPIPE (LIBMETAL_ERR_BASE + 32) /* Broken pipe */
#define EAGAIN (LIBMETAL_ERR_BASE + 35) /* Resource temporarily unavailable */
#ifdef __cplusplus
}
#endif
#endif /* __METAL_ARMCC_ERRNO__H__ */
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/metal/compiler/gcc/atomic.h
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/*
* Copyright (c) 2015, Xilinx Inc. and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* @file gcc/atomic.h
* @brief GCC specific atomic primitives for libmetal.
*/
#ifndef __METAL_GCC_ATOMIC__H__
#define __METAL_GCC_ATOMIC__H__
#ifdef __cplusplus
extern "C" {
#endif
typedef int atomic_flag;
typedef char atomic_char;
typedef unsigned char atomic_uchar;
typedef short atomic_short;
typedef unsigned short atomic_ushort;
typedef int atomic_int;
typedef unsigned int atomic_uint;
typedef atomic_uint atomic_uintptr_t;
typedef long atomic_long;
typedef unsigned long atomic_ulong;
typedef long long atomic_llong;
typedef unsigned long long atomic_ullong;
#define ATOMIC_FLAG_INIT 0
#define ATOMIC_VAR_INIT(VAL) (VAL)
typedef enum {
memory_order_relaxed,
memory_order_consume,
memory_order_acquire,
memory_order_release,
memory_order_acq_rel,
memory_order_seq_cst,
} memory_order;
#define atomic_flag_test_and_set(FLAG) \
__sync_lock_test_and_set((FLAG), 1)
#define atomic_flag_test_and_set_explicit(FLAG, MO) \
atomic_flag_test_and_set(FLAG)
#define atomic_flag_clear(FLAG) \
__sync_lock_release((FLAG))
#define atomic_flag_clear_explicit(FLAG, MO) \
atomic_flag_clear(FLAG)
#define atomic_init(OBJ, VAL) \
do { *(OBJ) = (VAL); } while (0)
#define atomic_is_lock_free(OBJ) \
(sizeof(*(OBJ)) <= sizeof(long))
#define atomic_store(OBJ, VAL) \
do { *(OBJ) = (VAL); __sync_synchronize(); } while (0)
#define atomic_store_explicit(OBJ, VAL, MO) \
atomic_store((OBJ), (VAL))
#define atomic_load(OBJ) \
({ __sync_synchronize(); *(OBJ); })
#define atomic_load_explicit(OBJ, MO) \
atomic_load(OBJ)
#define atomic_exchange(OBJ, DES) \
({ \
__typeof__(OBJ) obj = (OBJ); \
__typeof__(*obj) des = (DES); \
__typeof__(*obj) expval; \
__typeof__(*obj) oldval = atomic_load(obj); \
do { \
expval = oldval; \
oldval = __sync_val_compare_and_swap( \
obj, expval, des); \
} while (oldval != expval); \
oldval; \
})
#define atomic_exchange_explicit(OBJ, DES, MO) \
atomic_exchange((OBJ), (DES))
#define atomic_compare_exchange_strong(OBJ, EXP, DES) \
({ \
__typeof__(OBJ) obj = (OBJ); \
__typeof__(EXP) exp = (EXP); \
__typeof__(*obj) expval = *exp; \
__typeof__(*obj) oldval = __sync_val_compare_and_swap( \
obj, expval, (DES)); \
*exp = oldval; \
oldval == expval; \
})
#define atomic_compare_exchange_strong_explicit(OBJ, EXP, DES, MO) \
atomic_compare_exchange_strong((OBJ), (EXP), (DES))
#define atomic_compare_exchange_weak(OBJ, EXP, DES) \
atomic_compare_exchange_strong((OBJ), (EXP), (DES))
#define atomic_compare_exchange_weak_explicit(OBJ, EXP, DES, MO) \
atomic_compare_exchange_weak((OBJ), (EXP), (DES))
#define atomic_fetch_add(OBJ, VAL) \
__sync_fetch_and_add((OBJ), (VAL))
#define atomic_fetch_add_explicit(OBJ, VAL, MO) \
atomic_fetch_add((OBJ), (VAL))
#define atomic_fetch_sub(OBJ, VAL) \
__sync_fetch_and_sub((OBJ), (VAL))
#define atomic_fetch_sub_explicit(OBJ, VAL, MO) \
atomic_fetch_sub((OBJ), (VAL))
#define atomic_fetch_or(OBJ, VAL) \
__sync_fetch_and_or((OBJ), (VAL))
#define atomic_fetch_or_explicit(OBJ, VAL, MO) \
atomic_fetch_or((OBJ), (VAL))
#define atomic_fetch_xor(OBJ, VAL) \
__sync_fetch_and_xor((OBJ), (VAL))
#define atomic_fetch_xor_explicit(OBJ, VAL, MO) \
atomic_fetch_xor((OBJ), (VAL))
#define atomic_fetch_and(OBJ, VAL) \
__sync_fetch_and_and((OBJ), (VAL))
#define atomic_fetch_and_explicit(OBJ, VAL, MO) \
atomic_fetch_and((OBJ), (VAL))
#define atomic_thread_fence(MO) \
__sync_synchronize()
#define atomic_signal_fence(MO) \
__sync_synchronize()
#ifdef __cplusplus
}
#endif
#endif /* __METAL_GCC_ATOMIC__H__ */
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/metal/compiler/gcc/compiler.h
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/*
* Copyright (c) 2015, Xilinx Inc. and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* @file gcc/compiler.h
* @brief GCC specific primitives for libmetal.
*/
#ifndef __METAL_GCC_COMPILER__H__
#define __METAL_GCC_COMPILER__H__
#ifdef __cplusplus
extern "C" {
#endif
#define restrict __restrict__
#define metal_align(n) __attribute__((aligned(n)))
#define metal_weak __attribute__((weak))
#if defined(__STRICT_ANSI__)
#define metal_asm __asm__
#else
/*
* Even though __asm__ is always available in mainline GCC, we use asm in
* the non-strict modes for compatibility with other compilers that define
* __GNUC__
*/
#define metal_asm asm
#endif
#define METAL_PACKED_BEGIN
#define METAL_PACKED_END __attribute__((__packed__))
#ifndef __deprecated
#define __deprecated __attribute__((deprecated))
#endif
#ifdef __cplusplus
}
#endif
#endif /* __METAL_GCC_COMPILER__H__ */
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/metal/compiler/iar/compiler.h
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/*
* Copyright (c) 2018, ST Microelectronics. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* @file iar/compiler.h
* @brief IAR specific primitives for libmetal.
*/
#ifndef __METAL_IAR_COMPILER__H__
#define __METAL_IAR_COMPILER__H__
#ifdef __cplusplus
extern "C" {
#endif
#define restrict __restrict__
#define metal_align(n) __attribute__((aligned(n)))
#define metal_weak __attribute__((weak))
#define metal_asm asm
#define METAL_PACKED_BEGIN __packed
#define METAL_PACKED_END
#ifndef __deprecated
#define __deprecated __attribute__((deprecated))
#endif
#ifdef __cplusplus
}
#endif
#endif /* __METAL_IAR_COMPILER__H__ */
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/metal/compiler/iar/errno.h
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/*-
* Copyright (c) 2020 STMicroelectronics. All rights reserved.
*
* Copyright (c) 1982, 1986, 1989, 1993
* The Regents of the University of California. All rights reserved.
* (c) UNIX System Laboratories, Inc.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __METAL_IAR_ERRNO__H__
#define __METAL_IAR_ERRNO__H__
#include <errno.h>
#ifdef __cplusplus
extern "C" {
#endif
#define LIBMETAL_ERR_BASE 100
#define EPERM (LIBMETAL_ERR_BASE + 1) /* Operation not permitted */
#define ENOENT (LIBMETAL_ERR_BASE + 2) /* No such file or directory */
#define ESRCH (LIBMETAL_ERR_BASE + 3) /* No such process */
#define EINTR (LIBMETAL_ERR_BASE + 4) /* Interrupted system call */
#define EIO (LIBMETAL_ERR_BASE + 5) /* Input/output error */
#define ENXIO (LIBMETAL_ERR_BASE + 6) /* Device not configured */
#define E2BIG (LIBMETAL_ERR_BASE + 7) /* Argument list too long */
#define ENOEXEC (LIBMETAL_ERR_BASE + 8) /* Exec format error */
#define EBADF (LIBMETAL_ERR_BASE + 9) /* Bad file descriptor */
#define ECHILD (LIBMETAL_ERR_BASE + 10) /* No child processes */
#define EDEADLK (LIBMETAL_ERR_BASE + 11) /* Resource deadlock avoided */
#define ENOMEM (LIBMETAL_ERR_BASE + 12) /* Cannot allocate memory */
#define EACCES (LIBMETAL_ERR_BASE + 13) /* Permission denied */
#define EFAULT (LIBMETAL_ERR_BASE + 14) /* Bad address */
#define ENOTBLK (LIBMETAL_ERR_BASE + 15) /* Block device required */
#define EBUSY (LIBMETAL_ERR_BASE + 16) /* Device busy */
#define EEXIST (LIBMETAL_ERR_BASE + 17) /* File exists */
#define EXDEV (LIBMETAL_ERR_BASE + 18) /* Cross-device link */
#define ENODEV (LIBMETAL_ERR_BASE + 19) /* Operation not supported by device */
#define ENOTDIR (LIBMETAL_ERR_BASE + 20) /* Not a directory */
#define EISDIR (LIBMETAL_ERR_BASE + 21) /* Is a directory */
#define EINVAL (LIBMETAL_ERR_BASE + 22) /* Invalid argument */
#define ENFILE (LIBMETAL_ERR_BASE + 23) /* Too many open files in system */
#define EMFILE (LIBMETAL_ERR_BASE + 24) /* Too many open files */
#define ENOTTY (LIBMETAL_ERR_BASE + 25) /* Inappropriate ioctl for device */
#define ETXTBSY (LIBMETAL_ERR_BASE + 26) /* Text file busy */
#define EFBIG (LIBMETAL_ERR_BASE + 27) /* File too large */
#define ENOSPC (LIBMETAL_ERR_BASE + 28) /* No space left on device */
#define ESPIPE (LIBMETAL_ERR_BASE + 29) /* Illegal seek */
#define EROFS (LIBMETAL_ERR_BASE + 30) /* Read-only filesystem */
#define EMLINK (LIBMETAL_ERR_BASE + 31) /* Too many links */
#define EPIPE (LIBMETAL_ERR_BASE + 32) /* Broken pipe */
#define EAGAIN (LIBMETAL_ERR_BASE + 35) /* Resource temporarily unavailable */
#ifdef __cplusplus
}
#endif
#endif /* __METAL_IAR_ERRNO__H__ */
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/metal/condition.h
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/*
* Copyright (c) 2016-2022 Xilinx, Inc. and Contributors. All rights reserved.
* Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* @file condition.h
* @brief Condition variable for libmetal.
*/
#ifndef __METAL_CONDITION__H__
#define __METAL_CONDITION__H__
#include <metal/mutex.h>
#include <metal/utilities.h>
#ifdef __cplusplus
extern "C" {
#endif
/** \defgroup condition Condition Variable Interfaces
* @{
*/
/** Opaque libmetal condition variable data structure. */
struct metal_condition;
/**
* @brief Initialize a libmetal condition variable.
* @param[in] cv condition variable to initialize.
*/
static inline void metal_condition_init(struct metal_condition *cv);
/**
* @brief Notify one waiter.
* Before calling this function, the caller
* should have acquired the mutex.
* @param[in] cv condition variable
* @return zero on no errors, non-zero on errors
* @see metal_condition_wait, metal_condition_broadcast
*/
static inline int metal_condition_signal(struct metal_condition *cv);
/**
* @brief Notify all waiters.
* Before calling this function, the caller
* should have acquired the mutex.
* @param[in] cv condition variable
* @return zero on no errors, non-zero on errors
* @see metal_condition_wait, metal_condition_signal
*/
static inline int metal_condition_broadcast(struct metal_condition *cv);
/**
* @brief Block until the condition variable is notified.
* Before calling this function, the caller should
* have acquired the mutex.
* @param[in] cv condition variable
* @param[in] m mutex
* @return 0 on success, non-zero on failure.
* @see metal_condition_signal
*/
int metal_condition_wait(struct metal_condition *cv, metal_mutex_t *m);
/** @} */
#ifdef __cplusplus
}
#endif
#include <metal/system/generic/condition.h>
#endif /* __METAL_CONDITION__H__ */
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/metal/config.h
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/*
* Copyright (c) 2015, Xilinx Inc. and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* @file config.h
* @brief Generated configuration settings for libmetal.
*/
#ifndef __METAL_CONFIG__H__
#define __METAL_CONFIG__H__
#ifdef __cplusplus
extern "C" {
#endif
/** Library major version number. */
#define METAL_VER_MAJOR 1
/** Library minor version number. */
#define METAL_VER_MINOR 5
/** Library patch level. */
#define METAL_VER_PATCH 0
/** Library version string. */
#define METAL_VER "1.5.0"
/** System type (linux, generic, ...). */
#define METAL_SYSTEM "generic"
#define METAL_SYSTEM_GENERIC
/** Processor type (arm, x86_64, ...). */
#define METAL_PROCESSOR "arm"
#define METAL_PROCESSOR_ARM
/** Machine type (zynq, zynqmp, ...). */
#define METAL_MACHINE "zynqmp_a53"
#define METAL_MACHINE_ZYNQMP_A53
#define HAVE_STDATOMIC_H
/* #undef HAVE_FUTEX_H */
#ifdef __cplusplus
}
#endif
#endif /* __METAL_CONFIG__H__ */
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/metal/cpu.h
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/*
* Copyright (c) 2015, Xilinx Inc. and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* @file cpu.h
* @brief CPU primitives for libmetal.
*/
#ifndef __METAL_CPU__H__
#define __METAL_CPU__H__
# include <metal/processor/arm/cpu.h>
#endif /* __METAL_CPU__H__ */
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/metal/device.h
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/*
* Copyright (c) 2015, Xilinx Inc. and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* @file device.h
* @brief Bus abstraction for libmetal.
*/
#ifndef __METAL_BUS__H__
#define __METAL_BUS__H__
#include <stdint.h>
#include <metal/io.h>
#include <metal/list.h>
#include <metal/dma.h>
#include <metal/sys.h>
#ifdef __cplusplus
extern "C" {
#endif
/** \defgroup device Bus Abstraction
* @{
*/
#ifndef METAL_MAX_DEVICE_REGIONS
#define METAL_MAX_DEVICE_REGIONS 32
#endif
struct metal_bus;
struct metal_device;
/** Bus operations. */
struct metal_bus_ops {
void (*bus_close)(struct metal_bus *bus);
int (*dev_open)(struct metal_bus *bus,
const char *dev_name,
struct metal_device **device);
void (*dev_close)(struct metal_bus *bus,
struct metal_device *device);
void (*dev_irq_ack)(struct metal_bus *bus,
struct metal_device *device,
int irq);
int (*dev_dma_map)(struct metal_bus *bus,
struct metal_device *device,
uint32_t dir,
struct metal_sg *sg_in,
int nents_in,
struct metal_sg *sg_out);
void (*dev_dma_unmap)(struct metal_bus *bus,
struct metal_device *device,
uint32_t dir,
struct metal_sg *sg,
int nents);
};
/** Libmetal bus structure. */
struct metal_bus {
const char *name;
struct metal_bus_ops ops;
struct metal_list devices;
struct metal_list node;
};
/** Libmetal generic bus. */
extern struct metal_bus metal_generic_bus;
/** Libmetal device structure. */
struct metal_device {
const char *name; /**< Device name */
struct metal_bus *bus; /**< Bus that contains device */
unsigned int num_regions; /**< Number of I/O regions in
device */
struct metal_io_region regions[METAL_MAX_DEVICE_REGIONS]; /**< Array of
I/O regions in device*/
struct metal_list node; /**< Node on bus' list of devices */
int irq_num; /**< Number of IRQs per device */
void *irq_info; /**< IRQ ID */
};
/**
* @brief Register a libmetal bus.
* @param[in] bus Pre-initialized bus structure.
* @return 0 on success, or -errno on failure.
*/
extern int metal_bus_register(struct metal_bus *bus);
/**
* @brief Unregister a libmetal bus.
* @param[in] bus Pre-registered bus structure.
* @return 0 on success, or -errno on failure.
*/
extern int metal_bus_unregister(struct metal_bus *bus);
/**
* @brief Find a libmetal bus by name.
* @param[in] name Bus name.
* @param[out] bus Returned bus handle.
* @return 0 on success, or -errno on failure.
*/
extern int metal_bus_find(const char *name, struct metal_bus **bus);
/**
* @brief Statically register a generic libmetal device.
*
* In non-Linux systems, devices are always required to be statically
* registered at application initialization.
* In Linux system, devices can be dynamically opened via sysfs or libfdt based
* enumeration at runtime.
* This interface is used for static registration of devices. Subsequent calls
* to metal_device_open() look up in this list of pre-registered devices on the
* "generic" bus.
* "generic" bus is used on non-Linux system to group the memory mapped devices.
*
* @param[in] device Generic device.
* @return 0 on success, or -errno on failure.
*/
extern int metal_register_generic_device(struct metal_device *device);
/**
* @brief Open a libmetal device by name.
* @param[in] bus_name Bus name.
* @param[in] dev_name Device name.
* @param[out] device Returned device handle.
* @return 0 on success, or -errno on failure.
*/
extern int metal_device_open(const char *bus_name, const char *dev_name,
struct metal_device **device);
/**
* @brief Close a libmetal device.
* @param[in] device Device handle.
*/
extern void metal_device_close(struct metal_device *device);
/**
* @brief Get an I/O region accessor for a device region.
*
* @param[in] device Device handle.
* @param[in] index Region index.
* @return I/O accessor handle, or NULL on failure.
*/
static inline struct metal_io_region *
metal_device_io_region(struct metal_device *device, unsigned int index)
{
return (index < device->num_regions
? &device->regions[index]
: NULL);
}
/** @} */
#ifdef METAL_INTERNAL
extern int metal_generic_dev_sys_open(struct metal_device *dev);
extern int metal_generic_dev_open(struct metal_bus *bus, const char *dev_name,
struct metal_device **device);
extern int metal_generic_dev_dma_map(struct metal_bus *bus,
struct metal_device *device,
uint32_t dir,
struct metal_sg *sg_in,
int nents_in,
struct metal_sg *sg_out);
extern void metal_generic_dev_dma_unmap(struct metal_bus *bus,
struct metal_device *device,
uint32_t dir,
struct metal_sg *sg,
int nents);
#endif /* METAL_INTERNAL */
#ifdef __cplusplus
}
#endif
#endif /* __METAL_BUS__H__ */
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/metal/dma.h
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/*
* Copyright (c) 2016-2022 Xilinx, Inc. and Contributors. All rights reserved.
* Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* @file dma.h
* @brief DMA primitives for libmetal.
*/
#ifndef __METAL_DMA__H__
#define __METAL_DMA__H__
#include <stdint.h>
#include <metal/sys.h>
#ifdef __cplusplus
extern "C" {
#endif
/** \defgroup dma DMA Interfaces
* @{
*/
#define METAL_DMA_DEV_R 1 /**< DMA direction, device read */
#define METAL_DMA_DEV_W 2 /**< DMA direction, device write */
#define METAL_DMA_DEV_WR 3 /**< DMA direction, device read/write */
/**
* @brief scatter/gather list element structure
*/
struct metal_sg {
void *virt; /**< CPU virtual address */
struct metal_io_region *io; /**< IO region */
int len; /**< length */
};
struct metal_device;
/**
* @brief Map memory for DMA transaction.
* After the memory is DMA mapped, the memory should be
* accessed by the DMA device but not the CPU.
*
* @param[in] dev DMA device
* @param[in] dir DMA direction
* @param[in] sg_in sg list of memory to map
* @param[in] nents_in number of sg list entries of memory to map
* @param[out] sg_out sg list of mapped memory
* @return number of mapped sg entries, -error on failure.
*/
int metal_dma_map(struct metal_device *dev,
uint32_t dir,
struct metal_sg *sg_in,
int nents_in,
struct metal_sg *sg_out);
/**
* @brief Unmap DMA memory
* After the memory is DMA unmapped, the memory should
* be accessed by the CPU but not the DMA device.
*
* @param[in] dev DMA device
* @param[in] dir DMA direction
* @param[in] sg sg list of mapped DMA memory
* @param[in] nents number of sg list entries of DMA memory
*/
void metal_dma_unmap(struct metal_device *dev,
uint32_t dir,
struct metal_sg *sg,
int nents);
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* __METAL_DMA__H__ */
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/metal/errno.h
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/*
* Copyright (c) 2020 STMicroelectronnics. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* @file metal/errno.h
* @brief error specific primitives for libmetal.
*/
#ifndef __METAL_ERRNO__H__
#define __METAL_ERRNO__H__
#if defined(__ICCARM__)
# include <metal/compiler/iar/errno.h>
#elif defined(__CC_ARM)
# include <metal/compiler/armcc/errno.h>
#else
# include <errno.h>
#endif
#endif /* __METAL_ERRNO__H__ */
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/metal/io.h
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/*
* Copyright (c) 2015-2022 Xilinx, Inc. and Contributors. All rights reserved.
* Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* @file io.h
* @brief I/O access primitives for libmetal.
*/
#ifndef __METAL_IO__H__
#define __METAL_IO__H__
#include <limits.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <metal/assert.h>
#include <metal/compiler.h>
#include <metal/atomic.h>
#include <metal/sys.h>
#include <metal/cpu.h>
#ifdef __cplusplus
extern "C" {
#endif
/** \defgroup io IO Interfaces
* @{
*/
#ifdef __MICROBLAZE__
#define NO_ATOMIC_64_SUPPORT
#endif
struct metal_io_region;
/** Generic I/O operations. */
struct metal_io_ops {
uint64_t (*read)(struct metal_io_region *io,
unsigned long offset,
memory_order order,
int width);
void (*write)(struct metal_io_region *io,
unsigned long offset,
uint64_t value,
memory_order order,
int width);
int (*block_read)(struct metal_io_region *io,
unsigned long offset,
void *restrict dst,
memory_order order,
int len);
int (*block_write)(struct metal_io_region *io,
unsigned long offset,
const void *restrict src,
memory_order order,
int len);
void (*block_set)(struct metal_io_region *io,
unsigned long offset,
unsigned char value,
memory_order order,
int len);
void (*close)(struct metal_io_region *io);
metal_phys_addr_t (*offset_to_phys)(struct metal_io_region *io,
unsigned long offset);
unsigned long (*phys_to_offset)(struct metal_io_region *io,
metal_phys_addr_t phys);
};
/** Libmetal I/O region structure. */
struct metal_io_region {
void *virt; /**< base virtual address */
const metal_phys_addr_t *physmap; /**< table of base physical address
of each of the pages in the I/O
region */
size_t size; /**< size of the I/O region */
unsigned long page_shift; /**< page shift of I/O region */
metal_phys_addr_t page_mask; /**< page mask of I/O region */
unsigned int mem_flags; /**< memory attribute of the
I/O region */
struct metal_io_ops ops; /**< I/O region operations */
};
/**
* @brief Open a libmetal I/O region.
*
* @param[in, out] io I/O region handle.
* @param[in] virt Virtual address of region.
* @param[in] physmap Array of physical addresses per page.
* @param[in] size Size of region.
* @param[in] page_shift Log2 of page size (-1 for single page).
* @param[in] mem_flags Memory flags
* @param[in] ops ops
*/
void
metal_io_init(struct metal_io_region *io, void *virt,
const metal_phys_addr_t *physmap, size_t size,
unsigned int page_shift, unsigned int mem_flags,
const struct metal_io_ops *ops);
/**
* @brief Close a libmetal shared memory segment.
* @param[in] io I/O region handle.
*/
static inline void metal_io_finish(struct metal_io_region *io)
{
if (io->ops.close)
(*io->ops.close)(io);
memset(io, 0, sizeof(*io));
}
/**
* @brief Get size of I/O region.
*
* @param[in] io I/O region handle.
* @return Size of I/O region.
*/
static inline size_t metal_io_region_size(struct metal_io_region *io)
{
return io->size;
}
/**
* @brief Get virtual address for a given offset into the I/O region.
* @param[in] io I/O region handle.
* @param[in] offset Offset into shared memory segment.
* @return NULL if offset is out of range, or pointer to offset.
*/
static inline void *
metal_io_virt(struct metal_io_region *io, unsigned long offset)
{
return (io->virt != METAL_BAD_VA && offset < io->size
? (void *)((uintptr_t)io->virt + offset)
: NULL);
}
/**
* @brief Convert a virtual address to offset within I/O region.
* @param[in] io I/O region handle.
* @param[in] virt Virtual address within segment.
* @return METAL_BAD_OFFSET if out of range, or offset.
*/
static inline unsigned long
metal_io_virt_to_offset(struct metal_io_region *io, void *virt)
{
size_t offset = (uintptr_t)virt - (uintptr_t)io->virt;
return (offset < io->size ? offset : METAL_BAD_OFFSET);
}
/**
* @brief Get physical address for a given offset into the I/O region.
* @param[in] io I/O region handle.
* @param[in] offset Offset into shared memory segment.
* @return METAL_BAD_PHYS if offset is out of range, or physical address
* of offset.
*/
static inline metal_phys_addr_t
metal_io_phys(struct metal_io_region *io, unsigned long offset)
{
if (!io->ops.offset_to_phys) {
unsigned long page = (io->page_shift >=
sizeof(offset) * CHAR_BIT ?
0 : offset >> io->page_shift);
return (io->physmap && offset < io->size
? io->physmap[page] + (offset & io->page_mask)
: METAL_BAD_PHYS);
}
return io->ops.offset_to_phys(io, offset);
}
/**
* @brief Convert a physical address to offset within I/O region.
* @param[in] io I/O region handle.
* @param[in] phys Physical address within segment.
* @return METAL_BAD_OFFSET if out of range, or offset.
*/
static inline unsigned long
metal_io_phys_to_offset(struct metal_io_region *io, metal_phys_addr_t phys)
{
if (!io->ops.phys_to_offset) {
unsigned long offset =
(io->page_mask == (metal_phys_addr_t)(-1) ?
phys - io->physmap[0] : phys & io->page_mask);
do {
if (metal_io_phys(io, offset) == phys)
return offset;
offset += io->page_mask + 1;
} while (offset < io->size);
return METAL_BAD_OFFSET;
}
return (*io->ops.phys_to_offset)(io, phys);
}
/**
* @brief Convert a physical address to virtual address.
* @param[in] io Shared memory segment handle.
* @param[in] phys Physical address within segment.
* @return NULL if out of range, or corresponding virtual address.
*/
static inline void *
metal_io_phys_to_virt(struct metal_io_region *io, metal_phys_addr_t phys)
{
return metal_io_virt(io, metal_io_phys_to_offset(io, phys));
}
/**
* @brief Convert a virtual address to physical address.
* @param[in] io Shared memory segment handle.
* @param[in] virt Virtual address within segment.
* @return METAL_BAD_PHYS if out of range, or corresponding
* physical address.
*/
static inline metal_phys_addr_t
metal_io_virt_to_phys(struct metal_io_region *io, void *virt)
{
return metal_io_phys(io, metal_io_virt_to_offset(io, virt));
}
/**
* @brief Read a value from an I/O region.
* @param[in] io I/O region handle.
* @param[in] offset Offset into I/O region.
* @param[in] order Memory ordering.
* @param[in] width Width in bytes of datatype to read. This must be 1, 2,
* 4, or 8, and a compile time constant for this function
* to inline cleanly.
* @return Value.
*/
static inline uint64_t
metal_io_read(struct metal_io_region *io, unsigned long offset,
memory_order order, int width)
{
void *ptr = metal_io_virt(io, offset);
if (io->ops.read)
return (*io->ops.read)(io, offset, order, width);
else if (ptr && sizeof(atomic_uchar) == width)
return atomic_load_explicit((atomic_uchar *)ptr, order);
else if (ptr && sizeof(atomic_ushort) == width)
return atomic_load_explicit((atomic_ushort *)ptr, order);
else if (ptr && sizeof(atomic_uint) == width)
return atomic_load_explicit((atomic_uint *)ptr, order);
else if (ptr && sizeof(atomic_ulong) == width)
return atomic_load_explicit((atomic_ulong *)ptr, order);
#ifndef NO_ATOMIC_64_SUPPORT
else if (ptr && sizeof(atomic_ullong) == width)
return atomic_load_explicit((atomic_ullong *)ptr, order);
#endif
metal_assert(0);
return 0; /* quiet compiler */
}
/**
* @brief Write a value into an I/O region.
* @param[in] io I/O region handle.
* @param[in] offset Offset into I/O region.
* @param[in] value Value to write.
* @param[in] order Memory ordering.
* @param[in] width Width in bytes of datatype to read. This must be 1, 2,
* 4, or 8, and a compile time constant for this function
* to inline cleanly.
*/
static inline void
metal_io_write(struct metal_io_region *io, unsigned long offset,
uint64_t value, memory_order order, int width)
{
void *ptr = metal_io_virt(io, offset);
if (io->ops.write)
(*io->ops.write)(io, offset, value, order, width);
else if (ptr && sizeof(atomic_uchar) == width)
atomic_store_explicit((atomic_uchar *)ptr, (unsigned char)value,
order);
else if (ptr && sizeof(atomic_ushort) == width)
atomic_store_explicit((atomic_ushort *)ptr,
(unsigned short)value, order);
else if (ptr && sizeof(atomic_uint) == width)
atomic_store_explicit((atomic_uint *)ptr, (unsigned int)value,
order);
else if (ptr && sizeof(atomic_ulong) == width)
atomic_store_explicit((atomic_ulong *)ptr, (unsigned long)value,
order);
#ifndef NO_ATOMIC_64_SUPPORT
else if (ptr && sizeof(atomic_ullong) == width)
atomic_store_explicit((atomic_ullong *)ptr,
(unsigned long long)value, order);
#endif
else
metal_assert(0);
}
#define metal_io_read8_explicit(_io, _ofs, _order) \
metal_io_read((_io), (_ofs), (_order), 1)
#define metal_io_read8(_io, _ofs) \
metal_io_read((_io), (_ofs), memory_order_seq_cst, 1)
#define metal_io_write8_explicit(_io, _ofs, _val, _order) \
metal_io_write((_io), (_ofs), (_val), (_order), 1)
#define metal_io_write8(_io, _ofs, _val) \
metal_io_write((_io), (_ofs), (_val), memory_order_seq_cst, 1)
#define metal_io_read16_explicit(_io, _ofs, _order) \
metal_io_read((_io), (_ofs), (_order), 2)
#define metal_io_read16(_io, _ofs) \
metal_io_read((_io), (_ofs), memory_order_seq_cst, 2)
#define metal_io_write16_explicit(_io, _ofs, _val, _order) \
metal_io_write((_io), (_ofs), (_val), (_order), 2)
#define metal_io_write16(_io, _ofs, _val) \
metal_io_write((_io), (_ofs), (_val), memory_order_seq_cst, 2)
#define metal_io_read32_explicit(_io, _ofs, _order) \
metal_io_read((_io), (_ofs), (_order), 4)
#define metal_io_read32(_io, _ofs) \
metal_io_read((_io), (_ofs), memory_order_seq_cst, 4)
#define metal_io_write32_explicit(_io, _ofs, _val, _order) \
metal_io_write((_io), (_ofs), (_val), (_order), 4)
#define metal_io_write32(_io, _ofs, _val) \
metal_io_write((_io), (_ofs), (_val), memory_order_seq_cst, 4)
#define metal_io_read64_explicit(_io, _ofs, _order) \
metal_io_read((_io), (_ofs), (_order), 8)
#define metal_io_read64(_io, _ofs) \
metal_io_read((_io), (_ofs), memory_order_seq_cst, 8)
#define metal_io_write64_explicit(_io, _ofs, _val, _order) \
metal_io_write((_io), (_ofs), (_val), (_order), 8)
#define metal_io_write64(_io, _ofs, _val) \
metal_io_write((_io), (_ofs), (_val), memory_order_seq_cst, 8)
/**
* @brief Read a block from an I/O region.
* @param[in] io I/O region handle.
* @param[in] offset Offset into I/O region.
* @param[in] dst destination to store the read data.
* @param[in] len length in bytes to read.
* @return On success, number of bytes read. On failure, negative value
*/
int metal_io_block_read(struct metal_io_region *io, unsigned long offset,
void *restrict dst, int len);
/**
* @brief Write a block into an I/O region.
* @param[in] io I/O region handle.
* @param[in] offset Offset into I/O region.
* @param[in] src source to write.
* @param[in] len length in bytes to write.
* @return On success, number of bytes written. On failure, negative value
*/
int metal_io_block_write(struct metal_io_region *io, unsigned long offset,
const void *restrict src, int len);
/**
* @brief fill a block of an I/O region.
* @param[in] io I/O region handle.
* @param[in] offset Offset into I/O region.
* @param[in] value value to fill into the block
* @param[in] len length in bytes to fill.
* @return On success, number of bytes filled. On failure, negative value
*/
int metal_io_block_set(struct metal_io_region *io, unsigned long offset,
unsigned char value, int len);
/** @} */
#ifdef __cplusplus
}
#endif
#include <metal/system/generic/io.h>
#endif /* __METAL_IO__H__ */
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/metal/irq.h
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/*
* Copyright (c) 2016-2022 Xilinx, Inc. and Contributors. All rights reserved.
* Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* @file irq.h
* @brief Interrupt handling primitives for libmetal.
*/
#ifndef __METAL_IRQ__H__
#define __METAL_IRQ__H__
#include <metal/list.h>
#include <stdlib.h>
#ifdef __cplusplus
extern "C" {
#endif
/** \defgroup irq Interrupt Handling Interfaces
* @{
*/
/** IRQ handled status */
#define METAL_IRQ_NOT_HANDLED 0
#define METAL_IRQ_HANDLED 1
/**
* @brief type of interrupt handler
* @param[in] irq interrupt id
* @param[in] arg argument to pass to the handler
* @return irq handled status
*/
typedef int (*metal_irq_handler) (int irq, void *arg);
/**
* @brief Register interrupt handler for interrupt.
* Only allow single interrupt handler for a interrupt.
*
* If irq_handler is NULL, it will unregister interrupt
* handler from interrupt
*
* @param[in] irq interrupt id
* @param[in] irq_handler interrupt handler
* @param[in] arg arg is the argument pointing to the data which
* will be passed to the interrupt handler.
* @return 0 for success, non-zero on failure
*/
int metal_irq_register(int irq,
metal_irq_handler irq_handler,
void *arg);
/**
* @brief Unregister interrupt handler for interrupt.
*
* @param[in] irq interrupt id
*/
static inline
void metal_irq_unregister(int irq)
{
metal_irq_register(irq, 0, NULL);
}
/**
* @brief disable interrupts
* @return interrupts state
*/
unsigned int metal_irq_save_disable(void);
/**
* @brief restore interrupts to their previous state
* @param[in] flags previous interrupts state
*/
void metal_irq_restore_enable(unsigned int flags);
/**
* @brief metal_irq_enable
*
* Enables the given interrupt
*
* @param vector - interrupt vector number
*/
void metal_irq_enable(unsigned int vector);
/**
* @brief metal_irq_disable
*
* Disables the given interrupt
*
* @param vector - interrupt vector number
*/
void metal_irq_disable(unsigned int vector);
#include <metal/system/generic/irq.h>
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* __METAL_IRQ__H__ */
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/metal/irq_controller.h
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/*
* Copyright (c) 2016-2022 Xilinx, Inc. and Contributors. All rights reserved.
* Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* @file irq.h
* @brief Interrupt handling primitives for libmetal.
*/
#ifndef __METAL_IRQ_CONTROLLER__H__
#define __METAL_IRQ_CONTROLLER__H__
#ifdef __cplusplus
extern "C" {
#endif
/** \defgroup irq Interrupt Handling Interfaces
* @{
*/
#include <metal/irq.h>
#include <metal/list.h>
#include <stdlib.h>
/** IRQ ANY ID */
#define METAL_IRQ_ANY (-1)
/** IRQ state macro which will be passed to metal irq set state function
* to indicate which state the caller want the IRQ to change to.
*/
#define METAL_IRQ_DISABLE 0U
#define METAL_IRQ_ENABLE 1U
struct metal_irq_controller;
/**
* @brief type of interrupt controller to set irq enable
* @param[in] irq_cntr pointer to interrupt controller
* @param[in] irq interrupt id
* @param[in] enable IRQ state
*/
typedef void (*metal_irq_set_enable) (struct metal_irq_controller *irq_cntr,
int irq, unsigned int enable);
/**
* @brief type of controller specific registering interrupt function
* @param[in] irq_cntr pointer to interrupt controller
* @param[in] irq interrupt id
* @param[in] hd interrupt handler
* @param[in] arg argument which will be passed to the interrupt handler
* @return 0 for success, negative value for failure
*/
typedef int (*metal_cntr_irq_register) (struct metal_irq_controller *irq_cntr,
int irq, metal_irq_handler hd,
void *arg);
/** Libmetal interrupt structure */
struct metal_irq {
metal_irq_handler hd; /**< Interrupt handler */
void *arg; /**< Argument to pass to the interrupt handler */
};
/** Libmetal interrupt controller structure */
struct metal_irq_controller {
int irq_base; /**< Start of IRQ number of the range managed by
* the IRQ controller
*/
int irq_num; /**< Number of IRQs managed by the IRQ controller */
void *arg; /**< Argument to pass to interrupt controller function */
metal_irq_set_enable irq_set_enable; /**< function to set IRQ enable */
metal_cntr_irq_register irq_register; /**< function to register IRQ
* handler
*/
struct metal_list node; /**< list node */
struct metal_irq *irqs; /**< Array of IRQs managed by the controller */
};
#define METAL_IRQ_CONTROLLER_DECLARE(_irq_controller, \
_irq_base, _irq_num, \
_arg, \
_irq_set_enable, \
_irq_register, \
_irqs) \
struct metal_irq_controller _irq_controller = { \
.irq_base = _irq_base, \
.irq_num = _irq_num, \
.arg = _arg, \
.irq_set_enable = _irq_set_enable, \
.irq_register = _irq_register, \
.irqs = _irqs,\
}
/**
* @brief metal_irq_register_controller
*
* Register IRQ controller
* This function will allocate IRQ ids if it was
* not predefined in the irq controller. There is no
* locking in the function, it is not supposed to be
* called by multiple threads.
*
* @param[in] cntr Interrupt controller to register
* @return 0 on success, or negative value for failure.
*/
int metal_irq_register_controller(struct metal_irq_controller *cntr);
/**
* @brief metal_irq_handle
*
* Call registered IRQ handler
*
* @param[in] irq_data metal IRQ structure
* @param[in] irq IRQ id which will be passed to handler
* @return IRQ handler status
*/
static inline
int metal_irq_handle(struct metal_irq *irq_data, int irq)
{
if (irq_data && irq_data->hd) {
return irq_data->hd(irq, irq_data->arg);
} else {
return METAL_IRQ_NOT_HANDLED;
}
}
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* __METAL_IRQ__H__ */
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/metal/list.h
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/*
* Copyright (c) 2015-2022 Xilinx, Inc. and Contributors. All rights reserved.
* Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* @file list.h
* @brief List primitives for libmetal.
*/
#ifndef __METAL_LIST__H__
#define __METAL_LIST__H__
#include <stdbool.h>
#include <stdlib.h>
#ifdef __cplusplus
extern "C" {
#endif
/** \defgroup list List Primitives
* @{
*/
struct metal_list {
struct metal_list *next, *prev;
};
/*
* METAL_INIT_LIST - used for initializing an list element in a static struct
* or global
*/
#define METAL_INIT_LIST(name) { .next = &name, .prev = &name }
/*
* METAL_DECLARE_LIST - used for defining and initializing a global or
* static singleton list
*/
#define METAL_DECLARE_LIST(name) \
struct metal_list name = METAL_INIT_LIST(name)
static inline void metal_list_init(struct metal_list *list)
{
list->prev = list;
list->next = list;
}
static inline void metal_list_add_before(struct metal_list *node,
struct metal_list *new_node)
{
new_node->prev = node->prev;
new_node->next = node;
new_node->next->prev = new_node;
new_node->prev->next = new_node;
}
static inline void metal_list_add_after(struct metal_list *node,
struct metal_list *new_node)
{
new_node->prev = node;
new_node->next = node->next;
new_node->next->prev = new_node;
new_node->prev->next = new_node;
}
static inline void metal_list_add_head(struct metal_list *list,
struct metal_list *node)
{
metal_list_add_after(list, node);
}
static inline void metal_list_add_tail(struct metal_list *list,
struct metal_list *node)
{
metal_list_add_before(list, node);
}
static inline int metal_list_is_empty(struct metal_list *list)
{
return list->next == list;
}
static inline void metal_list_del(struct metal_list *node)
{
node->next->prev = node->prev;
node->prev->next = node->next;
node->prev = node;
node->next = node;
}
static inline struct metal_list *metal_list_first(struct metal_list *list)
{
return metal_list_is_empty(list) ? NULL : list->next;
}
#define metal_list_for_each(list, node) \
for ((node) = (list)->next; \
(node) != (list); \
(node) = (node)->next)
static inline bool metal_list_find_node(struct metal_list *list,
struct metal_list *node)
{
struct metal_list *n;
metal_list_for_each(list, n) {
if (n == node)
return true;
}
return false;
}
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* __METAL_LIST__H__ */
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/metal/log.h
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/*
* Copyright (c) 2015-2022 Xilinx, Inc. and Contributors. All rights reserved.
* Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* @file log.h
* @brief Logging support for libmetal.
*/
#ifndef __METAL_METAL_LOG__H__
#define __METAL_METAL_LOG__H__
#ifdef __cplusplus
extern "C" {
#endif
/** \defgroup logging Library Logging Interfaces
* @{
*/
/** Log message priority levels for libmetal. */
enum metal_log_level {
METAL_LOG_EMERGENCY, /**< system is unusable. */
METAL_LOG_ALERT, /**< action must be taken immediately. */
METAL_LOG_CRITICAL, /**< critical conditions. */
METAL_LOG_ERROR, /**< error conditions. */
METAL_LOG_WARNING, /**< warning conditions. */
METAL_LOG_NOTICE, /**< normal but significant condition. */
METAL_LOG_INFO, /**< informational messages. */
METAL_LOG_DEBUG, /**< debug-level messages. */
};
/** Log message handler type. */
typedef void (*metal_log_handler)(enum metal_log_level level,
const char *format, ...);
/**
* @brief Set libmetal log handler.
* @param[in] handler log message handler.
* @return 0 on success, or -errno on failure.
*/
extern void metal_set_log_handler(metal_log_handler handler);
/**
* @brief Get the current libmetal log handler.
* @return Current log handler.
*/
extern metal_log_handler metal_get_log_handler(void);
/**
* @brief Set the level for libmetal logging.
* @param[in] level log message level.
*/
extern void metal_set_log_level(enum metal_log_level level);
/**
* @brief Get the current level for libmetal logging.
* @return Current log level.
*/
extern enum metal_log_level metal_get_log_level(void);
/**
* @brief Default libmetal log handler. This handler prints libmetal log
* messages to stderr.
* @param[in] level log message level.
* @param[in] format log message format string.
* @return 0 on success, or -errno on failure.
*/
extern void metal_default_log_handler(enum metal_log_level level,
const char *format, ...);
/**
* @internal
*
* @brief used by the metal_log() macro to update the format string
*
* If ML_FUNC_LINE is defined this macro generates a unified format
* string for metal_log() and its convenience metal_*() macros, i.e. it
* adds function-name:line-number prefix to all log messages.
*
* @param[in] fmt format string passed from the metal_log() macro
*/
#if defined(ML_FUNC_LINE)
#define metal_fmt(fmt) "%s:%u " fmt, __func__, __LINE__
#else /* ML_FUNC_LINE */
#define metal_fmt(fmt) fmt
#endif /* ML_FUNC_LINE */
/**
* @brief Emit a log message if the log level permits.
*
* @param level Log level.
* @param fmt Format string.
* @param args... Variable number of arguments.
*/
#define metal_log(level, fmt, args...) ({ \
if (_metal.common.log_handler && level <= _metal.common.log_level) \
_metal.common.log_handler(level, metal_fmt(fmt), ##args); \
})
#define metal_err(fmt, args...) metal_log(METAL_LOG_ERROR, fmt, ##args)
#define metal_warn(fmt, args...) metal_log(METAL_LOG_WARNING, fmt, ##args)
#define metal_info(fmt, args...) metal_log(METAL_LOG_INFO, fmt, ##args)
#define metal_dbg(fmt, args...) metal_log(METAL_LOG_DEBUG, fmt, ##args)
/**
* Convenience macros ML_ERR, ML_INFO, ML_DBG add source
* function name and the line number before the message.
* Inspired by pr_err, pr_info, etc. in the kernel's printk.h.
* Keep the original ML_ERR, ML_INFO, ML_DBG until the open-amp
* code is converted to use the new metal_*() macros.
*/
#define ML_ERR(fmt, args...) metal_err(fmt, ##args)
#define ML_INFO(fmt, args...) metal_info(fmt, ##args)
#define ML_DBG(fmt, args...) metal_dbg(fmt, ##args)
/** @} */
#ifdef __cplusplus
}
#endif
#include <metal/system/generic/log.h>
#endif /* __METAL_METAL_LOG__H__ */
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/metal/mutex.h
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/*
* Copyright (c) 2015-2022 Xilinx, Inc. and Contributors. All rights reserved.
* Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* @file mutex.h
* @brief Mutex primitives for libmetal.
*/
#ifndef __METAL_MUTEX__H__
#define __METAL_MUTEX__H__
#include <metal/system/generic/mutex.h>
#ifdef __cplusplus
extern "C" {
#endif
/** \defgroup mutex Mutex Interfaces
* @{
*/
/**
* @brief Initialize a libmetal mutex.
* @param[in] mutex Mutex to initialize.
*/
static inline void metal_mutex_init(metal_mutex_t *mutex)
{
__metal_mutex_init(mutex);
}
/**
* @brief Deinitialize a libmetal mutex.
* @param[in] mutex Mutex to deinitialize.
*/
static inline void metal_mutex_deinit(metal_mutex_t *mutex)
{
__metal_mutex_deinit(mutex);
}
/**
* @brief Try to acquire a mutex
* @param[in] mutex Mutex to mutex.
* @return 0 on failure to acquire, non-zero on success.
*/
static inline int metal_mutex_try_acquire(metal_mutex_t *mutex)
{
return __metal_mutex_try_acquire(mutex);
}
/**
* @brief Acquire a mutex
* @param[in] mutex Mutex to mutex.
*/
static inline void metal_mutex_acquire(metal_mutex_t *mutex)
{
__metal_mutex_acquire(mutex);
}
/**
* @brief Release a previously acquired mutex.
* @param[in] mutex Mutex to mutex.
* @see metal_mutex_try_acquire, metal_mutex_acquire
*/
static inline void metal_mutex_release(metal_mutex_t *mutex)
{
__metal_mutex_release(mutex);
}
/**
* @brief Checked if a mutex has been acquired.
* @param[in] mutex mutex to check.
* @see metal_mutex_try_acquire, metal_mutex_acquire
*/
static inline int metal_mutex_is_acquired(metal_mutex_t *mutex)
{
return __metal_mutex_is_acquired(mutex);
}
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* __METAL_MUTEX__H__ */
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/metal/processor/arm/atomic.h
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/*
* Copyright (c) 2015, Xilinx Inc. and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* @file arm/atomic.h
* @brief Arm specific atomic primitives for libmetal.
*/
#ifndef __METAL_ARM_ATOMIC__H__
#define __METAL_ARM_ATOMIC__H__
#endif /* __METAL_ARM_ATOMIC__H__ */
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/metal/processor/arm/cpu.h
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/*
* Copyright (c) 2015-2022 Xilinx, Inc. and Contributors. All rights reserved.
* Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* @file cpu.h
* @brief CPU specific primitives
*/
#ifndef __METAL_ARM_CPU__H__
#define __METAL_ARM_CPU__H__
#define metal_cpu_yield()
#endif /* __METAL_ARM_CPU__H__ */
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/metal/shmem.h
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/*
* Copyright (c) 2015, Xilinx Inc. and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* @file shmem.h
* @brief Shared memory primitives for libmetal.
*/
#ifndef __METAL_SHMEM__H__
#define __METAL_SHMEM__H__
#include <metal/io.h>
#ifdef __cplusplus
extern "C" {
#endif
/** \defgroup shmem Shared Memory Interfaces
* @{
*/
/** Generic shared memory data structure. */
struct metal_generic_shmem {
const char *name;
struct metal_io_region io;
struct metal_list node;
};
/**
* @brief Open a libmetal shared memory segment.
*
* Open a shared memory segment.
*
* @param[in] name Name of segment to open.
* @param[in] size Size of segment.
* @param[out] io I/O region handle, if successful.
* @return 0 on success, or -errno on failure.
*
* @see metal_shmem_create
*/
extern int metal_shmem_open(const char *name, size_t size,
struct metal_io_region **io);
/**
* @brief Statically register a generic shared memory region.
*
* Shared memory regions may be statically registered at application
* initialization, or may be dynamically opened. This interface is used for
* static registration of regions. Subsequent calls to metal_shmem_open() look
* up in this list of pre-registered regions.
*
* @param[in] shmem Generic shmem structure.
* @return 0 on success, or -errno on failure.
*/
extern int metal_shmem_register_generic(struct metal_generic_shmem *shmem);
#ifdef METAL_INTERNAL
/**
* @brief Open a statically registered shmem segment.
*
* This interface is meant for internal libmetal use within system specific
* shmem implementations.
*
* @param[in] name Name of segment to open.
* @param[in] size Size of segment.
* @param[out] io I/O region handle, if successful.
* @return 0 on success, or -errno on failure.
*/
int metal_shmem_open_generic(const char *name, size_t size,
struct metal_io_region **result);
#endif
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* __METAL_SHMEM__H__ */
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/metal/sleep.h
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/*
* Copyright (c) 2016, Xilinx Inc. and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* @file sleep.h
* @brief Sleep primitives for libmetal.
*/
#ifndef __METAL_SLEEP__H__
#define __METAL_SLEEP__H__
#include <metal/system/generic/sleep.h>
#ifdef __cplusplus
extern "C" {
#endif
/** \defgroup sleep Sleep Interfaces
* @{
*/
/**
* @brief delay in microseconds
* delay the next execution in the calling thread
* fo usec microseconds.
*
* @param[in] usec microsecond intervals
* @return 0 on success, non-zero for failures
*/
static inline int metal_sleep_usec(unsigned int usec)
{
return __metal_sleep_usec(usec);
}
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* __METAL_SLEEP__H__ */
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/metal/softirq.h
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/*
* Copyright (c) 2019-2022 Xilinx, Inc. and Contributors. All rights reserved.
* Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* @file softirq.h
* @brief Soft Interrupt handling primitives for libmetal.
*/
#ifndef __METAL_SOFTIRQ__H__
#define __METAL_SOFTIRQ__H__
#include <metal/irq.h>
#ifdef __cplusplus
extern "C" {
#endif
/** \defgroup soft irq Interrupt Handling Interfaces
* @{
*/
/**
* @brief metal_softirq_init
*
* Initialize libmetal soft IRQs controller
*
* @return 0 on success, or negative value for failure
*/
int metal_softirq_init(void);
/**
* @brief metal_softirq_dispatch
*
* Dispatch the pending soft IRQs
*/
void metal_softirq_dispatch(void);
/**
* @brief metal_softirq_allocate
*
* Allocate soft IRQs
*
* This function doesn't have any locking, it is not supposed
* to be called by multiple threads.
*
* @param[in] num number of soft irqs requested
* @return soft irq base for success, or negative value for failure
*/
int metal_softirq_allocate(int num);
/**
* @brief metal_softirq_set
*
* Set soft IRQ to pending
*
* @param[in] irq soft IRQ ID to set
*/
void metal_softirq_set(int irq);
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* __METAL_SOFTIRQ__H__ */
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/metal/spinlock.h
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/*
* Copyright (c) 2016, Xilinx Inc. and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* @file spinlock.h
* @brief Spinlock primitives for libmetal.
*/
#ifndef __METAL_SPINLOCK__H__
#define __METAL_SPINLOCK__H__
#include <metal/atomic.h>
#include <metal/cpu.h>
#ifdef __cplusplus
extern "C" {
#endif
/** \defgroup spinlock Spinlock Interfaces
* @{
*/
struct metal_spinlock {
atomic_flag v;
};
/** Static metal spinlock initialization. */
#define METAL_SPINLOCK_INIT {ATOMIC_FLAG_INIT}
/**
* @brief Initialize a libmetal spinlock.
* @param[in] slock Spinlock to initialize.
*/
static inline void metal_spinlock_init(struct metal_spinlock *slock)
{
atomic_flag_clear(&slock->v);
}
/**
* @brief Acquire a spinlock.
* @param[in] slock Spinlock to acquire.
* @see metal_spinlock_release
*/
static inline void metal_spinlock_acquire(struct metal_spinlock *slock)
{
while (atomic_flag_test_and_set(&slock->v)) {
metal_cpu_yield();
}
}
/**
* @brief Release a previously acquired spinlock.
* @param[in] slock Spinlock to release.
* @see metal_spinlock_acquire
*/
static inline void metal_spinlock_release(struct metal_spinlock *slock)
{
atomic_flag_clear(&slock->v);
}
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* __METAL_SPINLOCK__H__ */
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/metal/sys.h
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/*
* Copyright (c) 2015, Xilinx Inc. and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* @file sys.h
* @brief System primitives for libmetal.
* @brief Top level include internal to libmetal library code.
*/
#ifndef __METAL_SYS__H__
#define __METAL_SYS__H__
#include <stdlib.h>
#include <metal/log.h>
#include <metal/list.h>
#ifdef __cplusplus
extern "C" {
#endif
/** \defgroup system Top Level Interfaces
* @{
*/
/** Physical address type. */
typedef unsigned long metal_phys_addr_t;
/** Interrupt request number. */
typedef int metal_irq_t;
/** Bad offset into shared memory or I/O region. */
#define METAL_BAD_OFFSET ((unsigned long)-1)
/** Bad physical address value. */
#define METAL_BAD_PHYS ((metal_phys_addr_t)-1)
/** Bad virtual address value. */
#define METAL_BAD_VA ((void *)-1)
/** Bad IRQ. */
#define METAL_BAD_IRQ ((metal_irq_t)-1)
/**
* Initialization configuration for libmetal.
*/
struct metal_init_params {
/** log message handler (defaults to stderr). */
metal_log_handler log_handler;
/** default log message level (defaults to emergency). */
enum metal_log_level log_level;
};
/**
* System independent runtime state for libmetal. This is part of a system
* specific singleton data structure (@see _metal).
*/
struct metal_common_state {
/** reference count to track metal_init/metal_finish. */
int ref_count;
/** Current log level. */
enum metal_log_level log_level;
/** Current log handler (null for none). */
metal_log_handler log_handler;
/** List of registered buses. */
struct metal_list bus_list;
/** Generic statically defined shared memory segments. */
struct metal_list generic_shmem_list;
/** Generic statically defined devices. */
struct metal_list generic_device_list;
};
struct metal_state;
#include <metal/system/generic/sys.h>
#ifndef METAL_INIT_DEFAULTS
#define METAL_INIT_DEFAULTS \
{ \
.log_handler = metal_default_log_handler, \
.log_level = METAL_LOG_INFO, \
}
#endif
/** System specific runtime data. */
extern struct metal_state _metal;
/**
* @brief Initialize libmetal.
*
* Initialize the libmetal library.
*
* @param[in] params Initialization params (@see metal_init_params).
*
* @return 0 on success, or -errno on failure.
*
* @see metal_finish
*/
extern int metal_init(const struct metal_init_params *params);
/**
* @brief Shutdown libmetal.
*
* Shutdown the libmetal library, and release all reserved resources.
*
* @see metal_init
*/
extern void metal_finish(void);
#ifdef METAL_INTERNAL
/**
* @brief libmetal system initialization.
*
* This function initializes libmetal on Linux or Generic platforms. This
* involves obtaining necessary pieces of system information (sysfs mount path,
* page size, etc.).
*
* @param[in] params Initialization parameters (@see metal_init_params).
* @return 0 on success, or -errno on failure.
*/
extern int metal_sys_init(const struct metal_init_params *params);
/**
* @brief libmetal system shutdown.
*
* This function shuts down and releases resources held by libmetal Linux or
* Generic platform layers.
*
* @see metal_sys_init
*/
extern void metal_sys_finish(void);
#endif
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* __METAL_SYS__H__ */
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/metal/system/generic/alloc.h
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/*
* Copyright (c) 2016, Xilinx Inc. and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* @file generic/alloc.c
* @brief generic libmetal memory allocattion definitions.
*/
#ifndef __METAL_ALLOC__H__
#error "Include metal/alloc.h instead of metal/generic/alloc.h"
#endif
#ifndef __METAL_GENERIC_ALLOC__H__
#define __METAL_GENERIC_ALLOC__H__
#include <stdlib.h>
#ifdef __cplusplus
extern "C" {
#endif
static inline void *__metal_allocate_memory(unsigned int size)
{
return malloc(size);
}
static inline void __metal_free_memory(void *ptr)
{
free(ptr);
}
#ifdef __cplusplus
}
#endif
#endif /* __METAL_GENERIC_ALLOC__H__ */
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/metal/system/generic/assert.h
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/*
* Copyright (c) 2018, Xilinx Inc. and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* @file assert.h
* @brief Generic assertion support.
*/
#ifndef __METAL_ASSERT__H__
#error "Include metal/assert.h instead of metal/generic/assert.h"
#endif
#ifndef __METAL_GENERIC_ASSERT__H__
#define __METAL_GENERIC_ASSERT__H__
#include <assert.h>
/**
* @brief Assertion macro for bare-metal applications.
* @param cond Condition to evaluate.
*/
#define metal_sys_assert(cond) assert(cond)
#endif /* __METAL_GENERIC_ASSERT__H__ */
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/metal/system/generic/cache.h
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/*
* Copyright (c) 2018, Linaro Limited. and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* @file generic/cache.h
* @brief generic cache operation primitives for libmetal.
*/
#ifndef __METAL_CACHE__H__
#error "Include metal/cache.h instead of metal/generic/cache.h"
#endif
#ifndef __METAL_GENERIC_CACHE__H__
#define __METAL_GENERIC_CACHE__H__
#ifdef __cplusplus
extern "C" {
#endif
extern void metal_machine_cache_flush(void *addr, unsigned int len);
extern void metal_machine_cache_invalidate(void *addr, unsigned int len);
static inline void __metal_cache_flush(void *addr, unsigned int len)
{
metal_machine_cache_flush(addr, len);
}
static inline void __metal_cache_invalidate(void *addr, unsigned int len)
{
metal_machine_cache_invalidate(addr, len);
}
#ifdef __cplusplus
}
#endif
#endif /* __METAL_GENERIC_CACHE__H__ */
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/metal/system/generic/condition.h
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/*
* Copyright (c) 2016, Xilinx Inc. and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* @file generic/condition.h
* @brief Generic condition variable primitives for libmetal.
*/
#ifndef __METAL_CONDITION__H__
#error "Include metal/condition.h instead of metal/generic/condition.h"
#endif
#ifndef __METAL_GENERIC_CONDITION__H__
#define __METAL_GENERIC_CONDITION__H__
#include <metal/atomic.h>
#include <stdint.h>
#include <limits.h>
#include <metal/errno.h>
#ifdef __cplusplus
extern "C" {
#endif
struct metal_condition {
atomic_uintptr_t mptr; /**< mutex pointer.
* The condition variable is attached to
* this mutex when it is waiting.
* It is also used to check correctness
* in case there are multiple waiters.
*/
atomic_int v; /**< condition variable value. */
};
/** Static metal condition variable initialization. */
#define METAL_CONDITION_INIT { ATOMIC_VAR_INIT(0), ATOMIC_VAR_INIT(0) }
static inline void metal_condition_init(struct metal_condition *cv)
{
atomic_init(&cv->mptr, 0);
atomic_init(&cv->v, 0);
}
static inline int metal_condition_signal(struct metal_condition *cv)
{
if (!cv)
return -EINVAL;
/** wake up waiters if there are any. */
atomic_fetch_add(&cv->v, 1);
return 0;
}
static inline int metal_condition_broadcast(struct metal_condition *cv)
{
return metal_condition_signal(cv);
}
#ifdef __cplusplus
}
#endif
#endif /* __METAL_GENERIC_CONDITION__H__ */
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/metal/system/generic/io.h
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/*
* Copyright (c) 2017, Xilinx Inc. and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* @file generic/io.h
* @brief Generic specific io definitions.
*/
#ifndef __METAL_IO__H__
#error "Include metal/io.h instead of metal/generic/io.h"
#endif
#ifndef __METAL_GENERIC_IO__H__
#define __METAL_GENERIC_IO__H__
#include <stdlib.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifdef METAL_INTERNAL
/**
* @brief memory mapping for an I/O region
*/
void metal_sys_io_mem_map(struct metal_io_region *io);
/**
* @brief memory mapping
*/
void *metal_machine_io_mem_map(void *va, metal_phys_addr_t pa,
size_t size, unsigned int flags);
#endif
#ifdef __cplusplus
}
#endif
#endif /* __METAL_GENERIC_IO__H__ */
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/metal/system/generic/irq.h
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/*
* Copyright (c) 2016, Xilinx Inc. and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* @file generic/irq.c
* @brief Generic libmetal irq definitions.
*/
#ifndef __METAL_IRQ__H__
#error "Include metal/irq.h instead of metal/generic/irq.h"
#endif
#ifndef __METAL_GENERIC_IRQ__H__
#define __METAL_GENERIC_IRQ__H__
#endif /* __METAL_GENERIC_IRQ__H__ */
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/metal/system/generic/log.h
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/*
* Copyright (c) 2018, Linaro Limited. and Contributors. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of Linaro nor the names of its contributors may be used
* to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* @file generic/log.h
* @brief Generic libmetal log handler definition.
*/
#ifndef __METAL_METAL_LOG__H__
#error "Include metal/log.h instead of metal/generic/log.h"
#endif
#ifndef __METAL_GENERIC_LOG__H__
#define __METAL_GENERIC_LOG__H__
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
#endif /* __METAL_GENERIC_LOG__H__ */
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/metal/system/generic/mutex.h
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/*
* Copyright (c) 2015, Xilinx Inc. and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* @file generic/mutex.h
* @brief Generic mutex primitives for libmetal.
*/
#ifndef __METAL_MUTEX__H__
#error "Include metal/mutex.h instead of metal/generic/mutex.h"
#endif
#ifndef __METAL_GENERIC_MUTEX__H__
#define __METAL_GENERIC_MUTEX__H__
#include <metal/atomic.h>
#ifdef __cplusplus
extern "C" {
#endif
typedef struct {
atomic_int v;
} metal_mutex_t;
#define METAL_MUTEX_UNLOCKED 0
#define METAL_MUTEX_LOCKED 1
/*
* METAL_MUTEX_INIT - used for initializing an mutex element in a static struct
* or global
*/
#define METAL_MUTEX_INIT(m) { ATOMIC_VAR_INIT(METAL_MUTEX_UNLOCKED) }
/*
* METAL_MUTEX_DEFINE - used for defining and initializing a global or
* static singleton mutex
*/
#define METAL_MUTEX_DEFINE(m) metal_mutex_t m = METAL_MUTEX_INIT(m)
static inline void __metal_mutex_init(metal_mutex_t *mutex)
{
atomic_store(&mutex->v, METAL_MUTEX_UNLOCKED);
}
static inline void __metal_mutex_deinit(metal_mutex_t *mutex)
{
(void)mutex;
}
static inline int __metal_mutex_try_acquire(metal_mutex_t *mutex)
{
int unlocked = METAL_MUTEX_UNLOCKED;
if (atomic_compare_exchange_strong(&mutex->v, &unlocked,
METAL_MUTEX_LOCKED)) {
return 1; /* acquired */
} else {
return 0; /* not acquired */
}
}
static inline void __metal_mutex_acquire(metal_mutex_t *mutex)
{
int unlocked = METAL_MUTEX_UNLOCKED;
while (!atomic_compare_exchange_weak(&mutex->v, &unlocked,
METAL_MUTEX_LOCKED)) {
;
}
}
static inline void __metal_mutex_release(metal_mutex_t *mutex)
{
atomic_store(&mutex->v, METAL_MUTEX_UNLOCKED);
}
static inline int __metal_mutex_is_acquired(metal_mutex_t *mutex)
{
return atomic_load(&mutex->v);
}
#ifdef __cplusplus
}
#endif
#endif /* __METAL_GENERIC_MUTEX__H__ */
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/metal/system/generic/sleep.h
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/*
* Copyright (c) 2018, Linaro Limited. and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* @file generic/sleep.h
* @brief Generic sleep primitives for libmetal.
*/
#ifndef __METAL_SLEEP__H__
#error "Include metal/sleep.h instead of metal/generic/sleep.h"
#endif
#ifndef __METAL_GENERIC_SLEEP__H__
#define __METAL_GENERIC_SLEEP__H__
#include <metal/utilities.h>
#ifdef __cplusplus
extern "C" {
#endif
static inline int __metal_sleep_usec(unsigned int usec)
{
metal_unused(usec);
/* Fix me */
return 0;
}
#ifdef __cplusplus
}
#endif
#endif /* __METAL_GENERIC_SLEEP__H__ */
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/metal/system/generic/sys.h
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/*
* Copyright (c) 2015, Xilinx Inc. and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* @file generic/sys.h
* @brief Generic system primitives for libmetal.
*/
#ifndef __METAL_SYS__H__
#error "Include metal/sys.h instead of metal/generic/sys.h"
#endif
#ifndef __METAL_GENERIC_SYS__H__
#define __METAL_GENERIC_SYS__H__
#include <limits.h>
#include <metal/errno.h>
#include <stdio.h>
#include <stdlib.h>
#include <stdarg.h>
#include <string.h>
#include <metal/system/generic/xlnx/sys.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifndef METAL_MAX_DEVICE_REGIONS
#define METAL_MAX_DEVICE_REGIONS 1
#endif
/** Structure of generic libmetal runtime state. */
struct metal_state {
/** Common (system independent) data. */
struct metal_common_state common;
};
#ifdef METAL_INTERNAL
/**
* @brief restore interrupts to state before disable_global_interrupt()
*/
void sys_irq_restore_enable(unsigned int flags);
/**
* @brief disable all interrupts
*/
unsigned int sys_irq_save_disable(void);
#endif /* METAL_INTERNAL */
#ifdef __cplusplus
}
#endif
#endif /* __METAL_GENERIC_SYS__H__ */
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/metal/system/generic/xlnx/sys.h
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/*
* Copyright (c) 2015, Xilinx Inc. and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* @file generic/xlnx/sys.h
* @brief generic xlnx system primitives for libmetal.
*/
#ifndef __METAL_GENERIC_SYS__H__
#error "Include metal/sys.h instead of metal/generic/zynqmp_a53/sys.h"
#endif
#ifndef __MICROBLAZE__
#include "xscugic.h"
#endif
#include <metal/assert.h>
#include <metal/io.h>
#include <metal/sys.h>
#include <stdint.h>
#include <metal/compiler.h>
#include <metal/utilities.h>
#include <xil_cache.h>
#include <xil_exception.h>
#include <xparameters.h>
#ifndef __METAL_GENERIC_XLNX_SYS__H__
#define __METAL_GENERIC_XLNX_SYS__H__
#ifdef __cplusplus
extern "C" {
#endif
#ifndef __MICROBLAZE__
#define XLNX_MAXIRQS XSCUGIC_MAX_NUM_INTR_INPUTS
#endif
#if defined(SDT) && !defined(__MICROBLAZE__)
#define XPAR_SCUGIC_0_DIST_BASEADDR XPAR_SCUGIC_DIST_BASEADDR
#endif
/**
* @brief metal_xlnx_irq_isr
*
* Xilinx interrupt ISR can be registered to the Xilinx embeddedsw
* IRQ controller driver.
*
* @param[in] arg input argument, interrupt vector id.
*/
void metal_xlnx_irq_isr(void *arg);
/**
* @brief metal_xlnx_irq_int
*
* Xilinx interrupt controller initialization. It will initialize
* the metal Xilinx IRQ controller data structure.
*
* @return 0 for success, or negative value for failure
*/
int metal_xlnx_irq_init(void);
/* Microblaze defines these routines */
#ifdef __MICROBLAZE__
void metal_weak sys_irq_enable(unsigned int vector);
void metal_weak sys_irq_disable(unsigned int vector);
#else
static inline void sys_irq_enable(unsigned int vector)
{
XScuGic_EnableIntr(XPAR_SCUGIC_0_DIST_BASEADDR, vector);
}
static inline void sys_irq_disable(unsigned int vector)
{
XScuGic_DisableIntr(XPAR_SCUGIC_0_DIST_BASEADDR, vector);
}
#endif
#ifdef __cplusplus
}
#endif
#endif /* __METAL_GENERIC_XLNX_SYS__H__ */
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/metal/time.h
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/*
* Copyright (c) 2016-2022 Xilinx, Inc. and Contributors. All rights reserved.
* Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* @file time.h
* @brief Time primitives for libmetal.
*/
#ifndef __METAL_TIME__H__
#define __METAL_TIME__H__
#include <stdint.h>
#include <metal/sys.h>
#ifdef __cplusplus
extern "C" {
#endif
/** \defgroup time TIME Interfaces
* @{
*/
/**
* @brief get timestamp
* This function returns the timestampe as unsigned long long
* value.
*
* @return timestamp
*/
unsigned long long metal_get_timestamp(void);
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* __METAL_TIME__H__ */
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/metal/utilities.h
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/*
* Copyright (c) 2015, Xilinx Inc. and Contributors. All rights reserved.
* Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* @file utilities.h
* @brief Utility routines for libmetal.
*/
#ifndef __METAL_UTILITIES__H__
#define __METAL_UTILITIES__H__
#include <stdint.h>
#include <limits.h>
#include <metal/assert.h>
#ifdef __cplusplus
extern "C" {
#endif
/** \defgroup utilities Simple Utilities
* @{
*/
#ifndef MB
#define MB (1024UL << 10UL)
#endif
#ifndef GB
#define GB (MB << 10UL)
#endif
/** Marker for unused function arguments/variables. */
#define metal_unused(x) do { (x) = (x); } while (0)
/** Figure out number of elements in an array. */
#define metal_dim(x) (sizeof(x) / sizeof(x[0]))
/** Minimum of two numbers (warning: multiple evaluation!). */
#define metal_min(x, y) ((x) < (y) ? (x) : (y))
/** Maximum of two numbers (warning: multiple evaluation!). */
#define metal_max(x, y) ((x) > (y) ? (x) : (y))
/** Sign of a number [-1, 0, or 1] (warning: multiple evaluation!). */
#define metal_sign(x) ((x) < 0 ? -1 : ((x) > 0 ? 1 : 0))
/** Align 'size' down to a multiple of 'align' (must be a power of two). */
#define metal_align_down(size, align) \
((size) & ~((align) - 1))
/** Align 'size' up to a multiple of 'align' (must be a power of two). */
#define metal_align_up(size, align) \
metal_align_down((size) + (align) - 1, align)
/** Divide (and round down). */
#define metal_div_round_down(num, den) \
((num) / (den))
/** Divide (and round up). */
#define metal_div_round_up(num, den) \
metal_div_round_down((num) + (den) - 1, (den))
/** Align 'ptr' down to a multiple of 'align' (must be a power of two). */
#define metal_ptr_align_down(ptr, align) \
(void *)(metal_align_down((uintptr_t)(ptr), (uintptr_t)(align)))
/** Align 'ptr' up to a multiple of 'align' (must be a power of two). */
#define metal_ptr_align_up(ptr, align) \
(void *)(metal_align_up((uintptr_t)(ptr), (uintptr_t)(align)))
/** Compute offset of a field within a structure. */
#define metal_offset_of(structure, member) \
((uintptr_t)&(((structure *)0)->member))
/** Compute pointer to a structure given a pointer to one of its fields. */
#define metal_container_of(ptr, structure, member) \
(void *)((uintptr_t)(ptr) - metal_offset_of(structure, member))
#define METAL_BITS_PER_ULONG (CHAR_BIT * sizeof(unsigned long))
#define metal_bit(bit) (1UL << (bit))
#define metal_bitmap_longs(x) metal_div_round_up((x), METAL_BITS_PER_ULONG)
static inline void metal_bitmap_set_bit(unsigned long *bitmap, int bit)
{
bitmap[bit / METAL_BITS_PER_ULONG] |=
metal_bit(bit & (METAL_BITS_PER_ULONG - 1));
}
static inline int metal_bitmap_is_bit_set(unsigned long *bitmap, int bit)
{
return ((bitmap[bit / METAL_BITS_PER_ULONG] &
metal_bit(bit & (METAL_BITS_PER_ULONG - 1))) == 0) ? 0 : 1;
}
static inline void metal_bitmap_clear_bit(unsigned long *bitmap, int bit)
{
bitmap[bit / METAL_BITS_PER_ULONG] &=
~metal_bit(bit & (METAL_BITS_PER_ULONG - 1));
}
static inline int metal_bitmap_is_bit_clear(unsigned long *bitmap, int bit)
{
return !metal_bitmap_is_bit_set(bitmap, bit);
}
static inline unsigned int
metal_bitmap_next_set_bit(unsigned long *bitmap, unsigned int start,
unsigned int max)
{
unsigned int bit;
for (bit = start;
bit < max && !metal_bitmap_is_bit_set(bitmap, bit);
bit++)
;
return bit;
}
#define metal_bitmap_for_each_set_bit(bitmap, bit, max) \
for ((bit) = metal_bitmap_next_set_bit((bitmap), 0, (max)); \
(bit) < (max); \
(bit) = metal_bitmap_next_set_bit((bitmap), (bit + 1), (max)))
static inline unsigned int
metal_bitmap_next_clear_bit(unsigned long *bitmap, unsigned int start,
unsigned int max)
{
unsigned int bit;
for (bit = start;
bit < max && !metal_bitmap_is_bit_clear(bitmap, bit);
bit++)
;
return bit;
}
#define metal_bitmap_for_each_clear_bit(bitmap, bit, max) \
for ((bit) = metal_bitmap_next_clear_bit((bitmap), 0, (max)); \
(bit) < (max); \
(bit) = metal_bitmap_next_clear_bit((bitmap), (bit + 1), (max)))
static inline unsigned long metal_log2(unsigned long in)
{
unsigned long result;
metal_assert((in & (in - 1)) == 0);
for (result = 0; (1UL << result) < in; result++)
;
return result;
}
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* __METAL_UTILITIES__H__ */
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/metal/version.h
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/*
* Copyright (c) 2015, Xilinx Inc. and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* @file version.h
* @brief Library version information for libmetal.
*/
#ifndef __METAL_VERSION__H__
#define __METAL_VERSION__H__
#ifdef __cplusplus
extern "C" {
#endif
/** \defgroup versions Library Version Interfaces
* @{
*/
/**
* @brief Library major version number.
*
* Return the major version number of the library linked into the application.
* This is required to match the value of METAL_VER_MAJOR, which is the major
* version of the library that the application was compiled against.
*
* @return Library major version number.
* @see METAL_VER_MAJOR
*/
extern int metal_ver_major(void);
/**
* @brief Library minor version number.
*
* Return the minor version number of the library linked into the application.
* This could differ from the value of METAL_VER_MINOR, which is the minor
* version of the library that the application was compiled against.
*
* @return Library minor version number.
* @see METAL_VER_MINOR
*/
extern int metal_ver_minor(void);
/**
* @brief Library patch level.
*
* Return the patch level of the library linked into the application. This
* could differ from the value of METAL_VER_PATCH, which is the patch level of
* the library that the application was compiled against.
*
* @return Library patch level.
* @see METAL_VER_PATCH
*/
extern int metal_ver_patch(void);
/**
* @brief Library version string.
*
* Return the version string of the library linked into the application. This
* could differ from the value of METAL_VER, which is the version string of
* the library that the application was compiled against.
*
* @return Library version string.
* @see METAL_VER
*/
extern const char *metal_ver(void);
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* __METAL_VERSION__H__ */
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/pm_api_version.h
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/******************************************************************************
* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
* @file pm_api_version.h
*
* @addtogroup xpm_versal_apis XilPM APIs
*****************************************************************************/
#ifndef PM_API_VERSION_H_
#define PM_API_VERSION_H_
/*****************************************************************************/
/**
* @section EEMI_API_DETAIL XilPM EEMI API Version Detail
*
* This section provides details of EEMI API version and it's history for PM APIs of XilPM library.
*
* | NAME | ID | Platform | Version| Description |
* |----------------------------|-------|---------------|:------:|---------------------------------------------------------------------------|
* | PM_GET_API_VERSION | 0x1 | Both | 1 | The API is used to request the version number of the API |
* | PM_SET_CONFIGURATION | 0x2 | ZynqMP | 1 | The API is used to configure the power management framework |
* | ^ | ^ | ^ | ^ | Note: Deprecated in Versal but supported in ZynqMP |
* | PM_GET_NODE_STATUS | 0x3 | Both | 1 | The API is used to obtain information about current status of a device |
* | PM_GET_OP_CHARACTERISTIC | 0x4 | Both | 2 | V1 - The API is used to get operating characteristics of a device |
* | ^ | ^ | ^ | ^ | V2 - Added support of bitmask functionality, user can check the supported\n "type" first before performing the actual functionality |
* | PM_REGISTER_NOTIFIER | 0x5 | Both | 2 | V1 - The API is used to register a subsystem to be notified about the\n device event |
* | ^ | ^ | ^ | ^ | V2 - Added support of event management functionality |
* | ^ | ^ | ^ | ^ | Note: V2 is supported in Versal but ZynqMP supports only V1 |
* | PM_REQUEST_SUSPEND | 0x6 | Both | 1 | The API is used to send suspend request to another subsystem |
* | PM_SELF_SUSPEND | 0x7 | Both | 3 | V1 - The API is used to suspend a child subsystem |
* | ^ | ^ | ^ | ^ | V2 - Added support of cpu idle functionality during force powerdown |
* | ^ | ^ | ^ | ^ | V3 - Added support of CPU off state |
* | ^ | ^ | ^ | ^ | Note: V3 is supported in Versal and Versal NET but ZynqMP supports only V1|
* | PM_FORCE_POWERDOWN | 0x8 | Both | 2 | V1 - The API is used to Powerdown other processor or node |
* | ^ | ^ | ^ | ^ | V2 - Added support of cpu idle functionality during force powerdown |
* | ^ | ^ | ^ | ^ | Note: V2 is supported in Versal but ZynqMP supports only V1 |
* | PM_ABORT_SUSPEND | 0x9 | Both | 1 | The API is used by a subsystem to abort suspend of a child subsystem |
* | PM_REQUEST_WAKEUP | 0xA | Both | 1 | The API is used to start-up and wake-up a child subsystem |
* | PM_SET_WAKEUP_SOURCE | 0xB | Both | 1 | The API is used to set wakeup source |
* | PM_SYSTEM_SHUTDOWN | 0xC | Both | 1 | The API is used to shutdown or restart the system |
* | PM_REQUEST_NODE | 0xD | Both | 2 | V1 - The API is used to request the usage of a device |
* | ^ | ^ | ^ | ^ | V2 - Added support of security policy handling during request device |
* | ^ | ^ | ^ | ^ | Note: V2 is supported in Versal but ZynqMP supports only V1 |
* | PM_RELEASE_NODE | 0xE | Both | 2 | V1 - The API is used to release the usage of a device |
* | ^ | ^ | ^ | ^ | V2 - Added support of security policy handling during request device |
* | ^ | ^ | ^ | ^ | Note: V2 is supported in Versal but ZynqMP supports only V1 |
* | PM_SET_REQUIREMENT | 0xF | Both | 1 | The API is used to announce a change in requirement for a specific slave\n node which is currently in use |
* | PM_SET_MAX_LATENCY | 0x10 | Both | 1 | The API is used to set maximum allowed latency for the device |
* | PM_RESET_ASSERT | 0x11 | Both | 1 | The API is used to reset or de-reset a device |
* | PM_RESET_GET_STATUS | 0x12 | Both | 1 | The API is used to read the device reset state |
* | PM_MMIO_WRITE | 0x13 | ZynqMP | 1 | The API is used to write a value into a register |
* | ^ | ^ | ^ | ^ | Note: Deprecated in Versal but supported in ZynqMP |
* | PM_MMIO_READ | 0x14 | ZynqMP | 1 | The API is used to read a value from a register |
* | ^ | ^ | ^ | ^ | Note: Deprecated in Versal but supported in ZynqMP |
* | PM_INIT_FINALIZE | 0x15 | Both | 1 | The API is used to initialize subsystem and release unused devices |
* | PM_GET_CHIPID | 0x18 | Both | 1 | The API is used to request the version and ID code of a chip |
* | PM_PINCTRL_REQUEST | 0x1C | Both | 1 | The API is used to request the pin |
* | PM_PINCTRL_RELEASE | 0x1D | Both | 1 | The API is used to release the pin |
* | PM_PINCTRL_GET_FUNCTION | 0x1E | Both | 1 | The API is used to read the pin function |
* | PM_PINCTRL_SET_FUNCTION | 0x1F | Both | 1 | The API is used to set the pin function |
* | PM_PINCTRL_CONFIG_PARAM_GET| 0x20 | Both | 1 | The API is used to read the pin parameter value |
* | PM_PINCTRL_CONFIG_PARAM_SET| 0x21 | Both | 2 | V1 - The API is used to set the pin parameter value |
* | ^ | ^ | ^ | ^ | V2 - Added support of MIO tri-state controlling functionality |
* | ^ | ^ | ^ | ^ | Note: V2 is supported in ZynqMP but Versal supports only V1 |
* | PM_IOCTL | 0x22 | Both | 3 | V1 - The API is used to perform driver-like IOCTL functions on shared\n system devices |
* | ^ | ^ | ^ | ^ | V2 - Added support of bitmask functionality, user can check the supported\n ID first before performing the actual functionality |
* | ^ | ^ | ^ | ^ | V3 - Add support of zeroization of AIE data and program memory separately |
* | ^ | ^ | ^ | ^ | Note: V3 is supported in Versal but ZynqMP supports only V2 |
* | PM_QUERY_DATA | 0x23 | Both | 2 | V1 - The API is used to query information about the platform resources |
* | ^ | ^ | ^ | ^ | V2 - Added support of bitmask functionality, user can check the supported\n ID first before performing the actual functionality |
* | PM_CLOCK_ENABLE | 0x24 | Both | 1 | The API is used to enable the clock |
* | PM_CLOCK_DISABLE | 0x25 | Both | 1 | The API is used to disable the clock |
* | PM_CLOCK_GETSTATE | 0x26 | Both | 1 | The API is used to read the clock state |
* | PM_CLOCK_SETDIVIDER | 0x27 | Both | 1 | The API is used to set the divider value of the clock |
* | PM_CLOCK_GETDIVIDER | 0x28 | Both | 1 | The API is used to read the clock divider |
* | PM_CLOCK_SETPARENT | 0x2B | Both | 1 | The API is used to set the parent of the clock |
* | PM_CLOCK_GETPARENT | 0x2C | Both | 1 | The API is used to read the clock parent |
* | PM_PLL_SET_PARAM | 0x30 | Both | 1 | The API is used to set the parameter of PLL clock |
* | PM_PLL_GET_PARAM | 0x31 | Both | 1 | The API is used to read the parameter of PLL clock |
* | PM_PLL_SET_MODE | 0x32 | Both | 1 | The API is used to set the mode of PLL clock |
* | PM_PLL_GET_MODE | 0x33 | Both | 1 | The API is used to read the mode of PLL clock |
* | PM_REGISTER_ACCESS | 0x34 | ZynqMP | 1 | The API is used for register read/write access data |
* | ^ | ^ | ^ | ^ | Note: Deprecated in Versal but supported in ZynqMP |
* | PM_EFUSE_ACCESS | 0x35 | ZynqMP | 1 | The API is used to provide access to efuse memory |
* | ^ | ^ | ^ | ^ | Note: Deprecated in Versal but supported in ZynqMP |
* | PM_FEATURE_CHECK | 0x3F | Both | 2 | V1 - The API is used to return supported version of the given API |
* | ^ | ^ | ^ | ^ | V2 - Added support of bitmask payload functionality |
*
*****************************************************************************/
/*****************************************************************************/
/**
* @section IOCTL_ID_DETAIL XilPM IOCTL IDs Detail
*
* This section provides the details of the IOCTL IDs which are supported across the different platforms and their brief descriptions.
*
* | Name | ID | Platform | Description |
* |------------------------------------|-------|---------------|---------------------------------------|
* | IOCTL_GET_RPU_OPER_MODE | 0 | Both | Get RPU mode |
* | IOCTL_SET_RPU_OPER_MODE | 1 | Both | Set RPU mode |
* | IOCTL_RPU_BOOT_ADDR_CONFIG | 2 | Both | RPU boot address config |
* | IOCTL_TCM_COMB_CONFIG | 3 | Both | TCM config |
* | IOCTL_SET_TAPDELAY_BYPASS | 4 | Both | TAP delay bypass |
* | IOCTL_SD_DLL_RESET | 6 | Both | SD DLL reset |
* | IOCTL_SET_SD_TAPDELAY | 7 | Both | SD TAP delay |
* | IOCTL_SET_PLL_FRAC_MODE | 8 | Both | Set PLL frac mode |
* | IOCTL_GET_PLL_FRAC_MODE | 9 | Both | Get PLL frac mode |
* | IOCTL_SET_PLL_FRAC_DATA | 10 | Both | Set PLL frac data |
* | IOCTL_GET_PLL_FRAC_DATA | 11 | Both | Get PLL frac data |
* | IOCTL_WRITE_GGS | 12 | Both | Write GGS |
* | IOCTL_READ_GGS | 13 | Both | Read GGS |
* | IOCTL_WRITE_PGGS | 14 | Both | Write PGGS |
* | IOCTL_READ_PGGS | 15 | Both | Read PGGS |
* | IOCTL_ULPI_RESET | 16 | ZynqMP | ULPI reset |
* | IOCTL_SET_BOOT_HEALTH_STATUS | 17 | Both | Set boot status |
* | IOCTL_AFI | 18 | ZynqMP | AFI |
* | IOCTL_OSPI_MUX_SELECT | 21 | Versal | OSPI mux select |
* | IOCTL_USB_SET_STATE | 22 | Versal | USB set state |
* | IOCTL_GET_LAST_RESET_REASON | 23 | Versal | Get last reset reason |
* | IOCTL_AIE_ISR_CLEAR | 24 | Versal | AIE ISR clear |
* | IOCTL_REGISTER_SGI | 25 | None | Register SGI to ATF |
* | IOCTL_SET_FEATURE_CONFIG | 26 | ZynqMP | Set runtime feature config |
* | IOCTL_GET_FEATURE_CONFIG | 27 | ZynqMP | Get runtime feature config |
* | IOCTL_READ_REG | 28 | Versal | Read a 32-bit register |
* | IOCTL_MASK_WRITE_REG | 29 | Versal | RMW a 32-bit register |
* | IOCTL_SET_SD_CONFIG | 30 | ZynqMP | Set SD config register value |
* | IOCTL_SET_GEM_CONFIG | 31 | ZynqMP | Set GEM config register value |
* | IOCTL_SET_USB_CONFIG | 32 | ZynqMP | Set USB config register value |
* | IOCTL_AIE_OPS | 33 | Versal | AIE1/AIEML Run Time Operations |
* | IOCTL_GET_QOS | 34 | Versal | Get Device QoS value |
* | IOCTL_GET_APU_OPER_MODE | 35 | Versal | Get APU operation mode |
* | IOCTL_SET_APU_OPER_MODE | 36 | Versal | Set APU operation mode |
* | IOCTL_PREPARE_DDR_SHUTDOWN | 37 | Versal | Prepare DDR for shut down |
* | IOCTL_GET_SSIT_TEMP | 38 | Versal | Get secondary SLR min/max temperature |
*
*****************************************************************************/
/*****************************************************************************/
/**
* @section QUERY_ID_DETAIL XilPM QUERY IDs Detail
*
* This section provides the details of the QUERY IDs which are supported across the different platforms and their brief descriptions.
*
* | Name | ID | Platform | Description |
* |--------------------------------------------|-------|---------------|---------------------------------------|
* | XPM_QID_INVALID | 0 | Both | Invalid Query ID |
* | XPM_QID_CLOCK_GET_NAME | 1 | Both | Get clock name |
* | XPM_QID_CLOCK_GET_TOPOLOGY | 2 | Both | Get clock topology |
* | XPM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS | 3 | Both | Get clock fixedfactor parameter |
* | XPM_QID_CLOCK_GET_MUXSOURCES | 4 | Both | Get clock mux sources |
* | XPM_QID_CLOCK_GET_ATTRIBUTES | 5 | Both | Get clock attributes |
* | XPM_QID_PINCTRL_GET_NUM_PINS | 6 | Both | Get total pins |
* | XPM_QID_PINCTRL_GET_NUM_FUNCTIONS | 7 | Both | Get total pin functions |
* | XPM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS | 8 | Both | Get total pin function groups |
* | XPM_QID_PINCTRL_GET_FUNCTION_NAME | 9 | Both | Get pin function name |
* | XPM_QID_PINCTRL_GET_FUNCTION_GROUPS | 10 | Both | Get pin function groups |
* | XPM_QID_PINCTRL_GET_PIN_GROUPS | 11 | Both | Get pin groups |
* | XPM_QID_CLOCK_GET_NUM_CLOCKS | 12 | Both | Get number of clocks |
* | XPM_QID_CLOCK_GET_MAX_DIVISOR | 13 | Both | Get max clock divisor |
* | XPM_QID_PLD_GET_PARENT | 14 | Versal | Get PLD parent |
* | XPM_QID_PINCTRL_GET_ATTRIBUTES | 15 | Versal | Get pin attributes |
*
*****************************************************************************/
/*****************************************************************************/
/**
* @section GET_OP_CHAR_DETAIL XilPM GET_OP_CHAR IDs Detail
*
* This section provides the details of the GET_OP_CHAR IDs which are supported across the different platforms and their brief descriptions.
*
* | Name | ID | Platform | Description |
* |------------------------------------|-------|---------------|-----------------------------------------------|
* | PM_OPCHAR_TYPE_POWER | 1 | ZynqMP | Operating characteristic ID power |
* | PM_OPCHAR_TYPE_TEMP | 2 | Versal | Operating characteristic ID temperature |
* | PM_OPCHAR_TYPE_LATENCY | 3 | Both | Operating characteristic ID latency |
*
*****************************************************************************/
/**
* PM API IDs
*/
typedef enum {
PM_API_MIN, /**< 0x0 */
PM_GET_API_VERSION, /**< 0x1 */
PM_SET_CONFIGURATION, /**< 0x2 */
PM_GET_NODE_STATUS, /**< 0x3 */
PM_GET_OP_CHARACTERISTIC, /**< 0x4 */
PM_REGISTER_NOTIFIER, /**< 0x5 */
PM_REQUEST_SUSPEND, /**< 0x6 */
PM_SELF_SUSPEND, /**< 0x7 */
PM_FORCE_POWERDOWN, /**< 0x8 */
PM_ABORT_SUSPEND, /**< 0x9 */
PM_REQUEST_WAKEUP, /**< 0xA */
PM_SET_WAKEUP_SOURCE, /**< 0xB */
PM_SYSTEM_SHUTDOWN, /**< 0xC */
PM_REQUEST_NODE, /**< 0xD */
PM_RELEASE_NODE, /**< 0xE */
PM_SET_REQUIREMENT, /**< 0xF */
PM_SET_MAX_LATENCY, /**< 0x10 */
PM_RESET_ASSERT, /**< 0x11 */
PM_RESET_GET_STATUS, /**< 0x12 */
PM_MMIO_WRITE, /**< 0x13 */
PM_MMIO_READ, /**< 0x14 */
PM_INIT_FINALIZE, /**< 0x15 */
PM_FPGA_LOAD, /**< 0x16 */
PM_FPGA_GET_STATUS, /**< 0x17 */
PM_GET_CHIPID, /**< 0x18 */
PM_SECURE_RSA_AES, /**< 0x19 */
PM_SECURE_SHA, /**< 0x1A */
PM_SECURE_RSA, /**< 0x1B */
PM_PINCTRL_REQUEST, /**< 0x1C */
PM_PINCTRL_RELEASE, /**< 0x1D */
PM_PINCTRL_GET_FUNCTION, /**< 0x1E */
PM_PINCTRL_SET_FUNCTION, /**< 0x1F */
PM_PINCTRL_CONFIG_PARAM_GET, /**< 0x20 */
PM_PINCTRL_CONFIG_PARAM_SET, /**< 0x21 */
PM_IOCTL, /**< 0x22 */
PM_QUERY_DATA, /**< 0x23 */
PM_CLOCK_ENABLE, /**< 0x24 */
PM_CLOCK_DISABLE, /**< 0x25 */
PM_CLOCK_GETSTATE, /**< 0x26 */
PM_CLOCK_SETDIVIDER, /**< 0x27 */
PM_CLOCK_GETDIVIDER, /**< 0x28 */
PM_CLOCK_SETRATE, /**< 0x29 */
/* PM_CLOCK_GETRATE API is deprecated */
PM_RESERVE_ID, /**< 0x2A */
PM_CLOCK_SETPARENT, /**< 0x2B */
PM_CLOCK_GETPARENT, /**< 0x2C */
PM_SECURE_IMAGE, /**< 0x2D */
PM_FPGA_READ, /**< 0x2E */
PM_SECURE_AES, /**< 0x2F */
PM_PLL_SET_PARAMETER, /**< 0x30 */
PM_PLL_GET_PARAMETER, /**< 0x31 */
PM_PLL_SET_MODE, /**< 0x32 */
PM_PLL_GET_MODE, /**< 0x33 */
PM_REGISTER_ACCESS, /**< 0x34 */
PM_EFUSE_ACCESS, /**< 0x35 */
PM_ADD_SUBSYSTEM, /**< 0x36 */
PM_DESTROY_SUBSYSTEM, /**< 0x37 */
PM_DESCRIBE_NODES, /**< 0x38 */
PM_ADD_NODE, /**< 0x39 */
PM_ADD_NODE_PARENT, /**< 0x3A */
PM_ADD_NODE_NAME, /**< 0x3B */
PM_ADD_REQUIREMENT, /**< 0x3C */
PM_SET_CURRENT_SUBSYSTEM, /**< 0x3D */
PM_INIT_NODE, /**< 0x3E */
PM_FEATURE_CHECK, /**< 0x3F */
PM_ISO_CONTROL, /**< 0x40 */
PM_ACTIVATE_SUBSYSTEM, /**< 0x41 */
PM_SET_NODE_ACCESS, /**< 0x42 */
PM_BISR, /**< 0x43 */
PM_APPLY_TRIM, /**< 0x44 */
PM_NOC_CLOCK_ENABLE, /**< 0x45 */
PM_IF_NOC_CLOCK_ENABLE, /**< 0x46 */
PM_FORCE_HOUSECLEAN, /**< 0x47 */
PM_FPGA_GET_VERSION, /**< 0x48 */
PM_FPGA_GET_FEATURE_LIST, /**< 0x49 */
PM_API_MAX /**< 0x4A */
} XPm_ApiId;
#endif /* PM_API_VERSION_H_ */
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/sleep.h
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/******************************************************************************
* Copyright (C) 2014 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
* @file sleep.h
*
* This header file contains ARM Cortex A53,A9,R5,Microblaze specific sleep
* related APIs.
*
* <pre>
* MODIFICATION HISTORY :
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 6.6 srm 11/02/17 Added processor specific sleep routines
* function prototypes.
* 7.7 sk 01/10/22 Typecast sleep declaration argument from unsigned int to
* u32 to fix misra_c_2012_directive_4_6 violation.
* 7.7 sk 01/10/22 Modify the return type of sleep_R5 and usleep_R5 from
* unsigned to void to fix misra_c_2012_rule_17_7 violation.
* 8.0 sk 03/02/22 Update usleep_R5 and usleep parameter types to fix misra_
* c_2012_directive_4_6 violation.
* 8.0 sk 03/17/22 Modify the return type of usleep_MB from int to void and
* sleep_MB from unsigned to void to fix misra_c_2012_rule_
* 17_7 violation.
* 8.0 sk 03/17/22 Modify sleep_MB parameter type from unsigned int to
* u32 and usleep_MB parameter type from unsigned long to
* ULONG to fix misra_c_2012_rule_4_6 violation.
* 9.0 ml 03/03/23 Add description to fix doxygen warnings.
* 9.1 mus 10/24/23 Add support for RISC-V.
* </pre>
*
******************************************************************************/
#ifndef SLEEP_H
#define SLEEP_H
#include "xil_types.h"
#include "xil_io.h"
#ifdef __cplusplus
extern "C" {
#endif
/*****************************************************************************/
/**
*
* This macro polls an address periodically until a condition is met or till the
* timeout occurs.
* The minimum timeout for calling this macro is 100us. If the timeout is less
* than 100us, it still waits for 100us. Also the unit for the timeout is 100us.
* If the timeout is not a multiple of 100us, it waits for a timeout of
* the next usec value which is a multiple of 100us.
*
* @param IO_func - accessor function to read the register contents.
* Depends on the register width.
* @param ADDR - Address to be polled
* @param VALUE - variable to read the value
* @param COND - Condition to checked (usually involves VALUE)
* @param TIMEOUT_US - timeout in micro seconds
*
* @return 0 - when the condition is met
* -1 - when the condition is not met till the timeout period
*
* @note none
*
*****************************************************************************/
#define Xil_poll_timeout(IO_func, ADDR, VALUE, COND, TIMEOUT_US) \
( { \
u64 timeout = TIMEOUT_US/100; \
if(TIMEOUT_US%100!=0) \
timeout++; \
for(;;) { \
VALUE = IO_func(ADDR); \
if(COND) \
break; \
else { \
usleep(100); \
timeout--; \
if(timeout==0) \
break; \
} \
} \
(timeout>0) ? 0 : -1; \
} )
/************************** Function Prototypes ******************************/
void usleep(ULONG useconds);
void sleep(u32 seconds);
void usleep_R5(ULONG useconds);
void sleep_R5(u32 seconds);
void usleep_MB(ULONG useconds);
void sleep_MB(u32 seconds);
int usleep_A53(unsigned long useconds);
unsigned sleep_A53(unsigned int seconds);
int usleep_A9(unsigned long useconds);
unsigned sleep_A9(unsigned int seconds);
void sleep_riscv(u32 seconds);
void usleep_riscv(ULONG useconds);
/*****************************************************************************/
#ifdef __cplusplus
}
#endif
#endif
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/vectors.h
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/******************************************************************************
* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
* @file vectors.h
*
* This file contains the C level vector prototypes for the ARM Cortex A9 core.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- ---------------------------------------------------
* 1.00a ecm 10/20/10 Initial version, moved over from bsp area
* 6.0 mus 07/27/16 Consolidated vectors for a9,a53 and r5 processors
* 8.0 sk 03/02/22 Update _VECTORS_H_ with VECTORS_H_ to fix misra_c_
* 2012_rule_21_1 violation.
* </pre>
*
* @note
*
* None.
*
******************************************************************************/
#ifndef VECTORS_H_
#define VECTORS_H_
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
#ifdef __cplusplus
extern "C" {
#endif
/***************** Macros (Inline Functions) Definitions *********************/
/**************************** Type Definitions *******************************/
/************************** Constant Definitions *****************************/
/************************** Function Prototypes ******************************/
void FIQInterrupt(void);
void IRQInterrupt(void);
#if !defined (__aarch64__)
void SWInterrupt(void);
void DataAbortInterrupt(void);
void PrefetchAbortInterrupt(void);
void UndefinedException(void);
#else
void SynchronousInterrupt(void);
void SErrorInterrupt(void);
#endif
#ifdef __cplusplus
}
#endif
#endif /* protection macro */
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/xaxipmon.h
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/******************************************************************************
* Copyright (C) 2007 - 2020 Xilinx, Inc. All rights reserved.
* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/****************************************************************************/
/**
*
* @file xaxipmon.h
* @addtogroup axipmon Overview
* @{
* @details
*
* The XAxiPmon driver supports the Xilinx AXI Performance Monitor device.
*
* The AXI Performance Monitor device provides following features:
*
* Configurable number of Metric Counters and Incrementers
* Computes performance metrics for Agents connected to
* monitor slots (Up to 8 slots)
*
* The following Metrics can be computed:
*
* Metrics computed for an AXI4 MM agent:
* Write Request Count: Total number of write requests by/to the agent.
* Read Request Count: Total number of read requests given by/to the
* agent.
* Read Latency: It is defined as the time from the start of read address
* transaction to the beginning of the read data service.
* Write Latency: It is defined as the period needed a master completes
* write data transaction, i.e. from write address
* transaction to write response from slave.
* Write Byte Count: Total number of bytes written by/to the agent.
* This metric is helpful when calculating the
* throughput of the system.
* Read Byte Count: Total number of bytes read from/by the agent.
* Average Write Latency: Average write latency seen by the agent.
* It can be derived from total write latency
* and the write request count.
* Average Read Latency: Average read latency seen by the agent. It can be
* derived from total read latency and the read
* request count.
* Master Write Idle Cycle Count: Number of idle cycles caused by the
* masters during write transactions to
* the slave.
* Slave Write Idle Cycle Count: Number of idle cycles caused by this slave
* during write transactions to the slave.
* Master Read Idle Cycle Count: Number of idle cycles caused by the
* master during read transactions to the
* slave.
* Slave Read Idle Cycle Count: Number of idle cycles caused by this slave
* during read transactions to the slave.
*
* Metrics computed for an AXI4-Stream agent:
*
* Transfer Cycle Count: Total number of writes by/to the agent.
* Data Byte Count: Total number of data bytes written by/to the agent.
* This metric helps in calculating the throughput
* of the system.
* Position Byte Count: Total number of position bytes transferred.
* Null Byte Count: Total number of null bytes transferred.
* Packet Count: Total number of packets transferred.
*
* There are three modes : Advanced, Profile and Trace.
* - Advanced mode has 10 Mertic Counters, Sampled Metric Counters, Incrementors
* and Sampled Incrementors.
* - Profile mode has only 47 Metric Counters and Sampled Metric Counters.
* - Trace mode has no Counters.
* User should refer to the hardware device specification for detailed
* information about the device.
*
* This header file contains the prototypes of driver functions that can
* be used to access the AXI Performance Monitor device.
*
*
* <b> Initialization and Configuration </b>
*
* The device driver enables higher layer software (e.g., an application) to
* communicate to the AXI Performance Monitor device.
*
* XAxiPmon_CfgInitialize() API is used to initialize the AXI Performance Monitor
* device. The user needs to first call the XAxiPmon_LookupConfig() API which
* returns the Configuration structure pointer which is passed as a parameter to
* the XAxiPmon_CfgInitialize() API.
*
*
* <b>Interrupts</b>
*
* The AXI Performance Monitor does not support Interrupts
*
*
* <b> Virtual Memory </b>
*
* This driver supports Virtual Memory. The RTOS is responsible for calculating
* the correct device base address in Virtual Memory space.
*
*
* <b> Threads </b>
*
* This driver is not thread safe. Any needs for threads or thread mutual
* exclusion must be satisfied by the layer above this driver.
*
* <b> Asserts </b>
*
* Asserts are used within all Xilinx drivers to enforce constraints on argument
* values. Asserts can be turned off on a system-wide basis by defining, at
* compile time, the NDEBUG identifier. By default, asserts are turned on and it
* is recommended that users leave asserts on during development.
*
*
* <b> Building the driver </b>
*
* The XAxiPmon driver is composed of several source files. This allows the user
* to build and link only those parts of the driver that are necessary.
*
* <b> Limitations of the driver </b>
*
*
* <br><br>
*
* <pre>
*
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ----- -------- -----------------------------------------------------
* 1.00a bss 02/27/12 First release
* 2.00a bss 06/23/12 Updated to support v2_00a version of IP.
* 3.00a bss 09/03/12 To support v2_01_a version of IP:
* Deleted XAxiPmon_SetAgent, XAxiPmon_GetAgent APIs and
* added XAPM_FLAG_EVENT, XAPM_FLAG_EVNTSTAR,
* XAPM_FLAG_EVNTSTOP.
* Deleted XAxiPmon_SetAgent, XAxiPmon_GetAgent APIs and
* modified XAxiPmon_SetMetrics, XAxiPmon_GetMetrics APIs
* in xaxipmon.c
* Deleted XAPM_AGENT_OFFSET Macro in xaxipmon_hw.h
* 3.01a bss 10/25/12 To support new version of IP:
* Added XAPM_MCXLOGEN_OFFSET macros in xaxipmon_hw.h.
* Added XAxiPmon_SetMetricCounterCutOff,
* XAxiPmon_GetMetricCounterCutOff,
* XAxiPmon_EnableExternalTrigger and
* XAxiPmon_DisableExternalTrigger APIs in xaxipmon.c
* Modified XAxiPmon_SetMetrics and XAxiPmon_GetMetrics
* (CR #683746) in xaxipmon.c
* Added XAxiPmon_EnableEventLog,
* XAxiPmon_DisableMetricsCounter,
* XAxiPmon_EnableMetricsCounter APIs in xaxipmon.c to
* replace macros in this file.
* Added XAPM_FLAG_XXX macros.
* Added XAxiPmon_StartCounters and XAxiPmon_StopCounters
* APIs (CR #683799).
* Added XAxiPmon_StartEventLog and XAxiPmon_StopEventLog
* APIs (CR #683801).
* Added XAxiPmon_GetMetricName API (CR #683803).
* Deleted XAxiPmon_SetAgent, XAxiPmon_GetAgent
* declarations (CR #677337)
* 4.00a bss 01/17/13 To support new version of IP:
* Added XAPM_METRIC_SET_12 to XAPM_METRIC_SET_15 macros.
* Added XAxiPmon_SetLogEnableRanges,
* XAxiPmon_GetLogEnableRanges,
* XAxiPmon_EnableMetricCounterTrigger,
* XAxiPmon_DisableMetricCounterTrigger,
* XAxiPmon_EnableEventLogTrigger,
* XAxiPmon_DisableEventLogTrigger,
* XAxiPmon_SetWriteLatencyId,
* XAxiPmon_SetReadLatencyId,
* XAxiPmon_GetWriteLatencyId,
* XAxiPmon_GetReadLatencyId APIs and removed
* XAxiPmon_SetMetricCounterCutOff,
* XAxiPmon_GetMetricCounterCutOff,
* XAxiPmon_EnableExternalTrigger and
* XAxiPmon_DisableExternalTrigger APIs in xaxipmon.c
* Added XAPM_LATENCYID_OFFSET,
* XAPM_CR_EVTLOG_EXTTRIGGER_MASK,
* XAPM_LATENCYID_RID_MASK and XAPM_LATENCYID_WID_MASK in
* xaxipmon_hw.h
* 5.00a bss 08/26/13 To support new version of IP:
* XAxiPmon_SampleMetrics Macro.
* Modified XAxiPmon_CfgInitialize, Assert functions
* Added XAxiPmon_GetMetricCounter,
* XAxiPmon_SetSampleInterval, XAxiPmon_GetSampleInterval,
* XAxiPmon_SetWrLatencyStart, XAxiPmon_SetWrLatencyEnd,
* XAxiPmon_SetRdLatencyStart, XAxiPmon_SetRdLatencyEnd,
* XAxiPmon_GetWrLatencyStart, XAxiPmon_GetWrLatencyEnd,
* XAxiPmon_GetRdLatencyStart, XAxiPmon_GetRdLatencyEnd,
* XAxiPmon_SetWriteIdMask, XAxiPmon_SetReadIdMask,
* XAxiPmon_GetWriteIdMask and XAxiPmon_GetReadIdMask APIs
* Renamed :
* XAxiPmon_SetWriteLatencyId to
* XAxiPmon_SetWriteId, XAxiPmon_SetReadLatencyId to
* XAxiPmon_SetReadId, XAxiPmon_GetWriteLatencyId to
* XAxiPmon_GetWriteId and XAxiPmon_SetReadLatencyId to
* XAxiPmon_GetReadId. in xaxipmon.c
* Added Macros XAPM_MC10_OFFSET to XAPM_MC47_OFFSET,
* XAPM_SMC10_OFFSET to XAPM_SMC47_OFFSET,
* XAPM_IDMASK_OFFSET, XAPM_CR_IDFILTER_ENABLE_MASK,
* XAPM_CR_WRLATENCY_START_MASK,
* XAPM_CR_WRLATENCY_END_MASK,
* XAPM_CR_RDLATENCY_START_MASK,
* XAPM_CR_RDLATENCY_END_MASK and
* XAPM_MAX_COUNTERS_PROFILE.
* Renamed:
* XAPM_LATENCYID_OFFSET to XAPM_ID_OFFSET,
* XAPM_LATENCYID_RID_MASK to XAPM_ID_RID_MASK,
* XAPM_LATENCYID_WID_MASK to XAPM_ID_WID_MASK.
* in xaxipmon_hw.h.
* Modified driver tcl to generate new parameters
* ScaleFactor, ModeProfile, ModeTrace and ModeAdvanced
* in Config structure.
* 6.0 adk 19/12/13 Updated as per the New Tcl API's
* 6.1 adk 16/04/14 Updated the driver tcl for the newly added parameters in
* The Axi pmon IP.
* 6.2 bss 04/21/14 Updated XAxiPmon_CfgInitialize in xaxipmon.c to Reset
* counters and FIFOs based on Modes(CR#782671). And if
* both profile and trace modes are present set mode as
* Advanced.
* 6.2 bss 03/02/15 To support Zynq MP APM:
* Added Is32BitFiltering in XAxiPmon_Config structure.
* Updated XAxiPmon_SetWriteId, XAxiPmon_SetReadId,
* XAxiPmon_GetWriteId, XAxiPmon_GetReadId
* XAxiPmon_SetWriteIdMask, XAxiPmon_SetReadIdMask
* XAxiPmon_GetWriteIdMask, XAxiPmon_GetReadIdMask
* functions in xaxipmon.c.
* Added XAPM_RID_OFFSET and XAPM_RIDMASK_OFFSET in
* xaxipmon_hw.h
*
* 6.3 kvn 07/02/15 Modified code according to MISRA-C:2012 guidelines.
* 6.4 sk 11/10/15 Used UINTPTR instead of u32 for Baseaddress CR# 867425.
* Changed the prototype of XAxiPmon_CfgInitialize API.
* 6.5 ms 01/23/17 Modified xil_printf statement in main function for all
* examples to ensure that "Successfully ran" and "Failed"
* strings are available in all examples. This is a fix
* for CR-965028.
* ms 03/17/17 Added readme.txt file in examples folder for doxygen
* generation.
* 6.6 ms 04/18/17 Modified tcl file to add suffix U for all macro
* definitions of axipmon in xparameters.h
* 6.10 ht 06/23/23 Added support for system device-tree flow.
* </pre>
*
*****************************************************************************/
#ifndef XAXIPMON_H /* Prevent circular inclusions */
#define XAXIPMON_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files ********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xstatus.h"
#include "xaxipmon_hw.h"
/************************** Constant Definitions ****************************/
/**
* @name Macro for Maximum number of Counters
*
* @{
*/
#define XAPM_MAX_COUNTERS 10U /**< Maximum number of Counters */
#define XAPM_MAX_COUNTERS_PROFILE 48U /**< Maximum number of Counters */
/*@}*/
/**
* @name Indices for Metric Counters and Sampled Metric Coounters used with
* XAxiPmon_GetMetricCounter and XAxiPmon_GetSampledMetricCounter APIs
* @{
*/
#define XAPM_METRIC_COUNTER_0 0U /**< Metric Counter 0 Register Index */
#define XAPM_METRIC_COUNTER_1 1U /**< Metric Counter 1 Register Index */
#define XAPM_METRIC_COUNTER_2 2U /**< Metric Counter 2 Register Index */
#define XAPM_METRIC_COUNTER_3 3U /**< Metric Counter 3 Register Index */
#define XAPM_METRIC_COUNTER_4 4U /**< Metric Counter 4 Register Index */
#define XAPM_METRIC_COUNTER_5 5U /**< Metric Counter 5 Register Index */
#define XAPM_METRIC_COUNTER_6 6U /**< Metric Counter 6 Register Index */
#define XAPM_METRIC_COUNTER_7 7U /**< Metric Counter 7 Register Index */
#define XAPM_METRIC_COUNTER_8 8U /**< Metric Counter 8 Register Index */
#define XAPM_METRIC_COUNTER_9 9U /**< Metric Counter 9 Register Index */
/*@}*/
/**
* @name Indices for Incrementers and Sampled Incrementers used with
* XAxiPmon_GetIncrementer and XAxiPmon_GetSampledIncrementer APIs
* @{
*/
#define XAPM_INCREMENTER_0 0U /**< Metric Counter 0 Register Index */
#define XAPM_INCREMENTER_1 1U /**< Metric Counter 0 Register Index */
#define XAPM_INCREMENTER_2 2U /**< Metric Counter 0 Register Index */
#define XAPM_INCREMENTER_3 3U /**< Metric Counter 0 Register Index */
#define XAPM_INCREMENTER_4 4U /**< Metric Counter 0 Register Index */
#define XAPM_INCREMENTER_5 5U /**< Metric Counter 0 Register Index */
#define XAPM_INCREMENTER_6 6U /**< Metric Counter 0 Register Index */
#define XAPM_INCREMENTER_7 7U /**< Metric Counter 0 Register Index */
#define XAPM_INCREMENTER_8 8U /**< Metric Counter 0 Register Index */
#define XAPM_INCREMENTER_9 9U /**< Metric Counter 0 Register Index */
/*@}*/
/**
* @name Macros for Metric Selector Settings
* @{
*/
#define XAPM_METRIC_SET_0 0U /**< Write Transaction Count */
#define XAPM_METRIC_SET_1 1U /**< Read Transaction Count */
#define XAPM_METRIC_SET_2 2U /**< Write Byte Count */
#define XAPM_METRIC_SET_3 3U /**< Read Byte Count */
#define XAPM_METRIC_SET_4 4U /**< Write Beat Count */
#define XAPM_METRIC_SET_5 5U /**< Total Read Latency */
#define XAPM_METRIC_SET_6 6U /**< Total Write Latency */
#define XAPM_METRIC_SET_7 7U /**< Slv_Wr_Idle_Cnt */
#define XAPM_METRIC_SET_8 8U /**< Mst_Rd_Idle_Cnt */
#define XAPM_METRIC_SET_9 9U /**< Num_BValids */
#define XAPM_METRIC_SET_10 10U /**< Num_WLasts */
#define XAPM_METRIC_SET_11 11U /**< Num_RLasts */
#define XAPM_METRIC_SET_12 12U /**< Minimum Write Latency */
#define XAPM_METRIC_SET_13 13U /**< Maximum Write Latency */
#define XAPM_METRIC_SET_14 14U /**< Minimum Read Latency */
#define XAPM_METRIC_SET_15 15U /**< Maximum Read Latency */
#define XAPM_METRIC_SET_16 16U /**< Transfer Cycle Count */
#define XAPM_METRIC_SET_17 17U /**< Packet Count */
#define XAPM_METRIC_SET_18 18U /**< Data Byte Count */
#define XAPM_METRIC_SET_19 19U /**< Position Byte Count */
#define XAPM_METRIC_SET_20 20U /**< Null Byte Count */
#define XAPM_METRIC_SET_21 21U /**< Slv_Idle_Cnt */
#define XAPM_METRIC_SET_22 22U /**< Mst_Idle_Cnt */
#define XAPM_METRIC_SET_30 30U /**< External event count */
/*@}*/
/**
* @name Macros for Maximum number of Agents
* @{
*/
#define XAPM_MAX_AGENTS 8U /**< Maximum number of Agents */
/*@}*/
/**
* @name Macros for Flags in Flag Enable Control Register
* @{
*/
#define XAPM_FLAG_WRADDR 0x00000001 /**< Write Address Flag */
#define XAPM_FLAG_FIRSTWR 0x00000002 /**< First Write Flag */
#define XAPM_FLAG_LASTWR 0x00000004 /**< Last Write Flag */
#define XAPM_FLAG_RESPONSE 0x00000008 /**< Response Flag */
#define XAPM_FLAG_RDADDR 0x00000010 /**< Read Address Flag */
#define XAPM_FLAG_FIRSTRD 0x00000020 /**< First Read Flag */
#define XAPM_FLAG_LASTRD 0x00000040 /**< Last Read Flag */
#define XAPM_FLAG_SWDATA 0x00010000 /**< Software-written Data Flag */
#define XAPM_FLAG_EVENT 0x00020000 /**< Last Read Flag */
#define XAPM_FLAG_EVNTSTOP 0x00040000 /**< Last Read Flag */
#define XAPM_FLAG_EVNTSTART 0x00080000 /**< Last Read Flag */
#define XAPM_FLAG_GCCOVF 0x00100000 /**< Global Clock Counter Overflow
* Flag */
#define XAPM_FLAG_SCLAPSE 0x00200000 /**< Sample Counter Lapse Flag */
#define XAPM_FLAG_MC0 0x00400000U /**< Metric Counter 0 Flag */
#define XAPM_FLAG_MC1 0x00800000U /**< Metric Counter 1 Flag */
#define XAPM_FLAG_MC2 0x01000000U /**< Metric Counter 2 Flag */
#define XAPM_FLAG_MC3 0x02000000U /**< Metric Counter 3 Flag */
#define XAPM_FLAG_MC4 0x04000000U /**< Metric Counter 4 Flag */
#define XAPM_FLAG_MC5 0x08000000U /**< Metric Counter 5 Flag */
#define XAPM_FLAG_MC6 0x10000000U /**< Metric Counter 6 Flag */
#define XAPM_FLAG_MC7 0x20000000U /**< Metric Counter 7 Flag */
#define XAPM_FLAG_MC8 0x40000000U /**< Metric Counter 8 Flag */
#define XAPM_FLAG_MC9 0x80000000U /**< Metric Counter 9 Flag */
/*@}*/
/**
* @name Macros for Read/Write Latency Start and End points
* @{
*/
#define XAPM_LATENCY_ADDR_ISSUE 0U /**< Address Issue as start
point for Latency calculation*/
#define XAPM_LATENCY_ADDR_ACCEPT 1U /**< Address Acceptance as start
point for Latency calculation*/
#define XAPM_LATENCY_LASTRD 0U /**< Last Read as end point for
Latency calculation */
#define XAPM_LATENCY_LASTWR 0U /**< Last Write as end point for
Latency calculation */
#define XAPM_LATENCY_FIRSTRD 1U /**< First Read as end point for
Latency calculation */
#define XAPM_LATENCY_FIRSTWR 1U /**< First Write as end point for
Latency calculation */
/*@}*/
/**
* @name Macros for Modes of APM
* @{
*/
#define XAPM_MODE_TRACE 2U /**< APM in Trace mode */
#define XAPM_MODE_PROFILE 1U /**< APM in Profile mode */
#define XAPM_MODE_ADVANCED 0U /**< APM in Advanced mode */
/*@}*/
/**************************** Type Definitions *******************************/
/**
* This typedef contains configuration information for the AXI Performance
* Monitor device.
*/
typedef struct {
#ifndef SDT
u16 DeviceId; /**< Unique ID of device */
#else
char *Name;
#endif
UINTPTR BaseAddress; /**< Device base address */
s32 GlobalClkCounterWidth; /**< Global Clock Counter Width */
s32 MetricSampleCounterWidth ; /**< Metric Sample Counters Width */
u8 IsEventCount; /**< Event Count Enabled 1 - enabled
0 - not enabled */
u8 NumberofSlots; /**< Number of Monitor Slots */
u8 NumberofCounters; /**< Number of Counters */
u8 HaveSampledCounters; /**< Have Sampled Counters 1 - present
0 - Not present */
u8 IsEventLog; /**< Event Logging Enabled 1 - enabled
0 - Not enabled */
u32 FifoDepth; /**< Event Log FIFO Depth */
u32 FifoWidth; /**< Event Log FIFO Width */
u32 TidWidth; /**< Streaming Interface TID Width */
u8 ScaleFactor; /**< Event Count Scaling factor */
u8 ModeAdvanced; /**< Advanced Mode */
u8 ModeProfile; /**< Profile Mode */
u8 ModeTrace; /**< Trace Mode */
u8 Is32BitFiltering; /**< 32 bit filtering enabled */
u32 IntId; /**< Interrupt ID on GIC **/
UINTPTR IntrParent; /** Bit[0] Interrupt parent type Bit[64/32:1]
* Parent base address */
} XAxiPmon_Config;
/**
* The driver's instance data. The user is required to allocate a variable
* of this type for every AXI Performance Monitor device in system. A pointer
* to a variable of this type is then passed to the driver API functions.
*/
typedef struct {
XAxiPmon_Config Config; /**< XAxiPmon_Config of current device */
u32 IsReady; /**< Device is initialized and ready */
u8 Mode; /**< APM Mode */
} XAxiPmon;
/***************** Macros (Inline Functions) Definitions ********************/
/****************************************************************************/
/**
*
* This routine enables the Global Interrupt.
*
* @param InstancePtr is a pointer to the XAxiPmon instance.
*
* @return None.
*
* @note C-Style signature:
* void XAxiPmon_IntrGlobalEnable(XAxiPmon *InstancePtr)
*
*****************************************************************************/
#define XAxiPmon_IntrGlobalEnable(InstancePtr) \
XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, \
XAPM_GIE_OFFSET, 1)
/****************************************************************************/
/**
*
* This routine disables the Global Interrupt.
*
* @param InstancePtr is a pointer to the XAxiPmon instance.
*
* @return None.
*
* @note C-Style signature:
* void XAxiPmon_IntrGlobalDisable(XAxiPmon *InstancePtr)
*
*****************************************************************************/
#define XAxiPmon_IntrGlobalDisable(InstancePtr) \
XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, \
XAPM_GIE_OFFSET, 0)
/****************************************************************************/
/**
*
* This routine enables interrupt(s). Use the XAPM_IXR_* constants defined in
* xaxipmon_hw.h to create the bit-mask to enable interrupts.
*
* @param InstancePtr is a pointer to the XAxiPmon instance.
* @param Mask is the mask to enable. Bit positions of 1 will be enabled.
* Bit positions of 0 will keep the previous setting. This mask is
* formed by OR'ing XAPM_IXR__* bits defined in xaxipmon_hw.h.
*
* @return None.
*
* @note C-Style signature:
* void XAxiPmon_IntrEnable(XAxiPmon *InstancePtr, u32 Mask)
*
*****************************************************************************/
#define XAxiPmon_IntrEnable(InstancePtr, Mask) \
XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_IE_OFFSET, \
XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \
XAPM_IE_OFFSET) | (Mask));
/****************************************************************************/
/**
*
* This routine disable interrupt(s). Use the XAPM_IXR_* constants defined in
* xaxipmon_hw.h to create the bit-mask to disable interrupts.
*
* @param InstancePtr is a pointer to the XAxiPmon instance.
* @param Mask is the mask to disable. Bit positions of 1 will be
* disabled. Bit positions of 0 will keep the previous setting.
* This mask is formed by OR'ing XAPM_IXR_* bits defined in
* xaxipmon_hw.h.
*
* @return None.
*
* @note C-Style signature:
* void XAxiPmon_IntrEnable(XAxiPmon *InstancePtr, u32 Mask)
*
*****************************************************************************/
#define XAxiPmon_IntrDisable(InstancePtr, Mask) \
XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_IE_OFFSET, \
XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \
XAPM_IE_OFFSET) | (Mask));
/****************************************************************************/
/**
*
* This routine clears the specified interrupt(s).
*
* @param InstancePtr is a pointer to the XAxiPmon instance.
* @param Mask is the mask to clear. Bit positions of 1 will be cleared.
* This mask is formed by OR'ing XAPM_IXR_* bits defined in
* xaxipmon_hw.h.
*
* @return None.
*
* @note C-Style signature:
* void XAxiPmon_IntrClear(XAxiPmon *InstancePtr, u32 Mask)
*
*****************************************************************************/
#define XAxiPmon_IntrClear(InstancePtr, Mask) \
XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_IS_OFFSET, \
XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \
XAPM_IS_OFFSET) | (Mask));
/****************************************************************************/
/**
*
* This routine returns the Interrupt Status Register.
*
* @param InstancePtr is a pointer to the XAxiPmon instance.
*
* @return Interrupt Status Register contents
*
* @note C-Style signature:
* void XAxiPmon_IntrClear(XAxiPmon *InstancePtr)
*
*****************************************************************************/
#define XAxiPmon_IntrGetStatus(InstancePtr) \
XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \
XAPM_IS_OFFSET);
/****************************************************************************/
/**
*
* This function enables the Global Clock Counter.
*
* @param InstancePtr is a pointer to the XAxiPmon instance.
*
* @return None
*
* @note C-Style signature:
* void XAxiPmon_EnableGlobalClkCounter(XAxiPmon *InstancePtr)
*
*****************************************************************************/
#define XAxiPmon_EnableGlobalClkCounter(InstancePtr) \
XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_CTL_OFFSET, \
XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \
XAPM_CTL_OFFSET) | XAPM_CR_GCC_ENABLE_MASK);
/****************************************************************************/
/**
*
* This function disbles the Global Clock Counter.
*
* @param InstancePtr is a pointer to the XAxiPmon instance.
*
* @return None
*
* @note C-Style signature:
* void XAxiPmon_DisableGlobalClkCounter(XAxiPmon *InstancePtr)
*
*****************************************************************************/
#define XAxiPmon_DisableGlobalClkCounter(InstancePtr) \
XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_CTL_OFFSET, \
XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \
XAPM_CTL_OFFSET) & ~(XAPM_CR_GCC_ENABLE_MASK));
/****************************************************************************/
/**
*
* This function enables the specified flag in Flag Control Register.
*
* @param InstancePtr is a pointer to the XAxiPmon instance.
* @param Flag is one of the XAPM_FLAG_* masks defined in xaxipmon.h
*
* @return None
*
* @note C-Style signature:
* void XAxiPmon_EnableFlag(XAxiPmon *InstancePtr)
*
*****************************************************************************/
#define XAxiPmon_EnableFlag(InstancePtr, Flag) \
XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_FEC_OFFSET, \
XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \
XAPM_FEC_OFFSET) | (Flag));
/****************************************************************************/
/**
*
* This function disables the specified flag in Flag Control Register.
*
* @param InstancePtr is a pointer to the XAxiPmon instance.
* @param Flag is one of the XAPM_FLAG_* masks defined in xaxipmon.h*
* @return None
*
* @note C-Style signature:
* void XAxiPmon_DisableFlag(XAxiPmon *InstancePtr)
*
*****************************************************************************/
#define XAxiPmon_DisableFlag(InstancePtr, Flag) \
XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_FEC_OFFSET, \
XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \
XAPM_FEC_OFFSET) & ~(Flag));
/****************************************************************************/
/**
*
* This function loads the sample interval register value into the sample
* interval counter.
*
* @param InstancePtr is a pointer to the XAxiPmon instance.
*
* @return None
*
* @note C-Style signature:
* void XAxiPmon_LoadSampleIntervalCounter(XAxiPmon *InstancePtr)
*
*****************************************************************************/
#define XAxiPmon_LoadSampleIntervalCounter(InstancePtr) \
XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_SICR_OFFSET, \
XAPM_SICR_LOAD_MASK);
/****************************************************************************/
/**
*
* This enables the down count of the sample interval counter.
*
* @param InstancePtr is a pointer to the XAxiPmon instance.
*
* @return None
*
* @note C-Style signature:
* void XAxiPmon_EnableSampleIntervalCounter(XAxiPmon *InstancePtr)
*
*****************************************************************************/
#define XAxiPmon_EnableSampleIntervalCounter(InstancePtr) \
XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_SICR_OFFSET,\
XAPM_SICR_ENABLE_MASK);
/****************************************************************************/
/**
*
* This disables the down count of the sample interval counter.
*
* @param InstancePtr is a pointer to the XAxiPmon instance.
*
* @return None
*
* @note C-Style signature:
* void XAxiPmon_DisableSampleIntervalCounter(XAxiPmon *InstancePtr)
*
*****************************************************************************/
#define XAxiPmon_DisableSampleIntervalCounter(InstancePtr) \
XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_SICR_OFFSET, \
XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \
XAPM_SICR_OFFSET) & ~(XAPM_SICR_ENABLE_MASK));
/****************************************************************************/
/**
*
* This enables Reset of Metric Counters when Sample Interval Counter lapses.
*
* @param InstancePtr is a pointer to the XAxiPmon instance.
*
* @return None
*
* @note C-Style signature:
* void XAxiPmon_EnableMetricCounterReset(XAxiPmon *InstancePtr)
*
*****************************************************************************/
#define XAxiPmon_EnableMetricCounterReset(InstancePtr) \
XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_SICR_OFFSET,\
XAPM_SICR_MCNTR_RST_MASK);
/****************************************************************************/
/**
*
* This disables the down count of the sample interval counter.
*
* @param InstancePtr is a pointer to the XAxiPmon instance.
*
* @return None
*
* @note C-Style signature:
* void XAxiPmon_DisableMetricCounterReset(XAxiPmon *InstancePtr)
*
*****************************************************************************/
#define XAxiPmon_DisableMetricCounterReset(InstancePtr) \
XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_SICR_OFFSET, \
XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \
XAPM_SICR_OFFSET) & ~(XAPM_SICR_MCNTR_RST_MASK));
/****************************************************************************/
/**
*
* This function enables the ID Filter Masking.
*
* @param InstancePtr is a pointer to the XAxiPmon instance.
*
* @return None
*
* @note C-Style signature:
* void XAxiPmon_EnableIDFilter(XAxiPmon *InstancePtr)
*
*****************************************************************************/
#define XAxiPmon_EnableIDFilter(InstancePtr) \
XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_CTL_OFFSET, \
XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \
XAPM_CTL_OFFSET) | XAPM_CR_IDFILTER_ENABLE_MASK);
/****************************************************************************/
/**
*
* This function disbles the ID Filter masking.
*
* @param InstancePtr is a pointer to the XAxiPmon instance.
*
* @return None
*
* @note C-Style signature:
* void XAxiPmon_DisableIDFilter(XAxiPmon *InstancePtr)
*
*****************************************************************************/
#define XAxiPmon_DisableIDFilter(InstancePtr) \
XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_CTL_OFFSET, \
XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \
XAPM_CTL_OFFSET) & ~(XAPM_CR_IDFILTER_ENABLE_MASK));
/****************************************************************************/
/**
*
* This function samples Metric Counters to Sampled Metric Counters by
* reading Sample Register and also returns interval. i.e. the number of
* clocks in between previous read to the current read of sample register.
*
* @param InstancePtr is a pointer to the XAxiPmon instance.
*
* @return Interval. i.e. the number of clocks in between previous
* read to the current read of sample register.
*
* @note C-Style signature:
* u32 XAxiPmon_SampleMetrics(XAxiPmon *InstancePtr)
*
*****************************************************************************/
#define XAxiPmon_SampleMetrics(InstancePtr) \
XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, XAPM_SR_OFFSET);
/************************** Function Prototypes *****************************/
/**
* Functions in xaxipmon_sinit.c
*/
#ifndef SDT
XAxiPmon_Config *XAxiPmon_LookupConfig(u16 DeviceId);
#else
XAxiPmon_Config *XAxiPmon_LookupConfig(UINTPTR BaseAddress);
#endif
/**
* Functions in xaxipmon.c
*/
s32 XAxiPmon_CfgInitialize(XAxiPmon *InstancePtr,
XAxiPmon_Config *ConfigPtr, UINTPTR EffectiveAddr);
s32 XAxiPmon_ResetMetricCounter(XAxiPmon *InstancePtr);
void XAxiPmon_ResetGlobalClkCounter(XAxiPmon *InstancePtr);
s32 XAxiPmon_ResetFifo(XAxiPmon *InstancePtr);
void XAxiPmon_SetIncrementerRange(XAxiPmon *InstancePtr, u8 IncrementerNum,
u16 RangeUpper, u16 RangeLower);
void XAxiPmon_GetIncrementerRange(XAxiPmon *InstancePtr, u8 IncrementerNum,
u16 *RangeUpper, u16 *RangeLower);
void XAxiPmon_SetSampleInterval(XAxiPmon *InstancePtr, u32 SampleInterval);
void XAxiPmon_GetSampleInterval(XAxiPmon *InstancePtr, u32 *SampleInterval);
s32 XAxiPmon_SetMetrics(XAxiPmon *InstancePtr, u8 Slot, u8 Metrics,
u8 CounterNum);
s32 XAxiPmon_GetMetrics(XAxiPmon *InstancePtr, u8 CounterNum, u8 *Metrics,
u8 *Slot);
void XAxiPmon_GetGlobalClkCounter(XAxiPmon *InstancePtr, u32 *CntHighValue,
u32 *CntLowValue);
u32 XAxiPmon_GetMetricCounter(XAxiPmon *InstancePtr, u32 CounterNum);
u32 XAxiPmon_GetSampledMetricCounter(XAxiPmon *InstancePtr, u32 CounterNum);
u32 XAxiPmon_GetIncrementer(XAxiPmon *InstancePtr, u32 IncrementerNum);
u32 XAxiPmon_GetSampledIncrementer(XAxiPmon *InstancePtr, u32 IncrementerNum);
void XAxiPmon_SetSwDataReg(XAxiPmon *InstancePtr, u32 SwData);
u32 XAxiPmon_GetSwDataReg(XAxiPmon *InstancePtr);
s32 XAxiPmon_StartEventLog(XAxiPmon *InstancePtr, u32 FlagEnables);
s32 XAxiPmon_StopEventLog(XAxiPmon *InstancePtr);
s32 XAxiPmon_StartCounters(XAxiPmon *InstancePtr, u32 SampleInterval);
s32 XAxiPmon_StopCounters(XAxiPmon *InstancePtr);
void XAxiPmon_EnableMetricsCounter(XAxiPmon *InstancePtr);
void XAxiPmon_DisableMetricsCounter(XAxiPmon *InstancePtr);
void XAxiPmon_SetLogEnableRanges(XAxiPmon *InstancePtr, u32 CounterNum,
u16 RangeUpper, u16 RangeLower);
void XAxiPmon_GetLogEnableRanges(XAxiPmon *InstancePtr, u32 CounterNum,
u16 *RangeUpper, u16 *RangeLower);
void XAxiPmon_EnableEventLog(XAxiPmon *InstancePtr);
void XAxiPmon_EnableMetricCounterTrigger(XAxiPmon *InstancePtr);
void XAxiPmon_DisableMetricCounterTrigger(XAxiPmon *InstancePtr);
void XAxiPmon_EnableEventLogTrigger(XAxiPmon *InstancePtr);
void XAxiPmon_DisableEventLogTrigger(XAxiPmon *InstancePtr);
const char *XAxiPmon_GetMetricName(u8 Metrics);
void XAxiPmon_SetWriteId(XAxiPmon *InstancePtr, u32 WriteId);
void XAxiPmon_SetReadId(XAxiPmon *InstancePtr, u32 ReadId);
u32 XAxiPmon_GetWriteId(XAxiPmon *InstancePtr);
u32 XAxiPmon_GetReadId(XAxiPmon *InstancePtr);
void XAxiPmon_SetWrLatencyStart(XAxiPmon *InstancePtr, u8 Param);
void XAxiPmon_SetWrLatencyEnd(XAxiPmon *InstancePtr, u8 Param);
void XAxiPmon_SetRdLatencyStart(XAxiPmon *InstancePtr, u8 Param);
void XAxiPmon_SetRdLatencyEnd(XAxiPmon *InstancePtr, u8 Param);
u8 XAxiPmon_GetWrLatencyStart(XAxiPmon *InstancePtr);
u8 XAxiPmon_GetWrLatencyEnd(XAxiPmon *InstancePtr);
u8 XAxiPmon_GetRdLatencyStart(XAxiPmon *InstancePtr);
u8 XAxiPmon_GetRdLatencyEnd(XAxiPmon *InstancePtr);
void XAxiPmon_SetWriteIdMask(XAxiPmon *InstancePtr, u32 WrMask);
void XAxiPmon_SetReadIdMask(XAxiPmon *InstancePtr, u32 RdMask);
u32 XAxiPmon_GetWriteIdMask(XAxiPmon *InstancePtr);
u32 XAxiPmon_GetReadIdMask(XAxiPmon *InstancePtr);
/**
* Functions in xaxipmon_selftest.c
*/
s32 XAxiPmon_SelfTest(XAxiPmon *InstancePtr);
#ifdef __cplusplus
}
#endif
#endif /* End of protection macro. */
/** @} */
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/xaxipmon_hw.h
+546
View File
@@ -0,0 +1,546 @@
/******************************************************************************
* Copyright (C) 2012 - 2020 Xilinx, Inc. All rights reserved.
* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/****************************************************************************/
/**
*
* @file xaxipmon_hw.h
* @addtogroup axipmon Overview
* @{
*
* This header file contains identifiers and basic driver functions (or
* macros) that can be used to access the AXI Performance Monitor.
*
* Refer to the device specification for more information about this driver.
*
* @note None.
*
* <pre>
*
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ----- -------- -----------------------------------------------------
* 1.00a bss 02/27/12 First release
* 2.00a bss 06/23/12 Updated to support v2_00a version of IP.
* 3.00a bss 09/03/12 Deleted XAPM_AGENT_OFFSET Macro to support
* v2_01a version of IP.
* 3.01a bss 10/25/12 To support new version of IP:
* Added XAPM_MCXLOGEN_OFFSET and
* XAPM_CR_EXTERNAL_TRIGGER_MASK macros.
* 4.00a bss 01/17/13 To support new version of IP:
* Added XAPM_LATENCYID_OFFSET,
* XAPM_CR_EVTLOG_EXTTRIGGER_MASK,
* XAPM_LATENCYID_RID_MASK and XAPM_LATENCYID_WID_MASK
* 5.00a bss 08/26/13 To support new version of IP:
* Added Macros XAPM_MC10_OFFSET to XAPM_MC47_OFFSET,
* XAPM_SMC10_OFFSET to XAPM_SMC47_OFFSET.
* Added macro XAPM_IDMASK_OFFSET, XAPM_SR_OFFSET.
* Added XAPM_CR_IDFILTER_ENABLE_MASK,
* XAPM_CR_WRLATENCY_START_MASK,
* XAPM_CR_WRLATENCY_END_MASK,
* XAPM_CR_RDLATENCY_START_MASK,
* XAPM_CR_RDLATENCY_END_MASK, XAPM_MASKID_RID_MASK
* and XAPM_MASKID_WID_MASK macros.
* Renamed:
* XAPM_LATENCYID_OFFSET to XAPM_ID_OFFSET,
* XAPM_LATENCYID_RID_MASK to XAPM_ID_RID_MASK,
* XAPM_LATENCYID_WID_MASK to XAPM_ID_WID_MASK.
*
* 6.2 bss 03/02/15 Added XAPM_RID_OFFSET and XAPM_RIDMASK_OFFSET to support
* Zynq MP APM.
*
* 6.3 kvn 07/02/15 Modified code according to MISRA-C:2012 guidelines.
* </pre>
*
*****************************************************************************/
#ifndef XAXIPMON_HW_H /* Prevent circular inclusions */
#define XAXIPMON_HW_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files ********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xil_io.h"
/************************** Constant Definitions ****************************/
/**@name Register offsets of AXIMONITOR in the Device Config
*
* The following constants provide access to each of the registers of the
* AXI PERFORMANCE MONITOR device.
* @{
*/
#define XAPM_GCC_HIGH_OFFSET 0x00000000U /**< Global Clock Counter
32 to 63 bits */
#define XAPM_GCC_LOW_OFFSET 0x00000004U /**< Global Clock Counter Lower
0-31 bits */
#define XAPM_SI_HIGH_OFFSET 0x00000020U /**< Sample Interval MSB */
#define XAPM_SI_LOW_OFFSET 0x00000024U /**< Sample Interval LSB */
#define XAPM_SICR_OFFSET 0x00000028U /**< Sample Interval Control
Register */
#define XAPM_SR_OFFSET 0x0000002CU /**< Sample Register */
#define XAPM_GIE_OFFSET 0x00000030U /**< Global Interrupt Enable
Register */
#define XAPM_IE_OFFSET 0x00000034U /**< Interrupt Enable Register */
#define XAPM_IS_OFFSET 0x00000038U /**< Interrupt Status Register */
#define XAPM_MSR0_OFFSET 0x00000044U /**< Metric Selector 0 Register */
#define XAPM_MSR1_OFFSET 0x00000048U /**< Metric Selector 1 Register */
#define XAPM_MSR2_OFFSET 0x0000004CU /**< Metric Selector 2 Register */
#define XAPM_MC0_OFFSET 0x00000100U /**< Metric Counter 0 Register */
#define XAPM_INC0_OFFSET 0x00000104U /**< Incrementer 0 Register */
#define XAPM_RANGE0_OFFSET 0x00000108U /**< Range 0 Register */
#define XAPM_MC0LOGEN_OFFSET 0x0000010CU /**< Metric Counter 0
Log Enable Register */
#define XAPM_MC1_OFFSET 0x00000110U /**< Metric Counter 1 Register */
#define XAPM_INC1_OFFSET 0x00000114U /**< Incrementer 1 Register */
#define XAPM_RANGE1_OFFSET 0x00000118U /**< Range 1 Register */
#define XAPM_MC1LOGEN_OFFSET 0x0000011CU /**< Metric Counter 1
Log Enable Register */
#define XAPM_MC2_OFFSET 0x00000120U /**< Metric Counter 2 Register */
#define XAPM_INC2_OFFSET 0x00000124U /**< Incrementer 2 Register */
#define XAPM_RANGE2_OFFSET 0x00000128U /**< Range 2 Register */
#define XAPM_MC2LOGEN_OFFSET 0x0000012CU /**< Metric Counter 2
Log Enable Register */
#define XAPM_MC3_OFFSET 0x00000130U /**< Metric Counter 3 Register */
#define XAPM_INC3_OFFSET 0x00000134U /**< Incrementer 3 Register */
#define XAPM_RANGE3_OFFSET 0x00000138U /**< Range 3 Register */
#define XAPM_MC3LOGEN_OFFSET 0x0000013CU /**< Metric Counter 3
Log Enable Register */
#define XAPM_MC4_OFFSET 0x00000140U /**< Metric Counter 4 Register */
#define XAPM_INC4_OFFSET 0x00000144U /**< Incrementer 4 Register */
#define XAPM_RANGE4_OFFSET 0x00000148U /**< Range 4 Register */
#define XAPM_MC4LOGEN_OFFSET 0x0000014CU /**< Metric Counter 4
Log Enable Register */
#define XAPM_MC5_OFFSET 0x00000150U /**< Metric Counter 5
Register */
#define XAPM_INC5_OFFSET 0x00000154U /**< Incrementer 5 Register */
#define XAPM_RANGE5_OFFSET 0x00000158U /**< Range 5 Register */
#define XAPM_MC5LOGEN_OFFSET 0x0000015CU /**< Metric Counter 5
Log Enable Register */
#define XAPM_MC6_OFFSET 0x00000160U /**< Metric Counter 6
Register */
#define XAPM_INC6_OFFSET 0x00000164U /**< Incrementer 6 Register */
#define XAPM_RANGE6_OFFSET 0x00000168U /**< Range 6 Register */
#define XAPM_MC6LOGEN_OFFSET 0x0000016CU /**< Metric Counter 6
Log Enable Register */
#define XAPM_MC7_OFFSET 0x00000170U /**< Metric Counter 7
Register */
#define XAPM_INC7_OFFSET 0x00000174U /**< Incrementer 7 Register */
#define XAPM_RANGE7_OFFSET 0x00000178U /**< Range 7 Register */
#define XAPM_MC7LOGEN_OFFSET 0x0000017CU /**< Metric Counter 7
Log Enable Register */
#define XAPM_MC8_OFFSET 0x00000180U /**< Metric Counter 8
Register */
#define XAPM_INC8_OFFSET 0x00000184U /**< Incrementer 8 Register */
#define XAPM_RANGE8_OFFSET 0x00000188U /**< Range 8 Register */
#define XAPM_MC8LOGEN_OFFSET 0x0000018CU /**< Metric Counter 8
Log Enable Register */
#define XAPM_MC9_OFFSET 0x00000190U /**< Metric Counter 9
Register */
#define XAPM_INC9_OFFSET 0x00000194U /**< Incrementer 9 Register */
#define XAPM_RANGE9_OFFSET 0x00000198U /**< Range 9 Register */
#define XAPM_MC9LOGEN_OFFSET 0x0000019CU /**< Metric Counter 9
Log Enable Register */
#define XAPM_SMC0_OFFSET 0x00000200U /**< Sampled Metric Counter
0 Register */
#define XAPM_SINC0_OFFSET 0x00000204U /**< Sampled Incrementer
0 Register */
#define XAPM_SMC1_OFFSET 0x00000210U /**< Sampled Metric Counter
1 Register */
#define XAPM_SINC1_OFFSET 0x00000214U /**< Sampled Incrementer
1 Register */
#define XAPM_SMC2_OFFSET 0x00000220U /**< Sampled Metric Counter
2 Register */
#define XAPM_SINC2_OFFSET 0x00000224U /**< Sampled Incrementer
2 Register */
#define XAPM_SMC3_OFFSET 0x00000230U /**< Sampled Metric Counter
3 Register */
#define XAPM_SINC3_OFFSET 0x00000234U /**< Sampled Incrementer
3 Register */
#define XAPM_SMC4_OFFSET 0x00000240U /**< Sampled Metric Counter
4 Register */
#define XAPM_SINC4_OFFSET 0x00000244U /**< Sampled Incrementer
4 Register */
#define XAPM_SMC5_OFFSET 0x00000250U /**< Sampled Metric Counter
5 Register */
#define XAPM_SINC5_OFFSET 0x00000254U /**< Sampled Incrementer
5 Register */
#define XAPM_SMC6_OFFSET 0x00000260U /**< Sampled Metric Counter
6 Register */
#define XAPM_SINC6_OFFSET 0x00000264U /**< Sampled Incrementer
6 Register */
#define XAPM_SMC7_OFFSET 0x00000270U /**< Sampled Metric Counter
7 Register */
#define XAPM_SINC7_OFFSET 0x00000274U /**< Sampled Incrementer
7 Register */
#define XAPM_SMC8_OFFSET 0x00000280U /**< Sampled Metric Counter
8 Register */
#define XAPM_SINC8_OFFSET 0x00000284U /**< Sampled Incrementer
8 Register */
#define XAPM_SMC9_OFFSET 0x00000290U /**< Sampled Metric Counter
9 Register */
#define XAPM_SINC9_OFFSET 0x00000294U /**< Sampled Incrementer
9 Register */
#define XAPM_MC10_OFFSET 0x000001A0U /**< Metric Counter 10
Register */
#define XAPM_MC11_OFFSET 0x000001B0U /**< Metric Counter 11
Register */
#define XAPM_MC12_OFFSET 0x00000500U /**< Metric Counter 12
Register */
#define XAPM_MC13_OFFSET 0x00000510U /**< Metric Counter 13
Register */
#define XAPM_MC14_OFFSET 0x00000520U /**< Metric Counter 14
Register */
#define XAPM_MC15_OFFSET 0x00000530U /**< Metric Counter 15
Register */
#define XAPM_MC16_OFFSET 0x00000540U /**< Metric Counter 16
Register */
#define XAPM_MC17_OFFSET 0x00000550U /**< Metric Counter 17
Register */
#define XAPM_MC18_OFFSET 0x00000560U /**< Metric Counter 18
Register */
#define XAPM_MC19_OFFSET 0x00000570U /**< Metric Counter 19
Register */
#define XAPM_MC20_OFFSET 0x00000580U /**< Metric Counter 20
Register */
#define XAPM_MC21_OFFSET 0x00000590U /**< Metric Counter 21
Register */
#define XAPM_MC22_OFFSET 0x000005A0U /**< Metric Counter 22
Register */
#define XAPM_MC23_OFFSET 0x000005B0U /**< Metric Counter 23
Register */
#define XAPM_MC24_OFFSET 0x00000700U /**< Metric Counter 24
Register */
#define XAPM_MC25_OFFSET 0x00000710U /**< Metric Counter 25
Register */
#define XAPM_MC26_OFFSET 0x00000720U /**< Metric Counter 26
Register */
#define XAPM_MC27_OFFSET 0x00000730U /**< Metric Counter 27
Register */
#define XAPM_MC28_OFFSET 0x00000740U /**< Metric Counter 28
Register */
#define XAPM_MC29_OFFSET 0x00000750U /**< Metric Counter 29
Register */
#define XAPM_MC30_OFFSET 0x00000760U /**< Metric Counter 30
Register */
#define XAPM_MC31_OFFSET 0x00000770U /**< Metric Counter 31
Register */
#define XAPM_MC32_OFFSET 0x00000780U /**< Metric Counter 32
Register */
#define XAPM_MC33_OFFSET 0x00000790U /**< Metric Counter 33
Register */
#define XAPM_MC34_OFFSET 0x000007A0U /**< Metric Counter 34
Register */
#define XAPM_MC35_OFFSET 0x000007B0U /**< Metric Counter 35
Register */
#define XAPM_MC36_OFFSET 0x00000900U /**< Metric Counter 36
Register */
#define XAPM_MC37_OFFSET 0x00000910U /**< Metric Counter 37
Register */
#define XAPM_MC38_OFFSET 0x00000920U /**< Metric Counter 38
Register */
#define XAPM_MC39_OFFSET 0x00000930U /**< Metric Counter 39
Register */
#define XAPM_MC40_OFFSET 0x00000940U /**< Metric Counter 40
Register */
#define XAPM_MC41_OFFSET 0x00000950U /**< Metric Counter 41
Register */
#define XAPM_MC42_OFFSET 0x00000960U /**< Metric Counter 42
Register */
#define XAPM_MC43_OFFSET 0x00000970U /**< Metric Counter 43
Register */
#define XAPM_MC44_OFFSET 0x00000980U /**< Metric Counter 44
Register */
#define XAPM_MC45_OFFSET 0x00000990U /**< Metric Counter 45
Register */
#define XAPM_MC46_OFFSET 0x000009A0U /**< Metric Counter 46
Register */
#define XAPM_MC47_OFFSET 0x000009B0U /**< Metric Counter 47
Register */
#define XAPM_SMC10_OFFSET 0x000002A0U /**< Sampled Metric Counter
10 Register */
#define XAPM_SMC11_OFFSET 0x000002B0U /**< Sampled Metric Counter
11 Register */
#define XAPM_SMC12_OFFSET 0x00000600U /**< Sampled Metric Counter
12 Register */
#define XAPM_SMC13_OFFSET 0x00000610U /**< Sampled Metric Counter
13 Register */
#define XAPM_SMC14_OFFSET 0x00000620U /**< Sampled Metric Counter
14 Register */
#define XAPM_SMC15_OFFSET 0x00000630U /**< Sampled Metric Counter
15 Register */
#define XAPM_SMC16_OFFSET 0x00000640U /**< Sampled Metric Counter
16 Register */
#define XAPM_SMC17_OFFSET 0x00000650U /**< Sampled Metric Counter
17 Register */
#define XAPM_SMC18_OFFSET 0x00000660U /**< Sampled Metric Counter
18 Register */
#define XAPM_SMC19_OFFSET 0x00000670U /**< Sampled Metric Counter
19 Register */
#define XAPM_SMC20_OFFSET 0x00000680U /**< Sampled Metric Counter
20 Register */
#define XAPM_SMC21_OFFSET 0x00000690U /**< Sampled Metric Counter
21 Register */
#define XAPM_SMC22_OFFSET 0x000006A0U /**< Sampled Metric Counter
22 Register */
#define XAPM_SMC23_OFFSET 0x000006B0U /**< Sampled Metric Counter
23 Register */
#define XAPM_SMC24_OFFSET 0x00000800U /**< Sampled Metric Counter
24 Register */
#define XAPM_SMC25_OFFSET 0x00000810U /**< Sampled Metric Counter
25 Register */
#define XAPM_SMC26_OFFSET 0x00000820U /**< Sampled Metric Counter
26 Register */
#define XAPM_SMC27_OFFSET 0x00000830U /**< Sampled Metric Counter
27 Register */
#define XAPM_SMC28_OFFSET 0x00000840U /**< Sampled Metric Counter
28 Register */
#define XAPM_SMC29_OFFSET 0x00000850U /**< Sampled Metric Counter
29 Register */
#define XAPM_SMC30_OFFSET 0x00000860U /**< Sampled Metric Counter
30 Register */
#define XAPM_SMC31_OFFSET 0x00000870U /**< Sampled Metric Counter
31 Register */
#define XAPM_SMC32_OFFSET 0x00000880U /**< Sampled Metric Counter
32 Register */
#define XAPM_SMC33_OFFSET 0x00000890U /**< Sampled Metric Counter
33 Register */
#define XAPM_SMC34_OFFSET 0x000008A0U /**< Sampled Metric Counter
34 Register */
#define XAPM_SMC35_OFFSET 0x000008B0U /**< Sampled Metric Counter
35 Register */
#define XAPM_SMC36_OFFSET 0x00000A00U /**< Sampled Metric Counter
36 Register */
#define XAPM_SMC37_OFFSET 0x00000A10U /**< Sampled Metric Counter
37 Register */
#define XAPM_SMC38_OFFSET 0x00000A20U /**< Sampled Metric Counter
38 Register */
#define XAPM_SMC39_OFFSET 0x00000A30U /**< Sampled Metric Counter
39 Register */
#define XAPM_SMC40_OFFSET 0x00000A40U /**< Sampled Metric Counter
40 Register */
#define XAPM_SMC41_OFFSET 0x00000A50U /**< Sampled Metric Counter
41 Register */
#define XAPM_SMC42_OFFSET 0x00000A60U /**< Sampled Metric Counter
42 Register */
#define XAPM_SMC43_OFFSET 0x00000A70U /**< Sampled Metric Counter
43 Register */
#define XAPM_SMC44_OFFSET 0x00000A80U /**< Sampled Metric Counter
44 Register */
#define XAPM_SMC45_OFFSET 0x00000A90U /**< Sampled Metric Counter
45 Register */
#define XAPM_SMC46_OFFSET 0x00000AA0U /**< Sampled Metric Counter
46 Register */
#define XAPM_SMC47_OFFSET 0x00000AB0U /**< Sampled Metric Counter
47 Register */
#define XAPM_CTL_OFFSET 0x00000300U /**< Control Register */
#define XAPM_ID_OFFSET 0x00000304U /**< Latency ID Register */
#define XAPM_IDMASK_OFFSET 0x00000308U /**< ID Mask Register */
#define XAPM_RID_OFFSET 0x0000030CU /**< Latency Write ID Register */
#define XAPM_RIDMASK_OFFSET 0x00000310U /**< Read ID Mask Register */
#define XAPM_FEC_OFFSET 0x00000400U /**< Flag Enable
Control Register */
#define XAPM_SWD_OFFSET 0x00000404U /**< Software-written
Data Register */
/* @} */
/**
* @name AXI Monitor Sample Interval Control Register mask(s)
* @{
*/
#define XAPM_SICR_MCNTR_RST_MASK 0x00000100U /**< Enable the Metric
Counter Reset */
#define XAPM_SICR_LOAD_MASK 0x00000002U /**< Load the Sample Interval
* Register Value into the
* counter */
#define XAPM_SICR_ENABLE_MASK 0x00000001U /**< Enable the downcounter */
/*@}*/
/** @name Interrupt Status/Enable Register Bit Definitions and Masks
* @{
*/
#define XAPM_IXR_MC9_OVERFLOW_MASK 0x00001000U /**< Metric Counter 9
* Overflow> */
#define XAPM_IXR_MC8_OVERFLOW_MASK 0x00000800U /**< Metric Counter 8
* Overflow> */
#define XAPM_IXR_MC7_OVERFLOW_MASK 0x00000400U /**< Metric Counter 7
* Overflow> */
#define XAPM_IXR_MC6_OVERFLOW_MASK 0x00000200U /**< Metric Counter 6
* Overflow> */
#define XAPM_IXR_MC5_OVERFLOW_MASK 0x00000100U /**< Metric Counter 5
* Overflow> */
#define XAPM_IXR_MC4_OVERFLOW_MASK 0x00000080U /**< Metric Counter 4
* Overflow> */
#define XAPM_IXR_MC3_OVERFLOW_MASK 0x00000040U /**< Metric Counter 3
* Overflow> */
#define XAPM_IXR_MC2_OVERFLOW_MASK 0x00000020U /**< Metric Counter 2
* Overflow> */
#define XAPM_IXR_MC1_OVERFLOW_MASK 0x00000010U /**< Metric Counter 1
* Overflow> */
#define XAPM_IXR_MC0_OVERFLOW_MASK 0x00000008U /**< Metric Counter 0
* Overflow> */
#define XAPM_IXR_FIFO_FULL_MASK 0x00000004U /**< Event Log FIFO
* full> */
#define XAPM_IXR_SIC_OVERFLOW_MASK 0x00000002U /**< Sample Interval
* Counter Overflow> */
#define XAPM_IXR_GCC_OVERFLOW_MASK 0x00000001U /**< Global Clock Counter
* Overflow> */
#define XAPM_IXR_ALL_MASK (XAPM_IXR_SIC_OVERFLOW_MASK | \
XAPM_IXR_GCC_OVERFLOW_MASK | \
XAPM_IXR_FIFO_FULL_MASK | \
XAPM_IXR_MC0_OVERFLOW_MASK | \
XAPM_IXR_MC1_OVERFLOW_MASK | \
XAPM_IXR_MC2_OVERFLOW_MASK | \
XAPM_IXR_MC3_OVERFLOW_MASK | \
XAPM_IXR_MC4_OVERFLOW_MASK | \
XAPM_IXR_MC5_OVERFLOW_MASK | \
XAPM_IXR_MC6_OVERFLOW_MASK | \
XAPM_IXR_MC7_OVERFLOW_MASK | \
XAPM_IXR_MC8_OVERFLOW_MASK | \
XAPM_IXR_MC9_OVERFLOW_MASK)
/* @} */
/**
* @name AXI Monitor Control Register mask(s)
* @{
*/
#define XAPM_CR_FIFO_RESET_MASK 0x02000000U
/**< FIFO Reset */
#define XAPM_CR_GCC_RESET_MASK 0x00020000U
/**< Global Clk
Counter Reset */
#define XAPM_CR_GCC_ENABLE_MASK 0x00010000U
/**< Global Clk
Counter Enable */
#define XAPM_CR_EVTLOG_EXTTRIGGER_MASK 0x00000200U
/**< Enable External trigger
to start event Log */
#define XAPM_CR_EVENTLOG_ENABLE_MASK 0x00000100U
/**< Event Log Enable */
#define XAPM_CR_RDLATENCY_END_MASK 0x00000080U
/**< Write Latency
End point */
#define XAPM_CR_RDLATENCY_START_MASK 0x00000040U
/**< Read Latency
Start point */
#define XAPM_CR_WRLATENCY_END_MASK 0x00000020U
/**< Write Latency
End point */
#define XAPM_CR_WRLATENCY_START_MASK 0x00000010U
/**< Write Latency
Start point */
#define XAPM_CR_IDFILTER_ENABLE_MASK 0x00000008U
/**< ID Filter Enable */
#define XAPM_CR_MCNTR_EXTTRIGGER_MASK 0x00000004U
/**< Enable External
trigger to start
Metric Counters */
#define XAPM_CR_MCNTR_RESET_MASK 0x00000002U
/**< Metrics Counter
Reset */
#define XAPM_CR_MCNTR_ENABLE_MASK 0x00000001U
/**< Metrics Counter
Enable */
/*@}*/
/**
* @name AXI Monitor ID Register mask(s)
* @{
*/
#define XAPM_ID_RID_MASK 0xFFFF0000U /**< Read ID */
#define XAPM_ID_WID_MASK 0x0000FFFFU /**< Write ID */
/*@}*/
/**
* @name AXI Monitor ID Mask Register mask(s)
* @{
*/
#define XAPM_MASKID_RID_MASK 0xFFFF0000U /**< Read ID Mask */
#define XAPM_MASKID_WID_MASK 0x0000FFFFU /**< Write ID Mask*/
/*@}*/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/*****************************************************************************/
/**
*
* Read a register of the AXI Performance Monitor device. This macro provides
* register access to all registers using the register offsets defined above.
*
* @param BaseAddress contains the base address of the device.
* @param RegOffset is the offset of the register to read.
*
* @return The contents of the register.
*
* @note C-style Signature:
* u32 XAxiPmon_ReadReg(u32 BaseAddress, u32 RegOffset);
*
******************************************************************************/
#define XAxiPmon_ReadReg(BaseAddress, RegOffset) \
(Xil_In32((BaseAddress) + (RegOffset)))
/*****************************************************************************/
/**
*
* Write a register of the AXI Performance Monitor device. This macro provides
* register access to all registers using the register offsets defined above.
*
* @param BaseAddress contains the base address of the device.
* @param RegOffset is the offset of the register to write.
* @param Data is the value to write to the register.
*
* @return None.
*
* @note C-style Signature:
* void XAxiPmon_WriteReg(u32 BaseAddress,
* u32 RegOffset,u32 Data)
*
******************************************************************************/
#define XAxiPmon_WriteReg(BaseAddress, RegOffset, Data) \
(Xil_Out32((BaseAddress) + (RegOffset), (Data)))
/************************** Function Prototypes ******************************/
#ifdef __cplusplus
}
#endif
#endif /* End of protection macro. */
/** @} */
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/xbasic_types.h
+113
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@@ -0,0 +1,113 @@
/******************************************************************************
* Copyright (c) 2010 - 2021 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xbasic_types.h
*
*
* @note Dummy File for backwards compatibility
*
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a adk 1/31/14 Added in bsp common folder for backward compatibility
* 7.0 aru 01/21/19 Modified the typedef of u32,u16,u8
* 7.0 aru 02/06/19 Included stdint.h and stddef.h
* </pre>
*
******************************************************************************/
/**
*@cond nocomments
*/
#ifndef XBASIC_TYPES_H /* prevent circular inclusions */
#define XBASIC_TYPES_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include <stddef.h>
/** @name Legacy types
* Deprecated legacy types.
* @{
*/
typedef uint8_t Xuint8; /**< unsigned 8-bit */
typedef char Xint8; /**< signed 8-bit */
typedef uint16_t Xuint16; /**< unsigned 16-bit */
typedef short Xint16; /**< signed 16-bit */
typedef uint32_t Xuint32; /**< unsigned 32-bit */
typedef long Xint32; /**< signed 32-bit */
typedef float Xfloat32; /**< 32-bit floating point */
typedef double Xfloat64; /**< 64-bit double precision FP */
typedef unsigned long Xboolean; /**< boolean (XTRUE or XFALSE) */
#if !defined __XUINT64__
typedef struct
{
Xuint32 Upper;
Xuint32 Lower;
} Xuint64;
#endif
/** @name New types
* New simple types.
* @{
*/
#ifndef __KERNEL__
#ifndef XIL_TYPES_H
typedef Xuint32 u32;
typedef Xuint16 u16;
typedef Xuint8 u8;
#endif
#else
#include <linux/types.h>
#endif
#ifndef TRUE
# define TRUE 1U
#endif
#ifndef FALSE
# define FALSE 0U
#endif
#ifndef NULL
#define NULL 0U
#endif
/*
* Xilinx NULL, TRUE and FALSE legacy support. Deprecated.
* Please use NULL, TRUE and FALSE
*/
#define XNULL NULL
#define XTRUE TRUE
#define XFALSE FALSE
/*
* This file is deprecated and users
* should use xil_types.h and xil_assert.h\n\r
*/
#warning The xbasics_type.h file is deprecated and users should use xil_types.h and xil_assert.
#warning Please refer the Standalone BSP UG647 for further details
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/**
*@endcond
*/
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/xclockps.h
+686
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@@ -0,0 +1,686 @@
/******************************************************************************
* Copyright (C) 2018 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/****************************************************************************/
/**
*
* @file xclockps.h
* @addtogroup clockps Overview
* @{
*
* The Xilinx Clock controller driver provides APIs to control clock parameters.
* Below are the feature of the driver:
* - Manages database for mux, plls, gates, dividers and fixed factors for all
* the supported clocks.
* - Allows to enable/disable specific clock.
* - Allows to change the parent for specific clock.
* - Allows to get/set rate for specific clock.
*
* This driver is intended to be RTOS and processor independent. It works with
* physical addresses only. Any needs for dynamic memory management, threads
* or thread mutual exclusion, virtual memory, or cache control must be
* satisfied by the layer above this driver.
*
* <pre>
* MODIFICATION HISTORY:
* Ver Who Date Changes
* ----- ------ -------- ---------------------------------------------
* 1.00 cjp 02/09/18 First release
* 1.00 sd 07/26/18 Fix Doxygen warnings
* 1.1 aru 03/20/19 Fix IAR issue by changing "XCLOCK_ABS_DIFF" to a
* function named "XClock_Absolute_Difference".
* 1.2 sd 02/13/20 Rename ARRAY_SIZE
* 1.4 sd 12/02/21 Fix compilation warnings reported with "-Wundef" flag.
* 1.5 sd 07/10/23 Added SDT support
* 1.6 sd 11/03/23 Fix the redefinition of the PSS_REF frequency
* </pre>
*
******************************************************************************/
#ifndef XCLOCK_H /* prevent circular inclusions */
#define XCLOCK_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xstatus.h"
#include "xil_types.h"
#include "xil_io.h"
#include "xclockps_hw.h"
#if defined (__aarch64__)
#include "xil_smc.h"
#endif
/************************** Constant Definitions *****************************/
/*
* Device ID and Num Instances defines for resetps. Resetps uses common
* hardware with other driver and hence this wrapper defines are required
*/
#ifndef SDT
#define XPAR_XCLOCKPS_NUM_INSTANCES (XPAR_XCRPSU_NUM_INSTANCES)
#define XPAR_XCLOCKPS_DEVICE_ID (XPAR_XCRPSU_0_DEVICE_ID)
#endif
/* Fixed clock rate definitions */
#define XCLOCK_FIX_RATE_VIDEO_CLK (27000000U)
#define XCLOCK_FIX_RATE_PSS_ALT_REF_CLK \
(0U)
#define XCLOCK_FIX_RATE_GT_CRX_REF_CLK \
(108000000U)
#define XCLOCK_FIX_RATE_AUX_REF_CLK (27000000U)
#define XCLOCK_FIX_RATE_DP_ACLK (100000000U)
/* Miscellaneous defines */
#define XCLOCK_INVALID_PARENT (0xFFFF)
#define XCLOCK_PARENT_TYPE_MASK (0xFF00)
#define XCLOCK_PARENT_IDX_MASK (0x00FF)
#define XCLOCK_INVALID_RATE (0)
#define XCLOCK_DIVIDERS_BITWIDTH (6)
#define XCLOCK_MAX_DIV_VAL XCLOCK_VALUE_MASK(XCLOCK_DIVIDERS_BITWIDTH)
#define XCLOCK_INVALID_DIV_INDEX (MAX_DIVIDER + 1)
#define XCLOCK_INVALID_PLL_INDEX (MAX_PLL + 1)
/* Clock Flags */
#define XCLOCK_CLOCK_IS_CRITICAL BIT(0) /**< Clock is critical and will not be disabled */
/* Bit mask of specific length */
#define XCLOCK_VALUE_MASK(masklen) ((1 << masklen) - 1)
/* Bit shift */
#define BIT(n) (1 << (n))
/* Calculates array size */
#define CLK_ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
/* Division rounded to closest integer */
#define XCLOCK_ROUND_DIV(a, b) ((a + (b / 2)) / b)
/* Division rounded to integer greater than actual value */
#define XCLOCK_CEIL_DIV(a, b) ((a + b - 1) / b)
/**
* Gives the max value for unsigned type
* Note:
* Not to be used with signed types
*/
#define XCLOCK_MAX_VALUE_UNSIGNED_TYPE(type) \
(type)(~0)
/**
* Parent ID for node parents.
* Parent ID is combination of parent type and node indices. Most significant
* 8 bits represent type of parent and least significant 8 bits represents
* the node index in nodes database
*/
#define XCLOCK_GENERATE_PARENT_ID(type, idx) \
((u16)((u16)(type << 8) | (u8)(idx)))
/* Parse parent to fetch out parent type */
#define XCLOCK_FETCH_PARENT_TYPE(parent) \
((parent & XCLOCK_PARENT_TYPE_MASK) >> 8)
/* Parse parent to fetch out parent database index */
#define XCLOCK_FETCH_PARENT_INDEX(parent) \
(parent & XCLOCK_PARENT_IDX_MASK)
/* Limits the value within min and max */
#define XCLOCK_LIMIT_VALUE(val, min, max) \
do { \
if (val < min) { \
val = min; \
} \
if (val > max) { \
val = max; \
} \
} while (0)
/**
* This macro checks if index is valid.
* type corresponds to node type and can have either of below:
* - IP
* - OP
* - PLL
* - MUX
* - GATE
* - DIVIDER
* - FIXEDFACTOR
*
* The macro assumes the index to have unsigned data type and ignores lower
* bound checks.
*/
#define XCLOCK_VALIDATE_INDEX(type, index) \
do { \
if (MAX_##type < index) { \
return XST_INVALID_PARAM; \
} \
} while (0)
/**
* This macro checks for valid index and returns no failure status.
* The macro assumes the index to have unsigned data type and ignores lower
* bound checks.
*/
#define XCLOCK_VALIDATE_INDEX_WARN(type, index) \
do { \
if (MAX_##type < index) { \
xil_printf("Warning: Index %d out of bound for %s\n", \
index, #type); \
return; \
} \
} while (0)
/* This macro validates pointer to not be null */
#define XCLOCK_VALIDATE_PTR(ptr) \
do { \
if (NULL == ptr) { \
return XST_INVALID_PARAM; \
} \
} while (0)
/**************************** Type Definitions *******************************/
/* Type defined for Rate */
#if defined (__aarch64__)
typedef u64 XClockRate;
#else
typedef u32 XClockRate;
#endif
/* This typedef contains configuration information for the device */
typedef struct {
#ifndef SDT
u16 DeviceId; /**< Unique ID of device */
#else
char *Name;
u32 BaseAddress;
#endif
} XClockPs_Config;
/**
* The XClockPs driver instance data. The user is required to allocate a
* variable of this type for every clock controller device in the system.
* A pointer to a variable of this type is then passed to the driver API
* functions.
*/
typedef struct {
XClockPs_Config Config; /**< Hardware Configuration */
} XClock;
/* Type of clock nodes */
typedef enum {
XCLOCK_TYPE_IP,
XCLOCK_TYPE_PLL,
XCLOCK_TYPE_MUX,
XCLOCK_TYPE_GATE,
XCLOCK_TYPE_DIVIDER,
XCLOCK_TYPE_FIXEDFACTOR,
XCLOCK_TYPE_MAX
} XClock_Types;
/* List of output clocks */
typedef enum {
MIN_OP,
IOPLL = MIN_OP, RPLL, APLL, DPLL, VPLL,
IOPLL_TO_FPD, RPLL_TO_FPD, APLL_TO_LPD, DPLL_TO_LPD, VPLL_TO_LPD,
ACPU, ACPU_HALF,
DBG_FPD, DBG_LPD, DBG_TRACE, DBG_TSTMP,
DP_VIDEO_REF, DP_AUDIO_REF, DP_STC_REF,
GDMA_REF, DPDMA_REF,
DDR_REF,
SATA_REF,
PCIE_REF,
GPU_REF, GPU_PP0_REF, GPU_PP1_REF,
TOPSW_MAIN, TOPSW_LSBUS,
GTGREF0_REF,
LPD_SWITCH, LPD_LSBUS,
USB0_BUS_REF, USB1_BUS_REF, USB3_DUAL_REF, USB0, USB1,
CPU_R5, CPU_R5_CORE,
CSU_SPB, CSU_PLL,
PCAP,
IOU_SWITCH,
GEM_TSU_REF, GEM_TSU,
GEM0_REF, GEM1_REF, GEM2_REF, GEM3_REF,
GEM0_RX, GEM1_RX, GEM2_RX, GEM3_RX,
QSPI_REF,
SDIO0_REF, SDIO1_REF,
UART0_REF, UART1_REF,
SPI0_REF, SPI1_REF,
NAND_REF,
I2C0_REF, I2C1_REF,
CAN0_REF, CAN1_REF, CAN0, CAN1,
DLL_REF,
ADMA_REF,
TIMESTAMP_REF,
AMS_REF,
PL0, PL1, PL2, PL3,
WDT,
MAX_OP = WDT,
} XClock_OutputClks;
/* List of input clocks */
typedef enum {
MIN_IP,
PSS_REF_CLK = MIN_IP,
VIDEO_CLK,
PSS_ALT_REF_CLK,
GT_CRX_REF_CLK,
AUX_REF_CLK,
DP_ACLK,
MAX_IP = DP_ACLK,
} XClock_InputClks;
/* Divider database indices */
typedef enum {
MIN_DIVIDER,
PL0_DIV0 = MIN_DIVIDER,
PL0_DIV1,
PL1_DIV0,
PL1_DIV1,
PL2_DIV0,
PL2_DIV1,
PL3_DIV0,
PL3_DIV1,
APLL_TO_LPD_DIV0,
DPLL_TO_LPD_DIV0,
VPLL_TO_LPD_DIV0,
IOPLL_TO_FPD_DIV0,
RPLL_TO_FPD_DIV0,
ACPU_DIV0,
DDR_REF_DIV0,
GEM0_REF_DIV0,
GEM0_REF_DIV1,
GEM1_REF_DIV0,
GEM1_REF_DIV1,
GEM2_REF_DIV0,
GEM2_REF_DIV1,
GEM3_REF_DIV0,
GEM3_REF_DIV1,
TIMESTAMP_REF_DIV0,
DBG_TRACE_DIV0,
DBG_FPD_DIV0,
DBG_LPD_DIV0,
DBG_TSTMP_DIV0,
DP_VIDEO_REF_DIV0,
DP_VIDEO_REF_DIV1,
DP_AUDIO_REF_DIV0,
DP_AUDIO_REF_DIV1,
DP_STC_REF_DIV0,
DP_STC_REF_DIV1,
GPU_REF_DIV0,
SATA_REF_DIV0,
PCIE_REF_DIV0,
GDMA_REF_DIV0,
DPDMA_REF_DIV0,
TOPSW_MAIN_DIV0,
TOPSW_LSBUS_DIV0,
GTGREF0_REF_DIV0,
USB3_DUAL_REF_DIV0,
USB3_DUAL_REF_DIV1,
USB0_BUS_REF_DIV0,
USB0_BUS_REF_DIV1,
USB1_BUS_REF_DIV0,
USB1_BUS_REF_DIV1,
GEM_TSU_REF_DIV0,
GEM_TSU_REF_DIV1,
QSPI_REF_DIV0,
QSPI_REF_DIV1,
SDIO0_REF_DIV0,
SDIO0_REF_DIV1,
SDIO1_REF_DIV0,
SDIO1_REF_DIV1,
UART0_REF_DIV0,
UART0_REF_DIV1,
UART1_REF_DIV0,
UART1_REF_DIV1,
SPI0_REF_DIV0,
SPI0_REF_DIV1,
SPI1_REF_DIV0,
SPI1_REF_DIV1,
CAN0_REF_DIV0,
CAN0_REF_DIV1,
CAN1_REF_DIV0,
CAN1_REF_DIV1,
CPU_R5_DIV0,
IOU_SWITCH_DIV0,
CSU_PLL_DIV0,
PCAP_DIV0,
LPD_SWITCH_DIV0,
LPD_LSBUS_DIV0,
NAND_REF_DIV0,
NAND_REF_DIV1,
ADMA_REF_DIV0,
AMS_REF_DIV0,
AMS_REF_DIV1,
I2C0_REF_DIV0,
I2C0_REF_DIV1,
I2C1_REF_DIV0,
I2C1_REF_DIV1,
MAX_DIVIDER = I2C1_REF_DIV1,
} XClock_DivIndices;
/* Mux database indices */
typedef enum {
MIN_MUX,
IOPLL_PRE_SRC_MUX = MIN_MUX,
IOPLL_INT_MUX,
IOPLL_POST_SRC_MUX,
IOPLL_MUX,
RPLL_PRE_SRC_MUX,
RPLL_INT_MUX,
RPLL_POST_SRC_MUX,
RPLL_MUX,
APLL_PRE_SRC_MUX,
APLL_INT_MUX,
APLL_POST_SRC_MUX,
APLL_MUX,
DPLL_PRE_SRC_MUX,
DPLL_INT_MUX,
DPLL_POST_SRC_MUX,
DPLL_MUX,
VPLL_PRE_SRC_MUX,
VPLL_INT_MUX,
VPLL_POST_SRC_MUX,
VPLL_MUX,
ACPU_MUX,
WDT_MUX,
DDR_MUX,
PL0_MUX,
PL1_MUX,
PL2_MUX,
PL3_MUX,
DBG_TRACE_MUX,
DBG_FPD_MUX,
DBG_LPD_MUX,
DBG_TSTMP_MUX,
DP_VIDEO_REF_MUX,
DP_AUDIO_REF_MUX,
DP_STC_REF_MUX,
GPU_REF_MUX,
SATA_REF_MUX,
PCIE_REF_MUX,
GDMA_REF_MUX,
DPDMA_REF_MUX,
TOPSW_MAIN_MUX,
TOPSW_LSBUS_MUX,
GTGREF0_REF_MUX,
USB3_DUAL_REF_MUX,
USB0_BUS_REF_MUX,
USB1_BUS_REF_MUX,
GEM0_REF_MUX,
GEM0_TX_MUX,
GEM1_REF_MUX,
GEM1_TX_MUX,
GEM2_REF_MUX,
GEM2_TX_MUX,
GEM3_REF_MUX,
GEM3_TX_MUX,
GEM_TSU_REF_MUX,
GEM_TSU_MUX,
QSPI_REF_MUX,
SDIO0_REF_MUX,
SDIO1_REF_MUX,
UART0_REF_MUX,
UART1_REF_MUX,
SPI0_REF_MUX,
SPI1_REF_MUX,
CAN0_REF_MUX,
CAN0_MIO_MUX,
CAN0_MUX,
CAN1_REF_MUX,
CAN1_MIO_MUX,
CAN1_MUX,
CPU_R5_MUX,
IOU_SWITCH_MUX,
CSU_PLL_MUX,
PCAP_MUX,
LPD_SWITCH_MUX,
LPD_LSBUS_MUX,
NAND_REF_MUX,
ADMA_REF_MUX,
DLL_REF_MUX,
AMS_REF_MUX,
I2C0_REF_MUX,
I2C1_REF_MUX,
TIMESTAMP_REF_MUX,
MAX_MUX = TIMESTAMP_REF_MUX,
} XClock_MuxIndices;
/* Fixed factor database indices */
typedef enum {
MIN_FIXEDFACTOR,
IOPLL_INT_HALF_FF = MIN_FIXEDFACTOR,
RPLL_INT_HALF_FF,
APLL_INT_HALF_FF,
DPLL_INT_HALF_FF,
VPLL_INT_HALF_FF,
ACPU_HALF_DIV_FF,
MAX_FIXEDFACTOR = ACPU_HALF_DIV_FF,
} XClock_FixFactIndices;
/* Gate database indices */
typedef enum {
MIN_GATE,
ACPU_GATE = MIN_GATE,
ACPU_HALF_GATE,
PL0_GATE,
PL1_GATE,
PL2_GATE,
PL3_GATE,
DBG_TRACE_GATE,
DBG_FPD_GATE,
DBG_LPD_GATE,
DP_VIDEO_REF_GATE,
DP_AUDIO_REF_GATE,
DP_STC_REF_GATE,
GPU_REF_GATE,
GPU_PP0_REF_GATE,
GPU_PP1_REF_GATE,
SATA_REF_GATE,
PCIE_REF_GATE,
GDMA_REF_GATE,
DPDMA_REF_GATE,
TOPSW_MAIN_GATE,
TOPSW_LSBUS_GATE,
GTGREF0_REF_GATE,
USB3_DUAL_REF_GATE,
USB0_BUS_REF_GATE,
USB1_BUS_REF_GATE,
GEM0_TX_GATE,
GEM0_REF_GATE,
GEM1_TX_GATE,
GEM1_REF_GATE,
GEM2_TX_GATE,
GEM2_REF_GATE,
GEM3_TX_GATE,
GEM3_REF_GATE,
GEM_TSU_REF_GATE,
QSPI_REF_GATE,
SDIO0_REF_GATE,
SDIO1_REF_GATE,
UART0_REF_GATE,
UART1_REF_GATE,
SPI0_REF_GATE,
SPI1_REF_GATE,
CAN0_REF_GATE,
CAN1_REF_GATE,
CPU_R5_GATE,
CPU_R5_CORE_GATE,
IOU_SWITCH_GATE,
CSU_PLL_GATE,
PCAP_GATE,
LPD_SWITCH_GATE,
LPD_LSBUS_GATE,
NAND_REF_GATE,
ADMA_REF_GATE,
AMS_REF_GATE,
I2C0_REF_GATE,
I2C1_REF_GATE,
TIMESTAMP_REF_GATE,
MAX_GATE = TIMESTAMP_REF_GATE,
} XClock_GateIndices;
/* Pll database indices */
typedef enum {
MIN_PLL,
IOPLL_INT_PLL = MIN_PLL,
RPLL_INT_PLL,
APLL_INT_PLL,
DPLL_INT_PLL,
VPLL_INT_PLL,
MAX_PLL = VPLL_INT_PLL,
} XClock_PllIndices;
/************************** Variable Definitions *****************************/
/***************** Macros (Inline Functions) Definitions *********************/
/****************************************************************************/
/**
* Read the given register.
*
* @param RegAddr is the address of the register to read
* @param Value is the pointer to variable holding read value
*
* @return XST_SUCCESS if successful
* XST_FAILURE if unsuccessful
*
* @note Read from register may fail in case driver doesn't have proper
* access at EL1 NONSECURE
*
******************************************************************************/
static inline XStatus XClock_ReadReg(u32 RegAddr, u32 *Value)
{
#if defined (__aarch64__) && (EL1_NONSECURE == 1)
XSmc_OutVar RegValue;
RegValue = Xil_Smc(MMIO_READ_SMC_FID, (u64)(RegAddr), 0, 0, 0, 0, 0, 0);
if (0x00 == (RegValue.Arg0 & 0xFFFFFFFF)) {
*Value = RegValue.Arg0 >> 32;
return XST_SUCCESS;
}
return XST_FAILURE;
#else
*Value = Xil_In32((u32)RegAddr);
return XST_SUCCESS;
#endif
}
/****************************************************************************/
/**
*
* Write the given register.
*
* @param RegAddr is the address of the register to write
* @param Value is the 32-bit value to write to the register
*
* @return XST_SUCCESS if successful
* XST_FAILURE if unsuccessful
*
* @note Write to register may fail in case driver doesn't have proper
* access at EL1 NONSECURE.
*
******************************************************************************/
static inline XStatus XClock_WriteReg(u32 RegAddr, u32 Value)
{
#if defined (__aarch64__) && (EL1_NONSECURE == 1)
XSmc_OutVar RegValue;
RegValue = Xil_Smc(MMIO_WRITE_SMC_FID,
(u64)(RegAddr) | ((u64)(0xFFFFFFFF) << 32),
(u64)Value, 0, 0, 0, 0, 0);
if (0x00 == (RegValue.Arg0 & 0xFFFFFFFF)) {
return XST_SUCCESS;
}
return XST_FAILURE;
#else
Xil_Out32((u32)RegAddr, (u32)Value);
return XST_SUCCESS;
#endif
}
/* Nodes init functions */
void XClock_PllBeginInit(void);
void XClock_MuxBeginInit(void);
void XClock_GateBeginInit(void);
void XClock_DivBeginInit(void);
void XClock_FixedFactorBeginInit(void);
/* Nodes callback register functions */
void XClock_PllRegisterFuncs(void);
void XClock_MuxRegisterFuncs(void);
void XClock_GateRegisterFuncs(void);
void XClock_DivRegisterFuncs(void);
void XClock_FixedFactorRegisterFuncs(void);
/* Function pointer holding update rate functions for nodes */
typedef void (*XClock_UpdateRateFuncPtr)(u8 NodeIdx);
extern XClock_UpdateRateFuncPtr XClock_NodeUpdateRate[XCLOCK_TYPE_MAX];
/* Function pointer holding Get Rate functions for nodes */
typedef XStatus (*XClock_FetchRateFuncPtr)(u8 NodeIdx, XClockRate *GetRate);
extern XClock_FetchRateFuncPtr XClock_NodeGetRate[XCLOCK_TYPE_MAX];
/* Function pointer holding Set Rate functions for nodes */
typedef XStatus (*XClock_SetRateFuncPtr)(u8 NodeIdx, XClockRate ParentRate,
XClockRate Rate, XClockRate *SetRate, u8 DryRun);
extern XClock_SetRateFuncPtr XClock_NodeSetRate[XCLOCK_TYPE_MAX];
/* Function pointer holding parent fetch functions for nodes */
typedef XStatus (*XClock_FetchParentFuncPtr)(XClock_Types *NodeType,
u8 *NodeIdx);
extern XClock_FetchParentFuncPtr XClock_NodeFetchParent[XCLOCK_TYPE_MAX];
/* Function pointer holding database index fetch functions for nodes */
typedef XStatus (*XClock_FetchIdxFuncPtr)(XClock_OutputClks ClockId,
u8 *NodeIdx);
extern XClock_FetchIdxFuncPtr XClock_NodeFetchIdx[XCLOCK_TYPE_MAX];
/* Function pointer holding disable functions for nodes */
typedef XStatus (*XClock_DisableNodeFuncPtr)(u8 NodeIdx);
extern XClock_DisableNodeFuncPtr XClock_NodeDisable[XCLOCK_TYPE_MAX];
/* Function pointer holding Enable functions for nodes */
typedef XStatus (*XClock_EnableNodeFuncPtr)(u8 NodeIdx);
extern XClock_EnableNodeFuncPtr XClock_NodeEnable[XCLOCK_TYPE_MAX];
/* Function pointer holding Init functions for nodes */
typedef void (*XClock_InitClkFuncPtr)(u8 NodeIdx);
extern XClock_InitClkFuncPtr XClock_NodeInit[XCLOCK_TYPE_MAX];
/* Function pointer holding parent set function for mux */
typedef XStatus (*XClock_SetParentFuncPtr)(u8 NodeIdx, u8 SetParentIdx);
extern XClock_SetParentFuncPtr XClock_MuxSetParent;
/* Wrapper functions */
XStatus XClock_EnableClkNode(XClock_Types NodeType, u8 NodeIdx);
XStatus XClock_DisableClkNode(XClock_Types NodeType, u8 NodeIdx);
void XClock_InitClk(XClock_Types NodeType, u8 NodeIdx);
void XClock_UpdateRate(XClock_Types NodeType, u8 NodeIdx);
XClockRate XClock_FetchRate(XClock_Types NodeType, u8 NodeIdx);
/* APIs */
#ifndef SDT
XClockPs_Config *XClock_LookupConfig(u16 DeviceId);
#else
XClockPs_Config *XClock_LookupConfig(u32 BaseAddress);
#endif
XStatus XClock_CfgInitialize(XClock *InstancePtr, XClockPs_Config *ConfigPtr);
XStatus XClock_EnableClock(XClock_OutputClks ClockId);
XStatus XClock_DisableClock(XClock_OutputClks ClockId);
XStatus XClock_GetParent(XClock_OutputClks ClockId,
XClock_Types *NodeType, u8 *NodeIdx);
XStatus XClock_GetRate(XClock_OutputClks ClockId, XClockRate *Rate);
XStatus XClock_SetParent(XClock_OutputClks ClockId, u8 MuxIdx,
u8 SetParentIdx);
XStatus XClock_SetRate(XClock_OutputClks ClockId, XClockRate Rate,
XClockRate *SetRate);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/** @} */
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/xclockps_hw.h
+136
View File
@@ -0,0 +1,136 @@
/******************************************************************************
* Copyright (C) 2018 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/****************************************************************************/
/**
*
* @file xclockps_hw.h
* @addtogroup clockps Overview
* @{
*
* This file contains the hardware details for the System Clock controller.
*
* <pre>
* MODIFICATION HISTORY:
* Ver Who Date Changes
* ----- ------ -------- ---------------------------------------------
* 1.00 cjp 02/09/18 First release
* 1.6 sd 10/30/23 Fix the redefinition of the PSS_REF
* </pre>
*
******************************************************************************/
#ifndef XCLOCK_HW_H /* prevent circular inclusions */
#define XCLOCK_HW_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
/************************** Constant Definitions *****************************/
/* CRL APB register defines */
#ifndef XPAR_PSU_PSS_REF_CLK_FREQ_HZ
#define XPAR_PSU_PSS_REF_CLK_FREQ_HZ 33330000U
#endif
#ifndef XPAR_PSU_CRL_APB_S_AXI_BASEADDR
#define XPAR_PSU_CRL_APB_S_AXI_BASEADDR 0xFF5E0000
#endif
#ifndef XPAR_PSU_IOUSLCR_0_S_AXI_BASEADDR
#define XPAR_PSU_IOUSLCR_0_S_AXI_BASEADDR 0xFF180000
#endif
#ifndef XPAR_PSU_CRF_APB_S_AXI_BASEADDR
#define XPAR_PSU_CRF_APB_S_AXI_BASEADDR 0xFD1A0000
#endif
#define CRL_APB_BASE_ADDR XPAR_PSU_CRL_APB_S_AXI_BASEADDR
#define IOPLL_CTRL (u32)(CRL_APB_BASE_ADDR + 0x20)
#define RPLL_CTRL (u32)(CRL_APB_BASE_ADDR + 0x30)
#define IOPLL_TO_FPD_CTRL (u32)(CRL_APB_BASE_ADDR + 0x44)
#define RPLL_TO_FPD_CTRL (u32)(CRL_APB_BASE_ADDR + 0x48)
#define USB3_DUAL_REF_CTRL (u32)(CRL_APB_BASE_ADDR + 0x4C)
#define GEM0_REF_CTRL (u32)(CRL_APB_BASE_ADDR + 0x50)
#define GEM1_REF_CTRL (u32)(CRL_APB_BASE_ADDR + 0x54)
#define GEM2_REF_CTRL (u32)(CRL_APB_BASE_ADDR + 0x58)
#define GEM3_REF_CTRL (u32)(CRL_APB_BASE_ADDR + 0x5C)
#define USB0_BUS_REF_CTRL (u32)(CRL_APB_BASE_ADDR + 0x60)
#define USB1_BUS_REF_CTRL (u32)(CRL_APB_BASE_ADDR + 0x64)
#define QSPI_REF_CTRL (u32)(CRL_APB_BASE_ADDR + 0x68)
#define SDIO0_REF_CTRL (u32)(CRL_APB_BASE_ADDR + 0x6C)
#define SDIO1_REF_CTRL (u32)(CRL_APB_BASE_ADDR + 0x70)
#define UART0_REF_CTRL (u32)(CRL_APB_BASE_ADDR + 0x74)
#define UART1_REF_CTRL (u32)(CRL_APB_BASE_ADDR + 0x78)
#define SPI0_REF_CTRL (u32)(CRL_APB_BASE_ADDR + 0x7C)
#define SPI1_REF_CTRL (u32)(CRL_APB_BASE_ADDR + 0x80)
#define CAN0_REF_CTRL (u32)(CRL_APB_BASE_ADDR + 0x84)
#define CAN1_REF_CTRL (u32)(CRL_APB_BASE_ADDR + 0x88)
#define CPU_R5_CTRL (u32)(CRL_APB_BASE_ADDR + 0x90)
#define IOU_SWITCH_CTRL (u32)(CRL_APB_BASE_ADDR + 0x9C)
#define CSU_PLL_CTRL (u32)(CRL_APB_BASE_ADDR + 0xA0)
#define PCAP_CTRL (u32)(CRL_APB_BASE_ADDR + 0xA4)
#define LPD_SWITCH_CTRL (u32)(CRL_APB_BASE_ADDR + 0xA8)
#define LPD_LBUS_CTRL (u32)(CRL_APB_BASE_ADDR + 0xAC)
#define DBG_LPD_CTRL (u32)(CRL_APB_BASE_ADDR + 0xB0)
#define NAND_REF_CTRL (u32)(CRL_APB_BASE_ADDR + 0xB4)
#define LPDDMA_REF_CTRL (u32)(CRL_APB_BASE_ADDR + 0xB8)
#define PL0_REF_CTRL (u32)(CRL_APB_BASE_ADDR + 0xC0)
#define PL1_REF_CTRL (u32)(CRL_APB_BASE_ADDR + 0xC4)
#define PL2_REF_CTRL (u32)(CRL_APB_BASE_ADDR + 0xC8)
#define PL3_REF_CTRL (u32)(CRL_APB_BASE_ADDR + 0xCC)
#define GEM_TSU_REF_CTRL (u32)(CRL_APB_BASE_ADDR + 0x100)
#define DLL_REF_CTRL (u32)(CRL_APB_BASE_ADDR + 0x104)
#define PSSYSMON_REF_CTRL (u32)(CRL_APB_BASE_ADDR + 0x108)
#define I2C0_REF_CTRL (u32)(CRL_APB_BASE_ADDR + 0x120)
#define I2C1_REF_CTRL (u32)(CRL_APB_BASE_ADDR + 0x124)
#define TSTMP_REF_CTRL (u32)(CRL_APB_BASE_ADDR + 0x128)
/* CRF APB register defines */
#define CRF_APB_BASE_ADDR XPAR_PSU_CRF_APB_S_AXI_BASEADDR
#define APLL_CTRL (u32)(CRF_APB_BASE_ADDR + 0x20)
#define DPLL_CTRL (u32)(CRF_APB_BASE_ADDR + 0x2C)
#define VPLL_CTRL (u32)(CRF_APB_BASE_ADDR + 0x38)
#define APLL_TO_LPD_CTRL (u32)(CRF_APB_BASE_ADDR + 0x48)
#define PLL_STATUS (u32)(CRF_APB_BASE_ADDR + 0x44)
#define DPLL_TO_LPD_CTRL (u32)(CRF_APB_BASE_ADDR + 0x4C)
#define VPLL_TO_LPD_CTRL (u32)(CRF_APB_BASE_ADDR + 0x50)
#define ACPU_CTRL (u32)(CRF_APB_BASE_ADDR + 0x60)
#define DBG_TRACE_CTRL (u32)(CRF_APB_BASE_ADDR + 0x64)
#define DBG_FPD_CTRL (u32)(CRF_APB_BASE_ADDR + 0x68)
#define DP_VIDEO_REF_CTRL (u32)(CRF_APB_BASE_ADDR + 0x70)
#define DP_AUDIO_REF_CTRL (u32)(CRF_APB_BASE_ADDR + 0x74)
#define DP_STC_REF_CTRL (u32)(CRF_APB_BASE_ADDR + 0x7C)
#define DDR_CTRL (u32)(CRF_APB_BASE_ADDR + 0x80)
#define GPU_REF_CTRL (u32)(CRF_APB_BASE_ADDR + 0x84)
#define SATA_REF_CTRL (u32)(CRF_APB_BASE_ADDR + 0xA0)
#define PCIE_REF_CTRL (u32)(CRF_APB_BASE_ADDR + 0xB4)
#define FPDDMA_REF_CTRL (u32)(CRF_APB_BASE_ADDR + 0xB8)
#define DPDMA_REF_CTRL (u32)(CRF_APB_BASE_ADDR + 0xBC)
#define TOPSW_MAIN_CTRL (u32)(CRF_APB_BASE_ADDR + 0xC0)
#define TOPSW_LSBUS_CTRL (u32)(CRF_APB_BASE_ADDR + 0xC4)
#define GTGREF0_REF_CTRL (u32)(CRF_APB_BASE_ADDR + 0xC8)
#define DBG_TSTMP_CTRL (u32)(CRF_APB_BASE_ADDR + 0xF8)
/* IOU SLCR defines */
#define IOU_SLCR_BASE_ADDR XPAR_PSU_IOUSLCR_0_S_AXI_BASEADDR
#define WDT_CLK_SEL (u32)(IOU_SLCR_BASE_ADDR + 0x300)
#define CAN_CLK_CTRL (u32)(IOU_SLCR_BASE_ADDR + 0x304)
#define GEM_CLK_CTRL (u32)(IOU_SLCR_BASE_ADDR + 0x308)
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/** @} */
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/xcoresightpsdcc.h
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/******************************************************************************
* Copyright (C) 2015 - 2020 Xilinx, Inc. All rights reserved.
* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xcoresightpsdcc.h
* @addtogroup coresightps_dcc Overview
* @{
* @details
*
* CoreSight driver component.
*
* The coresight is a part of debug communication channel (DCC) group. Jtag UART
* for ARM uses DCC. Each ARM core has its own DCC, so one need to select an
* ARM target in XSDB console before running the jtag terminal command. Using the
* coresight driver component, the output stream can be directed to a log file.
*
* @note None.
*
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ----- -------- -----------------------------------------------
* 1.00 kvn 02/14/15 First release
* 1.1 kvn 06/12/15 Add support for Zynq Ultrascale+ MP.
* kvn 08/18/15 Modified Makefile according to compiler changes.
* 1.3 asa 07/01/16 Made changes to ensure that the file does not compile
* for MB BSPs. Instead it throws up a warning. This
* fixes the CR#953056.
* 1.5 sne 01/19/19 Fixed MISRA-C Violations CR#1025101.
* 1.10 mus 10/06/23 Fix compilation error for Microblaze RISC-V processor.
*
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#ifndef XCORESIGHTPSDCC_H /* prevent circular inclusions */
#define XCORESIGHTPSDCC_H /* by using protection macros */
#if ! defined(__MICROBLAZE__) && ! defined(__riscv)
#include <xil_types.h>
void XCoresightPs_DccSendByte(u32 BaseAddress, u8 Data);
u8 XCoresightPs_DccRecvByte(u32 BaseAddress);
#endif
#endif
/** @} */
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/xcpu_cortexa53.h
+23
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@@ -0,0 +1,23 @@
/******************************************************************************
* Copyright (C) 2014 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xcpu_cortexa53.h
* @addtogroup cpu_cortexa53 Overview
* @{
* @details
*
* dummy file
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- ---------------------------------------------------------
* 1.4 ms 04/18/17 Modified tcl file to add suffix U for XPAR_CPU_ID
* parameter of cpu_cortexa53 in xparameters.h
******************************************************************************/
/** @} */
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/xcsudma.h
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/******************************************************************************
* Copyright (c) 2014 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
* @file xcsudma.h
* @addtogroup csuma_api CSUDMA APIs
* @{
* @details
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------ -------- -----------------------------------------------------
* 1.0 vnsld 22/10/14 First release
* 1.1 adk 10/05/16 Fixed CR#951040 race condition in the recv path when
* source and destination points to the same buffer.
* ms 03/17/17 Added readme.txt file in examples folder for doxygen
* generation.
* ms 04/10/17 Modified filename tag in xcsudma_selftest_example.c to
* include the file in doxygen examples.
* 1.2 adk 11/22/17 Added peripheral test app support for CSUDMA driver.
* 1.4 adk 04/12/17 Added support for PMC DMA.
* adk 09/03/18 Added new API XCsuDma_64BitTransfer() useful for 64-bit
* dma transfers through PMU processor(CR#996201).
* adk 25/06/18 Move CRP and PMC Global address defines to
* xparameters_ps.h file(CR#1002035).
* adk 08/08/18 Added new API XCsuDma_WaitForDoneTimeout() useful for
* polling dma transfer done.
* adk 28/08/18 Fixed misra-c required standard violations..
* Rama 02/26/19 Fixed IAR issue by changing
* "XCsuDma_WaitForDoneTimeout" to function
* arc 03/26/19 Fixed MISRA-C violations.
* 1.7 hk 08/03/20 Reorganize transfer function to accommodate all
* processors and cache functionality.
* 1.7 sk 08/26/20 Fix MISRA-C violations.
* 1.8 nsk 12/14/20 Updated the tcl to not to use the instance names.
* 1.9 sk 02/11/21 Add description for the dmatype macros.
* 1.9 sk 02/11/21 Remove the prototype of undefined functions.
* 1.11 sk 03/03/22 Move addtogroup to starting of the file and replace
* driver version with Overview.
* 1.11 sk 03/03/22 Update overview section based on review comments.
* 1.11 adk 03/15/22 Fixed syntax errors in csudma_tapp.tcl file, when stdout
* is configured as none.
* 1.14 ab 01/16/23 Added Xil_PlmStubHandler() to XCsuDma_WaitForDone.
* 1.14 ab 01/18/23 Added byte-aligned transfer API for VERSAL_NET devices.
* 1.14 adk 04/14/23 Added support for system device-tree flow.
* </pre>
*
******************************************************************************/
#ifndef XCSUDMA_H_
#define XCSUDMA_H_ /**< Prevent circular inclusions
* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xcsudma_hw.h"
#include "xil_types.h"
#include "xil_assert.h"
#include "xstatus.h"
#include "xil_cache.h"
#include "sleep.h"
#include "xil_util.h"
/************************** Constant Definitions *****************************/
/**
* This typedef contains CSU_DMA Channel Types.
*/
typedef enum {
XCSUDMA_SRC_CHANNEL = 0U, /**< Source Channel of CSU_DMA */
XCSUDMA_DST_CHANNEL /**< Destination Channel of CSU_DMA */
}XCsuDma_Channel;
/*@}*/
/**
* This typedef contains CSU_DMA Pause Types.
*/
typedef enum {
XCSUDMA_PAUSE_MEMORY, /**< Pauses memory data transfer
* to/from CSU_DMA */
XCSUDMA_PAUSE_STREAM, /**< Pauses stream data transfer
* to/from CSU_DMA */
}XCsuDma_PauseType;
/*@}*/
/** @name Ranges of Size
* @{
*/
#ifdef VERSAL_NET
#define XCSUDMA_SIZE_MAX 0x1FFFFFFFU /**< Maximum allowed no of bytes */
#else
#define XCSUDMA_SIZE_MAX 0x07FFFFFFU /**< Maximum allowed no of words */
#endif
#define XCSUDMA_DMATYPEIS_CSUDMA 0U /**< DMA is CSUDMA */
#define XCSUDMA_DMATYPEIS_PMCDMA0 1U /**< DMA is PMCDMA0 */
#define XCSUDMA_DMATYPEIS_PMCDMA1 2U /**< DMA is PMCDMA1 */
/*@}*/
/***************** Macros (Inline Functions) Definitions *********************/
/*****************************************************************************/
/**
*
* This function resets the CSU_DMA core.
*
* @return None.
*
* @note None.
* C-style signature:
* void XCsuDma_Reset()
*
******************************************************************************/
#define XCsuDma_Reset() \
Xil_Out32(((u32)(XCSU_BASEADDRESS) + (u32)(XCSU_DMA_RESET_OFFSET)), \
(u32)(XCSUDMA_RESET_SET_MASK)); \
Xil_Out32(((u32)(XCSU_BASEADDRESS) + (u32)(XCSU_DMA_RESET_OFFSET)), \
(u32)(XCSUDMA_RESET_UNSET_MASK));
#if defined (versal)
/*****************************************************************************/
/**
*
* This function resets the PMC_DMA core.
*
* @param DmaType Type of DMA (PMCDMA0 or PMCDMA1).
*
* @return None.
*
* @note C-style signature:
* void XCsuDma_PmcReset(u8 DmaType)
*
******************************************************************************/
#define XCsuDma_PmcReset(DmaType) \
Xil_Out32(((u32)(XPS_CRP_BASEADDRESS) + (u32)(XCRP_PMCDMA_RESET_OFFSET)), \
(u32)(XCSUDMA_RESET_SET_MASK << (DmaType - 1))); \
Xil_Out32(((u32)(XPS_CRP_BASEADDRESS) + (u32)(XCRP_PMCDMA_RESET_OFFSET)), \
(u32)(XCSUDMA_RESET_UNSET_MASK << (DmaType - 1)));
#endif
/*****************************************************************************/
/**
* This function will be in busy while loop until the data transfer is
* completed.
*
* @param InstancePtr Pointer to XCsuDma instance to be worked on.
* @param Channel Represents the type of channel either it is Source or
* Destination.
* Source channel - XCSUDMA_SRC_CHANNEL
* Destination Channel - XCSUDMA_DST_CHANNEL
*
* @return None.
*
* @note This function should be called after XCsuDma_Transfer in polled
* mode to wait until the data gets transfered completely.
* C-style signature:
* void XCsuDma_WaitForDone(XCsuDma *InstancePtr,
* XCsuDma_Channel Channel)
*
******************************************************************************/
#ifdef VERSAL_PLM
#define XCsuDma_WaitForDone(InstancePtr,Channel) \
while((XCsuDma_ReadReg(((InstancePtr)->Config.BaseAddress), \
((u32)(XCSUDMA_I_STS_OFFSET) + \
((u32)(Channel) * (u32)(XCSUDMA_OFFSET_DIFF)))) & \
(u32)(XCSUDMA_IXR_DONE_MASK)) != (XCSUDMA_IXR_DONE_MASK)) { \
Xil_PlmStubHandler(); \
}
#else
#define XCsuDma_WaitForDone(InstancePtr,Channel) \
while((XCsuDma_ReadReg(((InstancePtr)->Config.BaseAddress), \
((u32)(XCSUDMA_I_STS_OFFSET) + \
((u32)(Channel) * (u32)(XCSUDMA_OFFSET_DIFF)))) & \
(u32)(XCSUDMA_IXR_DONE_MASK)) != (XCSUDMA_IXR_DONE_MASK))
#endif
/*****************************************************************************/
/**
*
* This function returns the number of completed SRC/DST DMA transfers that
* have not been acknowledged by software based on the channel selection.
*
* @param InstancePtr Pointer to XCsuDma instance to be worked on.
* @param Channel Type of channel.
* Source channel - XCSUDMA_SRC_CHANNEL
* Destination Channel - XCSUDMA_DST_CHANNEL
*
* @return Count is number of completed DMA transfers but not acknowledged
* (Range is 0 to 7).
* - 000 - All finished transfers have been acknowledged.
* - Count - Count number of finished transfers are still
* outstanding.
*
* @note C-style signature:
* u8 XCsuDma_GetDoneCount(XCsuDma *InstancePtr,
* XCsuDma_Channel Channel)
*
******************************************************************************/
#define XCsuDma_GetDoneCount(InstancePtr, Channel) \
((XCsuDma_ReadReg(((InstancePtr)->Config.BaseAddress), \
((u32)(XCSUDMA_STS_OFFSET) + \
((u32)(Channel) * (u32)(XCSUDMA_OFFSET_DIFF)))) & \
(u32)(XCSUDMA_STS_DONE_CNT_MASK)) >> \
(u32)(XCSUDMA_STS_DONE_CNT_SHIFT))
/*****************************************************************************/
/**
*
* This function returns the current SRC/DST FIFO level in 32 bit words of the
* selected channel
*
* @param InstancePtr Pointer to XCsuDma instance to be worked on.
* @param Channel Type of channel
* Source channel - XCSUDMA_SRC_CHANNEL
* Destination Channel - XCSUDMA_DST_CHANNEL
*
* @return FIFO level. (Range is 0 to 128)
* - 0 Indicates empty
* - Any number 1 to 128 indicates the number of entries in FIFO.
*
* @note C-style signature:
* u8 XCsuDma_GetFIFOLevel(XCsuDma *InstancePtr,
* XCsuDma_Channel Channel)
*
******************************************************************************/
#define XCsuDma_GetFIFOLevel(InstancePtr, Channel) \
((XCsuDma_ReadReg(((InstancePtr)->Config.BaseAddress), \
((u32)(XCSUDMA_STS_OFFSET) + \
((u32)(Channel) * (u32)(XCSUDMA_OFFSET_DIFF)))) & \
(u32)(XCSUDMA_STS_FIFO_LEVEL_MASK)) >> \
(u32)(XCSUDMA_STS_FIFO_LEVEL_SHIFT))
/*****************************************************************************/
/**
*
* This function returns the current number of read(src)/write(dst) outstanding
* commands based on the type of channel selected.
*
* @param InstancePtr Pointer to XCsuDma instance to be worked on.
* @param Channel Type of channel
* Source channel - XCSUDMA_SRC_CHANNEL
* Destination Channel - XCSUDMA_DST_CHANNEL
*
* @return Count of outstanding commands. (Range is 0 to 9).
*
* @note C-style signature:
* u8 XCsuDma_GetWROutstandCount(XCsuDma *InstancePtr,
* XCsuDma_Channel Channel)
*
******************************************************************************/
#define XCsuDma_GetWROutstandCount(InstancePtr, Channel) \
((XCsuDma_ReadReg(((InstancePtr)->Config.BaseAddress), \
((u32)(XCSUDMA_STS_OFFSET) + \
((u32)(Channel) * (u32)(XCSUDMA_OFFSET_DIFF)))) & \
(u32)(XCUSDMA_STS_OUTSTDG_MASK)) >> \
(u32)(XCUSDMA_STS_OUTSTDG_SHIFT))
/*****************************************************************************/
/**
*
* This function returns the status of Channel either it is busy or not.
*
* @param InstancePtr Pointer to XCsuDma instance to be worked on.
* @param Channel Type of channel
* Source channel - XCSUDMA_SRC_CHANNEL
* Destination Channel - XCSUDMA_DST_CHANNEL
*
* @return Returns the current status of the core.
* - TRUE represents core is currently busy.
* - FALSE represents core is not involved in any transfers.
*
* @note C-style signature:
* s32 XCsuDma_IsBusy(XCsuDma *InstancePtr, XCsuDma_Channel Channel)
*
******************************************************************************/
#define XCsuDma_IsBusy(InstancePtr, Channel) \
(((XCsuDma_ReadReg(((InstancePtr)->Config.BaseAddress), \
((u32)(XCSUDMA_STS_OFFSET) + \
((u32)(Channel) * (u32)(XCSUDMA_OFFSET_DIFF)))) & \
(u32)(XCSUDMA_STS_BUSY_MASK)) == (XCSUDMA_STS_BUSY_MASK)) ? \
TRUE : FALSE)
/**************************** Type Definitions *******************************/
/**
* This typedef contains configuration information for a CSU_DMA core.
* Each CSU_DMA core should have an associated configuration structure.
*/
typedef struct {
#ifndef SDT
u16 DeviceId; /**< DeviceId is the unique ID of the
* device */
#else
char *Name; /**< Unique name of the device */
#endif
UINTPTR BaseAddress; /**< BaseAddress is the physical base address
* of the device's registers */
u8 DmaType; /**< DMA type
* 0 -- CSUDMA
* 1 -- PMC DMA 0
* 2 -- PMC DMA 1 */
#ifdef SDT
u32 IntrId; /** Bits[11:0] Interrupt-id Bits[15:12]
* trigger type and level flags */
UINTPTR IntrParent; /** Bit[0] Interrupt parent type Bit[64/32:1]
* Parent base address */
#endif
} XCsuDma_Config;
/******************************************************************************/
/**
*
* The XCsuDma driver instance data structure. A pointer to an instance data
* structure is passed around by functions to refer to a specific driver
* instance.
*/
typedef struct {
XCsuDma_Config Config; /**< Hardware configuration */
u32 IsReady; /**< Device and the driver instance
* are initialized */
}XCsuDma;
/******************************************************************************/
/**
* This typedef contains all the configuration feilds which must be set
* before the start of the data transfer. All these feilds of CSU_DMA can be
* configured by using XCsuDma_SetConfig API.
*/
typedef struct {
u8 SssFifoThesh; /**< SSS FIFO threshold value */
u8 ApbErr; /**< ABP invalid access error */
u8 EndianType; /**< Type of endianess */
u8 AxiBurstType; /**< Type of AXI bus */
u32 TimeoutValue; /**< Time out value */
u8 FifoThresh; /**< FIFO threshold value */
u8 Acache; /**< AXI CACHE selection */
u8 RouteBit; /**< Selection of Route */
u8 TimeoutEn; /**< Enable of time out counters */
u16 TimeoutPre; /**< Pre scaler value */
u8 MaxOutCmds; /**< Maximum number of outstanding
* commands */
}XCsuDma_Configure;
/*****************************************************************************/
/************************** Variable Definitions *****************************/
#ifndef SDT
extern XCsuDma_Config XCsuDma_ConfigTable[XPAR_XCSUDMA_NUM_INSTANCES];
#else
extern XCsuDma_Config XCsuDma_ConfigTable[];
#endif
/************************** Function Prototypes ******************************/
#ifndef SDT
XCsuDma_Config *XCsuDma_LookupConfig(u16 DeviceId);
#else
XCsuDma_Config *XCsuDma_LookupConfig(UINTPTR BaseAddress);
#endif
s32 XCsuDma_CfgInitialize(XCsuDma *InstancePtr, XCsuDma_Config *CfgPtr,
UINTPTR EffectiveAddr);
void XCsuDma_Transfer(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
u64 Addr, u32 Size, u8 EnDataLast);
void XCsuDma_64BitTransfer(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
u32 AddrLow, u32 AddrHigh, u32 Size, u8 EnDataLast);
#ifdef VERSAL_NET
void XCsuDma_ByteAlignedTransfer(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
u64 Addr, u32 Size, u8 EnDataLast);
#endif
u64 XCsuDma_GetAddr(XCsuDma *InstancePtr, XCsuDma_Channel Channel);
u32 XCsuDma_GetSize(XCsuDma *InstancePtr, XCsuDma_Channel Channel);
void XCsuDma_Pause(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
XCsuDma_PauseType Type);
s32 XCsuDma_IsPaused(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
XCsuDma_PauseType Type);
void XCsuDma_Resume(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
XCsuDma_PauseType Type);
u32 XCsuDma_GetCheckSum(XCsuDma *InstancePtr);
void XCsuDma_ClearCheckSum(XCsuDma *InstancePtr);
void XCsuDma_SetConfig(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
XCsuDma_Configure *ConfigurValues);
void XCsuDma_GetConfig(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
XCsuDma_Configure *ConfigurValues);
u32 XCsuDma_WaitForDoneTimeout(XCsuDma *InstancePtr, XCsuDma_Channel Channel);
/* Interrupt related APIs */
u32 XCsuDma_IntrGetStatus(XCsuDma *InstancePtr, XCsuDma_Channel Channel);
void XCsuDma_IntrClear(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
u32 Mask);
void XCsuDma_EnableIntr(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
u32 Mask);
void XCsuDma_DisableIntr(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
u32 Mask);
u32 XCsuDma_GetIntrMask(XCsuDma *InstancePtr, XCsuDma_Channel Channel);
s32 XCsuDma_SelfTest(XCsuDma *InstancePtr);
/******************************************************************************/
#ifdef __cplusplus
}
#endif
#endif /* End of protection macro */
/** @} */
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/xcsudma_hw.h
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@@ -0,0 +1,329 @@
/******************************************************************************
* Copyright (C) 2014 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xcsudma_hw.h
* @addtogroup csuma_api CSUDMA APIs
* @{
*
* The xcsudma_hw.h header file contains identifiers and register-level driver
* functions (or macros) that can be used to access the CSU_DMA core.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------ -------- ------------------------------------------------------
* 1.0 vnsld 22/10/14 First release
* 1.9 sk 02/11/21 Add description for XPS_CRP_BASEADDRESS and
* XCSUDMA_DONE_TIMEOUT_VAL macros.
* 1.11 sk 03/03/22 Replace driver version in addtogroup with Overview.
* 1.11 sk 03/03/22 Update Overview section based on review comments.
* 1.11 sk 03/03/22 Add cond INTERNAL to avoid internal macros.
* 1.12 sk 03/03/22 Added support for VERSAL NET.
* </pre>
*
******************************************************************************/
#ifndef XCSUDMA_HW_H_
#define XCSUDMA_HW_H_ /**< Prevent circular inclusions
* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_io.h"
#ifndef SDT
#include "xparameters.h"
#endif
/************************** Constant Definitions *****************************/
/** @name Registers offsets
* @{
*/
#define XCSUDMA_ADDR_OFFSET 0x000U /**< Address Register Offset */
#define XCSUDMA_SIZE_OFFSET 0x004U /**< Size Register Offset */
#define XCSUDMA_STS_OFFSET 0x008U /**< Status Register Offset */
#define XCSUDMA_CTRL_OFFSET 0x00CU /**< Control Register Offset */
#define XCSUDMA_I_STS_OFFSET 0x014U /**< Interrupt Status Register
* Offset */
/** @cond INTERNAL */
#define XCSUDMA_CRC_OFFSET 0x010U /**< CheckSum Register Offset */
#define XCSUDMA_I_EN_OFFSET 0x018U /**< Interrupt Enable Register
* Offset */
#define XCSUDMA_I_DIS_OFFSET 0x01CU /**< Interrupt Disable Register
* Offset */
#define XCSUDMA_I_MASK_OFFSET 0x020U /**< Interrupt Mask Register Offset */
#define XCSUDMA_CTRL2_OFFSET 0x024U /**< Interrupt Control Register 2
* Offset */
#define XCSUDMA_ADDR_MSB_OFFSET 0x028U /**< Address's MSB Register Offset */
#define XCSUDMA_SAFETY_CHK_OFFSET 0xFF8U /**< Safety Check Field Offset */
#define XCSUDMA_FUTURE_ECO_OFFSET 0xFFCU /**< Future potential ECO Offset */
/** @endcond */
/*@}*/
/** @cond INTERNAL */
/** @name CSU Base address, CRP Base Address and CSU_DMA reset offset
* @{
*/
#define XCSU_BASEADDRESS 0xFFCA0000U
/**< CSU Base Address */
#define XCSU_DMA_RESET_OFFSET 0x0000000CU /**< CSU_DMA Reset offset */
#ifndef XPS_CRP_BASEADDRESS
#define XPS_CRP_BASEADDRESS 0xF1260000U /**< CRP Base Address */
#endif
/*@}*/
/** @name CRP PMC_DMA reset offset
* @{
*/
#define XCRP_PMCDMA_RESET_OFFSET 0x00000328U /**< PMC_DMA Reset offset */
/*@}*/
/** @name CSU_DMA Reset register bit masks
* @{
*/
#define XCSUDMA_RESET_SET_MASK 0x00000001U /**< Reset set mask */
#define XCSUDMA_RESET_UNSET_MASK 0x00000000U /**< Reset unset mask*/
/*@}*/
/** @name Offset difference for Source and destination
* @{
*/
#define XCSUDMA_OFFSET_DIFF 0x00000800U /**< Offset difference for
* source and
* destination channels */
/*@}*/
/** @name Address register bit masks
* @{
*/
#if defined (VERSAL_NET)
#define XCSUDMA_ADDR_MASK 0xFFFFFFFFU /**< Address mask */
#else
#define XCSUDMA_ADDR_MASK 0xFFFFFFFCU /**< Address mask */
#endif
#define XCSUDMA_ADDR_LSB_MASK 0x00000003U /**< Address alignment check
* mask */
/*@}*/
/** @endcond */
/** @name Size register bit masks and shifts
* @{
*/
#define XCSUDMA_SIZE_MASK 0x1FFFFFFCU /**< Mask for size */
#if defined (VERSAL_NET)
#define XCSUDMA_LAST_WORD_MASK 0x20000000U /**< Last word check bit mask*/
#define XCSUDMA_SIZE_SHIFT 0U /**< Shift for size */
#else
#define XCSUDMA_LAST_WORD_MASK 0x00000001U /**< Last word check bit mask*/
#define XCSUDMA_SIZE_SHIFT 2U /**< Shift for size */
#endif
/*@}*/
/** @cond INTERNAL */
/** @name Status register bit masks and shifts
* @{
*/
#define XCSUDMA_STS_DONE_CNT_MASK 0x0000E000U /**< Count done mask */
#define XCSUDMA_STS_FIFO_LEVEL_MASK 0x00001FE0U /**< FIFO level mask */
#define XCUSDMA_STS_OUTSTDG_MASK 0x0000001EU /**< No.of outstanding
* read/write
* commands mask */
#define XCSUDMA_STS_BUSY_MASK 0x00000001U /**< Busy mask */
#define XCSUDMA_STS_DONE_CNT_SHIFT 13U /**< Shift for Count
* done */
#define XCSUDMA_STS_FIFO_LEVEL_SHIFT 5U /**< Shift for FIFO
* level */
#define XCUSDMA_STS_OUTSTDG_SHIFT 1U /**< Shift for No.of
* outstanding
* read/write
* commands */
/*@}*/
/** @name Control register bit masks and shifts
* @{
*/
#define XCSUDMA_CTRL_SSS_FIFOTHRESH_MASK 0xFE000000U /**< SSS FIFO threshold
* value mask */
#define XCSUDMA_CTRL_APB_ERR_MASK 0x01000000U /**< APB register
* access error
* mask */
#define XCSUDMA_CTRL_ENDIAN_MASK 0x00800000U /**< Endianess mask */
#define XCSUDMA_CTRL_BURST_MASK 0x00400000U /**< AXI burst type
* mask */
#define XCSUDMA_CTRL_TIMEOUT_MASK 0x003FFC00U /**< Time out value
* mask */
#define XCSUDMA_CTRL_FIFO_THRESH_MASK 0x000003FCU /**< FIFO threshold
* mask */
#define XCSUDMA_CTRL_PAUSE_MEM_MASK 0x00000001U /**< Memory pause
* mask */
#define XCSUDMA_CTRL_PAUSE_STRM_MASK 0x00000002U /**< Stream pause
* mask */
#define XCSUDMA_CTRL_SSS_FIFOTHRESH_SHIFT 25U /**< SSS FIFO threshold
* shift */
#define XCSUDMA_CTRL_APB_ERR_SHIFT 24U /**< APB error shift */
#define XCSUDMA_CTRL_ENDIAN_SHIFT 23U /**< Endianess shift */
#define XCSUDMA_CTRL_BURST_SHIFT 22U /**< AXI burst type
* shift */
#define XCSUDMA_CTRL_TIMEOUT_SHIFT 10U /**< Time out value
* shift */
#define XCSUDMA_CTRL_FIFO_THRESH_SHIFT 2U /**< FIFO thresh
* shift */
/*@}*/
/** @name CheckSum register bit masks
* @{
*/
#define XCSUDMA_CRC_RESET_MASK 0x00000000U /**< Mask to reset
* value of
* check sum */
/*@}*/
/** @endcond */
/** @name Interrupt Enable/Disable/Mask/Status registers bit masks
* @{
*/
#define XCSUDMA_IXR_FIFO_OVERFLOW_MASK 0x00000001U /**< FIFO overflow
* mask, it is valid
* only to Destination
* Channel */
#define XCSUDMA_IXR_INVALID_APB_MASK 0x00000040U /**< Invalid APB access
* mask */
#define XCSUDMA_IXR_FIFO_THRESHHIT_MASK 0x00000020U /**< FIFO threshold hit
* indicator mask */
#define XCSUDMA_IXR_TIMEOUT_MEM_MASK 0x00000010U /**< Time out counter
* expired to access
* memory mask */
#define XCSUDMA_IXR_TIMEOUT_STRM_MASK 0x00000008U /**< Time out counter
* expired to access
* stream mask */
#define XCSUDMA_IXR_AXI_WRERR_MASK 0x00000004U /**< AXI Read/Write
* error mask */
#define XCSUDMA_IXR_DONE_MASK 0x00000002U /**< Done mask */
#define XCSUDMA_IXR_MEM_DONE_MASK 0x00000001U /**< Memory done
* mask, it is valid
* only for source
* channel*/
#define XCSUDMA_IXR_SRC_MASK 0x0000007FU
/**< ((XCSUDMA_IXR_INVALID_APB_MASK)|
(XCSUDMA_IXR_FIFO_THRESHHIT_MASK) |
(XCSUDMA_IXR_TIMEOUT_MEM_MASK) |
(XCSUDMA_IXR_TIMEOUT_STRM_MASK) |
(XCSUDMA_IXR_AXI_WRERR_MASK) |
(XCSUDMA_IXR_DONE_MASK) |
(XCSUDMA_IXR_MEM_DONE_MASK)) */
/**< All interrupt mask
* for source */
#define XCSUDMA_IXR_DST_MASK 0x000000FEU
/**< ((XCSUDMA_IXR_FIFO_OVERFLOW_MASK) |
(XCSUDMA_IXR_INVALID_APB_MASK) |
(XCSUDMA_IXR_FIFO_THRESHHIT_MASK) |
(XCSUDMA_IXR_TIMEOUT_MEM_MASK) |
(XCSUDMA_IXR_TIMEOUT_STRM_MASK) |
(XCSUDMA_IXR_AXI_WRERR_MASK) |
(XCSUDMA_IXR_DONE_MASK)) */
/**< All interrupt mask
* for destination */
/*@}*/
/** @cond INTERNAL */
/** @name Control register 2 bit masks and shifts
* @{
*/
#define XCSUDMA_CTRL2_RESERVED_MASK 0x083F0000U /**< Reserved bits
* mask */
#define XCSUDMA_CTRL2_ACACHE_MASK 0X07000000U /**< AXI CACHE mask */
#define XCSUDMA_CTRL2_ROUTE_MASK 0x00800000U /**< Route mask */
#define XCSUDMA_CTRL2_TIMEOUT_EN_MASK 0x00400000U /**< Time out counters
* enable mask */
#define XCSUDMA_CTRL2_TIMEOUT_PRE_MASK 0x0000FFF0U /**< Time out pre
* mask */
#define XCSUDMA_CTRL2_MAXCMDS_MASK 0x0000000FU /**< Maximum commands
* mask */
#define XCSUDMA_CTRL2_RESET_MASK 0x0000FFF8U /**< Reset mask */
#define XCSUDMA_CTRL2_ACACHE_SHIFT 24U /**< Shift for
* AXI R/W CACHE */
#define XCSUDMA_CTRL2_ROUTE_SHIFT 23U /**< Shift for route */
#define XCSUDMA_CTRL2_TIMEOUT_EN_SHIFT 22U /**< Shift for Timeout
* enable feild */
#define XCSUDMA_CTRL2_TIMEOUT_PRE_SHIFT 4U /**< Shift for Timeout
* pre feild */
/*@}*/
/** @name MSB Address register bit masks and shifts
* @{
*/
#define XCSUDMA_MSB_ADDR_MASK 0x0001FFFFU /**< MSB bits of address
* mask */
#define XCSUDMA_MSB_ADDR_SHIFT 32U /**< Shift for MSB bits of
* address */
/*@}*/
/** @endcond */
/** @name Software done timeout value
* @{
*/
#define XCSUDMA_DONE_TIMEOUT_VAL 300000000U /**< SW timeout loop value
* for transfer completion */
/*@}*/
/***************** Macros (Inline Functions) Definitions *********************/
#define XCsuDma_In32 Xil_In32 /**< Input operation */
#define XCsuDma_Out32 Xil_Out32 /**< Output operation */
/*****************************************************************************/
/**
*
* This macro reads the given register.
*
* @param BaseAddress Base address of the CSU_DMA core.
* @param RegOffset Register offset of the register.
*
* @return The 32-bit value of the register.
*
* @note C-style signature:
* u32 XCsuDma_ReadReg(u32 BaseAddress, u32 RegOffset)
*
******************************************************************************/
#define XCsuDma_ReadReg(BaseAddress, RegOffset) \
XCsuDma_In32((BaseAddress) + (u32)(RegOffset))
/*****************************************************************************/
/**
*
* This macro writes the value into the given register.
*
* @param BaseAddress Base address of the CSU_DMA core.
* @param RegOffset Register offset of the register.
* @param Data 32-bit value to write to the register.
*
* @return None.
*
* @note C-style signature:
* void XCsuDma_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
*
******************************************************************************/
#define XCsuDma_WriteReg(BaseAddress, RegOffset, Data) \
XCsuDma_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data))
#ifdef __cplusplus
}
#endif
#endif /* End of protection macro */
/** @} */
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/xddr_xmpu0_cfg.h
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dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/xddrcpsu.h
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/*******************************************************************************
* Copyright (C) 2016 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
*******************************************************************************/
/******************************************************************************/
/**
*
* @file xddcrpsu.h
* @addtogroup ddrcpsu Overview
* @{
* @details
*
* The Xilinx DdrcPsu driver. This driver supports the Xilinx ddrcpsu
* IP core.
*
* @note None.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.0 ssc 04/28/16 First Release.
* 1.1 adk 04/08/16 Export DDR freq to xparameters.h file.
* 1.5 ht 08/03/23 Added support for system device-tree flow.
*
* </pre>
*
*******************************************************************************/
#ifndef XDDRCPS_H_
/* Prevent circular inclusions by using protection macros. */
#define XDDRCPS_H_
#ifdef __cplusplus
extern "C" {
#endif
/******************************* Include Files ********************************/
#ifdef SDT
#include "xil_types.h"
#include "xil_assert.h"
#include "xstatus.h"
/**************************** Type Definitions *******************************/
typedef struct {
char *Name;
UINTPTR BaseAddress;
u8 HasEccEn;
u32 InputClockFreq;
u8 AddrMapping;
u32 DdrFreq; /* DDR Freq in Hz */
u32 VideoBufSize;
u32 BrcMapping;
u8 HasDynamicDDrEn;
u8 Memtype;
u8 MemAddrMap;
u32 DataMask_Dbi;
u32 AddressMirror;
u32 Secondclk;
u32 Parity;
u32 PwrDnEn;
u32 ClockStopEn;
u32 LpAsr;
u32 TRefMode;
u32 Fgrm;
u32 SelfRefAbort;
u32 TRefRange;
} XDdrcpsu_Config;
typedef struct {
XDdrcpsu_Config Config; /**< Configuration structure */
u32 IsReady; /**< Device is initialized and ready */
} XDdrcPsu;
/************************** Function Prototypes ******************************/
XDdrcpsu_Config *XDdrcPsu_LookupConfig(UINTPTR BaseAddress);
s32 XDdrcPsu_CfgInitialize(XDdrcPsu *InstancePtr, XDdrcpsu_Config *CfgPtr);
#endif
#ifdef __cplusplus
}
#endif
#endif /* XDDRCPS_H_ */
/** @} */
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/xdebug.h
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/******************************************************************************
* Copyright (C) 2002 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef XDEBUG
#define XDEBUG
#ifdef __cplusplus
extern "C" {
#endif
#include "xil_printf.h"
#if defined(DEBUG) && !defined(NDEBUG)
#ifndef XDEBUG_WARNING
#define XDEBUG_WARNING
#warning DEBUG is enabled
#endif
int printf(const char *format, ...);
#define XDBG_DEBUG_ERROR 0x00000001U /* error condition messages */
#define XDBG_DEBUG_GENERAL 0x00000002U /* general debug messages */
#define XDBG_DEBUG_ALL 0xFFFFFFFFU /* all debugging data */
#define XDBG_DEBUG_FIFO_REG 0x00000100U /* display register reads/writes */
#define XDBG_DEBUG_FIFO_RX 0x00000101U /* receive debug messages */
#define XDBG_DEBUG_FIFO_TX 0x00000102U /* transmit debug messages */
#define XDBG_DEBUG_FIFO_ALL 0x0000010FU /* all fifo debug messages */
#define XDBG_DEBUG_TEMAC_REG 0x00000400U /* display register reads/writes */
#define XDBG_DEBUG_TEMAC_RX 0x00000401U /* receive debug messages */
#define XDBG_DEBUG_TEMAC_TX 0x00000402U /* transmit debug messages */
#define XDBG_DEBUG_TEMAC_ALL 0x0000040FU /* all temac debug messages */
#define XDBG_DEBUG_TEMAC_ADPT_RX 0x00000800U /* receive debug messages */
#define XDBG_DEBUG_TEMAC_ADPT_TX 0x00000801U /* transmit debug messages */
#define XDBG_DEBUG_TEMAC_ADPT_IOCTL 0x00000802U /* ioctl debug messages */
#define XDBG_DEBUG_TEMAC_ADPT_MISC 0x00000803U /* debug msg for other routines */
#define XDBG_DEBUG_TEMAC_ADPT_ALL 0x0000080FU /* all temac adapter debug messages */
#define xdbg_current_types (XDBG_DEBUG_GENERAL | XDBG_DEBUG_ERROR | XDBG_DEBUG_TEMAC_REG | XDBG_DEBUG_FIFO_RX | XDBG_DEBUG_FIFO_TX | XDBG_DEBUG_FIFO_REG)
#define xdbg_stmnt(x) x
/* In VxWorks, if _WRS_GNU_VAR_MACROS is defined, special syntax is needed for
* macros that accept variable number of arguments
*/
#if defined(XENV_VXWORKS) && defined(_WRS_GNU_VAR_MACROS)
#define xdbg_printf(type, args...) (((type) & xdbg_current_types) ? printf (## args) : 0)
#else /* ANSI Syntax */
#define xdbg_printf(type, ...) (((type) & xdbg_current_types) ? printf (__VA_ARGS__) : 0)
#endif
#define xdbg_exception_printf(type, ...) (((type) & xdbg_current_types) ? xil_printf (__VA_ARGS__) : 0)
#else /* defined(DEBUG) && !defined(NDEBUG) */
#define xdbg_stmnt(x) /**< Debug statement */
/* See VxWorks comments above */
#if defined(XENV_VXWORKS) && defined(_WRS_GNU_VAR_MACROS)
#define xdbg_printf(type, args...)
#else /* ANSI Syntax */
#define xdbg_printf(...) /**< Debug printf */
#endif
#endif /* defined(DEBUG) && !defined(NDEBUG) */
#ifdef __cplusplus
}
#endif
#endif /* XDEBUG */
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/xemacps.h
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/******************************************************************************
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2024 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/****************************************************************************/
/**
*
* @file xemacps.h
* @addtogroup emacps Overview
* @{
* @details
*
* The Xilinx Embedded Processor Block Ethernet driver.
*
* For a full description of XEMACPS features, please see the hardware spec.
* This driver supports the following features:
* - Memory mapped access to host interface registers
* - Statistics counter registers for RMON/MIB
* - API for interrupt driven frame transfers for hardware configured DMA
* - Virtual memory support
* - Unicast, broadcast, and multicast receive address filtering
* - Full and half duplex operation
* - Automatic PAD & FCS insertion and stripping
* - Flow control
* - Support up to four 48bit addresses
* - Address checking for four specific 48bit addresses
* - VLAN frame support
* - Pause frame support
* - Large frame support up to 1536 bytes
* - Checksum offload
*
* <b>Driver Description</b>
*
* The device driver enables higher layer software (e.g., an application) to
* communicate to the XEmacPs. The driver handles transmission and reception
* of Ethernet frames, as well as configuration and control. No pre or post
* processing of frame data is performed. The driver does not validate the
* contents of an incoming frame in addition to what has already occurred in
* hardware.
* A single device driver can support multiple devices even when those devices
* have significantly different configurations.
*
* <b>Initialization & Configuration</b>
*
* The XEmacPs_Config structure is used by the driver to configure itself.
* This configuration structure is typically created by the tool-chain based
* on hardware build properties.
*
* The driver instance can be initialized in
*
* - XEmacPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddress): Uses a
* configuration structure provided by the caller. If running in a system
* with address translation, the provided virtual memory base address
* replaces the physical address present in the configuration structure.
*
* The device supports DMA only as current development plan. No FIFO mode is
* supported. The driver expects to start the DMA channels and expects that
* the user has set up the buffer descriptor lists.
*
* <b>Interrupts and Asynchronous Callbacks</b>
*
* The driver has no dependencies on the interrupt controller. When an
* interrupt occurs, the handler will perform a small amount of
* housekeeping work, determine the source of the interrupt, and call the
* appropriate callback function. All callbacks are registered by the user
* level application.
*
* <b>Virtual Memory</b>
*
* All virtual to physical memory mappings must occur prior to accessing the
* driver API.
*
* For DMA transactions, user buffers supplied to the driver must be in terms
* of their physical address.
*
* <b>DMA</b>
*
* The DMA engine uses buffer descriptors (BDs) to describe Ethernet frames.
* These BDs are typically chained together into a list the hardware follows
* when transferring data in and out of the packet buffers. Each BD describes
* a memory region containing either a full or partial Ethernet packet.
*
* Interrupt coalescing is not supported from this built-in DMA engine.
*
* This API requires the user to understand how the DMA operates. The
* following paragraphs provide some explanation, but the user is encouraged
* to read documentation in xemacps_bdring.h as well as study example code
* that accompanies this driver.
*
* The API is designed to get BDs to and from the DMA engine in the most
* efficient means possible. The first step is to establish a memory region
* to contain all BDs for a specific channel. This is done with
* XEmacPs_BdRingCreate(). This function sets up a BD ring that hardware will
* follow as BDs are processed. The ring will consist of a user defined number
* of BDs which will all be partially initialized. For example on the transmit
* channel, the driver will initialize all BDs' so that they are configured
* for transmit. The more fields that can be permanently setup at
* initialization, then the fewer accesses will be needed to each BD while
* the DMA engine is in operation resulting in better throughput and CPU
* utilization. The best case initialization would require the user to set
* only a frame buffer address and length prior to submitting the BD to the
* engine.
*
* BDs move through the engine with the help of functions
* XEmacPs_BdRingAlloc(), XEmacPs_BdRingToHw(), XEmacPs_BdRingFromHw(),
* and XEmacPs_BdRingFree().
* All these functions handle BDs that are in place. That is, there are no
* copies of BDs kept anywhere and any BD the user interacts with is an actual
* BD from the same ring hardware accesses.
*
* BDs in the ring go through a series of states as follows:
* 1. Idle. The driver controls BDs in this state.
* 2. The user has data to transfer. XEmacPs_BdRingAlloc() is called to
* reserve BD(s). Once allocated, the user may setup the BD(s) with
* frame buffer address, length, and other attributes. The user controls
* BDs in this state.
* 3. The user submits BDs to the DMA engine with XEmacPs_BdRingToHw. BDs
* in this state are either waiting to be processed by hardware, are in
* process, or have been processed. The DMA engine controls BDs in this
* state.
* 4. Processed BDs are retrieved with XEmacEpv_BdRingFromHw() by the
* user. Once retrieved, the user can examine each BD for the outcome of
* the DMA transfer. The user controls BDs in this state. After examining
* the BDs the user calls XEmacPs_BdRingFree() which places the BDs back
* into state 1.
*
* Each of the four BD accessor functions operate on a set of BDs. A set is
* defined as a segment of the BD ring consisting of one or more BDs. The user
* views the set as a pointer to the first BD along with the number of BDs for
* that set. The set can be navigated by using macros XEmacPs_BdNext(). The
* user must exercise extreme caution when changing BDs in a set as there is
* nothing to prevent doing a mBdNext past the end of the set and modifying a
* BD out of bounds.
*
* XEmacPs_BdRingAlloc() + XEmacPs_BdRingToHw(), as well as
* XEmacPs_BdRingFromHw() + XEmacPs_BdRingFree() are designed to be used in
* tandem. The same BD set retrieved with BdRingAlloc should be the same one
* provided to hardware with BdRingToHw. Same goes with BdRingFromHw and
* BdRIngFree.
*
* <b>Alignment & Data Cache Restrictions</b>
*
* Due to the design of the hardware, all RX buffers, BDs need to be 4-byte
* aligned. Please reference xemacps_bd.h for cache related macros.
*
* DMA Tx:
*
* - If frame buffers exist in cached memory, then they must be flushed
* prior to committing them to hardware.
*
* DMA Rx:
*
* - If frame buffers exist in cached memory, then the cache must be
* invalidated for the memory region containing the frame prior to data
* access
*
* Both cache invalidate/flush are taken care of in driver code.
*
* <b>Buffer Copying</b>
*
* The driver is designed for a zero-copy buffer scheme. That is, the driver
* will not copy buffers. This avoids potential throughput bottlenecks within
* the driver. If byte copying is required, then the transfer will take longer
* to complete.
*
* <b>Checksum Offloading</b>
*
* The Embedded Processor Block Ethernet can be configured to perform IP, TCP
* and UDP checksum offloading in both receive and transmit directions.
*
* IP packets contain a 16-bit checksum field, which is the 16-bit 1s
* complement of the 1s complement sum of all 16-bit words in the header.
* TCP and UDP packets contain a 16-bit checksum field, which is the 16-bit
* 1s complement of the 1s complement sum of all 16-bit words in the header,
* the data and a conceptual pseudo header.
*
* To calculate these checksums in software requires each byte of the packet
* to be read. For TCP and UDP this can use a large amount of processing power.
* Offloading the checksum calculation to hardware can result in significant
* performance improvements.
*
* The transmit checksum offload is only available to use DMA in packet buffer
* mode. This is because the complete frame to be transmitted must be read
* into the packet buffer memory before the checksum can be calculated and
* written to the header at the beginning of the frame.
*
* For IP, TCP or UDP receive checksum offload to be useful, the operating
* system containing the protocol stack must be aware that this offload is
* available so that it can make use of the fact that the hardware has verified
* the checksum.
*
* When receive checksum offloading is enabled in the hardware, the IP header
* checksum is checked, where the packet meets the following criteria:
*
* 1. If present, the VLAN header must be four octets long and the CFI bit
* must not be set.
* 2. Encapsulation must be RFC 894 Ethernet Type Encoding or RFC 1042 SNAP
* encoding.
* 3. IP v4 packet.
* 4. IP header is of a valid length.
* 5. Good IP header checksum.
* 6. No IP fragmentation.
* 7. TCP or UDP packet.
*
* When an IP, TCP or UDP frame is received, the receive buffer descriptor
* gives an indication if the hardware was able to verify the checksums.
* There is also an indication if the frame had SNAP encapsulation. These
* indication bits will replace the type ID match indication bits when the
* receive checksum offload is enabled.
*
* If any of the checksums are verified incorrect by the hardware, the packet
* is discarded and the appropriate statistics counter incremented.
*
* <b>PHY Interfaces</b>
*
* RGMII 1.3 is the only interface supported.
*
* <b>Asserts</b>
*
* Asserts are used within all Xilinx drivers to enforce constraints on
* parameters. Asserts can be turned off on a system-wide basis by defining,
* at compile time, the NDEBUG identifier. By default, asserts are turned on
* and it is recommended that users leave asserts on during development. For
* deployment use -DNDEBUG compiler switch to remove assert code.
*
* @note
*
* Xilinx drivers are typically composed of two parts, one is the driver
* and the other is the adapter. The driver is independent of OS and processor
* and is intended to be highly portable. The adapter is OS-specific and
* facilitates communication between the driver and an OS.
* This driver is intended to be RTOS and processor independent. Any needs for
* dynamic memory management, threads or thread mutual exclusion, or cache
* control must be satisfied bythe layer above this driver.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a wsy 01/10/10 First release
* 1.00a asa 11/21/11 The function XEmacPs_BdRingFromHwTx in file
* xemacps_bdring.c is modified. Earlier it was checking for
* "BdLimit"(passed argument) number of BDs for finding out
* which BDs are successfully processed. Now one more check
* is added. It looks for BDs till the current BD pointer
* reaches HwTail. By doing this processing time is saved.
* 1.00a asa 01/24/12 The function XEmacPs_BdRingFromHwTx in file
* xemacps_bdring.c is modified. Now start of packet is
* searched for returning the number of BDs processed.
* 1.02a asa 11/05/12 Added a new API for deleting an entry from the HASH
* registers. Added a new API to set the bust length.
* Added some new hash-defines.
* 1.03a asa 01/23/12 Fix for CR #692702 which updates error handling for
* Rx errors. Under heavy Rx traffic, there will be a large
* number of errors related to receive buffer not available.
* Because of a HW bug (SI #692601), under such heavy errors,
* the Rx data path can become unresponsive. To reduce the
* probabilities for hitting this HW bug, the SW writes to
* bit 18 to flush a packet from Rx DPRAM immediately. The
* changes for it are done in the function
* XEmacPs_IntrHandler.
* 1.05a asa 09/23/13 Cache operations on BDs are not required and hence
* removed. It is expected that all BDs are allocated in
* from uncached area.
* 1.06a asa 11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff
* to 0x1fff. This fixes the CR#744902.
* Made changes in example file xemacps_example.h to fix compilation
* issues with iarcc compiler.
* 2.0 adk 10/12/13 Updated as per the New Tcl API's
* 2.1 adk 11/08/14 Fixed the CR#811288. Changes are made in the driver tcl file.
* 2.1 bss 09/08/14 Modified driver tcl to fix CR#820349 to export phy
* address in xparameters.h when GMII to RGMII converter
* is present in hw.
* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp GEM specification and 64-bit
* changes.
* 2.2 adk 29/10/14 Fixed CR#827686 when PCS/PMA core is configured with
* 1000BASE-X mode export proper values to the xparameters.h
* file. Changes are made in the driver tcl file.
* 3.0 adk 08/1/15 Don't include gem in peripheral test when gem is
* configured with PCS/PMA Core. Changes are made in the
* test app tcl(CR:827686).
* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
* 3.0 hk 03/18/15 Added support for jumbo frames. Increase AHB burst.
* Disable extended mode. Perform all 64 bit changes under
* check for arch64.
* Remove "used bit set" from TX error interrupt masks.
* 3.1 hk 07/27/15 Do not call error handler with '0' error code when
* there is no error. CR# 869403
* 08/10/15 Update upper 32 bit tx and rx queue ptr registers.
* 3.2 hk 02/22/16 Added SGMII support for Zynq Ultrascale+ MPSoC.
* 3.4 ms 01/23/17 Modified xil_printf statement in main function for all
* examples to ensure that "Successfully ran" and "Failed"
* strings are available in all examples. This is a fix
* for CR-965028.
* ms 03/17/17 Modified text file in examples folder for doxygen
* generation.
* ms 04/05/17 Added tabspace for return statements in functions of
* xemacps_ieee1588_example.c for proper documentation
* while generating doxygen.
* 3.5 hk 08/14/17 Update cache coherency information of the interface in
* its config structure.
* 3.6 rb 09/08/17 HwCnt variable (in XEmacPs_BdRing structure) is
* changed to volatile.
* Add API XEmacPs_BdRingPtrReset() to reset pointers
* 3.8 hk 07/19/18 Fixed CPP, GCC and doxygen warnings - CR-1006327
* hk 09/17/18 Fix PTP interrupt masks and cleanup comments.
* 3.9 hk 01/23/19 Add RX watermark support
* 3.11 sd 02/14/20 Add clock support
* 3.13 nsk 12/14/20 Updated the tcl to not to use the instance names.
*
* </pre>
*
****************************************************************************/
#ifndef XEMACPS_H /* prevent circular inclusions */
#define XEMACPS_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files ********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xstatus.h"
#include "xemacps_hw.h"
#include "xemacps_bd.h"
#include "xemacps_bdring.h"
#if defined (XCLOCKING)
#include "xil_clocking.h"
#endif
/************************** Constant Definitions ****************************/
/*
* Device information
*/
#define XEMACPS_DEVICE_NAME "xemacps"
#define XEMACPS_DEVICE_DESC "Xilinx PS 10/100/1000 MAC"
/** @name Configuration options
*
* Device configuration options. See the XEmacPs_SetOptions(),
* XEmacPs_ClearOptions() and XEmacPs_GetOptions() for information on how to
* use options.
*
* The default state of the options are noted and are what the device and
* driver will be set to after calling XEmacPs_Reset() or
* XEmacPs_Initialize().
*
* @{
*/
#define XEMACPS_PROMISC_OPTION 0x00000001U
/**< Accept all incoming packets.
* This option defaults to disabled (cleared) */
#define XEMACPS_FRAME1536_OPTION 0x00000002U
/**< Frame larger than 1516 support for Tx & Rx.
* This option defaults to disabled (cleared) */
#define XEMACPS_VLAN_OPTION 0x00000004U
/**< VLAN Rx & Tx frame support.
* This option defaults to disabled (cleared) */
#define XEMACPS_FLOW_CONTROL_OPTION 0x00000010U
/**< Enable recognition of flow control frames on Rx
* This option defaults to enabled (set) */
#define XEMACPS_FCS_STRIP_OPTION 0x00000020U
/**< Strip FCS and PAD from incoming frames. Note: PAD from VLAN frames is not
* stripped.
* This option defaults to enabled (set) */
#define XEMACPS_FCS_INSERT_OPTION 0x00000040U
/**< Generate FCS field and add PAD automatically for outgoing frames.
* This option defaults to disabled (cleared) */
#define XEMACPS_LENTYPE_ERR_OPTION 0x00000080U
/**< Enable Length/Type error checking for incoming frames. When this option is
* set, the MAC will filter frames that have a mismatched type/length field
* and if XEMACPS_REPORT_RXERR_OPTION is set, the user is notified when these
* types of frames are encountered. When this option is cleared, the MAC will
* allow these types of frames to be received.
*
* This option defaults to disabled (cleared) */
#define XEMACPS_TRANSMITTER_ENABLE_OPTION 0x00000100U
/**< Enable the transmitter.
* This option defaults to enabled (set) */
#define XEMACPS_RECEIVER_ENABLE_OPTION 0x00000200U
/**< Enable the receiver
* This option defaults to enabled (set) */
#define XEMACPS_BROADCAST_OPTION 0x00000400U
/**< Allow reception of the broadcast address
* This option defaults to enabled (set) */
#define XEMACPS_MULTICAST_OPTION 0x00000800U
/**< Allows reception of multicast addresses programmed into hash
* This option defaults to disabled (clear) */
#define XEMACPS_RX_CHKSUM_ENABLE_OPTION 0x00001000U
/**< Enable the RX checksum offload
* This option defaults to enabled (set) */
#define XEMACPS_TX_CHKSUM_ENABLE_OPTION 0x00002000U
/**< Enable the TX checksum offload
* This option defaults to enabled (set) */
#define XEMACPS_JUMBO_ENABLE_OPTION 0x00004000U
#define XEMACPS_SGMII_ENABLE_OPTION 0x00008000U
#define XEMACPS_DEFAULT_OPTIONS \
((u32)XEMACPS_FLOW_CONTROL_OPTION | \
(u32)XEMACPS_FCS_INSERT_OPTION | \
(u32)XEMACPS_FCS_STRIP_OPTION | \
(u32)XEMACPS_BROADCAST_OPTION | \
(u32)XEMACPS_LENTYPE_ERR_OPTION | \
(u32)XEMACPS_TRANSMITTER_ENABLE_OPTION | \
(u32)XEMACPS_RECEIVER_ENABLE_OPTION | \
(u32)XEMACPS_RX_CHKSUM_ENABLE_OPTION | \
(u32)XEMACPS_TX_CHKSUM_ENABLE_OPTION)
/**< Default options set when device is initialized or reset */
/*@}*/
/** @name Callback identifiers
*
* These constants are used as parameters to XEmacPs_SetHandler()
* @{
*/
#define XEMACPS_HANDLER_DMASEND 1U
#define XEMACPS_HANDLER_DMARECV 2U
#define XEMACPS_HANDLER_ERROR 3U
/*@}*/
/* Constants to determine the configuration of the hardware device. They are
* used to allow the driver to verify it can operate with the hardware.
*/
#define XEMACPS_MDIO_DIV_DFT MDC_DIV_32 /**< Default MDIO clock divisor */
/* The next few constants help upper layers determine the size of memory
* pools used for Ethernet buffers and descriptor lists.
*/
#define XEMACPS_MAC_ADDR_SIZE 6U /* size of Ethernet header */
#define XEMACPS_MTU 1500U /* max MTU size of Ethernet frame */
#define XEMACPS_MTU_JUMBO 10240U /* max MTU size of jumbo frame */
#define XEMACPS_HDR_SIZE 14U /* size of Ethernet header */
#define XEMACPS_HDR_VLAN_SIZE 18U /* size of Ethernet header with VLAN */
#define XEMACPS_TRL_SIZE 4U /* size of Ethernet trailer (FCS) */
#define XEMACPS_MAX_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \
XEMACPS_TRL_SIZE)
#define XEMACPS_MAX_VLAN_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \
XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE)
#define XEMACPS_MAX_VLAN_FRAME_SIZE_JUMBO (XEMACPS_MTU_JUMBO + XEMACPS_HDR_SIZE + \
XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE)
/* DMACR Bust length hash defines */
#define XEMACPS_SINGLE_BURST 0x00000001
#define XEMACPS_4BYTE_BURST 0x00000004
#define XEMACPS_8BYTE_BURST 0x00000008
#define XEMACPS_16BYTE_BURST 0x00000010
/**************************** Type Definitions ******************************/
/** @name Typedefs for callback functions
*
* These callbacks are invoked in interrupt context.
* @{
*/
/**
* Callback invoked when frame(s) have been sent or received in interrupt
* driven DMA mode. To set the send callback, invoke XEmacPs_SetHandler().
*
* @param CallBackRef is user data assigned when the callback was set.
*
* @note
* See xemacps_hw.h for bitmasks definitions and the device hardware spec for
* further information on their meaning.
*
*/
typedef void (*XEmacPs_Handler) (void *CallBackRef);
/**
* Callback when an asynchronous error occurs. To set this callback, invoke
* XEmacPs_SetHandler() with XEMACPS_HANDLER_ERROR in the HandlerType
* parameter.
*
* @param CallBackRef is user data assigned when the callback was set.
* @param Direction defines either receive or transmit error(s) has occurred.
* @param ErrorWord definition varies with Direction
*
*/
typedef void (*XEmacPs_ErrHandler) (void *CallBackRef, u8 Direction,
u32 ErrorWord);
/*@}*/
/**
* This typedef contains configuration information for a device.
*/
typedef struct {
#ifdef SDT
char *Name; /**< Unique name of the device */
#else
u16 DeviceId; /**< Unique ID of device */
#endif
UINTPTR BaseAddress;/**< Physical base address of IPIF registers */
u8 IsCacheCoherent; /**< Applicable only to A53 in EL1 mode;
* describes whether Cache Coherent or not */
#ifdef SDT
u16 IntrId;
UINTPTR IntrParent;
#endif
#if defined (XCLOCKING) || defined (SDT)
u32 RefClk; /**< Input clock */
#endif
#ifdef SDT
char *PhyType; /**< PhyType indicates which type of PHY interface is
* used (MII, GMII, RGMII, etc.
*/
#endif
u16 S1GDiv0; /**< 1Gbps Clock Divider 0 */
u8 S1GDiv1; /**< 1Gbps Clock Divider 1 */
u16 S100MDiv0; /**< 100Mbps Clock Divider 0 */
u8 S100MDiv1; /**< 100Mbps Clock Divider 1 */
u16 S10MDiv0; /**< 10Mbps Clock Divider 0 */
u8 S10MDiv1; /**< 10Mbps Clock Divider 1 */
} XEmacPs_Config;
/**
* The XEmacPs driver instance data. The user is required to allocate a
* structure of this type for every XEmacPs device in the system. A pointer
* to a structure of this type is then passed to the driver API functions.
*/
typedef struct XEmacPs_Instance {
XEmacPs_Config Config; /* Hardware configuration */
u32 IsStarted; /* Device is currently started */
u32 IsReady; /* Device is initialized and ready */
u32 Options; /* Current options word */
XEmacPs_BdRing TxBdRing; /* Transmit BD ring */
XEmacPs_BdRing RxBdRing; /* Receive BD ring */
XEmacPs_Handler SendHandler;
XEmacPs_Handler RecvHandler;
void *SendRef;
void *RecvRef;
XEmacPs_ErrHandler ErrorHandler;
void *ErrorRef;
u32 Version;
u32 RxBufMask;
u32 MaxMtuSize;
u32 MaxFrameSize;
u32 MaxVlanFrameSize;
} XEmacPs;
/***************** Macros (Inline Functions) Definitions ********************/
/****************************************************************************/
/**
* Retrieve the Tx ring object. This object can be used in the various Ring
* API functions.
*
* @param InstancePtr is the DMA channel to operate on.
*
* @return TxBdRing attribute
*
* @note
* C-style signature:
* XEmacPs_BdRing XEmacPs_GetTxRing(XEmacPs *InstancePtr)
*
*****************************************************************************/
#define XEmacPs_GetTxRing(InstancePtr) ((InstancePtr)->TxBdRing)
/****************************************************************************/
/**
* Retrieve the Rx ring object. This object can be used in the various Ring
* API functions.
*
* @param InstancePtr is the DMA channel to operate on.
*
* @return RxBdRing attribute
*
* @note
* C-style signature:
* XEmacPs_BdRing XEmacPs_GetRxRing(XEmacPs *InstancePtr)
*
*****************************************************************************/
#define XEmacPs_GetRxRing(InstancePtr) ((InstancePtr)->RxBdRing)
/****************************************************************************/
/**
*
* Enable interrupts specified in <i>Mask</i>. The corresponding interrupt for
* each bit set to 1 in <i>Mask</i>, will be enabled.
*
* @param InstancePtr is a pointer to the instance to be worked on.
* @param Mask contains a bit mask of interrupts to enable. The mask can
* be formed using a set of bitwise or'd values.
*
* @note
* The state of the transmitter and receiver are not modified by this function.
* C-style signature
* void XEmacPs_IntEnable(XEmacPs *InstancePtr, u32 Mask)
*
*****************************************************************************/
#define XEmacPs_IntEnable(InstancePtr, Mask) \
XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_IER_OFFSET, \
((Mask) & XEMACPS_IXR_ALL_MASK));
/****************************************************************************/
/**
*
* Disable interrupts specified in <i>Mask</i>. The corresponding interrupt for
* each bit set to 1 in <i>Mask</i>, will be enabled.
*
* @param InstancePtr is a pointer to the instance to be worked on.
* @param Mask contains a bit mask of interrupts to disable. The mask can
* be formed using a set of bitwise or'd values.
*
* @note
* The state of the transmitter and receiver are not modified by this function.
* C-style signature
* void XEmacPs_IntDisable(XEmacPs *InstancePtr, u32 Mask)
*
*****************************************************************************/
#define XEmacPs_IntDisable(InstancePtr, Mask) \
XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_IDR_OFFSET, \
((Mask) & XEMACPS_IXR_ALL_MASK));
/****************************************************************************/
/**
*
* Enable interrupts specified in <i>Mask</i>. The corresponding interrupt for
* each bit set to 1 in <i>Mask</i>, will be enabled.
*
* @param InstancePtr is a pointer to the instance to be worked on.
* @param Mask contains a bit mask of interrupts to enable. The mask can
* be formed using a set of bitwise or'd values.
*
* @note
* The state of the transmitter and receiver are not modified by this function.
* C-style signature
* void XEmacPs_IntQ1Enable(XEmacPs *InstancePtr, u32 Mask)
*
*****************************************************************************/
#define XEmacPs_IntQ1Enable(InstancePtr, Mask) \
XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_INTQ1_IER_OFFSET, \
((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
/****************************************************************************/
/**
*
* Disable interrupts specified in <i>Mask</i>. The corresponding interrupt for
* each bit set to 1 in <i>Mask</i>, will be enabled.
*
* @param InstancePtr is a pointer to the instance to be worked on.
* @param Mask contains a bit mask of interrupts to disable. The mask can
* be formed using a set of bitwise or'd values.
*
* @note
* The state of the transmitter and receiver are not modified by this function.
* C-style signature
* void XEmacPs_IntDisable(XEmacPs *InstancePtr, u32 Mask)
*
*****************************************************************************/
#define XEmacPs_IntQ1Disable(InstancePtr, Mask) \
XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_INTQ1_IDR_OFFSET, \
((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
/****************************************************************************/
/**
*
* This macro triggers trasmit circuit to send data currently in TX buffer(s).
*
* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
*
* @return
*
* @note
*
* Signature: void XEmacPs_Transmit(XEmacPs *InstancePtr)
*
*****************************************************************************/
#define XEmacPs_Transmit(InstancePtr) \
XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_NWCTRL_OFFSET, \
(XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_NWCTRL_OFFSET) | XEMACPS_NWCTRL_STARTTX_MASK))
/****************************************************************************/
/**
*
* This macro determines if the device is configured with checksum offloading
* on the receive channel
*
* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
*
* @return
*
* Boolean TRUE if the device is configured with checksum offloading, or
* FALSE otherwise.
*
* @note
*
* Signature: u32 XEmacPs_IsRxCsum(XEmacPs *InstancePtr)
*
*****************************************************************************/
#define XEmacPs_IsRxCsum(InstancePtr) \
((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_NWCFG_OFFSET) & XEMACPS_NWCFG_RXCHKSUMEN_MASK) != 0U \
? TRUE : FALSE)
/****************************************************************************/
/**
*
* This macro determines if the device is configured with checksum offloading
* on the transmit channel
*
* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
*
* @return
*
* Boolean TRUE if the device is configured with checksum offloading, or
* FALSE otherwise.
*
* @note
*
* Signature: u32 XEmacPs_IsTxCsum(XEmacPs *InstancePtr)
*
*****************************************************************************/
#define XEmacPs_IsTxCsum(InstancePtr) \
((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_DMACR_OFFSET) & XEMACPS_DMACR_TCPCKSUM_MASK) != 0U \
? TRUE : FALSE)
/************************** Function Prototypes *****************************/
/****************************************************************************/
/**
*
* This macro sets RX watermark register.
*
* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
* @param High is the non-zero RX high watermark value. When SRAM fill level
* is above this, a pause frame will be sent.
* @param Low is the non-zero RX low watermark value. When SRAM fill level
* is below this, a zero length pause frame will be sent IF the last
* pause frame sent was non-zero.
*
* @return None
*
* @note
*
* Signature: void XEmacPs_SetRXWatermark(XEmacPs *InstancePtr, u16 High,
* u16 Low)
*
*****************************************************************************/
#define XEmacPs_SetRXWatermark(InstancePtr, High, Low) \
XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_RXWATERMARK_OFFSET, \
(High & XEMACPS_RXWM_HIGH_MASK) | \
((Low << XEMACPS_RXWM_LOW_SHFT_MSK) & XEMACPS_RXWM_LOW_MASK) |)
/****************************************************************************/
/**
*
* This macro gets RX watermark register.
*
* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
*
* @return RX watermark register value
*
* @note
*
* Signature: void XEmacPs_GetRXWatermark(XEmacPs *InstancePtr)
*
*****************************************************************************/
#define XEmacPs_GetRXWatermark(InstancePtr) \
XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_RXWATERMARK_OFFSET)
/*
* Initialization functions in xemacps.c
*/
LONG XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config *CfgPtr,
UINTPTR EffectiveAddress);
void XEmacPs_Start(XEmacPs *InstancePtr);
void XEmacPs_Stop(XEmacPs *InstancePtr);
void XEmacPs_Reset(XEmacPs *InstancePtr);
void XEmacPs_SetQueuePtr(XEmacPs *InstancePtr, UINTPTR QPtr, u8 QueueNum,
u16 Direction);
/*
* Lookup configuration in xemacps_sinit.c
*/
#ifndef SDT
XEmacPs_Config *XEmacPs_LookupConfig(u16 DeviceId);
#else
XEmacPs_Config *XEmacPs_LookupConfig(UINTPTR BaseAddress);
#endif
/*
* Interrupt-related functions in xemacps_intr.c
* DMA only and FIFO is not supported. This DMA does not support coalescing.
*/
LONG XEmacPs_SetHandler(XEmacPs *InstancePtr, u32 HandlerType,
void *FuncPointer, void *CallBackRef);
void XEmacPs_IntrHandler(void *XEmacPsPtr);
/*
* MAC configuration/control functions in XEmacPs_control.c
*/
LONG XEmacPs_SetOptions(XEmacPs *InstancePtr, u32 Options);
LONG XEmacPs_ClearOptions(XEmacPs *InstancePtr, u32 Options);
u32 XEmacPs_GetOptions(XEmacPs *InstancePtr);
LONG XEmacPs_SetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index);
LONG XEmacPs_DeleteHash(XEmacPs *InstancePtr, void *AddressPtr);
void XEmacPs_GetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index);
LONG XEmacPs_SetHash(XEmacPs *InstancePtr, void *AddressPtr);
void XEmacPs_ClearHash(XEmacPs *InstancePtr);
void XEmacPs_GetHash(XEmacPs *InstancePtr, void *AddressPtr);
void XEmacPs_SetMdioDivisor(XEmacPs *InstancePtr,
XEmacPs_MdcDiv Divisor);
void XEmacPs_SetOperatingSpeed(XEmacPs *InstancePtr, u16 Speed);
u16 XEmacPs_GetOperatingSpeed(XEmacPs *InstancePtr);
LONG XEmacPs_PhyRead(XEmacPs *InstancePtr, u32 PhyAddress,
u32 RegisterNum, u16 *PhyDataPtr);
LONG XEmacPs_PhyWrite(XEmacPs *InstancePtr, u32 PhyAddress,
u32 RegisterNum, u16 PhyData);
LONG XEmacPs_SetTypeIdCheck(XEmacPs *InstancePtr, u32 Id_Check, u8 Index);
LONG XEmacPs_SendPausePacket(XEmacPs *InstancePtr);
void XEmacPs_DMABLengthUpdate(XEmacPs *InstancePtr, s32 BLength);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/** @} */
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/xemacps_bd.h
+764
View File
@@ -0,0 +1,764 @@
/******************************************************************************
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2024 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xemacps_bd.h
* @addtogroup emacps Overview
* @{
*
* This header provides operations to manage buffer descriptors in support
* of scatter-gather DMA.
*
* The API exported by this header defines abstracted macros that allow the
* user to read/write specific BD fields.
*
* <b>Buffer Descriptors</b>
*
* A buffer descriptor (BD) defines a DMA transaction. The macros defined by
* this header file allow access to most fields within a BD to tailor a DMA
* transaction according to user and hardware requirements. See the hardware
* IP DMA spec for more information on BD fields and how they affect transfers.
*
* The XEmacPs_Bd structure defines a BD. The organization of this structure
* is driven mainly by the hardware for use in scatter-gather DMA transfers.
*
* <b>Performance</b>
*
* Limiting I/O to BDs can improve overall performance of the DMA channel.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a wsy 01/10/10 First release
* 2.1 srt 07/15/14 Add support for Zynq Ultrascale MP GEM specification
* and 64-bit changes.
* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
* 3.0 hk 02/20/15 Added support for jumbo frames.
* Disable extended mode. Perform all 64 bit changes under
* check for arch64.
* 3.2 hk 11/18/15 Change BD typedef and number of words.
* 3.8 hk 08/18/18 Remove duplicate definition of XEmacPs_BdSetLength
* 3.8 mus 11/05/18 Support 64 bit DMA addresses for Microblaze-X platform.
* 3.9 aj 22/03/24 Add mask for XEmaPs_BdGetBufAddr
*
* </pre>
*
* ***************************************************************************
*/
#ifndef XEMACPS_BD_H /* prevent circular inclusions */
#define XEMACPS_BD_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include <string.h>
#include "xil_types.h"
#include "xil_assert.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
#ifdef __aarch64__
/* Minimum BD alignment */
#define XEMACPS_DMABD_MINIMUM_ALIGNMENT 64U
#define XEMACPS_BD_NUM_WORDS 4U
#else
/* Minimum BD alignment */
#define XEMACPS_DMABD_MINIMUM_ALIGNMENT 4U
#define XEMACPS_BD_NUM_WORDS 2U
#endif
/**
* The XEmacPs_Bd is the type for buffer descriptors (BDs).
*/
typedef u32 XEmacPs_Bd[XEMACPS_BD_NUM_WORDS];
/***************** Macros (Inline Functions) Definitions *********************/
/*****************************************************************************/
/**
* Zero out BD fields
*
* @param BdPtr is the BD pointer to operate on
*
* @return Nothing
*
* @note
* C-style signature:
* void XEmacPs_BdClear(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdClear(BdPtr) \
memset((BdPtr), 0, sizeof(XEmacPs_Bd))
/****************************************************************************/
/**
*
* Read the given Buffer Descriptor word.
*
* @param BaseAddress is the base address of the BD to read
* @param Offset is the word offset to be read
*
* @return The 32-bit value of the field
*
* @note
* C-style signature:
* u32 XEmacPs_BdRead(UINTPTR BaseAddress, UINTPTR Offset)
*
*****************************************************************************/
#define XEmacPs_BdRead(BaseAddress, Offset) \
(*(u32 *)((UINTPTR)((void*)(BaseAddress)) + (u32)(Offset)))
/****************************************************************************/
/**
*
* Write the given Buffer Descriptor word.
*
* @param BaseAddress is the base address of the BD to write
* @param Offset is the word offset to be written
* @param Data is the 32-bit value to write to the field
*
* @return None.
*
* @note
* C-style signature:
* void XEmacPs_BdWrite(UINTPTR BaseAddress, UINTPTR Offset, UINTPTR Data)
*
*****************************************************************************/
#define XEmacPs_BdWrite(BaseAddress, Offset, Data) \
(*(u32 *)((UINTPTR)(void*)(BaseAddress) + (u32)(Offset)) = (u32)(Data))
/*****************************************************************************/
/**
* Set the BD's Address field (word 0).
*
* @param BdPtr is the BD pointer to operate on
* @param Addr is the value to write to BD's status field.
*
* @note :
*
* C-style signature:
* void XEmacPs_BdSetAddressTx(XEmacPs_Bd* BdPtr, UINTPTR Addr)
*
*****************************************************************************/
#if defined(__aarch64__) || defined(__arch64__)
#define XEmacPs_BdSetAddressTx(BdPtr, Addr) \
XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
(u32)((Addr) & ULONG64_LO_MASK)); \
XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET, \
(u32)(((Addr) & ULONG64_HI_MASK) >> 32U));
#else
#define XEmacPs_BdSetAddressTx(BdPtr, Addr) \
XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, (u32)(Addr))
#endif
/*****************************************************************************/
/**
* Set the BD's Address field (word 0).
*
* @param BdPtr is the BD pointer to operate on
* @param Addr is the value to write to BD's status field.
*
* @note : Due to some bits are mixed within receive BD's address field,
* read-modify-write is performed.
*
* C-style signature:
* void XEmacPs_BdSetAddressRx(XEmacPs_Bd* BdPtr, UINTPTR Addr)
*
*****************************************************************************/
#ifdef __aarch64__
#define XEmacPs_BdSetAddressRx(BdPtr, Addr) \
XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
~XEMACPS_RXBUF_ADD_MASK) | ((u32)((Addr) & ULONG64_LO_MASK)))); \
XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET, \
(u32)(((Addr) & ULONG64_HI_MASK) >> 32U));
#else
#define XEmacPs_BdSetAddressRx(BdPtr, Addr) \
XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
~XEMACPS_RXBUF_ADD_MASK) | (UINTPTR)(Addr)))
#endif
/*****************************************************************************/
/**
* Set the BD's Status field (word 1).
*
* @param BdPtr is the BD pointer to operate on
* @param Data is the value to write to BD's status field.
*
* @note
* C-style signature:
* void XEmacPs_BdSetStatus(XEmacPs_Bd* BdPtr, UINTPTR Data)
*
*****************************************************************************/
#define XEmacPs_BdSetStatus(BdPtr, Data) \
XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | (Data))
/*****************************************************************************/
/**
* Retrieve the BD's Packet DMA transfer status word (word 1).
*
* @param BdPtr is the BD pointer to operate on
*
* @return Status word
*
* @note
* C-style signature:
* u32 XEmacPs_BdGetStatus(XEmacPs_Bd* BdPtr)
*
* Due to the BD bit layout differences in transmit and receive. User's
* caution is required.
*****************************************************************************/
#define XEmacPs_BdGetStatus(BdPtr) \
XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET)
/*****************************************************************************/
/**
* Get the address (bits 0..31) of the BD's buffer address (word 0)
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* UINTPTR XEmacPs_BdGetBufAddr(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#if defined(__aarch64__) || defined(__arch64__)
#define XEmacPs_BdGetBufAddr(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & XEMACPS_RXBUF_ADD_MASK) | \
(XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET)) << 32U)
#else
#define XEmacPs_BdGetBufAddr(BdPtr) \
(XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & XEMACPS_RXBUF_ADD_MASK)
#endif
/*****************************************************************************/
/**
* Set transfer length in bytes for the given BD. The length must be set each
* time a BD is submitted to hardware.
*
* @param BdPtr is the BD pointer to operate on
* @param LenBytes is the number of bytes to transfer.
*
* @note
* C-style signature:
* void XEmacPs_BdSetLength(XEmacPs_Bd* BdPtr, u32 LenBytes)
*
*****************************************************************************/
#define XEmacPs_BdSetLength(BdPtr, LenBytes) \
XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
~XEMACPS_TXBUF_LEN_MASK) | (LenBytes)))
/*****************************************************************************/
/**
* Retrieve the BD length field.
*
* For Tx channels, the returned value is the same as that written with
* XEmacPs_BdSetLength().
*
* For Rx channels, the returned value is the size of the received packet.
*
* @param BdPtr is the BD pointer to operate on
*
* @return Length field processed by hardware or set by
* XEmacPs_BdSetLength().
*
* @note
* C-style signature:
* UINTPTR XEmacPs_BdGetLength(XEmacPs_Bd* BdPtr)
* XEAMCPS_RXBUF_LEN_MASK is same as XEMACPS_TXBUF_LEN_MASK.
*
*****************************************************************************/
#define XEmacPs_BdGetLength(BdPtr) \
(XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_RXBUF_LEN_MASK)
/*****************************************************************************/
/**
* Retrieve the RX frame size.
*
* The returned value is the size of the received packet.
* This API supports jumbo frame sizes if enabled.
*
* @param InstancePtr is the pointer to XEmacps instance
*
* @param BdPtr is the BD pointer to operate on
*
* @return Length field processed by hardware or set by
* XEmacPs_BdSetLength().
*
* @note
* C-style signature:
* UINTPTR XEmacPs_GetRxFrameSize(XEmacPs* InstancePtr, XEmacPs_Bd* BdPtr)
* RxBufMask is dependent on whether jumbo is enabled or not.
*
*****************************************************************************/
#define XEmacPs_GetRxFrameSize(InstancePtr, BdPtr) \
(XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
(InstancePtr)->RxBufMask)
/*****************************************************************************/
/**
* Test whether the given BD has been marked as the last BD of a packet.
*
* @param BdPtr is the BD pointer to operate on
*
* @return TRUE if BD represents the "Last" BD of a packet, FALSE otherwise
*
* @note
* C-style signature:
* UINTPTR XEmacPs_BdIsLast(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsLast(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_RXBUF_EOF_MASK)!=0U ? TRUE : FALSE)
/*****************************************************************************/
/**
* Tell the DMA engine that the given transmit BD marks the end of the current
* packet to be processed.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* void XEmacPs_BdSetLast(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdSetLast(BdPtr) \
(XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
XEMACPS_TXBUF_LAST_MASK))
/*****************************************************************************/
/**
* Tell the DMA engine that the current packet does not end with the given
* BD.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* void XEmacPs_BdClearLast(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdClearLast(BdPtr) \
(XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
~XEMACPS_TXBUF_LAST_MASK))
/*****************************************************************************/
/**
* Set this bit to mark the last descriptor in the receive buffer descriptor
* list.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* void XEmacPs_BdSetRxWrap(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
/*#define XEmacPs_BdSetRxWrap(BdPtr) \
(XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) | \
XEMACPS_RXBUF_WRAP_MASK))
*/
/*****************************************************************************/
/**
* Determine the wrap bit of the receive BD which indicates end of the
* BD list.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* u8 XEmacPs_BdIsRxWrap(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsRxWrap(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
XEMACPS_RXBUF_WRAP_MASK)!=0U ? TRUE : FALSE)
/*****************************************************************************/
/**
* Sets this bit to mark the last descriptor in the transmit buffer
* descriptor list.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* void XEmacPs_BdSetTxWrap(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
/*#define XEmacPs_BdSetTxWrap(BdPtr) \
(XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
XEMACPS_TXBUF_WRAP_MASK))
*/
/*****************************************************************************/
/**
* Determine the wrap bit of the transmit BD which indicates end of the
* BD list.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* u8 XEmacPs_BdGetTxWrap(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsTxWrap(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_TXBUF_WRAP_MASK)!=0U ? TRUE : FALSE)
/*****************************************************************************/
/*
* Must clear this bit to enable the MAC to write data to the receive
* buffer. Hardware sets this bit once it has successfully written a frame to
* memory. Once set, software has to clear the bit before the buffer can be
* used again. This macro clear the new bit of the receive BD.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* void XEmacPs_BdClearRxNew(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdClearRxNew(BdPtr) \
(XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
~XEMACPS_RXBUF_NEW_MASK))
/*****************************************************************************/
/**
* Determine the new bit of the receive BD.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* UINTPTR XEmacPs_BdIsRxNew(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsRxNew(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
XEMACPS_RXBUF_NEW_MASK)!=0U ? TRUE : FALSE)
/*****************************************************************************/
/**
* Software sets this bit to disable the buffer to be read by the hardware.
* Hardware sets this bit for the first buffer of a frame once it has been
* successfully transmitted. This macro sets this bit of transmit BD to avoid
* confusion.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* void XEmacPs_BdSetTxUsed(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdSetTxUsed(BdPtr) \
(XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
XEMACPS_TXBUF_USED_MASK))
/*****************************************************************************/
/**
* Software clears this bit to enable the buffer to be read by the hardware.
* Hardware sets this bit for the first buffer of a frame once it has been
* successfully transmitted. This macro clears this bit of transmit BD.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* void XEmacPs_BdClearTxUsed(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdClearTxUsed(BdPtr) \
(XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
~XEMACPS_TXBUF_USED_MASK))
/*****************************************************************************/
/**
* Determine the used bit of the transmit BD.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* UINTPTR XEmacPs_BdIsTxUsed(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsTxUsed(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_TXBUF_USED_MASK)!=0U ? TRUE : FALSE)
/*****************************************************************************/
/**
* Determine if a frame fails to be transmitted due to too many retries.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* UINTPTR XEmacPs_BdIsTxRetry(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsTxRetry(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_TXBUF_RETRY_MASK)!=0U ? TRUE : FALSE)
/*****************************************************************************/
/**
* Determine if a frame fails to be transmitted due to data can not be
* feteched in time or buffers are exhausted.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* UINTPTR XEmacPs_BdIsTxUrun(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsTxUrun(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_TXBUF_URUN_MASK)!=0U ? TRUE : FALSE)
/*****************************************************************************/
/**
* Determine if a frame fails to be transmitted due to buffer is exhausted
* mid-frame.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* UINTPTR XEmacPs_BdIsTxExh(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsTxExh(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_TXBUF_EXH_MASK)!=0U ? TRUE : FALSE)
/*****************************************************************************/
/**
* Sets this bit, no CRC will be appended to the current frame. This control
* bit must be set for the first buffer in a frame and will be ignored for
* the subsequent buffers of a frame.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* This bit must be clear when using the transmit checksum generation offload,
* otherwise checksum generation and substitution will not occur.
*
* C-style signature:
* UINTPTR XEmacPs_BdSetTxNoCRC(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdSetTxNoCRC(BdPtr) \
(XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
XEMACPS_TXBUF_NOCRC_MASK))
/*****************************************************************************/
/**
* Clear this bit, CRC will be appended to the current frame. This control
* bit must be set for the first buffer in a frame and will be ignored for
* the subsequent buffers of a frame.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* This bit must be clear when using the transmit checksum generation offload,
* otherwise checksum generation and substitution will not occur.
*
* C-style signature:
* UINTPTR XEmacPs_BdClearTxNoCRC(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdClearTxNoCRC(BdPtr) \
(XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
~XEMACPS_TXBUF_NOCRC_MASK))
/*****************************************************************************/
/**
* Determine the broadcast bit of the receive BD.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* UINTPTR XEmacPs_BdIsRxBcast(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsRxBcast(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_RXBUF_BCAST_MASK)!=0U ? TRUE : FALSE)
/*****************************************************************************/
/**
* Determine the multicast hash bit of the receive BD.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* UINTPTR XEmacPs_BdIsRxMultiHash(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsRxMultiHash(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_RXBUF_MULTIHASH_MASK)!=0U ? TRUE : FALSE)
/*****************************************************************************/
/**
* Determine the unicast hash bit of the receive BD.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* UINTPTR XEmacPs_BdIsRxUniHash(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsRxUniHash(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_RXBUF_UNIHASH_MASK)!=0U ? TRUE : FALSE)
/*****************************************************************************/
/**
* Determine if the received frame is a VLAN Tagged frame.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* UINTPTR XEmacPs_BdIsRxVlan(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsRxVlan(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_RXBUF_VLAN_MASK)!=0U ? TRUE : FALSE)
/*****************************************************************************/
/**
* Determine if the received frame has Type ID of 8100h and null VLAN
* identifier(Priority tag).
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* UINTPTR XEmacPs_BdIsRxPri(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsRxPri(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_RXBUF_PRI_MASK)!=0U ? TRUE : FALSE)
/*****************************************************************************/
/**
* Determine if the received frame's Concatenation Format Indicator (CFI) of
* the frames VLANTCI field was set.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* UINTPTR XEmacPs_BdIsRxCFI(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsRxCFI(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_RXBUF_CFI_MASK)!=0U ? TRUE : FALSE)
/*****************************************************************************/
/**
* Determine the End Of Frame (EOF) bit of the receive BD.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* UINTPTR XEmacPs_BdGetRxEOF(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsRxEOF(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_RXBUF_EOF_MASK)!=0U ? TRUE : FALSE)
/*****************************************************************************/
/**
* Determine the Start Of Frame (SOF) bit of the receive BD.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* UINTPTR XEmacPs_BdGetRxSOF(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsRxSOF(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_RXBUF_SOF_MASK)!=0U ? TRUE : FALSE)
/************************** Function Prototypes ******************************/
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/** @} */
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/xemacps_bdring.h
+216
View File
@@ -0,0 +1,216 @@
/******************************************************************************
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xemacps_bdring.h
* @addtogroup emacps Overview
* @{
*
* The Xiline EmacPs Buffer Descriptor ring driver. This is part of EmacPs
* DMA functionalities.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a wsy 01/10/10 First release
* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp architecture.
* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
* 3.6 rb 09/08/17 HwCnt variable (in XEmacPs_BdRing structure) is
* changed to volatile.
*
* </pre>
*
******************************************************************************/
#ifndef XEMACPS_BDRING_H /* prevent curcular inclusions */
#define XEMACPS_BDRING_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/**************************** Type Definitions *******************************/
/** This is an internal structure used to maintain the DMA list */
typedef struct {
UINTPTR PhysBaseAddr;/**< Physical address of 1st BD in list */
UINTPTR BaseBdAddr; /**< Virtual address of 1st BD in list */
UINTPTR HighBdAddr; /**< Virtual address of last BD in the list */
u32 Length; /**< Total size of ring in bytes */
u32 RunState; /**< Flag to indicate DMA is started */
u32 Separation; /**< Number of bytes between the starting address
of adjacent BDs */
XEmacPs_Bd *FreeHead;
/**< First BD in the free group */
XEmacPs_Bd *PreHead;/**< First BD in the pre-work group */
XEmacPs_Bd *HwHead; /**< First BD in the work group */
XEmacPs_Bd *HwTail; /**< Last BD in the work group */
XEmacPs_Bd *PostHead;
/**< First BD in the post-work group */
XEmacPs_Bd *BdaRestart;
/**< BDA to load when channel is started */
volatile u32 HwCnt; /**< Number of BDs in work group */
u32 PreCnt; /**< Number of BDs in pre-work group */
u32 FreeCnt; /**< Number of allocatable BDs in the free group */
u32 PostCnt; /**< Number of BDs in post-work group */
u32 AllCnt; /**< Total Number of BDs for channel */
} XEmacPs_BdRing;
/***************** Macros (Inline Functions) Definitions *********************/
/*****************************************************************************/
/**
* Use this macro at initialization time to determine how many BDs will fit
* in a BD list within the given memory constraints.
*
* The results of this macro can be provided to XEmacPs_BdRingCreate().
*
* @param Alignment specifies what byte alignment the BDs must fall on and
* must be a power of 2 to get an accurate calculation (32, 64, 128,...)
* @param Bytes is the number of bytes to be used to store BDs.
*
* @return Number of BDs that can fit in the given memory area
*
* @note
* C-style signature:
* u32 XEmacPs_BdRingCntCalc(u32 Alignment, u32 Bytes)
*
******************************************************************************/
#define XEmacPs_BdRingCntCalc(Alignment, Bytes) \
(u32)((Bytes) / (sizeof(XEmacPs_Bd)))
/*****************************************************************************/
/**
* Use this macro at initialization time to determine how many bytes of memory
* is required to contain a given number of BDs at a given alignment.
*
* @param Alignment specifies what byte alignment the BDs must fall on. This
* parameter must be a power of 2 to get an accurate calculation (32, 64,
* 128,...)
* @param NumBd is the number of BDs to calculate memory size requirements for
*
* @return The number of bytes of memory required to create a BD list with the
* given memory constraints.
*
* @note
* C-style signature:
* u32 XEmacPs_BdRingMemCalc(u32 Alignment, u32 NumBd)
*
******************************************************************************/
#define XEmacPs_BdRingMemCalc(Alignment, NumBd) \
(u32)(sizeof(XEmacPs_Bd) * (NumBd))
/****************************************************************************/
/**
* Return the total number of BDs allocated by this channel with
* XEmacPs_BdRingCreate().
*
* @param RingPtr is the DMA channel to operate on.
*
* @return The total number of BDs allocated for this channel.
*
* @note
* C-style signature:
* u32 XEmacPs_BdRingGetCnt(XEmacPs_BdRing* RingPtr)
*
*****************************************************************************/
#define XEmacPs_BdRingGetCnt(RingPtr) ((RingPtr)->AllCnt)
/****************************************************************************/
/**
* Return the number of BDs allocatable with XEmacPs_BdRingAlloc() for pre-
* processing.
*
* @param RingPtr is the DMA channel to operate on.
*
* @return The number of BDs currently allocatable.
*
* @note
* C-style signature:
* u32 XEmacPs_BdRingGetFreeCnt(XEmacPs_BdRing* RingPtr)
*
*****************************************************************************/
#define XEmacPs_BdRingGetFreeCnt(RingPtr) ((RingPtr)->FreeCnt)
/****************************************************************************/
/**
* Return the next BD from BdPtr in a list.
*
* @param RingPtr is the DMA channel to operate on.
* @param BdPtr is the BD to operate on.
*
* @return The next BD in the list relative to the BdPtr parameter.
*
* @note
* C-style signature:
* XEmacPs_Bd *XEmacPs_BdRingNext(XEmacPs_BdRing* RingPtr,
* XEmacPs_Bd *BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdRingNext(RingPtr, BdPtr) \
(((UINTPTR)((void *)(BdPtr)) >= (RingPtr)->HighBdAddr) ? \
(XEmacPs_Bd*)((void*)(RingPtr)->BaseBdAddr) : \
(XEmacPs_Bd*)((UINTPTR)((void *)(BdPtr)) + (RingPtr)->Separation))
/****************************************************************************/
/**
* Return the previous BD from BdPtr in the list.
*
* @param RingPtr is the DMA channel to operate on.
* @param BdPtr is the BD to operate on
*
* @return The previous BD in the list relative to the BdPtr parameter.
*
* @note
* C-style signature:
* XEmacPs_Bd *XEmacPs_BdRingPrev(XEmacPs_BdRing* RingPtr,
* XEmacPs_Bd *BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdRingPrev(RingPtr, BdPtr) \
(((UINTPTR)(BdPtr) <= (RingPtr)->BaseBdAddr) ? \
(XEmacPs_Bd*)(RingPtr)->HighBdAddr : \
(XEmacPs_Bd*)((UINTPTR)(BdPtr) - (RingPtr)->Separation))
/************************** Function Prototypes ******************************/
/*
* Scatter gather DMA related functions in xemacps_bdring.c
*/
LONG XEmacPs_BdRingCreate(XEmacPs_BdRing * RingPtr, UINTPTR PhysAddr,
UINTPTR VirtAddr, u32 Alignment, u32 BdCount);
LONG XEmacPs_BdRingClone(XEmacPs_BdRing * RingPtr, XEmacPs_Bd * SrcBdPtr,
u8 Direction);
LONG XEmacPs_BdRingAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
XEmacPs_Bd ** BdSetPtr);
LONG XEmacPs_BdRingUnAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
XEmacPs_Bd * BdSetPtr);
LONG XEmacPs_BdRingToHw(XEmacPs_BdRing * RingPtr, u32 NumBd,
XEmacPs_Bd * BdSetPtr);
LONG XEmacPs_BdRingFree(XEmacPs_BdRing * RingPtr, u32 NumBd,
XEmacPs_Bd * BdSetPtr);
u32 XEmacPs_BdRingFromHwTx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
XEmacPs_Bd ** BdSetPtr);
u32 XEmacPs_BdRingFromHwRx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
XEmacPs_Bd ** BdSetPtr);
LONG XEmacPs_BdRingCheck(XEmacPs_BdRing * RingPtr, u8 Direction);
void XEmacPs_BdRingPtrReset(XEmacPs_BdRing * RingPtr, void *virtaddrloc);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macros */
/** @} */
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/xemacps_hw.h
+664
View File
@@ -0,0 +1,664 @@
/******************************************************************************
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xemacps_hw.h
* @addtogroup emacps Overview
* @{
*
* This header file contains identifiers and low-level driver functions (or
* macros) that can be used to access the PS Ethernet MAC (XEmacPs) device.
* High-level driver functions are defined in xemacps.h.
*
* @note
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a wsy 01/10/10 First release.
* 1.02a asa 11/05/12 Added hash defines for DMACR burst length configuration.
* 1.05a kpc 28/06/13 Added XEmacPs_ResetHw function prototype
* 1.06a asa 11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff
* to 0x1fff. This fixes the CR#744902.
* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp GEM specification.
* 3.0 kvn 12/16/14 Changed name of XEMACPS_NWCFG_LENGTHERRDSCRD_MASK to
* XEMACPS_NWCFG_LENERRDSCRD_MASK as it exceeds 31 characters.
* 3.0 kpc 1/23/15 Corrected the extended descriptor macro values.
* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
* 3.0 hk 03/18/15 Added support for jumbo frames.
* Remove "used bit set" from TX error interrupt masks.
* 3.1 hk 08/10/15 Update upper 32 bit tx and rx queue ptr register offsets.
* 3.2 hk 02/22/16 Added SGMII support for Zynq Ultrascale+ MPSoC.
* 3.8 hk 09/17/18 Fix PTP interrupt masks.
* 3.9 hk 01/23/19 Add RX watermark support
* 3.10 hk 05/16/19 Clear status registers properly in reset
* 3.18 sne 01/11/23 Add PCS control and status registers information.
* </pre>
*
******************************************************************************/
#ifndef XEMACPS_HW_H /* prevent circular inclusions */
#define XEMACPS_HW_H /* by using protection macros */
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xil_io.h"
#ifdef __cplusplus
extern "C" {
#endif
/************************** Constant Definitions *****************************/
#define XEMACPS_MAX_MAC_ADDR 4U /**< Maxmum number of mac address
supported */
#define XEMACPS_MAX_TYPE_ID 4U /**< Maxmum number of type id supported */
#ifdef __aarch64__
#define XEMACPS_BD_ALIGNMENT 64U /**< Minimum buffer descriptor alignment
on the local bus */
#else
#define XEMACPS_BD_ALIGNMENT 4U /**< Minimum buffer descriptor alignment
on the local bus */
#endif
#define XEMACPS_RX_BUF_ALIGNMENT 4U /**< Minimum buffer alignment when using
options that impose alignment
restrictions on the buffer data on
the local bus */
/** @name Direction identifiers
*
* These are used by several functions and callbacks that need
* to specify whether an operation specifies a send or receive channel.
* @{
*/
#define XEMACPS_SEND 1U /**< send direction */
#define XEMACPS_RECV 2U /**< receive direction */
/*@}*/
/** @name MDC clock division
* currently supporting 8, 16, 32, 48, 64, 96, 128, 224.
* @{
*/
typedef enum { MDC_DIV_8 = 0U, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48,
MDC_DIV_64, MDC_DIV_96, MDC_DIV_128, MDC_DIV_224
} XEmacPs_MdcDiv;
/*@}*/
#define XEMACPS_RX_BUF_SIZE 1536U /**< Specify the receive buffer size in
bytes, 64, 128, ... 10240 */
#define XEMACPS_RX_BUF_SIZE_JUMBO 10240U
#define XEMACPS_RX_BUF_UNIT 64U /**< Number of receive buffer bytes as a
unit, this is HW setup */
#define XEMACPS_MAX_RXBD 128U /**< Size of RX buffer descriptor queues */
#define XEMACPS_MAX_TXBD 128U /**< Size of TX buffer descriptor queues */
#define XEMACPS_MAX_HASH_BITS 64U /**< Maximum value for hash bits. 2**6 */
/* Register offset definitions. Unless otherwise noted, register access is
* 32 bit. Names are self explained here.
*/
#define XEMACPS_NWCTRL_OFFSET 0x00000000U /**< Network Control reg */
#define XEMACPS_NWCFG_OFFSET 0x00000004U /**< Network Config reg */
#define XEMACPS_NWSR_OFFSET 0x00000008U /**< Network Status reg */
#define XEMACPS_DMACR_OFFSET 0x00000010U /**< DMA Control reg */
#define XEMACPS_TXSR_OFFSET 0x00000014U /**< TX Status reg */
#define XEMACPS_RXQBASE_OFFSET 0x00000018U /**< RX Q Base address reg */
#define XEMACPS_TXQBASE_OFFSET 0x0000001CU /**< TX Q Base address reg */
#define XEMACPS_RXSR_OFFSET 0x00000020U /**< RX Status reg */
#define XEMACPS_ISR_OFFSET 0x00000024U /**< Interrupt Status reg */
#define XEMACPS_IER_OFFSET 0x00000028U /**< Interrupt Enable reg */
#define XEMACPS_IDR_OFFSET 0x0000002CU /**< Interrupt Disable reg */
#define XEMACPS_IMR_OFFSET 0x00000030U /**< Interrupt Mask reg */
#define XEMACPS_PHYMNTNC_OFFSET 0x00000034U /**< Phy Maintaince reg */
#define XEMACPS_RXPAUSE_OFFSET 0x00000038U /**< RX Pause Time reg */
#define XEMACPS_TXPAUSE_OFFSET 0x0000003CU /**< TX Pause Time reg */
#define XEMACPS_JUMBOMAXLEN_OFFSET 0x00000048U /**< Jumbo max length reg */
#define XEMACPS_RXWATERMARK_OFFSET 0x0000007CU /**< RX watermark reg */
#define XEMACPS_HASHL_OFFSET 0x00000080U /**< Hash Low address reg */
#define XEMACPS_HASHH_OFFSET 0x00000084U /**< Hash High address reg */
#define XEMACPS_LADDR1L_OFFSET 0x00000088U /**< Specific1 addr low reg */
#define XEMACPS_LADDR1H_OFFSET 0x0000008CU /**< Specific1 addr high reg */
#define XEMACPS_LADDR2L_OFFSET 0x00000090U /**< Specific2 addr low reg */
#define XEMACPS_LADDR2H_OFFSET 0x00000094U /**< Specific2 addr high reg */
#define XEMACPS_LADDR3L_OFFSET 0x00000098U /**< Specific3 addr low reg */
#define XEMACPS_LADDR3H_OFFSET 0x0000009CU /**< Specific3 addr high reg */
#define XEMACPS_LADDR4L_OFFSET 0x000000A0U /**< Specific4 addr low reg */
#define XEMACPS_LADDR4H_OFFSET 0x000000A4U /**< Specific4 addr high reg */
#define XEMACPS_MATCH1_OFFSET 0x000000A8U /**< Type ID1 Match reg */
#define XEMACPS_MATCH2_OFFSET 0x000000ACU /**< Type ID2 Match reg */
#define XEMACPS_MATCH3_OFFSET 0x000000B0U /**< Type ID3 Match reg */
#define XEMACPS_MATCH4_OFFSET 0x000000B4U /**< Type ID4 Match reg */
#define XEMACPS_STRETCH_OFFSET 0x000000BCU /**< IPG Stretch reg */
#define XEMACPS_OCTTXL_OFFSET 0x00000100U /**< Octects transmitted Low
reg */
#define XEMACPS_OCTTXH_OFFSET 0x00000104U /**< Octects transmitted High
reg */
#define XEMACPS_TXCNT_OFFSET 0x00000108U /**< Error-free Frmaes
transmitted counter */
#define XEMACPS_TXBCCNT_OFFSET 0x0000010CU /**< Error-free Broadcast
Frames counter*/
#define XEMACPS_TXMCCNT_OFFSET 0x00000110U /**< Error-free Multicast
Frame counter */
#define XEMACPS_TXPAUSECNT_OFFSET 0x00000114U /**< Pause Frames Transmitted
Counter */
#define XEMACPS_TX64CNT_OFFSET 0x00000118U /**< Error-free 64 byte Frames
Transmitted counter */
#define XEMACPS_TX65CNT_OFFSET 0x0000011CU /**< Error-free 65-127 byte
Frames Transmitted
counter */
#define XEMACPS_TX128CNT_OFFSET 0x00000120U /**< Error-free 128-255 byte
Frames Transmitted
counter*/
#define XEMACPS_TX256CNT_OFFSET 0x00000124U /**< Error-free 256-511 byte
Frames transmitted
counter */
#define XEMACPS_TX512CNT_OFFSET 0x00000128U /**< Error-free 512-1023 byte
Frames transmitted
counter */
#define XEMACPS_TX1024CNT_OFFSET 0x0000012CU /**< Error-free 1024-1518 byte
Frames transmitted
counter */
#define XEMACPS_TX1519CNT_OFFSET 0x00000130U /**< Error-free larger than
1519 byte Frames
transmitted counter */
#define XEMACPS_TXURUNCNT_OFFSET 0x00000134U /**< TX under run error
counter */
#define XEMACPS_SNGLCOLLCNT_OFFSET 0x00000138U /**< Single Collision Frame
Counter */
#define XEMACPS_MULTICOLLCNT_OFFSET 0x0000013CU /**< Multiple Collision Frame
Counter */
#define XEMACPS_EXCESSCOLLCNT_OFFSET 0x00000140U /**< Excessive Collision Frame
Counter */
#define XEMACPS_LATECOLLCNT_OFFSET 0x00000144U /**< Late Collision Frame
Counter */
#define XEMACPS_TXDEFERCNT_OFFSET 0x00000148U /**< Deferred Transmission
Frame Counter */
#define XEMACPS_TXCSENSECNT_OFFSET 0x0000014CU /**< Transmit Carrier Sense
Error Counter */
#define XEMACPS_OCTRXL_OFFSET 0x00000150U /**< Octects Received register
Low */
#define XEMACPS_OCTRXH_OFFSET 0x00000154U /**< Octects Received register
High */
#define XEMACPS_RXCNT_OFFSET 0x00000158U /**< Error-free Frames
Received Counter */
#define XEMACPS_RXBROADCNT_OFFSET 0x0000015CU /**< Error-free Broadcast
Frames Received Counter */
#define XEMACPS_RXMULTICNT_OFFSET 0x00000160U /**< Error-free Multicast
Frames Received Counter */
#define XEMACPS_RXPAUSECNT_OFFSET 0x00000164U /**< Pause Frames
Received Counter */
#define XEMACPS_RX64CNT_OFFSET 0x00000168U /**< Error-free 64 byte Frames
Received Counter */
#define XEMACPS_RX65CNT_OFFSET 0x0000016CU /**< Error-free 65-127 byte
Frames Received Counter */
#define XEMACPS_RX128CNT_OFFSET 0x00000170U /**< Error-free 128-255 byte
Frames Received Counter */
#define XEMACPS_RX256CNT_OFFSET 0x00000174U /**< Error-free 256-512 byte
Frames Received Counter */
#define XEMACPS_RX512CNT_OFFSET 0x00000178U /**< Error-free 512-1023 byte
Frames Received Counter */
#define XEMACPS_RX1024CNT_OFFSET 0x0000017CU /**< Error-free 1024-1518 byte
Frames Received Counter */
#define XEMACPS_RX1519CNT_OFFSET 0x00000180U /**< Error-free 1519-max byte
Frames Received Counter */
#define XEMACPS_RXUNDRCNT_OFFSET 0x00000184U /**< Undersize Frames Received
Counter */
#define XEMACPS_RXOVRCNT_OFFSET 0x00000188U /**< Oversize Frames Received
Counter */
#define XEMACPS_RXJABCNT_OFFSET 0x0000018CU /**< Jabbers Received
Counter */
#define XEMACPS_RXFCSCNT_OFFSET 0x00000190U /**< Frame Check Sequence
Error Counter */
#define XEMACPS_RXLENGTHCNT_OFFSET 0x00000194U /**< Length Field Error
Counter */
#define XEMACPS_RXSYMBCNT_OFFSET 0x00000198U /**< Symbol Error Counter */
#define XEMACPS_RXALIGNCNT_OFFSET 0x0000019CU /**< Alignment Error Counter */
#define XEMACPS_RXRESERRCNT_OFFSET 0x000001A0U /**< Receive Resource Error
Counter */
#define XEMACPS_RXORCNT_OFFSET 0x000001A4U /**< Receive Overrun Counter */
#define XEMACPS_RXIPCCNT_OFFSET 0x000001A8U /**< IP header Checksum Error
Counter */
#define XEMACPS_RXTCPCCNT_OFFSET 0x000001ACU /**< TCP Checksum Error
Counter */
#define XEMACPS_RXUDPCCNT_OFFSET 0x000001B0U /**< UDP Checksum Error
Counter */
#define XEMACPS_LAST_OFFSET 0x000001B4U /**< Last statistic counter
offset, for clearing */
#define XEMACPS_1588_SEC_OFFSET 0x000001D0U /**< 1588 second counter */
#define XEMACPS_1588_NANOSEC_OFFSET 0x000001D4U /**< 1588 nanosecond counter */
#define XEMACPS_1588_ADJ_OFFSET 0x000001D8U /**< 1588 nanosecond
adjustment counter */
#define XEMACPS_1588_INC_OFFSET 0x000001DCU /**< 1588 nanosecond
increment counter */
#define XEMACPS_PTP_TXSEC_OFFSET 0x000001E0U /**< 1588 PTP transmit second
counter */
#define XEMACPS_PTP_TXNANOSEC_OFFSET 0x000001E4U /**< 1588 PTP transmit
nanosecond counter */
#define XEMACPS_PTP_RXSEC_OFFSET 0x000001E8U /**< 1588 PTP receive second
counter */
#define XEMACPS_PTP_RXNANOSEC_OFFSET 0x000001ECU /**< 1588 PTP receive
nanosecond counter */
#define XEMACPS_PTPP_TXSEC_OFFSET 0x000001F0U /**< 1588 PTP peer transmit
second counter */
#define XEMACPS_PTPP_TXNANOSEC_OFFSET 0x000001F4U /**< 1588 PTP peer transmit
nanosecond counter */
#define XEMACPS_PTPP_RXSEC_OFFSET 0x000001F8U /**< 1588 PTP peer receive
second counter */
#define XEMACPS_PTPP_RXNANOSEC_OFFSET 0x000001FCU /**< 1588 PTP peer receive
nanosecond counter */
#define XEMACPS_PCS_CONTROL_OFFSET 0x00000200U /** PCS control register */
#define XEMACPS_PCS_STATUS_OFFSET 0x00000204U /** PCS status register */
#define XEMACPS_INTQ1_STS_OFFSET 0x00000400U /**< Interrupt Q1 Status
reg */
#define XEMACPS_TXQ1BASE_OFFSET 0x00000440U /**< TX Q1 Base address
reg */
#define XEMACPS_RXQ1BASE_OFFSET 0x00000480U /**< RX Q1 Base address
reg */
#define XEMACPS_MSBBUF_TXQBASE_OFFSET 0x000004C8U /**< MSB Buffer TX Q Base
reg */
#define XEMACPS_MSBBUF_RXQBASE_OFFSET 0x000004D4U /**< MSB Buffer RX Q Base
reg */
#define XEMACPS_INTQ1_IER_OFFSET 0x00000600U /**< Interrupt Q1 Enable
reg */
#define XEMACPS_INTQ1_IDR_OFFSET 0x00000620U /**< Interrupt Q1 Disable
reg */
#define XEMACPS_INTQ1_IMR_OFFSET 0x00000640U /**< Interrupt Q1 Mask
reg */
/* Define some bit positions for registers. */
/** @name network control register bit definitions
* @{
*/
#define XEMACPS_NWCTRL_FLUSH_DPRAM_MASK 0x00040000U /**< Flush a packet from
Rx SRAM */
#define XEMACPS_NWCTRL_ZEROPAUSETX_MASK 0x00000800U /**< Transmit zero quantum
pause frame */
#define XEMACPS_NWCTRL_PAUSETX_MASK 0x00000800U /**< Transmit pause frame */
#define XEMACPS_NWCTRL_HALTTX_MASK 0x00000400U /**< Halt transmission
after current frame */
#define XEMACPS_NWCTRL_STARTTX_MASK 0x00000200U /**< Start tx (tx_go) */
#define XEMACPS_NWCTRL_STATWEN_MASK 0x00000080U /**< Enable writing to
stat counters */
#define XEMACPS_NWCTRL_STATINC_MASK 0x00000040U /**< Increment statistic
registers */
#define XEMACPS_NWCTRL_STATCLR_MASK 0x00000020U /**< Clear statistic
registers */
#define XEMACPS_NWCTRL_MDEN_MASK 0x00000010U /**< Enable MDIO port */
#define XEMACPS_NWCTRL_TXEN_MASK 0x00000008U /**< Enable transmit */
#define XEMACPS_NWCTRL_RXEN_MASK 0x00000004U /**< Enable receive */
#define XEMACPS_NWCTRL_LOOPEN_MASK 0x00000002U /**< local loopback */
/*@}*/
/** @name network configuration register bit definitions
* @{
*/
#define XEMACPS_NWCFG_BADPREAMBEN_MASK 0x20000000U /**< disable rejection of
non-standard preamble */
#define XEMACPS_NWCFG_IPDSTRETCH_MASK 0x10000000U /**< enable transmit IPG */
#define XEMACPS_NWCFG_SGMIIEN_MASK 0x08000000U /**< SGMII Enable */
#define XEMACPS_NWCFG_FCSIGNORE_MASK 0x04000000U /**< disable rejection of
FCS error */
#define XEMACPS_NWCFG_HDRXEN_MASK 0x02000000U /**< RX half duplex */
#define XEMACPS_NWCFG_RXCHKSUMEN_MASK 0x01000000U /**< enable RX checksum
offload */
#define XEMACPS_NWCFG_PAUSECOPYDI_MASK 0x00800000U /**< Do not copy pause
Frames to memory */
#define XEMACPS_NWCFG_DWIDTH_64_MASK 0x00200000U /**< 64 bit Data bus width */
#define XEMACPS_NWCFG_MDC_SHIFT_MASK 18U /**< shift bits for MDC */
#define XEMACPS_NWCFG_MDCCLKDIV_MASK 0x001C0000U /**< MDC Mask PCLK divisor */
#define XEMACPS_NWCFG_FCSREM_MASK 0x00020000U /**< Discard FCS from
received frames */
#define XEMACPS_NWCFG_LENERRDSCRD_MASK 0x00010000U
/**< RX length error discard */
#define XEMACPS_NWCFG_RXOFFS_MASK 0x0000C000U /**< RX buffer offset */
#define XEMACPS_NWCFG_PAUSEEN_MASK 0x00002000U /**< Enable pause RX */
#define XEMACPS_NWCFG_RETRYTESTEN_MASK 0x00001000U /**< Retry test */
#define XEMACPS_NWCFG_XTADDMACHEN_MASK 0x00000200U
/**< External address match enable */
#define XEMACPS_NWCFG_PCSSEL_MASK 0x00000800U /**< PCS Select */
#define XEMACPS_NWCFG_1000_MASK 0x00000400U /**< 1000 Mbps */
#define XEMACPS_NWCFG_1536RXEN_MASK 0x00000100U /**< Enable 1536 byte
frames reception */
#define XEMACPS_NWCFG_UCASTHASHEN_MASK 0x00000080U /**< Receive unicast hash
frames */
#define XEMACPS_NWCFG_MCASTHASHEN_MASK 0x00000040U /**< Receive multicast hash
frames */
#define XEMACPS_NWCFG_BCASTDI_MASK 0x00000020U /**< Do not receive
broadcast frames */
#define XEMACPS_NWCFG_COPYALLEN_MASK 0x00000010U /**< Copy all frames */
#define XEMACPS_NWCFG_JUMBO_MASK 0x00000008U /**< Jumbo frames */
#define XEMACPS_NWCFG_NVLANDISC_MASK 0x00000004U /**< Receive only VLAN
frames */
#define XEMACPS_NWCFG_FDEN_MASK 0x00000002U/**< full duplex */
#define XEMACPS_NWCFG_100_MASK 0x00000001U /**< 100 Mbps */
#define XEMACPS_NWCFG_RESET_MASK 0x00080000U/**< reset value */
/*@}*/
/** @name network status register bit definitaions
* @{
*/
#define XEMACPS_NWSR_MDIOIDLE_MASK 0x00000004U /**< PHY management idle */
#define XEMACPS_NWSR_MDIO_MASK 0x00000002U /**< Status of mdio_in */
/*@}*/
/** @name MAC address register word 1 mask
* @{
*/
#define XEMACPS_LADDR_MACH_MASK 0x0000FFFFU /**< Address bits[47:32]
bit[31:0] are in BOTTOM */
/*@}*/
/** @name DMA control register bit definitions
* @{
*/
#define XEMACPS_DMACR_ADDR_WIDTH_64 0x40000000U /**< 64 bit address bus */
#define XEMACPS_DMACR_TXEXTEND_MASK 0x20000000U /**< Tx Extended desc mode */
#define XEMACPS_DMACR_RXEXTEND_MASK 0x10000000U /**< Rx Extended desc mode */
#define XEMACPS_DMACR_RXBUF_MASK 0x00FF0000U /**< Mask bit for RX buffer
size */
#define XEMACPS_DMACR_RXBUF_SHIFT 16U /**< Shift bit for RX buffer
size */
#define XEMACPS_DMACR_TCPCKSUM_MASK 0x00000800U /**< enable/disable TX
checksum offload */
#define XEMACPS_DMACR_TXSIZE_MASK 0x00000400U /**< TX buffer memory size */
#define XEMACPS_DMACR_RXSIZE_MASK 0x00000300U /**< RX buffer memory size */
#define XEMACPS_DMACR_ENDIAN_MASK 0x00000080U /**< endian configuration */
#define XEMACPS_DMACR_BLENGTH_MASK 0x0000001FU /**< buffer burst length */
#define XEMACPS_DMACR_SINGLE_AHB_BURST 0x00000001U /**< single AHB bursts */
#define XEMACPS_DMACR_INCR4_AHB_BURST 0x00000004U /**< 4 bytes AHB bursts */
#define XEMACPS_DMACR_INCR8_AHB_BURST 0x00000008U /**< 8 bytes AHB bursts */
#define XEMACPS_DMACR_INCR16_AHB_BURST 0x00000010U /**< 16 bytes AHB bursts */
/*@}*/
/** @name transmit status register bit definitions
* @{
*/
#define XEMACPS_TXSR_HRESPNOK_MASK 0x00000100U /**< Transmit hresp not OK */
#define XEMACPS_TXSR_URUN_MASK 0x00000040U /**< Transmit underrun */
#define XEMACPS_TXSR_TXCOMPL_MASK 0x00000020U /**< Transmit completed OK */
#define XEMACPS_TXSR_BUFEXH_MASK 0x00000010U /**< Transmit buffs exhausted
mid frame */
#define XEMACPS_TXSR_TXGO_MASK 0x00000008U /**< Status of go flag */
#define XEMACPS_TXSR_RXOVR_MASK 0x00000004U /**< Retry limit exceeded */
#define XEMACPS_TXSR_FRAMERX_MASK 0x00000002U /**< Collision tx frame */
#define XEMACPS_TXSR_USEDREAD_MASK 0x00000001U /**< TX buffer used bit set */
#define XEMACPS_TXSR_ERROR_MASK ((u32)XEMACPS_TXSR_HRESPNOK_MASK | \
(u32)XEMACPS_TXSR_URUN_MASK | \
(u32)XEMACPS_TXSR_BUFEXH_MASK | \
(u32)XEMACPS_TXSR_RXOVR_MASK | \
(u32)XEMACPS_TXSR_FRAMERX_MASK | \
(u32)XEMACPS_TXSR_USEDREAD_MASK)
/*@}*/
/**
* @name receive status register bit definitions
* @{
*/
#define XEMACPS_RXSR_HRESPNOK_MASK 0x00000008U /**< Receive hresp not OK */
#define XEMACPS_RXSR_RXOVR_MASK 0x00000004U /**< Receive overrun */
#define XEMACPS_RXSR_FRAMERX_MASK 0x00000002U /**< Frame received OK */
#define XEMACPS_RXSR_BUFFNA_MASK 0x00000001U /**< RX buffer used bit set */
#define XEMACPS_RXSR_ERROR_MASK ((u32)XEMACPS_RXSR_HRESPNOK_MASK | \
(u32)XEMACPS_RXSR_RXOVR_MASK | \
(u32)XEMACPS_RXSR_BUFFNA_MASK)
#define XEMACPS_SR_ALL_MASK 0xFFFFFFFFU /**< Mask for full register */
/*@}*/
/**
* @name PCS control register bit definitions
* @{
*/
#define XEMACPS_PCS_CON_AUTO_NEG_MASK 0x00001000U /**< Auto-negotiation */
/*@}*/
/**
* @name PCS status register bit definitions
* @{
*/
#define XEMACPS_PCS_STATUS_LINK_STATUS_MASK 0x00000004U /**< Link status */
/*@}*/
/**
* @name Interrupt Q1 status register bit definitions
* @{
*/
#define XEMACPS_INTQ1SR_TXCOMPL_MASK 0x00000080U /**< Transmit completed OK */
#define XEMACPS_INTQ1SR_TXERR_MASK 0x00000040U /**< Transmit AMBA Error */
#define XEMACPS_INTQ1_IXR_ALL_MASK ((u32)XEMACPS_INTQ1SR_TXCOMPL_MASK | \
(u32)XEMACPS_INTQ1SR_TXERR_MASK)
/*@}*/
/**
* @name interrupts bit definitions
* Bits definitions are same in XEMACPS_ISR_OFFSET,
* XEMACPS_IER_OFFSET, XEMACPS_IDR_OFFSET, and XEMACPS_IMR_OFFSET
* @{
*/
#define XEMACPS_IXR_PTPPSTX_MASK 0x02000000U /**< PTP Pdelay_resp TXed */
#define XEMACPS_IXR_PTPPDRTX_MASK 0x01000000U /**< PTP Pdelay_req TXed */
#define XEMACPS_IXR_PTPPSRX_MASK 0x00800000U /**< PTP Pdelay_resp RXed */
#define XEMACPS_IXR_PTPPDRRX_MASK 0x00400000U /**< PTP Pdelay_req RXed */
#define XEMACPS_IXR_PTPSTX_MASK 0x00200000U /**< PTP Sync TXed */
#define XEMACPS_IXR_PTPDRTX_MASK 0x00100000U /**< PTP Delay_req TXed */
#define XEMACPS_IXR_PTPSRX_MASK 0x00080000U /**< PTP Sync RXed */
#define XEMACPS_IXR_PTPDRRX_MASK 0x00040000U /**< PTP Delay_req RXed */
#define XEMACPS_IXR_PAUSETX_MASK 0x00004000U /**< Pause frame transmitted */
#define XEMACPS_IXR_PAUSEZERO_MASK 0x00002000U /**< Pause time has reached
zero */
#define XEMACPS_IXR_PAUSENZERO_MASK 0x00001000U /**< Pause frame received */
#define XEMACPS_IXR_HRESPNOK_MASK 0x00000800U /**< hresp not ok */
#define XEMACPS_IXR_RXOVR_MASK 0x00000400U /**< Receive overrun occurred */
#define XEMACPS_IXR_TXCOMPL_MASK 0x00000080U /**< Frame transmitted ok */
#define XEMACPS_IXR_TXEXH_MASK 0x00000040U /**< Transmit err occurred or
no buffers*/
#define XEMACPS_IXR_RETRY_MASK 0x00000020U /**< Retry limit exceeded */
#define XEMACPS_IXR_URUN_MASK 0x00000010U /**< Transmit underrun */
#define XEMACPS_IXR_TXUSED_MASK 0x00000008U /**< Tx buffer used bit read */
#define XEMACPS_IXR_RXUSED_MASK 0x00000004U /**< Rx buffer used bit read */
#define XEMACPS_IXR_FRAMERX_MASK 0x00000002U /**< Frame received ok */
#define XEMACPS_IXR_MGMNT_MASK 0x00000001U /**< PHY management complete */
#define XEMACPS_IXR_ALL_MASK 0x00007FFFU /**< Everything! */
#define XEMACPS_IXR_TX_ERR_MASK ((u32)XEMACPS_IXR_TXEXH_MASK | \
(u32)XEMACPS_IXR_RETRY_MASK | \
(u32)XEMACPS_IXR_URUN_MASK)
#define XEMACPS_IXR_RX_ERR_MASK ((u32)XEMACPS_IXR_HRESPNOK_MASK | \
(u32)XEMACPS_IXR_RXUSED_MASK | \
(u32)XEMACPS_IXR_RXOVR_MASK)
/*@}*/
/** @name PHY Maintenance bit definitions
* @{
*/
#define XEMACPS_PHYMNTNC_OP_MASK 0x40020000U /**< operation mask bits */
#define XEMACPS_PHYMNTNC_OP_R_MASK 0x20000000U /**< read operation */
#define XEMACPS_PHYMNTNC_OP_W_MASK 0x10000000U /**< write operation */
#define XEMACPS_PHYMNTNC_ADDR_MASK 0x0F800000U /**< Address bits */
#define XEMACPS_PHYMNTNC_REG_MASK 0x007C0000U /**< register bits */
#define XEMACPS_PHYMNTNC_DATA_MASK 0x00000FFFU /**< data bits */
#define XEMACPS_PHYMNTNC_PHAD_SHFT_MSK 23U /**< Shift bits for PHYAD */
#define XEMACPS_PHYMNTNC_PREG_SHFT_MSK 18U /**< Shift bits for PHREG */
/*@}*/
/** @name RX watermark bit definitions
* @{
*/
#define XEMACPS_RXWM_HIGH_MASK 0x0000FFFFU /**< RXWM high mask */
#define XEMACPS_RXWM_LOW_MASK 0xFFFF0000U /**< RXWM low mask */
#define XEMACPS_RXWM_LOW_SHFT_MSK 16U /**< Shift for RXWM low */
/*@}*/
/* Transmit buffer descriptor status words offset
* @{
*/
#define XEMACPS_BD_ADDR_OFFSET 0x00000000U /**< word 0/addr of BDs */
#define XEMACPS_BD_STAT_OFFSET 0x00000004U /**< word 1/status of BDs */
#define XEMACPS_BD_ADDR_HI_OFFSET 0x00000008U /**< word 2/addr of BDs */
/*
* @}
*/
/* Transmit buffer descriptor status words bit positions.
* Transmit buffer descriptor consists of two 32-bit registers,
* the first - word0 contains a 32-bit address pointing to the location of
* the transmit data.
* The following register - word1, consists of various information to control
* the XEmacPs transmit process. After transmit, this is updated with status
* information, whether the frame was transmitted OK or why it had failed.
* @{
*/
#define XEMACPS_TXBUF_USED_MASK 0x80000000U /**< Used bit. */
#define XEMACPS_TXBUF_WRAP_MASK 0x40000000U /**< Wrap bit, last descriptor */
#define XEMACPS_TXBUF_RETRY_MASK 0x20000000U /**< Retry limit exceeded */
#define XEMACPS_TXBUF_URUN_MASK 0x10000000U /**< Transmit underrun occurred */
#define XEMACPS_TXBUF_EXH_MASK 0x08000000U /**< Buffers exhausted */
#define XEMACPS_TXBUF_TCP_MASK 0x04000000U /**< Late collision. */
#define XEMACPS_TXBUF_NOCRC_MASK 0x00010000U /**< No CRC */
#define XEMACPS_TXBUF_LAST_MASK 0x00008000U /**< Last buffer */
#define XEMACPS_TXBUF_LEN_MASK 0x00003FFFU /**< Mask for length field */
/*
* @}
*/
/* Receive buffer descriptor status words bit positions.
* Receive buffer descriptor consists of two 32-bit registers,
* the first - word0 contains a 32-bit word aligned address pointing to the
* address of the buffer. The lower two bits make up the wrap bit indicating
* the last descriptor and the ownership bit to indicate it has been used by
* the XEmacPs.
* The following register - word1, contains status information regarding why
* the frame was received (the filter match condition) as well as other
* useful info.
* @{
*/
#define XEMACPS_RXBUF_BCAST_MASK 0x80000000U /**< Broadcast frame */
#define XEMACPS_RXBUF_MULTIHASH_MASK 0x40000000U /**< Multicast hashed frame */
#define XEMACPS_RXBUF_UNIHASH_MASK 0x20000000U /**< Unicast hashed frame */
#define XEMACPS_RXBUF_EXH_MASK 0x08000000U /**< buffer exhausted */
#define XEMACPS_RXBUF_AMATCH_MASK 0x06000000U /**< Specific address
matched */
#define XEMACPS_RXBUF_IDFOUND_MASK 0x01000000U /**< Type ID matched */
#define XEMACPS_RXBUF_IDMATCH_MASK 0x00C00000U /**< ID matched mask */
#define XEMACPS_RXBUF_VLAN_MASK 0x00200000U /**< VLAN tagged */
#define XEMACPS_RXBUF_PRI_MASK 0x00100000U /**< Priority tagged */
#define XEMACPS_RXBUF_VPRI_MASK 0x000E0000U /**< Vlan priority */
#define XEMACPS_RXBUF_CFI_MASK 0x00010000U /**< CFI frame */
#define XEMACPS_RXBUF_EOF_MASK 0x00008000U /**< End of frame. */
#define XEMACPS_RXBUF_SOF_MASK 0x00004000U /**< Start of frame. */
#define XEMACPS_RXBUF_LEN_MASK 0x00001FFFU /**< Mask for length field */
#define XEMACPS_RXBUF_LEN_JUMBO_MASK 0x00003FFFU /**< Mask for jumbo length */
#define XEMACPS_RXBUF_WRAP_MASK 0x00000002U /**< Wrap bit, last BD */
#define XEMACPS_RXBUF_NEW_MASK 0x00000001U /**< Used bit.. */
#define XEMACPS_RXBUF_ADD_MASK 0xFFFFFFFCU /**< Mask for address */
/*
* @}
*/
/*
* Define appropriate I/O access method to memory mapped I/O or other
* interface if necessary.
*/
#define XEmacPs_In32 Xil_In32
#define XEmacPs_Out32 Xil_Out32
/****************************************************************************/
/**
*
* Read the given register.
*
* @param BaseAddress is the base address of the device
* @param RegOffset is the register offset to be read
*
* @return The 32-bit value of the register
*
* @note
* C-style signature:
* u32 XEmacPs_ReadReg(u32 BaseAddress, u32 RegOffset)
*
*****************************************************************************/
#define XEmacPs_ReadReg(BaseAddress, RegOffset) \
XEmacPs_In32((BaseAddress) + (u32)(RegOffset))
/****************************************************************************/
/**
*
* Write the given register.
*
* @param BaseAddress is the base address of the device
* @param RegOffset is the register offset to be written
* @param Data is the 32-bit value to write to the register
*
* @return None.
*
* @note
* C-style signature:
* void XEmacPs_WriteReg(u32 BaseAddress, u32 RegOffset,
* u32 Data)
*
*****************************************************************************/
#define XEmacPs_WriteReg(BaseAddress, RegOffset, Data) \
XEmacPs_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data))
/************************** Function Prototypes *****************************/
/*
* Perform reset operation to the emacps interface
*/
void XEmacPs_ResetHw(u32 BaseAddr);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/** @} */
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/xenv.h
+169
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@@ -0,0 +1,169 @@
/******************************************************************************
* Copyright (c) 2002 - 2021 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xenv.h
*
* Defines common services that are typically found in a host operating.
* environment. This include file simply includes an OS specific file based
* on the compile-time constant BUILD_ENV_*, where * is the name of the target
* environment.
*
* All services are defined as macros.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00b ch 10/24/02 Added XENV_LINUX
* 1.00a rmm 04/17/02 First release
* </pre>
*
******************************************************************************/
/**
*@cond nocomments
*/
#ifndef XENV_H /* prevent circular inclusions */
#define XENV_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/*
* Select which target environment we are operating under
*/
/* VxWorks target environment */
#if defined XENV_VXWORKS
#include "xenv_vxworks.h"
/* Linux target environment */
#elif defined XENV_LINUX
#include "xenv_linux.h"
/* Unit test environment */
#elif defined XENV_UNITTEST
#include "ut_xenv.h"
/* Integration test environment */
#elif defined XENV_INTTEST
#include "int_xenv.h"
/* Standalone environment selected */
#else
#include "xenv_standalone.h"
#endif
/*
* The following comments specify the types and macro wrappers that are
* expected to be defined by the target specific header files
*/
/**************************** Type Definitions *******************************/
/*****************************************************************************/
/**
*
* XENV_TIME_STAMP
*
* A structure that contains a time stamp used by other time stamp macros
* defined below. This structure is processor dependent.
*/
/***************** Macros (Inline Functions) Definitions *********************/
/*****************************************************************************/
/**
*
* XENV_MEM_COPY(void *DestPtr, void *SrcPtr, unsigned Bytes)
*
* Copies a non-overlapping block of memory.
*
* @param DestPtr is the destination address to copy data to.
* @param SrcPtr is the source address to copy data from.
* @param Bytes is the number of bytes to copy.
*
* @return None
*/
/*****************************************************************************/
/**
*
* XENV_MEM_FILL(void *DestPtr, char Data, unsigned Bytes)
*
* Fills an area of memory with constant data.
*
* @param DestPtr is the destination address to set.
* @param Data contains the value to set.
* @param Bytes is the number of bytes to set.
*
* @return None
*/
/*****************************************************************************/
/**
*
* XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
*
* Samples the processor's or external timer's time base counter.
*
* @param StampPtr is the storage for the retrieved time stamp.
*
* @return None
*/
/*****************************************************************************/
/**
*
* XENV_TIME_STAMP_DELTA_US(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
*
* Computes the delta between the two time stamps.
*
* @param Stamp1Ptr - First sampled time stamp.
* @param Stamp1Ptr - Sedond sampled time stamp.
*
* @return An unsigned int value with units of microseconds.
*/
/*****************************************************************************/
/**
*
* XENV_TIME_STAMP_DELTA_MS(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
*
* Computes the delta between the two time stamps.
*
* @param Stamp1Ptr - First sampled time stamp.
* @param Stamp1Ptr - Sedond sampled time stamp.
*
* @return An unsigned int value with units of milliseconds.
*/
/*****************************************************************************//**
*
* XENV_USLEEP(unsigned delay)
*
* Delay the specified number of microseconds.
*
* @param delay is the number of microseconds to delay.
*
* @return None
*/
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/**
*@endcond
*/
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/xenv_standalone.h
+350
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@@ -0,0 +1,350 @@
/******************************************************************************
* Copyright (c) 2002 - 2021 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xenv_standalone.h
*
* Defines common services specified by xenv.h.
*
* @note
* This file is not intended to be included directly by driver code.
* Instead, the generic xenv.h file is intended to be included by driver
* code.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a wgr 02/28/07 Added cache handling macros.
* 1.00a wgr 02/27/07 Simplified code. Deprecated old-style macro names.
* 1.00a rmm 01/24/06 Implemented XENV_USLEEP. Assume implementation is being
* used under Xilinx standalone BSP.
* 1.00a xd 11/03/04 Improved support for doxygen.
* 1.00a rmm 03/21/02 First release
* 1.00a wgr 03/22/07 Converted to new coding style.
* 1.00a rpm 06/29/07 Added udelay macro for standalone
* 1.00a xd 07/19/07 Included xparameters.h as XPAR_ constants are referred
* to in MICROBLAZE section
* 1.00a ecm 09/19/08 updated for v7.20 of Microblaze, new functionality
*
* </pre>
*
*
******************************************************************************/
/**
*@cond nocomments
*/
#ifndef XENV_STANDALONE_H
#define XENV_STANDALONE_H
#include "xil_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
/******************************************************************************
*
* Get the processor dependent includes
*
******************************************************************************/
#include <string.h>
#if defined __MICROBLAZE__
# include "mb_interface.h"
# include "xparameters.h" /* XPAR constants used below in MB section */
#elif defined __PPC__
# include "sleep.h"
# include "xcache_l.h" /* also include xcache_l.h for caching macros */
#endif
/******************************************************************************
*
* MEMCPY / MEMSET related macros.
*
* The following are straight forward implementations of memset and memcpy.
*
* NOTE: memcpy may not work if source and target memory area are overlapping.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* Copies a non-overlapping block of memory.
*
* @param DestPtr
* Destination address to copy data to.
*
* @param SrcPtr
* Source address to copy data from.
*
* @param Bytes
* Number of bytes to copy.
*
* @return None.
*
* @note
* The use of XENV_MEM_COPY is deprecated. Use memcpy() instead.
*
* @note
* This implementation MAY BREAK work if source and target memory
* area are overlapping.
*
*****************************************************************************/
#define XENV_MEM_COPY(DestPtr, SrcPtr, Bytes) \
memcpy((void *) DestPtr, (const void *) SrcPtr, (size_t) Bytes)
/*****************************************************************************/
/**
*
* Fills an area of memory with constant data.
*
* @param DestPtr
* Destination address to copy data to.
*
* @param Data
* Value to set.
*
* @param Bytes
* Number of bytes to copy.
*
* @return None.
*
* @note
* The use of XENV_MEM_FILL is deprecated. Use memset() instead.
*
*****************************************************************************/
#define XENV_MEM_FILL(DestPtr, Data, Bytes) \
memset((void *) DestPtr, (s32) Data, (size_t) Bytes)
/******************************************************************************
*
* TIME related macros
*
******************************************************************************/
/**
* A structure that contains a time stamp used by other time stamp macros
* defined below. This structure is processor dependent.
*/
typedef s32 XENV_TIME_STAMP;
/*****************************************************************************/
/**
*
* Time is derived from the 64 bit PPC timebase register
*
* @param StampPtr is the storage for the retrieved time stamp.
*
* @return None.
*
* @note
*
* Signature: void XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
* <br><br>
* This macro must be implemented by the user.
*
*****************************************************************************/
#define XENV_TIME_STAMP_GET(StampPtr)
/*****************************************************************************/
/**
*
* This macro is not yet implemented and always returns 0.
*
* @param Stamp1Ptr is the first sampled time stamp.
* @param Stamp2Ptr is the second sampled time stamp.
*
* @return 0
*
* @note
*
* This macro must be implemented by the user.
*
*****************************************************************************/
#define XENV_TIME_STAMP_DELTA_US(Stamp1Ptr, Stamp2Ptr) (0)
/*****************************************************************************/
/**
*
* This macro is not yet implemented and always returns 0.
*
* @param Stamp1Ptr is the first sampled time stamp.
* @param Stamp2Ptr is the second sampled time stamp.
*
* @return 0
*
* @note
*
* This macro must be implemented by the user.
*
*****************************************************************************/
#define XENV_TIME_STAMP_DELTA_MS(Stamp1Ptr, Stamp2Ptr) (0)
/*****************************************************************************/
/**
* XENV_USLEEP(unsigned delay)
*
* Delay the specified number of microseconds. Not implemented without OS
* support.
*
* @param delay
* Number of microseconds to delay.
*
* @return None.
*
*****************************************************************************/
#ifdef __PPC__
#define XENV_USLEEP(delay) usleep(delay)
#define udelay(delay) usleep(delay)
#else
#define XENV_USLEEP(delay)
#define udelay(delay)
#endif
/******************************************************************************
*
* CACHE handling macros / mappings
*
******************************************************************************/
/******************************************************************************
*
* Processor independent macros
*
******************************************************************************/
#define XCACHE_ENABLE_CACHE() \
{ XCACHE_ENABLE_DCACHE(); XCACHE_ENABLE_ICACHE(); }
#define XCACHE_DISABLE_CACHE() \
{ XCACHE_DISABLE_DCACHE(); XCACHE_DISABLE_ICACHE(); }
/******************************************************************************
*
* MicroBlaze case
*
* NOTE: Currently the following macros will only work on systems that contain
* only ONE MicroBlaze processor. Also, the macros will only be enabled if the
* system is built using a xparameters.h file.
*
******************************************************************************/
#if defined __MICROBLAZE__
/* Check if MicroBlaze data cache was built into the core.
*/
#if (XPAR_MICROBLAZE_USE_DCACHE == 1)
# define XCACHE_ENABLE_DCACHE() microblaze_enable_dcache()
# define XCACHE_DISABLE_DCACHE() microblaze_disable_dcache()
# define XCACHE_INVALIDATE_DCACHE() microblaze_invalidate_dcache()
# define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len))
#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1)
# define XCACHE_FLUSH_DCACHE() microblaze_flush_dcache()
# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
microblaze_flush_dcache_range((s32)(Addr), (s32)(Len))
#else
# define XCACHE_FLUSH_DCACHE() microblaze_invalidate_dcache()
# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len))
#endif /*XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK*/
#else
# define XCACHE_ENABLE_DCACHE()
# define XCACHE_DISABLE_DCACHE()
# define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len)
# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len)
#endif /*XPAR_MICROBLAZE_USE_DCACHE*/
/* Check if MicroBlaze instruction cache was built into the core.
*/
#if (XPAR_MICROBLAZE_USE_ICACHE == 1)
# define XCACHE_ENABLE_ICACHE() microblaze_enable_icache()
# define XCACHE_DISABLE_ICACHE() microblaze_disable_icache()
# define XCACHE_INVALIDATE_ICACHE() microblaze_invalidate_icache()
# define XCACHE_INVALIDATE_ICACHE_RANGE(Addr, Len) \
microblaze_invalidate_icache_range((s32)(Addr), (s32)(Len))
#else
# define XCACHE_ENABLE_ICACHE()
# define XCACHE_DISABLE_ICACHE()
#endif /*XPAR_MICROBLAZE_USE_ICACHE*/
/******************************************************************************
*
* PowerPC case
*
* Note that the XCACHE_ENABLE_xxx functions are hardcoded to enable a
* specific memory region (0x80000001). Each bit (0-30) in the regions
* bitmask stands for 128MB of memory. Bit 31 stands for the upper 2GB
* range.
*
* regions --> cached address range
* ------------|--------------------------------------------------
* 0x80000000 | [0, 0x7FFFFFF]
* 0x00000001 | [0xF8000000, 0xFFFFFFFF]
* 0x80000001 | [0, 0x7FFFFFF],[0xF8000000, 0xFFFFFFFF]
*
******************************************************************************/
#elif defined __PPC__
#define XCACHE_ENABLE_DCACHE() XCache_EnableDCache(0x80000001)
#define XCACHE_DISABLE_DCACHE() XCache_DisableDCache()
#define XCACHE_ENABLE_ICACHE() XCache_EnableICache(0x80000001)
#define XCACHE_DISABLE_ICACHE() XCache_DisableICache()
#define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
XCache_InvalidateDCacheRange((u32)(Addr), (u32)(Len))
#define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
XCache_FlushDCacheRange((u32)(Addr), (u32)(Len))
#define XCACHE_INVALIDATE_ICACHE() XCache_InvalidateICache()
/******************************************************************************
*
* Unknown processor / architecture
*
******************************************************************************/
#else
/* #error "Unknown processor / architecture. Must be MicroBlaze or PowerPC." */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifndef XENV_STANDALONE_H */
/**
*@endcond
*/
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/xfpd_slcr.h
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/*******************************************************************************
* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*******************************************************************************/
#ifndef __XFPD_SLCR_H__
#define __XFPD_SLCR_H__
#ifdef __cplusplus
extern "C" {
#endif
/**
*@cond nocomments
*/
/**
* XfpdSlcr Base Address
*/
#define XFPD_SLCR_BASEADDR 0xFD610000UL
/**
* Register: XfpdSlcrWprot0
*/
#define XFPD_SLCR_WPROT0 ( ( XFPD_SLCR_BASEADDR ) + 0x00000000UL )
#define XFPD_SLCR_WPROT0_RSTVAL 0x00000001UL
#define XFPD_SLCR_WPROT0_ACT_SHIFT 0UL
#define XFPD_SLCR_WPROT0_ACT_WIDTH 1UL
#define XFPD_SLCR_WPROT0_ACT_MASK 0x00000001UL
#define XFPD_SLCR_WPROT0_ACT_DEFVAL 0x1UL
/**
* Register: XfpdSlcrCtrl
*/
#define XFPD_SLCR_CTRL ( ( XFPD_SLCR_BASEADDR ) + 0x00000004UL )
#define XFPD_SLCR_CTRL_RSTVAL 0x00000000UL
#define XFPD_SLCR_CTRL_SLVERR_EN_SHIFT 0UL
#define XFPD_SLCR_CTRL_SLVERR_EN_WIDTH 1UL
#define XFPD_SLCR_CTRL_SLVERR_EN_MASK 0x00000001UL
#define XFPD_SLCR_CTRL_SLVERR_EN_DEFVAL 0x0UL
/**
* Register: XfpdSlcrIsr
*/
#define XFPD_SLCR_ISR ( ( XFPD_SLCR_BASEADDR ) + 0x00000008UL )
#define XFPD_SLCR_ISR_RSTVAL 0x00000000UL
#define XFPD_SLCR_ISR_ADDR_DECD_ERR_SHIFT 0UL
#define XFPD_SLCR_ISR_ADDR_DECD_ERR_WIDTH 1UL
#define XFPD_SLCR_ISR_ADDR_DECD_ERR_MASK 0x00000001UL
#define XFPD_SLCR_ISR_ADDR_DECD_ERR_DEFVAL 0x0UL
/**
* Register: XfpdSlcrImr
*/
#define XFPD_SLCR_IMR ( ( XFPD_SLCR_BASEADDR ) + 0x0000000CUL )
#define XFPD_SLCR_IMR_RSTVAL 0x00000001UL
#define XFPD_SLCR_IMR_ADDR_DECD_ERR_SHIFT 0UL
#define XFPD_SLCR_IMR_ADDR_DECD_ERR_WIDTH 1UL
#define XFPD_SLCR_IMR_ADDR_DECD_ERR_MASK 0x00000001UL
#define XFPD_SLCR_IMR_ADDR_DECD_ERR_DEFVAL 0x1UL
/**
* Register: XfpdSlcrIer
*/
#define XFPD_SLCR_IER ( ( XFPD_SLCR_BASEADDR ) + 0x00000010UL )
#define XFPD_SLCR_IER_RSTVAL 0x00000000UL
#define XFPD_SLCR_IER_ADDR_DECD_ERR_SHIFT 0UL
#define XFPD_SLCR_IER_ADDR_DECD_ERR_WIDTH 1UL
#define XFPD_SLCR_IER_ADDR_DECD_ERR_MASK 0x00000001UL
#define XFPD_SLCR_IER_ADDR_DECD_ERR_DEFVAL 0x0UL
/**
* Register: XfpdSlcrIdr
*/
#define XFPD_SLCR_IDR ( ( XFPD_SLCR_BASEADDR ) + 0x00000014UL )
#define XFPD_SLCR_IDR_RSTVAL 0x00000000UL
#define XFPD_SLCR_IDR_ADDR_DECD_ERR_SHIFT 0UL
#define XFPD_SLCR_IDR_ADDR_DECD_ERR_WIDTH 1UL
#define XFPD_SLCR_IDR_ADDR_DECD_ERR_MASK 0x00000001UL
#define XFPD_SLCR_IDR_ADDR_DECD_ERR_DEFVAL 0x0UL
/**
* Register: XfpdSlcrItr
*/
#define XFPD_SLCR_ITR ( ( XFPD_SLCR_BASEADDR ) + 0x00000018UL )
#define XFPD_SLCR_ITR_RSTVAL 0x00000000UL
#define XFPD_SLCR_ITR_ADDR_DECD_ERR_SHIFT 0UL
#define XFPD_SLCR_ITR_ADDR_DECD_ERR_WIDTH 1UL
#define XFPD_SLCR_ITR_ADDR_DECD_ERR_MASK 0x00000001UL
#define XFPD_SLCR_ITR_ADDR_DECD_ERR_DEFVAL 0x0UL
/**
* Register: XfpdSlcrWdtClkSel
*/
#define XFPD_SLCR_WDT_CLK_SEL ( ( XFPD_SLCR_BASEADDR ) + 0x00000100UL )
#define XFPD_SLCR_WDT_CLK_SEL_RSTVAL 0x00000000UL
#define XFPD_SLCR_WDT_CLK_SEL_SHIFT 0UL
#define XFPD_SLCR_WDT_CLK_SEL_WIDTH 1UL
#define XFPD_SLCR_WDT_CLK_SEL_MASK 0x00000001UL
#define XFPD_SLCR_WDT_CLK_SEL_DEFVAL 0x0UL
/**
* Register: XfpdSlcrIntFpd
*/
#define XFPD_SLCR_INT_FPD ( ( XFPD_SLCR_BASEADDR ) + 0x00000200UL )
#define XFPD_SLCR_INT_FPD_RSTVAL 0x00000000UL
#define XFPD_SLCR_INT_FPD_GFM_SEL_SHIFT 0UL
#define XFPD_SLCR_INT_FPD_GFM_SEL_WIDTH 1UL
#define XFPD_SLCR_INT_FPD_GFM_SEL_MASK 0x00000001UL
#define XFPD_SLCR_INT_FPD_GFM_SEL_DEFVAL 0x0UL
/**
* Register: XfpdSlcrGpu
*/
#define XFPD_SLCR_GPU ( ( XFPD_SLCR_BASEADDR ) + 0x0000100CUL )
#define XFPD_SLCR_GPU_RSTVAL 0x00000007UL
#define XFPD_SLCR_GPU_ARCACHE_SHIFT 7UL
#define XFPD_SLCR_GPU_ARCACHE_WIDTH 4UL
#define XFPD_SLCR_GPU_ARCACHE_MASK 0x00000780UL
#define XFPD_SLCR_GPU_ARCACHE_DEFVAL 0x0UL
#define XFPD_SLCR_GPU_AWCACHE_SHIFT 3UL
#define XFPD_SLCR_GPU_AWCACHE_WIDTH 4UL
#define XFPD_SLCR_GPU_AWCACHE_MASK 0x00000078UL
#define XFPD_SLCR_GPU_AWCACHE_DEFVAL 0x0UL
#define XFPD_SLCR_GPU_PP1_IDLE_SHIFT 2UL
#define XFPD_SLCR_GPU_PP1_IDLE_WIDTH 1UL
#define XFPD_SLCR_GPU_PP1_IDLE_MASK 0x00000004UL
#define XFPD_SLCR_GPU_PP1_IDLE_DEFVAL 0x1UL
#define XFPD_SLCR_GPU_PP0_IDLE_SHIFT 1UL
#define XFPD_SLCR_GPU_PP0_IDLE_WIDTH 1UL
#define XFPD_SLCR_GPU_PP0_IDLE_MASK 0x00000002UL
#define XFPD_SLCR_GPU_PP0_IDLE_DEFVAL 0x1UL
#define XFPD_SLCR_GPU_IDLE_SHIFT 0UL
#define XFPD_SLCR_GPU_IDLE_WIDTH 1UL
#define XFPD_SLCR_GPU_IDLE_MASK 0x00000001UL
#define XFPD_SLCR_GPU_IDLE_DEFVAL 0x1UL
/**
* Register: XfpdSlcrGdmaCfg
*/
#define XFPD_SLCR_GDMA_CFG ( ( XFPD_SLCR_BASEADDR ) + 0x00003000UL )
#define XFPD_SLCR_GDMA_CFG_RSTVAL 0x00000048UL
#define XFPD_SLCR_GDMA_CFG_BUS_WIDTH_SHIFT 5UL
#define XFPD_SLCR_GDMA_CFG_BUS_WIDTH_WIDTH 2UL
#define XFPD_SLCR_GDMA_CFG_BUS_WIDTH_MASK 0x00000060UL
#define XFPD_SLCR_GDMA_CFG_BUS_WIDTH_DEFVAL 0x2UL
#define XFPD_SLCR_GDMA_CFG_NUM_CH_SHIFT 0UL
#define XFPD_SLCR_GDMA_CFG_NUM_CH_WIDTH 5UL
#define XFPD_SLCR_GDMA_CFG_NUM_CH_MASK 0x0000001fUL
#define XFPD_SLCR_GDMA_CFG_NUM_CH_DEFVAL 0x8UL
/**
* Register: XfpdSlcrGdma
*/
#define XFPD_SLCR_GDMA ( ( XFPD_SLCR_BASEADDR ) + 0x00003010UL )
#define XFPD_SLCR_GDMA_RSTVAL 0x00003b3bUL
#define XFPD_SLCR_GDMA_RAM1_EMAB_SHIFT 12UL
#define XFPD_SLCR_GDMA_RAM1_EMAB_WIDTH 3UL
#define XFPD_SLCR_GDMA_RAM1_EMAB_MASK 0x00007000UL
#define XFPD_SLCR_GDMA_RAM1_EMAB_DEFVAL 0x3UL
#define XFPD_SLCR_GDMA_RAM1_EMASA_SHIFT 11UL
#define XFPD_SLCR_GDMA_RAM1_EMASA_WIDTH 1UL
#define XFPD_SLCR_GDMA_RAM1_EMASA_MASK 0x00000800UL
#define XFPD_SLCR_GDMA_RAM1_EMASA_DEFVAL 0x1UL
#define XFPD_SLCR_GDMA_RAM1_EMAA_SHIFT 8UL
#define XFPD_SLCR_GDMA_RAM1_EMAA_WIDTH 3UL
#define XFPD_SLCR_GDMA_RAM1_EMAA_MASK 0x00000700UL
#define XFPD_SLCR_GDMA_RAM1_EMAA_DEFVAL 0x3UL
#define XFPD_SLCR_GDMA_RAM0_EMAB_SHIFT 4UL
#define XFPD_SLCR_GDMA_RAM0_EMAB_WIDTH 3UL
#define XFPD_SLCR_GDMA_RAM0_EMAB_MASK 0x00000070UL
#define XFPD_SLCR_GDMA_RAM0_EMAB_DEFVAL 0x3UL
#define XFPD_SLCR_GDMA_RAM0_EMASA_SHIFT 3UL
#define XFPD_SLCR_GDMA_RAM0_EMASA_WIDTH 1UL
#define XFPD_SLCR_GDMA_RAM0_EMASA_MASK 0x00000008UL
#define XFPD_SLCR_GDMA_RAM0_EMASA_DEFVAL 0x1UL
#define XFPD_SLCR_GDMA_RAM0_EMAA_SHIFT 0UL
#define XFPD_SLCR_GDMA_RAM0_EMAA_WIDTH 3UL
#define XFPD_SLCR_GDMA_RAM0_EMAA_MASK 0x00000007UL
#define XFPD_SLCR_GDMA_RAM0_EMAA_DEFVAL 0x3UL
/**
* Register: XfpdSlcrAfiFs
*/
#define XFPD_SLCR_AFI_FS ( ( XFPD_SLCR_BASEADDR ) + 0x00005000UL )
#define XFPD_SLCR_AFI_FS_RSTVAL 0x00000a00UL
#define XFPD_SLCR_AFI_FS_DW_SS1_SEL_SHIFT 10UL
#define XFPD_SLCR_AFI_FS_DW_SS1_SEL_WIDTH 2UL
#define XFPD_SLCR_AFI_FS_DW_SS1_SEL_MASK 0x00000c00UL
#define XFPD_SLCR_AFI_FS_DW_SS1_SEL_DEFVAL 0x2UL
#define XFPD_SLCR_AFI_FS_DW_SS0_SEL_SHIFT 8UL
#define XFPD_SLCR_AFI_FS_DW_SS0_SEL_WIDTH 2UL
#define XFPD_SLCR_AFI_FS_DW_SS0_SEL_MASK 0x00000300UL
#define XFPD_SLCR_AFI_FS_DW_SS0_SEL_DEFVAL 0x2UL
/**
* Register: XfpdSlcrErrAtbIsr
*/
#define XFPD_SLCR_ERR_ATB_ISR ( ( XFPD_SLCR_BASEADDR ) + 0x00006000UL )
#define XFPD_SLCR_ERR_ATB_ISR_RSTVAL 0x00000000UL
#define XFPD_SLCR_ERR_ATB_ISR_AFIFS1_SHIFT 2UL
#define XFPD_SLCR_ERR_ATB_ISR_AFIFS1_WIDTH 1UL
#define XFPD_SLCR_ERR_ATB_ISR_AFIFS1_MASK 0x00000004UL
#define XFPD_SLCR_ERR_ATB_ISR_AFIFS1_DEFVAL 0x0UL
#define XFPD_SLCR_ERR_ATB_ISR_AFIFS0_SHIFT 1UL
#define XFPD_SLCR_ERR_ATB_ISR_AFIFS0_WIDTH 1UL
#define XFPD_SLCR_ERR_ATB_ISR_AFIFS0_MASK 0x00000002UL
#define XFPD_SLCR_ERR_ATB_ISR_AFIFS0_DEFVAL 0x0UL
#define XFPD_SLCR_ERR_ATB_ISR_FPDS_SHIFT 0UL
#define XFPD_SLCR_ERR_ATB_ISR_FPDS_WIDTH 1UL
#define XFPD_SLCR_ERR_ATB_ISR_FPDS_MASK 0x00000001UL
#define XFPD_SLCR_ERR_ATB_ISR_FPDS_DEFVAL 0x0UL
/**
* Register: XfpdSlcrErrAtbImr
*/
#define XFPD_SLCR_ERR_ATB_IMR ( ( XFPD_SLCR_BASEADDR ) + 0x00006004UL )
#define XFPD_SLCR_ERR_ATB_IMR_RSTVAL 0x00000007UL
#define XFPD_SLCR_ERR_ATB_IMR_AFIFS1_SHIFT 2UL
#define XFPD_SLCR_ERR_ATB_IMR_AFIFS1_WIDTH 1UL
#define XFPD_SLCR_ERR_ATB_IMR_AFIFS1_MASK 0x00000004UL
#define XFPD_SLCR_ERR_ATB_IMR_AFIFS1_DEFVAL 0x1UL
#define XFPD_SLCR_ERR_ATB_IMR_AFIFS0_SHIFT 1UL
#define XFPD_SLCR_ERR_ATB_IMR_AFIFS0_WIDTH 1UL
#define XFPD_SLCR_ERR_ATB_IMR_AFIFS0_MASK 0x00000002UL
#define XFPD_SLCR_ERR_ATB_IMR_AFIFS0_DEFVAL 0x1UL
#define XFPD_SLCR_ERR_ATB_IMR_FPDS_SHIFT 0UL
#define XFPD_SLCR_ERR_ATB_IMR_FPDS_WIDTH 1UL
#define XFPD_SLCR_ERR_ATB_IMR_FPDS_MASK 0x00000001UL
#define XFPD_SLCR_ERR_ATB_IMR_FPDS_DEFVAL 0x1UL
/**
* Register: XfpdSlcrErrAtbIer
*/
#define XFPD_SLCR_ERR_ATB_IER ( ( XFPD_SLCR_BASEADDR ) + 0x00006008UL )
#define XFPD_SLCR_ERR_ATB_IER_RSTVAL 0x00000000UL
#define XFPD_SLCR_ERR_ATB_IER_AFIFS1_SHIFT 2UL
#define XFPD_SLCR_ERR_ATB_IER_AFIFS1_WIDTH 1UL
#define XFPD_SLCR_ERR_ATB_IER_AFIFS1_MASK 0x00000004UL
#define XFPD_SLCR_ERR_ATB_IER_AFIFS1_DEFVAL 0x0UL
#define XFPD_SLCR_ERR_ATB_IER_AFIFS0_SHIFT 1UL
#define XFPD_SLCR_ERR_ATB_IER_AFIFS0_WIDTH 1UL
#define XFPD_SLCR_ERR_ATB_IER_AFIFS0_MASK 0x00000002UL
#define XFPD_SLCR_ERR_ATB_IER_AFIFS0_DEFVAL 0x0UL
#define XFPD_SLCR_ERR_ATB_IER_FPDS_SHIFT 0UL
#define XFPD_SLCR_ERR_ATB_IER_FPDS_WIDTH 1UL
#define XFPD_SLCR_ERR_ATB_IER_FPDS_MASK 0x00000001UL
#define XFPD_SLCR_ERR_ATB_IER_FPDS_DEFVAL 0x0UL
/**
* Register: XfpdSlcrErrAtbIdr
*/
#define XFPD_SLCR_ERR_ATB_IDR ( ( XFPD_SLCR_BASEADDR ) + 0x0000600CUL )
#define XFPD_SLCR_ERR_ATB_IDR_RSTVAL 0x00000000UL
#define XFPD_SLCR_ERR_ATB_IDR_AFIFS1_SHIFT 2UL
#define XFPD_SLCR_ERR_ATB_IDR_AFIFS1_WIDTH 1UL
#define XFPD_SLCR_ERR_ATB_IDR_AFIFS1_MASK 0x00000004UL
#define XFPD_SLCR_ERR_ATB_IDR_AFIFS1_DEFVAL 0x0UL
#define XFPD_SLCR_ERR_ATB_IDR_AFIFS0_SHIFT 1UL
#define XFPD_SLCR_ERR_ATB_IDR_AFIFS0_WIDTH 1UL
#define XFPD_SLCR_ERR_ATB_IDR_AFIFS0_MASK 0x00000002UL
#define XFPD_SLCR_ERR_ATB_IDR_AFIFS0_DEFVAL 0x0UL
#define XFPD_SLCR_ERR_ATB_IDR_FPDS_SHIFT 0UL
#define XFPD_SLCR_ERR_ATB_IDR_FPDS_WIDTH 1UL
#define XFPD_SLCR_ERR_ATB_IDR_FPDS_MASK 0x00000001UL
#define XFPD_SLCR_ERR_ATB_IDR_FPDS_DEFVAL 0x0UL
/**
* Register: XfpdSlcrAtbCmdstore
*/
#define XFPD_SLCR_ATB_CMDSTORE ( ( XFPD_SLCR_BASEADDR ) + 0x00006010UL )
#define XFPD_SLCR_ATB_CMDSTORE_RSTVAL 0x00000007UL
#define XFPD_SLCR_ATB_CMDSTORE_AFIFS1_SHIFT 2UL
#define XFPD_SLCR_ATB_CMDSTORE_AFIFS1_WIDTH 1UL
#define XFPD_SLCR_ATB_CMDSTORE_AFIFS1_MASK 0x00000004UL
#define XFPD_SLCR_ATB_CMDSTORE_AFIFS1_DEFVAL 0x1UL
#define XFPD_SLCR_ATB_CMDSTORE_AFIFS0_SHIFT 1UL
#define XFPD_SLCR_ATB_CMDSTORE_AFIFS0_WIDTH 1UL
#define XFPD_SLCR_ATB_CMDSTORE_AFIFS0_MASK 0x00000002UL
#define XFPD_SLCR_ATB_CMDSTORE_AFIFS0_DEFVAL 0x1UL
#define XFPD_SLCR_ATB_CMDSTORE_FPDS_SHIFT 0UL
#define XFPD_SLCR_ATB_CMDSTORE_FPDS_WIDTH 1UL
#define XFPD_SLCR_ATB_CMDSTORE_FPDS_MASK 0x00000001UL
#define XFPD_SLCR_ATB_CMDSTORE_FPDS_DEFVAL 0x1UL
/**
* Register: XfpdSlcrAtbRespEn
*/
#define XFPD_SLCR_ATB_RESP_EN ( ( XFPD_SLCR_BASEADDR ) + 0x00006014UL )
#define XFPD_SLCR_ATB_RESP_EN_RSTVAL 0x00000000UL
#define XFPD_SLCR_ATB_RESP_EN_AFIFS1_SHIFT 2UL
#define XFPD_SLCR_ATB_RESP_EN_AFIFS1_WIDTH 1UL
#define XFPD_SLCR_ATB_RESP_EN_AFIFS1_MASK 0x00000004UL
#define XFPD_SLCR_ATB_RESP_EN_AFIFS1_DEFVAL 0x0UL
#define XFPD_SLCR_ATB_RESP_EN_AFIFS0_SHIFT 1UL
#define XFPD_SLCR_ATB_RESP_EN_AFIFS0_WIDTH 1UL
#define XFPD_SLCR_ATB_RESP_EN_AFIFS0_MASK 0x00000002UL
#define XFPD_SLCR_ATB_RESP_EN_AFIFS0_DEFVAL 0x0UL
#define XFPD_SLCR_ATB_RESP_EN_FPDS_SHIFT 0UL
#define XFPD_SLCR_ATB_RESP_EN_FPDS_WIDTH 1UL
#define XFPD_SLCR_ATB_RESP_EN_FPDS_MASK 0x00000001UL
#define XFPD_SLCR_ATB_RESP_EN_FPDS_DEFVAL 0x0UL
/**
* Register: XfpdSlcrAtbResptype
*/
#define XFPD_SLCR_ATB_RESPTYPE ( ( XFPD_SLCR_BASEADDR ) + 0x00006018UL )
#define XFPD_SLCR_ATB_RESPTYPE_RSTVAL 0x00000007UL
#define XFPD_SLCR_ATB_RESPTYPE_AFIFS1_SHIFT 2UL
#define XFPD_SLCR_ATB_RESPTYPE_AFIFS1_WIDTH 1UL
#define XFPD_SLCR_ATB_RESPTYPE_AFIFS1_MASK 0x00000004UL
#define XFPD_SLCR_ATB_RESPTYPE_AFIFS1_DEFVAL 0x1UL
#define XFPD_SLCR_ATB_RESPTYPE_AFIFS0_SHIFT 1UL
#define XFPD_SLCR_ATB_RESPTYPE_AFIFS0_WIDTH 1UL
#define XFPD_SLCR_ATB_RESPTYPE_AFIFS0_MASK 0x00000002UL
#define XFPD_SLCR_ATB_RESPTYPE_AFIFS0_DEFVAL 0x1UL
#define XFPD_SLCR_ATB_RESPTYPE_FPDS_SHIFT 0UL
#define XFPD_SLCR_ATB_RESPTYPE_FPDS_WIDTH 1UL
#define XFPD_SLCR_ATB_RESPTYPE_FPDS_MASK 0x00000001UL
#define XFPD_SLCR_ATB_RESPTYPE_FPDS_DEFVAL 0x1UL
/**
* Register: XfpdSlcrAtbPrescale
*/
#define XFPD_SLCR_ATB_PRESCALE ( ( XFPD_SLCR_BASEADDR ) + 0x00006020UL )
#define XFPD_SLCR_ATB_PRESCALE_RSTVAL 0x0000ffffUL
#define XFPD_SLCR_ATB_PRESCALE_EN_SHIFT 16UL
#define XFPD_SLCR_ATB_PRESCALE_EN_WIDTH 1UL
#define XFPD_SLCR_ATB_PRESCALE_EN_MASK 0x00010000UL
#define XFPD_SLCR_ATB_PRESCALE_EN_DEFVAL 0x0UL
#define XFPD_SLCR_ATB_PRESCALE_VAL_SHIFT 0UL
#define XFPD_SLCR_ATB_PRESCALE_VAL_WIDTH 16UL
#define XFPD_SLCR_ATB_PRESCALE_VAL_MASK 0x0000ffffUL
#define XFPD_SLCR_ATB_PRESCALE_VAL_DEFVAL 0xffffUL
/**
*@endcond
*/
#ifdef __cplusplus
}
#endif
#endif /* __XFPD_SLCR_H__ */
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/xfpd_slcr_secure.h
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/*******************************************************************************
* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*******************************************************************************/
#ifndef __XFPD_SLCR_SECURE_H__
#define __XFPD_SLCR_SECURE_H__
#ifdef __cplusplus
extern "C" {
#endif
/**
*@cond nocomments
*/
/**
* XfpdSlcrSecure Base Address
*/
#define XFPD_SLCR_SECURE_BASEADDR 0xFD690000UL
/**
* Register: XfpdSlcrSecCtrl
*/
#define XFPD_SLCR_SEC_CTRL ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000004UL )
#define XFPD_SLCR_SEC_CTRL_RSTVAL 0x00000000UL
#define XFPD_SLCR_SEC_CTRL_SLVERR_EN_SHIFT 0UL
#define XFPD_SLCR_SEC_CTRL_SLVERR_EN_WIDTH 1UL
#define XFPD_SLCR_SEC_CTRL_SLVERR_EN_MASK 0x00000001UL
#define XFPD_SLCR_SEC_CTRL_SLVERR_EN_DEFVAL 0x0UL
/**
* Register: XfpdSlcrSecIsr
*/
#define XFPD_SLCR_SEC_ISR ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000008UL )
#define XFPD_SLCR_SEC_ISR_RSTVAL 0x00000000UL
#define XFPD_SLCR_SEC_ISR_ADDR_DECD_ERR_SHIFT 0UL
#define XFPD_SLCR_SEC_ISR_ADDR_DECD_ERR_WIDTH 1UL
#define XFPD_SLCR_SEC_ISR_ADDR_DECD_ERR_MASK 0x00000001UL
#define XFPD_SLCR_SEC_ISR_ADDR_DECD_ERR_DEFVAL 0x0UL
/**
* Register: XfpdSlcrSecImr
*/
#define XFPD_SLCR_SEC_IMR ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x0000000CUL )
#define XFPD_SLCR_SEC_IMR_RSTVAL 0x00000001UL
#define XFPD_SLCR_SEC_IMR_ADDR_DECD_ERR_SHIFT 0UL
#define XFPD_SLCR_SEC_IMR_ADDR_DECD_ERR_WIDTH 1UL
#define XFPD_SLCR_SEC_IMR_ADDR_DECD_ERR_MASK 0x00000001UL
#define XFPD_SLCR_SEC_IMR_ADDR_DECD_ERR_DEFVAL 0x1UL
/**
* Register: XfpdSlcrSecIer
*/
#define XFPD_SLCR_SEC_IER ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000010UL )
#define XFPD_SLCR_SEC_IER_RSTVAL 0x00000000UL
#define XFPD_SLCR_SEC_IER_ADDR_DECD_ERR_SHIFT 0UL
#define XFPD_SLCR_SEC_IER_ADDR_DECD_ERR_WIDTH 1UL
#define XFPD_SLCR_SEC_IER_ADDR_DECD_ERR_MASK 0x00000001UL
#define XFPD_SLCR_SEC_IER_ADDR_DECD_ERR_DEFVAL 0x0UL
/**
* Register: XfpdSlcrSecIdr
*/
#define XFPD_SLCR_SEC_IDR ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000014UL )
#define XFPD_SLCR_SEC_IDR_RSTVAL 0x00000000UL
#define XFPD_SLCR_SEC_IDR_ADDR_DECD_ERR_SHIFT 0UL
#define XFPD_SLCR_SEC_IDR_ADDR_DECD_ERR_WIDTH 1UL
#define XFPD_SLCR_SEC_IDR_ADDR_DECD_ERR_MASK 0x00000001UL
#define XFPD_SLCR_SEC_IDR_ADDR_DECD_ERR_DEFVAL 0x0UL
/**
* Register: XfpdSlcrSecItr
*/
#define XFPD_SLCR_SEC_ITR ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000018UL )
#define XFPD_SLCR_SEC_ITR_RSTVAL 0x00000000UL
#define XFPD_SLCR_SEC_ITR_ADDR_DECD_ERR_SHIFT 0UL
#define XFPD_SLCR_SEC_ITR_ADDR_DECD_ERR_WIDTH 1UL
#define XFPD_SLCR_SEC_ITR_ADDR_DECD_ERR_MASK 0x00000001UL
#define XFPD_SLCR_SEC_ITR_ADDR_DECD_ERR_DEFVAL 0x0UL
/**
* Register: XfpdSlcrSecSata
*/
#define XFPD_SLCR_SEC_SATA ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000020UL )
#define XFPD_SLCR_SEC_SATA_RSTVAL 0x0000000eUL
#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA1_SHIFT 3UL
#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA1_WIDTH 1UL
#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA1_MASK 0x00000008UL
#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA1_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA0_SHIFT 2UL
#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA0_WIDTH 1UL
#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA0_MASK 0x00000004UL
#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA0_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_SATA_TZ_AXIS_SHIFT 1UL
#define XFPD_SLCR_SEC_SATA_TZ_AXIS_WIDTH 1UL
#define XFPD_SLCR_SEC_SATA_TZ_AXIS_MASK 0x00000002UL
#define XFPD_SLCR_SEC_SATA_TZ_AXIS_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_SATA_TZ_EN_SHIFT 0UL
#define XFPD_SLCR_SEC_SATA_TZ_EN_WIDTH 1UL
#define XFPD_SLCR_SEC_SATA_TZ_EN_MASK 0x00000001UL
#define XFPD_SLCR_SEC_SATA_TZ_EN_DEFVAL 0x0UL
/**
* Register: XfpdSlcrSecPcie
*/
#define XFPD_SLCR_SEC_PCIE ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000030UL )
#define XFPD_SLCR_SEC_PCIE_RSTVAL 0x01ffffffUL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_3_SHIFT 24UL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_3_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_3_MASK 0x01000000UL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_3_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_2_SHIFT 23UL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_2_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_2_MASK 0x00800000UL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_2_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_1_SHIFT 22UL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_1_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_1_MASK 0x00400000UL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_1_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_0_SHIFT 21UL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_0_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_0_MASK 0x00200000UL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_0_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_7_SHIFT 20UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_7_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_7_MASK 0x00100000UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_7_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_6_SHIFT 19UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_6_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_6_MASK 0x00080000UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_6_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_5_SHIFT 18UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_5_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_5_MASK 0x00040000UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_5_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_4_SHIFT 17UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_4_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_4_MASK 0x00020000UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_4_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_3_SHIFT 16UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_3_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_3_MASK 0x00010000UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_3_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_2_SHIFT 15UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_2_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_2_MASK 0x00008000UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_2_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_1_SHIFT 14UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_1_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_1_MASK 0x00004000UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_1_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_0_SHIFT 13UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_0_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_0_MASK 0x00002000UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_0_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_7_SHIFT 12UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_7_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_7_MASK 0x00001000UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_7_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_6_SHIFT 11UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_6_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_6_MASK 0x00000800UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_6_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_5_SHIFT 10UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_5_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_5_MASK 0x00000400UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_5_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_4_SHIFT 9UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_4_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_4_MASK 0x00000200UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_4_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_3_SHIFT 8UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_3_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_3_MASK 0x00000100UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_3_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_2_SHIFT 7UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_2_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_2_MASK 0x00000080UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_2_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_1_SHIFT 6UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_1_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_1_MASK 0x00000040UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_1_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_0_SHIFT 5UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_0_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_0_MASK 0x00000020UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_0_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_REGS_SHIFT 4UL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_REGS_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_REGS_MASK 0x00000010UL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_REGS_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_PBA_SHIFT 3UL
#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_PBA_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_PBA_MASK 0x00000008UL
#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_PBA_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_TABLE_SHIFT 2UL
#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_TABLE_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_TABLE_MASK 0x00000004UL
#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_TABLE_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_ECAM_SHIFT 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_ECAM_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_ECAM_MASK 0x00000002UL
#define XFPD_SLCR_SEC_PCIE_TZ_ECAM_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_BRIDGE_REGS_SHIFT 0UL
#define XFPD_SLCR_SEC_PCIE_TZ_BRIDGE_REGS_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_BRIDGE_REGS_MASK 0x00000001UL
#define XFPD_SLCR_SEC_PCIE_TZ_BRIDGE_REGS_DEFVAL 0x1UL
/**
* Register: XfpdSlcrSecDpdma
*/
#define XFPD_SLCR_SEC_DPDMA ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000040UL )
#define XFPD_SLCR_SEC_DPDMA_RSTVAL 0x00000001UL
#define XFPD_SLCR_SEC_DPDMA_TZ_SHIFT 0UL
#define XFPD_SLCR_SEC_DPDMA_TZ_WIDTH 1UL
#define XFPD_SLCR_SEC_DPDMA_TZ_MASK 0x00000001UL
#define XFPD_SLCR_SEC_DPDMA_TZ_DEFVAL 0x1UL
/**
* Register: XfpdSlcrSecGdma
*/
#define XFPD_SLCR_SEC_GDMA ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000050UL )
#define XFPD_SLCR_SEC_GDMA_RSTVAL 0x000000ffUL
#define XFPD_SLCR_SEC_GDMA_TZ_SHIFT 0UL
#define XFPD_SLCR_SEC_GDMA_TZ_WIDTH 8UL
#define XFPD_SLCR_SEC_GDMA_TZ_MASK 0x000000ffUL
#define XFPD_SLCR_SEC_GDMA_TZ_DEFVAL 0xffUL
/**
* Register: XfpdSlcrSecGic
*/
#define XFPD_SLCR_SEC_GIC ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000060UL )
#define XFPD_SLCR_SEC_GIC_RSTVAL 0x00000000UL
#define XFPD_SLCR_SEC_GIC_CFG_DIS_SHIFT 0UL
#define XFPD_SLCR_SEC_GIC_CFG_DIS_WIDTH 1UL
#define XFPD_SLCR_SEC_GIC_CFG_DIS_MASK 0x00000001UL
#define XFPD_SLCR_SEC_GIC_CFG_DIS_DEFVAL 0x0UL
/**
*@endcond
*/
#ifdef __cplusplus
}
#endif
#endif /* __XFPD_SLCR_SECURE_H__ */
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/xfpd_xmpu_cfg.h
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dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/xfpd_xmpu_sink.h
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/*******************************************************************************
* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*******************************************************************************/
#ifndef __XFPD_XMPU_SINK_H__
#define __XFPD_XMPU_SINK_H__
#ifdef __cplusplus
extern "C" {
#endif
/**
*@cond nocomments
*/
/**
* XfpdXmpuSink Base Address
*/
#define XFPD_XMPU_SINK_BASEADDR 0xFD4F0000UL
/**
* Register: XfpdXmpuSinkErrSts
*/
#define XFPD_XMPU_SINK_ERR_STS ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF00UL )
#define XFPD_XMPU_SINK_ERR_STS_RSTVAL 0x00000000UL
#define XFPD_XMPU_SINK_ERR_STS_RDWR_SHIFT 31UL
#define XFPD_XMPU_SINK_ERR_STS_RDWR_WIDTH 1UL
#define XFPD_XMPU_SINK_ERR_STS_RDWR_MASK 0x80000000UL
#define XFPD_XMPU_SINK_ERR_STS_RDWR_DEFVAL 0x0UL
#define XFPD_XMPU_SINK_ERR_STS_ADDR_SHIFT 0UL
#define XFPD_XMPU_SINK_ERR_STS_ADDR_WIDTH 12UL
#define XFPD_XMPU_SINK_ERR_STS_ADDR_MASK 0x00000fffUL
#define XFPD_XMPU_SINK_ERR_STS_ADDR_DEFVAL 0x0UL
/**
* Register: XfpdXmpuSinkIsr
*/
#define XFPD_XMPU_SINK_ISR ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF10UL )
#define XFPD_XMPU_SINK_ISR_RSTVAL 0x00000000UL
#define XFPD_XMPU_SINK_ISRADDRDECDERR_SHIFT 0UL
#define XFPD_XMPU_SINK_ISRADDRDECDERR_WIDTH 1UL
#define XFPD_XMPU_SINK_ISRADDRDECDERR_MASK 0x00000001UL
#define XFPD_XMPU_SINK_ISRADDRDECDERR_DEFVAL 0x0UL
/**
* Register: XfpdXmpuSinkImr
*/
#define XFPD_XMPU_SINK_IMR ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF14UL )
#define XFPD_XMPU_SINK_IMR_RSTVAL 0x00000001UL
#define XFPD_XMPU_SINK_IMRADDRDECDERR_SHIFT 0UL
#define XFPD_XMPU_SINK_IMRADDRDECDERR_WIDTH 1UL
#define XFPD_XMPU_SINK_IMRADDRDECDERR_MASK 0x00000001UL
#define XFPD_XMPU_SINK_IMRADDRDECDERR_DEFVAL 0x1UL
/**
* Register: XfpdXmpuSinkIer
*/
#define XFPD_XMPU_SINK_IER ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF18UL )
#define XFPD_XMPU_SINK_IER_RSTVAL 0x00000000UL
#define XFPD_XMPU_SINK_IERADDRDECDERR_SHIFT 0UL
#define XFPD_XMPU_SINK_IERADDRDECDERR_WIDTH 1UL
#define XFPD_XMPU_SINK_IERADDRDECDERR_MASK 0x00000001UL
#define XFPD_XMPU_SINK_IERADDRDECDERR_DEFVAL 0x0UL
/**
* Register: XfpdXmpuSinkIdr
*/
#define XFPD_XMPU_SINK_IDR ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF1CUL )
#define XFPD_XMPU_SINK_IDR_RSTVAL 0x00000000UL
#define XFPD_XMPU_SINK_IDRADDRDECDERR_SHIFT 0UL
#define XFPD_XMPU_SINK_IDRADDRDECDERR_WIDTH 1UL
#define XFPD_XMPU_SINK_IDRADDRDECDERR_MASK 0x00000001UL
#define XFPD_XMPU_SINK_IDRADDRDECDERR_DEFVAL 0x0UL
/**
*@endcond
*/
#ifdef __cplusplus
}
#endif
#endif /* __XFPD_XMPU_SINK_H__ */
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/xgpiops.h
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/******************************************************************************
* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (c) 2022 - 2024 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xgpiops.h
* @addtogroup gpiops Overview
* @{
* @details
*
* The Xilinx PS GPIO driver. This driver supports the Xilinx PS GPIO
* Controller.
*
* The GPIO Controller supports the following features:
* - 6 banks
* - Masked writes (There are no masked reads)
* - Bypass mode
* - Configurable Interrupts (Level/Edge)
*
* This driver is intended to be RTOS and processor independent. Any needs for
* dynamic memory management, threads or thread mutual exclusion, virtual
* memory, or cache control must be satisfied by the layer above this driver.
*
* Here is GPIO Bank and Pin mapping information for different platforms.
* Zynq:
* PS GPIO contain 4 banks and 118 pins
* Bank 0 MIO pins 0 - 31
* Bank 1 MIO pins 32 - 53
* Bank 2 MIO pins 54 - 85
* Bank 3 EMIO signals 86 - 117
*
* Zynq Ultrascale+ MP:
* PS GPIO contain 6 banks and 174 pins
* Bank 0 MIO pins 0 - 25
* Bank 1 MIO pins 26 - 51
* Bank 2 MIO pins 52 - 77
* Bank 3 EMIO signals 78 - 109
* Bank 4 EMIO signals 110 - 141
* Bank 5 EMIO signals 142 - 173
* Versal: Two GPIOPS instances PMC GPIO and PS GPIO
* PMC GPIO contain 4 banks and 116 pins
* Bank 0 MIO pins 0 - 25
* Bank 1 MIO pins 26 - 51
* Bank 3 EMIO signals 52 - 83
* Bank 4 EMIO signals 84 - 115
* PS GPIO contains 2 banks and 58 pins
* Bank 0 MIO pins 0 - 25
* Bank 3 EMIO signals 26-57
*
* This driver supports all the features listed above, if applicable.
*
* <b>Driver Description</b>
*
* The device driver enables higher layer software (e.g., an application) to
* communicate to the GPIO.
*
* <b>Interrupts</b>
*
* The driver provides interrupt management functions and an interrupt handler.
* Users of this driver need to provide callback functions. An interrupt handler
* example is available with the driver.
*
* <b>Threads</b>
*
* This driver is not thread safe. Any needs for threads or thread mutual
* exclusion must be satisfied by the layer above this driver.
*
* <b>Asserts</b>
*
* Asserts are used within all Xilinx drivers to enforce constraints on argument
* values. Asserts can be turned off on a system-wide basis by defining, at
* compile time, the NDEBUG identifier. By default, asserts are turned on and it
* is recommended that users leave asserts on during development.
*
* <b>Building the driver</b>
*
* The XGpioPs driver is composed of several source files. This allows the user
* to build and link only those parts of the driver that are necessary.
* <br><br>
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a sv 01/15/10 First Release
* 1.01a sv 04/15/12 Removed the APIs XGpioPs_SetMode, XGpioPs_SetModePin
* XGpioPs_GetMode, XGpioPs_GetModePin as they are not
* relevant to Zynq device.The interrupts are disabled
* for output pins on all banks during initialization.
* 1.02a hk 08/22/13 Added low level reset API
* 2.1 hk 04/29/14 Use Input data register DATA_RO for read. CR# 771667.
* 2.2 sk 10/13/14 Used Pin number in Bank instead of pin number
* passed to APIs. CR# 822636
* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
* 3.1 kvn 04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
* ms 03/17/17 Added readme.txt file in examples folder for doxygen
* generation.
* ms 04/05/17 Added tabspace for return statements in functions of
* gpiops examples for proper documentation while
* generating doxygen.
* 3.3 ms 04/17/17 Added notes about gpio input and output pin description
* for zcu102 and zc702 boards in polled and interrupt
* example, configured Interrupt pin to input pin for
* proper functioning of interrupt example.
* 3.4 aru 08/17/18 Resolved MISRA-C mandatory violations. CR# 1007751
* 3.5 sne 03/01/19 Fixes violations according to MISRAC-2012
* in safety mode and modified the code such as
* Use of mixed mode arithmetic,Declared the pointer param
* as Pointer to const,Casting operation to a pointer,
* Literal value requires a U suffix.
* 3.5 sne 03/14/19 Added Versal support.
* 3.6 mus 04/05/19 Replaced XPLAT_versal macro with XPLAT_VERSAL, to be in
* sync with standalone BSP
* 3.6 sne 06/12/19 Fixed IAR compiler warning.
* 3.6 sne 08/14/19 Added interrupt handler support on versal.
* 3.7 sne 12/04/19 Reverted versal examples support.
* 3.8 sne 08/28/20 Modify Makefile to support parallel make execution.
* 3.8 sne 09/17/20 Added description for Versal PS and PMC GPIO pins.
* 3.9 sne 03/15/21 Fixed MISRA-C violations.
* 3.11 sg 02/23/23 Update bank and pin mapping information.
* 3.12 gm 07/11/23 Added SDT support.
* 3.13 gm 03/15/24 Remove const of XGpioPs InstancePtr from function proto
* type of XGpioPs_IntrEnable, XGpioPs_IntrDisable,
* XGpioPs_IntrEnablePin and XGpioPs_IntrDisablePin
* to add multi-core interrupt support.
*
* </pre>
*
******************************************************************************/
#ifndef XGPIOPS_H /* prevent circular inclusions */
#define XGPIOPS_H /**< by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xstatus.h"
#include "xgpiops_hw.h"
#include "xplatform_info.h"
/************************** Constant Definitions *****************************/
/** @name Interrupt types
* @{
* The following constants define the interrupt types that can be set for each
* GPIO pin.
*/
#define XGPIOPS_IRQ_TYPE_EDGE_RISING 0x00U /**< Interrupt on Rising edge */
#define XGPIOPS_IRQ_TYPE_EDGE_FALLING 0x01U /**< Interrupt Falling edge */
#define XGPIOPS_IRQ_TYPE_EDGE_BOTH 0x02U /**< Interrupt on both edges */
#define XGPIOPS_IRQ_TYPE_LEVEL_HIGH 0x03U /**< Interrupt on high level */
#define XGPIOPS_IRQ_TYPE_LEVEL_LOW 0x04U /**< Interrupt on low level */
/** @}*/
#define XGPIOPS_BANK_MAX_PINS (u32)32 /**< Max pins in a GPIO bank */
#define XGPIOPS_BANK0 0x00U /**< GPIO Bank 0 */
#define XGPIOPS_BANK1 0x01U /**< GPIO Bank 1 */
#define XGPIOPS_BANK2 0x02U /**< GPIO Bank 2 */
#define XGPIOPS_BANK3 0x03U /**< GPIO Bank 3 */
#define XGPIOPS_BANK4 0x04U /**< GPIO Bank 4 */
#define XGPIOPS_BANK5 0x05U /**< GPIO Bank 5 */
#define XGPIOPS_MAX_BANKS_ZYNQMP 0x06U /**< Max banks in a
* Zynq Ultrascale+ MP GPIO device
*/
#define XGPIOPS_MAX_BANKS 0x04U /**< Max banks in a Zynq GPIO device */
#define XGPIOPS_MAX_BANKS_CNT 0x06U /**< Max banks number of all platforms */
#define XGPIOPS_DEVICE_MAX_PIN_NUM_ZYNQMP (u32)174 /**< Max pins in the
* Zynq Ultrascale+ MP GPIO device
* 0 - 25, Bank 0
* 26 - 51, Bank 1
* 52 - 77, Bank 2
* 78 - 109, Bank 3
* 110 - 141, Bank 4
* 142 - 173, Bank 5
*/
#define XGPIOPS_DEVICE_MAX_PIN_NUM (u32)118 /**< Max pins in the Zynq GPIO device
* 0 - 31, Bank 0
* 32 - 53, Bank 1
* 54 - 85, Bank 2
* 86 - 117, Bank 3
*/
/**************************** Type Definitions *******************************/
/****************************************************************************/
/**
* This handler data type allows the user to define a callback function to
* handle the interrupts for the GPIO device. The application using this
* driver is expected to define a handler of this type, to support interrupt
* driven mode. The handler executes in an interrupt context such that minimal
* processing should be performed.
*
* @param CallBackRef is a callback reference passed in by the upper layer
* when setting the callback functions for a GPIO bank. It is
* passed back to the upper layer when the callback is invoked. Its
* type is not important to the driver component, so it is a void
* pointer.
* @param Bank is the bank for which the interrupt status has changed.
* @param Status is the Interrupt status of the GPIO bank.
*
*****************************************************************************/
typedef void (*XGpioPs_Handler) (void *CallBackRef, u32 Bank, u32 Status);
/**
* This typedef contains configuration information for a device.
*/
typedef struct {
#ifndef SDT
u16 DeviceId; /**< Unique ID of device */
#else
char *Name;
#endif
UINTPTR BaseAddr; /**< Register base address */
#ifdef SDT
u16 IntrId; /** Bits[11:0] Interrupt-id Bits[15:12]
* trigger type and level flags */
UINTPTR IntrParent; /** Bit[0] Interrupt parent type Bit[64/32:1]
* Parent base address */
#endif
} XGpioPs_Config;
/**
* The XGpioPs driver instance data. The user is required to allocate a
* variable of this type for the GPIO device in the system. A pointer
* to a variable of this type is then passed to the driver API functions.
*/
typedef struct {
XGpioPs_Config GpioConfig; /**< Device configuration */
u32 IsReady; /**< Device is initialized and ready */
XGpioPs_Handler Handler; /**< Status handlers for all banks */
void *CallBackRef; /**< Callback ref for bank handlers */
u32 Platform; /**< Platform data */
u32 MaxPinNum; /**< Max pins in the GPIO device */
u8 MaxBanks; /**< Max banks in a GPIO device */
u32 PmcGpio; /**< Flag for accessing PS GPIO for versal*/
u32 CoreIntrMask[XGPIOPS_MAX_BANKS_CNT]; /**< Interrupt mask per core */
} XGpioPs;
/************************** Variable Definitions *****************************/
extern XGpioPs_Config XGpioPs_ConfigTable[];
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/* Functions in xgpiops.c */
s32 XGpioPs_CfgInitialize(XGpioPs *InstancePtr, const XGpioPs_Config *ConfigPtr,
u32 EffectiveAddr);
/* Bank APIs in xgpiops.c */
u32 XGpioPs_Read(const XGpioPs *InstancePtr, u8 Bank);
void XGpioPs_Write(const XGpioPs *InstancePtr, u8 Bank, u32 Data);
void XGpioPs_SetDirection(const XGpioPs *InstancePtr, u8 Bank, u32 Direction);
u32 XGpioPs_GetDirection(const XGpioPs *InstancePtr, u8 Bank);
void XGpioPs_SetOutputEnable(const XGpioPs *InstancePtr, u8 Bank, u32 OpEnable);
u32 XGpioPs_GetOutputEnable(const XGpioPs *InstancePtr, u8 Bank);
#ifdef versal
void XGpioPs_GetBankPin(const XGpioPs *InstancePtr,u8 PinNumber,u8 *BankNumber, u8 *PinNumberInBank);
#else
void XGpioPs_GetBankPin(u8 PinNumber,u8 *BankNumber, u8 *PinNumberInBank);
#endif
/* Pin APIs in xgpiops.c */
u32 XGpioPs_ReadPin(const XGpioPs *InstancePtr, u32 Pin);
void XGpioPs_WritePin(const XGpioPs *InstancePtr, u32 Pin, u32 Data);
void XGpioPs_SetDirectionPin(const XGpioPs *InstancePtr, u32 Pin, u32 Direction);
u32 XGpioPs_GetDirectionPin(const XGpioPs *InstancePtr, u32 Pin);
void XGpioPs_SetOutputEnablePin(const XGpioPs *InstancePtr, u32 Pin, u32 OpEnable);
u32 XGpioPs_GetOutputEnablePin(const XGpioPs *InstancePtr, u32 Pin);
/* Diagnostic functions in xgpiops_selftest.c */
s32 XGpioPs_SelfTest(XGpioPs *InstancePtr);
/* Functions in xgpiops_intr.c */
/* Bank APIs in xgpiops_intr.c */
void XGpioPs_IntrEnable(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
void XGpioPs_IntrDisable(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
u32 XGpioPs_IntrGetEnabled(const XGpioPs *InstancePtr, u8 Bank);
u32 XGpioPs_IntrGetStatus(const XGpioPs *InstancePtr, u8 Bank);
void XGpioPs_IntrClear(const XGpioPs *InstancePtr, u8 Bank, u32 Mask);
void XGpioPs_SetIntrType(const XGpioPs *InstancePtr, u8 Bank, u32 IntrType,
u32 IntrPolarity, u32 IntrOnAny);
void XGpioPs_GetIntrType(const XGpioPs *InstancePtr, u8 Bank, u32 *IntrType,
u32 *IntrPolarity, u32 *IntrOnAny);
void XGpioPs_SetCallbackHandler(XGpioPs *InstancePtr, void *CallBackRef,
XGpioPs_Handler FuncPointer);
void XGpioPs_IntrHandler(const XGpioPs *InstancePtr);
/* Pin APIs in xgpiops_intr.c */
void XGpioPs_SetIntrTypePin(const XGpioPs *InstancePtr, u32 Pin, u8 IrqType);
u8 XGpioPs_GetIntrTypePin(const XGpioPs *InstancePtr, u32 Pin);
void XGpioPs_IntrEnablePin(XGpioPs *InstancePtr, u32 Pin);
void XGpioPs_IntrDisablePin(XGpioPs *InstancePtr, u32 Pin);
u32 XGpioPs_IntrGetEnabledPin(const XGpioPs *InstancePtr, u32 Pin);
u32 XGpioPs_IntrGetStatusPin(const XGpioPs *InstancePtr, u32 Pin);
void XGpioPs_IntrClearPin(const XGpioPs *InstancePtr, u32 Pin);
/* Functions in xgpiops_sinit.c */
#ifndef SDT
XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId);
#else
XGpioPs_Config *XGpioPs_LookupConfig(u32 BaseAddress);
#endif
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/** @} */
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/xgpiops_hw.h
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/******************************************************************************
* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xgpiops_hw.h
* @addtogroup gpiops Overview
* @{
*
* This header file contains the identifiers and basic driver functions (or
* macros) that can be used to access the device. Other driver functions
* are defined in xgpiops.h.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------
* 1.00a sv 01/15/10 First Release
* 1.02a hk 08/22/13 Added low level reset API function prototype and
* related constant definitions
* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
* 3.1 kvn 04/13/15 Corrected reset values of banks.
* 3.5 sne 03/14/19 Added versal support.
* </pre>
*
******************************************************************************/
#ifndef XGPIOPS_HW_H /* prevent circular inclusions */
#define XGPIOPS_HW_H /**< by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xil_io.h"
/************************** Constant Definitions *****************************/
/** @name Register offsets for the GPIO. Each register is 32 bits.
* @{
*/
#define XGPIOPS_DATA_LSW_OFFSET 0x00000000U /**< Mask and Data Register LSW, WO */
#define XGPIOPS_DATA_MSW_OFFSET 0x00000004U /**< Mask and Data Register MSW, WO */
#define XGPIOPS_DATA_OFFSET 0x00000040U /**< Data Register, RW */
#define XGPIOPS_DATA_RO_OFFSET 0x00000060U /**< Data Register - Input, RO */
#define XGPIOPS_DIRM_OFFSET 0x00000204U /**< Direction Mode Register, RW */
#define XGPIOPS_OUTEN_OFFSET 0x00000208U /**< Output Enable Register, RW */
#define XGPIOPS_INTMASK_OFFSET 0x0000020CU /**< Interrupt Mask Register, RO */
#define XGPIOPS_INTEN_OFFSET 0x00000210U /**< Interrupt Enable Register, WO */
#define XGPIOPS_INTDIS_OFFSET 0x00000214U /**< Interrupt Disable Register, WO*/
#define XGPIOPS_INTSTS_OFFSET 0x00000218U /**< Interrupt Status Register, RO */
#define XGPIOPS_INTTYPE_OFFSET 0x0000021CU /**< Interrupt Type Register, RW */
#define XGPIOPS_INTPOL_OFFSET 0x00000220U /**< Interrupt Polarity Register, RW */
#define XGPIOPS_INTANY_OFFSET 0x00000224U /**< Interrupt On Any Register, RW */
/** @} */
/** @name Register offsets for each Bank.
* @{
*/
#define XGPIOPS_DATA_MASK_OFFSET 0x00000008U /**< Data/Mask Registers offset */
#define XGPIOPS_DATA_BANK_OFFSET 0x00000004U /**< Data Registers offset */
#define XGPIOPS_REG_MASK_OFFSET 0x00000040U /**< Registers offset */
/** @} */
/* For backwards compatibility */
#define XGPIOPS_BYPM_MASK_OFFSET (u32)0x40 /**< Mask for backward support */
/** @name Interrupt type reset values for each bank
* @{
*/
#ifdef XPAR_PSU_GPIO_0_BASEADDR
#define XGPIOPS_INTTYPE_BANK0_RESET 0x03FFFFFFU /**< Resets specific to Zynq Ultrascale+ MP */
#define XGPIOPS_INTTYPE_BANK1_RESET 0x03FFFFFFU /**< Resets specific to Zynq Ultrascale+ MP */
#define XGPIOPS_INTTYPE_BANK2_RESET 0x03FFFFFFU /**< Resets specific to Zynq Ultrascale+ MP */
#else
#define XGPIOPS_INTTYPE_BANK0_RESET 0xFFFFFFFFU /**< Resets specific to Zynq */
#define XGPIOPS_INTTYPE_BANK1_RESET 0x003FFFFFU /**< Resets specific to Zynq */
#define XGPIOPS_INTTYPE_BANK2_RESET 0xFFFFFFFFU /**< Resets specific to Zynq */
#endif
#define XGPIOPS_INTTYPE_BANK3_RESET 0xFFFFFFFFU /**< Reset common to both platforms */
#define XGPIOPS_INTTYPE_BANK4_RESET 0xFFFFFFFFU /**< Resets specific to Zynq Ultrascale+ MP */
#define XGPIOPS_INTTYPE_BANK5_RESET 0xFFFFFFFFU /**< Resets specific to Zynq Ultrascale+ MP */
/** @} */
#define XGPIOPS_PS_GPIO_BASEADDR 0xFF0B0000U /**< Flag for Base Address for PS_GPIO in Versal */
#define XGPIOPS_ZERO 0U /**< Flag for 0 Value */
#define XGPIOPS_ONE 1U /**< Flag for 1 Value */
#define XGPIOPS_TWO 2U /**< Flag for 2 Value */
#define XGPIOPS_THREE 3U /**< Flag for 3 Value */
#define XGPIOPS_FOUR 4U /**< Flag for 4 Value */
#define XGPIOPS_SIX 6U /**< Flag for 6 Value */
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/****************************************************************************/
/**
*
* This macro reads the given register.
*
* @param BaseAddr is the base address of the device.
* @param RegOffset is the register offset to be read.
*
* @return The 32-bit value of the register
*
* @note None.
*
*****************************************************************************/
#define XGpioPs_ReadReg(BaseAddr, RegOffset) \
Xil_In32((BaseAddr) + (u32)(RegOffset))
/****************************************************************************/
/**
*
* This macro writes to the given register.
*
* @param BaseAddr is the base address of the device.
* @param RegOffset is the offset of the register to be written.
* @param Data is the 32-bit value to write to the register.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
#define XGpioPs_WriteReg(BaseAddr, RegOffset, Data) \
Xil_Out32((BaseAddr) + (u32)(RegOffset), (u32)(Data))
/************************** Function Prototypes ******************************/
void XGpioPs_ResetHw(UINTPTR BaseAddress);
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* XGPIOPS_HW_H */
/** @} */
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/xiicps.h
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/******************************************************************************
* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2024 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xiicps.h
* @addtogroup iicps_api IICPS APIs
* @{
* @details
*
*
* <pre> MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------ -------- -----------------------------------------------
* 1.00a drg/jz 01/30/08 First release
* 1.00a sdm 09/21/11 Fixed an issue in the XIicPs_SetOptions and
* XIicPs_ClearOptions where the InstancePtr->Options
* was not updated correctly.
* Updated the InstancePtr->Options in the
* XIicPs_CfgInitialize by calling XIicPs_GetOptions.
* Updated the XIicPs_SetupMaster to not check for
* Bus Busy condition when the Hold Bit is set.
* Removed some unused variables.
* 1.01a sg 03/30/12 Fixed an issue in XIicPs_MasterSendPolled where a
* check for transfer completion is added, which indicates
* the completion of current transfer.
* 1.02a sg 08/29/12 Updated the logic to arrive at the best divisors
* to achieve I2C clock with minimum error for
* CR #674195
* 1.03a hk 05/04/13 Initialized BestDivA and BestDivB to 0.
* This is fix for CR#704398 to remove warning.
* 2.0 hk 03/07/14 Added check for error status in the while loop that
* checks for completion.
* (XIicPs_MasterSendPolled function). CR# 762244, 764875.
* Limited frequency set when 100KHz or 400KHz is
* selected. This is a hardware limitation. CR#779290.
* 2.1 hk 04/24/14 Fix for CR# 789821 to handle >14 byte transfers.
* Explicitly reset CR and clear FIFO in Abort function
* and state the same in the comments. CR# 784254.
* Fix for CR# 761060 - provision for repeated start.
* 2.2 hk 08/23/14 Slave monitor mode changes - clear FIFO, enable
* read mode and clear transfer size register.
* Disable NACK to avoid interrupts on each retry.
* 2.3 sk 10/07/14 Repeated start feature deleted.
* 3.0 sk 11/03/14 Modified TimeOut Register value to 0xFF
* in XIicPs_Reset.
* 12/06/14 Implemented Repeated start feature.
* 01/31/15 Modified the code according to MISRAC 2012 Compliant.
* 02/18/15 Implemented larger data transfer using repeated start
* in Zynq UltraScale MP.
* 3.3 kvn 05/05/16 Modified latest code for MISRA-C:2012 Compliance.
* ms 03/17/17 Added readme.txt file in examples folder for doxygen
* generation.
* 3.7 ask 04/17/18 Updated the Eeprom scanning mechanism
* as per the other examples (CR#997545)
* 3.8 ask 08/01/18 Fix for Cppcheck and Doxygen warnings
* 3.8 sd 09/06/18 Enable the Timeout interrupt
* 3.9 sg 03/09/19 Added arbitration lost support in polled transfer
* 3.11 rna 12/23/19 Added 10 bit address support for Master/Slave
* 3.11 sd 02/06/20 Added clocking support.
* 3.11 rna 02/20/20 Reorganization of driver for modularity.
* Added new files xiicps_xfer.c and xiicps_xfer.h.
* Moved internal data transfer APIs to xiicps_xfer.
* 3.13 rna 05/24/21 Fixed Misra-c violations
* 3.16 gm 05/10/22 Added support to get the status of receive valid data.
* Added support for clock stretching and timeout support.
* 3.18 gm 07/14/23 Added SDT support.
* sd 09/06/23 Compile refclk for SDT
*
* </pre>
*
******************************************************************************/
#ifndef XIICPS_H /* prevent circular inclusions */
#define XIICPS_H /**< by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
#if defined (XCLOCKING)
#include "xil_clocking.h"
#endif
#include "xstatus.h"
#include "xiicps_hw.h"
#include "xplatform_info.h"
/************************** Constant Definitions *****************************/
/** @name Configuration options
*
* The following options may be specified or retrieved for the device and
* enable/disable additional features of the IIC. Each of the options
* are bit fields, so more than one may be specified.
*
* @{
*/
#define XIICPS_7_BIT_ADDR_OPTION 0x01U /**< 7-bit address mode */
#define XIICPS_10_BIT_ADDR_OPTION 0x02U /**< 10-bit address mode */
#define XIICPS_SLAVE_MON_OPTION 0x04U /**< Slave monitor mode */
#define XIICPS_REP_START_OPTION 0x08U /**< Repeated Start */
/** @} */
/** @name Callback events
*
* These constants specify the handler events that are passed to an application
* event handler from the driver. These constants are bit masks such that
* more than one event can be passed to the handler.
*
* @{
*/
#define XIICPS_EVENT_COMPLETE_SEND 0x0001U /**< Transmit Complete Event*/
#define XIICPS_EVENT_COMPLETE_RECV 0x0002U /**< Receive Complete Event*/
#define XIICPS_EVENT_TIME_OUT 0x0004U /**< Transfer timed out */
#define XIICPS_EVENT_ERROR 0x0008U /**< Receive error */
#define XIICPS_EVENT_ARB_LOST 0x0010U /**< Arbitration lost */
#define XIICPS_EVENT_NACK 0x0020U /**< NACK Received */
#define XIICPS_EVENT_SLAVE_RDY 0x0040U /**< Slave ready */
#define XIICPS_EVENT_RX_OVR 0x0080U /**< RX overflow */
#define XIICPS_EVENT_TX_OVR 0x0100U /**< TX overflow */
#define XIICPS_EVENT_RX_UNF 0x0200U /**< RX underflow */
/** @} */
/** name Role constants
*
* These constants are used to pass into the device setup routines to
* set up the device according to transfer direction.
*/
#define SENDING_ROLE 1 /**< Transfer direction is sending */
#define RECVING_ROLE 0 /**< Transfer direction is receiving */
#define XIICPS_MAX_TRANSFER_SIZE ((u32)255U - (u32)3U) /**< Max transfer size */
/**************************** Type Definitions *******************************/
/**
* The handler data type allows the user to define a callback function to
* respond to interrupt events in the system. This function is executed
* in interrupt context, so that the amount of processing should be minimized.
*
* @param CallBackRef Reference passed in by the upper
* layer when setting the callback functions, and passed back to
* the upper layer when the callback is invoked. Its type is
* not important to the driver, so it is a void pointer.
* @param StatusEvent Indicates one or more status events that occurred.
*/
typedef void (*XIicPs_IntrHandler) (void *CallBackRef, u32 StatusEvent);
/**
* This typedef contains configuration information for the device.
*/
typedef struct {
#ifndef SDT
u16 DeviceId; /**< Unique ID of device */
#else
char *Name;
#endif
UINTPTR BaseAddress; /**< Base address of the device */
u32 InputClockHz; /**< Input clock frequency */
#ifdef SDT
u16 IntrId; /**< Bits[11:0] Interrupt-id Bits[15:12]
* trigger type and level flags */
UINTPTR IntrParent; /**< Bit[0] Interrupt parent type Bit[64/32:1]
* Parent base address */
#endif
#if defined (XCLOCKING) || defined (SDT)
u32 RefClk; /**< Input clocks */
#endif
} XIicPs_Config;
/**
* The XIicPs driver instance data. The user is required to allocate a
* variable of this type for each IIC device in the system. A pointer
* to a variable of this type is then passed to the driver API functions.
*/
typedef struct {
XIicPs_Config Config; /**< Configuration structure */
u32 IsReady; /**< Device is initialized and ready */
u32 Options; /**< Options set in the device */
u8 *SendBufferPtr; /**< Pointer to send buffer */
u8 *RecvBufferPtr; /**< Pointer to recv buffer */
s32 SendByteCount; /**< Number of bytes still expected to send */
s32 RecvByteCount; /**< Number of bytes still expected to receive */
s32 CurrByteCount; /**< No. of bytes expected in current transfer */
s32 UpdateTxSize; /**< If tx size register has to be updated */
s32 IsSend; /**< Whether master is sending or receiving */
s32 IsRepeatedStart; /**< Indicates if user set repeated start */
s32 Is10BitAddr; /**< Indicates if user set 10 bit address */
XIicPs_IntrHandler StatusHandler; /**< Event handler function */
#if defined (XCLOCKING)
u32 IsClkEnabled; /**< Input clock enabled */
#endif
void *CallBackRef; /**< Callback reference for event handler */
} XIicPs;
/************************** Variable Definitions *****************************/
extern XIicPs_Config XIicPs_ConfigTable[]; /**< Configuration table */
/***************** Macros (Inline Functions) Definitions *********************/
/****************************************************************************/
/**
*
* This function is to check if Rx data is valid or not.
*
* @param InstancePtr Pointer to the XIicPs instance.
*
* @return returns '1' if Rx data is valid, '0' otherwise.
*
*
******************************************************************************/
static INLINE u32 XIicPs_RxDataValidStatus(XIicPs *InstancePtr)
{
return ((XIicPs_ReadReg(InstancePtr->Config.BaseAddress, XIICPS_SR_OFFSET))
& XIICPS_SR_RXDV_MASK);
}
/****************************************************************************/
/**
* Place one byte into the transmit FIFO.
*
* @param InstancePtr Pointer to the XIicPs instance.
*
* @return None.
*
* @note C-Style signature:
* void XIicPs_SendByte(XIicPs *InstancePtr)
*
*****************************************************************************/
#define XIicPs_SendByte(InstancePtr) \
{ \
u8 Data; \
Data = *((InstancePtr)->SendBufferPtr); \
XIicPs_Out32((InstancePtr)->Config.BaseAddress \
+ (u32)(XIICPS_DATA_OFFSET), \
(u32)(Data)); \
(InstancePtr)->SendBufferPtr += 1; \
(InstancePtr)->SendByteCount -= 1;\
}
/****************************************************************************/
/**
*
* Receive one byte from FIFO.
*
* @param InstancePtr Pointer to the XIicPs instance.
*
* @return None.
*
* @note C-Style signature:
* u8 XIicPs_RecvByte(XIicPs *InstancePtr)
*
*****************************************************************************/
#define XIicPs_RecvByte(InstancePtr) \
{ \
u8 *Data, Value; \
Value = (u8)(XIicPs_In32((InstancePtr)->Config.BaseAddress \
+ (u32)XIICPS_DATA_OFFSET)); \
Data = &Value; \
*(InstancePtr)->RecvBufferPtr = *Data; \
(InstancePtr)->RecvBufferPtr += 1; \
(InstancePtr)->RecvByteCount --; \
}
/************************** Function Prototypes ******************************/
/**
* Function for configuration lookup, in xiicps_sinit.c
*/
#ifndef SDT
XIicPs_Config *XIicPs_LookupConfig(u16 DeviceId);
#else
XIicPs_Config *XIicPs_LookupConfig(u32 BaseAddress);
#endif
/**
* Functions for general setup, in xiicps.c
* @{
*/
s32 XIicPs_CfgInitialize(XIicPs *InstancePtr, XIicPs_Config * ConfigPtr,
u32 EffectiveAddr);
void XIicPs_Abort(XIicPs *InstancePtr);
void XIicPs_Reset(XIicPs *InstancePtr);
s32 XIicPs_BusIsBusy(XIicPs *InstancePtr);
s32 TransmitFifoFill(XIicPs *InstancePtr);
/** @} */
/**
* Functions for interrupts, in xiicps_intr.c
*/
void XIicPs_SetStatusHandler(XIicPs *InstancePtr, void *CallBackRef,
XIicPs_IntrHandler FunctionPtr);
/**
* Functions for device as master, in xiicps_master.c
* @{
*/
void XIicPs_MasterSend(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
u16 SlaveAddr);
void XIicPs_MasterRecv(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
u16 SlaveAddr);
s32 XIicPs_MasterSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
u16 SlaveAddr);
s32 XIicPs_MasterRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
u16 SlaveAddr);
void XIicPs_EnableSlaveMonitor(XIicPs *InstancePtr, u16 SlaveAddr);
void XIicPs_DisableSlaveMonitor(XIicPs *InstancePtr);
void XIicPs_MasterInterruptHandler(XIicPs *InstancePtr);
/** @} */
/**
* Functions for device as slave, in xiicps_slave.c
* @{
*/
void XIicPs_SetupSlave(XIicPs *InstancePtr, u16 SlaveAddr);
void XIicPs_SlaveSend(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount);
void XIicPs_SlaveRecv(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount);
s32 XIicPs_SlaveSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount);
s32 XIicPs_SlaveRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount);
void XIicPs_SlaveInterruptHandler(XIicPs *InstancePtr);
void XIicPsSclHold(XIicPs *InstancePtr, u8 Enable);
void XIicPsSetTimeOut(XIicPs *InstancePtr, u8 Value);
/** @} */
/**
* Functions for selftest, in xiicps_selftest.c
*/
s32 XIicPs_SelfTest(XIicPs *InstancePtr);
/**
* Functions for setting and getting data rate, in xiicps_options.c
* @{
*/
s32 XIicPs_SetOptions(XIicPs *InstancePtr, u32 Options);
s32 XIicPs_ClearOptions(XIicPs *InstancePtr, u32 Options);
u32 XIicPs_GetOptions(XIicPs *InstancePtr);
s32 XIicPs_SetSClk(XIicPs *InstancePtr, u32 FsclHz);
u32 XIicPs_GetSClk(XIicPs *InstancePtr);
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/** @} */
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/xiicps_hw.h
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/******************************************************************************
* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2024 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xiicps_hw.h
* @addtogroup iicps_api IICPS APIs
* @{
*
* The xiicps_hw.h header file contains the hardware definition for an IIC device.
* It includes register definitions and interface functions to read/write
* the registers.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------ -------- -----------------------------------------------
* 1.00a drg/jz 01/30/10 First release
* 1.04a kpc 11/07/13 Added function prototype.
* 3.0 sk 11/03/14 Modified the TimeOut Register value to 0xFF
* 01/31/15 Modified the code according to MISRAC 2012 Compliant.
* 3.10 sg 06/24/19 Added timeout macro for polled transfer.
* </pre>
*
******************************************************************************/
#ifndef XIICPS_HW_H /* prevent circular inclusions */
#define XIICPS_HW_H /**< by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xil_io.h"
/************************** Constant Definitions *****************************/
/** @name Register Map
*
* Register offsets for the IIC.
* @{
*/
#define XIICPS_CR_OFFSET 0x00U /**< 32-bit Control */
#define XIICPS_SR_OFFSET 0x04U /**< Status */
#define XIICPS_ADDR_OFFSET 0x08U /**< IIC Address */
#define XIICPS_DATA_OFFSET 0x0CU /**< IIC FIFO Data */
#define XIICPS_ISR_OFFSET 0x10U /**< Interrupt Status */
#define XIICPS_TRANS_SIZE_OFFSET 0x14U /**< Transfer Size */
#define XIICPS_SLV_PAUSE_OFFSET 0x18U /**< Slave monitor pause */
#define XIICPS_TIME_OUT_OFFSET 0x1CU /**< Time Out */
#define XIICPS_IMR_OFFSET 0x20U /**< Interrupt Enabled Mask */
#define XIICPS_IER_OFFSET 0x24U /**< Interrupt Enable */
#define XIICPS_IDR_OFFSET 0x28U /**< Interrupt Disable */
/** @} */
/** @cond INTERNAL */
/** @name Control Register
*
* This register contains various control bits that
* affects the operation of the IIC controller. Read/Write.
* @{
*/
#define XIICPS_CR_DIV_A_MASK 0x0000C000U /**< Clock Divisor A */
#define XIICPS_CR_DIV_A_SHIFT 14U /**< Clock Divisor A shift */
#define XIICPS_DIV_A_MAX 4U /**< Maximum value of Divisor A */
#define XIICPS_CR_DIV_B_MASK 0x00003F00U /**< Clock Divisor B */
#define XIICPS_CR_DIV_B_SHIFT 8U /**< Clock Divisor B shift */
#define XIICPS_CR_CLR_FIFO_MASK 0x00000040U /**< Clear FIFO, auto clears*/
#define XIICPS_CR_SLVMON_MASK 0x00000020U /**< Slave monitor mode */
#define XIICPS_CR_HOLD_MASK 0x00000010U /**< Hold bus 1=Hold scl,
0=terminate transfer */
#define XIICPS_CR_ACKEN_MASK 0x00000008U /**< Enable TX of ACK when
Master receiver*/
#define XIICPS_CR_NEA_MASK 0x00000004U /**< Addressing Mode 1=7 bit,
0=10 bit */
#define XIICPS_CR_MS_MASK 0x00000002U /**< Master mode bit 1=Master,
0=Slave */
#define XIICPS_CR_RD_WR_MASK 0x00000001U /**< Read or Write Master
transfer 0=Transmitter,
1=Receiver*/
#define XIICPS_CR_RESET_VALUE 0U /**< Reset value of the Control
register */
/** @} */
/** @name IIC Status Register
*
* This register is used to indicate status of the IIC controller. Read only
* @{
*/
#define XIICPS_SR_BA_MASK 0x00000100U /**< Bus Active Mask */
#define XIICPS_SR_RXOVF_MASK 0x00000080U /**< Receiver Overflow Mask */
#define XIICPS_SR_TXDV_MASK 0x00000040U /**< Transmit Data Valid Mask */
#define XIICPS_SR_RXDV_MASK 0x00000020U /**< Receiver Data Valid Mask */
#define XIICPS_SR_RXRW_MASK 0x00000008U /**< Receive read/write Mask */
/** @} */
/** @name IIC Address Register
*
* Normal addressing mode uses add[6:0]. Extended addressing mode uses add[9:0].
* A write access to this register always initiates a transfer if the IIC is in
* master mode. Read/Write
* @{
*/
#define XIICPS_ADDR_MASK 0x000003FF /**< IIC Address Mask */
/** @} */
/** @name IIC Data Register
*
* When written to, the data register sets data to transmit. When read from, the
* data register reads the last received byte of data. Read/Write
* @{
*/
#define XIICPS_DATA_MASK 0x000000FF /**< IIC Data Mask */
/** @} */
/** @endcond */
/** @name IIC Interrupt Registers
*
* <b>IIC Interrupt Status Register</b>
*
* This register holds the interrupt status flags for the IIC controller. Some
* of the flags are level triggered
* - i.e. are set as long as the interrupt condition exists. Other flags are
* edge triggered, which means they are set one the interrupt condition occurs
* then remain set until they are cleared by software.
* The interrupts are cleared by writing a one to the interrupt bit position
* in the Interrupt Status Register. Read/Write.
*
* <b>IIC Interrupt Enable Register</b>
*
* This register is used to enable interrupt sources for the IIC controller.
* Writing a '1' to a bit in this register clears the corresponding bit in the
* IIC Interrupt Mask register. Write only.
*
* <b>IIC Interrupt Disable Register </b>
*
* This register is used to disable interrupt sources for the IIC controller.
* Writing a '1' to a bit in this register sets the corresponding bit in the
* IIC Interrupt Mask register. Write only.
*
* <b>IIC Interrupt Mask Register</b>
*
* This register shows the enabled/disabled status of each IIC controller
* interrupt source. A bit set to 1 will ignore the corresponding interrupt in
* the status register. A bit set to 0 means the interrupt is enabled.
* All mask bits are set and all interrupts are disabled after reset. Read only.
*
* All four registers have the same bit definitions. They are only defined once
* for each of the Interrupt Enable Register, Interrupt Disable Register,
* Interrupt Mask Register, and Interrupt Status Register
* @{
*/
#define XIICPS_IXR_ARB_LOST_MASK 0x00000200U /**< Arbitration Lost Interrupt
mask */
#define XIICPS_IXR_RX_UNF_MASK 0x00000080U /**< FIFO Receive Underflow
Interrupt mask */
#define XIICPS_IXR_TX_OVR_MASK 0x00000040U /**< Transmit Overflow
Interrupt mask */
#define XIICPS_IXR_RX_OVR_MASK 0x00000020U /**< Receive Overflow Interrupt
mask */
#define XIICPS_IXR_SLV_RDY_MASK 0x00000010U /**< Monitored Slave Ready
Interrupt mask */
#define XIICPS_IXR_TO_MASK 0x00000008U /**< Transfer Time Out
Interrupt mask */
#define XIICPS_IXR_NACK_MASK 0x00000004U /**< NACK Interrupt mask */
#define XIICPS_IXR_DATA_MASK 0x00000002U /**< Data Interrupt mask */
#define XIICPS_IXR_COMP_MASK 0x00000001U /**< Transfer Complete
Interrupt mask */
#define XIICPS_IXR_DEFAULT_MASK 0x000002FFU /**< Default ISR Mask */
#define XIICPS_IXR_ALL_INTR_MASK 0x000002FFU /**< All ISR Mask */
/** @} */
/** @cond INTERNAL */
/** @name IIC Transfer Size Register
*
* The register's meaning varies according to the operating mode as follows:
* - Master transmitter mode: number of data bytes still not transmitted minus
* one
* - Master receiver mode: number of data bytes that are still expected to be
* received
* - Slave transmitter mode: number of bytes remaining in the FIFO after the
* master terminates the transfer
* - Slave receiver mode: number of valid data bytes in the FIFO
*
* This register is cleared if CLR_FIFO bit in the control register is set.
* Read/Write
* @{
*/
#define XIICPS_TRANS_SIZE_MASK 0x0000003F /**< IIC Transfer Size Mask */
#define XIICPS_FIFO_DEPTH 16 /**< Number of bytes in the FIFO */
#define XIICPS_DATA_INTR_DEPTH 14 /**< Number of bytes at DATA intr */
/** @} */
/** @name IIC Slave Monitor Pause Register
*
* This register is associated with the slave monitor mode of the I2C interface.
* It is meaningful only when the module is in master mode and bit SLVMON in the
* control register is set.
*
* This register defines the pause interval between consecutive attempts to
* address the slave once a write to an I2C address register is done by the
* host. It represents the number of sclk cycles minus one between two attempts.
*
* The reset value of the register is 0, which results in the master repeatedly
* trying to access the slave immediately after unsuccessful attempt.
* Read/Write
* @{
*/
#define XIICPS_SLV_PAUSE_MASK 0x0000000F /**< Slave monitor pause mask */
/** @} */
/** @name IIC Time Out Register
*
* The value of time out register represents the time out interval in number of
* sclk cycles minus one.
*
* When the accessed slave holds the sclk line low for longer than the time out
* period, thus prohibiting the I2C interface in master mode to complete the
* current transfer, an interrupt is generated and TO interrupt flag is set.
*
* The reset value of the register is 0x1f.
* Read/Write
* @{
*/
#define XIICPS_TIME_OUT_MASK 0x000000FFU /**< IIC Time Out mask */
#define XIICPS_TO_RESET_VALUE 0x000000FFU /**< IIC Time Out reset value */
/** @} */
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
#define XIicPs_In32 Xil_In32 /**< XIicPs read */
#define XIicPs_Out32 Xil_Out32 /**< XIicPs write */
#define XIICPS_POLL_DEFAULT_TIMEOUT_VAL 1000U /**< Timeout in us */
/** @endcond */
/****************************************************************************/
/**
* Reads an IIC register.
*
* @param BaseAddress Contains the base address of the device.
* @param RegOffset Contains the offset from the 1st register of the
* device to select the specific register.
*
* @return The value read from the register.
*
* @note C-Style signature:
* u32 XIicPs_ReadReg(u32 BaseAddress. int RegOffset)
*
******************************************************************************/
#define XIicPs_ReadReg(BaseAddress, RegOffset) \
XIicPs_In32((BaseAddress) + (u32)(RegOffset))
/***************************************************************************/
/**
* Writes an IIC register.
*
* @param BaseAddress Contains the base address of the device.
* @param RegOffset Contains the offset from the 1st register of the
* device to select the specific register.
* @param RegisterValue Value to be written to the register.
*
* @return None.
*
* @note C-Style signature:
* void XIicPs_WriteReg(u32 BaseAddress, int RegOffset, u32 RegisterValue)
*
******************************************************************************/
#define XIicPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
XIicPs_Out32((BaseAddress) + (u32)(RegOffset), (u32)(RegisterValue))
/***************************************************************************/
/**
* Reads the interrupt enable register.
*
* @param BaseAddress Contains the base address of the device.
*
* @return Current bit mask that represents currently enabled interrupts.
*
* @note C-Style signature:
* u32 XIicPs_ReadIER(u32 BaseAddress)
*
******************************************************************************/
#define XIicPs_ReadIER(BaseAddress) \
XIicPs_ReadReg((BaseAddress), XIICPS_IER_OFFSET)
/***************************************************************************/
/**
* Writes to the interrupt enable register.
*
* @param BaseAddress Contains the base address of the device.
*
* @param IntrMask Interrupts to be enabled.
*
* @return None.
*
* @note C-Style signature:
* void XIicPs_EnabledInterrupts(u32 BaseAddress, u32 IntrMask)
*
******************************************************************************/
#define XIicPs_EnableInterrupts(BaseAddress, IntrMask) \
XIicPs_WriteReg((BaseAddress), XIICPS_IER_OFFSET, (IntrMask))
/***************************************************************************/
/**
* Disables all interrupts.
*
* @param BaseAddress Contains the base address of the device.
*
* @return None.
*
* @note C-Style signature:
* void XIicPs_DisableAllInterrupts(u32 BaseAddress)
*
******************************************************************************/
#define XIicPs_DisableAllInterrupts(BaseAddress) \
XIicPs_WriteReg((BaseAddress), XIICPS_IDR_OFFSET, \
XIICPS_IXR_ALL_INTR_MASK)
/***************************************************************************/
/**
* Disables selected interrupts.
*
* @param BaseAddress Contains the base address of the device.
*
* @param IntrMask Interrupts to be disabled.
*
* @return None.
*
* @note C-Style signature:
* void XIicPs_DisableInterrupts(u32 BaseAddress, u32 IntrMask)
*
******************************************************************************/
#define XIicPs_DisableInterrupts(BaseAddress, IntrMask) \
XIicPs_WriteReg((BaseAddress), XIICPS_IDR_OFFSET, \
(IntrMask))
/************************** Variable Definitions *****************************/
/************************** Function Prototypes ******************************/
/*
* Perform reset operation to the I2c interface
*/
/** @cond INTERNAL */
void XIicPs_ResetHw(UINTPTR BaseAddress);
/** @endcond */
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/** @} */
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/xiicps_xfer.h
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/******************************************************************************
* Copyright (C) 2021 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2024 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xiicps_xfer.h
* @addtogroup iicps_api IICPS APIs
* @{
*
* The xiicps_xfer.h file contains implementation of required helper functions
* for the XIicPs driver.
*
* <pre> MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------ -------- --------------------------------------------
* 3.11 rna 12/10/19 First release
* 3.18 gm 08/25/23 Added function prototypes for XIicPs_MasterPolledRead,
* XIicPs_MasterIntrSend, XIicPs_MasterIntrRead and
* XIicPs_MasterRead.
* </pre>
*
******************************************************************************/
/** @cond INTERNAL */
#ifndef XIICPS_XFER_H /* prevent circular inclusions */
#define XIICPS_XFER_H /**< by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xiicps.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/*****************************************************************************/
/**
*
* Checks if Rx data is valid or not.
*
* @param InstancePtr Pointer to the XIicPs instance.
*
* @return The return value is '1' if Rx data is valid, '0' otherwise.
*
* @note None.
*
******************************************************************************/
static INLINE u32 XIicPs_RxDataValid(XIicPs *InstancePtr)
{
return ((XIicPs_ReadReg(InstancePtr->Config.BaseAddress, XIICPS_SR_OFFSET))
& XIICPS_SR_RXDV_MASK);
}
/*****************************************************************************/
/**
*
* Checks if Rx FIFO is full or not.
*
* @param InstancePtr Pointer to the XIicPs instance.
* @param ByteCountVar Number of bytes to be received.
*
* @return The return value is '0' if Rx FIFO is full, '1' otherwise.
*
* @note None.
*
******************************************************************************/
static INLINE u32 XIicPs_RxFIFOFull(XIicPs *InstancePtr, s32 ByteCountVar)
{
u32 Status = 0;
Status = (u32)(XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
XIICPS_TRANS_SIZE_OFFSET) !=(u32)(ByteCountVar -
(s32)XIICPS_FIFO_DEPTH));
return Status;
}
/************************** Variable Definitions *****************************/
/************************** Function Prototypes ******************************/
/*
* This function prepares a device to transfer as a master.
*/
s32 XIicPs_SetupMaster(XIicPs *InstancePtr, s32 Role);
/*
* This function handles continuation of sending data.
*/
void MasterSendData(XIicPs *InstancePtr);
/*
* This function handles polled mode receive in master mode.
*/
void XIicPs_MasterPolledRead(XIicPs *InstancePtr, s32 IsHold, s32 ByteCountVar);
/*
* This function handles interrupt-driven send in master mode.
*/
void XIicPs_MasterIntrSend(XIicPs *InstancePtr, u32 IntrStatusReg,
u32 *StatusEventPtr);
/*
* This function handles interrupt-driven receive in master mode.
*/
void XIicPs_MasterIntrRead(XIicPs *InstancePtr, u32 *IntrStatusRegPtr,
s32 IsHold);
/*
* This function handles interrupt-driven send in master mode.
*/
void XIicPs_MasterRead(XIicPs *InstancePtr, s32 IsHold, s32 *ByteCntPtr);
/*
* This function handles continuation of receiving data.
*/
s32 SlaveRecvData(XIicPs *InstancePtr);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/** @endcond */
/** @} */
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/xil_assert.h
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/******************************************************************************
* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_assert.h
*
* @addtogroup common_assert_apis Assert APIs and Macros
*
* The xil_assert.h file contains assert related functions and macros.
* Assert APIs/Macros specifies that a application program satisfies certain
* conditions at particular points in its execution. These function can be
* used by application programs to ensure that, application code is satisfying
* certain conditions.
*
* @{
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a hbm 07/14/09 First release
* 6.0 kvn 05/31/16 Make Xil_AsserWait a global variable
* </pre>
*
******************************************************************************/
/**
*@cond nocomments
*/
#ifndef XIL_ASSERT_H /* prevent circular inclusions */
#define XIL_ASSERT_H /* by using protection macros */
#include "xil_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
/************************** Constant Definitions *****************************/
#define XIL_ASSERT_NONE 0U
#define XIL_ASSERT_OCCURRED 1U
#define XNULL NULL
extern u32 Xil_AssertStatus;
extern s32 Xil_AssertWait;
extern void Xil_Assert(const char8 *File, s32 Line);
/**
*@endcond
*/
void XNullHandler(void *NullParameter);
/**
* This data type defines a callback to be invoked when an
* assert occurs. The callback is invoked only when asserts are enabled
*/
typedef void (*Xil_AssertCallback) (const char8 *File, s32 Line);
/***************** Macros (Inline Functions) Definitions *********************/
#ifndef NDEBUG
/*****************************************************************************/
/**
* @brief This assert macro is to be used for void functions. This in
* conjunction with the Xil_AssertWait boolean can be used to
* accommodate tests so that asserts which fail allow execution to
* continue.
*
* @param Expression: expression to be evaluated. If it evaluates to
* false, the assert occurs.
*
* @return Returns void unless the Xil_AssertWait variable is true, in which
* case no return is made and an infinite loop is entered.
*
******************************************************************************/
#define Xil_AssertVoid(Expression) \
{ \
if (Expression) { \
Xil_AssertStatus = XIL_ASSERT_NONE; \
} else { \
Xil_Assert(__FILE__, __LINE__); \
Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
return; \
} \
}
/*****************************************************************************/
/**
* @brief This assert macro is to be used for functions that do return a
* value. This in conjunction with the Xil_AssertWait boolean can be
* used to accommodate tests so that asserts which fail allow execution
* to continue.
*
* @param Expression: expression to be evaluated. If it evaluates to false,
* the assert occurs.
*
* @return Returns 0 unless the Xil_AssertWait variable is true, in which
* case no return is made and an infinite loop is entered.
*
******************************************************************************/
#define Xil_AssertNonvoid(Expression) \
{ \
if (Expression) { \
Xil_AssertStatus = XIL_ASSERT_NONE; \
} else { \
Xil_Assert(__FILE__, __LINE__); \
Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
return 0; \
} \
}
/*****************************************************************************/
/**
* @brief Always assert. This assert macro is to be used for void functions.
* Use for instances where an assert should always occur.
*
* @return Returns void unless the Xil_AssertWait variable is true, in which
* case no return is made and an infinite loop is entered.
*
******************************************************************************/
#define Xil_AssertVoidAlways() \
{ \
Xil_Assert(__FILE__, __LINE__); \
Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
return; \
}
/*****************************************************************************/
/**
* @brief Always assert. This assert macro is to be used for functions that
* do return a value. Use for instances where an assert should always
* occur.
*
* @return Returns void unless the Xil_AssertWait variable is true, in which
* case no return is made and an infinite loop is entered.
*
******************************************************************************/
#define Xil_AssertNonvoidAlways() \
{ \
Xil_Assert(__FILE__, __LINE__); \
Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
return 0; \
}
#else
#define Xil_AssertVoid(Expression)
#define Xil_AssertVoidAlways()
#define Xil_AssertNonvoid(Expression)
#define Xil_AssertNonvoidAlways()
#endif
/************************** Function Prototypes ******************************/
void Xil_AssertSetCallback(Xil_AssertCallback Routine);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/**
* @} End of "addtogroup common_assert_apis".
*/
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/xil_cache.h
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/******************************************************************************
* Copyright (C) 2014 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_cache.h
*
* @addtogroup a53_64_cache_apis Cortex A53 64bit Processor Cache Functions
*
* Cache functions provide access to cache related operations such as flush
* and invalidate for instruction and data caches. It gives option to perform
* the cache operations on a single cacheline, a range of memory and an entire
* cache.
*
* @{
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 5.00 pkp 05/29/14 First release
* 9.00 ml 03/03/23 Add description to fix doxygen warnings.
* </pre>
*
******************************************************************************/
#ifndef XIL_CACHE_H
#define XIL_CACHE_H
#include "xil_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*@cond nocomments
*/
/************************** Constant Definitions *****************************/
#define L1_DATA_PREFETCH_CONTROL_MASK 0xE000
#define L1_DATA_PREFETCH_CONTROL_SHIFT 13
/**
*@endcond
*/
/***************** Macros (Inline Functions) Definitions *********************/
#define Xil_DCacheFlushRange Xil_DCacheInvalidateRange /**< DCache range */
/************************** Function Prototypes ******************************/
void Xil_DCacheEnable(void);
void Xil_DCacheDisable(void);
void Xil_DCacheInvalidate(void);
void Xil_DCacheInvalidateRange(INTPTR adr, INTPTR len);
void Xil_DCacheInvalidateLine(INTPTR adr);
void Xil_DCacheFlush(void);
void Xil_DCacheFlushLine(INTPTR adr);
void Xil_ICacheEnable(void);
void Xil_ICacheDisable(void);
void Xil_ICacheInvalidate(void);
void Xil_ICacheInvalidateRange(INTPTR adr, INTPTR len);
void Xil_ICacheInvalidateLine(INTPTR adr);
void Xil_ConfigureL1Prefetch(u8 num);
#ifdef __cplusplus
}
#endif
#endif
/**
* @} End of "addtogroup a53_64_cache_apis".
*/
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/xil_cache_vxworks.h
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/******************************************************************************
* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_cache_vxworks.h
*
* Contains the cache related functions for VxWorks that is wrapped by
* xil_cache.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a hbm 12/11/09 Initial release
*
* </pre>
*
* @note
*
******************************************************************************/
/**
*@cond nocomments
*/
#ifndef XIL_CACHE_VXWORKS_H
#define XIL_CACHE_VXWORKS_H
#ifdef __cplusplus
extern "C" {
#endif
#include "vxWorks.h"
#include "vxLib.h"
#include "sysLibExtra.h"
#include "cacheLib.h"
#if (CPU_FAMILY==PPC)
#define Xil_DCacheEnable() cacheEnable(DATA_CACHE)
#define Xil_DCacheDisable() cacheDisable(DATA_CACHE)
#define Xil_DCacheInvalidateRange(Addr, Len) \
cacheInvalidate(DATA_CACHE, (void *)(Addr), (Len))
#define Xil_DCacheFlushRange(Addr, Len) \
cacheFlush(DATA_CACHE, (void *)(Addr), (Len))
#define Xil_ICacheEnable() cacheEnable(INSTRUCTION_CACHE)
#define Xil_ICacheDisable() cacheDisable(INSTRUCTION_CACHE)
#define Xil_ICacheInvalidateRange(Addr, Len) \
cacheInvalidate(INSTRUCTION_CACHE, (void *)(Addr), (Len))
#else
#error "Unknown processor / architecture. Must be PPC for VxWorks."
#endif
#ifdef __cplusplus
}
#endif
#endif
/**
*@endcond
*/
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/xil_clocking.h
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/******************************************************************************
* Copyright (c) 2020 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_clocking.h
*
* The xil_clocking.h file contains clocking related functions and macros.
* certain conditions.
*
* @{
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 7.2 sd 12/11/19 First release
* 7.2 sd 03/20/20 Added checking for isolation case
* 7.7 sk 01/10/22 Add function prototype for Xil_ClockGetRate to fix
* misra_c_2012_rule_8_4 violation.
* 9.0 ml 03/03/23 Added description to fix doxygen warnings.
* </pre>
*
******************************************************************************/
#ifndef XIL_CLOCKING_H /**< prevent circular inclusions */
#define XIL_CLOCKING_H /**< by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
#include "xdebug.h"
#include "xil_printf.h"
#include "xil_types.h"
#include "xil_assert.h"
#include "xparameters.h"
#include "xstatus.h"
#if defined (XPAR_XCRPSU_0_DEVICE_ID) || defined(XPAR_PSU_CRL_APB_BASEADDR)
#include "xclockps.h"
#else
typedef u32 XClock_OutputClks;
typedef u64 XClockRate;
#endif
/***************************** Include Files *********************************/
/************************** Constant Definitions *****************************/
XStatus Xil_ClockDisable(XClock_OutputClks ClockId);
XStatus Xil_ClockEnable(XClock_OutputClks ClockId);
XStatus Xil_ClockInit(void);
XStatus Xil_ClockGet(void);
XStatus Xil_ClockSetRate(XClock_OutputClks ClockId, XClockRate Rate, XClockRate *SetRate);
XStatus Xil_ClockGetRate(XClock_OutputClks ClockId, XClockRate *Rate);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/xil_cryptoalginfo.h
+50
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@@ -0,0 +1,50 @@
/******************************************************************************/
/**
* Copyright (c) 2023 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/****************************************************************************/
/**
* @file xil_cryptoalginfo.h
* @{
* @details
*
* Crypto algotithm information structure declaration.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- -------- -------- -----------------------------------------------
* 9.0 mmd 07/04/23 First release.
* </pre>
*
*****************************************************************************/
#ifndef XIL_CRYPTOALGINFO_H
#define XIL_CRYPTOALGINFO_H
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
/**************************** Type Definitions *******************************/
typedef enum _Xil_CryptoAlgNistStatus {
NOT_APPLICABLE = 0x00,
NIST_COMPLIANT = 0x11,
NIST_NON_COMPLIANT = 0xFE,
} Xil_CryptoAlgNistStatus;
typedef struct _Xil_CryptoAlgInfo {
u32 Version;
Xil_CryptoAlgNistStatus NistStatus;
} Xil_CryptoAlgInfo;
#ifdef __cplusplus
}
#endif
#endif /* XIL_CRYPTOALGINFO_H */
dj_47dr_ibert/vitis_classic/system_top/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/psu_cortexa53_0/include/xil_errata.h
+67
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/******************************************************************************
* Copyright (c) 2017 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_errata.h
*
* @addtogroup a53_errata Cortex A53 64 bit Processor Errata Support
* @{
* Various ARM errata are handled in the standalone BSP. The implementation for
* errata handling follows ARM guidelines and is based on the open source Linux
* support for these errata.
*
* @note
* The errata handling is enabled by default. To disable handling of all the
* errata globally, un-define the macro ENABLE_ARM_ERRATA in xil_errata.h. To
* disable errata on a per-erratum basis, un-define relevant macros in
* xil_errata.h.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 6.4 mus 08/11/17 First release
* </pre>
*
******************************************************************************/
#ifndef XIL_ERRATA_H
#define XIL_ERRATA_H
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name errata_definitions
*
* The errata conditions handled in the standalone BSP are listed below
* @{
*/
#define ENABLE_ARM_ERRATA 1
#ifdef ENABLE_ARM_ERRATA
/**
* Errata No: 855873
* Description: An eviction might overtake a cache clean operation
*/
#define CONFIG_ARM_ERRATA_855873 1
/*@}*/
#endif /* ENABLE_ARM_ERRATA */
#ifdef __cplusplus
}
#endif
#endif /* XIL_ERRATA_H */
/**
* @} End of "addtogroup a53_errata".
*/

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