From b0e7676af212bf0b6535045d8f8aab8abbe47395 Mon Sep 17 00:00:00 2001 From: Josh Gao Date: Mon, 28 Oct 2024 15:41:16 +0800 Subject: [PATCH] add dj_47dr_lmx vivado project --- dj_47dr_lmx/.gitignore | 119 + .../dj_47dr_lmx.runs/impl_1/debug_nets.ltx | 1458 ++++ .../dj_47dr_lmx.runs/impl_1/system_top.bit | 3 + .../dj_47dr_lmx.runs/impl_1/system_top.ltx | 1458 ++++ .../constrs_1/new/dj_47dr.xdc | 20 + .../system_bd_auto_pc_0.xci | 304 + .../system_bd_axi_spi_engine_0_0.xci | 294 + .../system_bd_clk_wiz_0_0.xci | 658 ++ .../system_bd_ps8_0_axi_periph_0.xci | 353 + .../system_bd_rst_ps8_0_96M_0.xci | 196 + .../system_bd_spi_engine_execution_0_0.xci | 176 + .../system_bd_usp_rf_data_converter_0_0.xci | 3117 ++++++++ .../system_bd_util_ds_buf_0_0.xci | 99 + .../system_bd_util_ds_buf_0_1.xci | 102 + .../system_bd_util_ds_buf_1_0.xci | 99 + .../ip/system_bd_xbar_0/system_bd_xbar_0.xci | 1523 ++++ .../system_bd_xlconcat_0_0.xci | 308 + .../system_bd_xlconstant_0_0.xci | 50 + .../system_bd_xpm_cdc_gen_0_0.xci | 126 + .../system_bd_xpm_cdc_gen_pl_sysref_0.xci | 126 + .../system_bd_zynq_ultra_ps_e_0_1.xci | 2045 ++++++ .../sources_1/bd/system_bd/system_bd.bd | 4907 +++++++++++++ .../sources_1/bd/system_bd/system_bd.bda | 249 + .../sources_1/bd/system_bd/ui/bd_2942602e.ui | 34 + .../sources_1/bd/system_bd/ui/bd_af01e55c.ui | 34 + .../sources_1/bd/system_bd/ui/bd_c6d0cb12.ui | 179 + .../sources_1/bd/system_bd/ui/bd_e4e34314.ui | 28 + .../sources_1/bd/system_bd/ui/bd_ea40ff00.ui | 26 + .../sources_1/ip/cmpy_18x8/cmpy_18x8.xci | 213 + .../sources_1/ip/dds_32b_8b/dds_32b_8b.xci | 358 + .../sources_1/ip/hop_rom/hop_rom.xci | 254 + .../sources_1/ip/hrc_64_12_025.coe | 771 ++ .../ip/hrc_64_12_025/hrc_64_12_025.xci | 350 + .../sources_1/ip/ila_adc/ila_adc.xci | 6314 +++++++++++++++++ .../sources_1/ip/ila_dac/ila_dac.xci | 6300 ++++++++++++++++ .../sources_1/ip/sweep_freq.coe | 258 + .../ip/vio_manual_ctrl/vio_manual_ctrl.xci | 1632 +++++ .../sources_1/new/system_top.v | 716 ++ .../dj_47dr_lmx.srcs/sources_1/new/tx_qpsk.v | 539 ++ .../utils_1/imports/synth_1/system_top.dcp | 3 + dj_47dr_lmx/dj_47dr_lmx.xpr | 990 +++ dj_47dr_lmx/system_top.xsa | 3 + 42 files changed, 36792 insertions(+) create mode 100644 dj_47dr_lmx/.gitignore create mode 100644 dj_47dr_lmx/dj_47dr_lmx.runs/impl_1/debug_nets.ltx create mode 100644 dj_47dr_lmx/dj_47dr_lmx.runs/impl_1/system_top.bit create mode 100644 dj_47dr_lmx/dj_47dr_lmx.runs/impl_1/system_top.ltx create mode 100644 dj_47dr_lmx/dj_47dr_lmx.srcs/constrs_1/new/dj_47dr.xdc create mode 100644 dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ip/system_bd_auto_pc_0/system_bd_auto_pc_0.xci create mode 100644 dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0.xci create mode 100644 dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ip/system_bd_clk_wiz_0_0/system_bd_clk_wiz_0_0.xci create mode 100644 dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ip/system_bd_ps8_0_axi_periph_0/system_bd_ps8_0_axi_periph_0.xci create mode 100644 dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ip/system_bd_rst_ps8_0_96M_0/system_bd_rst_ps8_0_96M_0.xci create mode 100644 dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ip/system_bd_spi_engine_execution_0_0/system_bd_spi_engine_execution_0_0.xci create mode 100644 dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ip/system_bd_usp_rf_data_converter_0_0/system_bd_usp_rf_data_converter_0_0.xci create mode 100644 dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ip/system_bd_util_ds_buf_0_0/system_bd_util_ds_buf_0_0.xci create mode 100644 dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ip/system_bd_util_ds_buf_0_1/system_bd_util_ds_buf_0_1.xci create mode 100644 dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ip/system_bd_util_ds_buf_1_0/system_bd_util_ds_buf_1_0.xci create mode 100644 dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ip/system_bd_xbar_0/system_bd_xbar_0.xci create mode 100644 dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ip/system_bd_xlconcat_0_0/system_bd_xlconcat_0_0.xci create mode 100644 dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ip/system_bd_xlconstant_0_0/system_bd_xlconstant_0_0.xci create mode 100644 dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ip/system_bd_xpm_cdc_gen_0_0/system_bd_xpm_cdc_gen_0_0.xci create mode 100644 dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ip/system_bd_xpm_cdc_gen_pl_sysref_0/system_bd_xpm_cdc_gen_pl_sysref_0.xci create mode 100644 dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ip/system_bd_zynq_ultra_ps_e_0_1/system_bd_zynq_ultra_ps_e_0_1.xci create mode 100644 dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/system_bd.bd create mode 100644 dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/system_bd.bda create mode 100644 dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ui/bd_2942602e.ui create mode 100644 dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ui/bd_af01e55c.ui create mode 100644 dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ui/bd_c6d0cb12.ui create mode 100644 dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ui/bd_e4e34314.ui create mode 100644 dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ui/bd_ea40ff00.ui create mode 100644 dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/ip/cmpy_18x8/cmpy_18x8.xci create mode 100644 dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/ip/dds_32b_8b/dds_32b_8b.xci create mode 100644 dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/ip/hop_rom/hop_rom.xci create mode 100644 dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/ip/hrc_64_12_025.coe create mode 100644 dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/ip/hrc_64_12_025/hrc_64_12_025.xci create mode 100644 dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/ip/ila_adc/ila_adc.xci create mode 100644 dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/ip/ila_dac/ila_dac.xci create mode 100644 dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/ip/sweep_freq.coe create mode 100644 dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/ip/vio_manual_ctrl/vio_manual_ctrl.xci create mode 100644 dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/new/system_top.v create mode 100644 dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/new/tx_qpsk.v create mode 100644 dj_47dr_lmx/dj_47dr_lmx.srcs/utils_1/imports/synth_1/system_top.dcp create mode 100644 dj_47dr_lmx/dj_47dr_lmx.xpr create mode 100644 dj_47dr_lmx/system_top.xsa diff --git a/dj_47dr_lmx/.gitignore b/dj_47dr_lmx/.gitignore new file mode 100644 index 0000000..15117b5 --- /dev/null +++ b/dj_47dr_lmx/.gitignore @@ -0,0 +1,119 @@ +################################################################################ +############################### Project Specific ############################### +################################################################################ +# everything +* + +# git related +!/.gitignore +!/.gitattributes + +# project documents +!/*.md +!/*.txt + +################################################################################ +############################### Vivado Specific ################################ +################################################################################ + +# xpr: needed for recreating design +!/*.xpr + +# source: include everything +!/*.srcs/ +!/*.srcs/**/* + +# runs: exclude everything but design run results +!/*.runs/ +!/*.runs/impl_*/ +!/*.runs/impl_*/*.bit +!/*.runs/impl_*/*.ltx + +# xsa (Xilinx support archive): include for ps +!/*.xsa + +################################################################################ +################################ Vitis Specific ################################ +################################################################################ + +# include sdk directory and everything in it +!/vitis*/ +!/vitis*/** +/vitis*/**.log +/vitis*/.analytics + +# exclude some obscure hidden SDK folders +/vitis*/.metadata/ +/vitis*/.sdk/ +/vitis*/RemoteSystemsTempFiles/ +/vitis*/webtalk/ + +# hw_platform: exclude the entire hw_platform folder, as everything can be +# generated from the .hdf file. Make sure to include the bitstream in the .hdf +# file when exporting from Vivado! +/vitis*/*_hw_platform_*/ + +# BSP: only keep `.cproject`, `.project`, `.sdkproject`, `.system.mss` and +# Makefile, ps lib files are regenerated automatically +/vitis*/*_bsp/* +!/vitis*/*_bsp/*.cproject +!/vitis*/*_bsp/*.project +!/vitis*/*_bsp/*.sdkproject +!/vitis*/*_bsp/system.mss +!/vitis*/*_bsp/Makefile + +# Application: ignored file patterns, exclude Debug & Release folders +/vitis*/**/*.o +/vitis*/**/*.d +/vitis*/**/*.a +/vitis*/*/Debug/ +/vitis*/*/Release/ + +################################################################################ +############################ Vivado & Vitis Common ############################# +################################################################################ + +# file patterns that should always be ignored (journal files, log files, dump +# files that are created upon Vivado/SDK errors) +*.jou +*.log +*.backup.jou +*.backup.log +*.upgrade_log +*.dmp +*.debug +vivado_pid* + +# vivado workspace files +xsim.dir/ +xvlog.pb + +# Xilinx tools generated files +.metadata/ +.settings/ +.wsdata/ +.Xil/ +logs/ +Packages/ +*.log* + +# System generated files +# -- macOS +.DS_Store +.AppleDouble +.LSOverride +._* + +# -- Windows +Thumbs.db +ehthumbs.db +Desktop.ini + +# -- Linux +*~ + +# IDEs and editors' files +*.idea +*.vscode +*.sublime-workspace +*.sublime-project diff --git a/dj_47dr_lmx/dj_47dr_lmx.runs/impl_1/debug_nets.ltx b/dj_47dr_lmx/dj_47dr_lmx.runs/impl_1/debug_nets.ltx new file mode 100644 index 0000000..f27ec25 --- /dev/null +++ b/dj_47dr_lmx/dj_47dr_lmx.runs/impl_1/debug_nets.ltx @@ -0,0 +1,1458 @@ +{ + "ltx_root": { + "version": 4, + "minor": 0, + "ltx_data": [ + { + "name": "EDA_PROBESET", + "active": true, + "debug_cores": [ + { + "type": "XSDB_V3", + "name": "dbg_hub", + "spec": "labtools_xsdbm_v3", + "clk_input_freq_hz": "245760640" + }, + { + "type": "ILA_V3", + "name": "u_ila_adc", + "spec": "labtools_ila_v6", + "ipName": "ila", + "core_location": { + "user_chain": 1, + "slave_index": 0, + "bscan_switch_index": 0 + }, + "uuid": "507FFF6187E459B698B8EBFAEAD80858", + "pins": [ + { + "name": "probe0", + "id": 0, + "type": "DATA_TRIGGER", + "direction": "IN", + "isVector": true, + "leftIndex": 0, + "rightIndex": 15, + "portIndex": 0, + "nets": [ + { + "name": "rx_ch1_i", + "isBus": true, + "subnets": [ + { + "name": "rx_ch1_i[15]" + }, + { + "name": "rx_ch1_i[14]" + }, + { + "name": "rx_ch1_i[13]" + }, + { + "name": "rx_ch1_i[12]" + }, + { + "name": "rx_ch1_i[11]" + }, + { + "name": "rx_ch1_i[10]" + }, + { + "name": "rx_ch1_i[9]" + }, + { + "name": "rx_ch1_i[8]" + }, + { + "name": "rx_ch1_i[7]" + }, + { + "name": "rx_ch1_i[6]" + }, + { + "name": "rx_ch1_i[5]" + }, + { + "name": "rx_ch1_i[4]" + }, + { + "name": "rx_ch1_i[3]" + }, + { + "name": "rx_ch1_i[2]" + }, + { + "name": "rx_ch1_i[1]" + }, + { + "name": "rx_ch1_i[0]" + } + ] + } + ] + }, + { + "name": "probe1", + "id": 1, + "type": "DATA_TRIGGER", + "direction": "IN", + "isVector": true, + "leftIndex": 0, + "rightIndex": 15, + "portIndex": 1, + "nets": [ + { + "name": "rx_ch1_q", + "isBus": true, + "subnets": [ + { + "name": "rx_ch1_q[15]" + }, + { + "name": "rx_ch1_q[14]" + }, + { + "name": "rx_ch1_q[13]" + }, + { + "name": "rx_ch1_q[12]" + }, + { + "name": "rx_ch1_q[11]" + }, + { + "name": "rx_ch1_q[10]" + }, + { + "name": "rx_ch1_q[9]" + }, + { + "name": "rx_ch1_q[8]" + }, + { + "name": "rx_ch1_q[7]" + }, + { + "name": "rx_ch1_q[6]" + }, + { + "name": "rx_ch1_q[5]" + }, + { + "name": "rx_ch1_q[4]" + }, + { + "name": "rx_ch1_q[3]" + }, + { + "name": "rx_ch1_q[2]" + }, + { + "name": "rx_ch1_q[1]" + }, + { + "name": "rx_ch1_q[0]" + } + ] + } + ] + }, + { + "name": "probe2", + "id": 2, + "type": "DATA_TRIGGER", + "direction": "IN", + "isVector": true, + "leftIndex": 0, + "rightIndex": 15, + "portIndex": 2, + "nets": [ + { + "name": "rx_ch2_i", + "isBus": true, + "subnets": [ + { + "name": "rx_ch2_i[15]" + }, + { + "name": "rx_ch2_i[14]" + }, + { + "name": "rx_ch2_i[13]" + }, + { + "name": "rx_ch2_i[12]" + }, + { + "name": "rx_ch2_i[11]" + }, + { + "name": "rx_ch2_i[10]" + }, + { + "name": "rx_ch2_i[9]" + }, + { + "name": "rx_ch2_i[8]" + }, + { + "name": "rx_ch2_i[7]" + }, + { + "name": "rx_ch2_i[6]" + }, + { + "name": "rx_ch2_i[5]" + }, + { + "name": "rx_ch2_i[4]" + }, + { + "name": "rx_ch2_i[3]" + }, + { + "name": "rx_ch2_i[2]" + }, + { + "name": "rx_ch2_i[1]" + }, + { + "name": "rx_ch2_i[0]" + } + ] + } + ] + }, + { + "name": "probe3", + "id": 3, + "type": "DATA_TRIGGER", + "direction": "IN", + "isVector": true, + "leftIndex": 0, + "rightIndex": 15, + "portIndex": 3, + "nets": [ + { + "name": "rx_ch2_q", + "isBus": true, + "subnets": [ + { + "name": "rx_ch2_q[15]" + }, + { + "name": "rx_ch2_q[14]" + }, + { + "name": "rx_ch2_q[13]" + }, + { + "name": "rx_ch2_q[12]" + }, + { + "name": "rx_ch2_q[11]" + }, + { + "name": "rx_ch2_q[10]" + }, + { + "name": "rx_ch2_q[9]" + }, + { + "name": "rx_ch2_q[8]" + }, + { + "name": "rx_ch2_q[7]" + }, + { + "name": "rx_ch2_q[6]" + }, + { + "name": "rx_ch2_q[5]" + }, + { + "name": "rx_ch2_q[4]" + }, + { + "name": "rx_ch2_q[3]" + }, + { + "name": "rx_ch2_q[2]" + }, + { + "name": "rx_ch2_q[1]" + }, + { + "name": "rx_ch2_q[0]" + } + ] + } + ] + }, + { + "name": "probe4", + "id": 4, + "type": "DATA_TRIGGER", + "direction": "IN", + "isVector": true, + "leftIndex": 0, + "rightIndex": 15, + "portIndex": 4, + "nets": [ + { + "name": "rx_ch3_i", + "isBus": true, + "subnets": [ + { + "name": "rx_ch3_i[15]" + }, + { + "name": "rx_ch3_i[14]" + }, + { + "name": "rx_ch3_i[13]" + }, + { + "name": "rx_ch3_i[12]" + }, + { + "name": "rx_ch3_i[11]" + }, + { + "name": "rx_ch3_i[10]" + }, + { + "name": "rx_ch3_i[9]" + }, + { + "name": "rx_ch3_i[8]" + }, + { + "name": "rx_ch3_i[7]" + }, + { + "name": "rx_ch3_i[6]" + }, + { + "name": "rx_ch3_i[5]" + }, + { + "name": "rx_ch3_i[4]" + }, + { + "name": "rx_ch3_i[3]" + }, + { + "name": "rx_ch3_i[2]" + }, + { + "name": "rx_ch3_i[1]" + }, + { + "name": "rx_ch3_i[0]" + } + ] + } + ] + }, + { + "name": "probe5", + "id": 5, + "type": "DATA_TRIGGER", + "direction": "IN", + "isVector": true, + "leftIndex": 0, + "rightIndex": 15, + "portIndex": 5, + "nets": [ + { + "name": "rx_ch3_q", + "isBus": true, + "subnets": [ + { + "name": "rx_ch3_q[15]" + }, + { + "name": "rx_ch3_q[14]" + }, + { + "name": "rx_ch3_q[13]" + }, + { + "name": "rx_ch3_q[12]" + }, + { + "name": "rx_ch3_q[11]" + }, + { + "name": "rx_ch3_q[10]" + }, + { + "name": "rx_ch3_q[9]" + }, + { + "name": "rx_ch3_q[8]" + }, + { + "name": "rx_ch3_q[7]" + }, + { + "name": "rx_ch3_q[6]" + }, + { + "name": "rx_ch3_q[5]" + }, + { + "name": "rx_ch3_q[4]" + }, + { + "name": "rx_ch3_q[3]" + }, + { + "name": "rx_ch3_q[2]" + }, + { + "name": "rx_ch3_q[1]" + }, + { + "name": "rx_ch3_q[0]" + } + ] + } + ] + }, + { + "name": "probe6", + "id": 6, + "type": "DATA_TRIGGER", + "direction": "IN", + "isVector": true, + "leftIndex": 0, + "rightIndex": 15, + "portIndex": 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} + ] + }, + { + "name": "probe_out3", + "id": 21, + "type": "DATA", + "direction": "OUT", + "isVector": true, + "leftIndex": 0, + "rightIndex": 1, + "portIndex": 3, + "nets": [ + { + "name": "iq_sel", + "isBus": true, + "subnets": [ + { + "name": "iq_sel[1]" + }, + { + "name": "iq_sel[0]" + } + ] + } + ] + }, + { + "name": "probe_out4", + "id": 22, + "type": "DATA", + "direction": "OUT", + "isVector": true, + "leftIndex": 0, + "rightIndex": 3, + "portIndex": 4, + "nets": [ + { + "name": "bb_rshift", + "isBus": true, + "subnets": [ + { + "name": "bb_rshift[3]" + }, + { + "name": "bb_rshift[2]" + }, + { + "name": "bb_rshift[1]" + }, + { + "name": "bb_rshift[0]" + } + ] + } + ] + } + ] + } + ] + } + ] + } +} \ No newline at end of file diff --git a/dj_47dr_lmx/dj_47dr_lmx.srcs/constrs_1/new/dj_47dr.xdc b/dj_47dr_lmx/dj_47dr_lmx.srcs/constrs_1/new/dj_47dr.xdc new file mode 100644 index 0000000..7defd1b --- /dev/null +++ b/dj_47dr_lmx/dj_47dr_lmx.srcs/constrs_1/new/dj_47dr.xdc @@ -0,0 +1,20 @@ +set_property -dict {PACKAGE_PIN F14 IOSTANDARD LVPECL } [get_ports pl_refclk_p ] ;# PL_CLK_P +set_property -dict {PACKAGE_PIN F10 IOSTANDARD LVPECL } [get_ports pl_sysref_p ] ;# PL_SYSREF_P + +set_property -dict {PACKAGE_PIN B13 IOSTANDARD LVCMOS33} [get_ports lmk_spi_sck ] ;# LMK_SPI_SCK +set_property -dict {PACKAGE_PIN A13 IOSTANDARD LVCMOS33} [get_ports lmk_spi_cs ] ;# LMK_SPI_CS +set_property -dict {PACKAGE_PIN C14 IOSTANDARD LVCMOS33} [get_ports lmk_spi_mosi ] ;# LMK_SPI_SDI +set_property -dict {PACKAGE_PIN A14 IOSTANDARD LVCMOS33} [get_ports lmk_spi_miso ] ;# LMK_SPI_SDO + +set_property -dict {PACKAGE_PIN H13 IOSTANDARD LVCMOS33} [get_ports lmx_adc_spi_sck ] ;# LMX_RF_ADC_SCK +set_property -dict {PACKAGE_PIN K14 IOSTANDARD LVCMOS33} [get_ports lmx_adc_spi_cs ] ;# LMX_RF_ADC_CS +set_property -dict {PACKAGE_PIN J13 IOSTANDARD LVCMOS33} [get_ports lmx_adc_spi_mosi ] ;# LMX_RF_ADC_SDI +set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVCMOS33} [get_ports lmx_adc_spi_miso ] ;# LMX_RF_ADC_SDO + +set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS33} [get_ports lmx_dac_spi_sck ] ;# LMX_RF_DAC_CLK +set_property -dict {PACKAGE_PIN G13 IOSTANDARD LVCMOS33} [get_ports lmx_dac_spi_cs ] ;# LMX_RF_DAC_CS +set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVCMOS33} [get_ports lmx_dac_spi_mosi ] ;# LMX_RF_DAC_SDI +set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS33} [get_ports lmx_dac_spi_miso ] ;# LMX_RF_DAC_SDO + +# Route HDGC clock through BUFG to adjacent CMT +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets u_system_bd_wrapper/system_bd_i/mts_clk_gen/util_ds_buf_pl_clk/U0/USE_IBUFDS.GEN_IBUFDS[0].IBUFDS_I/O] diff --git a/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ip/system_bd_auto_pc_0/system_bd_auto_pc_0.xci b/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ip/system_bd_auto_pc_0/system_bd_auto_pc_0.xci new file mode 100644 index 0000000..4d7333c --- /dev/null +++ b/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ip/system_bd_auto_pc_0/system_bd_auto_pc_0.xci @@ -0,0 +1,304 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "system_bd_auto_pc_0", + "cell_name": "ps8_0_axi_periph/s00_couplers/auto_pc", + "component_reference": "xilinx.com:ip:axi_protocol_converter:2.1", + "ip_revision": "31", + "gen_directory": "../../../../../../dj_47dr_lmx.gen/sources_1/bd/system_bd/ip/system_bd_auto_pc_0", + "parameters": { + "component_parameters": { + "SI_PROTOCOL": [ { "value": "AXI4", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ], + "MI_PROTOCOL": [ { "value": "AXI4LITE", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ], + "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ], + "TRANSLATION_MODE": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ], + "ADDR_WIDTH": [ { "value": "40", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "DATA_WIDTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "ID_WIDTH": [ { "value": "16", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "AWUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "ARUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "RUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "WUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "BUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "Component_Name": [ { "value": "system_bd_auto_pc_0", "resolve_type": "user", "usage": "all" } ] + }, + "model_parameters": { + "C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ], + "C_M_AXI_PROTOCOL": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_S_AXI_PROTOCOL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_IGNORE_ID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI_ID_WIDTH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI_ADDR_WIDTH": [ { "value": "40", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI_SUPPORTS_WRITE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI_SUPPORTS_READ": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI_SUPPORTS_USER_SIGNALS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI_AWUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI_ARUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI_WUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI_RUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI_BUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_TRANSLATION_MODE": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ] + }, + "project_parameters": { + "ARCHITECTURE": [ { "value": "zynquplusRFSOC" } ], + "BASE_BOARD_PART": [ { "value": "" } ], + "BOARD_CONNECTIONS": [ { "value": "" } ], + "DEVICE": [ { "value": "xczu47dr" } ], + "NEXTGEN_VERSAL": [ { "value": "0" } ], + "PACKAGE": [ { "value": "ffve1156" } ], + "PREFHDL": [ { "value": "VERILOG" } ], + "SILICON_REVISION": [ { "value": "" } ], + "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], + "SPEEDGRADE": [ { "value": "-2" } ], + "STATIC_POWER": [ { "value": "" } ], + "TEMPERATURE_GRADE": [ { "value": "I" } ] + }, + "runtime_parameters": { + "IPCONTEXT": [ { "value": "IP_Integrator" } ], + "IPREVISION": [ { "value": "31" } ], + "MANAGED": [ { "value": "TRUE" } ], + "OUTPUTDIR": [ { "value": "../../../../../../dj_47dr_lmx.gen/sources_1/bd/system_bd/ip/system_bd_auto_pc_0" } ], + "SELECTEDSIMMODEL": [ { "value": "rtl" } ], + "SHAREDDIR": [ { "value": "../../ipshared" } ], + "SWVERSION": [ { "value": "2024.1" } ], + "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ] + } + }, + "boundary": { + "ports": { + "aclk": [ { "direction": "in" } ], + "aresetn": [ { "direction": "in" } ], + "s_axi_awid": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0x0000" } ], + "s_axi_awaddr": [ { "direction": "in", "size_left": "39", "size_right": "0", "driver_value": "0x0000000000" } ], + "s_axi_awlen": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0x00" } ], + "s_axi_awsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ], + "s_axi_awburst": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x1" } ], + "s_axi_awlock": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ], + "s_axi_awcache": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ], + "s_axi_awprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ], + "s_axi_awregion": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ], + "s_axi_awqos": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ], + "s_axi_awvalid": [ { "direction": "in", "driver_value": "0x0" } ], + "s_axi_awready": [ { "direction": "out" } ], + "s_axi_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0x00000000" } ], + "s_axi_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0xF" } ], + "s_axi_wlast": [ { "direction": "in", "driver_value": "0x1" } ], + "s_axi_wvalid": [ { "direction": "in", "driver_value": "0x0" } ], + "s_axi_wready": [ { "direction": "out" } ], + "s_axi_bid": [ { "direction": "out", "size_left": "15", "size_right": "0" } ], + "s_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ], + "s_axi_bvalid": [ { "direction": "out" } ], + "s_axi_bready": [ { "direction": "in", "driver_value": "0x0" } ], + "s_axi_arid": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0x0000" } ], + "s_axi_araddr": [ { "direction": "in", "size_left": "39", "size_right": "0", "driver_value": "0x0000000000" } ], + "s_axi_arlen": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0x00" } ], + "s_axi_arsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ], + "s_axi_arburst": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x1" } ], + "s_axi_arlock": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ], + "s_axi_arcache": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ], + "s_axi_arprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ], + "s_axi_arregion": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ], + "s_axi_arqos": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ], + "s_axi_arvalid": [ { "direction": "in", "driver_value": "0x0" } ], + "s_axi_arready": [ { "direction": "out" } ], + "s_axi_rid": [ { "direction": "out", "size_left": "15", "size_right": "0" } ], + "s_axi_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ], + "s_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ], + "s_axi_rlast": [ { "direction": "out" } ], + "s_axi_rvalid": [ { "direction": "out" } ], + "s_axi_rready": [ { "direction": "in", "driver_value": "0x0" } ], + "m_axi_awaddr": [ { "direction": "out", "size_left": "39", "size_right": "0" } ], + "m_axi_awprot": [ { "direction": "out", "size_left": "2", "size_right": "0" } ], + "m_axi_awvalid": [ { "direction": "out" } ], + "m_axi_awready": [ { "direction": "in", "driver_value": "0x0" } ], + "m_axi_wdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ], + "m_axi_wstrb": [ { "direction": "out", "size_left": "3", "size_right": "0" } ], + "m_axi_wvalid": [ { "direction": "out" } ], + "m_axi_wready": [ { "direction": "in", "driver_value": "0x0" } ], + "m_axi_bresp": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ], + "m_axi_bvalid": [ { "direction": "in", "driver_value": "0x0" } ], + "m_axi_bready": [ { "direction": "out" } ], + "m_axi_araddr": [ { "direction": "out", "size_left": "39", "size_right": "0" } ], + "m_axi_arprot": [ { "direction": "out", "size_left": "2", "size_right": "0" } ], + "m_axi_arvalid": [ { "direction": "out" } ], + "m_axi_arready": [ { "direction": "in", "driver_value": "0x0" } ], + "m_axi_rdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0x00000000" } ], + "m_axi_rresp": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ], + "m_axi_rvalid": [ { "direction": "in", "driver_value": "0x0" } ], + "m_axi_rready": [ { "direction": "out" } ] + }, + "interfaces": { + "S_AXI": { + "vlnv": "xilinx.com:interface:aximm:1.0", + "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "slave", + "parameters": { + "DATA_WIDTH": [ { "value": "32", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "PROTOCOL": [ { "value": "AXI4", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_HZ": [ { "value": "96968727", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "ID_WIDTH": [ { "value": "16", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "ADDR_WIDTH": [ { "value": "40", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "AWUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "ARUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "WUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "RUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "BUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_BURST": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_LOCK": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_PROT": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_CACHE": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_QOS": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_REGION": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, 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"user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "CLK": [ { "physical_name": "s_axi_aclk" } ] + } + }, + "spi_engine_offload_ctrl0_s_axi_signal_reset": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "RST": [ { "physical_name": "s_axi_aresetn" } ] + } + } + }, + "memory_maps": { + "s_axi": { + "address_blocks": { + "axi_lite": { + "base_address": "0", + "range": "65536" + } + } + } + } + } + } +} \ No newline at end of file diff --git a/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ip/system_bd_clk_wiz_0_0/system_bd_clk_wiz_0_0.xci b/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ip/system_bd_clk_wiz_0_0/system_bd_clk_wiz_0_0.xci new file mode 100644 index 0000000..600b0fd --- /dev/null +++ b/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ip/system_bd_clk_wiz_0_0/system_bd_clk_wiz_0_0.xci @@ -0,0 +1,658 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "system_bd_clk_wiz_0_0", + "cell_name": "mts_clk_gen/clk_wiz_pl_clk", + "component_reference": "xilinx.com:ip:clk_wiz:6.0", + "ip_revision": "14", + "gen_directory": "../../../../../../dj_47dr_lmx.gen/sources_1/bd/system_bd/ip/system_bd_clk_wiz_0_0", + "parameters": { + "component_parameters": { + "Component_Name": [ { "value": "system_bd_clk_wiz_0_0", "resolve_type": "user", "usage": "all" } ], + "USER_CLK_FREQ0": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "USER_CLK_FREQ1": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "USER_CLK_FREQ2": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "USER_CLK_FREQ3": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "ENABLE_CLOCK_MONITOR": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "OPTIMIZE_CLOCKING_STRUCTURE_EN": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "ENABLE_USER_CLOCK0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "ENABLE_USER_CLOCK1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "ENABLE_USER_CLOCK2": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "ENABLE_USER_CLOCK3": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Enable_PLL0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Enable_PLL1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "REF_CLK_FREQ": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PRECISION": [ { "value": "1", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PRIMITIVE": [ { "value": "MMCM", "resolve_type": "user", "usage": "all" } ], + "PRIMTYPE_SEL": [ { "value": "mmcm_adv", "resolve_type": "user", "usage": "all" } ], + "CLOCK_MGR_TYPE": [ { "value": "auto", "resolve_type": "user", "usage": "all" } ], + "USE_FREQ_SYNTH": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_SPREAD_SPECTRUM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_PHASE_ALIGNMENT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_MIN_POWER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_DYN_PHASE_SHIFT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_DYN_RECONFIG": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "JITTER_SEL": [ { "value": "No_Jitter", "resolve_type": "user", "usage": "all" } ], + "PRIM_IN_FREQ": [ { "value": "245.76", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PRIM_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "IN_FREQ_UNITS": [ { "value": "Units_MHz", "resolve_type": "user", "usage": "all" } ], + "PHASESHIFT_MODE": [ { "value": "LATENCY", "resolve_type": "user", "usage": "all" } ], + "IN_JITTER_UNITS": [ { "value": "Units_UI", "resolve_type": "user", "usage": "all" } ], + "RELATIVE_INCLK": [ { "value": "REL_PRIMARY", "resolve_type": "user", "usage": "all" } ], + "USE_INCLK_SWITCHOVER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "SECONDARY_IN_FREQ": [ { "value": "100.000", "value_permission": "bd_and_user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "SECONDARY_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "SECONDARY_PORT": [ { "value": "clk_in2", "resolve_type": "user", "usage": "all" } ], + "SECONDARY_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "user", "usage": "all" } ], + "JITTER_OPTIONS": [ { "value": "UI", "resolve_type": "user", "usage": "all" } ], + "CLKIN1_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKIN2_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PRIM_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "SECONDARY_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKIN1_JITTER_PS": [ { "value": "40.69", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT1_USED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT2_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT3_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT4_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT5_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT6_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT7_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "NUM_OUT_CLKS": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "CLK_OUT1_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_OUT2_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_OUT3_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_OUT4_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_OUT5_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_OUT6_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_OUT7_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "PRIMARY_PORT": [ { "value": "clk_in1", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT1_PORT": [ { "value": "clk_out1", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT2_PORT": [ { "value": "clk_out2", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT3_PORT": [ { "value": "clk_out3", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT4_PORT": [ { "value": "clk_out4", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT5_PORT": [ { "value": "clk_out5", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT6_PORT": [ { "value": "clk_out6", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT7_PORT": [ { "value": "clk_out7", "resolve_type": "user", "usage": "all" } ], + "DADDR_PORT": [ { "value": "daddr", "resolve_type": "user", "usage": "all" } ], + "DCLK_PORT": [ { "value": "dclk", "resolve_type": "user", "usage": "all" } ], + "DRDY_PORT": [ { "value": "drdy", "resolve_type": "user", "usage": "all" } ], + "DWE_PORT": [ { "value": "dwe", "resolve_type": "user", "usage": "all" } ], + "DIN_PORT": [ { "value": "din", "resolve_type": "user", "usage": "all" } ], + "DOUT_PORT": [ { "value": "dout", "resolve_type": "user", "usage": "all" } ], + "DEN_PORT": [ { "value": "den", "resolve_type": "user", "usage": "all" } ], + "PSCLK_PORT": [ { "value": "psclk", "resolve_type": "user", "usage": "all" } ], + "PSEN_PORT": [ { "value": "psen", "resolve_type": "user", "usage": "all" } ], + "PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "user", "usage": "all" } ], + "PSDONE_PORT": [ { "value": "psdone", "resolve_type": "user", "usage": "all" } ], + "CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "245.76", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT2_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT3_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT3_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT4_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT4_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT5_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT5_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT5_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT6_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT6_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT7_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT7_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "USE_MAX_I_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_MIN_O_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT1_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT2_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT3_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT4_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "PRIM_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "user", "usage": "all" } ], + "CLKOUT1_DRIVES": [ { "value": "Buffer", "resolve_type": "user", "usage": "all" } ], + "CLKOUT2_DRIVES": [ { "value": "Buffer", "resolve_type": "user", "usage": "all" } ], + "CLKOUT3_DRIVES": [ { "value": "Buffer", "resolve_type": "user", "usage": "all" } ], + "CLKOUT4_DRIVES": [ { "value": "Buffer", "resolve_type": "user", "usage": "all" } ], + "CLKOUT5_DRIVES": [ { "value": "Buffer", "resolve_type": "user", "usage": "all" } ], + "CLKOUT6_DRIVES": [ { "value": "Buffer", "resolve_type": "user", "usage": "all" } ], + "CLKOUT7_DRIVES": [ { "value": "Buffer", "resolve_type": "user", "usage": "all" } ], + "FEEDBACK_SOURCE": [ { "value": "FDBK_AUTO", "resolve_type": "user", "usage": "all" } ], + "CLKFB_IN_SIGNALING": [ { "value": "SINGLE", "resolve_type": "user", "usage": "all" } ], + "CLKFB_IN_PORT": [ { "value": "clkfb_in", "resolve_type": "user", "usage": "all" } ], + "CLKFB_IN_P_PORT": [ { "value": "clkfb_in_p", "resolve_type": "user", "usage": "all" } ], + "CLKFB_IN_N_PORT": [ { "value": "clkfb_in_n", "resolve_type": "user", "usage": "all" } ], + "CLKFB_OUT_PORT": [ { "value": "clkfb_out", "resolve_type": "user", "usage": "all" } ], + "CLKFB_OUT_P_PORT": [ { "value": "clkfb_out_p", "resolve_type": "user", "usage": "all" } ], + "CLKFB_OUT_N_PORT": [ { "value": "clkfb_out_n", "resolve_type": "user", "usage": "all" } ], + "PLATFORM": [ { "value": "UNKNOWN", "resolve_type": "user", "usage": "all" } ], + "SUMMARY_STRINGS": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ], + "USE_LOCKED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CALC_DONE": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ], + "USE_RESET": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_POWER_DOWN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_STATUS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_FREEZE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_CLK_VALID": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_INCLK_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_CLKFB_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "RESET_PORT": [ { "value": "reset", "resolve_type": "user", "usage": "all" } ], + "LOCKED_PORT": [ { "value": "locked", "resolve_type": "user", "usage": "all" } ], + "POWER_DOWN_PORT": [ { "value": "power_down", "resolve_type": "user", "usage": "all" } ], + "CLK_VALID_PORT": [ { "value": "CLK_VALID", "resolve_type": "user", "usage": "all" } ], + "STATUS_PORT": [ { "value": "STATUS", "resolve_type": "user", "usage": "all" } ], + "CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "user", "usage": "all" } ], + "INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "user", "usage": "all" } ], + "CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "user", "usage": "all" } ], + "SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "user", "usage": "all" } ], + "SS_MOD_FREQ": [ { "value": "250", "resolve_type": "user", "format": "float", "usage": "all" } ], + "SS_MOD_TIME": [ { "value": "0.004", "resolve_type": "user", "format": "float", "usage": "all" } ], + "OVERRIDE_MMCM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ], + "MMCM_DIVCLK_DIVIDE": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ], + "MMCM_CLKFBOUT_MULT_F": [ { "value": "4.875", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKIN1_PERIOD": [ { "value": "4.069", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKIN2_PERIOD": [ { "value": "10.0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT4_CASCADE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLOCK_HOLD": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_COMPENSATION": [ { "value": "AUTO", "resolve_type": "user", "usage": "all" } ], + "MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_STARTUP_WAIT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT0_DIVIDE_F": [ { "value": "4.875", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT2_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT3_USE_FINE_PS": [ { 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"value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT6_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT6_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "OVERRIDE_PLL": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "PLL_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ], + "PLL_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ], + "PLL_CLKFBOUT_MULT": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLK_FEEDBACK": [ { "value": "CLKFBOUT", "resolve_type": "user", "usage": "all" } ], + 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"is_static_object": false } ] + }, + "port_maps": { + "RST": [ { "physical_name": "peripheral_aresetn" } ] + } + } + } + } + } +} \ No newline at end of file diff --git a/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ip/system_bd_spi_engine_execution_0_0/system_bd_spi_engine_execution_0_0.xci b/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ip/system_bd_spi_engine_execution_0_0/system_bd_spi_engine_execution_0_0.xci new file mode 100644 index 0000000..ca6107e --- /dev/null +++ b/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ip/system_bd_spi_engine_execution_0_0/system_bd_spi_engine_execution_0_0.xci @@ -0,0 +1,176 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "system_bd_spi_engine_execution_0_0", + "cell_name": "axi_spi_engine/spi_engine_execution", + "component_reference": "analog.com:user:spi_engine_execution:1.0", + "ip_revision": "1", + "gen_directory": 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{ "value": "system_bd_spi_engine_execution_0_0", "resolve_type": "user", "usage": "all" } ] + }, + "model_parameters": { + "NUM_OF_CS": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "DEFAULT_SPI_CFG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "DEFAULT_CLK_DIV": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "DATA_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "NUM_OF_SDI": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "SDO_DEFAULT": [ { "value": "\"0\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], + "ECHO_SCLK": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ], + "SDI_DELAY": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ] + }, + "project_parameters": { + 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"resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M01_A08_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M01_A09_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M01_A10_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M01_A11_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M01_A12_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M01_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M01_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M01_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M02_A00_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M02_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M02_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M02_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M02_A04_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M02_A05_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M02_A06_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M02_A07_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M02_A08_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M02_A09_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M02_A10_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M02_A11_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M02_A12_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M02_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M02_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M02_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M03_A00_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M03_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M03_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M03_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M03_A04_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M03_A05_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M03_A06_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M03_A07_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M03_A08_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M03_A09_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M03_A10_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M03_A11_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M03_A12_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M03_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M03_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M03_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M04_A00_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M04_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M04_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M04_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M04_A04_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M04_A05_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M04_A06_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M04_A07_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M04_A08_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M04_A09_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M04_A10_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M04_A11_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M04_A12_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M04_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M04_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M04_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A00_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A04_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A05_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A06_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A07_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A08_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A09_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A10_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A11_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A12_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A00_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A04_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A05_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A06_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A07_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A08_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A09_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A10_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A11_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A12_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A00_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A04_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A05_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A06_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A07_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A08_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A09_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A10_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A11_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A12_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A00_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A04_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A05_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A06_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A07_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A08_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A09_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A10_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A11_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A12_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A00_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A04_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A05_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A06_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A07_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A08_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A09_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A10_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A11_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A12_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M09_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A00_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A04_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A05_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A06_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A07_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A08_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A09_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A10_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A11_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A12_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M10_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A00_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A04_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A05_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A06_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A07_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A08_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A09_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A10_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A11_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A12_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M11_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A00_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A04_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A05_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A06_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A07_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A08_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A09_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A10_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A11_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A12_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M12_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A00_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A04_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A05_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A06_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A07_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A08_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A09_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A10_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A11_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A12_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M13_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M14_A00_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M14_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M14_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M14_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M14_A04_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M14_A05_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M14_A06_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M14_A07_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M14_A08_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M14_A09_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M14_A10_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M14_A11_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M14_A12_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M14_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M14_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M14_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M15_A00_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M15_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M15_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M15_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M15_A04_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M15_A05_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M15_A06_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M15_A07_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M15_A08_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M15_A09_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M15_A10_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M15_A11_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M15_A12_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M15_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M15_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M15_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M00_A00_ADDR_WIDTH": [ { "value": "16", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M00_A01_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M00_A02_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M00_A03_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M00_A04_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M00_A05_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M00_A06_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M00_A07_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M00_A08_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M00_A09_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M00_A10_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", 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-0,0 +1,4907 @@ +{ + "design": { + "design_info": { + "boundary_crc": "0x7879DD10C9E21201", + "device": "xczu47dr-ffve1156-2-i", + "gen_directory": "../../../../dj_47dr_lmx.gen/sources_1/bd/system_bd", + "name": "system_bd", + "rev_ctrl_bd_flag": "RevCtrlBdOff", + "synth_flow_mode": "Hierarchical", + "tool_version": "2024.1", + "validated": "true" + }, + "design_tree": { + "usp_rf_data_converter": "", + "axi_spi_engine": { + "axi_spi_engine": "", + "spi_engine_execution": "" + }, + "ps8_0_axi_periph": { + "xbar": "", + "s00_couplers": { + "auto_pc": "" + }, + "m00_couplers": {}, + "m01_couplers": {} + }, + "rst_ps8_0_96M": "", + "mts_clk_gen": { + "util_ds_buf_pl_clk": "", + "util_bufg_pl_clk": "", + "util_ds_buf_pl_sysref": "", + "clk_wiz_pl_clk": "", + "xpm_cdc_gen_pl_sysref": "", + "xpm_cdc_gen_mts_sysref": "", + "xlconstant_0": "" + }, + "xlconcat_0": "", + "zynq_ultra_ps_e": "" + }, + "interface_ports": { + "spi": { + "mode": "Master", + "vlnv_bus_definition": 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{ + "value": "0", + "value_src": "const_prop" + } + }, + "port_maps": { + "TDATA": { + "physical_name": "m13_axis_tdata", + "direction": "O", + "left": "15", + "right": "0" + }, + "TREADY": { + "physical_name": "m13_axis_tready", + "direction": "I" + }, + "TVALID": { + "physical_name": "m13_axis_tvalid", + "direction": "O" + } + } + }, + "m20_axis": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:axis:1.0", + "vlnv": "xilinx.com:interface:axis_rtl:1.0", + "parameters": { + "CLK_DOMAIN": { + "value": "system_bd_m2_axis_aclk", + "value_src": "default" + }, + "FREQ_HZ": { + "value": "100000000", + "value_src": "default" + }, + "HAS_TKEEP": { + "value": "0", + "value_src": "const_prop" + }, + "HAS_TLAST": { + "value": "0", + "value_src": "const_prop" + }, + "HAS_TREADY": { + "value": "1", + "value_src": "auto_prop" + }, + "HAS_TSTRB": { + "value": "0", + "value_src": "const_prop" + }, + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "LAYERED_METADATA": { + "value": "undef", + "value_src": "default" + }, + "PHASE": { + "value": "0.0", + "value_src": "default" + }, + "TDATA_NUM_BYTES": { + "value": "2", + "value_src": "auto_prop" + }, + "TDEST_WIDTH": { + "value": "0", + "value_src": "const_prop" + }, + "TID_WIDTH": { + "value": "0", + "value_src": "const_prop" + }, + "TUSER_WIDTH": { + "value": "0", + "value_src": "const_prop" + } + }, + "port_maps": { + "TDATA": { + "physical_name": "m20_axis_tdata", + "direction": "O", + "left": "15", + "right": "0" + }, + "TREADY": { + "physical_name": "m20_axis_tready", + "direction": "I" + }, + "TVALID": { + "physical_name": "m20_axis_tvalid", + "direction": "O" + } + } + }, + "m21_axis": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:axis:1.0", + "vlnv": "xilinx.com:interface:axis_rtl:1.0", + "parameters": { + "CLK_DOMAIN": { + "value": "system_bd_m2_axis_aclk", + "value_src": "default" + }, + "FREQ_HZ": { + "value": "100000000", + "value_src": "default" + }, + "HAS_TKEEP": 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"TUSER_WIDTH": { + "value": "0", + "value_src": "const_prop" + } + }, + "port_maps": { + "TDATA": { + "physical_name": "m22_axis_tdata", + "direction": "O", + "left": "15", + "right": "0" + }, + "TREADY": { + "physical_name": "m22_axis_tready", + "direction": "I" + }, + "TVALID": { + "physical_name": "m22_axis_tvalid", + "direction": "O" + } + } + }, + "m23_axis": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:axis:1.0", + "vlnv": "xilinx.com:interface:axis_rtl:1.0", + "parameters": { + "CLK_DOMAIN": { + "value": "system_bd_m2_axis_aclk", + "value_src": "default" + }, + "FREQ_HZ": { + "value": "100000000", + "value_src": "default" + }, + "HAS_TKEEP": { + "value": "0", + "value_src": "const_prop" + }, + "HAS_TLAST": { + "value": "0", + "value_src": "const_prop" + }, + "HAS_TREADY": { + "value": "1", + "value_src": "auto_prop" + }, + "HAS_TSTRB": { + "value": "0", + "value_src": "const_prop" + }, + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + 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"const_prop" + }, + "TUSER_WIDTH": { + "value": "0", + "value_src": "const_prop" + } + }, + "port_maps": { + "TDATA": { + "physical_name": "m31_axis_tdata", + "direction": "O", + "left": "15", + "right": "0" + }, + "TREADY": { + "physical_name": "m31_axis_tready", + "direction": "I" + }, + "TVALID": { + "physical_name": "m31_axis_tvalid", + "direction": "O" + } + } + }, + "m32_axis": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:axis:1.0", + "vlnv": "xilinx.com:interface:axis_rtl:1.0", + "parameters": { + "CLK_DOMAIN": { + "value": "system_bd_m3_axis_aclk", + "value_src": "default" + }, + "FREQ_HZ": { + "value": "100000000", + "value_src": "default" + }, + "HAS_TKEEP": { + "value": "0", + "value_src": "const_prop" + }, + "HAS_TLAST": { + "value": "0", + "value_src": "const_prop" + }, + "HAS_TREADY": { + "value": "1", + "value_src": "auto_prop" + }, + "HAS_TSTRB": { + "value": "0", + "value_src": "const_prop" + }, + "INSERT_VIP": { + "value": "0", + "value_src": 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"value_src": "default" + }, + "HAS_TKEEP": { + "value": "0", + "value_src": "const_prop" + }, + "HAS_TLAST": { + "value": "0", + "value_src": "const_prop" + }, + "HAS_TREADY": { + "value": "1", + "value_src": "auto_prop" + }, + "HAS_TSTRB": { + "value": "0", + "value_src": "const_prop" + }, + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "LAYERED_METADATA": { + "value": "undef", + "value_src": "default" + }, + "PHASE": { + "value": "0.0", + "value_src": "default" + }, + "TDATA_NUM_BYTES": { + "value": "2", + "value_src": "auto_prop" + }, + "TDEST_WIDTH": { + "value": "0", + "value_src": "const_prop" + }, + "TID_WIDTH": { + "value": "0", + "value_src": "const_prop" + }, + "TUSER_WIDTH": { + "value": "0", + "value_src": "const_prop" + } + }, + "port_maps": { + "TDATA": { + "physical_name": "m33_axis_tdata", + "direction": "O", + "left": "15", + "right": "0" + }, + "TREADY": { + "physical_name": "m33_axis_tready", + "direction": "I" + }, + "TVALID": { + "physical_name": "m33_axis_tvalid", + "direction": "O" + } + } + }, + "s00_axis": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:axis:1.0", + "vlnv": "xilinx.com:interface:axis_rtl:1.0", + "parameters": { + "CLK_DOMAIN": { + "value": "system_bd_s0_axis_aclk", + "value_src": "default" + }, + "FREQ_HZ": { + "value": "100000000", + "value_src": "default" + }, + "HAS_TKEEP": { + "value": "0" + }, + "HAS_TLAST": { + "value": "0" + }, + "HAS_TREADY": { + "value": "1" + }, + "HAS_TSTRB": { + "value": "0" + }, + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "LAYERED_METADATA": { + "value": "undef" + }, + "PHASE": { + "value": "0.0", + "value_src": "default" + }, + "TDATA_NUM_BYTES": { + "value": "4" + }, + "TDEST_WIDTH": { + "value": "0" + }, + "TID_WIDTH": { + "value": "0" + }, + "TUSER_WIDTH": { + "value": "0" + } + }, + "port_maps": { + "TDATA": { + "physical_name": "s00_axis_tdata", + "direction": "I", + "left": "31", + "right": "0" + }, + "TREADY": { + "physical_name": "s00_axis_tready", + "direction": "O" + }, + "TVALID": { + "physical_name": "s00_axis_tvalid", + "direction": "I" + } + } + }, + "s02_axis": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:axis:1.0", + "vlnv": "xilinx.com:interface:axis_rtl:1.0", + "parameters": { + "CLK_DOMAIN": { + "value": "system_bd_s0_axis_aclk", + "value_src": "default" + }, + "FREQ_HZ": { + "value": "100000000", + "value_src": "default" + }, + "HAS_TKEEP": { + "value": "0" + }, + "HAS_TLAST": { + "value": "0" + }, + "HAS_TREADY": { + "value": "1" + }, + "HAS_TSTRB": { + "value": "0" + }, + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "LAYERED_METADATA": { + "value": "undef" + }, + "PHASE": { + "value": "0.0", + "value_src": "default" + }, + "TDATA_NUM_BYTES": { + "value": "4" + }, + "TDEST_WIDTH": { + "value": "0" + }, + "TID_WIDTH": { + "value": "0" + }, + "TUSER_WIDTH": { + "value": "0" + } + }, + "port_maps": { + "TDATA": { + "physical_name": "s02_axis_tdata", + "direction": "I", + "left": "31", + "right": "0" + }, + "TREADY": { + "physical_name": "s02_axis_tready", + "direction": "O" + }, + "TVALID": { + "physical_name": "s02_axis_tvalid", + "direction": "I" + } + } + }, + "s10_axis": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:axis:1.0", + "vlnv": "xilinx.com:interface:axis_rtl:1.0", + "parameters": { + "CLK_DOMAIN": { + "value": "system_bd_s1_axis_aclk", + "value_src": "default" + }, + "FREQ_HZ": { + "value": "100000000", + "value_src": "default" + }, + "HAS_TKEEP": { + "value": "0" + }, + "HAS_TLAST": { + "value": "0" + }, + "HAS_TREADY": { + "value": "1" + }, + "HAS_TSTRB": { + "value": "0" + }, + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "LAYERED_METADATA": { + "value": "undef" + }, + "PHASE": { + "value": "0.0", + "value_src": "default" + }, + "TDATA_NUM_BYTES": { + "value": "4" + }, + "TDEST_WIDTH": { + "value": "0" + }, + "TID_WIDTH": { + "value": "0" + }, + "TUSER_WIDTH": { + "value": "0" + } + }, + "port_maps": { + "TDATA": { + "physical_name": "s10_axis_tdata", + "direction": "I", + "left": "31", + "right": "0" + }, + "TREADY": { + "physical_name": "s10_axis_tready", + "direction": "O" + }, + "TVALID": { + "physical_name": "s10_axis_tvalid", + "direction": "I" + } + } + }, + "s12_axis": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:axis:1.0", + "vlnv": "xilinx.com:interface:axis_rtl:1.0", + "parameters": { + "CLK_DOMAIN": { + "value": "system_bd_s1_axis_aclk", + "value_src": "default" + }, + "FREQ_HZ": { + "value": "100000000", + "value_src": "default" + }, + "HAS_TKEEP": { + "value": "0" + }, + "HAS_TLAST": { + "value": "0" + }, + "HAS_TREADY": { + "value": "1" + }, + "HAS_TSTRB": { + "value": "0" + }, + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "LAYERED_METADATA": { + "value": "undef" + }, + "PHASE": { + "value": "0.0", + "value_src": "default" + }, + "TDATA_NUM_BYTES": { + "value": "4" + }, + "TDEST_WIDTH": { + "value": "0" + }, + "TID_WIDTH": { + "value": "0" + }, + "TUSER_WIDTH": { + "value": "0" + } + }, + "port_maps": { + "TDATA": { + "physical_name": "s12_axis_tdata", + "direction": "I", + "left": "31", + "right": "0" + }, + "TREADY": { + "physical_name": "s12_axis_tready", + "direction": "O" + }, + "TVALID": { + "physical_name": "s12_axis_tvalid", + "direction": "I" + } + } + }, + "s20_axis": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:axis:1.0", + "vlnv": "xilinx.com:interface:axis_rtl:1.0", + "parameters": { + "CLK_DOMAIN": { + "value": "system_bd_s2_axis_aclk", + "value_src": "default" + }, + "FREQ_HZ": { + "value": "100000000", + "value_src": "default" + }, + "HAS_TKEEP": { + "value": "0" + }, + "HAS_TLAST": { + "value": "0" + }, + "HAS_TREADY": { + "value": "1" + }, + "HAS_TSTRB": { + "value": "0" + }, + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "LAYERED_METADATA": { + "value": "undef" + }, + "PHASE": { + "value": "0.0", + "value_src": "default" + }, + "TDATA_NUM_BYTES": { + "value": "4" + }, + "TDEST_WIDTH": { + "value": "0" + }, + "TID_WIDTH": { + "value": "0" + }, + "TUSER_WIDTH": { + "value": "0" + } + }, + "port_maps": { + "TDATA": { + "physical_name": "s20_axis_tdata", + "direction": "I", + "left": "31", + "right": "0" + }, + "TREADY": { + "physical_name": "s20_axis_tready", + "direction": "O" + }, + "TVALID": { + "physical_name": "s20_axis_tvalid", + "direction": "I" + } + } + }, + "s22_axis": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:axis:1.0", + "vlnv": "xilinx.com:interface:axis_rtl:1.0", + "parameters": { + "CLK_DOMAIN": { + "value": "system_bd_s2_axis_aclk", + "value_src": "default" + }, + "FREQ_HZ": { + "value": "100000000", + "value_src": "default" + }, + "HAS_TKEEP": { + "value": "0" + }, + "HAS_TLAST": { + "value": "0" + }, + "HAS_TREADY": { + "value": "1" + }, + "HAS_TSTRB": { + "value": "0" + }, + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "LAYERED_METADATA": { + "value": "undef" + }, + "PHASE": { + "value": "0.0", + "value_src": "default" + }, + "TDATA_NUM_BYTES": { + "value": "4" + }, + "TDEST_WIDTH": { + "value": "0" + }, + "TID_WIDTH": { + "value": "0" + }, + "TUSER_WIDTH": { + "value": "0" + } + }, + "port_maps": { + "TDATA": { + "physical_name": "s22_axis_tdata", + "direction": "I", + "left": "31", + "right": "0" + }, + "TREADY": { + "physical_name": "s22_axis_tready", + "direction": "O" + }, + "TVALID": { + "physical_name": "s22_axis_tvalid", + "direction": "I" + } + } + }, + "s30_axis": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:axis:1.0", + "vlnv": "xilinx.com:interface:axis_rtl:1.0", + "parameters": { + "CLK_DOMAIN": { + "value": "system_bd_s3_axis_aclk", + "value_src": "default" + }, + "FREQ_HZ": { + "value": "100000000", + "value_src": "default" + }, + "HAS_TKEEP": { + "value": "0" + }, + "HAS_TLAST": { + "value": "0" + }, + "HAS_TREADY": { + "value": "1" + }, + "HAS_TSTRB": { + "value": "0" + }, + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "LAYERED_METADATA": { + "value": "undef" + }, + "PHASE": { + "value": "0.0", + "value_src": "default" + }, + "TDATA_NUM_BYTES": { + "value": "4" + }, + "TDEST_WIDTH": { + "value": "0" + }, + "TID_WIDTH": { + "value": "0" + }, + "TUSER_WIDTH": { + "value": "0" + } + }, + "port_maps": { + "TDATA": { + "physical_name": "s30_axis_tdata", + "direction": "I", + "left": "31", + "right": "0" + }, + "TREADY": { + "physical_name": "s30_axis_tready", + "direction": "O" + }, + "TVALID": { + "physical_name": "s30_axis_tvalid", + "direction": "I" + } + } + }, + "s32_axis": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:axis:1.0", + "vlnv": "xilinx.com:interface:axis_rtl:1.0", + "parameters": { + "CLK_DOMAIN": { + "value": "system_bd_s3_axis_aclk", + "value_src": "default" + }, + "FREQ_HZ": { + "value": "100000000", + "value_src": "default" + }, + "HAS_TKEEP": { + "value": "0" + }, + "HAS_TLAST": { + "value": "0" + }, + "HAS_TREADY": { + "value": "1" + }, + "HAS_TSTRB": { + "value": "0" + }, + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "LAYERED_METADATA": { + "value": "undef" + }, + "PHASE": { + "value": "0.0", + "value_src": "default" + }, + "TDATA_NUM_BYTES": { + "value": "4" + }, + "TDEST_WIDTH": { + "value": "0" + }, + "TID_WIDTH": { + "value": "0" + }, + "TUSER_WIDTH": { + "value": "0" + } + }, + "port_maps": { + "TDATA": { + "physical_name": "s32_axis_tdata", + "direction": "I", + "left": "31", + "right": "0" + }, + "TREADY": { + "physical_name": "s32_axis_tready", + "direction": "O" + }, + "TVALID": { + "physical_name": "s32_axis_tvalid", + "direction": "I" + } + } + }, + "sysref_in": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:display_usp_rf_data_converter:diff_pins:1.0", + "vlnv": "xilinx.com:display_usp_rf_data_converter:diff_pins_rtl:1.0", + "port_maps": { + "diff_n": { + "physical_name": "sysref_in_diff_n", + "direction": "I" + }, + "diff_p": { + "physical_name": "sysref_in_diff_p", + "direction": "I" + } + } + }, + "vin0_01": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:diff_analog_io:1.0", + "vlnv": "xilinx.com:interface:diff_analog_io_rtl:1.0", + "port_maps": { + "V_N": { + "physical_name": "vin0_01_v_n", + "direction": "I" + }, + "V_P": { + "physical_name": "vin0_01_v_p", + "direction": "I" + } + } + }, + "vin0_23": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:diff_analog_io:1.0", + "vlnv": "xilinx.com:interface:diff_analog_io_rtl:1.0", + "port_maps": { + "V_N": { + "physical_name": "vin0_23_v_n", + "direction": "I" + }, + "V_P": { + "physical_name": "vin0_23_v_p", + "direction": "I" + } + } + }, + "vin1_01": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:diff_analog_io:1.0", + "vlnv": "xilinx.com:interface:diff_analog_io_rtl:1.0", + "port_maps": { + "V_N": { + "physical_name": "vin1_01_v_n", + "direction": "I" + }, + "V_P": { + "physical_name": "vin1_01_v_p", + "direction": "I" + } + } + }, + "vin1_23": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:diff_analog_io:1.0", + "vlnv": "xilinx.com:interface:diff_analog_io_rtl:1.0", + "port_maps": { + "V_N": { + "physical_name": "vin1_23_v_n", + "direction": "I" + }, + "V_P": { + "physical_name": "vin1_23_v_p", + "direction": "I" + } + } + }, + "vin2_01": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:diff_analog_io:1.0", + "vlnv": "xilinx.com:interface:diff_analog_io_rtl:1.0", + "port_maps": { + "V_N": { + "physical_name": "vin2_01_v_n", + "direction": "I" + }, + "V_P": { + "physical_name": "vin2_01_v_p", + "direction": "I" + } + } + }, + "vin2_23": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:diff_analog_io:1.0", + "vlnv": "xilinx.com:interface:diff_analog_io_rtl:1.0", + "port_maps": { + "V_N": { + "physical_name": "vin2_23_v_n", + "direction": "I" + }, + "V_P": { + "physical_name": "vin2_23_v_p", + "direction": "I" + } + } + }, + "vin3_01": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:diff_analog_io:1.0", + "vlnv": "xilinx.com:interface:diff_analog_io_rtl:1.0", + "port_maps": { + "V_N": { + "physical_name": "vin3_01_v_n", + "direction": "I" + }, + "V_P": { + "physical_name": "vin3_01_v_p", + "direction": "I" + } + } + }, + "vin3_23": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:diff_analog_io:1.0", + "vlnv": "xilinx.com:interface:diff_analog_io_rtl:1.0", + "port_maps": { + "V_N": { + "physical_name": "vin3_23_v_n", + "direction": "I" + }, + "V_P": { + "physical_name": "vin3_23_v_p", + "direction": "I" + } + } + }, + "vout00": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:diff_analog_io:1.0", + "vlnv": "xilinx.com:interface:diff_analog_io_rtl:1.0", + "port_maps": { + "V_N": { + "physical_name": "vout00_v_n", + "direction": "O" + }, + "V_P": { + "physical_name": "vout00_v_p", + "direction": "O" + } + } + }, + "vout02": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:diff_analog_io:1.0", + "vlnv": "xilinx.com:interface:diff_analog_io_rtl:1.0", + "port_maps": { + "V_N": { + "physical_name": "vout02_v_n", + "direction": "O" + }, + "V_P": { + "physical_name": "vout02_v_p", + "direction": "O" + } + } + }, + "vout10": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:diff_analog_io:1.0", + "vlnv": "xilinx.com:interface:diff_analog_io_rtl:1.0", + "port_maps": { + "V_N": { + "physical_name": "vout10_v_n", + "direction": "O" + }, + "V_P": { + "physical_name": "vout10_v_p", + "direction": "O" + } + } + }, + "vout12": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:diff_analog_io:1.0", + "vlnv": "xilinx.com:interface:diff_analog_io_rtl:1.0", + "port_maps": { + "V_N": { + "physical_name": "vout12_v_n", + "direction": "O" + }, + "V_P": { + "physical_name": "vout12_v_p", + "direction": "O" + } + } + }, + "vout20": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:diff_analog_io:1.0", + "vlnv": "xilinx.com:interface:diff_analog_io_rtl:1.0", + "port_maps": { + "V_N": { + "physical_name": "vout20_v_n", + "direction": "O" + }, + "V_P": { + "physical_name": "vout20_v_p", + "direction": "O" + } + } + }, + "vout22": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:diff_analog_io:1.0", + "vlnv": "xilinx.com:interface:diff_analog_io_rtl:1.0", + "port_maps": { + "V_N": { + "physical_name": "vout22_v_n", + "direction": "O" + }, + "V_P": { + "physical_name": "vout22_v_p", + "direction": "O" + } + } + }, + "vout30": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:diff_analog_io:1.0", + "vlnv": "xilinx.com:interface:diff_analog_io_rtl:1.0", + "port_maps": { + "V_N": { + "physical_name": "vout30_v_n", + "direction": "O" + }, + "V_P": { + "physical_name": "vout30_v_p", + "direction": "O" + } + } + }, + "vout32": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:diff_analog_io:1.0", + "vlnv": "xilinx.com:interface:diff_analog_io_rtl:1.0", + "port_maps": { + "V_N": { + "physical_name": "vout32_v_n", + "direction": "O" + }, + "V_P": { + "physical_name": "vout32_v_p", + "direction": "O" + } + } + } + }, + "ports": { + "spi_active": { + "direction": "O" + }, + "sys_rstn": { + "type": "clk", + "direction": "O", + "parameters": { + "FREQ_HZ": { + "value": "100000000", + "value_src": "default" + }, + "FREQ_TOLERANCE_HZ": { + "value": "0", + "value_src": "default" + }, + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "PHASE": { + "value": "0.0", + "value_src": "default" + } + } + }, + "sys_clk": { + "direction": "O", + "parameters": { + "CLK_DOMAIN": { + "value": "system_bd_clk_wiz_0_0_clk_out1", + "value_src": "default_prop" + }, + "FREQ_HZ": { + "value": "245760000", + "value_src": "ip_prop" + }, + "PHASE": { + "value": "0.0", + "value_src": "ip_prop" + } + } + }, + "ps_clk0": { + "type": "clk", + "direction": "O", + "parameters": { + "CLK_DOMAIN": { + "value": "system_bd_zynq_ultra_ps_e_0_1_pl_clk0", + "value_src": "default_prop" + }, + "FREQ_HZ": { + "value": "96968727", + "value_src": "user_prop" + }, + "FREQ_TOLERANCE_HZ": { + "value": "0", + "value_src": "default" + }, + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "PHASE": { + "value": "0.0", + "value_src": "default" + } + } + }, + "clk_adc0": { + "type": "clk", + "direction": "O", + "parameters": { + "CLK_DOMAIN": { + "value": "system_bd_usp_rf_data_converter_0_0_clk_adc0", + "value_src": "default_prop" + }, + "FREQ_HZ": { + "value": "38400000", + "value_src": "user_prop" + }, + "FREQ_TOLERANCE_HZ": { + "value": "0", + "value_src": "default" + }, + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "PHASE": { + "value": "0.0", + "value_src": "default" + } + } + }, + "clk_adc1": { + "type": "clk", + "direction": "O", + "parameters": { + "CLK_DOMAIN": { + "value": "system_bd_usp_rf_data_converter_0_0_clk_adc1", + "value_src": "default_prop" + }, + "FREQ_HZ": { + "value": "38400000", + "value_src": "user_prop" + }, + "FREQ_TOLERANCE_HZ": { + "value": "0", + "value_src": "default" + }, + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "PHASE": { + "value": "0.0", + "value_src": "default" + } + } + }, + "clk_adc2": { + "type": "clk", + "direction": "O", + "parameters": { + "CLK_DOMAIN": { + "value": "system_bd_usp_rf_data_converter_0_0_clk_adc2", + "value_src": "default_prop" + }, + "FREQ_HZ": { + "value": "38400000", + "value_src": "user_prop" + }, + "FREQ_TOLERANCE_HZ": { + "value": "0", + "value_src": "default" + }, + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "PHASE": { + "value": "0.0", + "value_src": "default" + } + } + }, + "clk_adc3": { + "type": "clk", + "direction": "O", + "parameters": { + "CLK_DOMAIN": { + "value": "system_bd_usp_rf_data_converter_0_0_clk_adc3", + "value_src": "default_prop" + }, + "FREQ_HZ": { + "value": "38400000", + "value_src": "user_prop" + }, + "FREQ_TOLERANCE_HZ": { + "value": "0", + "value_src": "default" + }, + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "PHASE": { + "value": "0.0", + "value_src": "default" + } + } + }, + "clk_dac0": { + "type": "clk", + "direction": "O", + "parameters": { + "CLK_DOMAIN": { + "value": "system_bd_usp_rf_data_converter_0_0_clk_dac0", + "value_src": "default_prop" + }, + "FREQ_HZ": { + "value": "38400000", + "value_src": "user_prop" + }, + "FREQ_TOLERANCE_HZ": { + "value": "0", + "value_src": "default" + }, + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "PHASE": { + "value": "0.0", + "value_src": "default" + } + } + }, + "clk_dac1": { + "type": "clk", + "direction": "O", + "parameters": { + "CLK_DOMAIN": { + "value": "system_bd_usp_rf_data_converter_0_0_clk_dac1", + "value_src": "default_prop" + }, + "FREQ_HZ": { + "value": "38400000", + "value_src": "user_prop" + }, + "FREQ_TOLERANCE_HZ": { + "value": "0", + "value_src": "default" + }, + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "PHASE": { + "value": "0.0", + "value_src": "default" + } + } + }, + "clk_dac2": { + "type": "clk", + "direction": "O", + "parameters": { + "CLK_DOMAIN": { + "value": "system_bd_usp_rf_data_converter_0_0_clk_dac2", + "value_src": "default_prop" + }, + "FREQ_HZ": { + "value": "38400000", + "value_src": "user_prop" + }, + "FREQ_TOLERANCE_HZ": { + "value": "0", + "value_src": "default" + }, + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "PHASE": { + "value": "0.0", + "value_src": "default" + } + } + }, + "clk_dac3": { + "type": "clk", + "direction": "O", + "parameters": { + "CLK_DOMAIN": { + "value": "system_bd_usp_rf_data_converter_0_0_clk_dac3", + "value_src": "default_prop" + }, + "FREQ_HZ": { + "value": "38400000", + "value_src": "user_prop" + }, + "FREQ_TOLERANCE_HZ": { + "value": "0", + "value_src": "default" + }, + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "PHASE": { + "value": "0.0", + "value_src": "default" + } + } + }, + "m0_axis_aclk": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "m00_axis:m01_axis:m02_axis:m03_axis", + "value_src": "default" + }, + "ASSOCIATED_RESET": { + "value": "m0_axis_aresetn" + }, + "CLK_DOMAIN": { + "value": "system_bd_m0_axis_aclk", + "value_src": "default" + }, + "FREQ_HZ": { + "value": "100000000", + "value_src": "default" + }, + "FREQ_TOLERANCE_HZ": { + "value": "0", + "value_src": "default" + }, + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "PHASE": { + "value": "0.0", + "value_src": "default" + } + } + }, + "m0_axis_aresetn": { + "type": "rst", + "direction": "I", + "parameters": { + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "POLARITY": { + "value": "ACTIVE_LOW", + "value_src": "default" + } + } + }, + "m1_axis_aclk": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "m10_axis:m11_axis:m12_axis:m13_axis", + "value_src": "default" + }, + "ASSOCIATED_RESET": { + "value": "m1_axis_aresetn" + }, + "CLK_DOMAIN": { + "value": "system_bd_m1_axis_aclk", + "value_src": "default" + }, + "FREQ_HZ": { + "value": "100000000", + "value_src": "default" + }, + "FREQ_TOLERANCE_HZ": { + "value": "0", + "value_src": "default" + }, + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "PHASE": { + "value": "0.0", + "value_src": "default" + } + } + }, + "m1_axis_aresetn": { + "type": "rst", + "direction": "I", + "parameters": { + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "POLARITY": { + "value": "ACTIVE_LOW", + "value_src": "default" + } + } + }, + "m2_axis_aclk": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "m20_axis:m21_axis:m22_axis:m23_axis", + "value_src": "default" + }, + "ASSOCIATED_RESET": { + "value": "m2_axis_aresetn" + }, + "CLK_DOMAIN": { + "value": "system_bd_m2_axis_aclk", + "value_src": "default" + }, + "FREQ_HZ": { + "value": "100000000", + "value_src": "default" + }, + "FREQ_TOLERANCE_HZ": { + "value": "0", + "value_src": "default" + }, + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "PHASE": { + "value": "0.0", + "value_src": "default" + } + } + }, + "m2_axis_aresetn": { + "type": "rst", + "direction": "I", + "parameters": { + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "POLARITY": { + "value": "ACTIVE_LOW", + "value_src": "default" + } + } + }, + "m3_axis_aclk": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "m30_axis:m31_axis:m32_axis:m33_axis", + "value_src": "default" + }, + "ASSOCIATED_RESET": { + "value": "m3_axis_aresetn" + }, + "CLK_DOMAIN": { + "value": "system_bd_m3_axis_aclk", + "value_src": "default" + }, + "FREQ_HZ": { + "value": "100000000", + "value_src": "default" + }, + "FREQ_TOLERANCE_HZ": { + "value": "0", + "value_src": "default" + }, + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "PHASE": { + "value": "0.0", + "value_src": "default" + } + } + }, + "m3_axis_aresetn": { + "type": "rst", + "direction": "I", + "parameters": { + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "POLARITY": { + "value": "ACTIVE_LOW", + "value_src": "default" + } + } + }, + "s0_axis_aclk": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "s00_axis:s02_axis", + "value_src": "default" + }, + "ASSOCIATED_RESET": { + "value": "s0_axis_aresetn" + }, + "CLK_DOMAIN": { + "value": "system_bd_s0_axis_aclk", + "value_src": "default" + }, + "FREQ_HZ": { + "value": "100000000", + "value_src": "default" + }, + "FREQ_TOLERANCE_HZ": { + "value": "0", + "value_src": "default" + }, + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "PHASE": { + "value": "0.0", + "value_src": "default" + } + } + }, + "s0_axis_aresetn": { + "type": "rst", + "direction": "I", + "parameters": { + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "POLARITY": { + "value": "ACTIVE_LOW", + "value_src": "default" + } + } + }, + "s1_axis_aclk": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "s10_axis:s12_axis", + "value_src": "default" + }, + "ASSOCIATED_RESET": { + "value": "s1_axis_aresetn" + }, + "CLK_DOMAIN": { + "value": "system_bd_s1_axis_aclk", + "value_src": "default" + }, + "FREQ_HZ": { + "value": "100000000", + "value_src": "default" + }, + "FREQ_TOLERANCE_HZ": { + "value": "0", + "value_src": "default" + }, + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "PHASE": { + "value": "0.0", + "value_src": "default" + } + } + }, + "s1_axis_aresetn": { + "type": "rst", + "direction": "I", + "parameters": { + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "POLARITY": { + "value": "ACTIVE_LOW", + "value_src": "default" + } + } + }, + "s2_axis_aclk": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "s20_axis:s22_axis", + "value_src": "default" + }, + "ASSOCIATED_RESET": { + "value": "s2_axis_aresetn" + }, + "CLK_DOMAIN": { + "value": "system_bd_s2_axis_aclk", + "value_src": "default" + }, + "FREQ_HZ": { + "value": "100000000", + "value_src": "default" + }, + "FREQ_TOLERANCE_HZ": { + "value": "0", + "value_src": "default" + }, + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "PHASE": { + "value": "0.0", + "value_src": "default" + } + } + }, + "s2_axis_aresetn": { + "type": "rst", + "direction": "I", + "parameters": { + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "POLARITY": { + "value": "ACTIVE_LOW", + "value_src": "default" + } + } + }, + "s3_axis_aclk": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "s30_axis:s32_axis", + "value_src": "default" + }, + "ASSOCIATED_RESET": { + "value": "s3_axis_aresetn" + }, + "CLK_DOMAIN": { + "value": "system_bd_s3_axis_aclk", + "value_src": "default" + }, + "FREQ_HZ": { + "value": "100000000", + "value_src": "default" + }, + "FREQ_TOLERANCE_HZ": { + "value": "0", + "value_src": "default" + }, + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "PHASE": { + "value": "0.0", + "value_src": "default" + } + } + }, + "s3_axis_aresetn": { + "type": "rst", + "direction": "I", + "parameters": { + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "POLARITY": { + "value": "ACTIVE_LOW", + "value_src": "default" + } + } + } + }, + "components": { + "usp_rf_data_converter": { + "vlnv": "xilinx.com:ip:usp_rf_data_converter:2.6", + "ip_revision": "9", + "xci_name": "system_bd_usp_rf_data_converter_0_0", + "xci_path": "ip/system_bd_usp_rf_data_converter_0_0/system_bd_usp_rf_data_converter_0_0.xci", + "inst_hier_path": "usp_rf_data_converter", + "parameters": { + "ADC0_Clock_Source": { + "value": "2" + }, + "ADC0_Multi_Tile_Sync": { + "value": "true" + }, + "ADC0_PLL_Enable": { + "value": "false" + }, + "ADC0_Refclk_Freq": { + "value": "4915.200" + }, + "ADC0_Sampling_Rate": { + "value": "4.9152" + }, + "ADC1_Clock_Dist": { + "value": "0" + }, + "ADC1_Clock_Source": { + "value": "2" + }, + "ADC1_Multi_Tile_Sync": { + "value": "true" + }, + "ADC1_PLL_Enable": { + "value": "false" + }, + "ADC1_Refclk_Freq": { + "value": "4915.200" + }, + "ADC2_Clock_Dist": { + "value": "1" + }, + "ADC2_Clock_Source": { + "value": "2" + }, + "ADC2_Multi_Tile_Sync": { + "value": "true" + }, + "ADC2_PLL_Enable": { + "value": "false" + }, + "ADC2_Refclk_Freq": { + "value": "4915.200" + }, + "ADC3_Clock_Source": { + "value": "2" + }, + "ADC3_Multi_Tile_Sync": { + "value": "true" + }, + "ADC3_PLL_Enable": { + "value": "false" + }, + "ADC3_Refclk_Freq": { + "value": "4915.200" + }, + "ADC_Data_Type00": { + "value": "1" + }, + "ADC_Data_Type02": { + "value": "1" + }, + "ADC_Data_Type12": { + "value": "1" + }, + "ADC_Data_Type22": { + "value": "1" + }, + "ADC_Data_Type32": { + "value": "1" + }, + "ADC_Data_Width00": { + "value": "1" + }, + "ADC_Data_Width02": { + "value": "1" + }, + "ADC_Data_Width10": { + "value": "1" + }, + "ADC_Data_Width12": { + "value": "1" + }, + "ADC_Data_Width20": { + "value": "1" + }, + "ADC_Data_Width22": { + "value": "1" + }, + "ADC_Data_Width30": { + "value": "1" + }, + "ADC_Data_Width32": { + "value": "1" + }, + "ADC_Decimation_Mode00": { + "value": "20" + }, + "ADC_Decimation_Mode02": { + "value": "20" + }, + "ADC_Decimation_Mode10": { + "value": "20" + }, + "ADC_Decimation_Mode12": { + "value": "20" + }, + "ADC_Decimation_Mode20": { + "value": "20" + }, + "ADC_Decimation_Mode22": { + "value": "20" + }, + "ADC_Decimation_Mode30": { + "value": "20" + }, + "ADC_Decimation_Mode32": { + "value": "20" + }, + "ADC_Mixer_Type00": { + "value": "2" + }, + "ADC_Mixer_Type02": { + "value": "2" + }, + "ADC_Mixer_Type10": { + "value": "2" + }, + "ADC_Mixer_Type12": { + "value": "2" + }, + "ADC_Mixer_Type20": { + "value": "2" + }, + "ADC_Mixer_Type22": { + "value": "2" + }, + "ADC_Mixer_Type30": { + "value": "2" + }, + "ADC_Mixer_Type32": { + "value": "2" + }, + "ADC_Slice02_Enable": { + "value": "true" + }, + "ADC_Slice10_Enable": { + "value": "true" + }, + "ADC_Slice12_Enable": { + "value": "true" + }, + "ADC_Slice20_Enable": { + "value": "true" + }, + "ADC_Slice22_Enable": { + "value": "true" + }, + "ADC_Slice30_Enable": { + "value": "true" + }, + "ADC_Slice32_Enable": { + "value": "true" + }, + "DAC0_Clock_Dist": { + "value": "0" + }, + "DAC0_Clock_Source": { + "value": "6" + }, + "DAC0_Multi_Tile_Sync": { + "value": "true" + }, + "DAC0_PLL_Enable": { + "value": "false" + }, + "DAC0_Refclk_Freq": { + "value": "4915.200" + }, + "DAC1_Multi_Tile_Sync": { + "value": "true" + }, + "DAC1_PLL_Enable": { + "value": "false" + }, + "DAC1_Refclk_Freq": { + "value": "4915.200" + }, + "DAC2_Clock_Dist": { + "value": "1" + }, + "DAC2_Clock_Source": { + "value": "6" + }, + "DAC2_Multi_Tile_Sync": { + "value": "true" + }, + "DAC2_PLL_Enable": { + "value": "false" + }, + "DAC2_Refclk_Freq": { + "value": "4915.200" + }, + "DAC3_Multi_Tile_Sync": { + "value": "true" + }, + "DAC3_PLL_Enable": { + "value": "false" + }, + "DAC3_Refclk_Freq": { + "value": "4915.200" + }, + "DAC_Data_Width00": { + "value": "2" + }, + "DAC_Data_Width02": { + "value": "2" + }, + "DAC_Data_Width10": { + "value": "2" + }, + "DAC_Data_Width12": { + "value": "2" + }, + "DAC_Data_Width20": { + "value": "2" + }, + "DAC_Data_Width22": { + "value": "2" + }, + "DAC_Data_Width30": { + "value": "2" + }, + "DAC_Data_Width32": { + "value": "2" + }, + "DAC_Interpolation_Mode00": { + "value": "20" + }, + "DAC_Interpolation_Mode02": { + "value": "20" + }, + "DAC_Interpolation_Mode10": { + "value": "20" + }, + "DAC_Interpolation_Mode12": { + "value": "20" + }, + "DAC_Interpolation_Mode20": { + "value": "20" + }, + "DAC_Interpolation_Mode22": { + "value": "20" + }, + "DAC_Interpolation_Mode30": { + "value": "20" + }, + "DAC_Interpolation_Mode32": { + "value": "20" + }, + "DAC_Mixer_Type00": { + "value": "2" + }, + "DAC_Mixer_Type02": { + "value": "2" + }, + "DAC_Mixer_Type10": { + "value": "2" + }, + "DAC_Mixer_Type12": { + "value": "2" + }, + "DAC_Mixer_Type20": { + "value": "2" + }, + "DAC_Mixer_Type22": { + "value": "2" + }, + "DAC_Mixer_Type30": { + "value": "2" + }, + "DAC_Mixer_Type32": { + "value": "2" + }, + "DAC_Slice00_Enable": { + "value": "true" + }, + "DAC_Slice02_Enable": { + "value": "true" + }, + "DAC_Slice10_Enable": { + "value": "true" + }, + "DAC_Slice12_Enable": { + "value": "true" + }, + "DAC_Slice20_Enable": { + "value": "true" + }, + "DAC_Slice22_Enable": { + "value": "true" + }, + "DAC_Slice30_Enable": { + "value": "true" + }, + "DAC_Slice32_Enable": { + "value": "true" + } + } + }, + "axi_spi_engine": { + "interface_ports": { + "s_axi": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "spi": { + "mode": "Master", + "vlnv_bus_definition": "analog.com:interface:spi_engine:1.0", + "vlnv": "analog.com:interface:spi_engine_rtl:1.0" + } + }, + "ports": { + "s_axi_aclk": { + "type": "clk", + "direction": "I" + }, + "s_axi_aresetn": { + "type": "rst", + "direction": "I" + }, + "active": { + "direction": "O" + }, + "irq": { + "direction": "O" + } + }, + "components": { + "axi_spi_engine": { + "vlnv": "analog.com:user:axi_spi_engine:1.0", + "ip_revision": "1", + "xci_name": "system_bd_axi_spi_engine_0_0", + "xci_path": "ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0.xci", + "inst_hier_path": "axi_spi_engine/axi_spi_engine", + "parameters": { + "NUM_OF_SDI": { + "value": "1" + } + } + }, + "spi_engine_execution": { + "vlnv": "analog.com:user:spi_engine_execution:1.0", + "ip_revision": "1", + "xci_name": "system_bd_spi_engine_execution_0_0", + "xci_path": "ip/system_bd_spi_engine_execution_0_0/system_bd_spi_engine_execution_0_0.xci", + "inst_hier_path": "axi_spi_engine/spi_engine_execution", + "parameters": { + "NUM_OF_CS": { + "value": "3" + }, + "NUM_OF_SDI": { + "value": "1" + } + } + } + }, + "interface_nets": { + "Conn1": { + "interface_ports": [ + "axi_spi_engine/s_axi", + "s_axi" + ] + }, + "Conn2": { + "interface_ports": [ + "spi_engine_execution/spi", + "spi" + ] + }, + "axi_spi_engine_spi_engine_ctrl": { + "interface_ports": [ + "axi_spi_engine/spi_engine_ctrl", + "spi_engine_execution/ctrl" + ] + } + }, + "nets": { + "axi_spi_engine_irq": { + "ports": [ + "axi_spi_engine/irq", + "irq" + ] + }, + "axi_spi_engine_spi_resetn": { + "ports": [ + "axi_spi_engine/spi_resetn", + "spi_engine_execution/resetn" + ] + }, + "s_axi_aclk_0_1": { + "ports": [ + "s_axi_aclk", + "axi_spi_engine/s_axi_aclk", + "axi_spi_engine/spi_clk", + "spi_engine_execution/clk" + ] + }, + "s_axi_aresetn_1": { + "ports": [ + "s_axi_aresetn", + "axi_spi_engine/s_axi_aresetn" + ] + }, + "spi_engine_execution_active": { + "ports": [ + "spi_engine_execution/active", + "active" + ] + } + } + }, + "ps8_0_axi_periph": { + "vlnv": "xilinx.com:ip:axi_interconnect:2.1", + "xci_path": "ip/system_bd_ps8_0_axi_periph_0/system_bd_ps8_0_axi_periph_0.xci", + "inst_hier_path": "ps8_0_axi_periph", + "xci_name": "system_bd_ps8_0_axi_periph_0", + "parameters": { + "NUM_MI": { + "value": "2" + } + }, + "interface_ports": { + "S00_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "M00_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "M01_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_RESET": { + "value": "ARESETN" + } + } + }, + "ARESETN": { + "type": "rst", + "direction": "I" + }, + "S00_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S00_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S00_ARESETN" + } + } + }, + "S00_ARESETN": { + "type": "rst", + "direction": "I" + }, + "M00_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M00_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M00_ARESETN" + } + } + }, + "M00_ARESETN": { + "type": "rst", + "direction": "I" + }, + "M01_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M01_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M01_ARESETN" + } + } + }, + "M01_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "components": { + "xbar": { + "vlnv": "xilinx.com:ip:axi_crossbar:2.1", + "ip_revision": "32", + "xci_name": "system_bd_xbar_0", + "xci_path": "ip/system_bd_xbar_0/system_bd_xbar_0.xci", + "inst_hier_path": "ps8_0_axi_periph/xbar", + "parameters": { + "NUM_MI": { + "value": "2" + }, + "NUM_SI": { + "value": "1" + }, + "STRATEGY": { + "value": "0" + } + }, + "interface_ports": { + "S00_AXI": { + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "Slave", + "bridges": [ + "M00_AXI", + "M01_AXI" + ] + } + } + }, + "s00_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "components": { + "auto_pc": { + "vlnv": "xilinx.com:ip:axi_protocol_converter:2.1", + "ip_revision": "31", + "xci_name": "system_bd_auto_pc_0", + "xci_path": "ip/system_bd_auto_pc_0/system_bd_auto_pc_0.xci", + "inst_hier_path": "ps8_0_axi_periph/s00_couplers/auto_pc", + "parameters": { + "MI_PROTOCOL": { + "value": "AXI4LITE" + }, + "SI_PROTOCOL": { + "value": "AXI4" + } + }, + "interface_ports": { + "S_AXI": { + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "Slave", + "bridges": [ + "M_AXI" + ] + } + } + } + }, + "interface_nets": { + "auto_pc_to_s00_couplers": { + "interface_ports": [ + "M_AXI", + "auto_pc/M_AXI" + ] + }, + "s00_couplers_to_auto_pc": { + "interface_ports": [ + "S_AXI", + "auto_pc/S_AXI" + ] + } + }, + "nets": { + "S_ACLK_1": { + "ports": [ + "S_ACLK", + "auto_pc/aclk" + ] + }, + "S_ARESETN_1": { + "ports": [ + "S_ARESETN", + "auto_pc/aresetn" + ] + } + } + }, + "m00_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "interface_nets": { + "m00_couplers_to_m00_couplers": { + "interface_ports": [ + "S_AXI", + "M_AXI" + ] + } + } + }, + "m01_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "interface_nets": { + "m01_couplers_to_m01_couplers": { + "interface_ports": [ + "S_AXI", + "M_AXI" + ] + } + } + } + }, + "interface_nets": { + "m00_couplers_to_ps8_0_axi_periph": { + "interface_ports": [ + "m00_couplers/M_AXI", + "M00_AXI" + ] + }, + "m01_couplers_to_ps8_0_axi_periph": { + "interface_ports": [ + "m01_couplers/M_AXI", + "M01_AXI" + ] + }, + "ps8_0_axi_periph_to_s00_couplers": { + "interface_ports": [ + "S00_AXI", + "s00_couplers/S_AXI" + ] + }, + "s00_couplers_to_xbar": { + "interface_ports": [ + "s00_couplers/M_AXI", + "xbar/S00_AXI" + ] + }, + "xbar_to_m00_couplers": { + "interface_ports": [ + "xbar/M00_AXI", + "m00_couplers/S_AXI" + ] + }, + "xbar_to_m01_couplers": { + "interface_ports": [ + "xbar/M01_AXI", + "m01_couplers/S_AXI" + ] + } + }, + "nets": { + "ps8_0_axi_periph_ACLK_net": { + "ports": [ + "ACLK", + "xbar/aclk", + "s00_couplers/S_ACLK", + "s00_couplers/M_ACLK", + "m00_couplers/M_ACLK", + "m01_couplers/M_ACLK", + "m00_couplers/S_ACLK", + "m01_couplers/S_ACLK" + ] + }, + "ps8_0_axi_periph_ARESETN_net": { + "ports": [ + "ARESETN", + "xbar/aresetn", + "s00_couplers/S_ARESETN", + "s00_couplers/M_ARESETN", + "m00_couplers/M_ARESETN", + "m01_couplers/M_ARESETN", + "m00_couplers/S_ARESETN", + "m01_couplers/S_ARESETN" + ] + } + } + }, + "rst_ps8_0_96M": { + "vlnv": "xilinx.com:ip:proc_sys_reset:5.0", + "ip_revision": "15", + "xci_name": "system_bd_rst_ps8_0_96M_0", + "xci_path": "ip/system_bd_rst_ps8_0_96M_0/system_bd_rst_ps8_0_96M_0.xci", + "inst_hier_path": "rst_ps8_0_96M" + }, + "mts_clk_gen": { + "interface_ports": { + "pl_clk": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:diff_clock:1.0", + "vlnv": "xilinx.com:interface:diff_clock_rtl:1.0" + }, + "pl_sysref": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:diff_clock:1.0", + "vlnv": "xilinx.com:interface:diff_clock_rtl:1.0" + } + }, + "ports": { + "mts_sysref": { + "direction": "O", + "left": "0", + "right": "0" + }, + "sys_rstn": { + "type": "clk", + "direction": "O" + }, + "sys_clk": { + "direction": "O" + } + }, + "components": { + "util_ds_buf_pl_clk": { + "vlnv": "xilinx.com:ip:util_ds_buf:2.2", + "ip_revision": "32", + "xci_name": "system_bd_util_ds_buf_0_0", + "xci_path": "ip/system_bd_util_ds_buf_0_0/system_bd_util_ds_buf_0_0.xci", + "inst_hier_path": "mts_clk_gen/util_ds_buf_pl_clk" + }, + "util_bufg_pl_clk": { + "vlnv": "xilinx.com:ip:util_ds_buf:2.2", + "ip_revision": "32", + "xci_name": "system_bd_util_ds_buf_0_1", + "xci_path": "ip/system_bd_util_ds_buf_0_1/system_bd_util_ds_buf_0_1.xci", + "inst_hier_path": "mts_clk_gen/util_bufg_pl_clk", + "parameters": { + "C_BUF_TYPE": { + "value": "BUFG" + } + } + }, + "util_ds_buf_pl_sysref": { + "vlnv": "xilinx.com:ip:util_ds_buf:2.2", + "ip_revision": "32", + "xci_name": "system_bd_util_ds_buf_1_0", + "xci_path": "ip/system_bd_util_ds_buf_1_0/system_bd_util_ds_buf_1_0.xci", + "inst_hier_path": "mts_clk_gen/util_ds_buf_pl_sysref" + }, + "clk_wiz_pl_clk": { + "vlnv": "xilinx.com:ip:clk_wiz:6.0", + "ip_revision": "14", + "xci_name": "system_bd_clk_wiz_0_0", + "xci_path": "ip/system_bd_clk_wiz_0_0/system_bd_clk_wiz_0_0.xci", + "inst_hier_path": "mts_clk_gen/clk_wiz_pl_clk", + "parameters": { + "CLKIN1_JITTER_PS": { + "value": "40.69" + }, + "CLKOUT1_JITTER": { + "value": "85.228" + }, + "CLKOUT1_PHASE_ERROR": { + "value": "77.902" + }, + "CLKOUT1_REQUESTED_OUT_FREQ": { + "value": "245.76" + }, + "MMCM_CLKFBOUT_MULT_F": { + "value": "4.875" + }, + "MMCM_CLKIN1_PERIOD": { + "value": "4.069" + }, + "MMCM_CLKIN2_PERIOD": { + "value": "10.0" + }, + "MMCM_CLKOUT0_DIVIDE_F": { + "value": "4.875" + }, + "MMCM_DIVCLK_DIVIDE": { + "value": "1" + }, + "OPTIMIZE_CLOCKING_STRUCTURE_EN": { + "value": "true" + }, + "PRIM_IN_FREQ": { + "value": "245.76" + }, + "USE_RESET": { + "value": "false" + } + } + }, + "xpm_cdc_gen_pl_sysref": { + "vlnv": "xilinx.com:ip:xpm_cdc_gen:1.0", + "ip_revision": "4", + "xci_name": "system_bd_xpm_cdc_gen_0_0", + "xci_path": "ip/system_bd_xpm_cdc_gen_0_0/system_bd_xpm_cdc_gen_0_0.xci", + "inst_hier_path": "mts_clk_gen/xpm_cdc_gen_pl_sysref", + "parameters": { + "CDC_TYPE": { + "value": "xpm_cdc_single" + }, + "DEST_SYNC_FF": { + "value": "2" + }, + "SIM_ASSERT_CHK": { + "value": "false" + }, + "SRC_INPUT_REG": { + "value": "false" + } + } + }, + "xpm_cdc_gen_mts_sysref": { + "vlnv": "xilinx.com:ip:xpm_cdc_gen:1.0", + "ip_revision": "4", + "xci_name": "system_bd_xpm_cdc_gen_pl_sysref_0", + "xci_path": "ip/system_bd_xpm_cdc_gen_pl_sysref_0/system_bd_xpm_cdc_gen_pl_sysref_0.xci", + "inst_hier_path": "mts_clk_gen/xpm_cdc_gen_mts_sysref", + "parameters": { + "CDC_TYPE": { + "value": "xpm_cdc_single" + }, + "DEST_SYNC_FF": { + "value": "2" + }, + "SIM_ASSERT_CHK": { + "value": "false" + }, + "SRC_INPUT_REG": { + "value": "false" + } + } + }, + "xlconstant_0": { + "vlnv": "xilinx.com:ip:xlconstant:1.1", + "ip_revision": "9", + "xci_name": "system_bd_xlconstant_0_0", + "xci_path": "ip/system_bd_xlconstant_0_0/system_bd_xlconstant_0_0.xci", + "inst_hier_path": "mts_clk_gen/xlconstant_0", + "parameters": { + "CONST_VAL": { + "value": "0" + } + } + } + }, + "interface_nets": { + "Conn1": { + "interface_ports": [ + "util_ds_buf_pl_clk/CLK_IN_D", + "pl_clk" + ] + }, + "Conn2": { + "interface_ports": [ + "util_ds_buf_pl_sysref/CLK_IN_D", + "pl_sysref" + ] + } + }, + "nets": { + "clk_wiz_pl_clk_clk_out1": { + "ports": [ + "clk_wiz_pl_clk/clk_out1", + "sys_clk", + "xpm_cdc_gen_mts_sysref/dest_clk" + ] + }, + "clk_wiz_pl_clk_locked": { + "ports": [ + "clk_wiz_pl_clk/locked", + "sys_rstn" + ] + }, + "util_bufg_pl_clk_BUFG_O": { + "ports": [ + "util_bufg_pl_clk/BUFG_O", + "clk_wiz_pl_clk/clk_in1", + "xpm_cdc_gen_pl_sysref/dest_clk" + ] + }, + "util_ds_buf_pl_clk_IBUF_OUT": { + "ports": [ + "util_ds_buf_pl_clk/IBUF_OUT", + "util_bufg_pl_clk/BUFG_I" + ] + }, + "util_ds_buf_pl_sysref_IBUF_OUT": { + "ports": [ + "util_ds_buf_pl_sysref/IBUF_OUT", + "xpm_cdc_gen_pl_sysref/src_in" + ] + }, + "xlconstant_0_dout": { + "ports": [ + "xlconstant_0/dout", + "xpm_cdc_gen_pl_sysref/src_clk", + "xpm_cdc_gen_mts_sysref/src_clk" + ] + }, + "xpm_cdc_gen_mts_sysref_dest_out": { + "ports": [ + "xpm_cdc_gen_mts_sysref/dest_out", + "mts_sysref" + ] + }, + "xpm_cdc_gen_pl_sysref_dest_out": { + "ports": [ + "xpm_cdc_gen_pl_sysref/dest_out", + "xpm_cdc_gen_mts_sysref/src_in" + ] + } + } + }, + "xlconcat_0": { + "vlnv": "xilinx.com:ip:xlconcat:2.1", + "ip_revision": "6", + "xci_name": "system_bd_xlconcat_0_0", + "xci_path": "ip/system_bd_xlconcat_0_0/system_bd_xlconcat_0_0.xci", + "inst_hier_path": "xlconcat_0" + }, + "zynq_ultra_ps_e": { + "vlnv": "xilinx.com:ip:zynq_ultra_ps_e:3.5", + "ip_revision": "3", + "xci_name": "system_bd_zynq_ultra_ps_e_0_1", + "xci_path": "ip/system_bd_zynq_ultra_ps_e_0_1/system_bd_zynq_ultra_ps_e_0_1.xci", + "inst_hier_path": "zynq_ultra_ps_e", + "parameters": { + "PSU_BANK_0_IO_STANDARD": { + "value": "LVCMOS18" + }, + "PSU_BANK_1_IO_STANDARD": { + "value": "LVCMOS18" + }, + "PSU_BANK_2_IO_STANDARD": { + "value": "LVCMOS18" + }, + "PSU_BANK_3_IO_STANDARD": { + "value": "LVCMOS18" + }, + "PSU_DDR_RAM_HIGHADDR": { + "value": "0xFFFFFFFF" + }, + "PSU_DDR_RAM_HIGHADDR_OFFSET": { + "value": "0x800000000" + }, + "PSU_DDR_RAM_LOWADDR_OFFSET": { + "value": "0x80000000" + }, + "PSU_DYNAMIC_DDR_CONFIG_EN": { + "value": "1" + }, + "PSU_MIO_1_DRIVE_STRENGTH": { + "value": "12" + }, + "PSU_MIO_1_SLEW": { + "value": "fast" + }, + "PSU_MIO_4_INPUT_TYPE": { + "value": "cmos" + }, + "PSU_MIO_TREE_PERIPHERALS": { + "value": [ + "Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash##Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash##I2C 0#I2C 0#I2C", + "1#I2C 1#UART 0#UART 0#######PMU GPI 0######################################Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#MDIO 3#MDIO 3" + ] + }, + "PSU_MIO_TREE_SIGNALS": { + "value": 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"name": "M_AXI_HPM0_FPD:FPD_AFI_FS1_01", + "display_name": "M_AXI_HPM0_FPD/FPD_AFI_FS1_01", + "base_address": "0x000400000000", + "range": "4G", + "width": "35", + "usage": "register" + }, + "M_AXI_HPM0_FPD:FPD_AFI_FS1_10": { + "name": "M_AXI_HPM0_FPD:FPD_AFI_FS1_10", + "display_name": "M_AXI_HPM0_FPD/FPD_AFI_FS1_10", + "base_address": "0x001000000000", + "range": "224G", + "width": "39", + "usage": "register" + } + } + } + } + } + } + } + }, + "interface_nets": { + "adc2_clk_1": { + "interface_ports": [ + "adc2_clk", + "usp_rf_data_converter/adc2_clk" + ] + }, + "adi_spi_engine_spi_0": { + "interface_ports": [ + "spi", + "axi_spi_engine/spi" + ] + }, + "dac2_clk_1": { + "interface_ports": [ + "dac2_clk", + "usp_rf_data_converter/dac2_clk" + ] + }, + "pl_clk_0_1": { + "interface_ports": [ + "pl_clk", + "mts_clk_gen/pl_clk" + ] + }, + "pl_sysref_0_1": { + "interface_ports": [ + "pl_sysref", + "mts_clk_gen/pl_sysref" + ] + }, + "ps8_0_axi_periph_M00_AXI": { + "interface_ports": [ + "ps8_0_axi_periph/M00_AXI", + "axi_spi_engine/s_axi" + ] + }, + "ps8_0_axi_periph_M01_AXI": { + "interface_ports": [ + "ps8_0_axi_periph/M01_AXI", + "usp_rf_data_converter/s_axi" + ] + }, + "s00_axis_0_1": { + "interface_ports": [ + "s00_axis", + "usp_rf_data_converter/s00_axis" + ] + }, + "s02_axis_0_1": { + "interface_ports": [ + "s02_axis", + "usp_rf_data_converter/s02_axis" + ] + }, + "s10_axis_0_1": { + "interface_ports": [ + "s10_axis", + "usp_rf_data_converter/s10_axis" + ] + }, + "s12_axis_0_1": { + "interface_ports": [ + "s12_axis", + "usp_rf_data_converter/s12_axis" + ] + }, + "s20_axis_0_1": { + "interface_ports": [ + "s20_axis", + "usp_rf_data_converter/s20_axis" + ] + }, + "s22_axis_0_1": { + "interface_ports": [ + "s22_axis", + "usp_rf_data_converter/s22_axis" + ] + }, + "s30_axis_0_1": { + "interface_ports": [ + "s30_axis", + "usp_rf_data_converter/s30_axis" + ] + }, + "s32_axis_0_1": { + "interface_ports": [ + "s32_axis", + "usp_rf_data_converter/s32_axis" + ] + }, + "sysref_in_0_1": { + "interface_ports": [ + "sysref_in", + "usp_rf_data_converter/sysref_in" + ] + }, + "usp_rf_data_converter_m00_axis": { + "interface_ports": [ + "m00_axis", + "usp_rf_data_converter/m00_axis" + ] + }, + "usp_rf_data_converter_m01_axis": { + "interface_ports": [ + "m01_axis", + "usp_rf_data_converter/m01_axis" + ] + }, + "usp_rf_data_converter_m02_axis": { + "interface_ports": [ + "m02_axis", + "usp_rf_data_converter/m02_axis" + ] + }, + "usp_rf_data_converter_m03_axis": { + "interface_ports": [ + "m03_axis", + "usp_rf_data_converter/m03_axis" + ] + }, + "usp_rf_data_converter_m10_axis": { + "interface_ports": [ + "m10_axis", + "usp_rf_data_converter/m10_axis" + ] + }, + "usp_rf_data_converter_m11_axis": { + "interface_ports": [ + "m11_axis", + "usp_rf_data_converter/m11_axis" + ] + }, + "usp_rf_data_converter_m12_axis": { + "interface_ports": [ + "m12_axis", + "usp_rf_data_converter/m12_axis" + ] + }, + "usp_rf_data_converter_m13_axis": { + "interface_ports": [ + "m13_axis", + "usp_rf_data_converter/m13_axis" + ] + }, + "usp_rf_data_converter_m20_axis": { + "interface_ports": [ + "m20_axis", + "usp_rf_data_converter/m20_axis" + ] + }, + "usp_rf_data_converter_m21_axis": { + "interface_ports": [ + "m21_axis", + "usp_rf_data_converter/m21_axis" + ] + }, + "usp_rf_data_converter_m22_axis": { + "interface_ports": [ + "m22_axis", + "usp_rf_data_converter/m22_axis" + ] + }, + "usp_rf_data_converter_m23_axis": { + "interface_ports": [ + "m23_axis", + "usp_rf_data_converter/m23_axis" + ] + }, + "usp_rf_data_converter_m30_axis": { + "interface_ports": [ + "m30_axis", + "usp_rf_data_converter/m30_axis" + ] + }, + "usp_rf_data_converter_m31_axis": { + "interface_ports": [ + "m31_axis", + "usp_rf_data_converter/m31_axis" + ] + }, + "usp_rf_data_converter_m32_axis": { + "interface_ports": [ + "m32_axis", + "usp_rf_data_converter/m32_axis" + ] + }, + "usp_rf_data_converter_m33_axis": { + "interface_ports": [ + "m33_axis", + "usp_rf_data_converter/m33_axis" + ] + }, + "usp_rf_data_converter_vout00": { + "interface_ports": [ + "vout00", + "usp_rf_data_converter/vout00" + ] + }, + "usp_rf_data_converter_vout02": { + "interface_ports": [ + "vout02", + "usp_rf_data_converter/vout02" + ] + }, + "usp_rf_data_converter_vout10": { + "interface_ports": [ + "vout10", + "usp_rf_data_converter/vout10" + ] + }, + "usp_rf_data_converter_vout12": { + "interface_ports": [ + "vout12", + "usp_rf_data_converter/vout12" + ] + }, + "usp_rf_data_converter_vout20": { + "interface_ports": [ + "vout20", + "usp_rf_data_converter/vout20" + ] + }, + "usp_rf_data_converter_vout22": { + "interface_ports": [ + "vout22", + "usp_rf_data_converter/vout22" + ] + }, + "usp_rf_data_converter_vout30": { + "interface_ports": [ + "vout30", + "usp_rf_data_converter/vout30" + ] + }, + "usp_rf_data_converter_vout32": { + "interface_ports": [ + "vout32", + "usp_rf_data_converter/vout32" + ] + }, + "vin0_01_0_1": { + "interface_ports": [ + "vin0_01", + "usp_rf_data_converter/vin0_01" + ] + }, + "vin0_23_0_1": { + "interface_ports": [ + "vin0_23", + "usp_rf_data_converter/vin0_23" + ] + }, + "vin1_01_0_1": { + "interface_ports": [ + "vin1_01", + "usp_rf_data_converter/vin1_01" + ] + }, + "vin1_23_0_1": { + "interface_ports": [ + "vin1_23", + "usp_rf_data_converter/vin1_23" + ] + }, + "vin2_01_0_1": { + "interface_ports": [ + "vin2_01", + "usp_rf_data_converter/vin2_01" + ] + }, + "vin2_23_0_1": { + "interface_ports": [ + "vin2_23", + "usp_rf_data_converter/vin2_23" + ] + }, + "vin3_01_0_1": { + "interface_ports": [ + "vin3_01", + "usp_rf_data_converter/vin3_01" + ] + }, + "vin3_23_0_1": { + "interface_ports": [ + "vin3_23", + "usp_rf_data_converter/vin3_23" + ] + }, + "zynq_ultra_ps_e_M_AXI_HPM0_LPD": { + "interface_ports": [ + "zynq_ultra_ps_e/M_AXI_HPM0_LPD", + "ps8_0_axi_periph/S00_AXI" + ] + } + }, + "nets": { + "adi_spi_engine_active_0": { + "ports": [ + "axi_spi_engine/active", + "spi_active" + ] + }, + "adi_spi_engine_irq": { + "ports": [ + "axi_spi_engine/irq", + "xlconcat_0/In1" + ] + }, + "m0_axis_aclk_0_1": { + "ports": [ + "m0_axis_aclk", + "usp_rf_data_converter/m0_axis_aclk" + ] + }, + "m0_axis_aresetn_0_1": { + "ports": [ + "m0_axis_aresetn", + "usp_rf_data_converter/m0_axis_aresetn" + ] + }, + "m1_axis_aclk_0_1": { + "ports": [ + "m1_axis_aclk", + "usp_rf_data_converter/m1_axis_aclk" + ] + }, + "m1_axis_aresetn_0_1": { + "ports": [ + "m1_axis_aresetn", + "usp_rf_data_converter/m1_axis_aresetn" + ] + }, + "m2_axis_aclk_0_1": { + "ports": [ + "m2_axis_aclk", + "usp_rf_data_converter/m2_axis_aclk" + ] + }, + "m2_axis_aresetn_0_1": { + "ports": [ + "m2_axis_aresetn", + "usp_rf_data_converter/m2_axis_aresetn" + ] + }, + "m3_axis_aclk_0_1": { + "ports": [ + "m3_axis_aclk", + "usp_rf_data_converter/m3_axis_aclk" + ] + }, + "m3_axis_aresetn_0_1": { + "ports": [ + "m3_axis_aresetn", + "usp_rf_data_converter/m3_axis_aresetn" + ] + }, + "mts_sysref_gen_clk_out1_0": { + "ports": [ + "mts_clk_gen/sys_rstn", + "sys_rstn" + ] + }, + "mts_sysref_gen_locked_0": { + "ports": [ + "mts_clk_gen/sys_clk", + "sys_clk" + ] + }, + "mts_sysref_gen_mts_sysref": { + "ports": [ + "mts_clk_gen/mts_sysref", + "usp_rf_data_converter/user_sysref_adc", + "usp_rf_data_converter/user_sysref_dac" + ] + }, + "rst_ps8_0_96M_peripheral_aresetn": { + "ports": [ + "rst_ps8_0_96M/peripheral_aresetn", + "ps8_0_axi_periph/S00_ARESETN", + "axi_spi_engine/s_axi_aresetn", + "ps8_0_axi_periph/M00_ARESETN", + "ps8_0_axi_periph/ARESETN", + "usp_rf_data_converter/s_axi_aresetn", + "ps8_0_axi_periph/M01_ARESETN" + ] + }, + "s0_axis_aclk_0_1": { + "ports": [ + "s0_axis_aclk", + "usp_rf_data_converter/s0_axis_aclk" + ] + }, + "s0_axis_aresetn_0_1": { + "ports": [ + "s0_axis_aresetn", + "usp_rf_data_converter/s0_axis_aresetn" + ] + }, + "s1_axis_aclk_0_1": { + "ports": [ + "s1_axis_aclk", + "usp_rf_data_converter/s1_axis_aclk" + ] + }, + "s1_axis_aresetn_0_1": { + "ports": [ + "s1_axis_aresetn", + "usp_rf_data_converter/s1_axis_aresetn" + ] + }, + "s2_axis_aclk_0_1": { + "ports": [ + "s2_axis_aclk", + "usp_rf_data_converter/s2_axis_aclk" + ] + }, + "s2_axis_aresetn_0_1": { + "ports": [ + "s2_axis_aresetn", + "usp_rf_data_converter/s2_axis_aresetn" + ] + }, + "s3_axis_aclk_0_1": { + "ports": [ + "s3_axis_aclk", + "usp_rf_data_converter/s3_axis_aclk" + ] + }, + "s3_axis_aresetn_0_1": { + "ports": [ + "s3_axis_aresetn", + "usp_rf_data_converter/s3_axis_aresetn" + ] + }, + "usp_rf_data_converter_clk_adc0": { + "ports": [ + "usp_rf_data_converter/clk_adc0", + "clk_adc0" + ] + }, + "usp_rf_data_converter_clk_adc1": { + "ports": [ + "usp_rf_data_converter/clk_adc1", + "clk_adc1" + ] + }, + "usp_rf_data_converter_clk_adc2": { + "ports": [ + "usp_rf_data_converter/clk_adc2", + "clk_adc2" + ] + }, + "usp_rf_data_converter_clk_adc3": { + "ports": [ + "usp_rf_data_converter/clk_adc3", + "clk_adc3" + ] + }, + "usp_rf_data_converter_clk_dac0": { + "ports": [ + "usp_rf_data_converter/clk_dac0", + "clk_dac0" + ] + }, + "usp_rf_data_converter_clk_dac1": { + "ports": [ + "usp_rf_data_converter/clk_dac1", + "clk_dac1" + ] + }, + "usp_rf_data_converter_clk_dac2": { + "ports": [ + "usp_rf_data_converter/clk_dac2", + "clk_dac2" + ] + }, + "usp_rf_data_converter_clk_dac3": { + "ports": [ + "usp_rf_data_converter/clk_dac3", + "clk_dac3" + ] + }, + "usp_rf_data_converter_irq": { + "ports": [ + "usp_rf_data_converter/irq", + "xlconcat_0/In0" + ] + }, + "xlconcat_0_dout": { + "ports": [ + "xlconcat_0/dout", + "zynq_ultra_ps_e/pl_ps_irq0" + ] + }, + "zynq_ultra_ps_e_pl_clk0": { + "ports": [ + "zynq_ultra_ps_e/pl_clk0", + "ps_clk0", + "ps8_0_axi_periph/S00_ACLK", + "rst_ps8_0_96M/slowest_sync_clk", + "axi_spi_engine/s_axi_aclk", + "ps8_0_axi_periph/M00_ACLK", + "ps8_0_axi_periph/ACLK", + "usp_rf_data_converter/s_axi_aclk", + "ps8_0_axi_periph/M01_ACLK", + "zynq_ultra_ps_e/maxihpm0_lpd_aclk" + ] + }, + "zynq_ultra_ps_e_pl_resetn0": { + "ports": [ + "zynq_ultra_ps_e/pl_resetn0", + "rst_ps8_0_96M/ext_reset_in" + ] + } + }, + "addressing": { + "/zynq_ultra_ps_e": { + "address_spaces": { + "Data": { + "segments": { + "SEG_axi_spi_engine_axi_lite": { + "address_block": "/axi_spi_engine/axi_spi_engine/s_axi/axi_lite", + "offset": "0x0080000000", + "range": "64K" + }, + "SEG_usp_rf_data_converter_Reg": { + "address_block": "/usp_rf_data_converter/s_axi/Reg", + "offset": "0x0080040000", + "range": "256K" + } + } + } + } + } + } + } +} \ No newline at end of file diff --git a/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/system_bd.bda b/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/system_bd.bda new file mode 100644 index 0000000..b8b6e84 --- /dev/null +++ b/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/system_bd.bda @@ -0,0 +1,249 @@ +{ + "graphjs": { + "version": "1.0", + "keys": [ + { + "abrv": "VH", + "name": "vert_hid", + "type": "int", + "for": "node" + }, + { + "abrv": "VM", + "name": "vert_name", + "type": "string", + "for": "node" + }, + { + "abrv": "VT", + "name": "vert_type", + "type": "string", + "for": "node" + }, + { + "abrv": "BA", + "name": "base_addr", + "type": "string", + "for": "node" + }, + { + "abrv": "HA", + "name": "high_addr", + "type": "string", + "for": "node" + }, + { + "abrv": "BP", + "name": "base_param", + "type": "string", + "for": "node" + }, + { + "abrv": "HP", + "name": "high_param", + "type": "string", + "for": "node" + }, + { + "abrv": "MA", + "name": "master_addrspace", + "type": "string", + "for": "node" + }, + { + "abrv": "MX", + "name": "master_instance", + "type": "string", + "for": "node" + }, + { + "abrv": "MI", + "name": "master_interface", + "type": "string", + "for": "node" + }, + { + "abrv": "MS", + "name": "master_segment", + "type": "string", + "for": "node" + }, + { + "abrv": "MV", + "name": "master_vlnv", + "type": "string", + "for": "node" + }, + { + "abrv": "SX", + "name": "slave_instance", + "type": "string", + "for": "node" + }, + { + "abrv": "SI", + "name": "slave_interface", + "type": "string", + "for": "node" + }, + { + "abrv": "MM", + "name": "slave_memmap", + "type": "string", + "for": "node" + }, + { + "abrv": "SS", + "name": "slave_segment", + "type": "string", + "for": "node" + }, + { + "abrv": "SV", + "name": "slave_vlnv", + "type": "string", + "for": "node" + }, + { + "abrv": "TM", + "name": "memory_type", + "type": "string", + "for": "node" + }, + { + "abrv": "TU", + "name": "usage_type", + "type": "string", + "for": "node" + }, + { + "abrv": "LT", + "name": "lock_type", + "type": "string", + "for": "node" + }, + { + "abrv": "BT", + "name": "boot_type", + "type": "string", + "for": "node" + }, + { + "abrv": "EH", + "name": "edge_hid", + "type": "int", + "for": "edge" + } + ], + "vertice_type_order": [ + { + "abrv": "BC", + "desc": "Block Container" + }, + { + "abrv": "PR", + "desc": "Parital Reference" + }, + { + "abrv": "VR", + "desc": "Variant" + }, + { + "abrv": "PM", + "desc": "Variant Permutations" + }, + { + "abrv": "CX", + "desc": "Boundary Connection" + }, + { + "abrv": "AC", + "desc": "Assignment Coordinate" + }, + { + "abrv": "ACE", + "desc": "Excluded Assign Coordinate" + }, + { + "abrv": "APX", + "desc": "Boundary Aperture" + }, + { + "abrv": "CIP", + "desc": "High level Processing System" + } + ], + "vertices": { + "V0": { + "VM": "system_bd", + "VT": "BC" + }, + "V1": { + "VH": "2", + "VM": "system_bd", + "VT": "VR" + }, + "V2": { + "VH": "2", + "VT": "PM", + "TU": "active" + }, + "V3": { + "VT": "AC", + "BA": "0x0080000000", + "HA": "0x008000FFFF", + "BP": "C_BASEADDR", + "HP": "C_HIGHADDR", + "MA": "Data", + "MX": "/zynq_ultra_ps_e", + "MI": "M_AXI_HPM0_LPD", + "MS": "SEG_axi_spi_engine_axi_lite", + "MV": "xilinx.com:ip:zynq_ultra_ps_e:3.5", + "SX": "/axi_spi_engine/axi_spi_engine", + "SI": "s_axi", + "SS": "axi_lite", + "SV": "analog.com:user:axi_spi_engine:1.0", + "TM": "both", + "TU": "register" + }, + "V4": { + "VT": "AC", + "BA": "0x0080040000", + "HA": "0x008007FFFF", + "BP": "C_BASEADDR", + "HP": "C_HIGHADDR", + "MA": "Data", + "MX": "/zynq_ultra_ps_e", + "MI": "M_AXI_HPM0_LPD", + "MS": "SEG_usp_rf_data_converter_Reg", + "MV": "xilinx.com:ip:zynq_ultra_ps_e:3.5", + "SX": "/usp_rf_data_converter", + "SI": "s_axi", + "SS": "Reg", + "SV": "xilinx.com:ip:usp_rf_data_converter:2.6", + "TM": "both", + "TU": "register" + } + }, + "edges": [ + { + "src": "V0", + "trg": "V1" + }, + { + "src": "V1", + "trg": "V2" + }, + { + "src": "V3", + "trg": "V2", + "EH": "2" + }, + { + "src": "V4", + "trg": "V2", + "EH": "2" + } + ] + } +} diff --git a/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ui/bd_2942602e.ui b/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ui/bd_2942602e.ui new file mode 100644 index 0000000..901b2ad --- /dev/null +++ b/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ui/bd_2942602e.ui @@ -0,0 +1,34 @@ +{ + "ActiveEmotionalView":"Default View", + "Default View_ScaleFactor":"1.0", + "Default View_TopLeft":"-360,-198", + "ExpandedHierarchyInLayout":"", + "guistr":"# # String gsaved with Nlview 7.7.1 2023-07-26 3bc4126617 VDI=43 GEI=38 GUI=JA:21.0 TLS +# -string -flagsOSRD +preplace port pl_clk -pg 1 -lvl 0 -x 0 -y 70 -defaultsOSRD +preplace port pl_sysref -pg 1 -lvl 0 -x 0 -y 240 -defaultsOSRD +preplace port port-id_sys_rstn -pg 1 -lvl 5 -x 1060 -y 80 -defaultsOSRD +preplace port port-id_sys_clk -pg 1 -lvl 5 -x 1060 -y 60 -defaultsOSRD +preplace portBus mts_sysref -pg 1 -lvl 5 -x 1060 -y 170 -defaultsOSRD +preplace inst util_ds_buf_pl_clk -pg 1 -lvl 1 -x 150 -y 70 -defaultsOSRD +preplace inst util_bufg_pl_clk -pg 1 -lvl 2 -x 410 -y 70 -defaultsOSRD -resize 220 88 +preplace inst util_ds_buf_pl_sysref -pg 1 -lvl 2 -x 410 -y 240 -defaultsOSRD -resize 220 88 +preplace inst clk_wiz_pl_clk -pg 1 -lvl 3 -x 670 -y 70 -defaultsOSRD +preplace inst xpm_cdc_gen_pl_sysref -pg 1 -lvl 3 -x 670 -y 220 -defaultsOSRD +preplace inst xpm_cdc_gen_mts_sysref -pg 1 -lvl 4 -x 910 -y 160 -defaultsOSRD -resize 200 116 +preplace inst xlconstant_0 -pg 1 -lvl 2 -x 410 -y 350 -defaultsOSRD +preplace netloc util_ds_buf_pl_clk_IBUF_OUT 1 1 1 NJ 70 +preplace netloc util_bufg_pl_clk_BUFG_O 1 2 1 540 70n +preplace netloc xlconstant_0_dout 1 2 2 550 140 NJ +preplace netloc util_ds_buf_pl_sysref_IBUF_OUT 1 2 1 NJ 240 +preplace netloc xpm_cdc_gen_pl_sysref_dest_out 1 3 1 790 180n +preplace netloc xpm_cdc_gen_mts_sysref_dest_out 1 4 1 1030J 160n +preplace netloc clk_wiz_pl_clk_locked 1 3 2 NJ 80 N +preplace netloc clk_wiz_pl_clk_clk_out1 1 3 2 790 60 NJ +preplace netloc Conn1 1 0 1 NJ 70 +preplace netloc Conn2 1 0 2 NJ 240 NJ +levelinfo -pg 1 0 150 410 670 910 1060 +pagesize -pg 1 -db -bbox -sgen -120 0 1230 410 +" +} + diff --git a/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ui/bd_af01e55c.ui b/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ui/bd_af01e55c.ui new file mode 100644 index 0000000..901b2ad --- /dev/null +++ b/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ui/bd_af01e55c.ui @@ -0,0 +1,34 @@ +{ + "ActiveEmotionalView":"Default View", + "Default View_ScaleFactor":"1.0", + "Default View_TopLeft":"-360,-198", + "ExpandedHierarchyInLayout":"", + "guistr":"# # String gsaved with Nlview 7.7.1 2023-07-26 3bc4126617 VDI=43 GEI=38 GUI=JA:21.0 TLS +# -string -flagsOSRD +preplace port pl_clk -pg 1 -lvl 0 -x 0 -y 70 -defaultsOSRD +preplace port pl_sysref -pg 1 -lvl 0 -x 0 -y 240 -defaultsOSRD +preplace port port-id_sys_rstn -pg 1 -lvl 5 -x 1060 -y 80 -defaultsOSRD +preplace port port-id_sys_clk -pg 1 -lvl 5 -x 1060 -y 60 -defaultsOSRD +preplace portBus mts_sysref -pg 1 -lvl 5 -x 1060 -y 170 -defaultsOSRD +preplace inst util_ds_buf_pl_clk -pg 1 -lvl 1 -x 150 -y 70 -defaultsOSRD +preplace inst util_bufg_pl_clk -pg 1 -lvl 2 -x 410 -y 70 -defaultsOSRD -resize 220 88 +preplace inst util_ds_buf_pl_sysref -pg 1 -lvl 2 -x 410 -y 240 -defaultsOSRD -resize 220 88 +preplace inst clk_wiz_pl_clk -pg 1 -lvl 3 -x 670 -y 70 -defaultsOSRD +preplace inst xpm_cdc_gen_pl_sysref -pg 1 -lvl 3 -x 670 -y 220 -defaultsOSRD +preplace inst xpm_cdc_gen_mts_sysref -pg 1 -lvl 4 -x 910 -y 160 -defaultsOSRD -resize 200 116 +preplace inst xlconstant_0 -pg 1 -lvl 2 -x 410 -y 350 -defaultsOSRD +preplace netloc util_ds_buf_pl_clk_IBUF_OUT 1 1 1 NJ 70 +preplace netloc util_bufg_pl_clk_BUFG_O 1 2 1 540 70n +preplace netloc xlconstant_0_dout 1 2 2 550 140 NJ +preplace netloc util_ds_buf_pl_sysref_IBUF_OUT 1 2 1 NJ 240 +preplace netloc xpm_cdc_gen_pl_sysref_dest_out 1 3 1 790 180n +preplace netloc xpm_cdc_gen_mts_sysref_dest_out 1 4 1 1030J 160n +preplace netloc clk_wiz_pl_clk_locked 1 3 2 NJ 80 N +preplace netloc clk_wiz_pl_clk_clk_out1 1 3 2 790 60 NJ +preplace netloc Conn1 1 0 1 NJ 70 +preplace netloc Conn2 1 0 2 NJ 240 NJ +levelinfo -pg 1 0 150 410 670 910 1060 +pagesize -pg 1 -db -bbox -sgen -120 0 1230 410 +" +} + diff --git a/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ui/bd_c6d0cb12.ui b/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ui/bd_c6d0cb12.ui new file mode 100644 index 0000000..ab0bd28 --- /dev/null +++ b/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ui/bd_c6d0cb12.ui @@ -0,0 +1,179 @@ +{ + "ActiveEmotionalView":"Default View", + "Default View_ScaleFactor":"0.537304", + "Default View_TopLeft":"-1158,4", + "ExpandedHierarchyInLayout":"", + "guistr":"# # String gsaved with Nlview 7.7.1 2023-07-26 3bc4126617 VDI=43 GEI=38 GUI=JA:21.0 TLS +# -string -flagsOSRD +preplace port spi -pg 1 -lvl 4 -x 1120 -y 330 -defaultsOSRD +preplace port pl_clk -pg 1 -lvl 0 -x 0 -y 1450 -defaultsOSRD +preplace port pl_sysref -pg 1 -lvl 0 -x 0 -y 1470 -defaultsOSRD +preplace port adc2_clk -pg 1 -lvl 0 -x 0 -y 700 -defaultsOSRD +preplace port dac2_clk -pg 1 -lvl 0 -x 0 -y 720 -defaultsOSRD +preplace port m00_axis -pg 1 -lvl 4 -x 1120 -y 590 -defaultsOSRD +preplace port m01_axis -pg 1 -lvl 4 -x 1120 -y 610 -defaultsOSRD +preplace port m02_axis -pg 1 -lvl 4 -x 1120 -y 630 -defaultsOSRD +preplace port m03_axis -pg 1 -lvl 4 -x 1120 -y 650 -defaultsOSRD +preplace port m10_axis -pg 1 -lvl 4 -x 1120 -y 670 -defaultsOSRD +preplace port m11_axis -pg 1 -lvl 4 -x 1120 -y 690 -defaultsOSRD +preplace port m12_axis -pg 1 -lvl 4 -x 1120 -y 710 -defaultsOSRD +preplace port m13_axis -pg 1 -lvl 4 -x 1120 -y 730 -defaultsOSRD +preplace port m20_axis -pg 1 -lvl 4 -x 1120 -y 750 -defaultsOSRD +preplace port m21_axis -pg 1 -lvl 4 -x 1120 -y 770 -defaultsOSRD +preplace port m22_axis -pg 1 -lvl 4 -x 1120 -y 790 -defaultsOSRD +preplace port m23_axis -pg 1 -lvl 4 -x 1120 -y 810 -defaultsOSRD +preplace port m30_axis -pg 1 -lvl 4 -x 1120 -y 830 -defaultsOSRD +preplace port m31_axis -pg 1 -lvl 4 -x 1120 -y 850 -defaultsOSRD +preplace port m32_axis -pg 1 -lvl 4 -x 1120 -y 870 -defaultsOSRD +preplace port m33_axis -pg 1 -lvl 4 -x 1120 -y 890 -defaultsOSRD +preplace port s00_axis -pg 1 -lvl 0 -x 0 -y 540 -defaultsOSRD +preplace port s02_axis -pg 1 -lvl 0 -x 0 -y 560 -defaultsOSRD +preplace port s10_axis -pg 1 -lvl 0 -x 0 -y 580 -defaultsOSRD +preplace port s12_axis -pg 1 -lvl 0 -x 0 -y 600 -defaultsOSRD +preplace port s20_axis -pg 1 -lvl 0 -x 0 -y 620 -defaultsOSRD +preplace port s22_axis -pg 1 -lvl 0 -x 0 -y 640 -defaultsOSRD +preplace port s30_axis -pg 1 -lvl 0 -x 0 -y 660 -defaultsOSRD +preplace port s32_axis -pg 1 -lvl 0 -x 0 -y 680 -defaultsOSRD +preplace port sysref_in -pg 1 -lvl 0 -x 0 -y 900 -defaultsOSRD +preplace port vin0_01 -pg 1 -lvl 0 -x 0 -y 740 -defaultsOSRD +preplace port vin0_23 -pg 1 -lvl 0 -x 0 -y 760 -defaultsOSRD +preplace port vin1_01 -pg 1 -lvl 0 -x 0 -y 780 -defaultsOSRD +preplace port vin1_23 -pg 1 -lvl 0 -x 0 -y 800 -defaultsOSRD +preplace port vin2_01 -pg 1 -lvl 0 -x 0 -y 820 -defaultsOSRD +preplace port vin2_23 -pg 1 -lvl 0 -x 0 -y 840 -defaultsOSRD +preplace port vin3_01 -pg 1 -lvl 0 -x 0 -y 860 -defaultsOSRD +preplace port vin3_23 -pg 1 -lvl 0 -x 0 -y 880 -defaultsOSRD +preplace port vout00 -pg 1 -lvl 4 -x 1120 -y 910 -defaultsOSRD +preplace port vout02 -pg 1 -lvl 4 -x 1120 -y 930 -defaultsOSRD +preplace port vout10 -pg 1 -lvl 4 -x 1120 -y 950 -defaultsOSRD +preplace port vout12 -pg 1 -lvl 4 -x 1120 -y 970 -defaultsOSRD +preplace port vout20 -pg 1 -lvl 4 -x 1120 -y 990 -defaultsOSRD +preplace port vout22 -pg 1 -lvl 4 -x 1120 -y 1010 -defaultsOSRD +preplace port vout30 -pg 1 -lvl 4 -x 1120 -y 1030 -defaultsOSRD +preplace port vout32 -pg 1 -lvl 4 -x 1120 -y 1050 -defaultsOSRD +preplace port port-id_spi_active -pg 1 -lvl 4 -x 1120 -y 350 -defaultsOSRD +preplace port port-id_sys_rstn -pg 1 -lvl 4 -x 1120 -y 1460 -defaultsOSRD +preplace port port-id_sys_clk -pg 1 -lvl 4 -x 1120 -y 1480 -defaultsOSRD +preplace port port-id_ps_clk0 -pg 1 -lvl 4 -x 1120 -y 540 -defaultsOSRD +preplace port port-id_clk_adc0 -pg 1 -lvl 4 -x 1120 -y 1070 -defaultsOSRD +preplace port port-id_clk_adc1 -pg 1 -lvl 4 -x 1120 -y 1090 -defaultsOSRD +preplace port port-id_clk_adc2 -pg 1 -lvl 4 -x 1120 -y 1110 -defaultsOSRD +preplace port port-id_clk_adc3 -pg 1 -lvl 4 -x 1120 -y 1130 -defaultsOSRD +preplace port port-id_clk_dac0 -pg 1 -lvl 4 -x 1120 -y 1150 -defaultsOSRD +preplace port port-id_clk_dac1 -pg 1 -lvl 4 -x 1120 -y 1170 -defaultsOSRD +preplace port port-id_clk_dac2 -pg 1 -lvl 4 -x 1120 -y 1190 -defaultsOSRD +preplace port port-id_clk_dac3 -pg 1 -lvl 4 -x 1120 -y 1210 -defaultsOSRD +preplace port port-id_m0_axis_aclk -pg 1 -lvl 0 -x 0 -y 1020 -defaultsOSRD +preplace port port-id_m0_axis_aresetn -pg 1 -lvl 0 -x 0 -y 1000 -defaultsOSRD +preplace port port-id_m1_axis_aclk -pg 1 -lvl 0 -x 0 -y 1060 -defaultsOSRD +preplace port port-id_m1_axis_aresetn -pg 1 -lvl 0 -x 0 -y 1040 -defaultsOSRD +preplace port port-id_m2_axis_aclk -pg 1 -lvl 0 -x 0 -y 1100 -defaultsOSRD +preplace port port-id_m2_axis_aresetn -pg 1 -lvl 0 -x 0 -y 1080 -defaultsOSRD +preplace port port-id_m3_axis_aclk -pg 1 -lvl 0 -x 0 -y 1140 -defaultsOSRD +preplace port port-id_m3_axis_aresetn -pg 1 -lvl 0 -x 0 -y 1120 -defaultsOSRD +preplace port port-id_s0_axis_aclk -pg 1 -lvl 0 -x 0 -y 1180 -defaultsOSRD +preplace port port-id_s0_axis_aresetn -pg 1 -lvl 0 -x 0 -y 1160 -defaultsOSRD +preplace port port-id_s1_axis_aclk -pg 1 -lvl 0 -x 0 -y 1220 -defaultsOSRD +preplace port port-id_s1_axis_aresetn -pg 1 -lvl 0 -x 0 -y 1200 -defaultsOSRD +preplace port port-id_s2_axis_aclk -pg 1 -lvl 0 -x 0 -y 1260 -defaultsOSRD +preplace port port-id_s2_axis_aresetn -pg 1 -lvl 0 -x 0 -y 1240 -defaultsOSRD +preplace port port-id_s3_axis_aclk -pg 1 -lvl 0 -x 0 -y 1300 -defaultsOSRD +preplace port port-id_s3_axis_aresetn -pg 1 -lvl 0 -x 0 -y 1280 -defaultsOSRD +preplace inst usp_rf_data_converter -pg 1 -lvl 1 -x 360 -y 910 -defaultsOSRD +preplace inst axi_spi_engine -pg 1 -lvl 2 -x 880 -y 350 -defaultsOSRD +preplace inst ps8_0_axi_periph -pg 1 -lvl 1 -x 360 -y 340 -defaultsOSRD +preplace inst rst_ps8_0_96M -pg 1 -lvl 2 -x 880 -y 170 -defaultsOSRD +preplace inst mts_clk_gen -pg 1 -lvl 1 -x 360 -y 1460 -defaultsOSRD +preplace inst xlconcat_0 -pg 1 -lvl 2 -x 880 -y 470 -defaultsOSRD -orient R180 +preplace inst zynq_ultra_ps_e -pg 1 -lvl 1 -x 360 -y 110 -defaultsOSRD +preplace netloc adi_spi_engine_active_0 1 2 2 N 350 N +preplace netloc adi_spi_engine_irq 1 2 1 1060 370n +preplace netloc m0_axis_aclk_0_1 1 0 1 NJ 1020 +preplace netloc m0_axis_aresetn_0_1 1 0 1 NJ 1000 +preplace netloc m1_axis_aclk_0_1 1 0 1 NJ 1060 +preplace netloc m1_axis_aresetn_0_1 1 0 1 NJ 1040 +preplace netloc m2_axis_aclk_0_1 1 0 1 NJ 1100 +preplace netloc m2_axis_aresetn_0_1 1 0 1 NJ 1080 +preplace netloc m3_axis_aclk_0_1 1 0 1 NJ 1140 +preplace netloc m3_axis_aresetn_0_1 1 0 1 NJ 1120 +preplace netloc mts_sysref_gen_clk_out1_0 1 1 3 N 1460 NJ 1460 N +preplace netloc mts_sysref_gen_locked_0 1 1 3 N 1480 NJ 1480 N +preplace netloc mts_sysref_gen_mts_sysref 1 0 2 20 1380 670 +preplace netloc rst_ps8_0_96M_peripheral_aresetn 1 0 3 40 1360 700J 270 1060 +preplace netloc s0_axis_aclk_0_1 1 0 1 NJ 1180 +preplace netloc s0_axis_aresetn_0_1 1 0 1 NJ 1160 +preplace netloc s1_axis_aclk_0_1 1 0 1 NJ 1220 +preplace netloc s1_axis_aresetn_0_1 1 0 1 NJ 1200 +preplace netloc s2_axis_aclk_0_1 1 0 1 NJ 1260 +preplace netloc s2_axis_aresetn_0_1 1 0 1 NJ 1240 +preplace netloc s3_axis_aclk_0_1 1 0 1 NJ 1300 +preplace netloc s3_axis_aresetn_0_1 1 0 1 N 1280 +preplace netloc usp_rf_data_converter_clk_adc0 1 1 3 N 1070 NJ 1070 N +preplace netloc usp_rf_data_converter_clk_adc1 1 1 3 N 1090 NJ 1090 N +preplace netloc usp_rf_data_converter_clk_adc2 1 1 3 N 1110 NJ 1110 N +preplace netloc usp_rf_data_converter_clk_adc3 1 1 3 N 1130 NJ 1130 N +preplace netloc usp_rf_data_converter_clk_dac0 1 1 3 N 1150 NJ 1150 N +preplace netloc usp_rf_data_converter_clk_dac1 1 1 3 N 1170 NJ 1170 N +preplace netloc usp_rf_data_converter_clk_dac2 1 1 3 N 1190 NJ 1190 N +preplace netloc usp_rf_data_converter_clk_dac3 1 1 3 N 1210 NJ 1210 N +preplace netloc usp_rf_data_converter_irq 1 1 2 N 1230 1060 +preplace netloc xlconcat_0_dout 1 0 2 20 10 680J +preplace netloc zynq_ultra_ps_e_pl_clk0 1 0 4 30 1370 690J 540 NJ 540 N +preplace netloc zynq_ultra_ps_e_pl_resetn0 1 1 1 670 110n +preplace netloc adc2_clk_1 1 0 1 N 700 +preplace netloc adi_spi_engine_spi_0 1 2 2 N 330 N +preplace netloc dac2_clk_1 1 0 1 N 720 +preplace netloc pl_clk_0_1 1 0 1 N 1450 +preplace netloc pl_sysref_0_1 1 0 1 N 1470 +preplace netloc ps8_0_axi_periph_M00_AXI 1 1 1 NJ 330 +preplace netloc ps8_0_axi_periph_M01_AXI 1 0 2 50 200 670J +preplace netloc s00_axis_0_1 1 0 1 NJ 540 +preplace netloc s02_axis_0_1 1 0 1 NJ 560 +preplace netloc s10_axis_0_1 1 0 1 NJ 580 +preplace netloc s12_axis_0_1 1 0 1 NJ 600 +preplace netloc s20_axis_0_1 1 0 1 NJ 620 +preplace netloc s22_axis_0_1 1 0 1 NJ 640 +preplace netloc s30_axis_0_1 1 0 1 NJ 660 +preplace netloc s32_axis_0_1 1 0 1 NJ 680 +preplace netloc sysref_in_0_1 1 0 1 NJ 900 +preplace netloc usp_rf_data_converter_m00_axis 1 1 3 N 590 NJ 590 N +preplace netloc usp_rf_data_converter_m01_axis 1 1 3 N 610 NJ 610 N +preplace netloc usp_rf_data_converter_m02_axis 1 1 3 N 630 NJ 630 N +preplace netloc usp_rf_data_converter_m03_axis 1 1 3 N 650 NJ 650 N +preplace netloc usp_rf_data_converter_m10_axis 1 1 3 N 670 NJ 670 N +preplace netloc usp_rf_data_converter_m11_axis 1 1 3 N 690 NJ 690 N +preplace netloc usp_rf_data_converter_m12_axis 1 1 3 N 710 NJ 710 N +preplace netloc usp_rf_data_converter_m13_axis 1 1 3 N 730 NJ 730 N +preplace netloc usp_rf_data_converter_m20_axis 1 1 3 N 750 NJ 750 N +preplace netloc usp_rf_data_converter_m21_axis 1 1 3 N 770 NJ 770 N +preplace netloc usp_rf_data_converter_m22_axis 1 1 3 N 790 NJ 790 N +preplace netloc usp_rf_data_converter_m23_axis 1 1 3 N 810 NJ 810 N +preplace netloc usp_rf_data_converter_m30_axis 1 1 3 N 830 NJ 830 N +preplace netloc usp_rf_data_converter_m31_axis 1 1 3 N 850 NJ 850 N +preplace netloc usp_rf_data_converter_m32_axis 1 1 3 N 870 NJ 870 N +preplace netloc usp_rf_data_converter_m33_axis 1 1 3 N 890 NJ 890 N +preplace netloc usp_rf_data_converter_vout00 1 1 3 N 910 NJ 910 N +preplace netloc usp_rf_data_converter_vout02 1 1 3 N 930 NJ 930 N +preplace netloc usp_rf_data_converter_vout10 1 1 3 N 950 NJ 950 N +preplace netloc usp_rf_data_converter_vout12 1 1 3 N 970 NJ 970 N +preplace netloc usp_rf_data_converter_vout20 1 1 3 N 990 NJ 990 N +preplace netloc usp_rf_data_converter_vout22 1 1 3 N 1010 NJ 1010 N +preplace netloc usp_rf_data_converter_vout30 1 1 3 N 1030 NJ 1030 N +preplace netloc usp_rf_data_converter_vout32 1 1 3 N 1050 NJ 1050 N +preplace netloc vin0_01_0_1 1 0 1 NJ 740 +preplace netloc vin0_23_0_1 1 0 1 NJ 760 +preplace netloc vin1_01_0_1 1 0 1 NJ 780 +preplace netloc vin1_23_0_1 1 0 1 NJ 800 +preplace netloc vin2_01_0_1 1 0 1 NJ 820 +preplace netloc vin2_23_0_1 1 0 1 NJ 840 +preplace netloc vin3_01_0_1 1 0 1 NJ 860 +preplace netloc vin3_23_0_1 1 0 1 NJ 880 +preplace netloc zynq_ultra_ps_e_M_AXI_HPM0_LPD 1 0 2 40 20 670 +levelinfo -pg 1 0 360 880 1080 1120 +pagesize -pg 1 -db -bbox -sgen -170 0 1240 1530 +" +} +{ + "da_axi4_cnt":"4", + "da_board_cnt":"1" +} diff --git a/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ui/bd_e4e34314.ui b/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ui/bd_e4e34314.ui new file mode 100644 index 0000000..575c8a4 --- /dev/null +++ b/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ui/bd_e4e34314.ui @@ -0,0 +1,28 @@ +{ + "ActiveEmotionalView":"Default View", + "Default View_ScaleFactor":"1.0", + "Default View_TopLeft":"-578,-657", + "ExpandedHierarchyInLayout":"", + "guistr":"# # String gsaved with Nlview 7.7.1 2023-07-26 3bc4126617 VDI=43 GEI=38 GUI=JA:21.0 TLS +# -string -flagsOSRD +preplace port s_axi -pg 1 -lvl 0 -x 0 -y -270 -defaultsOSRD +preplace port spi -pg 1 -lvl 3 -x 740 -y -250 -defaultsOSRD +preplace port port-id_s_axi_aclk -pg 1 -lvl 0 -x 0 -y -250 -defaultsOSRD +preplace port port-id_s_axi_aresetn -pg 1 -lvl 0 -x 0 -y -230 -defaultsOSRD +preplace port port-id_active -pg 1 -lvl 3 -x 740 -y -230 -defaultsOSRD +preplace port port-id_irq -pg 1 -lvl 3 -x 740 -y -320 -defaultsOSRD +preplace inst axi_spi_engine -pg 1 -lvl 1 -x 340 -y -240 -defaultsOSRD +preplace inst spi_engine_execution -pg 1 -lvl 2 -x 600 -y -240 -defaultsOSRD +preplace netloc axi_spi_engine_irq 1 1 2 480J -320 NJ +preplace netloc axi_spi_engine_spi_resetn 1 1 1 N -220 +preplace netloc s_axi_aclk_0_1 1 0 2 200 -150 490J +preplace netloc s_axi_aresetn_1 1 0 1 NJ -230 +preplace netloc spi_engine_execution_active 1 2 1 NJ -230 +preplace netloc Conn1 1 0 1 NJ -270 +preplace netloc Conn2 1 2 1 NJ -250 +preplace netloc axi_spi_engine_spi_engine_ctrl 1 1 1 N -260 +levelinfo -pg 1 0 340 600 740 +pagesize -pg 1 -db -bbox -sgen -150 -630 840 180 +" +} +0 diff --git a/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ui/bd_ea40ff00.ui b/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ui/bd_ea40ff00.ui new file mode 100644 index 0000000..3600602 --- /dev/null +++ b/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ui/bd_ea40ff00.ui @@ -0,0 +1,26 @@ +{ + "ActiveEmotionalView":"Default View", + "Default View_ScaleFactor":"1.0", + "Default View_TopLeft":"-578,-657", + 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+levelinfo -pg 1 0 340 590 710 +pagesize -pg 1 -db -bbox -sgen -150 -630 810 180 +" +} + diff --git a/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/ip/cmpy_18x8/cmpy_18x8.xci b/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/ip/cmpy_18x8/cmpy_18x8.xci new file mode 100644 index 0000000..0e08d98 --- /dev/null +++ b/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/ip/cmpy_18x8/cmpy_18x8.xci @@ -0,0 +1,213 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "cmpy_18x8", + "component_reference": "xilinx.com:ip:cmpy:6.0", + "ip_revision": "24", + "gen_directory": "../../../../dj_47dr_lmx.gen/sources_1/ip/cmpy_18x8", + "parameters": { + "component_parameters": { + "Component_Name": [ { "value": "cmpy_18x8", "resolve_type": "user", "usage": "all" } ], + "APortWidth": [ { "value": "18", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "HasATLAST": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "HasATUSER": [ { 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} ], + "probe_out4": [ { "direction": "out", "size_left": "3", "size_right": "0" } ] + }, + "interfaces": { + "signal_clock": { + "vlnv": "xilinx.com:signal:clock:1.0", + "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", + "mode": "slave", + "parameters": { + "FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ], + "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "CLK": [ { "physical_name": "clk" } ] + } + } + } + } + } +} \ No newline at end of file diff --git a/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/new/system_top.v b/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/new/system_top.v new file mode 100644 index 0000000..6af765c --- /dev/null +++ b/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/new/system_top.v @@ -0,0 +1,716 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 03/15/2022 08:34:01 PM +// Design Name: +// Module Name: system_top +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module system_top +( + // ************************************************************************* + // *************************** Clocks and SYSREF *************************** + // ************************************************************************* + // adc clock + input adc1_clk_in_p , + input adc1_clk_in_n , + input adc2_clk_in_p , + input adc2_clk_in_n , + // dac clock + input dac0_clk_in_p , + input dac0_clk_in_n , + input dac2_clk_in_p , + input dac2_clk_in_n , + // sysref for rf + input rf_sysref_p , + input rf_sysref_n , + // sysref for pl + input pl_sysref_p , + input pl_sysref_n , + // fpga clock + input pl_refclk_p , + input pl_refclk_n , + // ************************************************************************* + // ******************************** RF-DAC ********************************* + // ************************************************************************* + input adc0_01_in_p , + input adc0_01_in_n , + input adc0_23_in_p , + input adc0_23_in_n , + input adc1_01_in_p , + input adc1_01_in_n , + input adc1_23_in_p , + input adc1_23_in_n , + input adc2_01_in_p , + input adc2_01_in_n , + input adc2_23_in_p , + input adc2_23_in_n , + input adc3_01_in_p , + input adc3_01_in_n , + input adc3_23_in_p , + input adc3_23_in_n , + // ************************************************************************* + // ******************************** RF-DAC ********************************* + // ************************************************************************* + output dac00_out_p , + output dac00_out_n , + output dac02_out_p , + output dac02_out_n , + output dac10_out_p , + output dac10_out_n , + output dac12_out_p , + output dac12_out_n , + output dac20_out_p , + output dac20_out_n , + output dac22_out_p , + output dac22_out_n , + output dac30_out_p , + output dac30_out_n , + output dac32_out_p , + output dac32_out_n , + // ************************************************************************* + // ***************************** SPI Interface ***************************** + // ************************************************************************* + // lmk04828 + output lmk_spi_sck , + output lmk_spi_cs , + inout lmk_spi_mosi , + input lmk_spi_miso , + // lmx2594-adc + output lmx_adc_spi_sck , + output lmx_adc_spi_cs , + inout lmx_adc_spi_mosi , + input lmx_adc_spi_miso , + // lmx2594-dac + output lmx_dac_spi_sck , + output lmx_dac_spi_cs , + inout lmx_dac_spi_mosi , + input lmx_dac_spi_miso +); + + +//////////////////////////////////////////////////////////////////////////////// +//////////////////////////// Block Design Interface //////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +wire ps_clk0; +wire sys_clk; +wire sys_rstn; + +// spi interface +wire spi_sclk ; +wire [2:0] spi_cs ; +reg spi_sdi ; +wire spi_sdo ; +wire spi_sdo_t ; +wire spi_three_wire; +wire spi_active ; + +assign lmk_spi_sck = spi_sclk; +assign lmk_spi_cs = spi_cs[0]; +assign lmk_spi_mosi = spi_sdo_t ? 1'bz : spi_sdo; + +assign lmx_adc_spi_sck = spi_sclk; +assign lmx_adc_spi_cs = spi_cs[1]; +assign lmx_adc_spi_mosi = spi_sdo_t ? 1'bz : spi_sdo; + +assign lmx_dac_spi_sck = spi_sclk; +assign lmx_dac_spi_cs = spi_cs[2]; +assign lmx_dac_spi_mosi = spi_sdo_t ? 1'bz : spi_sdo; + +always @(*) begin + case (spi_cs) + 3'b110: spi_sdi = spi_three_wire ? lmk_spi_mosi : lmk_spi_miso; + 3'b101: spi_sdi = spi_three_wire ? lmx_adc_spi_mosi : lmx_adc_spi_miso; + 3'b011: spi_sdi = spi_three_wire ? lmx_dac_spi_mosi : lmx_dac_spi_miso; + default: spi_sdi = 1'bz; + endcase +end + +// ----------------------------------------------------------------------------- +// ADC Tile & Channel Mapping (Dual RF-ADC) +// ----------------------------------------------------------------------------- +// m00_axis adc00 adc tile 224 (adc0), channel 0 +// m01_axis adc01 adc tile 224 (adc0), channel 1 +// m02_axis adc02 adc tile 224 (adc0), channel 2 +// m03_axis adc03 adc tile 224 (adc0), channel 3 +// ----------------------------------------------------------------------------- +// m10_axis adc10 adc tile 225 (adc1), channel 0 +// m11_axis adc11 adc tile 225 (adc1), channel 1 +// m12_axis adc12 adc tile 225 (adc1), channel 2 +// m13_axis adc13 adc tile 225 (adc1), channel 3 +// ----------------------------------------------------------------------------- +// m20_axis adc20 adc tile 226 (adc2), channel 0 +// m21_axis adc21 adc tile 226 (adc2), channel 1 +// m22_axis adc22 adc tile 226 (adc2), channel 2 +// m23_axis adc23 adc tile 226 (adc2), channel 3 +// ----------------------------------------------------------------------------- +// m30_axis adc30 adc tile 227 (adc3), channel 0 +// m31_axis adc31 adc tile 227 (adc3), channel 1 +// m32_axis adc32 adc tile 227 (adc3), channel 2 +// m33_axis adc33 adc tile 227 (adc3), channel 3 +// ----------------------------------------------------------------------------- +// Note: +// 1) If digital output data is set to real, only channel 0/2 is enabled; if +// digital output data is set to i/q, both channel 0/2 and 1/3 are enabled, +// since i/q data are transferred in different channels. +// 2) When modify the following wire definition, **ONLY** change the data width. +// The extra definition will be optimized automatically. +// ----------------------------------------------------------------------------- +wire [15:0] adc00_data, adc01_data; +wire adc00_data_ready, adc01_data_ready; +wire adc00_data_valid, adc01_data_valid; + +wire [15:0] adc02_data, adc03_data; +wire adc02_data_ready, adc03_data_ready; +wire adc02_data_valid, adc03_data_valid; + +wire [15:0] adc10_data, adc11_data; +wire adc10_data_ready, adc11_data_ready; +wire adc10_data_valid, adc11_data_valid; + +wire [15:0] adc12_data, adc13_data; +wire adc12_data_ready, adc13_data_ready; +wire adc12_data_valid, adc13_data_valid; + +wire [15:0] adc20_data, adc21_data; +wire adc20_data_ready, adc21_data_ready; +wire adc20_data_valid, adc21_data_valid; + +wire [15:0] adc22_data, adc23_data; +wire adc22_data_ready, adc23_data_ready; +wire adc22_data_valid, adc23_data_valid; + +wire [15:0] adc30_data, adc31_data; +wire adc30_data_ready, adc31_data_ready; +wire adc30_data_valid, adc31_data_valid; + +wire [15:0] adc32_data, adc33_data; +wire adc32_data_ready, adc33_data_ready; +wire adc32_data_valid, adc33_data_valid; + +// ----------------------------------------------------------------------------- +// DAC Tile & Channel Mapping (Dual RF-DAC) +// ----------------------------------------------------------------------------- +// s00_axis dac00 dac tile 228 (dac0), channel 0 +// s01_axis dac00 dac tile 228 (dac0), channel 1 +// s02_axis dac02 dac tile 228 (dac0), channel 2 +// s03_axis dac02 dac tile 228 (dac0), channel 3 +// ----------------------------------------------------------------------------- +// s10_axis dac10 dac tile 229 (dac1), channel 0 +// s11_axis dac10 dac tile 229 (dac1), channel 1 +// s12_axis dac12 dac tile 229 (dac1), channel 2 +// s13_axis dac12 dac tile 229 (dac1), channel 3 +// ----------------------------------------------------------------------------- +// s20_axis dac20 dac tile 230 (dac2), channel 0 +// s21_axis dac20 dac tile 230 (dac2), channel 1 +// s22_axis dac22 dac tile 230 (dac2), channel 2 +// s23_axis dac22 dac tile 230 (dac2), channel 3 +// ----------------------------------------------------------------------------- +// s30_axis dac30 dac tile 231 (dac3), channel 0 +// s31_axis dac30 dac tile 231 (dac3), channel 1 +// s32_axis dac32 dac tile 231 (dac3), channel 2 +// s33_axis dac32 dac tile 231 (dac3), channel 3 +// ----------------------------------------------------------------------------- +// Note: +// 1) In most single-band cases, only channel 0/2 is enabled since i/q data are +// transferred in one signle channel; when multi-band is used, multiple digital +// channel may be enabled. +// 2) When modify the following wire definition, **ONLY** change the data width. +// The extra definition will be optimized automatically. +// ----------------------------------------------------------------------------- +wire [31:0] dac00_data, dac01_data; +wire dac00_data_ready, dac01_data_ready; +wire dac00_data_valid, dac01_data_valid; + +wire [31:0] dac02_data, dac03_data; +wire dac02_data_ready, dac03_data_ready; +wire dac02_data_valid, dac03_data_valid; + +wire [31:0] dac10_data, dac11_data; +wire dac10_data_ready, dac11_data_ready; +wire dac10_data_valid, dac11_data_valid; + +wire [31:0] dac12_data, dac13_data; +wire dac12_data_ready, dac13_data_ready; +wire dac12_data_valid, dac13_data_valid; + +wire [31:0] dac20_data, dac21_data; +wire dac20_data_ready, dac21_data_ready; +wire dac20_data_valid, dac21_data_valid; + +wire [31:0] dac22_data, dac23_data; +wire dac22_data_ready, dac23_data_ready; +wire dac22_data_valid, dac23_data_valid; + +wire [31:0] dac30_data, dac31_data; +wire dac30_data_ready, dac31_data_ready; +wire dac30_data_valid, dac31_data_valid; + +wire [31:0] dac32_data, dac33_data; +wire dac32_data_ready, dac33_data_ready; +wire dac32_data_valid, dac33_data_valid; + +system_bd_wrapper u_system_bd_wrapper +( + // ************************************************************************* + // ********************* PL SYSREF & Reference Clocks ********************** + // ************************************************************************* + .ps_clk0 (ps_clk0 ), + + .pl_clk_clk_p (pl_refclk_p ), + .pl_clk_clk_n (pl_refclk_n ), + + .pl_sysref_clk_p (pl_sysref_p ), + .pl_sysref_clk_n (pl_sysref_n ), + + .sys_clk (sys_clk ), + .sys_rstn (sys_rstn ), + + // ************************************************************************* + // ********************* RF SYSREF & Reference Clocks ********************** + // ************************************************************************* + .spi_sclk (spi_sclk ), + .spi_cs (spi_cs ), + .spi_sdi (spi_sdi ), + .spi_sdo (spi_sdo ), + .spi_sdo_t (spi_sdo_t ), + .spi_three_wire (spi_three_wire ), + .spi_active (spi_active ), + + // ************************************************************************* + // ********************* RF SYSREF & Reference Clocks ********************** + // ************************************************************************* + // rf sysref + .sysref_in_diff_p (rf_sysref_p ), // input sysref_in_diff_p + .sysref_in_diff_n (rf_sysref_n ), // input sysref_in_diff_n + + // ------------------------------------------------------------------------- + // RF ADC Reference Clocks Mapping + // ------------------------------------------------------------------------- + // adc0_clk_clk adc tile 224 (adc0) ref clock input, nc on borad + // adc1_clk_clk adc tile 225 (adc1) ref clock input, from lmk04828 + // adc2_clk_clk adc tile 226 (adc2) ref clock input, from sma + // adc3_clk_clk adc tile 227 (adc3) ref clock input, nc on borad + // clk_adc0 adc tile 224 (adc0) clock output + // clk_adc1 adc tile 225 (adc1) clock output + // clk_adc2 adc tile 226 (adc2) clock output + // clk_adc3 adc tile 227 (adc3) clock output + // ------------------------------------------------------------------------- + // Note: + // When modify the following wire connections, **ONLY** uncomment the needed + // ports and comment the not-needed ones. + // ------------------------------------------------------------------------- + // .adc1_clk_clk_p (adc1_clk_in_p ), // input adc1_clk_clk_p + // .adc1_clk_clk_n (adc1_clk_in_n ), // input adc1_clk_clk_n + .adc2_clk_clk_p (adc2_clk_in_p ), // input adc2_clk_clk_p + .adc2_clk_clk_n (adc2_clk_in_n ), // input adc2_clk_clk_n + .clk_adc0 ( ), // output clk_adc0 + .clk_adc1 ( ), // output clk_adc1 + .clk_adc2 ( ), // output clk_adc2 + .clk_adc3 ( ), // output clk_adc3 + + // ------------------------------------------------------------------------- + // RF DAC Reference Clocks Mapping + // ------------------------------------------------------------------------- + // dac0_clk_clk dac tile 228 (dac0) ref clock input, from lmk04828 + // dac1_clk_clk dac tile 229 (dac1) ref clock input, none for zu48dr + // dac2_clk_clk dac tile 230 (dac2) ref clock input, from sma + // dac3_clk_clk dac tile 231 (dac3) ref clock input, none for zu48dr + // clk_dac0 dac tile 228 (dac0) clock output + // clk_dac1 dac tile 229 (dac1) clock output + // clk_dac2 dac tile 230 (dac2) clock output + // clk_dac3 dac tile 231 (dac3) clock output + // ------------------------------------------------------------------------- + // Note: + // When modify the following wire connections, **ONLY** uncomment the needed + // ports and comment the not-needed ones. + // ------------------------------------------------------------------------- + // .dac0_clk_clk_p (dac0_clk_in_p ), // input dac0_clk_clk_p + // .dac0_clk_clk_n (dac0_clk_in_n ), // input dac0_clk_clk_n + .dac2_clk_clk_p (dac2_clk_in_p ), // input dac2_clk_clk_p + .dac2_clk_clk_n (dac2_clk_in_n ), // input dac2_clk_clk_n + .clk_dac0 ( ), // output clk_dac0 + .clk_dac1 ( ), // output clk_dac1 + .clk_dac2 ( ), // output clk_dac2 + .clk_dac3 ( ), // output clk_dac3 + + // ************************************************************************* + // *********** RF-ADC Tile 224 (adc0) Digital & Analog Interface *********** + // ************************************************************************* + // fabric clock (axi4-stream clock) + .m0_axis_aclk (sys_clk ), // input m0_axis_aclk + .m0_axis_aresetn (sys_rstn ), // input m0_axis_aresetn + + // channel 0 data + .m00_axis_tdata (adc00_data ), // output [15:0]m00_axis_tdata + .m00_axis_tready (adc00_data_ready ), // input m00_axis_tready + .m00_axis_tvalid (adc00_data_valid ), // output m00_axis_tvalid + // channel 1 data + .m01_axis_tdata (adc01_data ), // output [15:0]m01_axis_tdata + .m01_axis_tready (adc01_data_ready ), // input m01_axis_tready + .m01_axis_tvalid (adc01_data_valid ), // output m01_axis_tvalid + // analog input signal, J3 on board + .vin0_01_v_p (adc0_01_in_p ), // input vin0_01_v_p + .vin0_01_v_n (adc0_01_in_n ), // input vin0_01_v_n + + // channel 2 data + .m02_axis_tdata (adc02_data ), // output [15:0]m02_axis_tdata + .m02_axis_tready (adc02_data_ready ), // input m02_axis_tready + .m02_axis_tvalid (adc02_data_valid ), // output m02_axis_tvalid + // channel 3 data + .m03_axis_tdata (adc03_data ), // output [15:0]m03_axis_tdata + .m03_axis_tready (adc03_data_ready ), // input m03_axis_tready + .m03_axis_tvalid (adc03_data_valid ), // output m03_axis_tvalid + // analog input signal, J5 on board + .vin0_23_v_p (adc0_23_in_p ), // input vin0_23_v_p + .vin0_23_v_n (adc0_23_in_n ), // input vin0_23_v_n + + // ************************************************************************* + // *********** RF-ADC Tile 225 (adc1) Digital & Analog Interface *********** + // ************************************************************************* + // fabric clock (axi4-stream clock) + .m1_axis_aclk (sys_clk ), // input m1_axis_aclk + .m1_axis_aresetn (sys_rstn ), // input m1_axis_aresetn + + // channel 0 data + .m10_axis_tdata (adc10_data ), // output [15:0]m10_axis_tdata + .m10_axis_tready (adc10_data_ready ), // input m10_axis_tready + .m10_axis_tvalid (adc10_data_valid ), // output m10_axis_tvalid + // channel 1 data + .m11_axis_tdata (adc11_data ), // output [15:0]m11_axis_tdata + .m11_axis_tready (adc11_data_ready ), // input m11_axis_tready + .m11_axis_tvalid (adc11_data_valid ), // output m11_axis_tvalid + // analog input signal, J6 on board + .vin1_01_v_p (adc1_01_in_p ), // input vin1_01_v_p + .vin1_01_v_n (adc1_01_in_n ), // input vin1_01_v_n + + // channel 2 data + .m12_axis_tdata (adc12_data ), // output [15:0]m12_axis_tdata + .m12_axis_tready (adc12_data_ready ), // input m12_axis_tready + .m12_axis_tvalid (adc12_data_valid ), // output m12_axis_tvalid + // channel 3 data + .m13_axis_tdata (adc13_data ), // output [15:0]m13_axis_tdata + .m13_axis_tready (adc13_data_ready ), // input m13_axis_tready + .m13_axis_tvalid (adc13_data_valid ), // output m13_axis_tvalid + // analog input signal, J7 on board + .vin1_23_v_p (adc1_23_in_p ), // input vin1_23_v_p + .vin1_23_v_n (adc1_23_in_n ), // input vin1_23_v_n + + // ************************************************************************* + // *********** RF-ADC Tile 226 (adc2) Digital & Analog Interface *********** + // ************************************************************************* + // fabric clock (axi4-stream clock) + .m2_axis_aclk (sys_clk ), // input m2_axis_aclk + .m2_axis_aresetn (sys_rstn ), // input m2_axis_aresetn + + // channel 0 data + .m20_axis_tdata (adc20_data ), // output [15:0]m20_axis_tdata + .m20_axis_tready (adc20_data_ready ), // input m20_axis_tready + .m20_axis_tvalid (adc20_data_valid ), // output m20_axis_tvalid + // channel 1 data + .m21_axis_tdata (adc21_data ), // output [15:0]m21_axis_tdata + .m21_axis_tready (adc21_data_ready ), // input m21_axis_tready + .m21_axis_tvalid (adc21_data_valid ), // output m21_axis_tvalid + // analog input signal, J8 on board + .vin2_01_v_p (adc2_01_in_p ), // input vin2_01_v_p + .vin2_01_v_n (adc2_01_in_n ), // input vin2_01_v_n + + // channel 2 data + .m22_axis_tdata (adc22_data ), // output [15:0]m22_axis_tdata + .m22_axis_tready (adc22_data_ready ), // input m22_axis_tready + .m22_axis_tvalid (adc22_data_valid ), // output m22_axis_tvalid + // channel 3 data + .m23_axis_tdata (adc23_data ), // output [15:0]m23_axis_tdata + .m23_axis_tready (adc23_data_ready ), // input m23_axis_tready + .m23_axis_tvalid (adc23_data_valid ), // output m23_axis_tvalid + // analog input signal, J9 on board + .vin2_23_v_p (adc2_23_in_p ), // input vin2_23_v_p + .vin2_23_v_n (adc2_23_in_n ), // input vin2_23_v_n + + // ************************************************************************* + // *********** RF-ADC Tile 227 (adc3) Digital & Analog Interface *********** + // ************************************************************************* + // fabric clock (axi4-stream clock) + .m3_axis_aclk (sys_clk ), // input m3_axis_aclk + .m3_axis_aresetn (sys_rstn ), // input m3_axis_aresetn + + // channel 0 data + .m30_axis_tdata (adc30_data ), // output [15:0]m30_axis_tdata + .m30_axis_tready (adc30_data_ready ), // input m30_axis_tready + .m30_axis_tvalid (adc30_data_valid ), // output m30_axis_tvalid + // channel 1 data + .m31_axis_tdata (adc31_data ), // output [15:0]m31_axis_tdata + .m31_axis_tready (adc31_data_ready ), // input m31_axis_tready + .m31_axis_tvalid (adc31_data_valid ), // output m31_axis_tvalid + // analog input signal, J10 on board + .vin3_01_v_p (adc3_01_in_p ), // input vin3_01_v_p + .vin3_01_v_n (adc3_01_in_n ), // input vin3_01_v_n + + // channel 2 data + .m32_axis_tdata (adc32_data ), // output [15:0]m32_axis_tdata + .m32_axis_tready (adc32_data_ready ), // input m32_axis_tready + .m32_axis_tvalid (adc32_data_valid ), // output m32_axis_tvalid + // channel 3 data + .m33_axis_tdata (adc33_data ), // output [15:0]m33_axis_tdata + .m33_axis_tready (adc33_data_ready ), // input m33_axis_tready + .m33_axis_tvalid (adc33_data_valid ), // output m33_axis_tvalid + // analog input signal, J12 on board + .vin3_23_v_p (adc3_23_in_p ), // input vin3_23_v_p + .vin3_23_v_n (adc3_23_in_n ), // input vin3_23_v_n + + // ************************************************************************* + // *********** RF-DAC Tile 228 (dac0) Digital & Analog Interface *********** + // ************************************************************************* + // fabric clock (axi4-stream clock) + .s0_axis_aclk (sys_clk ), // input s0_axis_aclk + .s0_axis_aresetn (sys_rstn ), // input s0_axis_aresetn + + // channel 0 data + .s00_axis_tdata (dac00_data ), // input [31:0]s00_axis_tdata + .s00_axis_tready (dac00_data_ready ), // output s00_axis_tready + .s00_axis_tvalid (dac00_data_valid ), // input s00_axis_tvalid + // channel 1 data + // .s01_axis_tdata (dac01_data ), // input [31:0]s01_axis_tdata + // .s01_axis_tready (dac01_data_ready ), // output s01_axis_tready + // .s01_axis_tvalid (dac01_data_valid ), // input s01_axis_tvalid + // analog output signal, J14 on board + .vout00_v_p (dac00_out_p ), // output vout00_v_p + .vout00_v_n (dac00_out_n ), // output vout00_v_n + + // channel 2 data + .s02_axis_tdata (dac02_data ), // input [31:0]s02_axis_tdata + .s02_axis_tready (dac02_data_ready ), // output s02_axis_tready + .s02_axis_tvalid (dac02_data_valid ), // input s02_axis_tvalid + // channel 3 data + // .s03_axis_tdata (dac03_data ), // input [31:0]s03_axis_tdata + // .s03_axis_tready (dac03_data_ready ), // output s03_axis_tready + // .s03_axis_tvalid (dac03_data_valid ), // input s03_axis_tvalid + // analog output signal, J16 on board + .vout02_v_p (dac02_out_p ), // output vout02_v_p + .vout02_v_n (dac02_out_n ), // output vout02_v_n + + // ************************************************************************* + // *********** RF-DAC Tile 229 (dac1) Digital & Analog Interface *********** + // ************************************************************************* + // fabric clock (axi4-stream clock) + .s1_axis_aclk (sys_clk ), // input s1_axis_aclk + .s1_axis_aresetn (sys_rstn ), // input s1_axis_aresetn + + // channel 0 data + .s10_axis_tdata (dac10_data ), // input [31:0]s10_axis_tdata + .s10_axis_tready (dac10_data_ready ), // output s10_axis_tready + .s10_axis_tvalid (dac10_data_valid ), // input s10_axis_tvalid + // channel 1 data + // .s11_axis_tdata (dac11_data ), // input [31:0]s11_axis_tdata + // .s11_axis_tready (dac11_data_ready ), // output s11_axis_tready + // .s11_axis_tvalid (dac11_data_valid ), // input s11_axis_tvalid + // analog output signal, J17 on board + .vout10_v_p (dac10_out_p ), // output vout10_v_p + .vout10_v_n (dac10_out_n ), // output vout10_v_n + + // channel 2 data + .s12_axis_tdata (dac12_data ), // input [31:0]s12_axis_tdata + .s12_axis_tready (dac12_data_ready ), // output s12_axis_tready + .s12_axis_tvalid (dac12_data_valid ), // input s12_axis_tvalid + // channel 3 data + // .s13_axis_tdata (dac13_data ), // input [31:0]s13_axis_tdata + // .s13_axis_tready (dac13_data_ready ), // output s13_axis_tready + // .s13_axis_tvalid (dac13_data_valid ), // input s13_axis_tvalid + // analog output signal, J18 on board + .vout12_v_p (dac12_out_p ), // output vout12_v_p + .vout12_v_n (dac12_out_n ), // output vout12_v_n + + // ************************************************************************* + // *********** RF-DAC Tile 230 (dac2) Digital & Analog Interface *********** + // ************************************************************************* + // fabric clock (axi4-stream clock) + .s2_axis_aclk (sys_clk ), // input s2_axis_aclk + .s2_axis_aresetn (sys_rstn ), // input s2_axis_aresetn + + // channel 0 data + .s20_axis_tdata (dac20_data ), // input [31:0]s20_axis_tdata + .s20_axis_tready (dac20_data_ready ), // output s20_axis_tready + .s20_axis_tvalid (dac20_data_valid ), // input s20_axis_tvalid + // channel 1 data + // .s21_axis_tdata (dac21_data ), // input [31:0]s21_axis_tdata + // .s21_axis_tready (dac21_data_ready ), // output s21_axis_tready + // .s21_axis_tvalid (dac21_data_valid ), // input s21_axis_tvalid + // analog output signal, J19 on board + .vout20_v_p (dac20_out_p ), // output vout20_v_p + .vout20_v_n (dac20_out_n ), // output vout20_v_n + + // channel 2 data + .s22_axis_tdata (dac22_data ), // input [31:0]s22_axis_tdata + .s22_axis_tready (dac22_data_ready ), // output s22_axis_tready + .s22_axis_tvalid (dac22_data_valid ), // input s22_axis_tvalid + // channel 3 data + // .s23_axis_tdata (dac23_data ), // input [31:0]s23_axis_tdata + // .s23_axis_tready (dac23_data_ready ), // output s23_axis_tready + // .s23_axis_tvalid (dac23_data_valid ), // input s23_axis_tvalid + // analog output signal, J20 on board + .vout22_v_p (dac22_out_p ), // output vout22_v_p + .vout22_v_n (dac22_out_n ), // output vout22_v_n + + // ************************************************************************* + // *********** RF-DAC Tile 231 (dac3) Digital & Analog Interface *********** + // ************************************************************************* + // fabric clock (axi4-stream clock) + .s3_axis_aclk (sys_clk ), // input s3_axis_aclk + .s3_axis_aresetn (sys_rstn ), // input s3_axis_aresetn + + // channel 0 data + .s30_axis_tdata (dac30_data ), // input [31:0]s30_axis_tdata + .s30_axis_tready (dac30_data_ready ), // output s30_axis_tready + .s30_axis_tvalid (dac30_data_valid ), // input s30_axis_tvalid + // channel 1 data + // .s31_axis_tdata (dac31_data ), // input [31:0]s31_axis_tdata + // .s31_axis_tready (dac31_data_ready ), // output s31_axis_tready + // .s31_axis_tvalid (dac31_data_valid ), // input s31_axis_tvalid + // analog output signal, J21 on board + .vout30_v_p (dac30_out_p ), // output vout30_v_p + .vout30_v_n (dac30_out_n ), // output vout30_v_n + + // channel 2 data + .s32_axis_tdata (dac32_data ), // input [31:0]s32_axis_tdata + .s32_axis_tready (dac32_data_ready ), // output s32_axis_tready + .s32_axis_tvalid (dac32_data_valid ), // input s32_axis_tvalid + // channel 3 data + // .s33_axis_tdata (dac33_data ), // input [31:0]s33_axis_tdata + // .s33_axis_tready (dac33_data_ready ), // output s33_axis_tready + // .s33_axis_tvalid (dac33_data_valid ), // input s33_axis_tvalid + // analog output signal, J23 on board + .vout32_v_p (dac32_out_p ), // output vout32_v_p + .vout32_v_n (dac32_out_n ) // output vout32_v_n +); + + +//////////////////////////////////////////////////////////////////////////////// +////////////////////////////////// Tx Signal /////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +// tx signal mapping +wire [15:0] tx_data_i, tx_data_q; + +assign dac00_data = {tx_data_q, tx_data_i}; +assign dac02_data = {tx_data_q, tx_data_i}; +assign dac10_data = {tx_data_q, tx_data_i}; +assign dac12_data = {tx_data_q, tx_data_i}; +assign dac20_data = {tx_data_q, tx_data_i}; +assign dac22_data = {tx_data_q, tx_data_i}; +assign dac30_data = {tx_data_q, tx_data_i}; +assign dac32_data = {tx_data_q, tx_data_i}; + +// transimitter logic +wire [ 1:0] waveform_sel; +wire sweep_on ; +wire [31:0] freq_set ; +wire [ 1:0] iq_sel ; +wire [ 3:0] bb_rshift ; + +tx_qpsk #( + .DATA_WIDTH (16), + .BIT_DATA (1024'b0000000100100010000011001001101000010010101000011110101110101101101100000000110000011011001100001010110101110001101111110001000111100111101101101000000010100001011010101000111110111100100101100000100110010001010001101101110000001111000111011111110010000110001011011101000011010101100111100101101100100000100010010011000000101100010100111011001110001011111101010001011101101011000011001101101010000011101001111010011010100100111000001111100111001101111010001010101101111100001001110100011101011111011010010000100001010010101100011100111111101100001000110100111001001111000011011101100011000111101111101001001010000001101000110010111010010110100010001011001101001010010001100001110110111100000101110010101110011101110111001100111010101110111101100101000100110110001000011100101111100101001100110010101010011111100110001101011110011010110100110001001011100001011110101010101111111101000001010100101111000101011110111010100110111001000111000111111111100000001110000111111011100010011111000110011111010110010110010010010000000001), + .BIT_DATA_LEN (1024), + .CLK_FREQ (245_760_000) +) u_tx_qpsk +( + .clk (sys_clk ), // input clk + .rst (~sys_rstn ), // input rst + .tx_data_i (tx_data_i ), // output [15:0] tx_data_i + .tx_data_q (tx_data_q ), // output [15:0] tx_data_q + // debug ports + .waveform_sel (waveform_sel[1:0] ), // input [ 1:0] waveform_sel + .sweep_on (sweep_on ), // input sweep_on + .freq_set (freq_set ), // input [31:0] freq_set + .iq_sel (iq_sel ), // input [ 1:0] iq_sel + .bb_rshift (bb_rshift ) // input [ 3:0] bb_rshift +); + +//////////////////////////////////////////////////////////////////////////////// +////////////////////////////////// Rx Signal /////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +// rx signal mapping +wire [15:0] rx_ch1_i, rx_ch1_q; +wire [15:0] rx_ch2_i, rx_ch2_q; +wire [15:0] rx_ch3_i, rx_ch3_q; +wire [15:0] rx_ch4_i, rx_ch4_q; +wire [15:0] rx_ch5_i, rx_ch5_q; +wire [15:0] rx_ch6_i, rx_ch6_q; +wire [15:0] rx_ch7_i, rx_ch7_q; +wire [15:0] rx_ch8_i, rx_ch8_q; + +assign rx_ch1_i = adc00_data; +assign rx_ch1_q = adc01_data; +assign rx_ch2_i = adc02_data; +assign rx_ch2_q = adc03_data; +assign rx_ch3_i = adc10_data; +assign rx_ch3_q = adc11_data; +assign rx_ch4_i = adc12_data; +assign rx_ch4_q = adc13_data; +assign rx_ch5_i = adc20_data; +assign rx_ch5_q = adc21_data; +assign rx_ch6_i = adc22_data; +assign rx_ch6_q = adc23_data; +assign rx_ch7_i = adc30_data; +assign rx_ch7_q = adc31_data; +assign rx_ch8_i = adc32_data; +assign rx_ch8_q = adc33_data; + +// receiver logic + + +//////////////////////////////////////////////////////////////////////////////// +//////////////////////////////// ILAs and VIOs ///////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +ila_adc u_ila_adc +( + .clk (sys_clk ), // input wire clk + .probe0 (rx_ch1_i ), // input wire [15:0] probe0 + .probe1 (rx_ch1_q ), // input wire [15:0] probe1 + .probe2 (rx_ch2_i ), // input wire [15:0] probe2 + .probe3 (rx_ch2_q ), // input wire [15:0] probe3 + .probe4 (rx_ch3_i ), // input wire [15:0] probe4 + .probe5 (rx_ch3_q ), // input wire [15:0] probe5 + .probe6 (rx_ch4_i ), // input wire [15:0] probe6 + .probe7 (rx_ch4_q ), // input wire [15:0] probe7 + .probe8 (rx_ch5_i ), // input wire [15:0] probe8 + .probe9 (rx_ch5_q ), // input wire [15:0] probe9 + .probe10(rx_ch6_i ), // input wire [15:0] probe10 + .probe11(rx_ch6_q ), // input wire [15:0] probe11 + .probe12(rx_ch7_i ), // input wire [15:0] probe12 + .probe13(rx_ch7_q ), // input wire [15:0] probe13 + .probe14(rx_ch8_i ), // input wire [15:0] probe14 + .probe15(rx_ch8_q ) // input wire [15:0] probe15 +); + +ila_dac u_ila_dac +( + .clk (sys_clk ), // input wire clk + .probe0 (tx_data_i ), // input wire [15:0] probe0 + .probe1 (tx_data_q ) // input wire [15:0] probe1 +); + +vio_manual_ctrl u_vio_manual_ctrl +( + .clk (sys_clk ), // input wire clk + .probe_out0 (waveform_sel[1:0] ), // output wire [1 : 0] probe_out0 + .probe_out1 (sweep_on ), // output wire [0 : 0] probe_out1 + .probe_out2 (freq_set[31:0] ), // output wire [31 : 0] probe_out2 + .probe_out3 (iq_sel[1:0] ), // output wire [1 : 0] probe_out3 + .probe_out4 (bb_rshift[3:0] ) // output wire [3 : 0] probe_out4 +); + +endmodule diff --git a/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/new/tx_qpsk.v b/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/new/tx_qpsk.v new file mode 100644 index 0000000..d757ea0 --- /dev/null +++ b/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/new/tx_qpsk.v @@ -0,0 +1,539 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// _ _ ____ +// | | ___ ___| |__ / ___| __ _ ___ +// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \ +// | |_| | (_) \__ \ | | | | |_| | (_| | (_) | +// \___/ \___/|___/_| |_| \____|\__,_|\___/ +// +// Create Date: 2022/03/23 20:17:56 +// Last Modified Date: 2023/03/10 15:41 +// Design Name: +// Module Name: tx_qpsk +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// 20230228-1541 - 修改不扫频、无基带频偏时 [baseband_i/q] 的数据输出，原来从 +// 乘法器引出，会导致频率为 0 时输出数据错误，现在直接从基带数据引出。 +// 20230310-1542 - 增加输入参数，发送数据更改为直接由参数输入，发送方波改为 8 +// 倍过采样，发送双音信号中 1MHz 信号的频率控制字可以根据参数中的时钟频率计 +// 算得出。 +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module tx_qpsk +#( + parameter DATA_WIDTH = 12, // need to be <= 16 + parameter BIT_DATA = 128'b00000011000010100011110010001011001110101001111101000011100010010011011010110111101100011010010111011100110010101011111110000001, // inverse pseudorandom bit sequence, [0,flip(PRSB7)] + parameter BIT_DATA_LEN = 128, + parameter SQUARE_INTERP = 8, + parameter CLK_FREQ = 245760000 // in Hertz +) +( + input clk , + input rst , + output [DATA_WIDTH-1:0] tx_data_i , + output [DATA_WIDTH-1:0] tx_data_q , + // debug ports + input [ 1:0] waveform_sel , + input sweep_on , + input [31:0] freq_set , + input [ 1:0] iq_sel , + input [ 3:0] bb_rshift +); + +localparam RCOS_INTERP = 64; +localparam INTERP = (RCOS_INTERP > SQUARE_INTERP) ? RCOS_INTERP : SQUARE_INTERP; +localparam FREQ_WORD_1M = 64'd2**64'd32*64'd1000000/CLK_FREQ; + +//////////////////////////////////////////////////////////////////////////////// +///////////////////////////////// Data Counter ///////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +// symbol & interpolation counter +reg [$clog2(INTERP*BIT_DATA_LEN)-1 : 0] cnt = 'b0; + +always @(posedge clk) begin + if (rst) begin + cnt <= 'b0; + end + else begin + cnt <= (cnt == INTERP*BIT_DATA_LEN - 1) ? 'b0 : cnt + 16'b1; + end +end + +//////////////////////////////////////////////////////////////////////////////// +////////////////////// Root-Rasied Cosine Shaping Filter /////////////////////// +//////////////////////////////////////////////////////////////////////////////// +// address +reg [$clog2(BIT_DATA_LEN)-1 : 0] hrc_data_addr_i = 'b0; +reg [$clog2(BIT_DATA_LEN)-1 : 0] hrc_data_addr_q = 'b1; + +always @(posedge clk) begin + if (rst) begin + hrc_data_addr_i <= 'b0; + hrc_data_addr_q <= 'b1; + end + else begin + hrc_data_addr_i <= {cnt[$clog2(RCOS_INTERP) +: ($clog2(BIT_DATA_LEN)-1)],1'b0}; + hrc_data_addr_q <= {cnt[$clog2(RCOS_INTERP) +: ($clog2(BIT_DATA_LEN)-1)],1'b1}; + end +end + +// bit data +reg hrc_data_i = 'b0; +reg hrc_data_q = 'b0; + +always @(posedge clk) begin + if (rst) begin + hrc_data_i <= 'b0; + hrc_data_q <= 'b0; + end + else begin + hrc_data_i <= BIT_DATA[hrc_data_addr_i]; + hrc_data_q <= BIT_DATA[hrc_data_addr_q]; + end +end + +// polarization +wire [ 7:0] hrc_data_polar_i; +wire [ 7:0] hrc_data_polar_q; + +assign hrc_data_polar_i = {{7{hrc_data_i}},1'b1}; +assign hrc_data_polar_q = {{7{hrc_data_q}},1'b1}; + +// root raised cosine shaping-filter +wire [23:0] hrc_wave_i; +wire [23:0] hrc_wave_q; + +hrc_64_12_025 u_hrc_i ( + .aclk (clk ), // input wire aclk + .s_axis_data_tvalid (~rst ), // input wire s_axis_data_tvalid + .s_axis_data_tready ( ), // output wire s_axis_data_tready + .s_axis_data_tdata (hrc_data_polar_i ), // input wire [7 : 0] s_axis_data_tdata + .m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid + .m_axis_data_tdata (hrc_wave_i ) // output wire [23 : 0] m_axis_data_tdata +); + +hrc_64_12_025 u_hrc_q ( + .aclk (clk ), // input wire aclk + .s_axis_data_tvalid (~rst ), // input wire s_axis_data_tvalid + .s_axis_data_tready ( ), // output wire s_axis_data_tready + .s_axis_data_tdata (hrc_data_polar_q ), // input wire [7 : 0] s_axis_data_tdata + .m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid + .m_axis_data_tdata (hrc_wave_q ) // output wire [23 : 0] m_axis_data_tdata +); + + +//////////////////////////////////////////////////////////////////////////////// +//////////////////////////// Square Shaping Filter ///////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +// address +reg [$clog2(BIT_DATA_LEN)-1 : 0] hsq_data_addr = 'b0; + +always @(posedge clk) begin + if (rst) begin + hsq_data_addr <= 'b0; + end + else + hsq_data_addr <= {cnt[$clog2(SQUARE_INTERP) +: $clog2(BIT_DATA_LEN)]}; +end + +// bit data +reg hsq_data = 'b0; + +always @(posedge clk) begin + if (rst) begin + hsq_data <= 'b0; + end + else begin + hsq_data <= BIT_DATA[hsq_data_addr]; + end +end + +// square shaping-filter +reg [17:0] hsq_wave_i ='b0; +reg [17:0] hsq_wave_q ='b0; + +always @(posedge clk) begin + if (rst) begin + hsq_wave_i <= 'b0; + hsq_wave_q <= 'b0; + end + else begin + hsq_wave_i <= hsq_data ? 18'b01_1111_1111_1111_1111 : 18'b10_0000_0000_0000_0001; + hsq_wave_q <= hsq_data ? 18'b10_0000_0000_0000_0001 : 18'b01_1111_1111_1111_1111; + end +end + + +//////////////////////////////////////////////////////////////////////////////// +/////////////////////////////// Two Tone Siganl //////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +// cosine wave with freq of 1 MHz +wire signed [7:0] cos_1m; +wire signed [7:0] sin_1m; + +dds_32b_8b u_dds_1m +( + .aclk (clk ), // input wire aclk + .s_axis_config_tvalid (1'b1 ), // input wire s_axis_config_tvalid + .s_axis_config_tdata (FREQ_WORD_1M[31:0] ), // input wire [31 : 0] s_axis_config_tdata + .m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid + .m_axis_data_tdata ({sin_1m,cos_1m} ) // output wire [15 : 0] m_axis_data_tdata +); + +// two-tone signal +reg signed [16:0] two_tone_wave_i = 'b0; +reg signed [16:0] two_tone_wave_q = 'b0; + +always @(posedge clk) begin + if (rst) begin + two_tone_wave_i <= 'b0; + two_tone_wave_q <= 'b0; + end + else begin + two_tone_wave_i <= 17'b0_0111_1111_1111_1111 + {cos_1m[7],cos_1m,8'd0}; + two_tone_wave_q <= 17'b0 + {sin_1m[7],sin_1m,8'd0}; + end +end + + +//////////////////////////////////////////////////////////////////////////////// +///////////////////// Waveform Selection & Hopping Control ///////////////////// +//////////////////////////////////////////////////////////////////////////////// +// baseband signal select +reg [17:0] baseband_sel_i = 'b0; +reg [17:0] baseband_sel_q = 'b0; + +always @(posedge clk) begin + if (rst) begin + baseband_sel_i <= 'b0; + baseband_sel_q <= 'b0; + end + else begin + case (waveform_sel[1:0]) + 2'd0: begin + baseband_sel_i <= {hrc_wave_i[16:0],1'b0}; + baseband_sel_q <= {hrc_wave_q[16:0],1'b0}; + end + 2'd1: begin + baseband_sel_i <= hsq_wave_i[17:0]; + baseband_sel_q <= hsq_wave_q[17:0]; + end + 2'd2: begin + baseband_sel_i <= 18'b01_1111_1111_1111_1111; + baseband_sel_q <= 18'b0; + end + 2'd3: begin + baseband_sel_i <= {two_tone_wave_i[16:0],1'b0}; + baseband_sel_q <= {two_tone_wave_q[16:0],1'b0}; + end + default: begin + baseband_sel_i <= {hrc_wave_i[16:0],1'b0}; + baseband_sel_q <= {hrc_wave_q[16:0],1'b0}; + end + endcase + end +end + +// hopping control, 3750hop/s +reg [23:0] sweep_rom_addr = 'b0; +wire [31:0] freq_sweep; + +always @(posedge clk) begin + if (rst) begin + sweep_rom_addr <= 'b0; + end + else if (sweep_on) begin + sweep_rom_addr <= sweep_rom_addr + 24'b1; + end + else begin + sweep_rom_addr <= 'b0; + end +end + +hop_rom u_sweep_rom +( + .clka (clk ), // input wire clka + .addra (sweep_rom_addr[23:16] ), // input wire [7 : 0] addra + .douta (freq_sweep ) // output wire [31 : 0] douta +); + +// choose the actual frequency word +reg [31:0] freq_word = 'b0; + +always @(posedge clk) begin + if (rst) begin + freq_word <= 'b0; + end + else if (sweep_on) begin + // frequency sweep + freq_word <= freq_sweep; + end + else begin + // normal operation + freq_word <= freq_set; + end +end + +// baseband frequency shift carrier generation +wire [ 7:0] cos_dds; +wire [ 7:0] sin_dds; +reg [ 7:0] cos = 'b0; +reg [ 7:0] sin = 'b0; + +dds_32b_8b u_dds_bb_shift ( + .aclk (clk ), // input wire aclk + .s_axis_config_tvalid (~rst ), // input wire s_axis_config_tvalid + .s_axis_config_tdata (freq_word ), // input wire [31 : 0] s_axis_config_tdata + .m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid + .m_axis_data_tdata ({sin_dds,cos_dds}) // output wire [31 : 0] m_axis_data_tdata +); + +always @(posedge clk) begin + if (rst) begin + cos <= 'b0; + sin <= 'b0; + end + else if (freq_word == 'b0) begin + // to make sure the carriers stay at the right position when freq = 0 + cos <= 8'b0111_1111; + sin <= 8'b0111_1111; + end + else begin + cos <= cos_dds; + sin <= sin_dds; + end +end + +// baseband frequency shift modulation +wire [47:0] mod_cmpy_a; +wire [15:0] mod_cmpy_b; +wire [63:0] mod_cmpy_out; + +wire [26:0] baseband_mult_i; +wire [26:0] baseband_mult_q; + +assign mod_cmpy_a = {6'b0,baseband_sel_q,6'b0,baseband_sel_i}; +assign mod_cmpy_b = {-sin,cos}; + +assign baseband_mult_i = mod_cmpy_out[58:32]; +assign baseband_mult_q = mod_cmpy_out[26: 0]; + +cmpy_18x8 u_cmpy_18x8 +( + .aclk (clk ), // input wire aclk + .s_axis_a_tvalid (1'b1 ), // input wire s_axis_a_tvalid + .s_axis_a_tdata (mod_cmpy_a ), // input wire [47 : 0] s_axis_a_tdata + .s_axis_b_tvalid (1'b1 ), // input wire s_axis_b_tvalid + .s_axis_b_tdata (mod_cmpy_b ), // input wire [15 : 0] s_axis_b_tdata + .m_axis_dout_tvalid ( ), // output wire m_axis_dout_tvalid + .m_axis_dout_tdata (mod_cmpy_out ) // output wire [63 : 0] m_axis_dout_tdata +); + +// truncate to 16-bit +reg signed [15:0] baseband_i = 'b0; +reg signed [15:0] baseband_q = 'b0; + +always @(posedge clk) begin + if (rst) begin + baseband_i <= 'b0; + baseband_q <= 'b0; + end + else begin + case (waveform_sel[1:0]) + 2'd0: begin + // scale rasied-cosine-shaped bpsk signal by 1.125 or 1.625 + baseband_i <= (sweep_on == 0 && freq_set == 0) ? (baseband_sel_i[17 -: 16] + {{3{baseband_sel_i[17]}},baseband_sel_i[17 -: 13]}) : (baseband_mult_i[25:10] + {baseband_mult_i[25],baseband_mult_i[25:11]} + {{3{baseband_mult_i[25]}},baseband_mult_i[25:13]}); + baseband_q <= (sweep_on == 0 && freq_set == 0) ? (baseband_sel_q[17 -: 16] + {{3{baseband_sel_q[17]}},baseband_sel_q[17 -: 13]}) : (baseband_mult_q[25:10] + {baseband_mult_q[25],baseband_mult_q[25:11]} + {{3{baseband_mult_q[25]}},baseband_mult_q[25:13]}); + end + 2'd1: begin + baseband_i <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_i[17 -: 16] : (baseband_mult_i[25:10] + {{2{baseband_mult_i[25]}},baseband_mult_i[25:12]}); + baseband_q <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_q[17 -: 16] : (baseband_mult_q[25:10] + {{2{baseband_mult_q[25]}},baseband_mult_q[25:12]}); + end + 2'd2: begin + baseband_i <= baseband_mult_i[24:9]; + baseband_q <= baseband_mult_q[24:9]; + end + 2'd3: begin + baseband_i <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_i[17 -: 16] : baseband_mult_i[24:9]; + baseband_q <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_q[17 -: 16] : baseband_mult_q[24:9]; + end + default: begin + // scale rasied-cosine-shaped bpsk signal by 1.125 + baseband_i <= baseband_mult_i[25:10] + {{3{baseband_mult_i[25]}},baseband_mult_i[25:13]}; + baseband_q <= baseband_mult_q[25:10] + {{3{baseband_mult_q[25]}},baseband_mult_q[25:13]}; + end + endcase + end +end + +// iq selection & baseband right shift +reg signed [15:0] baseband_data_i = 'b0; +reg signed [15:0] baseband_data_q = 'b0; + +always @(posedge clk) begin + if (rst) begin + baseband_data_i <= 'b0; + baseband_data_q <= 'b0; + end + else begin + // inphase selection + if (iq_sel[1]) begin + baseband_data_i <= baseband_i >>> bb_rshift; + end + else begin + baseband_data_i <= 'b0; + end + // quadrature selection + if (iq_sel[0]) begin + baseband_data_q <= baseband_q >>> bb_rshift; + end + else begin + baseband_data_q <= 'b0; + end + end +end + +// output data to ports +assign tx_data_i = baseband_data_i[15 -: DATA_WIDTH]; +assign tx_data_q = baseband_data_q[15 -: DATA_WIDTH]; + +endmodule + + +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2020/12/08 12:43:46 +// Design Name: +// Module Name: tb_tx_qpsk +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +// module tb_tx_qpsk; + +// reg clk = 1'b0 ; +// reg rst = 1'b1 ; +// reg tx_on = 1'b1 ; +// reg [31:0] freq_set ; +// reg [ 1:0] waveform_sel = 2'b00; +// reg [ 1:0] iq_sel = 2'b11 ; +// wire [11:0] tx_data_i ; +// wire [11:0] tx_data_q ; +// reg [ 3:0] bb_rshift = 5'b0 ; + +// tx_qpsk u_tx_qpsk +// ( +// .clk (clk ), +// .rst (rst ), +// .tx_data_i (tx_data_i ), +// .tx_data_q (tx_data_q ), +// .waveform_sel (waveform_sel ), +// .sweep_on (1'b0 ), +// // .freq_set (32'd447392426 ), +// .freq_set (32'd0 ), +// .iq_sel (iq_sel ), +// .bb_rshift (bb_rshift ) +// ); + +// initial begin +// #102 +// rst = 1'b0; +// // freq_set = 32'd873813333; +// // waveform_sel = 2'b00; +// // bb_rshift = 5'd0; +// // #5000 +// // bb_rshift = 5'd1; +// // #5000 +// // bb_rshift = 5'd2; +// // #5000 +// // bb_rshift = 5'd3; +// // #5000 +// // bb_rshift = 5'd4; +// // #5000 +// // bb_rshift = 5'd5; +// // #5000 +// // bb_rshift = 5'd6; +// // #5000 +// // bb_rshift = 5'd7; +// // #5000 +// // bb_rshift = 5'd8; +// // #5000 +// // bb_rshift = 5'd9; +// // #5000 +// // bb_rshift = 5'd14; +// // #5000 +// // bb_rshift = 5'd15; +// // #5000 +// // bb_rshift = 5'd16; +// // freq_set = 32'd0; +// // func_sel = 3'b010; +// // #7777 +// // freq_set = 32'd536870912; +// // func_sel = 3'b100; +// // #7777 +// // freq_set = 32'd0; +// // func_sel = 3'b100; +// // #7777 +// // freq_set = 32'd536870912; +// // func_sel = 3'b010; +// // #7777 +// // freq_set = 32'd0; +// // func_sel = 3'b010; +// // freq_set = 32'd536870912; +// // iq_sel = 2'b00; +// // #7777 +// // freq_set = 32'd536870912; +// // iq_sel = 2'b01; +// // #7777 +// // freq_set = 32'd536870912; +// // iq_sel = 2'b10; +// // #7777 +// // freq_set = 32'd536870912; +// // iq_sel = 2'b11; +// end + +// always #5 clk = ~clk; + +// // integer i; +// // integer w_file; + +// // initial begin +// // w_file = $fopen("D:\\qpsk_josh.txt","w"); +// // for (i = 0; i <= 35000; i = i + 1) begin +// // wait(clk); +// // #10; +// // $fdisplay(w_file,"%d %d",$signed(tx_data_i), +// // $signed(tx_data_q)); +// // if (i == 35000) begin +// // $fclose(w_file); +// // $stop; +// // end +// // end +// // end + +// endmodule diff --git a/dj_47dr_lmx/dj_47dr_lmx.srcs/utils_1/imports/synth_1/system_top.dcp b/dj_47dr_lmx/dj_47dr_lmx.srcs/utils_1/imports/synth_1/system_top.dcp new file mode 100644 index 0000000..68852d6 --- /dev/null +++ b/dj_47dr_lmx/dj_47dr_lmx.srcs/utils_1/imports/synth_1/system_top.dcp @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:b0bec5ce39d6c191c8c3a13bd0a7ee666b4cc76cb4ec23e9cedb0725f9c28129 +size 240583 diff --git a/dj_47dr_lmx/dj_47dr_lmx.xpr b/dj_47dr_lmx/dj_47dr_lmx.xpr new file mode 100644 index 0000000..7fe7419 --- /dev/null +++ b/dj_47dr_lmx/dj_47dr_lmx.xpr @@ -0,0 +1,990 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/dj_47dr_lmx/system_top.xsa b/dj_47dr_lmx/system_top.xsa new file mode 100644 index 0000000..81bf51a --- /dev/null +++ b/dj_47dr_lmx/system_top.xsa @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:85e750076cb918bc00450c2f0c85b2390ccecd94704993fe69c5d87eadf81aba +size 2183364