feat: 新增9371地检驱动工程, 9371自收发正常
This commit is contained in:
@@ -0,0 +1,69 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
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||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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||||
//
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||||
// OR
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||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module ad_mem #(
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parameter DATA_WIDTH = 16,
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parameter ADDRESS_WIDTH = 5
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) (
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input clka,
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input wea,
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input [(ADDRESS_WIDTH-1):0] addra,
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input [(DATA_WIDTH-1):0] dina,
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input clkb,
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input reb,
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input [(ADDRESS_WIDTH-1):0] addrb,
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output reg [(DATA_WIDTH-1):0] doutb
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);
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(* ram_style = "block" *)
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reg [(DATA_WIDTH-1):0] m_ram[0:((2**ADDRESS_WIDTH)-1)];
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always @(posedge clka) begin
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if (wea == 1'b1) begin
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m_ram[addra] <= dina;
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end
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end
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always @(posedge clkb) begin
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if (reb == 1'b1) begin
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doutb <= m_ram[addrb];
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end
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end
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endmodule
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@@ -0,0 +1,147 @@
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// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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||||
//
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||||
// OR
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||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
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||||
// ***************************************************************************
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// ***************************************************************************
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// A simple asymetric memory. The write and read memory space must have the same size.
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// 2^A_ADDRESS_WIDTH * A_DATA_WIDTH == 2^B_ADDRESS_WIDTH * B_DATA_WIDTH
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`timescale 1ns/100ps
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module ad_mem_asym #(
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parameter A_ADDRESS_WIDTH = 8,
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parameter A_DATA_WIDTH = 256,
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parameter B_ADDRESS_WIDTH = 10,
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parameter B_DATA_WIDTH = 64,
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parameter CASCADE_HEIGHT = -1
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) (
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input clka,
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input wea,
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input [A_ADDRESS_WIDTH-1:0] addra,
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input [A_DATA_WIDTH-1:0] dina,
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input clkb,
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input reb,
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input [B_ADDRESS_WIDTH-1:0] addrb,
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output reg [B_DATA_WIDTH-1:0] doutb
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);
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`define max(a,b) {(a) > (b) ? (a) : (b)}
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`define min(a,b) {(a) < (b) ? (a) : (b)}
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function integer clog2;
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input integer value;
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begin
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if (value < 2)
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clog2 = value;
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else begin
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value = value - 1;
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for (clog2 = 0; value > 0; clog2 = clog2 + 1)
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value = value >> 1;
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end
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end
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endfunction
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localparam MEM_ADDRESS_WIDTH = `max(A_ADDRESS_WIDTH, B_ADDRESS_WIDTH);
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localparam MIN_WIDTH = `min(A_DATA_WIDTH, B_DATA_WIDTH);
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localparam MAX_WIDTH = `max(A_DATA_WIDTH, B_DATA_WIDTH);
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localparam MEM_DATA_WIDTH = MIN_WIDTH;
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localparam MEM_SIZE = 2 ** MEM_ADDRESS_WIDTH;
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localparam MEM_RATIO = MAX_WIDTH / MIN_WIDTH;
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localparam MEM_RATIO_LOG2 = clog2(MEM_RATIO);
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// internal registers
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(* ram_style = "block", cascade_height = CASCADE_HEIGHT *)
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reg [MEM_DATA_WIDTH-1:0] m_ram[0:MEM_SIZE-1];
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//---------------------------------------------------------------------------
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// write interface
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//---------------------------------------------------------------------------
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// write data width is narrower than read data width
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generate if (A_DATA_WIDTH <= B_DATA_WIDTH) begin
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always @(posedge clka) begin
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if (wea == 1'b1) begin
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m_ram[addra] <= dina;
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end
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end
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end
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endgenerate
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// write data width is wider than read data width
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generate if (A_DATA_WIDTH > B_DATA_WIDTH) begin
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always @(posedge clka) begin : memwrite
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integer i;
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reg [MEM_RATIO_LOG2-1:0] lsb;
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for (i = 0; i < MEM_RATIO; i = i + 1) begin : awrite
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lsb = i;
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if (wea) begin
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m_ram[{addra, lsb}] <= dina[i * MIN_WIDTH +: MIN_WIDTH];
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end
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end
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end
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end
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endgenerate
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//---------------------------------------------------------------------------
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// read interface
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//---------------------------------------------------------------------------
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// read data width is narrower than write data width
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generate if (A_DATA_WIDTH >= B_DATA_WIDTH) begin
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always @(posedge clkb) begin
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if (reb == 1'b1) begin
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doutb <= m_ram[addrb];
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end
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end
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end
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endgenerate
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// read data width is wider than write data width
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generate if (A_DATA_WIDTH < B_DATA_WIDTH) begin
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always @(posedge clkb) begin : memread
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integer i;
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reg [MEM_RATIO_LOG2-1:0] lsb;
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for (i = 0; i < MEM_RATIO; i = i + 1) begin : aread
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lsb = i;
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if (reb == 1'b1) begin
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doutb[i*MIN_WIDTH +: MIN_WIDTH] <= m_ram[{addrb, lsb}];
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end
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end
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end
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end
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endgenerate
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endmodule
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@@ -0,0 +1,75 @@
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// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
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`timescale 1ns/100ps
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module ad_rst (
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// clock reset
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input rst_async,
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input clk,
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output rstn,
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output reg rst
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);
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// internal registers
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reg rst_async_d1 = 1'd1;
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reg rst_async_d2 = 1'd1;
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reg rst_sync = 1'd1;
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reg rst_sync_d = 1'd1;
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// simple reset synchronizer
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always @(posedge clk or posedge rst_async) begin
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if (rst_async) begin
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rst_async_d1 <= 1'b1;
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rst_async_d2 <= 1'b1;
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rst_sync <= 1'b1;
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end else begin
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rst_async_d1 <= 1'b0;
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rst_async_d2 <= rst_async_d1;
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rst_sync <= rst_async_d2;
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end
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end
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// two-stage synchronizer to prevent metastability on the falling edge
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always @(posedge clk) begin
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rst_sync_d <= rst_sync;
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rst <= rst_sync_d;
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end
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assign rstn = ~rst;
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endmodule
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@@ -0,0 +1,238 @@
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// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
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`timescale 1ns/100ps
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module up_axi #(
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parameter AXI_ADDRESS_WIDTH = 16
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) (
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// reset and clocks
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input up_rstn,
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input up_clk,
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// axi4 interface
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input up_axi_awvalid,
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input [(AXI_ADDRESS_WIDTH-1):0] up_axi_awaddr,
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output up_axi_awready,
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input up_axi_wvalid,
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input [31:0] up_axi_wdata,
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input [ 3:0] up_axi_wstrb,
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output up_axi_wready,
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output up_axi_bvalid,
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output [ 1:0] up_axi_bresp,
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input up_axi_bready,
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input up_axi_arvalid,
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input [(AXI_ADDRESS_WIDTH-1):0] up_axi_araddr,
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output up_axi_arready,
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output up_axi_rvalid,
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output [ 1:0] up_axi_rresp,
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output [31:0] up_axi_rdata,
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input up_axi_rready,
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// pcore interface
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output up_wreq,
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output [(AXI_ADDRESS_WIDTH-3):0] up_waddr,
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output [31:0] up_wdata,
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input up_wack,
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output up_rreq,
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output [(AXI_ADDRESS_WIDTH-3):0] up_raddr,
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input [31:0] up_rdata,
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input up_rack
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);
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|
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// internal registers
|
||||
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reg up_axi_awready_int = 'd0;
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reg up_axi_wready_int = 'd0;
|
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reg up_axi_bvalid_int = 'd0;
|
||||
reg up_wack_d = 'd0;
|
||||
reg up_wsel = 'd0;
|
||||
reg up_wreq_int = 'd0;
|
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reg [(AXI_ADDRESS_WIDTH-3):0] up_waddr_int = 'd0;
|
||||
reg [31:0] up_wdata_int = 'd0;
|
||||
reg [ 4:0] up_wcount = 'd0;
|
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reg up_axi_arready_int = 'd0;
|
||||
reg up_axi_rvalid_int = 'd0;
|
||||
reg [31:0] up_axi_rdata_int = 'd0;
|
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reg up_rack_d = 'd0;
|
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reg [31:0] up_rdata_d = 'd0;
|
||||
reg up_rsel = 'd0;
|
||||
reg up_rreq_int = 'd0;
|
||||
reg [(AXI_ADDRESS_WIDTH-3):0] up_raddr_int = 'd0;
|
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reg [ 4:0] up_rcount = 'd0;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire up_wack_s;
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||||
wire up_rack_s;
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||||
wire [31:0] up_rdata_s;
|
||||
|
||||
// write channel interface
|
||||
|
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assign up_axi_awready = up_axi_awready_int;
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||||
assign up_axi_wready = up_axi_wready_int;
|
||||
assign up_axi_bvalid = up_axi_bvalid_int;
|
||||
assign up_axi_bresp = 2'd0;
|
||||
|
||||
always @(posedge up_clk) begin
|
||||
if (up_rstn == 1'b0) begin
|
||||
up_axi_awready_int <= 'd0;
|
||||
up_axi_wready_int <= 'd0;
|
||||
up_axi_bvalid_int <= 'd0;
|
||||
end else begin
|
||||
if (up_axi_awready_int == 1'b1) begin
|
||||
up_axi_awready_int <= 1'b0;
|
||||
end else if (up_wack_s == 1'b1) begin
|
||||
up_axi_awready_int <= 1'b1;
|
||||
end
|
||||
if (up_axi_wready_int == 1'b1) begin
|
||||
up_axi_wready_int <= 1'b0;
|
||||
end else if (up_wack_s == 1'b1) begin
|
||||
up_axi_wready_int <= 1'b1;
|
||||
end
|
||||
if ((up_axi_bready == 1'b1) && (up_axi_bvalid_int == 1'b1)) begin
|
||||
up_axi_bvalid_int <= 1'b0;
|
||||
end else if (up_wack_d == 1'b1) begin
|
||||
up_axi_bvalid_int <= 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign up_wreq = up_wreq_int;
|
||||
assign up_waddr = up_waddr_int;
|
||||
assign up_wdata = up_wdata_int;
|
||||
assign up_wack_s = (up_wcount == 5'h1f) ? 1'b1 : (up_wcount[4] & up_wack);
|
||||
|
||||
always @(posedge up_clk) begin
|
||||
if (up_rstn == 1'b0) begin
|
||||
up_wack_d <= 'd0;
|
||||
up_wsel <= 'd0;
|
||||
up_wreq_int <= 'd0;
|
||||
up_waddr_int <= 'd0;
|
||||
up_wdata_int <= 'd0;
|
||||
up_wcount <= 'd0;
|
||||
end else begin
|
||||
up_wack_d <= up_wack_s;
|
||||
if (up_wsel == 1'b1) begin
|
||||
if ((up_axi_bready == 1'b1) && (up_axi_bvalid_int == 1'b1)) begin
|
||||
up_wsel <= 1'b0;
|
||||
end
|
||||
up_wreq_int <= 1'b0;
|
||||
end else begin
|
||||
up_wsel <= up_axi_awvalid & up_axi_wvalid;
|
||||
up_wreq_int <= up_axi_awvalid & up_axi_wvalid;
|
||||
up_waddr_int <= up_axi_awaddr[(AXI_ADDRESS_WIDTH-1):2];
|
||||
up_wdata_int <= up_axi_wdata;
|
||||
end
|
||||
if (up_wack_s == 1'b1) begin
|
||||
up_wcount <= 5'h00;
|
||||
end else if (up_wcount[4] == 1'b1) begin
|
||||
up_wcount <= up_wcount + 1'b1;
|
||||
end else if (up_wreq_int == 1'b1) begin
|
||||
up_wcount <= 5'h10;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// read channel interface
|
||||
|
||||
assign up_axi_arready = up_axi_arready_int;
|
||||
assign up_axi_rvalid = up_axi_rvalid_int;
|
||||
assign up_axi_rdata = up_axi_rdata_int;
|
||||
assign up_axi_rresp = 2'd0;
|
||||
|
||||
always @(posedge up_clk) begin
|
||||
if (up_rstn == 1'b0) begin
|
||||
up_axi_arready_int <= 'd0;
|
||||
up_axi_rvalid_int <= 'd0;
|
||||
up_axi_rdata_int <= 'd0;
|
||||
end else begin
|
||||
if (up_axi_arready_int == 1'b1) begin
|
||||
up_axi_arready_int <= 1'b0;
|
||||
end else if (up_rack_s == 1'b1) begin
|
||||
up_axi_arready_int <= 1'b1;
|
||||
end
|
||||
if ((up_axi_rready == 1'b1) && (up_axi_rvalid_int == 1'b1)) begin
|
||||
up_axi_rvalid_int <= 1'b0;
|
||||
up_axi_rdata_int <= 32'd0;
|
||||
end else if (up_rack_d == 1'b1) begin
|
||||
up_axi_rvalid_int <= 1'b1;
|
||||
up_axi_rdata_int <= up_rdata_d;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign up_rreq = up_rreq_int;
|
||||
assign up_raddr = up_raddr_int;
|
||||
assign up_rack_s = (up_rcount == 5'h1f) ? 1'b1 : (up_rcount[4] & up_rack);
|
||||
assign up_rdata_s = (up_rcount == 5'h1f) ? {2{16'hdead}} : up_rdata;
|
||||
|
||||
always @(posedge up_clk) begin
|
||||
if (up_rstn == 1'b0) begin
|
||||
up_rack_d <= 'd0;
|
||||
up_rdata_d <= 'd0;
|
||||
up_rsel <= 'd0;
|
||||
up_rreq_int <= 'd0;
|
||||
up_raddr_int <= 'd0;
|
||||
up_rcount <= 'd0;
|
||||
end else begin
|
||||
up_rack_d <= up_rack_s;
|
||||
up_rdata_d <= up_rdata_s;
|
||||
if (up_rsel == 1'b1) begin
|
||||
if ((up_axi_rready == 1'b1) && (up_axi_rvalid_int == 1'b1)) begin
|
||||
up_rsel <= 1'b0;
|
||||
end
|
||||
up_rreq_int <= 1'b0;
|
||||
end else begin
|
||||
up_rsel <= up_axi_arvalid;
|
||||
up_rreq_int <= up_axi_arvalid;
|
||||
up_raddr_int <= up_axi_araddr[(AXI_ADDRESS_WIDTH-1):2];
|
||||
end
|
||||
if (up_rack_s == 1'b1) begin
|
||||
up_rcount <= 5'h00;
|
||||
end else if (up_rcount[4] == 1'b1) begin
|
||||
up_rcount <= up_rcount + 1'b1;
|
||||
end else if (up_rreq_int == 1'b1) begin
|
||||
up_rcount <= 5'h10;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,661 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2015-2024 Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module axi_spi_engine #(
|
||||
|
||||
parameter CMD_FIFO_ADDRESS_WIDTH = 4,
|
||||
parameter SYNC_FIFO_ADDRESS_WIDTH = 4,
|
||||
parameter SDO_FIFO_ADDRESS_WIDTH = 5,
|
||||
parameter SDI_FIFO_ADDRESS_WIDTH = 5,
|
||||
parameter MM_IF_TYPE = 0,
|
||||
parameter ASYNC_SPI_CLK = 0,
|
||||
parameter NUM_OFFLOAD = 0,
|
||||
parameter OFFLOAD0_CMD_MEM_ADDRESS_WIDTH = 4,
|
||||
parameter OFFLOAD0_SDO_MEM_ADDRESS_WIDTH = 4,
|
||||
parameter ID = 0,
|
||||
parameter [15:0] DATA_WIDTH = 8,
|
||||
parameter [ 7:0] NUM_OF_SDI = 1,
|
||||
parameter CFG_INFO_0 = 0,
|
||||
parameter CFG_INFO_1 = 0,
|
||||
parameter CFG_INFO_2 = 0,
|
||||
parameter CFG_INFO_3 = 0
|
||||
) (
|
||||
|
||||
// Slave AXI interface
|
||||
|
||||
input s_axi_aclk,
|
||||
input s_axi_aresetn,
|
||||
input s_axi_awvalid,
|
||||
input [15:0] s_axi_awaddr,
|
||||
output s_axi_awready,
|
||||
input [2:0] s_axi_awprot,
|
||||
input s_axi_wvalid,
|
||||
input [31:0] s_axi_wdata,
|
||||
input [ 3:0] s_axi_wstrb,
|
||||
output s_axi_wready,
|
||||
output s_axi_bvalid,
|
||||
output [ 1:0] s_axi_bresp,
|
||||
input s_axi_bready,
|
||||
input s_axi_arvalid,
|
||||
input [15:0] s_axi_araddr,
|
||||
output s_axi_arready,
|
||||
input [2:0] s_axi_arprot,
|
||||
output s_axi_rvalid,
|
||||
input s_axi_rready,
|
||||
output [ 1:0] s_axi_rresp,
|
||||
output [31:0] s_axi_rdata,
|
||||
|
||||
// up interface
|
||||
|
||||
input up_clk,
|
||||
input up_rstn,
|
||||
input up_wreq,
|
||||
input [13:0] up_waddr,
|
||||
input [31:0] up_wdata,
|
||||
output up_wack,
|
||||
input up_rreq,
|
||||
input [13:0] up_raddr,
|
||||
output [31:0] up_rdata,
|
||||
output up_rack,
|
||||
|
||||
output reg irq,
|
||||
|
||||
// SPI signals
|
||||
|
||||
input spi_clk,
|
||||
|
||||
output spi_resetn,
|
||||
|
||||
input cmd_ready,
|
||||
output cmd_valid,
|
||||
output [15:0] cmd_data,
|
||||
|
||||
input sdo_data_ready,
|
||||
output sdo_data_valid,
|
||||
output [(DATA_WIDTH-1):0] sdo_data,
|
||||
|
||||
output sdi_data_ready,
|
||||
input sdi_data_valid,
|
||||
input [(NUM_OF_SDI * DATA_WIDTH-1):0] sdi_data,
|
||||
|
||||
output sync_ready,
|
||||
input sync_valid,
|
||||
input [7:0] sync_data,
|
||||
|
||||
// Offload ctrl signals
|
||||
|
||||
output offload0_cmd_wr_en,
|
||||
output [15:0] offload0_cmd_wr_data,
|
||||
|
||||
output offload0_sdo_wr_en,
|
||||
output [(DATA_WIDTH-1):0] offload0_sdo_wr_data,
|
||||
|
||||
output offload0_mem_reset,
|
||||
output offload0_enable,
|
||||
input offload0_enabled,
|
||||
|
||||
output offload_sync_ready,
|
||||
input offload_sync_valid,
|
||||
input [7:0] offload_sync_data
|
||||
);
|
||||
|
||||
localparam PCORE_VERSION = 'h010201;
|
||||
localparam S_AXI = 0;
|
||||
localparam UP_FIFO = 1;
|
||||
|
||||
wire clk;
|
||||
wire rstn;
|
||||
|
||||
wire [CMD_FIFO_ADDRESS_WIDTH-1:0] cmd_fifo_room;
|
||||
wire cmd_fifo_almost_empty;
|
||||
wire up_cmd_fifo_almost_empty;
|
||||
|
||||
wire [15:0] cmd_fifo_in_data;
|
||||
wire cmd_fifo_in_ready;
|
||||
wire cmd_fifo_in_valid;
|
||||
|
||||
wire [SDO_FIFO_ADDRESS_WIDTH-1:0] sdo_fifo_room;
|
||||
wire sdo_fifo_almost_empty;
|
||||
wire up_sdo_fifo_almost_empty;
|
||||
|
||||
wire [(DATA_WIDTH-1):0] sdo_fifo_in_data;
|
||||
wire sdo_fifo_in_ready;
|
||||
wire sdo_fifo_in_valid;
|
||||
|
||||
wire sdi_fifo_out_data_msb_s;
|
||||
wire [SDI_FIFO_ADDRESS_WIDTH-1:0] sdi_fifo_level;
|
||||
wire sdi_fifo_almost_full;
|
||||
wire up_sdi_fifo_almost_full;
|
||||
|
||||
wire [(NUM_OF_SDI * DATA_WIDTH-1):0] sdi_fifo_out_data;
|
||||
wire sdi_fifo_out_ready;
|
||||
wire sdi_fifo_out_valid;
|
||||
|
||||
wire [7:0] sync_fifo_data;
|
||||
wire sync_fifo_valid;
|
||||
|
||||
wire [7:0] offload_sync_fifo_data;
|
||||
wire offload_sync_fifo_valid;
|
||||
|
||||
reg up_sw_reset = 1'b1;
|
||||
wire up_sw_resetn = ~up_sw_reset;
|
||||
|
||||
reg [31:0] up_rdata_ff = 'd0;
|
||||
reg up_wack_ff = 1'b0;
|
||||
reg up_rack_ff = 1'b0;
|
||||
wire up_wreq_s;
|
||||
wire up_rreq_s;
|
||||
wire [31:0] up_wdata_s;
|
||||
wire [13:0] up_waddr_s;
|
||||
wire [13:0] up_raddr_s;
|
||||
|
||||
// Scratch register
|
||||
reg [31:0] up_scratch = 'h00;
|
||||
|
||||
reg [7:0] sync_id = 'h00;
|
||||
reg sync_id_pending = 1'b0;
|
||||
|
||||
reg [7:0] offload_sync_id = 'h00;
|
||||
reg offload_sync_id_pending = 1'b0;
|
||||
|
||||
generate if (MM_IF_TYPE == S_AXI) begin
|
||||
|
||||
// assign clock and reset
|
||||
|
||||
assign clk = s_axi_aclk;
|
||||
assign rstn = s_axi_aresetn;
|
||||
|
||||
// interface wrapper
|
||||
|
||||
up_axi #(
|
||||
.AXI_ADDRESS_WIDTH (16)
|
||||
) i_up_axi (
|
||||
.up_rstn(rstn),
|
||||
.up_clk(clk),
|
||||
.up_axi_awvalid(s_axi_awvalid),
|
||||
.up_axi_awaddr(s_axi_awaddr),
|
||||
.up_axi_awready(s_axi_awready),
|
||||
.up_axi_wvalid(s_axi_wvalid),
|
||||
.up_axi_wdata(s_axi_wdata),
|
||||
.up_axi_wstrb(s_axi_wstrb),
|
||||
.up_axi_wready(s_axi_wready),
|
||||
.up_axi_bvalid(s_axi_bvalid),
|
||||
.up_axi_bresp(s_axi_bresp),
|
||||
.up_axi_bready(s_axi_bready),
|
||||
.up_axi_arvalid(s_axi_arvalid),
|
||||
.up_axi_araddr(s_axi_araddr),
|
||||
.up_axi_arready(s_axi_arready),
|
||||
.up_axi_rvalid(s_axi_rvalid),
|
||||
.up_axi_rresp(s_axi_rresp),
|
||||
.up_axi_rdata(s_axi_rdata),
|
||||
.up_axi_rready(s_axi_rready),
|
||||
.up_wreq(up_wreq_s),
|
||||
.up_waddr(up_waddr_s),
|
||||
.up_wdata(up_wdata_s),
|
||||
.up_wack(up_wack_ff),
|
||||
.up_rreq(up_rreq_s),
|
||||
.up_raddr(up_raddr_s),
|
||||
.up_rdata(up_rdata_ff),
|
||||
.up_rack(up_rack_ff));
|
||||
|
||||
assign up_rdata = 32'b0;
|
||||
assign up_rack = 1'b0;
|
||||
assign up_wack = 1'b0;
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (MM_IF_TYPE == UP_FIFO) begin
|
||||
|
||||
// assign clock and reset
|
||||
|
||||
assign clk = up_clk;
|
||||
assign rstn = up_rstn;
|
||||
|
||||
assign up_wreq_s = up_wreq;
|
||||
assign up_waddr_s = up_waddr;
|
||||
assign up_wdata_s = up_wdata;
|
||||
assign up_wack = up_wack_ff;
|
||||
assign up_rreq_s = up_rreq;
|
||||
assign up_raddr_s = up_raddr;
|
||||
assign up_rdata = up_rdata_ff;
|
||||
assign up_rack = up_rack_ff;
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// IRQ handling
|
||||
reg [4:0] up_irq_mask = 5'h0;
|
||||
wire [4:0] up_irq_source;
|
||||
wire [4:0] up_irq_pending;
|
||||
|
||||
assign up_irq_source = {
|
||||
offload_sync_id_pending,
|
||||
sync_id_pending,
|
||||
up_sdi_fifo_almost_full,
|
||||
up_sdo_fifo_almost_empty,
|
||||
up_cmd_fifo_almost_empty
|
||||
};
|
||||
|
||||
assign up_irq_pending = up_irq_mask & up_irq_source;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rstn == 1'b0)
|
||||
irq <= 1'b0;
|
||||
else
|
||||
irq <= |up_irq_pending;
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rstn == 1'b0) begin
|
||||
up_wack_ff <= 1'b0;
|
||||
up_scratch <= 'h00;
|
||||
up_sw_reset <= 1'b1;
|
||||
end else begin
|
||||
up_wack_ff <= up_wreq_s;
|
||||
if (up_wreq_s) begin
|
||||
case (up_waddr_s)
|
||||
8'h02: up_scratch <= up_wdata_s;
|
||||
8'h10: up_sw_reset <= up_wdata_s;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
reg offload0_enable_reg;
|
||||
reg offload0_mem_reset_reg;
|
||||
wire offload0_enabled_s;
|
||||
|
||||
// the software reset should reset all the registers
|
||||
always @(posedge clk) begin
|
||||
if (up_sw_resetn == 1'b0) begin
|
||||
up_irq_mask <= 'h00;
|
||||
offload0_enable_reg <= 1'b0;
|
||||
offload0_mem_reset_reg <= 1'b0;
|
||||
end else begin
|
||||
if (up_wreq_s) begin
|
||||
case (up_waddr_s)
|
||||
8'h20: up_irq_mask <= up_wdata_s;
|
||||
8'h40: offload0_enable_reg <= up_wdata_s[0];
|
||||
8'h42: offload0_mem_reset_reg <= up_wdata_s[0];
|
||||
endcase
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rstn == 1'b0) begin
|
||||
up_rack_ff <= 'd0;
|
||||
end else begin
|
||||
up_rack_ff <= up_rreq_s;
|
||||
end
|
||||
end
|
||||
|
||||
generate
|
||||
if (NUM_OF_SDI > 1) begin
|
||||
// Only the first two SDI data can be recovered through AXI regmap
|
||||
assign sdi_fifo_out_data_msb_s = sdi_fifo_out_data[DATA_WIDTH+:DATA_WIDTH];
|
||||
end else begin
|
||||
assign sdi_fifo_out_data_msb_s = sdi_fifo_out_data;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
reg [7:0] offload_sdo_mem_address_width = OFFLOAD0_SDO_MEM_ADDRESS_WIDTH;
|
||||
reg [7:0] offload_cmd_mem_address_width = OFFLOAD0_CMD_MEM_ADDRESS_WIDTH;
|
||||
reg [7:0] sdi_fifo_address_width = SDI_FIFO_ADDRESS_WIDTH;
|
||||
reg [7:0] sdo_fifo_address_width = SDO_FIFO_ADDRESS_WIDTH;
|
||||
reg [7:0] sync_fifo_address_width = SYNC_FIFO_ADDRESS_WIDTH;
|
||||
reg [7:0] cmd_fifo_address_width = CMD_FIFO_ADDRESS_WIDTH;
|
||||
always @(posedge clk) begin
|
||||
case (up_raddr_s)
|
||||
8'h00: up_rdata_ff <= PCORE_VERSION;
|
||||
8'h01: up_rdata_ff <= ID;
|
||||
8'h02: up_rdata_ff <= up_scratch;
|
||||
8'h03: up_rdata_ff <= {8'b0, NUM_OF_SDI, DATA_WIDTH};
|
||||
8'h04: up_rdata_ff <= {16'b0, offload_sdo_mem_address_width, offload_cmd_mem_address_width};
|
||||
8'h05: up_rdata_ff <= {sdi_fifo_address_width, sdo_fifo_address_width, sync_fifo_address_width, cmd_fifo_address_width};
|
||||
8'h10: up_rdata_ff <= up_sw_reset;
|
||||
8'h20: up_rdata_ff <= up_irq_mask;
|
||||
8'h21: up_rdata_ff <= up_irq_pending;
|
||||
8'h22: up_rdata_ff <= up_irq_source;
|
||||
8'h30: up_rdata_ff <= sync_id;
|
||||
8'h31: up_rdata_ff <= offload_sync_id;
|
||||
8'h34: up_rdata_ff <= cmd_fifo_room;
|
||||
8'h35: up_rdata_ff <= sdo_fifo_room;
|
||||
8'h36: up_rdata_ff <= (sdi_fifo_out_valid == 1) ? sdi_fifo_level + 1 : sdi_fifo_level; /* beacuse of first-word-fall-through */
|
||||
8'h3a: up_rdata_ff <= sdi_fifo_out_data[DATA_WIDTH-1:0];
|
||||
8'h3b: up_rdata_ff <= sdi_fifo_out_data_msb_s; /* store SDI's 32 bits MSB, if exists */
|
||||
8'h3c: up_rdata_ff <= sdi_fifo_out_data; /* PEEK register */
|
||||
8'h40: up_rdata_ff <= {offload0_enable_reg};
|
||||
8'h41: up_rdata_ff <= {offload0_enabled_s};
|
||||
8'h80: up_rdata_ff <= CFG_INFO_0;
|
||||
8'h81: up_rdata_ff <= CFG_INFO_1;
|
||||
8'h82: up_rdata_ff <= CFG_INFO_2;
|
||||
8'h83: up_rdata_ff <= CFG_INFO_3;
|
||||
default: up_rdata_ff <= 'h00;
|
||||
endcase
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (up_sw_resetn == 1'b0) begin
|
||||
sync_id <= 'h00;
|
||||
sync_id_pending <= 1'b0;
|
||||
end else begin
|
||||
if (sync_fifo_valid == 1'b1) begin
|
||||
sync_id <= sync_fifo_data;
|
||||
sync_id_pending <= 1'b1;
|
||||
end else if (up_wreq_s == 1'b1 && up_waddr_s == 8'h21 && up_wdata_s[3] == 1'b1) begin
|
||||
sync_id_pending <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (up_sw_resetn == 1'b0) begin
|
||||
offload_sync_id <= 'h00;
|
||||
offload_sync_id_pending <= 1'b0;
|
||||
end else begin
|
||||
if (offload_sync_fifo_valid == 1'b1) begin
|
||||
offload_sync_id <= offload_sync_fifo_data;
|
||||
offload_sync_id_pending <= 1'b1;
|
||||
end else if (up_wreq_s == 1'b1 && up_waddr_s == 8'h21 && up_wdata_s[4] == 1'b1) begin
|
||||
offload_sync_id_pending <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
generate if (ASYNC_SPI_CLK) begin
|
||||
|
||||
wire spi_reset;
|
||||
ad_rst i_spi_resetn (
|
||||
.rst_async(up_sw_reset),
|
||||
.clk(spi_clk),
|
||||
.rst(spi_reset),
|
||||
.rstn());
|
||||
assign spi_resetn = ~spi_reset;
|
||||
end else begin
|
||||
assign spi_resetn = ~up_sw_reset;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
assign cmd_fifo_in_valid = up_wreq_s == 1'b1 && up_waddr_s == 8'h38;
|
||||
assign cmd_fifo_in_data = up_wdata_s[15:0];
|
||||
|
||||
util_axis_fifo #(
|
||||
.DATA_WIDTH(16),
|
||||
.ADDRESS_WIDTH(CMD_FIFO_ADDRESS_WIDTH),
|
||||
.ASYNC_CLK(ASYNC_SPI_CLK),
|
||||
.M_AXIS_REGISTERED(0),
|
||||
.ALMOST_EMPTY_THRESHOLD(1),
|
||||
.ALMOST_FULL_THRESHOLD(1)
|
||||
) i_cmd_fifo (
|
||||
.s_axis_aclk(clk),
|
||||
.s_axis_aresetn(up_sw_resetn),
|
||||
.s_axis_ready(cmd_fifo_in_ready),
|
||||
.s_axis_valid(cmd_fifo_in_valid),
|
||||
.s_axis_data(cmd_fifo_in_data),
|
||||
.s_axis_room(cmd_fifo_room),
|
||||
.s_axis_tlast(1'b0),
|
||||
.s_axis_full(),
|
||||
.s_axis_almost_full(),
|
||||
.m_axis_aclk(spi_clk),
|
||||
.m_axis_aresetn(spi_resetn),
|
||||
.m_axis_ready(cmd_ready),
|
||||
.m_axis_valid(cmd_valid),
|
||||
.m_axis_data(cmd_data),
|
||||
.m_axis_tlast(),
|
||||
.m_axis_empty(),
|
||||
.m_axis_almost_empty(cmd_fifo_almost_empty),
|
||||
.m_axis_level());
|
||||
|
||||
assign sdo_fifo_in_valid = up_wreq_s == 1'b1 && up_waddr_s == 8'h39;
|
||||
assign sdo_fifo_in_data = up_wdata_s[(DATA_WIDTH-1):0];
|
||||
|
||||
util_axis_fifo #(
|
||||
.DATA_WIDTH(DATA_WIDTH),
|
||||
.ASYNC_CLK(ASYNC_SPI_CLK),
|
||||
.ADDRESS_WIDTH(SDO_FIFO_ADDRESS_WIDTH),
|
||||
.M_AXIS_REGISTERED(0),
|
||||
.ALMOST_EMPTY_THRESHOLD(1),
|
||||
.ALMOST_FULL_THRESHOLD(1)
|
||||
) i_sdo_fifo (
|
||||
.s_axis_aclk(clk),
|
||||
.s_axis_aresetn(up_sw_resetn),
|
||||
.s_axis_ready(sdo_fifo_in_ready),
|
||||
.s_axis_valid(sdo_fifo_in_valid),
|
||||
.s_axis_data(sdo_fifo_in_data),
|
||||
.s_axis_room(sdo_fifo_room),
|
||||
.s_axis_tlast(1'b0),
|
||||
.s_axis_full(),
|
||||
.s_axis_almost_full(),
|
||||
.m_axis_aclk(spi_clk),
|
||||
.m_axis_aresetn(spi_resetn),
|
||||
.m_axis_ready(sdo_data_ready),
|
||||
.m_axis_valid(sdo_data_valid),
|
||||
.m_axis_data(sdo_data),
|
||||
.m_axis_tlast(),
|
||||
.m_axis_level(),
|
||||
.m_axis_empty(),
|
||||
.m_axis_almost_empty(sdo_fifo_almost_empty));
|
||||
|
||||
assign sdi_fifo_out_ready = up_rreq_s == 1'b1 && up_raddr_s == 8'h3a;
|
||||
|
||||
util_axis_fifo #(
|
||||
.DATA_WIDTH(NUM_OF_SDI * DATA_WIDTH),
|
||||
.ASYNC_CLK(ASYNC_SPI_CLK),
|
||||
.ADDRESS_WIDTH(SDI_FIFO_ADDRESS_WIDTH),
|
||||
.M_AXIS_REGISTERED(0),
|
||||
.ALMOST_EMPTY_THRESHOLD(1),
|
||||
.ALMOST_FULL_THRESHOLD(31)
|
||||
) i_sdi_fifo (
|
||||
.s_axis_aclk(spi_clk),
|
||||
.s_axis_aresetn(spi_resetn),
|
||||
.s_axis_ready(sdi_data_ready),
|
||||
.s_axis_valid(sdi_data_valid),
|
||||
.s_axis_data(sdi_data),
|
||||
.s_axis_room(),
|
||||
.s_axis_tlast(),
|
||||
.s_axis_full(),
|
||||
.s_axis_almost_full(sdi_fifo_almost_full),
|
||||
.m_axis_aclk(clk),
|
||||
.m_axis_aresetn(up_sw_resetn),
|
||||
.m_axis_ready(sdi_fifo_out_ready),
|
||||
.m_axis_valid(sdi_fifo_out_valid),
|
||||
.m_axis_data(sdi_fifo_out_data),
|
||||
.m_axis_tlast(),
|
||||
.m_axis_level(sdi_fifo_level),
|
||||
.m_axis_empty(),
|
||||
.m_axis_almost_empty());
|
||||
|
||||
generate if (ASYNC_SPI_CLK) begin
|
||||
|
||||
// synchronization FIFO for the SYNC interface
|
||||
util_axis_fifo #(
|
||||
.DATA_WIDTH(8),
|
||||
.ASYNC_CLK(ASYNC_SPI_CLK),
|
||||
.ADDRESS_WIDTH(SYNC_FIFO_ADDRESS_WIDTH),
|
||||
.M_AXIS_REGISTERED(0)
|
||||
) i_sync_fifo (
|
||||
.s_axis_aclk(spi_clk),
|
||||
.s_axis_aresetn(spi_resetn),
|
||||
.s_axis_ready(sync_ready),
|
||||
.s_axis_valid(sync_valid),
|
||||
.s_axis_data(sync_data),
|
||||
.s_axis_room(),
|
||||
.s_axis_full(),
|
||||
.m_axis_aclk(clk),
|
||||
.m_axis_aresetn(up_sw_resetn),
|
||||
.m_axis_ready(1'b1),
|
||||
.m_axis_valid(sync_fifo_valid),
|
||||
.m_axis_data(sync_fifo_data),
|
||||
.m_axis_level(),
|
||||
.m_axis_empty());
|
||||
|
||||
// synchronization FIFO for the offload command interface
|
||||
wire up_offload0_cmd_wr_en_s;
|
||||
wire [15:0] up_offload0_cmd_wr_data_s;
|
||||
|
||||
util_axis_fifo #(
|
||||
.DATA_WIDTH(16),
|
||||
.ASYNC_CLK(ASYNC_SPI_CLK),
|
||||
.ADDRESS_WIDTH(SYNC_FIFO_ADDRESS_WIDTH),
|
||||
.M_AXIS_REGISTERED(0)
|
||||
) i_offload_cmd_fifo (
|
||||
.s_axis_aclk(clk),
|
||||
.s_axis_aresetn(up_sw_resetn),
|
||||
.s_axis_ready(),
|
||||
.s_axis_valid(up_offload0_cmd_wr_en_s),
|
||||
.s_axis_data(up_offload0_cmd_wr_data_s),
|
||||
.s_axis_room(),
|
||||
.s_axis_full(),
|
||||
.m_axis_aclk(spi_clk),
|
||||
.m_axis_aresetn(spi_resetn),
|
||||
.m_axis_ready(1'b1),
|
||||
.m_axis_valid(offload0_cmd_wr_en),
|
||||
.m_axis_data(offload0_cmd_wr_data),
|
||||
.m_axis_level(),
|
||||
.m_axis_empty());
|
||||
|
||||
assign up_offload0_cmd_wr_en_s = up_wreq_s == 1'b1 && up_waddr_s == 8'h44;
|
||||
assign up_offload0_cmd_wr_data_s = up_wdata_s[15:0];
|
||||
|
||||
// synchronization FIFO for the offload SDO interface
|
||||
wire up_offload0_sdo_wr_en_s;
|
||||
wire [DATA_WIDTH-1:0] up_offload0_sdo_wr_data_s;
|
||||
|
||||
util_axis_fifo #(
|
||||
.DATA_WIDTH(DATA_WIDTH),
|
||||
.ASYNC_CLK(ASYNC_SPI_CLK),
|
||||
.ADDRESS_WIDTH(SYNC_FIFO_ADDRESS_WIDTH),
|
||||
.M_AXIS_REGISTERED(0)
|
||||
) i_offload_sdo_fifo (
|
||||
.s_axis_aclk(clk),
|
||||
.s_axis_aresetn(up_sw_resetn),
|
||||
.s_axis_ready(),
|
||||
.s_axis_valid(up_offload0_sdo_wr_en_s),
|
||||
.s_axis_data(up_offload0_sdo_wr_data_s),
|
||||
.s_axis_room(),
|
||||
.s_axis_full(),
|
||||
.m_axis_aclk(spi_clk),
|
||||
.m_axis_aresetn(spi_resetn),
|
||||
.m_axis_ready(1'b1),
|
||||
.m_axis_valid(offload0_sdo_wr_en),
|
||||
.m_axis_data(offload0_sdo_wr_data),
|
||||
.m_axis_level(),
|
||||
.m_axis_empty());
|
||||
|
||||
assign up_offload0_sdo_wr_en_s = up_wreq_s == 1'b1 && up_waddr_s == 8'h45;
|
||||
assign up_offload0_sdo_wr_data_s = up_wdata_s[DATA_WIDTH-1:0];
|
||||
|
||||
// synchronization FIFO for the Offload SYNC interface
|
||||
util_axis_fifo #(
|
||||
.DATA_WIDTH(8),
|
||||
.ASYNC_CLK(ASYNC_SPI_CLK),
|
||||
.ADDRESS_WIDTH(SYNC_FIFO_ADDRESS_WIDTH),
|
||||
.M_AXIS_REGISTERED(0)
|
||||
) i_offload_sync_fifo (
|
||||
.s_axis_aclk(spi_clk),
|
||||
.s_axis_aresetn(spi_resetn),
|
||||
.s_axis_ready(offload_sync_ready),
|
||||
.s_axis_valid(offload_sync_valid),
|
||||
.s_axis_data(offload_sync_data),
|
||||
.s_axis_room(),
|
||||
.s_axis_full(),
|
||||
.m_axis_aclk(clk),
|
||||
.m_axis_aresetn(up_sw_resetn),
|
||||
.m_axis_ready(1'b1),
|
||||
.m_axis_valid(offload_sync_fifo_valid),
|
||||
.m_axis_data(offload_sync_fifo_data),
|
||||
.m_axis_level(),
|
||||
.m_axis_empty());
|
||||
|
||||
end else begin /* ASYNC_SPI_CLK == 0 */
|
||||
|
||||
assign sync_fifo_valid = sync_valid;
|
||||
assign sync_fifo_data = sync_data;
|
||||
assign sync_ready = 1'b1;
|
||||
|
||||
assign offload0_cmd_wr_en = up_wreq_s == 1'b1 && up_waddr_s == 8'h44;
|
||||
assign offload0_cmd_wr_data = up_wdata_s[15:0];
|
||||
|
||||
assign offload0_sdo_wr_en = up_wreq_s == 1'b1 && up_waddr_s == 8'h45;
|
||||
assign offload0_sdo_wr_data = up_wdata_s[DATA_WIDTH-1:0];
|
||||
|
||||
assign offload_sync_fifo_valid = offload_sync_valid;
|
||||
assign offload_sync_fifo_data = offload_sync_data;
|
||||
assign offload_sync_ready = 1'b1;
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
sync_bits #(
|
||||
.NUM_OF_BITS (1),
|
||||
.ASYNC_CLK (ASYNC_SPI_CLK)
|
||||
) i_offload_enable_sync (
|
||||
.in_bits (offload0_enable_reg),
|
||||
.out_resetn (spi_resetn),
|
||||
.out_clk (spi_clk),
|
||||
.out_bits (offload0_enable));
|
||||
|
||||
sync_bits #(
|
||||
.NUM_OF_BITS (1),
|
||||
.ASYNC_CLK (ASYNC_SPI_CLK)
|
||||
) i_offload_enabled_sync (
|
||||
.in_bits (offload0_enabled),
|
||||
.out_resetn (up_sw_resetn),
|
||||
.out_clk (clk),
|
||||
.out_bits (offload0_enabled_s));
|
||||
|
||||
sync_bits #(
|
||||
.NUM_OF_BITS (1),
|
||||
.ASYNC_CLK (ASYNC_SPI_CLK)
|
||||
) i_offload_mem_reset_sync (
|
||||
.in_bits (offload0_mem_reset_reg),
|
||||
.out_resetn (spi_resetn),
|
||||
.out_clk (spi_clk),
|
||||
.out_bits (offload0_mem_reset));
|
||||
|
||||
sync_bits #(
|
||||
.NUM_OF_BITS (3),
|
||||
.ASYNC_CLK (ASYNC_SPI_CLK)
|
||||
) i_fifo_status (
|
||||
.in_bits ({cmd_fifo_almost_empty, sdi_fifo_almost_full, sdo_fifo_almost_empty}),
|
||||
.out_resetn (up_sw_resetn),
|
||||
.out_clk (clk),
|
||||
.out_bits ({up_cmd_fifo_almost_empty, up_sdi_fifo_almost_full, up_sdo_fifo_almost_empty}));
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,8 @@
|
||||
###############################################################################
|
||||
## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIBSD
|
||||
###############################################################################
|
||||
|
||||
set_false_path \
|
||||
-to [get_registers *cdc_sync_stage1*]
|
||||
|
||||
@@ -0,0 +1,35 @@
|
||||
###############################################################################
|
||||
## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved.
|
||||
# SPDX short identifier: ADIBSD
|
||||
###############################################################################
|
||||
|
||||
<: set ComponentName [getComponentNameString] :>
|
||||
<: setOutputDirectory "./" :>
|
||||
<: setFileName [ttcl_add $ComponentName "_constr"] :>
|
||||
<: setFileExtension ".xdc" :>
|
||||
<: setFileProcessingOrder late :>
|
||||
<: set async_spi_clk [getBooleanValue "ASYNC_SPI_CLK"] :>
|
||||
|
||||
<: if { $async_spi_clk } { :>
|
||||
|
||||
set_property ASYNC_REG TRUE \
|
||||
[get_cells -quiet -hierarchical *cdc_sync_stage1_reg*] \
|
||||
[get_cells -quiet -hierarchical *cdc_sync_stage2_reg*]
|
||||
|
||||
set_false_path -quiet \
|
||||
-from [get_cells -quiet -hierarchical -filter {NAME =~ *i_address_gray/*cdc_sync_stage0_reg* && IS_SEQUENTIAL}] \
|
||||
-to [get_cells -quiet -hierarchical -filter {NAME =~ *i_address_gray/*cdc_sync_stage1_reg* && IS_SEQUENTIAL}]
|
||||
|
||||
set_false_path -quiet \
|
||||
-to [get_cells -quiet -hierarchical -filter {NAME =~ *i_offload_enable_sync/cdc_sync_stage1_reg* && IS_SEQUENTIAL}]
|
||||
|
||||
set_false_path -quiet \
|
||||
-to [get_cells -quiet -hierarchical -filter {NAME =~ *i_offload_enabled_sync/cdc_sync_stage1_reg* && IS_SEQUENTIAL}]
|
||||
|
||||
set_false_path -quiet \
|
||||
-to [get_cells -quiet -hierarchical -filter {NAME =~ *i_offload_mem_reset_sync/cdc_sync_stage1_reg* && IS_SEQUENTIAL}]
|
||||
|
||||
set_false_path -quiet \
|
||||
-to [get_cells -quiet -hierarchical -filter {NAME =~ *i_fifo_status/cdc_sync_stage1_reg* && IS_SEQUENTIAL}]
|
||||
|
||||
<: } :>
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,3 @@
|
||||
# This file is automatically written. Do not modify.
|
||||
proc gen_USERPARAMETER_OFFLOAD0_CMD_MEM_ADDRESS_WIDTH_ENABLEMENT {NUM_OFFLOAD } {expr $NUM_OFFLOAD > 0}
|
||||
proc gen_USERPARAMETER_OFFLOAD0_SDO_MEM_ADDRESS_WIDTH_ENABLEMENT {NUM_OFFLOAD } {expr $NUM_OFFLOAD > 0}
|
||||
@@ -0,0 +1,289 @@
|
||||
|
||||
# Loading additional proc with user specified bodies to compute parameter values.
|
||||
source [file join [file dirname [file dirname [info script]]] gui/axi_spi_engine_v1_0.gtcl]
|
||||
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set AXI_SPI_Engine_soft-controller [ipgui::add_page $IPINST -name "AXI SPI Engine soft-controller"]
|
||||
#Adding Group
|
||||
set General_Configuration [ipgui::add_group $IPINST -name "General Configuration" -parent ${AXI_SPI_Engine_soft-controller}]
|
||||
set ID [ipgui::add_param $IPINST -name "ID" -parent ${General_Configuration}]
|
||||
set_property tooltip {[ID] Core instance ID} ${ID}
|
||||
set DATA_WIDTH [ipgui::add_param $IPINST -name "DATA_WIDTH" -parent ${General_Configuration}]
|
||||
set_property tooltip {[DATA_WIDTH] Define the data interface width} ${DATA_WIDTH}
|
||||
set NUM_OF_SDI [ipgui::add_param $IPINST -name "NUM_OF_SDI" -parent ${General_Configuration}]
|
||||
set_property tooltip {[NUM_OF_SDI] Define the number of MISO lines} ${NUM_OF_SDI}
|
||||
set MM_IF_TYPE [ipgui::add_param $IPINST -name "MM_IF_TYPE" -parent ${General_Configuration}]
|
||||
set_property tooltip {[MM_IF_TYPE] Define the memory mapped interface type} ${MM_IF_TYPE}
|
||||
set ASYNC_SPI_CLK [ipgui::add_param $IPINST -name "ASYNC_SPI_CLK" -parent ${General_Configuration}]
|
||||
set_property tooltip {[ASYNC_SPI_CLK] Define the relationship between the core clock and the memory mapped interface clock} ${ASYNC_SPI_CLK}
|
||||
|
||||
#Adding Group
|
||||
set Command_stream_FIFO_configuration [ipgui::add_group $IPINST -name "Command stream FIFO configuration" -parent ${AXI_SPI_Engine_soft-controller}]
|
||||
set CMD_FIFO_ADDRESS_WIDTH [ipgui::add_param $IPINST -name "CMD_FIFO_ADDRESS_WIDTH" -parent ${Command_stream_FIFO_configuration}]
|
||||
set_property tooltip {[CMD_FIFO_ADDRESS_WIDTH] Define the depth of the FIFO} ${CMD_FIFO_ADDRESS_WIDTH}
|
||||
set SYNC_FIFO_ADDRESS_WIDTH [ipgui::add_param $IPINST -name "SYNC_FIFO_ADDRESS_WIDTH" -parent ${Command_stream_FIFO_configuration}]
|
||||
set_property tooltip {[SYNC_FIFO_ADDRESS_WIDTH] Define the depth of the FIFO} ${SYNC_FIFO_ADDRESS_WIDTH}
|
||||
set SDO_FIFO_ADDRESS_WIDTH [ipgui::add_param $IPINST -name "SDO_FIFO_ADDRESS_WIDTH" -parent ${Command_stream_FIFO_configuration}]
|
||||
set_property tooltip {[SDO_FIFO_ADDRESS_WIDTH] Define the depth of the FIFO} ${SDO_FIFO_ADDRESS_WIDTH}
|
||||
set SDI_FIFO_ADDRESS_WIDTH [ipgui::add_param $IPINST -name "SDI_FIFO_ADDRESS_WIDTH" -parent ${Command_stream_FIFO_configuration}]
|
||||
set_property tooltip {[SDI_FIFO_ADDRESS_WIDTH] Define the depth of the FIFO} ${SDI_FIFO_ADDRESS_WIDTH}
|
||||
|
||||
#Adding Group
|
||||
set Offload_module_configuration [ipgui::add_group $IPINST -name "Offload module configuration" -parent ${AXI_SPI_Engine_soft-controller}]
|
||||
set NUM_OFFLOAD [ipgui::add_param $IPINST -name "NUM_OFFLOAD" -parent ${Offload_module_configuration}]
|
||||
set_property tooltip {[NUM_OFFLOAD] Number of offloads} ${NUM_OFFLOAD}
|
||||
set OFFLOAD0_CMD_MEM_ADDRESS_WIDTH [ipgui::add_param $IPINST -name "OFFLOAD0_CMD_MEM_ADDRESS_WIDTH" -parent ${Offload_module_configuration}]
|
||||
set_property tooltip {[OFFLOAD0_CMD_MEM_ADDRESS_WIDTH] Define the depth of the FIFO} ${OFFLOAD0_CMD_MEM_ADDRESS_WIDTH}
|
||||
set OFFLOAD0_SDO_MEM_ADDRESS_WIDTH [ipgui::add_param $IPINST -name "OFFLOAD0_SDO_MEM_ADDRESS_WIDTH" -parent ${Offload_module_configuration}]
|
||||
set_property tooltip {[OFFLOAD0_SDO_MEM_ADDRESS_WIDTH] Define the depth of the FIFO} ${OFFLOAD0_SDO_MEM_ADDRESS_WIDTH}
|
||||
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.OFFLOAD0_CMD_MEM_ADDRESS_WIDTH { PARAM_VALUE.OFFLOAD0_CMD_MEM_ADDRESS_WIDTH PARAM_VALUE.NUM_OFFLOAD } {
|
||||
# Procedure called to update OFFLOAD0_CMD_MEM_ADDRESS_WIDTH when any of the dependent parameters in the arguments change
|
||||
|
||||
set OFFLOAD0_CMD_MEM_ADDRESS_WIDTH ${PARAM_VALUE.OFFLOAD0_CMD_MEM_ADDRESS_WIDTH}
|
||||
set NUM_OFFLOAD ${PARAM_VALUE.NUM_OFFLOAD}
|
||||
set values(NUM_OFFLOAD) [get_property value $NUM_OFFLOAD]
|
||||
if { [gen_USERPARAMETER_OFFLOAD0_CMD_MEM_ADDRESS_WIDTH_ENABLEMENT $values(NUM_OFFLOAD)] } {
|
||||
set_property enabled true $OFFLOAD0_CMD_MEM_ADDRESS_WIDTH
|
||||
} else {
|
||||
set_property enabled false $OFFLOAD0_CMD_MEM_ADDRESS_WIDTH
|
||||
}
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.OFFLOAD0_CMD_MEM_ADDRESS_WIDTH { PARAM_VALUE.OFFLOAD0_CMD_MEM_ADDRESS_WIDTH } {
|
||||
# Procedure called to validate OFFLOAD0_CMD_MEM_ADDRESS_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.OFFLOAD0_SDO_MEM_ADDRESS_WIDTH { PARAM_VALUE.OFFLOAD0_SDO_MEM_ADDRESS_WIDTH PARAM_VALUE.NUM_OFFLOAD } {
|
||||
# Procedure called to update OFFLOAD0_SDO_MEM_ADDRESS_WIDTH when any of the dependent parameters in the arguments change
|
||||
|
||||
set OFFLOAD0_SDO_MEM_ADDRESS_WIDTH ${PARAM_VALUE.OFFLOAD0_SDO_MEM_ADDRESS_WIDTH}
|
||||
set NUM_OFFLOAD ${PARAM_VALUE.NUM_OFFLOAD}
|
||||
set values(NUM_OFFLOAD) [get_property value $NUM_OFFLOAD]
|
||||
if { [gen_USERPARAMETER_OFFLOAD0_SDO_MEM_ADDRESS_WIDTH_ENABLEMENT $values(NUM_OFFLOAD)] } {
|
||||
set_property enabled true $OFFLOAD0_SDO_MEM_ADDRESS_WIDTH
|
||||
} else {
|
||||
set_property enabled false $OFFLOAD0_SDO_MEM_ADDRESS_WIDTH
|
||||
}
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.OFFLOAD0_SDO_MEM_ADDRESS_WIDTH { PARAM_VALUE.OFFLOAD0_SDO_MEM_ADDRESS_WIDTH } {
|
||||
# Procedure called to validate OFFLOAD0_SDO_MEM_ADDRESS_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.ASYNC_SPI_CLK { PARAM_VALUE.ASYNC_SPI_CLK } {
|
||||
# Procedure called to update ASYNC_SPI_CLK when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.ASYNC_SPI_CLK { PARAM_VALUE.ASYNC_SPI_CLK } {
|
||||
# Procedure called to validate ASYNC_SPI_CLK
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.CFG_INFO_0 { PARAM_VALUE.CFG_INFO_0 } {
|
||||
# Procedure called to update CFG_INFO_0 when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.CFG_INFO_0 { PARAM_VALUE.CFG_INFO_0 } {
|
||||
# Procedure called to validate CFG_INFO_0
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.CFG_INFO_1 { PARAM_VALUE.CFG_INFO_1 } {
|
||||
# Procedure called to update CFG_INFO_1 when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.CFG_INFO_1 { PARAM_VALUE.CFG_INFO_1 } {
|
||||
# Procedure called to validate CFG_INFO_1
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.CFG_INFO_2 { PARAM_VALUE.CFG_INFO_2 } {
|
||||
# Procedure called to update CFG_INFO_2 when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.CFG_INFO_2 { PARAM_VALUE.CFG_INFO_2 } {
|
||||
# Procedure called to validate CFG_INFO_2
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.CFG_INFO_3 { PARAM_VALUE.CFG_INFO_3 } {
|
||||
# Procedure called to update CFG_INFO_3 when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.CFG_INFO_3 { PARAM_VALUE.CFG_INFO_3 } {
|
||||
# Procedure called to validate CFG_INFO_3
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.CMD_FIFO_ADDRESS_WIDTH { PARAM_VALUE.CMD_FIFO_ADDRESS_WIDTH } {
|
||||
# Procedure called to update CMD_FIFO_ADDRESS_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.CMD_FIFO_ADDRESS_WIDTH { PARAM_VALUE.CMD_FIFO_ADDRESS_WIDTH } {
|
||||
# Procedure called to validate CMD_FIFO_ADDRESS_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } {
|
||||
# Procedure called to update DATA_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } {
|
||||
# Procedure called to validate DATA_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } {
|
||||
# Procedure called to update ID when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } {
|
||||
# Procedure called to validate ID
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.MM_IF_TYPE { PARAM_VALUE.MM_IF_TYPE } {
|
||||
# Procedure called to update MM_IF_TYPE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.MM_IF_TYPE { PARAM_VALUE.MM_IF_TYPE } {
|
||||
# Procedure called to validate MM_IF_TYPE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.NUM_OFFLOAD { PARAM_VALUE.NUM_OFFLOAD } {
|
||||
# Procedure called to update NUM_OFFLOAD when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.NUM_OFFLOAD { PARAM_VALUE.NUM_OFFLOAD } {
|
||||
# Procedure called to validate NUM_OFFLOAD
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.NUM_OF_SDI { PARAM_VALUE.NUM_OF_SDI } {
|
||||
# Procedure called to update NUM_OF_SDI when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.NUM_OF_SDI { PARAM_VALUE.NUM_OF_SDI } {
|
||||
# Procedure called to validate NUM_OF_SDI
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.SDI_FIFO_ADDRESS_WIDTH { PARAM_VALUE.SDI_FIFO_ADDRESS_WIDTH } {
|
||||
# Procedure called to update SDI_FIFO_ADDRESS_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.SDI_FIFO_ADDRESS_WIDTH { PARAM_VALUE.SDI_FIFO_ADDRESS_WIDTH } {
|
||||
# Procedure called to validate SDI_FIFO_ADDRESS_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.SDO_FIFO_ADDRESS_WIDTH { PARAM_VALUE.SDO_FIFO_ADDRESS_WIDTH } {
|
||||
# Procedure called to update SDO_FIFO_ADDRESS_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.SDO_FIFO_ADDRESS_WIDTH { PARAM_VALUE.SDO_FIFO_ADDRESS_WIDTH } {
|
||||
# Procedure called to validate SDO_FIFO_ADDRESS_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.SYNC_FIFO_ADDRESS_WIDTH { PARAM_VALUE.SYNC_FIFO_ADDRESS_WIDTH } {
|
||||
# Procedure called to update SYNC_FIFO_ADDRESS_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.SYNC_FIFO_ADDRESS_WIDTH { PARAM_VALUE.SYNC_FIFO_ADDRESS_WIDTH } {
|
||||
# Procedure called to validate SYNC_FIFO_ADDRESS_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.CMD_FIFO_ADDRESS_WIDTH { MODELPARAM_VALUE.CMD_FIFO_ADDRESS_WIDTH PARAM_VALUE.CMD_FIFO_ADDRESS_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.CMD_FIFO_ADDRESS_WIDTH}] ${MODELPARAM_VALUE.CMD_FIFO_ADDRESS_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.SYNC_FIFO_ADDRESS_WIDTH { MODELPARAM_VALUE.SYNC_FIFO_ADDRESS_WIDTH PARAM_VALUE.SYNC_FIFO_ADDRESS_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.SYNC_FIFO_ADDRESS_WIDTH}] ${MODELPARAM_VALUE.SYNC_FIFO_ADDRESS_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.SDO_FIFO_ADDRESS_WIDTH { MODELPARAM_VALUE.SDO_FIFO_ADDRESS_WIDTH PARAM_VALUE.SDO_FIFO_ADDRESS_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.SDO_FIFO_ADDRESS_WIDTH}] ${MODELPARAM_VALUE.SDO_FIFO_ADDRESS_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.SDI_FIFO_ADDRESS_WIDTH { MODELPARAM_VALUE.SDI_FIFO_ADDRESS_WIDTH PARAM_VALUE.SDI_FIFO_ADDRESS_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.SDI_FIFO_ADDRESS_WIDTH}] ${MODELPARAM_VALUE.SDI_FIFO_ADDRESS_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.MM_IF_TYPE { MODELPARAM_VALUE.MM_IF_TYPE PARAM_VALUE.MM_IF_TYPE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.MM_IF_TYPE}] ${MODELPARAM_VALUE.MM_IF_TYPE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.ASYNC_SPI_CLK { MODELPARAM_VALUE.ASYNC_SPI_CLK PARAM_VALUE.ASYNC_SPI_CLK } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.ASYNC_SPI_CLK}] ${MODELPARAM_VALUE.ASYNC_SPI_CLK}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.NUM_OFFLOAD { MODELPARAM_VALUE.NUM_OFFLOAD PARAM_VALUE.NUM_OFFLOAD } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.NUM_OFFLOAD}] ${MODELPARAM_VALUE.NUM_OFFLOAD}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.OFFLOAD0_CMD_MEM_ADDRESS_WIDTH { MODELPARAM_VALUE.OFFLOAD0_CMD_MEM_ADDRESS_WIDTH PARAM_VALUE.OFFLOAD0_CMD_MEM_ADDRESS_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.OFFLOAD0_CMD_MEM_ADDRESS_WIDTH}] ${MODELPARAM_VALUE.OFFLOAD0_CMD_MEM_ADDRESS_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.OFFLOAD0_SDO_MEM_ADDRESS_WIDTH { MODELPARAM_VALUE.OFFLOAD0_SDO_MEM_ADDRESS_WIDTH PARAM_VALUE.OFFLOAD0_SDO_MEM_ADDRESS_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.OFFLOAD0_SDO_MEM_ADDRESS_WIDTH}] ${MODELPARAM_VALUE.OFFLOAD0_SDO_MEM_ADDRESS_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DATA_WIDTH { MODELPARAM_VALUE.DATA_WIDTH PARAM_VALUE.DATA_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DATA_WIDTH}] ${MODELPARAM_VALUE.DATA_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.NUM_OF_SDI { MODELPARAM_VALUE.NUM_OF_SDI PARAM_VALUE.NUM_OF_SDI } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.NUM_OF_SDI}] ${MODELPARAM_VALUE.NUM_OF_SDI}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.CFG_INFO_0 { MODELPARAM_VALUE.CFG_INFO_0 PARAM_VALUE.CFG_INFO_0 } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.CFG_INFO_0}] ${MODELPARAM_VALUE.CFG_INFO_0}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.CFG_INFO_1 { MODELPARAM_VALUE.CFG_INFO_1 PARAM_VALUE.CFG_INFO_1 } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.CFG_INFO_1}] ${MODELPARAM_VALUE.CFG_INFO_1}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.CFG_INFO_2 { MODELPARAM_VALUE.CFG_INFO_2 PARAM_VALUE.CFG_INFO_2 } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.CFG_INFO_2}] ${MODELPARAM_VALUE.CFG_INFO_2}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.CFG_INFO_3 { MODELPARAM_VALUE.CFG_INFO_3 PARAM_VALUE.CFG_INFO_3 } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.CFG_INFO_3}] ${MODELPARAM_VALUE.CFG_INFO_3}
|
||||
}
|
||||
|
||||
@@ -0,0 +1,11 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:busDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>analog.com</spirit:vendor>
|
||||
<spirit:library>interface</spirit:library>
|
||||
<spirit:name>spi_engine</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:directConnection>false</spirit:directConnection>
|
||||
<spirit:isAddressable>false</spirit:isAddressable>
|
||||
<spirit:maxMasters>1</spirit:maxMasters>
|
||||
<spirit:maxSlaves>1</spirit:maxSlaves>
|
||||
</spirit:busDefinition>
|
||||
@@ -0,0 +1,11 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:busDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>analog.com</spirit:vendor>
|
||||
<spirit:library>interface</spirit:library>
|
||||
<spirit:name>spi_engine_ctrl</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:directConnection>false</spirit:directConnection>
|
||||
<spirit:isAddressable>false</spirit:isAddressable>
|
||||
<spirit:maxMasters>1</spirit:maxMasters>
|
||||
<spirit:maxSlaves>1</spirit:maxSlaves>
|
||||
</spirit:busDefinition>
|
||||
@@ -0,0 +1,174 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:abstractionDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>analog.com</spirit:vendor>
|
||||
<spirit:library>interface</spirit:library>
|
||||
<spirit:name>spi_engine_ctrl_rtl</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="spi_engine_ctrl" spirit:version="1.0"/>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>cmd_ready</spirit:logicalName>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
</spirit:onSlave>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>cmd_valid</spirit:logicalName>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onSlave>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>cmd_data</spirit:logicalName>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>16</spirit:width>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>16</spirit:width>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onSlave>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>sdo_ready</spirit:logicalName>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
</spirit:onSlave>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>sdo_valid</spirit:logicalName>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onSlave>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>sdo_data</spirit:logicalName>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onSlave>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>sdi_ready</spirit:logicalName>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onSlave>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>sdi_valid</spirit:logicalName>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
</spirit:onSlave>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>sdi_data</spirit:logicalName>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
</spirit:onSlave>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>sync_ready</spirit:logicalName>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onSlave>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>sync_valid</spirit:logicalName>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
</spirit:onSlave>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>sync_data</spirit:logicalName>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>8</spirit:width>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>8</spirit:width>
|
||||
</spirit:onSlave>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
</spirit:ports>
|
||||
</spirit:abstractionDefinition>
|
||||
@@ -0,0 +1,100 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
`ifndef spi_engine_ctrl_v1_0
|
||||
`define spi_engine_ctrl_v1_0
|
||||
|
||||
package parameter_structs;
|
||||
|
||||
typedef struct packed {
|
||||
bit portEnabled;
|
||||
integer portWidth;
|
||||
}portConfig;
|
||||
|
||||
typedef struct packed {
|
||||
// <typeName> <LogicalName> = {<enablement>, <width>}
|
||||
portConfig sdo_data;
|
||||
portConfig sdi_data;
|
||||
}spi_engine_ctrl_v1_0_port_configuration;
|
||||
|
||||
parameter spi_engine_ctrl_v1_0_port_configuration spi_engine_ctrl_v1_0_default_port_configuration = '{sdo_data:'{1, -1}, sdi_data:'{1, -1}};
|
||||
|
||||
endpackage
|
||||
|
||||
interface spi_engine_ctrl_v1_0 #(parameter_structs::spi_engine_ctrl_v1_0_port_configuration port_configuration)();
|
||||
logic cmd_ready; //
|
||||
logic cmd_valid; //
|
||||
logic [15:0] cmd_data; //
|
||||
logic sdo_ready; //
|
||||
logic sdo_valid; //
|
||||
logic [port_configuration.sdo_data.portWidth-1:0] sdo_data; //
|
||||
logic sdi_ready; //
|
||||
logic sdi_valid; //
|
||||
logic [port_configuration.sdi_data.portWidth-1:0] sdi_data; //
|
||||
logic sync_ready; //
|
||||
logic sync_valid; //
|
||||
logic [7:0] sync_data; //
|
||||
|
||||
modport MASTER (
|
||||
input cmd_ready, sdo_ready, sdi_valid, sdi_data, sync_valid, sync_data,
|
||||
output cmd_valid, cmd_data, sdo_valid, sdo_data, sdi_ready, sync_ready
|
||||
);
|
||||
|
||||
modport SLAVE (
|
||||
input cmd_valid, cmd_data, sdo_valid, sdo_data, sdi_ready, sync_ready,
|
||||
output cmd_ready, sdo_ready, sdi_valid, sdi_data, sync_valid, sync_data
|
||||
);
|
||||
|
||||
modport MONITOR (
|
||||
input cmd_ready, cmd_valid, cmd_data, sdo_ready, sdo_valid, sdo_data, sdi_ready, sdi_valid, sdi_data, sync_ready, sync_valid, sync_data
|
||||
);
|
||||
|
||||
endinterface // spi_engine_ctrl_v1_0
|
||||
|
||||
`endif
|
||||
@@ -0,0 +1,11 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:busDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>analog.com</spirit:vendor>
|
||||
<spirit:library>interface</spirit:library>
|
||||
<spirit:name>spi_engine_offload_ctrl</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:directConnection>false</spirit:directConnection>
|
||||
<spirit:isAddressable>false</spirit:isAddressable>
|
||||
<spirit:maxMasters>1</spirit:maxMasters>
|
||||
<spirit:maxSlaves>1</spirit:maxSlaves>
|
||||
</spirit:busDefinition>
|
||||
@@ -0,0 +1,148 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:abstractionDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>analog.com</spirit:vendor>
|
||||
<spirit:library>interface</spirit:library>
|
||||
<spirit:name>spi_engine_offload_ctrl_rtl</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="spi_engine_offload_ctrl" spirit:version="1.0"/>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>cmd_wr_en</spirit:logicalName>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onSlave>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>cmd_wr_data</spirit:logicalName>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>16</spirit:width>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>16</spirit:width>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onSlave>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>sdo_wr_en</spirit:logicalName>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onSlave>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>sdo_wr_data</spirit:logicalName>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onSlave>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>mem_reset</spirit:logicalName>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onSlave>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>enable</spirit:logicalName>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onSlave>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>enabled</spirit:logicalName>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
</spirit:onSlave>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>sync_ready</spirit:logicalName>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onSlave>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>sync_valid</spirit:logicalName>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
</spirit:onSlave>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>sync_data</spirit:logicalName>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>8</spirit:width>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>8</spirit:width>
|
||||
</spirit:onSlave>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
</spirit:ports>
|
||||
</spirit:abstractionDefinition>
|
||||
@@ -0,0 +1,97 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
`ifndef spi_engine_offload_ctrl_v1_0
|
||||
`define spi_engine_offload_ctrl_v1_0
|
||||
|
||||
package parameter_structs;
|
||||
|
||||
typedef struct packed {
|
||||
bit portEnabled;
|
||||
integer portWidth;
|
||||
}portConfig;
|
||||
|
||||
typedef struct packed {
|
||||
// <typeName> <LogicalName> = {<enablement>, <width>}
|
||||
portConfig sdo_wr_data;
|
||||
}spi_engine_offload_ctrl_v1_0_port_configuration;
|
||||
|
||||
parameter spi_engine_offload_ctrl_v1_0_port_configuration spi_engine_offload_ctrl_v1_0_default_port_configuration = '{sdo_wr_data:'{1, -1}};
|
||||
|
||||
endpackage
|
||||
|
||||
interface spi_engine_offload_ctrl_v1_0 #(parameter_structs::spi_engine_offload_ctrl_v1_0_port_configuration port_configuration)();
|
||||
logic cmd_wr_en; //
|
||||
logic [15:0] cmd_wr_data; //
|
||||
logic sdo_wr_en; //
|
||||
logic [port_configuration.sdo_wr_data.portWidth-1:0] sdo_wr_data; //
|
||||
logic mem_reset; //
|
||||
logic enable; //
|
||||
logic enabled; //
|
||||
logic sync_ready; //
|
||||
logic sync_valid; //
|
||||
logic [7:0] sync_data; //
|
||||
|
||||
modport MASTER (
|
||||
input enabled, sync_valid, sync_data,
|
||||
output cmd_wr_en, cmd_wr_data, sdo_wr_en, sdo_wr_data, mem_reset, enable, sync_ready
|
||||
);
|
||||
|
||||
modport SLAVE (
|
||||
input cmd_wr_en, cmd_wr_data, sdo_wr_en, sdo_wr_data, mem_reset, enable, sync_ready,
|
||||
output enabled, sync_valid, sync_data
|
||||
);
|
||||
|
||||
modport MONITOR (
|
||||
input cmd_wr_en, cmd_wr_data, sdo_wr_en, sdo_wr_data, mem_reset, enable, enabled, sync_ready, sync_valid, sync_data
|
||||
);
|
||||
|
||||
endinterface // spi_engine_offload_ctrl_v1_0
|
||||
|
||||
`endif
|
||||
@@ -0,0 +1,90 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:abstractionDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>analog.com</spirit:vendor>
|
||||
<spirit:library>interface</spirit:library>
|
||||
<spirit:name>spi_engine_rtl</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="spi_engine" spirit:version="1.0"/>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>sclk</spirit:logicalName>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onSlave>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>sdo</spirit:logicalName>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onSlave>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>sdo_t</spirit:logicalName>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onSlave>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>sdi</spirit:logicalName>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
</spirit:onSlave>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>cs</spirit:logicalName>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onSlave>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>three_wire</spirit:logicalName>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onSlave>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
</spirit:ports>
|
||||
</spirit:abstractionDefinition>
|
||||
@@ -0,0 +1,94 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
`ifndef spi_engine_v1_0
|
||||
`define spi_engine_v1_0
|
||||
|
||||
package parameter_structs;
|
||||
|
||||
typedef struct packed {
|
||||
bit portEnabled;
|
||||
integer portWidth;
|
||||
}portConfig;
|
||||
|
||||
typedef struct packed {
|
||||
// <typeName> <LogicalName> = {<enablement>, <width>}
|
||||
portConfig sdi;
|
||||
portConfig cs;
|
||||
}spi_engine_v1_0_port_configuration;
|
||||
|
||||
parameter spi_engine_v1_0_port_configuration spi_engine_v1_0_default_port_configuration = '{sdi:'{1, -1}, cs:'{1, -1}};
|
||||
|
||||
endpackage
|
||||
|
||||
interface spi_engine_v1_0 #(parameter_structs::spi_engine_v1_0_port_configuration port_configuration)();
|
||||
logic sclk; //
|
||||
logic sdo; //
|
||||
logic sdo_t; //
|
||||
logic [port_configuration.sdi.portWidth-1:0] sdi; //
|
||||
logic [port_configuration.cs.portWidth-1:0] cs; //
|
||||
logic three_wire; //
|
||||
|
||||
modport MASTER (
|
||||
input sdi,
|
||||
output sclk, sdo, sdo_t, cs, three_wire
|
||||
);
|
||||
|
||||
modport SLAVE (
|
||||
input sclk, sdo, sdo_t, cs, three_wire,
|
||||
output sdi
|
||||
);
|
||||
|
||||
modport MONITOR (
|
||||
input sclk, sdo, sdo_t, sdi, cs, three_wire
|
||||
);
|
||||
|
||||
endinterface // spi_engine_v1_0
|
||||
|
||||
`endif
|
||||
@@ -0,0 +1,383 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>analog.com</spirit:vendor>
|
||||
<spirit:library>user</spirit:library>
|
||||
<spirit:name>spi_axis_reorder</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>s_axis</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axis_ready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axis_valid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axis_data</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>m_axis</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m_axis_ready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m_axis_valid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m_axis_data</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>s_axis_m_axis_signal_clock</spirit:name>
|
||||
<spirit:displayName>s_axis_m_axis_signal_clock</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>axis_aclk</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS_M_AXIS_SIGNAL_CLOCK.ASSOCIATED_BUSIF">s_axis:m_axis</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS_M_AXIS_SIGNAL_CLOCK.ASSOCIATED_RESET">axis_aresetn</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>s_axis_m_axis_signal_reset</spirit:name>
|
||||
<spirit:displayName>s_axis_m_axis_signal_reset</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>axis_aresetn</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS_M_AXIS_SIGNAL_RESET.POLARITY">ACTIVE_LOW</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
</spirit:busInterfaces>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
|
||||
<spirit:displayName>Synthesis</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
|
||||
<spirit:language>Verilog</spirit:language>
|
||||
<spirit:modelName>spi_axis_reorder</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>d53c278f</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:language>Verilog</spirit:language>
|
||||
<spirit:modelName>spi_axis_reorder</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>d53c278f</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_xpgui</spirit:name>
|
||||
<spirit:displayName>UI Layout</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>130431ad</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
</spirit:views>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:name>axis_aclk</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>axis_aresetn</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>s_axis_valid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>s_axis_ready</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
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</spirit:port>
|
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<spirit:port>
|
||||
<spirit:name>s_axis_data</spirit:name>
|
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<spirit:wire>
|
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<spirit:direction>in</spirit:direction>
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<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) * 32) - 1)">63</spirit:left>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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<spirit:driver>
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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</spirit:driver>
|
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</spirit:wire>
|
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</spirit:port>
|
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<spirit:port>
|
||||
<spirit:name>m_axis_valid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
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<spirit:wireTypeDefs>
|
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
|
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</spirit:wire>
|
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</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>m_axis_ready</spirit:name>
|
||||
<spirit:wire>
|
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<spirit:direction>in</spirit:direction>
|
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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</spirit:port>
|
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<spirit:port>
|
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<spirit:name>m_axis_data</spirit:name>
|
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<spirit:wire>
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<spirit:direction>out</spirit:direction>
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<spirit:vector>
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<spirit:left spirit:format="long">63</spirit:left>
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<spirit:right spirit:format="long">0</spirit:right>
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</spirit:vector>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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</spirit:port>
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</spirit:ports>
|
||||
<spirit:modelParameters>
|
||||
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
|
||||
<spirit:name>NUM_OF_LANES</spirit:name>
|
||||
<spirit:displayName>Num Of Lanes</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.NUM_OF_LANES">2</spirit:value>
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</spirit:modelParameter>
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</spirit:modelParameters>
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</spirit:model>
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<spirit:fileSets>
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<spirit:fileSet>
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<spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
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<spirit:file>
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<spirit:name>spi_axis_reorder.v</spirit:name>
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<spirit:fileType>verilogSource</spirit:fileType>
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<spirit:userFileType>CHECKSUM_d53c278f</spirit:userFileType>
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<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
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<spirit:name>spi_axis_reorder.v</spirit:name>
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<spirit:fileType>verilogSource</spirit:fileType>
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<spirit:fileSet>
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<spirit:name>xilinx_xpgui_view_fileset</spirit:name>
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<spirit:file>
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<spirit:name>xgui/spi_axis_reorder_v1_0.tcl</spirit:name>
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<spirit:fileType>tclSource</spirit:fileType>
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<spirit:userFileType>CHECKSUM_130431ad</spirit:userFileType>
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<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
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</spirit:file>
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</spirit:fileSet>
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</spirit:fileSets>
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<spirit:description>spi_axis_reorder_v1_0</spirit:description>
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<spirit:parameters>
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<spirit:parameter>
|
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<spirit:name>NUM_OF_LANES</spirit:name>
|
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<spirit:displayName>Num Of Lanes</spirit:displayName>
|
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<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.NUM_OF_LANES">2</spirit:value>
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</spirit:parameter>
|
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<spirit:parameter>
|
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<spirit:name>Component_Name</spirit:name>
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<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">spi_axis_reorder_v1_0</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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<xilinx:coreExtensions>
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<xilinx:family xilinx:lifeCycle="Production">qvirtex7</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">versal</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">kintex7l</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">qkintex7</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">qkintex7l</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">akintex7</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">qartix7</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">qzynq</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">azynq</xilinx:family>
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</xilinx:supportedFamilies>
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<xilinx:taxonomies>
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<xilinx:taxonomy>/Analog_Devices</xilinx:taxonomy>
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</xilinx:taxonomies>
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<xilinx:displayName>spi_axis_reorder_v1_0</xilinx:displayName>
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<xilinx:autoFamilySupportLevel>level_2</xilinx:autoFamilySupportLevel>
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<xilinx:definitionSource>package_project</xilinx:definitionSource>
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<xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
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<xilinx:vendorURL>http://www.analog.com</xilinx:vendorURL>
|
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<xilinx:coreRevision>1</xilinx:coreRevision>
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<xilinx:coreCreationDateTime>2025-04-30T13:52:18Z</xilinx:coreCreationDateTime>
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</xilinx:coreExtensions>
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<xilinx:packagingInfo>
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<xilinx:xilinxVersion>2024.1.2</xilinx:xilinxVersion>
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<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="afbeddb7"/>
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<xilinx:checksum xilinx:scope="ports" xilinx:value="db78853a"/>
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||||
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="197f2558"/>
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<xilinx:checksum xilinx:scope="parameters" xilinx:value="f0fce92c"/>
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</xilinx:packagingInfo>
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</spirit:vendorExtensions>
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</spirit:component>
|
||||
@@ -0,0 +1,140 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
// Re-ordering module for Flexi-SPI
|
||||
//
|
||||
module spi_axis_reorder #(
|
||||
|
||||
parameter [3:0] NUM_OF_LANES = 2
|
||||
) (
|
||||
input axis_aclk,
|
||||
input axis_aresetn,
|
||||
|
||||
input s_axis_valid,
|
||||
output s_axis_ready,
|
||||
input [(NUM_OF_LANES * 32)-1:0] s_axis_data,
|
||||
|
||||
output m_axis_valid,
|
||||
input m_axis_ready,
|
||||
output [63:0] m_axis_data
|
||||
);
|
||||
|
||||
// re-packager is always ready
|
||||
assign s_axis_ready = 1'b1;
|
||||
|
||||
genvar i, j;
|
||||
generate
|
||||
if (NUM_OF_LANES == 1) begin : g_reorder_1_lane_interleaved
|
||||
|
||||
reg wr_addr = 0;
|
||||
reg [63:0] axis_data_int;
|
||||
reg mem_is_full;
|
||||
|
||||
// address control
|
||||
// NOTE: ready is ignored, taking the fact that the module is always ready
|
||||
always @(posedge axis_aclk) begin
|
||||
if (axis_aresetn == 1'b0) begin
|
||||
wr_addr <= 1'b0;
|
||||
axis_data_int <= 64'b0;
|
||||
end else begin
|
||||
if ((s_axis_valid == 1'b1) && (s_axis_ready == 1'b1)) begin
|
||||
wr_addr <= wr_addr + 1'b1;
|
||||
axis_data_int <= (wr_addr) ? {s_axis_data, axis_data_int[31:0]} :
|
||||
{axis_data_int[63:32], s_axis_data};
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// latch the state of the memory
|
||||
always @(posedge axis_aclk) begin
|
||||
if (axis_aresetn == 1'b0) begin
|
||||
mem_is_full <= 1'b0;
|
||||
end else begin
|
||||
if ((wr_addr == 1'b1) && (s_axis_valid == 1'b1)) begin
|
||||
mem_is_full <= 1'b1;
|
||||
end else begin
|
||||
mem_is_full <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// reorder the interleaved data
|
||||
assign m_axis_valid = mem_is_full;
|
||||
for (i=0; i<32; i=i+1) begin
|
||||
assign m_axis_data[ i] = axis_data_int[2*i+1];
|
||||
assign m_axis_data[32+i] = axis_data_int[2*i];
|
||||
end
|
||||
|
||||
end else if (NUM_OF_LANES == 2) begin : g_reorder_2_lanes
|
||||
|
||||
assign m_axis_valid = s_axis_valid;
|
||||
assign m_axis_data = s_axis_data;
|
||||
|
||||
end else if (NUM_OF_LANES == 4) begin : g_reorder_4_lanes
|
||||
|
||||
assign m_axis_valid = s_axis_valid;
|
||||
for (i=0; i<16; i=i+1) begin
|
||||
// first channel
|
||||
assign m_axis_data[2*i ] = s_axis_data[32+i];
|
||||
assign m_axis_data[2*i+1] = s_axis_data[ i];
|
||||
// second channel
|
||||
assign m_axis_data[2*i+32] = s_axis_data[96+i];
|
||||
assign m_axis_data[2*i+33] = s_axis_data[64+i];
|
||||
end
|
||||
|
||||
end else if (NUM_OF_LANES == 8) begin : g_reorder_8_lanes
|
||||
|
||||
assign m_axis_valid = s_axis_valid;
|
||||
for (i=0; i<8; i=i+1) begin
|
||||
// first channel
|
||||
assign m_axis_data[4*i ] = s_axis_data[96+i];
|
||||
assign m_axis_data[4*i+1] = s_axis_data[64+i];
|
||||
assign m_axis_data[4*i+2] = s_axis_data[32+i];
|
||||
assign m_axis_data[4*i+3] = s_axis_data[ i];
|
||||
// second channel
|
||||
assign m_axis_data[4*i+32] = s_axis_data[224+i];
|
||||
assign m_axis_data[4*i+33] = s_axis_data[192+i];
|
||||
assign m_axis_data[4*i+34] = s_axis_data[160+i];
|
||||
assign m_axis_data[4*i+35] = s_axis_data[128+i];
|
||||
end
|
||||
|
||||
end else begin
|
||||
// WARNING: Invalid configuration, leave everybody in the air
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,25 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
|
||||
ipgui::add_param $IPINST -name "NUM_OF_LANES" -parent ${Page_0}
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.NUM_OF_LANES { PARAM_VALUE.NUM_OF_LANES } {
|
||||
# Procedure called to update NUM_OF_LANES when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.NUM_OF_LANES { PARAM_VALUE.NUM_OF_LANES } {
|
||||
# Procedure called to validate NUM_OF_LANES
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.NUM_OF_LANES { MODELPARAM_VALUE.NUM_OF_LANES PARAM_VALUE.NUM_OF_LANES } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.NUM_OF_LANES}] ${MODELPARAM_VALUE.NUM_OF_LANES}
|
||||
}
|
||||
|
||||
@@ -0,0 +1,807 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>analog.com</spirit:vendor>
|
||||
<spirit:library>user</spirit:library>
|
||||
<spirit:name>spi_engine_execution</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>ctrl</spirit:name>
|
||||
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="spi_engine_ctrl" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="spi_engine_ctrl_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>cmd_ready</spirit:name>
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||||
</spirit:logicalPort>
|
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<spirit:physicalPort>
|
||||
<spirit:name>cmd_ready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>cmd_valid</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>cmd_valid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>cmd_data</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>cmd</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>sdo_ready</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sdo_data_ready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>sdo_valid</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sdo_data_valid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>sdo_data</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sdo_data</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>sdi_ready</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sdi_data_ready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>sdi_valid</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sdi_data_valid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>sdi_data</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sdi_data</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>sync_ready</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sync_ready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>sync_valid</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sync_valid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>sync_data</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sync</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>ctrl_signal_clock</spirit:name>
|
||||
<spirit:displayName>ctrl_signal_clock</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>clk</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.CTRL_SIGNAL_CLOCK.ASSOCIATED_BUSIF">ctrl</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.CTRL_SIGNAL_CLOCK.ASSOCIATED_RESET">resetn</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>ctrl_signal_reset</spirit:name>
|
||||
<spirit:displayName>ctrl_signal_reset</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>resetn</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.CTRL_SIGNAL_RESET.POLARITY">ACTIVE_LOW</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>spi</spirit:name>
|
||||
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="spi_engine" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="spi_engine_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>sclk</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sclk</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>sdi</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sdi</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>sdo</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sdo</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>sdo_t</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sdo_t</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>three_wire</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>three_wire</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>cs</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>cs</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>spi_signal_clock</spirit:name>
|
||||
<spirit:displayName>spi_signal_clock</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>clk</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.SPI_SIGNAL_CLOCK.ASSOCIATED_BUSIF">spi</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.SPI_SIGNAL_CLOCK.ASSOCIATED_RESET">resetn</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>spi_signal_reset</spirit:name>
|
||||
<spirit:displayName>spi_signal_reset</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>resetn</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.SPI_SIGNAL_RESET.POLARITY">ACTIVE_LOW</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
</spirit:busInterfaces>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
|
||||
<spirit:displayName>Synthesis</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
|
||||
<spirit:language>Verilog</spirit:language>
|
||||
<spirit:modelName>spi_engine_execution</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>b0f6c79d</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:language>Verilog</spirit:language>
|
||||
<spirit:modelName>spi_engine_execution</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>b0f6c79d</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_xpgui</spirit:name>
|
||||
<spirit:displayName>UI Layout</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>3d941b35</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
</spirit:views>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:name>clk</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>resetn</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>active</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>reg</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>cmd_ready</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>cmd_valid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>cmd</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">15</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>sdo_data_valid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>sdo_data_ready</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>reg</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>sdo_data</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.DATA_WIDTH')) - 1)">7</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>sdi_data_ready</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>sdi_data_valid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>reg</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>sdi_data</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.NUM_OF_SDI')) * spirit:decode(id('MODELPARAM_VALUE.DATA_WIDTH'))) - 1)">7</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>sync_ready</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>sync_valid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>reg</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>sync</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">7</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>echo_sclk</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:portInfo>
|
||||
<xilinx:enablement>
|
||||
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.echo_sclk" xilinx:dependency="ECHO_SCLK">false</xilinx:isEnabled>
|
||||
</xilinx:enablement>
|
||||
</xilinx:portInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>sclk</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>reg</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>sdo</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>reg</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>sdo_t</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>reg</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>sdi</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_SDI')) - 1)">0</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>cs</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CS')) - 1)">0</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>reg</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>three_wire</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>reg</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
</spirit:ports>
|
||||
<spirit:modelParameters>
|
||||
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
|
||||
<spirit:name>NUM_OF_CS</spirit:name>
|
||||
<spirit:displayName>Num Of Cs</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.NUM_OF_CS">1</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>DEFAULT_SPI_CFG</spirit:name>
|
||||
<spirit:displayName>Default Spi Cfg</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DEFAULT_SPI_CFG">0</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>DEFAULT_CLK_DIV</spirit:name>
|
||||
<spirit:displayName>Default Clk Div</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DEFAULT_CLK_DIV">0</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>DATA_WIDTH</spirit:name>
|
||||
<spirit:displayName>Data Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DATA_WIDTH">8</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>NUM_OF_SDI</spirit:name>
|
||||
<spirit:displayName>Num Of Sdi</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.NUM_OF_SDI">1</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>SDO_DEFAULT</spirit:name>
|
||||
<spirit:displayName>Sdo Default</spirit:displayName>
|
||||
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SDO_DEFAULT" spirit:bitStringLength="1">"0"</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>ECHO_SCLK</spirit:name>
|
||||
<spirit:displayName>Echo Sclk</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.ECHO_SCLK">false</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>SDI_DELAY</spirit:name>
|
||||
<spirit:displayName>Sdi Delay</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SDI_DELAY">false</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
</spirit:modelParameters>
|
||||
</spirit:model>
|
||||
<spirit:choices>
|
||||
<spirit:choice>
|
||||
<spirit:name>choice_list_b71134be</spirit:name>
|
||||
<spirit:enumeration>"0"</spirit:enumeration>
|
||||
<spirit:enumeration>"1"</spirit:enumeration>
|
||||
</spirit:choice>
|
||||
<spirit:choice>
|
||||
<spirit:name>choice_list_dd9ee503</spirit:name>
|
||||
<spirit:enumeration>0</spirit:enumeration>
|
||||
<spirit:enumeration>1</spirit:enumeration>
|
||||
<spirit:enumeration>2</spirit:enumeration>
|
||||
<spirit:enumeration>3</spirit:enumeration>
|
||||
</spirit:choice>
|
||||
</spirit:choices>
|
||||
<spirit:fileSets>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>spi_engine_execution_constr.ttcl</spirit:name>
|
||||
<spirit:userFileType>ttcl</spirit:userFileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>spi_engine_execution.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
<spirit:userFileType>CHECKSUM_b0f6c79d</spirit:userFileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>spi_engine_execution.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_xpgui_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>xgui/spi_engine_execution_v1_0.tcl</spirit:name>
|
||||
<spirit:fileType>tclSource</spirit:fileType>
|
||||
<spirit:userFileType>CHECKSUM_b2ce64e5</spirit:userFileType>
|
||||
<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
</spirit:fileSets>
|
||||
<spirit:description>spi_engine_execution_v1_0</spirit:description>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>NUM_OF_CS</spirit:name>
|
||||
<spirit:displayName>Number of CSN lines</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.NUM_OF_CS" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>DEFAULT_SPI_CFG</spirit:name>
|
||||
<spirit:displayName>Default SPI mode</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DEFAULT_SPI_CFG" spirit:choiceRef="choice_list_dd9ee503">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>DEFAULT_CLK_DIV</spirit:name>
|
||||
<spirit:displayName>Default SCLK divider</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DEFAULT_CLK_DIV" spirit:minimum="0" spirit:maximum="255" spirit:rangeType="long">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>DATA_WIDTH</spirit:name>
|
||||
<spirit:displayName>Parallel data width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DATA_WIDTH" spirit:minimum="8" spirit:maximum="32" spirit:rangeType="long">8</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>NUM_OF_SDI</spirit:name>
|
||||
<spirit:displayName>Number of MISO</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.NUM_OF_SDI" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>SDO_DEFAULT</spirit:name>
|
||||
<spirit:displayName>MOSI default level</spirit:displayName>
|
||||
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.SDO_DEFAULT" spirit:choiceRef="choice_list_b71134be" spirit:bitStringLength="1">"0"</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ECHO_SCLK</spirit:name>
|
||||
<spirit:displayName>Echoed SCLK</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.ECHO_SCLK">false</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>SDI_DELAY</spirit:name>
|
||||
<spirit:displayName>Delay MISO latching</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.SDI_DELAY">false</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>Component_Name</spirit:name>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">spi_engine_execution_v1_0</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:coreExtensions>
|
||||
<xilinx:supportedFamilies>
|
||||
<xilinx:family xilinx:lifeCycle="Production">virtex7</xilinx:family>
|
||||
</xilinx:supportedFamilies>
|
||||
<xilinx:taxonomies>
|
||||
<xilinx:taxonomy>/Analog_Devices</xilinx:taxonomy>
|
||||
</xilinx:taxonomies>
|
||||
<xilinx:displayName>spi_engine_execution_v1_0</xilinx:displayName>
|
||||
<xilinx:autoFamilySupportLevel>level_2</xilinx:autoFamilySupportLevel>
|
||||
<xilinx:definitionSource>package_project</xilinx:definitionSource>
|
||||
<xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
|
||||
<xilinx:vendorURL>https://wiki.analog.com/resources/fpga/peripherals/spi_engine/engine</xilinx:vendorURL>
|
||||
<xilinx:coreRevision>1</xilinx:coreRevision>
|
||||
<xilinx:coreCreationDateTime>2025-04-30T13:51:37Z</xilinx:coreCreationDateTime>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2024.1.2</xilinx:xilinxVersion>
|
||||
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="7d9e4b99"/>
|
||||
<xilinx:checksum xilinx:scope="ports" xilinx:value="ca4aa6ef"/>
|
||||
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="0dd4e337"/>
|
||||
<xilinx:checksum xilinx:scope="parameters" xilinx:value="0194bdcd"/>
|
||||
</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
@@ -0,0 +1,635 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2015-2024 Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module spi_engine_execution #(
|
||||
|
||||
parameter NUM_OF_CS = 1,
|
||||
parameter DEFAULT_SPI_CFG = 0,
|
||||
parameter DEFAULT_CLK_DIV = 0,
|
||||
parameter DATA_WIDTH = 8, // Valid data widths values are 8/16/24/32
|
||||
parameter NUM_OF_SDI = 1,
|
||||
parameter [0:0] SDO_DEFAULT = 1'b0,
|
||||
parameter ECHO_SCLK = 0,
|
||||
parameter [1:0] SDI_DELAY = 2'b00
|
||||
) (
|
||||
input clk,
|
||||
input resetn,
|
||||
|
||||
output reg active,
|
||||
|
||||
output cmd_ready,
|
||||
input cmd_valid,
|
||||
input [15:0] cmd,
|
||||
|
||||
input sdo_data_valid,
|
||||
output reg sdo_data_ready,
|
||||
input [(DATA_WIDTH-1):0] sdo_data,
|
||||
|
||||
input sdi_data_ready,
|
||||
output reg sdi_data_valid,
|
||||
output [(NUM_OF_SDI * DATA_WIDTH)-1:0] sdi_data,
|
||||
|
||||
input sync_ready,
|
||||
output reg sync_valid,
|
||||
output [7:0] sync,
|
||||
|
||||
input echo_sclk,
|
||||
output reg sclk,
|
||||
output reg sdo,
|
||||
output reg sdo_t,
|
||||
input [NUM_OF_SDI-1:0] sdi,
|
||||
output reg [NUM_OF_CS-1:0] cs,
|
||||
output reg three_wire
|
||||
);
|
||||
|
||||
localparam CMD_TRANSFER = 3'b000;
|
||||
localparam CMD_CHIPSELECT = 3'b001;
|
||||
localparam CMD_WRITE = 3'b010;
|
||||
localparam CMD_MISC = 3'b011;
|
||||
localparam CMD_CS_INV = 3'b100;
|
||||
|
||||
localparam MISC_SYNC = 1'b0;
|
||||
localparam MISC_SLEEP = 1'b1;
|
||||
|
||||
localparam REG_CLK_DIV = 2'b00;
|
||||
localparam REG_CONFIG = 2'b01;
|
||||
localparam REG_WORD_LENGTH = 2'b10;
|
||||
|
||||
localparam BIT_COUNTER_WIDTH = DATA_WIDTH > 16 ? 5 :
|
||||
DATA_WIDTH > 8 ? 4 : 3;
|
||||
|
||||
localparam BIT_COUNTER_CARRY = 2** (BIT_COUNTER_WIDTH + 1);
|
||||
localparam BIT_COUNTER_CLEAR = {{8{1'b1}}, {BIT_COUNTER_WIDTH{1'b0}}, 1'b1};
|
||||
|
||||
reg sclk_int = 1'b0;
|
||||
wire sdo_int_s;
|
||||
reg sdo_t_int = 1'b0;
|
||||
|
||||
reg idle;
|
||||
|
||||
reg [7:0] clk_div_counter = 'h00;
|
||||
reg [7:0] clk_div_counter_next = 'h00;
|
||||
reg clk_div_last;
|
||||
|
||||
reg [(BIT_COUNTER_WIDTH+8):0] counter = 'h00;
|
||||
|
||||
wire [7:0] sleep_counter = counter[(BIT_COUNTER_WIDTH+8):(BIT_COUNTER_WIDTH+1)];
|
||||
wire [1:0] cs_sleep_counter = counter[(BIT_COUNTER_WIDTH+2):(BIT_COUNTER_WIDTH+1)];
|
||||
wire [(BIT_COUNTER_WIDTH-1):0] bit_counter = counter[BIT_COUNTER_WIDTH:1];
|
||||
wire [7:0] transfer_counter = counter[(BIT_COUNTER_WIDTH+8):(BIT_COUNTER_WIDTH+1)];
|
||||
wire ntx_rx = counter[0];
|
||||
|
||||
reg trigger = 1'b0;
|
||||
reg trigger_next = 1'b0;
|
||||
reg wait_for_io = 1'b0;
|
||||
reg transfer_active = 1'b0;
|
||||
|
||||
wire last_bit;
|
||||
wire first_bit;
|
||||
reg last_transfer;
|
||||
reg [7:0] word_length = DATA_WIDTH;
|
||||
reg [7:0] left_aligned = 8'b0;
|
||||
wire end_of_word;
|
||||
|
||||
reg [7:0] sdi_counter = 8'b0;
|
||||
|
||||
assign first_bit = ((bit_counter == 'h0) || (bit_counter == word_length));
|
||||
|
||||
reg [15:0] cmd_d1;
|
||||
|
||||
reg cpha = DEFAULT_SPI_CFG[0];
|
||||
reg cpol = DEFAULT_SPI_CFG[1];
|
||||
reg [7:0] clk_div = DEFAULT_CLK_DIV;
|
||||
|
||||
reg [NUM_OF_CS-1:0] cs_inv_mask_reg = 'h0;
|
||||
|
||||
reg sdo_enabled = 1'b0;
|
||||
reg sdi_enabled = 1'b0;
|
||||
|
||||
reg [(DATA_WIDTH-1):0] data_sdo_shift = 'h0;
|
||||
|
||||
reg [SDI_DELAY+1:0] trigger_rx_d = {(SDI_DELAY+2){1'b0}};
|
||||
|
||||
wire [2:0] inst = cmd[14:12];
|
||||
wire [2:0] inst_d1 = cmd_d1[14:12];
|
||||
|
||||
wire exec_cmd = cmd_ready && cmd_valid;
|
||||
wire exec_transfer_cmd = exec_cmd && inst == CMD_TRANSFER;
|
||||
wire exec_cs_inv_cmd = exec_cmd && inst == CMD_CS_INV;
|
||||
wire exec_write_cmd = exec_cmd && inst == CMD_WRITE;
|
||||
wire exec_chipselect_cmd = exec_cmd && inst == CMD_CHIPSELECT;
|
||||
wire exec_misc_cmd = exec_cmd && inst == CMD_MISC;
|
||||
wire exec_sync_cmd = exec_misc_cmd && cmd[8] == MISC_SYNC;
|
||||
|
||||
wire trigger_tx;
|
||||
wire trigger_rx;
|
||||
|
||||
wire sleep_counter_compare;
|
||||
wire cs_sleep_counter_compare;
|
||||
wire cs_sleep_early_exit;
|
||||
reg cs_sleep_repeat;
|
||||
reg cs_active;
|
||||
|
||||
wire io_ready1;
|
||||
wire io_ready2;
|
||||
wire trigger_rx_s;
|
||||
|
||||
wire last_sdi_bit;
|
||||
wire end_of_sdi_latch;
|
||||
|
||||
(* direct_enable = "yes" *) wire cs_gen;
|
||||
|
||||
assign cs_gen = inst_d1 == CMD_CHIPSELECT
|
||||
&& ((cs_sleep_counter_compare == 1'b1) || cs_sleep_early_exit)
|
||||
&& (cs_sleep_repeat == 1'b0)
|
||||
&& (idle == 1'b0);
|
||||
assign cmd_ready = idle;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (exec_transfer_cmd) begin
|
||||
sdo_enabled <= cmd[8];
|
||||
sdi_enabled <= cmd[9];
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (cmd_ready & cmd_valid)
|
||||
cmd_d1 <= cmd;
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (resetn == 1'b0) begin
|
||||
active <= 1'b0;
|
||||
end else begin
|
||||
if (exec_cmd == 1'b1)
|
||||
active <= 1'b1;
|
||||
else if (sync_ready == 1'b1 && sync_valid == 1'b1)
|
||||
active <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
// Load the interface configurations from the 'Configuration Write'
|
||||
// instruction
|
||||
always @(posedge clk) begin
|
||||
if (resetn == 1'b0) begin
|
||||
cpha <= DEFAULT_SPI_CFG[0];
|
||||
cpol <= DEFAULT_SPI_CFG[1];
|
||||
three_wire <= DEFAULT_SPI_CFG[2];
|
||||
clk_div <= DEFAULT_CLK_DIV;
|
||||
word_length <= DATA_WIDTH;
|
||||
left_aligned <= 8'b0;
|
||||
end else if (exec_write_cmd == 1'b1) begin
|
||||
if (cmd[9:8] == REG_CONFIG) begin
|
||||
cpha <= cmd[0];
|
||||
cpol <= cmd[1];
|
||||
three_wire <= cmd[2];
|
||||
end else if (cmd[9:8] == REG_CLK_DIV) begin
|
||||
clk_div <= cmd[7:0];
|
||||
end else if (cmd[9:8] == REG_WORD_LENGTH) begin
|
||||
// the max value of this reg must be DATA_WIDTH
|
||||
word_length <= cmd[7:0];
|
||||
left_aligned <= DATA_WIDTH - cmd[7:0];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if ((clk_div_last == 1'b0 && idle == 1'b0 && wait_for_io == 1'b0 &&
|
||||
clk_div_counter == 'h01) || clk_div == 'h00)
|
||||
clk_div_last <= 1'b1;
|
||||
else
|
||||
clk_div_last <= 1'b0;
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (clk_div_last == 1'b1 || idle == 1'b1 || wait_for_io == 1'b1) begin
|
||||
clk_div_counter <= clk_div;
|
||||
trigger <= 1'b1;
|
||||
end else begin
|
||||
clk_div_counter <= clk_div_counter - 1'b1;
|
||||
trigger <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
assign trigger_tx = trigger == 1'b1 && ntx_rx == 1'b0;
|
||||
assign trigger_rx = trigger == 1'b1 && ntx_rx == 1'b1;
|
||||
|
||||
assign sleep_counter_compare = sleep_counter == cmd_d1[7:0];
|
||||
assign cs_sleep_counter_compare = cs_sleep_counter == cmd_d1[9:8];
|
||||
assign cs_sleep_early_exit = (cmd_d1[9:8] == 2'b00);
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (resetn == 1'b0) begin
|
||||
cs_sleep_repeat <= 1'b0;
|
||||
end else begin
|
||||
if (idle) begin
|
||||
cs_sleep_repeat <= 1'b0;
|
||||
end else if (cs_sleep_counter_compare && (inst_d1 == CMD_CHIPSELECT)) begin
|
||||
cs_sleep_repeat <= !cs_sleep_repeat;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (idle == 1'b1 || (cs_sleep_counter_compare && !cs_sleep_repeat && inst_d1 == CMD_CHIPSELECT)) begin
|
||||
counter <= 'h00;
|
||||
end else if (clk_div_last == 1'b1 && wait_for_io == 1'b0) begin
|
||||
if (bit_counter == word_length && transfer_active) begin
|
||||
counter <= (counter & BIT_COUNTER_CLEAR) + 'h1 + BIT_COUNTER_CARRY;
|
||||
end else begin
|
||||
counter <= counter + (transfer_active ? 'h1 : (2**BIT_COUNTER_WIDTH));
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (resetn == 1'b0) begin
|
||||
idle <= 1'b1;
|
||||
end else begin
|
||||
if (exec_transfer_cmd || exec_chipselect_cmd || exec_misc_cmd) begin
|
||||
idle <= 1'b0;
|
||||
end else begin
|
||||
case (inst_d1)
|
||||
CMD_TRANSFER: begin
|
||||
if (transfer_active == 1'b0 && wait_for_io == 1'b0 && end_of_sdi_latch == 1'b1)
|
||||
idle <= 1'b1;
|
||||
end
|
||||
CMD_CHIPSELECT: begin
|
||||
if ((cs_sleep_counter_compare && cs_sleep_repeat) || cs_sleep_early_exit)
|
||||
idle <= 1'b1;
|
||||
end
|
||||
CMD_MISC: begin
|
||||
case (cmd_d1[8])
|
||||
MISC_SLEEP: begin
|
||||
if (sleep_counter_compare)
|
||||
idle <= 1'b1;
|
||||
end
|
||||
MISC_SYNC: begin
|
||||
if (sync_ready)
|
||||
idle <= 1'b1;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk ) begin
|
||||
if (resetn == 1'b0) begin
|
||||
cs_inv_mask_reg <= 'h0;
|
||||
end else begin
|
||||
if (exec_cs_inv_cmd == 1'b1) begin
|
||||
cs_inv_mask_reg <= cmd[NUM_OF_CS-1:0];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (resetn == 1'b0) begin
|
||||
cs <= 'hff;
|
||||
end else if (cs_gen) begin
|
||||
cs <= cmd_d1[NUM_OF_CS-1:0]^cs_inv_mask_reg[NUM_OF_CS-1:0];
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (resetn == 1'b0) begin
|
||||
sync_valid <= 1'b0;
|
||||
end else begin
|
||||
if (exec_sync_cmd == 1'b1) begin
|
||||
sync_valid <= 1'b1;
|
||||
end else if (sync_ready == 1'b1) begin
|
||||
sync_valid <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign sync = cmd_d1[7:0];
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (resetn == 1'b0)
|
||||
sdo_data_ready <= 1'b0;
|
||||
else if (sdo_enabled == 1'b1 && first_bit == 1'b1 && trigger_tx == 1'b1 && transfer_active == 1'b1)
|
||||
sdo_data_ready <= 1'b1;
|
||||
else if (sdo_data_valid == 1'b1)
|
||||
sdo_data_ready <= 1'b0;
|
||||
end
|
||||
|
||||
assign io_ready1 = (sdi_data_valid == 1'b0 || sdi_data_ready == 1'b1) &&
|
||||
(sdo_enabled == 1'b0 || last_transfer == 1'b1 || sdo_data_valid == 1'b1);
|
||||
assign io_ready2 = (sdi_enabled == 1'b0 || sdi_data_ready == 1'b1) &&
|
||||
(sdo_enabled == 1'b0 || last_transfer == 1'b1 || sdo_data_valid == 1'b1);
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (idle == 1'b1) begin
|
||||
last_transfer <= 1'b0;
|
||||
end else if (trigger_tx == 1'b1 && transfer_active == 1'b1) begin
|
||||
if (transfer_counter == cmd_d1[7:0])
|
||||
last_transfer <= 1'b1;
|
||||
else
|
||||
last_transfer <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (resetn == 1'b0) begin
|
||||
transfer_active <= 1'b0;
|
||||
wait_for_io <= 1'b0;
|
||||
end else begin
|
||||
if (exec_transfer_cmd == 1'b1) begin
|
||||
wait_for_io <= 1'b1;
|
||||
transfer_active <= 1'b0;
|
||||
end else if (wait_for_io == 1'b1 && io_ready1 == 1'b1) begin
|
||||
wait_for_io <= 1'b0;
|
||||
if (last_transfer == 1'b0)
|
||||
transfer_active <= 1'b1;
|
||||
else
|
||||
transfer_active <= 1'b0;
|
||||
end else if (transfer_active == 1'b1 && end_of_word == 1'b1) begin
|
||||
if (last_transfer == 1'b1 || io_ready2 == 1'b0)
|
||||
transfer_active <= 1'b0;
|
||||
if (io_ready2 == 1'b0)
|
||||
wait_for_io <= 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (transfer_active == 1'b1 || wait_for_io == 1'b1)
|
||||
begin
|
||||
sdo_t_int <= ~sdo_enabled;
|
||||
end else begin
|
||||
sdo_t_int <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
// Load the SDO parallel data into the SDO shift register. In case of a custom
|
||||
// data width, additional bit shifting must done at load.
|
||||
always @(posedge clk) begin
|
||||
if ((inst_d1 == CMD_TRANSFER) && (!sdo_enabled)) begin
|
||||
data_sdo_shift <= {DATA_WIDTH{SDO_DEFAULT}};
|
||||
end else if (transfer_active == 1'b1 && trigger_tx == 1'b1) begin
|
||||
if (first_bit == 1'b1)
|
||||
data_sdo_shift <= sdo_data << left_aligned;
|
||||
else
|
||||
data_sdo_shift <= {data_sdo_shift[(DATA_WIDTH-2):0], 1'b0};
|
||||
end
|
||||
end
|
||||
|
||||
assign sdo_int_s = data_sdo_shift[DATA_WIDTH-1];
|
||||
|
||||
// In case of an interface with high clock rate (SCLK > 50MHz), the latch of
|
||||
// the SDI line can be delayed with 1, 2 or 3 SPI core clock cycle.
|
||||
// Taking the fact that in high SCLK frequencies the pre-scaler most likely will
|
||||
// be set to 0, to reduce the core clock's speed, this delay will mean that SDI will
|
||||
// be latched at one of the next consecutive SCLK edge.
|
||||
|
||||
always @(posedge clk) begin
|
||||
trigger_rx_d <= {trigger_rx_d, trigger_rx};
|
||||
end
|
||||
|
||||
assign trigger_rx_s = trigger_rx_d[SDI_DELAY+1];
|
||||
|
||||
// Load the serial data into SDI shift register(s), then link it to the output
|
||||
// register of the module
|
||||
// NOTE: ECHO_SCLK mode can be used when the SCLK line is looped back to the FPGA
|
||||
// through an other level shifter, in order to remove the round-trip timing delays
|
||||
// introduced by the level shifters. This can improve the timing significantly
|
||||
// on higher SCLK rates. Devices like ad4630 have an echod SCLK, which can be
|
||||
// used to latch the MISO lines, improving the overall timing margin of the
|
||||
// interface.
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (!resetn) begin // set cs_active during reset for a cycle to clear shift reg
|
||||
cs_active <= 1;
|
||||
end else begin
|
||||
cs_active <= ~(&cmd_d1[NUM_OF_CS-1:0]) & cs_gen;
|
||||
end
|
||||
end
|
||||
|
||||
genvar i;
|
||||
|
||||
// NOTE: SPI configuration (CPOL/PHA) is only hardware configurable at this point
|
||||
generate
|
||||
if (ECHO_SCLK == 1) begin : g_echo_sclk_miso_latch
|
||||
|
||||
reg [7:0] sdi_counter_d = 8'b0;
|
||||
reg [7:0] sdi_transfer_counter = 8'b0;
|
||||
reg [7:0] num_of_transfers = 8'b0;
|
||||
reg [(NUM_OF_SDI * DATA_WIDTH)-1:0] sdi_data_latch = {(NUM_OF_SDI * DATA_WIDTH){1'b0}};
|
||||
|
||||
if ((DEFAULT_SPI_CFG[1:0] == 2'b01) || (DEFAULT_SPI_CFG[1:0] == 2'b10)) begin : g_echo_miso_nshift_reg
|
||||
|
||||
// MISO shift register runs on negative echo_sclk
|
||||
for (i=0; i<NUM_OF_SDI; i=i+1) begin: g_sdi_shift_reg
|
||||
reg [DATA_WIDTH-1:0] data_sdi_shift;
|
||||
|
||||
always @(negedge echo_sclk or posedge cs_active) begin
|
||||
if (cs_active) begin
|
||||
data_sdi_shift <= 0;
|
||||
end else begin
|
||||
data_sdi_shift <= {data_sdi_shift, sdi[i]};
|
||||
end
|
||||
end
|
||||
|
||||
// intended LATCH
|
||||
always @(negedge echo_sclk) begin
|
||||
if (last_sdi_bit)
|
||||
sdi_data_latch[i*DATA_WIDTH+:DATA_WIDTH] <= {data_sdi_shift, sdi[i]};
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
always @(posedge echo_sclk or posedge cs_active) begin
|
||||
if (cs_active) begin
|
||||
sdi_counter <= 8'b0;
|
||||
sdi_counter_d <= 8'b0;
|
||||
end else begin
|
||||
sdi_counter <= (sdi_counter == word_length-1) ? 8'b0 : sdi_counter + 1'b1;
|
||||
sdi_counter_d <= sdi_counter;
|
||||
end
|
||||
end
|
||||
|
||||
end else begin : g_echo_miso_pshift_reg
|
||||
|
||||
// MISO shift register runs on positive echo_sclk
|
||||
for (i=0; i<NUM_OF_SDI; i=i+1) begin: g_sdi_shift_reg
|
||||
reg [DATA_WIDTH-1:0] data_sdi_shift;
|
||||
always @(posedge echo_sclk or posedge cs_active) begin
|
||||
if (cs_active) begin
|
||||
data_sdi_shift <= 0;
|
||||
end else begin
|
||||
data_sdi_shift <= {data_sdi_shift, sdi[i]};
|
||||
end
|
||||
end
|
||||
// intended LATCH
|
||||
always @(posedge echo_sclk) begin
|
||||
if (last_sdi_bit)
|
||||
sdi_data_latch[i*DATA_WIDTH+:DATA_WIDTH] <= data_sdi_shift;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge echo_sclk or posedge cs_active) begin
|
||||
if (cs_active) begin
|
||||
sdi_counter <= 8'b0;
|
||||
sdi_counter_d <= 8'b0;
|
||||
end else begin
|
||||
sdi_counter <= (sdi_counter == word_length-1) ? 8'b0 : sdi_counter + 1'b1;
|
||||
sdi_counter_d <= sdi_counter;
|
||||
end
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
assign sdi_data = sdi_data_latch;
|
||||
assign last_sdi_bit = (sdi_counter == 0) && (sdi_counter_d == word_length-1);
|
||||
|
||||
// sdi_data_valid is synchronous to SPI clock, so synchronize the
|
||||
// last_sdi_bit to SPI clock
|
||||
|
||||
reg [3:0] last_sdi_bit_m = 4'b0;
|
||||
always @(posedge clk) begin
|
||||
if (cs_active) begin
|
||||
last_sdi_bit_m <= 4'b0;
|
||||
end else begin
|
||||
last_sdi_bit_m <= {last_sdi_bit_m, last_sdi_bit};
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (cs_active) begin
|
||||
sdi_data_valid <= 1'b0;
|
||||
end else if (sdi_enabled == 1'b1 &&
|
||||
last_sdi_bit_m[3] == 1'b0 &&
|
||||
last_sdi_bit_m[2] == 1'b1) begin
|
||||
sdi_data_valid <= 1'b1;
|
||||
end else if (sdi_data_ready == 1'b1) begin
|
||||
sdi_data_valid <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (cs_active) begin
|
||||
num_of_transfers <= 8'b0;
|
||||
end else begin
|
||||
if (cmd_d1[15:12] == 4'b0) begin
|
||||
num_of_transfers <= cmd_d1[7:0] + 1'b1; // cmd_d1 contains the NUM_OF_TRANSFERS - 1
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (cs_active) begin
|
||||
sdi_transfer_counter <= 0;
|
||||
end else if (last_sdi_bit_m[2] == 1'b0 &&
|
||||
last_sdi_bit_m[1] == 1'b1) begin
|
||||
sdi_transfer_counter <= sdi_transfer_counter + 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
assign end_of_sdi_latch = last_sdi_bit_m[2] & (sdi_transfer_counter == num_of_transfers);
|
||||
|
||||
end /* g_echo_sclk_miso_latch */
|
||||
else
|
||||
begin : g_sclk_miso_latch
|
||||
|
||||
assign end_of_sdi_latch = 1'b1;
|
||||
|
||||
for (i=0; i<NUM_OF_SDI; i=i+1) begin: g_sdi_shift_reg
|
||||
|
||||
reg [DATA_WIDTH-1:0] data_sdi_shift;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (cs_active) begin
|
||||
data_sdi_shift <= 0;
|
||||
end else begin
|
||||
if (trigger_rx_s == 1'b1) begin
|
||||
data_sdi_shift <= {data_sdi_shift, sdi[i]};
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign sdi_data[i*DATA_WIDTH+:DATA_WIDTH] = data_sdi_shift;
|
||||
|
||||
end
|
||||
|
||||
assign last_sdi_bit = (sdi_counter == word_length-1);
|
||||
always @(posedge clk) begin
|
||||
if (resetn == 1'b0) begin
|
||||
sdi_counter <= 8'b0;
|
||||
end else begin
|
||||
if (trigger_rx_s == 1'b1) begin
|
||||
sdi_counter <= last_sdi_bit ? 8'b0 : sdi_counter + 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (resetn == 1'b0)
|
||||
sdi_data_valid <= 1'b0;
|
||||
else if (sdi_enabled == 1'b1 && last_sdi_bit == 1'b1 && trigger_rx_s == 1'b1)
|
||||
sdi_data_valid <= 1'b1;
|
||||
else if (sdi_data_ready == 1'b1)
|
||||
sdi_data_valid <= 1'b0;
|
||||
end
|
||||
|
||||
end /* g_sclk_miso_latch */
|
||||
endgenerate
|
||||
|
||||
// end_of_word will signal the end of a transaction, pushing the command
|
||||
// stream execution to the next command. end_of_word in normal mode can be
|
||||
// generated using the global bit_counter
|
||||
assign last_bit = bit_counter == word_length - 1;
|
||||
assign end_of_word = last_bit == 1'b1 && ntx_rx == 1'b1 && clk_div_last == 1'b1;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (transfer_active == 1'b1) begin
|
||||
sclk_int <= cpol ^ cpha ^ ntx_rx;
|
||||
end else begin
|
||||
sclk_int <= cpol;
|
||||
end
|
||||
end
|
||||
|
||||
// Additional register stage to improve timing
|
||||
always @(posedge clk) begin
|
||||
sclk <= sclk_int;
|
||||
sdo <= sdo_int_s;
|
||||
sdo_t <= sdo_t_int;
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,36 @@
|
||||
###############################################################################
|
||||
## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIBSD
|
||||
###############################################################################
|
||||
|
||||
<: set ComponentName [getComponentNameString] :>
|
||||
<: setOutputDirectory "./" :>
|
||||
<: setFileName [ttcl_add $ComponentName "_constr"] :>
|
||||
<: setFileExtension ".xdc" :>
|
||||
<: setFileProcessingOrder late :>
|
||||
<: set echo_sclk [getBooleanValue "ECHO_SCLK"] :>
|
||||
|
||||
# Relax the timing between the SDI shift register and DMA. The shift register
|
||||
# runs at negative edge of echoSCLK and the DMA runs at spi_clk. Registers
|
||||
# will have valid data at worst case (fastest rate) in every 8 echoSCLK cycle.
|
||||
|
||||
set_multicycle_path -setup -from [get_pins -hier -filter {name=~*data_sdi_shift_reg[*]/C}] 8
|
||||
set_multicycle_path -hold -from [get_pins -hier -filter {name=~*data_sdi_shift_reg[*]/C}] 7
|
||||
|
||||
# word_length is updated before transfer, never changes during transfer, therefor
|
||||
# it's safe to define a false path between word_length and sdi_counter
|
||||
set_false_path -from [get_cells -hierarchical -filter {NAME=~*word_length_reg[*]}] -to [get_cells -hierarchical -filter {NAME=~*sdi_counter_reg[*]}]
|
||||
|
||||
<: if { $echo_sclk } { :>
|
||||
|
||||
## SDI counter runs on echo_SCLK but sdi_data_valid is generated with spi_clk which
|
||||
# is synchronous to SCLK. The last_sdi_bit should be transferred into spi_clk domain.
|
||||
set_property ASYNC_REG true [get_cells -hier {*last_sdi_bit_m_reg[0]}]
|
||||
set_property ASYNC_REG true [get_cells -hier {*last_sdi_bit_m_reg[1]}]
|
||||
set_false_path -to [get_cells -hier -filter {name =~ *last_sdi_bit_m_reg[0]* && IS_SEQUENTIAL}]
|
||||
|
||||
# SDI shift registers are reset asynchronously after a negative edge of CSN - define the reset line as a false path
|
||||
set_false_path -to [get_pins -hierarchical -filter {NAME=~*g_echo_sclk_miso_latch.*.data_sdi_shift_reg[*]/C*}]
|
||||
set_false_path -to [get_pins -hierarchical -filter {NAME=~*g_echo_sclk_miso_latch.*.sdi_data_latch_reg[*]/CE}]
|
||||
|
||||
<: } :>
|
||||
@@ -0,0 +1,150 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set SPI_Engine_execution [ipgui::add_page $IPINST -name "SPI Engine execution" -display_name {AXI SPI Engine execution}]
|
||||
#Adding Group
|
||||
set General_Configuration [ipgui::add_group $IPINST -name "General Configuration" -parent ${SPI_Engine_execution}]
|
||||
set DATA_WIDTH [ipgui::add_param $IPINST -name "DATA_WIDTH" -parent ${General_Configuration}]
|
||||
set_property tooltip {[DATA_WIDTH] Define the data interface width} ${DATA_WIDTH}
|
||||
set NUM_OF_CS [ipgui::add_param $IPINST -name "NUM_OF_CS" -parent ${General_Configuration}]
|
||||
set_property tooltip {[NUM_OF_CS] Define the number of chip select lines} ${NUM_OF_CS}
|
||||
set NUM_OF_SDI [ipgui::add_param $IPINST -name "NUM_OF_SDI" -parent ${General_Configuration}]
|
||||
set_property tooltip {[NUM_OF_SDI] Define the number of MISO lines} ${NUM_OF_SDI}
|
||||
|
||||
#Adding Group
|
||||
set SPI_Configuration [ipgui::add_group $IPINST -name "SPI Configuration" -parent ${SPI_Engine_execution}]
|
||||
set DEFAULT_SPI_CFG [ipgui::add_param $IPINST -name "DEFAULT_SPI_CFG" -parent ${SPI_Configuration} -widget comboBox]
|
||||
set_property tooltip {[DEFAULT_SPI_CFG] Define the default SPI configuration, bit 1 defines CPOL, bit 0 defines CPHA} ${DEFAULT_SPI_CFG}
|
||||
set DEFAULT_CLK_DIV [ipgui::add_param $IPINST -name "DEFAULT_CLK_DIV" -parent ${SPI_Configuration}]
|
||||
set_property tooltip {[DEFAULT_CLK_DIV] Define the default SCLK divider, fSCLK = fCoreClk / DEFAULT_CLK_DIV + 1} ${DEFAULT_CLK_DIV}
|
||||
|
||||
#Adding Group
|
||||
set MOSI/MISO_Configuration [ipgui::add_group $IPINST -name "MOSI/MISO Configuration" -parent ${SPI_Engine_execution}]
|
||||
set SDI_DELAY [ipgui::add_param $IPINST -name "SDI_DELAY" -parent ${MOSI/MISO_Configuration}]
|
||||
set_property tooltip {[SDI_DELAY] Delay the MISO latching to the next consecutive SCLK edge} ${SDI_DELAY}
|
||||
set SDO_DEFAULT [ipgui::add_param $IPINST -name "SDO_DEFAULT" -parent ${MOSI/MISO_Configuration} -widget comboBox]
|
||||
set_property tooltip {[SDO_DEFAULT] Define the default voltage level on MOSI} ${SDO_DEFAULT}
|
||||
|
||||
#Adding Group
|
||||
set Custom_clocking_options [ipgui::add_group $IPINST -name "Custom clocking options" -parent ${SPI_Engine_execution}]
|
||||
set ECHO_SCLK [ipgui::add_param $IPINST -name "ECHO_SCLK" -parent ${Custom_clocking_options}]
|
||||
set_property tooltip {[ECHO_SCLK] Activate echo SCLK option (hardware support required)} ${ECHO_SCLK}
|
||||
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } {
|
||||
# Procedure called to update DATA_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } {
|
||||
# Procedure called to validate DATA_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DEFAULT_CLK_DIV { PARAM_VALUE.DEFAULT_CLK_DIV } {
|
||||
# Procedure called to update DEFAULT_CLK_DIV when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DEFAULT_CLK_DIV { PARAM_VALUE.DEFAULT_CLK_DIV } {
|
||||
# Procedure called to validate DEFAULT_CLK_DIV
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DEFAULT_SPI_CFG { PARAM_VALUE.DEFAULT_SPI_CFG } {
|
||||
# Procedure called to update DEFAULT_SPI_CFG when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DEFAULT_SPI_CFG { PARAM_VALUE.DEFAULT_SPI_CFG } {
|
||||
# Procedure called to validate DEFAULT_SPI_CFG
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.ECHO_SCLK { PARAM_VALUE.ECHO_SCLK } {
|
||||
# Procedure called to update ECHO_SCLK when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.ECHO_SCLK { PARAM_VALUE.ECHO_SCLK } {
|
||||
# Procedure called to validate ECHO_SCLK
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.NUM_OF_CS { PARAM_VALUE.NUM_OF_CS } {
|
||||
# Procedure called to update NUM_OF_CS when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.NUM_OF_CS { PARAM_VALUE.NUM_OF_CS } {
|
||||
# Procedure called to validate NUM_OF_CS
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.NUM_OF_SDI { PARAM_VALUE.NUM_OF_SDI } {
|
||||
# Procedure called to update NUM_OF_SDI when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.NUM_OF_SDI { PARAM_VALUE.NUM_OF_SDI } {
|
||||
# Procedure called to validate NUM_OF_SDI
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.SDI_DELAY { PARAM_VALUE.SDI_DELAY } {
|
||||
# Procedure called to update SDI_DELAY when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.SDI_DELAY { PARAM_VALUE.SDI_DELAY } {
|
||||
# Procedure called to validate SDI_DELAY
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.SDO_DEFAULT { PARAM_VALUE.SDO_DEFAULT } {
|
||||
# Procedure called to update SDO_DEFAULT when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.SDO_DEFAULT { PARAM_VALUE.SDO_DEFAULT } {
|
||||
# Procedure called to validate SDO_DEFAULT
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.NUM_OF_CS { MODELPARAM_VALUE.NUM_OF_CS PARAM_VALUE.NUM_OF_CS } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.NUM_OF_CS}] ${MODELPARAM_VALUE.NUM_OF_CS}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DEFAULT_SPI_CFG { MODELPARAM_VALUE.DEFAULT_SPI_CFG PARAM_VALUE.DEFAULT_SPI_CFG } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DEFAULT_SPI_CFG}] ${MODELPARAM_VALUE.DEFAULT_SPI_CFG}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DEFAULT_CLK_DIV { MODELPARAM_VALUE.DEFAULT_CLK_DIV PARAM_VALUE.DEFAULT_CLK_DIV } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DEFAULT_CLK_DIV}] ${MODELPARAM_VALUE.DEFAULT_CLK_DIV}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DATA_WIDTH { MODELPARAM_VALUE.DATA_WIDTH PARAM_VALUE.DATA_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DATA_WIDTH}] ${MODELPARAM_VALUE.DATA_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.NUM_OF_SDI { MODELPARAM_VALUE.NUM_OF_SDI PARAM_VALUE.NUM_OF_SDI } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.NUM_OF_SDI}] ${MODELPARAM_VALUE.NUM_OF_SDI}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.SDO_DEFAULT { MODELPARAM_VALUE.SDO_DEFAULT PARAM_VALUE.SDO_DEFAULT } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.SDO_DEFAULT}] ${MODELPARAM_VALUE.SDO_DEFAULT}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.ECHO_SCLK { MODELPARAM_VALUE.ECHO_SCLK PARAM_VALUE.ECHO_SCLK } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.ECHO_SCLK}] ${MODELPARAM_VALUE.ECHO_SCLK}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.SDI_DELAY { MODELPARAM_VALUE.SDI_DELAY PARAM_VALUE.SDI_DELAY } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.SDI_DELAY}] ${MODELPARAM_VALUE.SDI_DELAY}
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,144 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module spi_engine_interconnect #(
|
||||
|
||||
parameter DATA_WIDTH = 8, // Valid data widths values are 8/16/24/32
|
||||
parameter NUM_OF_SDI = 1
|
||||
) (
|
||||
input clk,
|
||||
input resetn,
|
||||
|
||||
output m_cmd_valid,
|
||||
input m_cmd_ready,
|
||||
output [15:0] m_cmd_data,
|
||||
|
||||
output m_sdo_valid,
|
||||
input m_sdo_ready,
|
||||
output [(DATA_WIDTH-1):0] m_sdo_data,
|
||||
|
||||
input m_sdi_valid,
|
||||
output m_sdi_ready,
|
||||
input [(NUM_OF_SDI * DATA_WIDTH-1):0] m_sdi_data,
|
||||
|
||||
input m_sync_valid,
|
||||
output m_sync_ready,
|
||||
input [7:0] m_sync,
|
||||
|
||||
input s0_cmd_valid,
|
||||
output s0_cmd_ready,
|
||||
input [15:0] s0_cmd_data,
|
||||
|
||||
input s0_sdo_valid,
|
||||
output s0_sdo_ready,
|
||||
input [(DATA_WIDTH-1):0] s0_sdo_data,
|
||||
|
||||
output s0_sdi_valid,
|
||||
input s0_sdi_ready,
|
||||
output [(NUM_OF_SDI * DATA_WIDTH-1):0] s0_sdi_data,
|
||||
|
||||
output s0_sync_valid,
|
||||
input s0_sync_ready,
|
||||
output [7:0] s0_sync,
|
||||
|
||||
input s1_cmd_valid,
|
||||
output s1_cmd_ready,
|
||||
input [15:0] s1_cmd_data,
|
||||
|
||||
input s1_sdo_valid,
|
||||
output s1_sdo_ready,
|
||||
input [(DATA_WIDTH-1):0] s1_sdo_data,
|
||||
|
||||
output s1_sdi_valid,
|
||||
input s1_sdi_ready,
|
||||
output [(NUM_OF_SDI * DATA_WIDTH-1):0] s1_sdi_data,
|
||||
|
||||
output s1_sync_valid,
|
||||
input s1_sync_ready,
|
||||
output [7:0] s1_sync
|
||||
);
|
||||
|
||||
reg s_active = 1'b0;
|
||||
|
||||
reg idle = 1'b1;
|
||||
|
||||
`define spi_engine_interconnect_mux(s0, s1) (idle == 1'b1 ? 1'b0 : (s_active == 1'b0 ? s0 : s1))
|
||||
|
||||
assign m_cmd_data = s_active == 1'b0 ? s0_cmd_data : s1_cmd_data;
|
||||
assign m_cmd_valid = `spi_engine_interconnect_mux(s0_cmd_valid, s1_cmd_valid);
|
||||
assign s0_cmd_ready = `spi_engine_interconnect_mux(m_cmd_ready, 1'b0);
|
||||
assign s1_cmd_ready = `spi_engine_interconnect_mux(1'b0, m_cmd_ready);
|
||||
|
||||
assign m_sdo_data = s_active == 1'b0 ? s0_sdo_data : s1_sdo_data;
|
||||
assign m_sdo_valid = `spi_engine_interconnect_mux(s0_sdo_valid, s1_sdo_valid);
|
||||
assign s0_sdo_ready = `spi_engine_interconnect_mux(m_sdo_ready, 1'b0);
|
||||
assign s1_sdo_ready = `spi_engine_interconnect_mux(1'b0, m_sdo_ready);
|
||||
|
||||
assign s0_sdi_data = m_sdi_data;
|
||||
assign s1_sdi_data = m_sdi_data;
|
||||
assign m_sdi_ready = `spi_engine_interconnect_mux(s0_sdi_ready, s1_sdi_ready);
|
||||
assign s0_sdi_valid = `spi_engine_interconnect_mux(m_sdi_valid, 1'b0);
|
||||
assign s1_sdi_valid = `spi_engine_interconnect_mux(1'b0, m_sdi_valid);
|
||||
|
||||
assign s0_sync = m_sync;
|
||||
assign s1_sync = m_sync;
|
||||
assign m_sync_ready = `spi_engine_interconnect_mux(s0_sync_ready, s1_sync_ready);
|
||||
assign s0_sync_valid = `spi_engine_interconnect_mux(m_sync_valid, 1'b0);
|
||||
assign s1_sync_valid = `spi_engine_interconnect_mux(1'b0, m_sync_valid);
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (idle == 1'b1) begin
|
||||
if (s0_cmd_valid)
|
||||
s_active <= 1'b0;
|
||||
else if (s1_cmd_valid)
|
||||
s_active <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (resetn == 1'b0) begin
|
||||
idle <= 1'b1;
|
||||
end else begin
|
||||
if (m_sync_valid == 1'b1 && m_sync_ready == 1'b1) begin
|
||||
idle <= 1'b1;
|
||||
end else if (s0_cmd_valid == 1'b1 || s1_cmd_valid == 1'b1) begin
|
||||
idle <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,45 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set SPI_Engine_interconnect [ipgui::add_page $IPINST -name "SPI Engine interconnect"]
|
||||
#Adding Group
|
||||
set General_Configuration [ipgui::add_group $IPINST -name "General Configuration" -parent ${SPI_Engine_interconnect}]
|
||||
set DATA_WIDTH [ipgui::add_param $IPINST -name "DATA_WIDTH" -parent ${General_Configuration}]
|
||||
set_property tooltip {[DATA_WIDTH] Define the data interface width} ${DATA_WIDTH}
|
||||
set NUM_OF_SDI [ipgui::add_param $IPINST -name "NUM_OF_SDI" -parent ${General_Configuration}]
|
||||
set_property tooltip {[NUM_OF_SDI] Define the number of MISO lines} ${NUM_OF_SDI}
|
||||
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } {
|
||||
# Procedure called to update DATA_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } {
|
||||
# Procedure called to validate DATA_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.NUM_OF_SDI { PARAM_VALUE.NUM_OF_SDI } {
|
||||
# Procedure called to update NUM_OF_SDI when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.NUM_OF_SDI { PARAM_VALUE.NUM_OF_SDI } {
|
||||
# Procedure called to validate NUM_OF_SDI
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.DATA_WIDTH { MODELPARAM_VALUE.DATA_WIDTH PARAM_VALUE.DATA_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DATA_WIDTH}] ${MODELPARAM_VALUE.DATA_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.NUM_OF_SDI { MODELPARAM_VALUE.NUM_OF_SDI PARAM_VALUE.NUM_OF_SDI } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.NUM_OF_SDI}] ${MODELPARAM_VALUE.NUM_OF_SDI}
|
||||
}
|
||||
|
||||
@@ -0,0 +1,954 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>analog.com</spirit:vendor>
|
||||
<spirit:library>user</spirit:library>
|
||||
<spirit:name>spi_engine_offload</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>spi_engine_ctrl</spirit:name>
|
||||
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="spi_engine_ctrl" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="spi_engine_ctrl_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>cmd_ready</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>cmd_ready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>cmd_valid</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>cmd_valid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>cmd_data</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>cmd</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>sdo_ready</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sdo_data_ready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>sdo_valid</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sdo_data_valid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>sdo_data</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sdo_data</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>sdi_ready</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sdi_data_ready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>sdi_valid</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sdi_data_valid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>sdi_data</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sdi_data</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>sync_ready</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sync_ready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>sync_valid</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sync_valid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>sync_data</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sync_data</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>spi_engine_offload_ctrl</spirit:name>
|
||||
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="spi_engine_offload_ctrl" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="spi_engine_offload_ctrl_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>cmd_wr_en</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>ctrl_cmd_wr_en</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>cmd_wr_data</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>ctrl_cmd_wr_data</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>sdo_wr_en</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>ctrl_sdo_wr_en</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>sdo_wr_data</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>ctrl_sdo_wr_data</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>enable</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>ctrl_enable</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>enabled</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>ctrl_enabled</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>mem_reset</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>ctrl_mem_reset</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>sync_ready</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>status_sync_ready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>sync_valid</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>status_sync_valid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>sync_data</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>status_sync_data</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>offload_sdi</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>offload_sdi_valid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>offload_sdi_ready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>offload_sdi_data</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>spi_engine_ctrl_offload_sdi_signal_clock</spirit:name>
|
||||
<spirit:displayName>spi_engine_ctrl_offload_sdi_signal_clock</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>spi_clk</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.SPI_ENGINE_CTRL_OFFLOAD_SDI_SIGNAL_CLOCK.ASSOCIATED_BUSIF">spi_engine_ctrl:offload_sdi</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.SPI_ENGINE_CTRL_OFFLOAD_SDI_SIGNAL_CLOCK.ASSOCIATED_RESET">spi_resetn</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>spi_engine_ctrl_offload_sdi_signal_reset</spirit:name>
|
||||
<spirit:displayName>spi_engine_ctrl_offload_sdi_signal_reset</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>spi_resetn</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.SPI_ENGINE_CTRL_OFFLOAD_SDI_SIGNAL_RESET.POLARITY">ACTIVE_LOW</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>spi_engine_offload_ctrl_signal_clock</spirit:name>
|
||||
<spirit:displayName>spi_engine_offload_ctrl_signal_clock</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
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|
||||
<spirit:name>ctrl_clk</spirit:name>
|
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|
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|
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|
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|
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|
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|
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<spirit:name>viewChecksum</spirit:name>
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|
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|
||||
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|
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|
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|
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|
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|
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<spirit:typeName>std_logic</spirit:typeName>
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|
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|
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|
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
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||||
<spirit:typeName>std_logic</spirit:typeName>
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.DATA_WIDTH')) - 1)">7</spirit:left>
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
<spirit:typeName>std_logic</spirit:typeName>
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
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|
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<spirit:typeName>std_logic</spirit:typeName>
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||||
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|
||||
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|
||||
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|
||||
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|
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<spirit:direction>out</spirit:direction>
|
||||
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|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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||||
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|
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|
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|
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|
||||
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|
||||
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|
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|
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|
||||
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|
||||
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|
||||
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|
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|
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||||
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||||
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|
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||||
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||||
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|
||||
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|
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|
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||||
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||||
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|
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||||
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|
||||
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|
||||
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|
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||||
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|
||||
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||||
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
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|
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||||
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||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
<spirit:left spirit:format="long">15</spirit:left>
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||||
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|
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|
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||||
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||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
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|
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||||
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||||
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|
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
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||||
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||||
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|
||||
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||||
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||||
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|
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|
||||
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|
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|
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<spirit:wireTypeDef>
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||||
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|
||||
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|
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|
||||
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|
||||
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||||
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|
||||
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||||
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||||
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|
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|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
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|
||||
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|
||||
<spirit:port>
|
||||
<spirit:name>sync_valid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
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|
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|
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|
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|
||||
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|
||||
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|
||||
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|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>sync_ready</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
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|
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|
||||
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|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>sync_data</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">7</spirit:left>
|
||||
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|
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<spirit:wireTypeDefs>
|
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<spirit:wireTypeDef>
|
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|
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|
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|
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|
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|
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<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>offload_sdi_valid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
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|
||||
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|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>offload_sdi_ready</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
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<spirit:typeName>std_logic</spirit:typeName>
|
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|
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|
||||
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|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>offload_sdi_data</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.NUM_OF_SDI')) * spirit:decode(id('MODELPARAM_VALUE.DATA_WIDTH'))) - 1)">7</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
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</spirit:vector>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
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</spirit:wireTypeDef>
|
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</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
</spirit:ports>
|
||||
<spirit:modelParameters>
|
||||
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
|
||||
<spirit:name>ASYNC_SPI_CLK</spirit:name>
|
||||
<spirit:displayName>Async Spi Clk</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.ASYNC_SPI_CLK">false</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>ASYNC_TRIG</spirit:name>
|
||||
<spirit:displayName>Async Trig</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.ASYNC_TRIG">false</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>CMD_MEM_ADDRESS_WIDTH</spirit:name>
|
||||
<spirit:displayName>Cmd Mem Address Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CMD_MEM_ADDRESS_WIDTH">4</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>SDO_MEM_ADDRESS_WIDTH</spirit:name>
|
||||
<spirit:displayName>Sdo Mem Address Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SDO_MEM_ADDRESS_WIDTH">4</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
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<spirit:name>DATA_WIDTH</spirit:name>
|
||||
<spirit:displayName>Data Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DATA_WIDTH">8</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>NUM_OF_SDI</spirit:name>
|
||||
<spirit:displayName>Num Of Sdi</spirit:displayName>
|
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<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.NUM_OF_SDI">1</spirit:value>
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</spirit:modelParameter>
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</spirit:modelParameters>
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<spirit:name>spi_engine_offload_constr.ttcl</spirit:name>
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<spirit:userFileType>ttcl</spirit:userFileType>
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<spirit:name>spi_engine_offload.v</spirit:name>
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<spirit:fileType>verilogSource</spirit:fileType>
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<spirit:file>
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<spirit:name>xgui/spi_engine_offload_v1_0.tcl</spirit:name>
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<spirit:fileType>tclSource</spirit:fileType>
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<spirit:userFileType>CHECKSUM_1ce3c7e4</spirit:userFileType>
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<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
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<spirit:fileSet>
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<spirit:name>xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset</spirit:name>
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<spirit:vendorExtensions>
|
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<xilinx:subCoreRef>
|
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<xilinx:componentRef xilinx:vendor="analog.com" xilinx:library="user" xilinx:name="util_cdc" xilinx:version="1.0"/>
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</spirit:vendorExtensions>
|
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</spirit:fileSet>
|
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</spirit:fileSets>
|
||||
<spirit:description>spi_engine_offload_v1_0</spirit:description>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASYNC_SPI_CLK</spirit:name>
|
||||
<spirit:displayName>Asynchronous core clock</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.ASYNC_SPI_CLK">false</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASYNC_TRIG</spirit:name>
|
||||
<spirit:displayName>Asynchronous trigger</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.ASYNC_TRIG">false</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CMD_MEM_ADDRESS_WIDTH</spirit:name>
|
||||
<spirit:displayName>Command FIFO address width</spirit:displayName>
|
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<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CMD_MEM_ADDRESS_WIDTH" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>SDO_MEM_ADDRESS_WIDTH</spirit:name>
|
||||
<spirit:displayName>MOSI FIFO address width</spirit:displayName>
|
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<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.SDO_MEM_ADDRESS_WIDTH" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>DATA_WIDTH</spirit:name>
|
||||
<spirit:displayName>Shift register's data width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DATA_WIDTH" spirit:minimum="8" spirit:maximum="256" spirit:rangeType="long">8</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>NUM_OF_SDI</spirit:name>
|
||||
<spirit:displayName>Number of MISO lines</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.NUM_OF_SDI" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>Component_Name</spirit:name>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">spi_engine_offload_v1_0</spirit:value>
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</spirit:parameter>
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<spirit:vendorExtensions>
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||||
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</xilinx:supportedFamilies>
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<xilinx:taxonomies>
|
||||
<xilinx:taxonomy>/Analog_Devices</xilinx:taxonomy>
|
||||
</xilinx:taxonomies>
|
||||
<xilinx:displayName>spi_engine_offload_v1_0</xilinx:displayName>
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<xilinx:autoFamilySupportLevel>level_2</xilinx:autoFamilySupportLevel>
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<xilinx:definitionSource>package_project</xilinx:definitionSource>
|
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<xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
|
||||
<xilinx:vendorURL>https://wiki.analog.com/resources/fpga/peripherals/spi_engine/offload</xilinx:vendorURL>
|
||||
<xilinx:coreRevision>1</xilinx:coreRevision>
|
||||
<xilinx:coreCreationDateTime>2025-04-30T13:54:08Z</xilinx:coreCreationDateTime>
|
||||
</xilinx:coreExtensions>
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<xilinx:packagingInfo>
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<xilinx:xilinxVersion>2024.1.2</xilinx:xilinxVersion>
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<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="582124d3"/>
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||||
<xilinx:checksum xilinx:scope="ports" xilinx:value="2756ddd5"/>
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<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="ae1a9eae"/>
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<xilinx:checksum xilinx:scope="parameters" xilinx:value="e2e1ec4a"/>
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</xilinx:packagingInfo>
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||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
@@ -0,0 +1,317 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2015-2024 Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module spi_engine_offload #(
|
||||
|
||||
parameter ASYNC_SPI_CLK = 0,
|
||||
parameter ASYNC_TRIG = 0,
|
||||
parameter CMD_MEM_ADDRESS_WIDTH = 4,
|
||||
parameter SDO_MEM_ADDRESS_WIDTH = 4,
|
||||
parameter DATA_WIDTH = 8, // Valid data widths values are 8/16/24/32
|
||||
parameter NUM_OF_SDI = 1
|
||||
) (
|
||||
input ctrl_clk,
|
||||
|
||||
input ctrl_cmd_wr_en,
|
||||
input [15:0] ctrl_cmd_wr_data,
|
||||
|
||||
input ctrl_sdo_wr_en,
|
||||
input [(DATA_WIDTH-1):0] ctrl_sdo_wr_data,
|
||||
|
||||
input ctrl_enable,
|
||||
output ctrl_enabled,
|
||||
input ctrl_mem_reset,
|
||||
|
||||
output status_sync_valid,
|
||||
input status_sync_ready,
|
||||
output [7:0] status_sync_data,
|
||||
|
||||
input spi_clk,
|
||||
input spi_resetn,
|
||||
|
||||
input trigger,
|
||||
|
||||
output cmd_valid,
|
||||
input cmd_ready,
|
||||
output [15:0] cmd,
|
||||
|
||||
output sdo_data_valid,
|
||||
input sdo_data_ready,
|
||||
output [(DATA_WIDTH-1):0] sdo_data,
|
||||
|
||||
input sdi_data_valid,
|
||||
output sdi_data_ready,
|
||||
input [(NUM_OF_SDI * DATA_WIDTH-1):0] sdi_data,
|
||||
|
||||
input sync_valid,
|
||||
output sync_ready,
|
||||
input [7:0] sync_data,
|
||||
|
||||
output offload_sdi_valid,
|
||||
input offload_sdi_ready,
|
||||
output [(NUM_OF_SDI * DATA_WIDTH-1):0] offload_sdi_data
|
||||
);
|
||||
|
||||
reg spi_active = 1'b0;
|
||||
|
||||
reg [CMD_MEM_ADDRESS_WIDTH-1:0] ctrl_cmd_wr_addr = 'h00;
|
||||
reg [CMD_MEM_ADDRESS_WIDTH-1:0] spi_cmd_rd_addr = 'h00;
|
||||
reg [SDO_MEM_ADDRESS_WIDTH-1:0] ctrl_sdo_wr_addr = 'h00;
|
||||
reg [SDO_MEM_ADDRESS_WIDTH-1:0] spi_sdo_rd_addr = 'h00;
|
||||
|
||||
reg [15:0] cmd_mem[0:2**CMD_MEM_ADDRESS_WIDTH-1];
|
||||
reg [(DATA_WIDTH-1):0] sdo_mem[0:2**SDO_MEM_ADDRESS_WIDTH-1];
|
||||
|
||||
reg trigger_last_reg;
|
||||
|
||||
wire [15:0] cmd_int_s;
|
||||
wire [CMD_MEM_ADDRESS_WIDTH-1:0] spi_cmd_rd_addr_next;
|
||||
wire spi_enable;
|
||||
wire trigger_posedge;
|
||||
|
||||
assign cmd_valid = spi_active;
|
||||
assign sdo_data_valid = spi_active;
|
||||
|
||||
assign offload_sdi_valid = sdi_data_valid;
|
||||
|
||||
// we don't want to block the SDI interface after disabling the module
|
||||
// so just assert the SDI_READY if the sink module (DMA) is disabled
|
||||
assign sdi_data_ready = (spi_enable) ? offload_sdi_ready : 1'b1;
|
||||
|
||||
assign offload_sdi_data = sdi_data;
|
||||
|
||||
assign cmd_int_s = cmd_mem[spi_cmd_rd_addr];
|
||||
assign sdo_data = sdo_mem[spi_sdo_rd_addr];
|
||||
|
||||
/* SYNC ID counter. The offload module increments the sync_id on each
|
||||
* transaction. The initial value of the sync_id is the value of the last
|
||||
* sync_id command loaded into the command buffer.
|
||||
*/
|
||||
|
||||
reg [ 7:0] ctrl_sync_id_init = 8'b0;
|
||||
reg ctrl_sync_id_load = 1'b0;
|
||||
reg [ 7:0] spi_sync_id_counter = 8'b0;
|
||||
|
||||
wire [ 7:0] spi_sync_id_init_s;
|
||||
|
||||
always @(posedge ctrl_clk) begin
|
||||
if (ctrl_mem_reset) begin
|
||||
ctrl_sync_id_init <= 8'b0;
|
||||
ctrl_sync_id_load <= 1'b0;
|
||||
end else begin
|
||||
if (ctrl_cmd_wr_en && (ctrl_cmd_wr_data[15:8] == 8'h30)) begin
|
||||
ctrl_sync_id_init <= ctrl_cmd_wr_data;
|
||||
ctrl_sync_id_load <= 1'b1;
|
||||
end else begin
|
||||
ctrl_sync_id_load <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
wire spi_sync_id_load_s;
|
||||
|
||||
sync_event #(
|
||||
.NUM_OF_EVENTS(1),
|
||||
.ASYNC_CLK(1)
|
||||
) i_sync_sync_id_load (
|
||||
.in_clk (ctrl_clk),
|
||||
.in_event(ctrl_sync_id_load),
|
||||
.out_clk(spi_clk),
|
||||
.out_event(spi_sync_id_load_s));
|
||||
|
||||
sync_bits #(
|
||||
.NUM_OF_BITS(8),
|
||||
.ASYNC_CLK(1)
|
||||
) i_sync_sync_id (
|
||||
.in_bits(ctrl_sync_id_init),
|
||||
.out_clk(spi_clk),
|
||||
.out_resetn(1'b1),
|
||||
.out_bits(spi_sync_id_init_s));
|
||||
|
||||
always @(posedge spi_clk) begin
|
||||
if (!spi_resetn) begin
|
||||
spi_sync_id_counter <= 8'b0;
|
||||
end else begin
|
||||
if (spi_sync_id_load_s) begin
|
||||
spi_sync_id_counter <= spi_sync_id_init_s;
|
||||
end else if(cmd_valid && cmd_ready && (cmd[15:8] == 8'h30)) begin
|
||||
spi_sync_id_counter <= spi_sync_id_counter + 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign cmd = (cmd_int_s[15:8] == 8'h30) ? {cmd_int_s[15:8], spi_sync_id_counter} : cmd_int_s;
|
||||
|
||||
/*
|
||||
* Forwarded SYNC interface, this can be used to monitor the state of the
|
||||
* offload command sequence through SPI Engine regmap
|
||||
*/
|
||||
|
||||
assign status_sync_data = sync_data;
|
||||
assign status_sync_valid = sync_valid;
|
||||
assign sync_ready = status_sync_ready;
|
||||
|
||||
generate if (ASYNC_SPI_CLK) begin
|
||||
|
||||
/*
|
||||
* The synchronization circuit takes care that there are no glitches on the
|
||||
* ctrl_enabled signal. ctrl_do_enable is asserted whenever ctrl_enable is
|
||||
* asserted, but only deasserted once the signal has been synchronized back from
|
||||
* the SPI domain. This makes sure that we can't end up in a state where the
|
||||
* enable signal in the SPI domain is asserted, but neither enable nor enabled
|
||||
* is asserted in the control domain.
|
||||
*/
|
||||
|
||||
reg ctrl_do_enable = 1'b0;
|
||||
wire ctrl_is_enabled;
|
||||
reg spi_enabled = 1'b0;
|
||||
|
||||
always @(posedge ctrl_clk) begin
|
||||
if (ctrl_enable) begin
|
||||
ctrl_do_enable <= 1'b1;
|
||||
end else if (ctrl_is_enabled) begin
|
||||
ctrl_do_enable <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
assign ctrl_enabled = ctrl_is_enabled | ctrl_do_enable;
|
||||
|
||||
always @(posedge spi_clk) begin
|
||||
spi_enabled <= spi_enable | spi_active;
|
||||
end
|
||||
|
||||
sync_bits #(
|
||||
.NUM_OF_BITS(1),
|
||||
.ASYNC_CLK(1)
|
||||
) i_sync_enable (
|
||||
.in_bits(ctrl_do_enable),
|
||||
.out_clk(spi_clk),
|
||||
.out_resetn(1'b1),
|
||||
.out_bits(spi_enable));
|
||||
|
||||
sync_bits #(
|
||||
.NUM_OF_BITS(1),
|
||||
.ASYNC_CLK(1)
|
||||
) i_sync_enabled (
|
||||
.in_bits(spi_enabled),
|
||||
.out_clk(ctrl_clk),
|
||||
.out_resetn(1'b1),
|
||||
.out_bits(ctrl_is_enabled));
|
||||
|
||||
end else begin
|
||||
assign spi_enable = ctrl_enable;
|
||||
assign ctrl_enabled = spi_enable | spi_active;
|
||||
end endgenerate
|
||||
|
||||
assign spi_cmd_rd_addr_next = spi_cmd_rd_addr + 1;
|
||||
|
||||
wire trigger_s;
|
||||
sync_bits #(
|
||||
.NUM_OF_BITS(1),
|
||||
.ASYNC_CLK(ASYNC_TRIG)
|
||||
) i_sync_trigger (
|
||||
.in_bits(trigger),
|
||||
.out_clk(spi_clk),
|
||||
.out_resetn(1'b1),
|
||||
.out_bits(trigger_s));
|
||||
|
||||
always @(posedge spi_clk) begin
|
||||
if (!spi_resetn) begin
|
||||
trigger_last_reg <= 1'b0;
|
||||
end else begin
|
||||
trigger_last_reg <= trigger_s;
|
||||
end
|
||||
end
|
||||
|
||||
assign trigger_posedge = trigger_s && !trigger_last_reg;
|
||||
|
||||
always @(posedge spi_clk) begin
|
||||
if (!spi_resetn) begin
|
||||
spi_active <= 1'b0;
|
||||
end else begin
|
||||
if (!spi_active) begin
|
||||
// start offload when we have a valid trigger, offload is enabled and
|
||||
// the DMA is enabled
|
||||
if (trigger_posedge && spi_enable && offload_sdi_ready)
|
||||
spi_active <= 1'b1;
|
||||
end else if (cmd_ready && (spi_cmd_rd_addr_next == ctrl_cmd_wr_addr)) begin
|
||||
spi_active <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge spi_clk) begin
|
||||
if (!cmd_valid) begin
|
||||
spi_cmd_rd_addr <= 'h00;
|
||||
end else if (cmd_ready) begin
|
||||
spi_cmd_rd_addr <= spi_cmd_rd_addr_next;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge spi_clk) begin
|
||||
if (!spi_active) begin
|
||||
spi_sdo_rd_addr <= 'h00;
|
||||
end else if (sdo_data_ready) begin
|
||||
spi_sdo_rd_addr <= spi_sdo_rd_addr + 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge ctrl_clk) begin
|
||||
if (ctrl_mem_reset)
|
||||
ctrl_cmd_wr_addr <= 'h00;
|
||||
else if (ctrl_cmd_wr_en)
|
||||
ctrl_cmd_wr_addr <= ctrl_cmd_wr_addr + 1'b1;
|
||||
end
|
||||
|
||||
always @(posedge ctrl_clk) begin
|
||||
if (ctrl_cmd_wr_en)
|
||||
cmd_mem[ctrl_cmd_wr_addr] <= ctrl_cmd_wr_data;
|
||||
end
|
||||
|
||||
always @(posedge ctrl_clk) begin
|
||||
if (ctrl_mem_reset)
|
||||
ctrl_sdo_wr_addr <= 'h00;
|
||||
else if (ctrl_sdo_wr_en)
|
||||
ctrl_sdo_wr_addr <= ctrl_sdo_wr_addr + 1'b1;
|
||||
end
|
||||
|
||||
always @(posedge ctrl_clk) begin
|
||||
if (ctrl_sdo_wr_en)
|
||||
sdo_mem[ctrl_sdo_wr_addr] <= ctrl_sdo_wr_data;
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,17 @@
|
||||
###############################################################################
|
||||
## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIBSD
|
||||
###############################################################################
|
||||
|
||||
<: set ComponentName [getComponentNameString] :>
|
||||
<: setOutputDirectory "./" :>
|
||||
<: setFileName [ttcl_add $ComponentName "_constr"] :>
|
||||
<: setFileExtension ".xdc" :>
|
||||
<: setFileProcessingOrder late :>
|
||||
|
||||
<: set async_trigger [getBooleanValue "ASYNC_TRIG"] :>
|
||||
<: if { $async_trigger } { :>
|
||||
set_false_path -quiet \
|
||||
-to [get_cells -quiet -hierarchical -filter {NAME =~ *i_sync_trigger/cdc_sync_stage1_reg* && IS_SEQUENTIAL}]
|
||||
|
||||
<: } :>
|
||||
@@ -0,0 +1,112 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set SPI_Engine_RX_offload [ipgui::add_page $IPINST -name "SPI Engine RX offload"]
|
||||
#Adding Group
|
||||
set General_Configuration [ipgui::add_group $IPINST -name "General Configuration" -parent ${SPI_Engine_RX_offload}]
|
||||
set DATA_WIDTH [ipgui::add_param $IPINST -name "DATA_WIDTH" -parent ${General_Configuration}]
|
||||
set_property tooltip {[DATA_WIDTH] Define the data interface width} ${DATA_WIDTH}
|
||||
set NUM_OF_SDI [ipgui::add_param $IPINST -name "NUM_OF_SDI" -parent ${General_Configuration}]
|
||||
set_property tooltip {[NUM_OF_SDI] Define the number of MISO lines} ${NUM_OF_SDI}
|
||||
set ASYNC_SPI_CLK [ipgui::add_param $IPINST -name "ASYNC_SPI_CLK" -parent ${General_Configuration}]
|
||||
set_property tooltip {[ASYNC_SPI_CLK] Define the relationship between the core clock and the memory mapped interface clock} ${ASYNC_SPI_CLK}
|
||||
set ASYNC_TRIG [ipgui::add_param $IPINST -name "ASYNC_TRIG" -parent ${General_Configuration}]
|
||||
set_property tooltip {[ASYNC_TRIG] Set if the external trigger is asynchronous to the core clk} ${ASYNC_TRIG}
|
||||
|
||||
#Adding Group
|
||||
set Command_stream_FIFO_configuration [ipgui::add_group $IPINST -name "Command stream FIFO configuration" -parent ${SPI_Engine_RX_offload}]
|
||||
set CMD_MEM_ADDRESS_WIDTH [ipgui::add_param $IPINST -name "CMD_MEM_ADDRESS_WIDTH" -parent ${Command_stream_FIFO_configuration}]
|
||||
set_property tooltip {[CMD_MEM_ADDRESS_WIDTH] Define the depth of the FIFO} ${CMD_MEM_ADDRESS_WIDTH}
|
||||
set SDO_MEM_ADDRESS_WIDTH [ipgui::add_param $IPINST -name "SDO_MEM_ADDRESS_WIDTH" -parent ${Command_stream_FIFO_configuration}]
|
||||
set_property tooltip {[SDO_MEM_ADDRESS_WIDTH] Define the depth of the FIFO} ${SDO_MEM_ADDRESS_WIDTH}
|
||||
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.ASYNC_SPI_CLK { PARAM_VALUE.ASYNC_SPI_CLK } {
|
||||
# Procedure called to update ASYNC_SPI_CLK when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.ASYNC_SPI_CLK { PARAM_VALUE.ASYNC_SPI_CLK } {
|
||||
# Procedure called to validate ASYNC_SPI_CLK
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.ASYNC_TRIG { PARAM_VALUE.ASYNC_TRIG } {
|
||||
# Procedure called to update ASYNC_TRIG when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.ASYNC_TRIG { PARAM_VALUE.ASYNC_TRIG } {
|
||||
# Procedure called to validate ASYNC_TRIG
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.CMD_MEM_ADDRESS_WIDTH { PARAM_VALUE.CMD_MEM_ADDRESS_WIDTH } {
|
||||
# Procedure called to update CMD_MEM_ADDRESS_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.CMD_MEM_ADDRESS_WIDTH { PARAM_VALUE.CMD_MEM_ADDRESS_WIDTH } {
|
||||
# Procedure called to validate CMD_MEM_ADDRESS_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } {
|
||||
# Procedure called to update DATA_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } {
|
||||
# Procedure called to validate DATA_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.NUM_OF_SDI { PARAM_VALUE.NUM_OF_SDI } {
|
||||
# Procedure called to update NUM_OF_SDI when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.NUM_OF_SDI { PARAM_VALUE.NUM_OF_SDI } {
|
||||
# Procedure called to validate NUM_OF_SDI
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.SDO_MEM_ADDRESS_WIDTH { PARAM_VALUE.SDO_MEM_ADDRESS_WIDTH } {
|
||||
# Procedure called to update SDO_MEM_ADDRESS_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.SDO_MEM_ADDRESS_WIDTH { PARAM_VALUE.SDO_MEM_ADDRESS_WIDTH } {
|
||||
# Procedure called to validate SDO_MEM_ADDRESS_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.ASYNC_SPI_CLK { MODELPARAM_VALUE.ASYNC_SPI_CLK PARAM_VALUE.ASYNC_SPI_CLK } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.ASYNC_SPI_CLK}] ${MODELPARAM_VALUE.ASYNC_SPI_CLK}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.ASYNC_TRIG { MODELPARAM_VALUE.ASYNC_TRIG PARAM_VALUE.ASYNC_TRIG } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.ASYNC_TRIG}] ${MODELPARAM_VALUE.ASYNC_TRIG}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.CMD_MEM_ADDRESS_WIDTH { MODELPARAM_VALUE.CMD_MEM_ADDRESS_WIDTH PARAM_VALUE.CMD_MEM_ADDRESS_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.CMD_MEM_ADDRESS_WIDTH}] ${MODELPARAM_VALUE.CMD_MEM_ADDRESS_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.SDO_MEM_ADDRESS_WIDTH { MODELPARAM_VALUE.SDO_MEM_ADDRESS_WIDTH PARAM_VALUE.SDO_MEM_ADDRESS_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.SDO_MEM_ADDRESS_WIDTH}] ${MODELPARAM_VALUE.SDO_MEM_ADDRESS_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DATA_WIDTH { MODELPARAM_VALUE.DATA_WIDTH PARAM_VALUE.DATA_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DATA_WIDTH}] ${MODELPARAM_VALUE.DATA_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.NUM_OF_SDI { MODELPARAM_VALUE.NUM_OF_SDI PARAM_VALUE.NUM_OF_SDI } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.NUM_OF_SDI}] ${MODELPARAM_VALUE.NUM_OF_SDI}
|
||||
}
|
||||
|
||||
@@ -0,0 +1,840 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>analog.com</spirit:vendor>
|
||||
<spirit:library>user</spirit:library>
|
||||
<spirit:name>util_axis_fifo</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>s_axis</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axis_valid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axis_ready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axis_data</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TLAST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axis_tlast</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TKEEP</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axis_tkeep</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>m_axis</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m_axis_valid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m_axis_ready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m_axis_data</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TLAST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m_axis_tlast</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TKEEP</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m_axis_tkeep</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>m_axis_signal_clock</spirit:name>
|
||||
<spirit:displayName>m_axis_signal_clock</spirit:displayName>
|
||||
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<spirit:name>RST</spirit:name>
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<spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
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<spirit:name>viewChecksum</spirit:name>
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<spirit:value>2735fcaa</spirit:value>
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<spirit:name>viewChecksum</spirit:name>
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<spirit:value>2735fcaa</spirit:value>
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<spirit:name>xilinx_xpgui</spirit:name>
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<spirit:displayName>UI Layout</spirit:displayName>
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<spirit:name>viewChecksum</spirit:name>
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<spirit:value>fa323617</spirit:value>
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<spirit:displayName>Utility XIT/TTCL</spirit:displayName>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:name>m_axis_ready</spirit:name>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:direction>out</spirit:direction>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:name>m_axis_data</spirit:name>
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<spirit:direction>out</spirit:direction>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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<spirit:port>
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<spirit:name>m_axis_tkeep</spirit:name>
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<spirit:wire>
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<spirit:direction>out</spirit:direction>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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<xilinx:portInfo>
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<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axis_tkeep" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.TKEEP_EN')) = 1)">true</xilinx:isEnabled>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:direction>out</spirit:direction>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic</spirit:typeName>
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||||
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|
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic</spirit:typeName>
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||||
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<spirit:typeName>std_logic</spirit:typeName>
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||||
</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
@@ -0,0 +1,2 @@
|
||||
# This file is automatically written. Do not modify.
|
||||
proc gen_USERPARAMETER_REMOVE_NULL_BEAT_EN_ENABLEMENT {TKEEP_EN } {expr $TKEEP_EN == "true"}
|
||||
@@ -0,0 +1,363 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
`timescale 1ns/1ps
|
||||
|
||||
module util_axis_fifo #(
|
||||
parameter DATA_WIDTH = 64,
|
||||
parameter ADDRESS_WIDTH = 5,
|
||||
parameter ASYNC_CLK = 1,
|
||||
parameter M_AXIS_REGISTERED = 1,
|
||||
parameter [ADDRESS_WIDTH-1:0] ALMOST_EMPTY_THRESHOLD = 16,
|
||||
parameter [ADDRESS_WIDTH-1:0] ALMOST_FULL_THRESHOLD = 16,
|
||||
parameter TLAST_EN = 0,
|
||||
parameter TKEEP_EN = 0,
|
||||
parameter REMOVE_NULL_BEAT_EN = 0
|
||||
) (
|
||||
input m_axis_aclk,
|
||||
input m_axis_aresetn,
|
||||
input m_axis_ready,
|
||||
output m_axis_valid,
|
||||
output [DATA_WIDTH-1:0] m_axis_data,
|
||||
output [DATA_WIDTH/8-1:0] m_axis_tkeep,
|
||||
output m_axis_tlast,
|
||||
output [ADDRESS_WIDTH-1:0] m_axis_level,
|
||||
output m_axis_empty,
|
||||
output m_axis_almost_empty,
|
||||
|
||||
input s_axis_aclk,
|
||||
input s_axis_aresetn,
|
||||
output s_axis_ready,
|
||||
input s_axis_valid,
|
||||
input [DATA_WIDTH-1:0] s_axis_data,
|
||||
input [DATA_WIDTH/8-1:0] s_axis_tkeep,
|
||||
input s_axis_tlast,
|
||||
output [ADDRESS_WIDTH-1:0] s_axis_room,
|
||||
output s_axis_full,
|
||||
output s_axis_almost_full
|
||||
);
|
||||
|
||||
localparam MEM_WORD = (TKEEP_EN & TLAST_EN) ? (DATA_WIDTH+DATA_WIDTH/8+1) :
|
||||
(TKEEP_EN) ? (DATA_WIDTH+DATA_WIDTH/8) :
|
||||
(TLAST_EN) ? (DATA_WIDTH+1) :
|
||||
(DATA_WIDTH);
|
||||
|
||||
wire [MEM_WORD-1:0] s_axis_data_int_s;
|
||||
wire [MEM_WORD-1:0] m_axis_data_int_s;
|
||||
|
||||
generate if (ADDRESS_WIDTH == 0) begin : zerodeep /* it's not a real FIFO, just a 1 stage pipeline */
|
||||
|
||||
if (ASYNC_CLK) begin
|
||||
|
||||
(* KEEP = "yes" *) reg [DATA_WIDTH-1:0] cdc_sync_fifo_ram;
|
||||
reg s_axis_waddr = 1'b0;
|
||||
reg m_axis_raddr = 1'b0;
|
||||
|
||||
wire m_axis_waddr;
|
||||
wire s_axis_raddr;
|
||||
|
||||
sync_bits #(
|
||||
.NUM_OF_BITS(1),
|
||||
.ASYNC_CLK(ASYNC_CLK)
|
||||
) i_waddr_sync (
|
||||
.out_clk(m_axis_aclk),
|
||||
.out_resetn(m_axis_aresetn),
|
||||
.in_bits(s_axis_waddr),
|
||||
.out_bits(m_axis_waddr));
|
||||
|
||||
sync_bits #(
|
||||
.NUM_OF_BITS(1),
|
||||
.ASYNC_CLK(ASYNC_CLK)
|
||||
) i_raddr_sync (
|
||||
.out_clk(s_axis_aclk),
|
||||
.out_resetn(s_axis_aresetn),
|
||||
.in_bits(m_axis_raddr),
|
||||
.out_bits(s_axis_raddr));
|
||||
|
||||
assign m_axis_valid = m_axis_raddr != m_axis_waddr;
|
||||
assign m_axis_level = ~m_axis_ready;
|
||||
assign m_axis_empty = 0;
|
||||
assign m_axis_almost_empty = 0;
|
||||
assign s_axis_ready = s_axis_raddr == s_axis_waddr;
|
||||
assign s_axis_full = 0;
|
||||
assign s_axis_almost_full = 0;
|
||||
assign s_axis_room = s_axis_ready;
|
||||
|
||||
always @(posedge s_axis_aclk) begin
|
||||
if (s_axis_ready == 1'b1 && s_axis_valid == 1'b1)
|
||||
cdc_sync_fifo_ram <= s_axis_data;
|
||||
end
|
||||
|
||||
always @(posedge s_axis_aclk) begin
|
||||
if (s_axis_aresetn == 1'b0) begin
|
||||
s_axis_waddr <= 1'b0;
|
||||
end else if (s_axis_ready & s_axis_valid) begin
|
||||
s_axis_waddr <= s_axis_waddr + 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge m_axis_aclk) begin
|
||||
if (m_axis_aresetn == 1'b0) begin
|
||||
m_axis_raddr <= 1'b0;
|
||||
end else begin
|
||||
if (m_axis_valid & m_axis_ready)
|
||||
m_axis_raddr <= m_axis_raddr + 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
assign m_axis_data = cdc_sync_fifo_ram;
|
||||
|
||||
// TLAST support
|
||||
if (TLAST_EN) begin
|
||||
|
||||
reg axis_tlast_d;
|
||||
|
||||
always @(posedge s_axis_aclk) begin
|
||||
if (s_axis_ready == 1'b1 && s_axis_valid == 1'b1)
|
||||
axis_tlast_d <= s_axis_tlast;
|
||||
end
|
||||
assign m_axis_tlast = axis_tlast_d;
|
||||
end else
|
||||
assign m_axis_tlast = 'b0;
|
||||
|
||||
// TKEEP support
|
||||
if (TKEEP_EN) begin
|
||||
|
||||
reg axis_tkeep_d;
|
||||
|
||||
always @(posedge s_axis_aclk) begin
|
||||
if (s_axis_ready == 1'b1 && s_axis_valid == 1'b1)
|
||||
axis_tkeep_d <= s_axis_tkeep;
|
||||
end
|
||||
assign m_axis_tkeep = axis_tkeep_d;
|
||||
end else
|
||||
assign m_axis_tkeep = {DATA_WIDTH/8{1'b1}};
|
||||
|
||||
end /* zerodeep */
|
||||
else
|
||||
begin /* !ASYNC_CLK */
|
||||
|
||||
// Note: In this mode, the write and read interface must have a symmetric
|
||||
// aspect ratio
|
||||
reg [DATA_WIDTH-1:0] axis_data_d;
|
||||
reg axis_valid_d;
|
||||
|
||||
always @(posedge s_axis_aclk) begin
|
||||
if (!s_axis_aresetn) begin
|
||||
axis_data_d <= {DATA_WIDTH{1'b0}};
|
||||
axis_valid_d <= 1'b0;
|
||||
end else if (s_axis_ready) begin
|
||||
axis_data_d <= s_axis_data;
|
||||
axis_valid_d <= s_axis_valid;
|
||||
end
|
||||
end
|
||||
|
||||
assign m_axis_data = axis_data_d;
|
||||
assign m_axis_valid = axis_valid_d;
|
||||
assign s_axis_ready = m_axis_ready | ~m_axis_valid;
|
||||
assign m_axis_empty = 1'b0;
|
||||
assign m_axis_almost_empty = 1'b0;
|
||||
assign m_axis_level = 1'b0;
|
||||
assign s_axis_full = 1'b0;
|
||||
assign s_axis_almost_full = 1'b0;
|
||||
assign s_axis_room = 1'b0;
|
||||
|
||||
// TLAST support
|
||||
if (TLAST_EN) begin
|
||||
reg axis_tlast_d;
|
||||
|
||||
always @(posedge s_axis_aclk) begin
|
||||
if (!s_axis_aresetn) begin
|
||||
axis_tlast_d <= 1'b0;
|
||||
end else if (s_axis_ready) begin
|
||||
axis_tlast_d <= s_axis_tlast;
|
||||
end
|
||||
end
|
||||
assign m_axis_tlast = axis_tlast_d;
|
||||
end else
|
||||
assign m_axis_tlast = 'b0;
|
||||
|
||||
// TKEEP support
|
||||
if (TKEEP_EN) begin
|
||||
reg axis_tkeep_d;
|
||||
|
||||
always @(posedge s_axis_aclk) begin
|
||||
if (!s_axis_aresetn) begin
|
||||
axis_tkeep_d <= 1'b0;
|
||||
end else if (s_axis_ready) begin
|
||||
axis_tkeep_d <= s_axis_tkeep;
|
||||
end
|
||||
end
|
||||
assign m_axis_tkeep = axis_tkeep_d;
|
||||
end else
|
||||
assign m_axis_tkeep = {DATA_WIDTH/8{1'b1}};
|
||||
|
||||
end /* !ASYNC_CLK */
|
||||
|
||||
end else begin : fifo /* ADDRESS_WIDTH != 0 - this is a real FIFO implementation */
|
||||
|
||||
wire [ADDRESS_WIDTH-1:0] s_axis_waddr;
|
||||
wire [ADDRESS_WIDTH-1:0] m_axis_raddr;
|
||||
wire _m_axis_ready;
|
||||
wire _m_axis_valid;
|
||||
|
||||
wire s_mem_write;
|
||||
wire m_mem_read;
|
||||
|
||||
reg valid = 1'b0;
|
||||
|
||||
/* Control for first falls through */
|
||||
always @(posedge m_axis_aclk) begin
|
||||
if (m_axis_aresetn == 1'b0) begin
|
||||
valid <= 1'b0;
|
||||
end else begin
|
||||
if (_m_axis_valid)
|
||||
valid <= 1'b1;
|
||||
else if (m_axis_ready)
|
||||
valid <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
if (REMOVE_NULL_BEAT_EN) begin
|
||||
// remove NULL bytes from the stream - NOTE: TKEEP is all-LOW or all-HIGH
|
||||
assign s_mem_write = s_axis_ready & s_axis_valid & (&s_axis_tkeep);
|
||||
end else begin
|
||||
assign s_mem_write = s_axis_ready & s_axis_valid;
|
||||
end
|
||||
assign m_mem_read = (~valid || m_axis_ready) && _m_axis_valid;
|
||||
|
||||
util_axis_fifo_address_generator #(
|
||||
.ASYNC_CLK(ASYNC_CLK),
|
||||
.ADDRESS_WIDTH(ADDRESS_WIDTH),
|
||||
.ALMOST_EMPTY_THRESHOLD (ALMOST_EMPTY_THRESHOLD),
|
||||
.ALMOST_FULL_THRESHOLD (ALMOST_FULL_THRESHOLD)
|
||||
) i_address_gray (
|
||||
.m_axis_aclk(m_axis_aclk),
|
||||
.m_axis_aresetn(m_axis_aresetn),
|
||||
.m_axis_ready(_m_axis_ready),
|
||||
.m_axis_valid(_m_axis_valid),
|
||||
.m_axis_raddr(m_axis_raddr),
|
||||
.m_axis_level(m_axis_level),
|
||||
.m_axis_empty(m_axis_empty),
|
||||
.m_axis_almost_empty(m_axis_almost_empty),
|
||||
.s_axis_aclk(s_axis_aclk),
|
||||
.s_axis_aresetn(s_axis_aresetn),
|
||||
.s_axis_ready(s_axis_ready),
|
||||
.s_axis_valid(s_axis_valid),
|
||||
.s_axis_full(s_axis_full),
|
||||
.s_axis_almost_full(s_axis_almost_full),
|
||||
.s_axis_waddr(s_axis_waddr),
|
||||
.s_axis_room(s_axis_room));
|
||||
|
||||
// TLAST and TKEEP support
|
||||
if (TLAST_EN & TKEEP_EN) begin
|
||||
assign s_axis_data_int_s = {s_axis_tkeep, s_axis_tlast, s_axis_data};
|
||||
assign m_axis_tkeep = m_axis_data_int_s[MEM_WORD-1-:DATA_WIDTH/8];
|
||||
assign m_axis_tlast = m_axis_data_int_s[DATA_WIDTH];
|
||||
assign m_axis_data = m_axis_data_int_s[DATA_WIDTH-1:0];
|
||||
end else if (TKEEP_EN) begin
|
||||
assign s_axis_data_int_s = {s_axis_tkeep, s_axis_data};
|
||||
assign m_axis_tkeep = m_axis_data_int_s[MEM_WORD-1-:DATA_WIDTH/8];
|
||||
assign m_axis_tlast = 'b0;
|
||||
assign m_axis_data = m_axis_data_int_s[DATA_WIDTH-1:0];
|
||||
end else if (TLAST_EN) begin
|
||||
assign s_axis_data_int_s = {s_axis_tlast, s_axis_data};
|
||||
assign m_axis_tkeep = {DATA_WIDTH/8{1'b1}};
|
||||
assign m_axis_tlast = m_axis_data_int_s[DATA_WIDTH];
|
||||
assign m_axis_data = m_axis_data_int_s[DATA_WIDTH-1:0];
|
||||
end else begin
|
||||
assign s_axis_data_int_s = {s_axis_data};
|
||||
assign m_axis_tkeep = {DATA_WIDTH/8{1'b1}};
|
||||
assign m_axis_tlast = 'b0;
|
||||
assign m_axis_data = m_axis_data_int_s[DATA_WIDTH-1:0];
|
||||
end
|
||||
|
||||
if (ASYNC_CLK == 1) begin : async_clocks /* Asynchronous WRITE/READ clocks */
|
||||
|
||||
// The assumption is that in this mode the M_AXIS_REGISTERED is 1
|
||||
// When the clocks are asynchronous instantiate a block RAM
|
||||
// regardless of the requested size to make sure we threat the
|
||||
// clock crossing correctly
|
||||
ad_mem #(
|
||||
.DATA_WIDTH (MEM_WORD),
|
||||
.ADDRESS_WIDTH (ADDRESS_WIDTH)
|
||||
) i_mem (
|
||||
.clka(s_axis_aclk),
|
||||
.wea(s_mem_write),
|
||||
.addra(s_axis_waddr),
|
||||
.dina(s_axis_data_int_s),
|
||||
.clkb(m_axis_aclk),
|
||||
.reb(m_mem_read),
|
||||
.addrb(m_axis_raddr),
|
||||
.doutb(m_axis_data_int_s));
|
||||
|
||||
assign _m_axis_ready = ~valid || m_axis_ready;
|
||||
assign m_axis_valid = valid;
|
||||
|
||||
end else begin : sync_clocks /* Synchronous WRITE/READ clocks */
|
||||
|
||||
reg [MEM_WORD-1:0] ram[0:2**ADDRESS_WIDTH-1];
|
||||
|
||||
// When the clocks are synchronous use behavioral modeling for the SDP RAM
|
||||
// Let the synthesizer decide what to infer (distributed or block RAM)
|
||||
always @(posedge s_axis_aclk) begin
|
||||
if (s_mem_write)
|
||||
ram[s_axis_waddr] <= s_axis_data_int_s;
|
||||
end
|
||||
|
||||
if (M_AXIS_REGISTERED == 1) begin
|
||||
|
||||
reg [MEM_WORD-1:0] data;
|
||||
|
||||
always @(posedge m_axis_aclk) begin
|
||||
if (m_mem_read)
|
||||
data <= ram[m_axis_raddr];
|
||||
end
|
||||
|
||||
assign _m_axis_ready = ~valid || m_axis_ready;
|
||||
assign m_axis_data_int_s = data;
|
||||
assign m_axis_valid = valid;
|
||||
|
||||
end else begin
|
||||
|
||||
assign _m_axis_ready = m_axis_ready;
|
||||
assign m_axis_valid = _m_axis_valid;
|
||||
assign m_axis_data_int_s = ram[m_axis_raddr];
|
||||
|
||||
end
|
||||
end
|
||||
end /* fifo */
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,172 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
module util_axis_fifo_address_generator #(
|
||||
parameter ASYNC_CLK = 0, // single or double clocked FIFO
|
||||
parameter ADDRESS_WIDTH = 4, // address width, effective FIFO depth
|
||||
parameter [ADDRESS_WIDTH-1:0] ALMOST_EMPTY_THRESHOLD = 16,
|
||||
parameter [ADDRESS_WIDTH-1:0] ALMOST_FULL_THRESHOLD = 16
|
||||
) (
|
||||
|
||||
// Read interface - Sink side
|
||||
|
||||
input m_axis_aclk,
|
||||
input m_axis_aresetn,
|
||||
input m_axis_ready,
|
||||
output m_axis_valid,
|
||||
output m_axis_empty,
|
||||
output m_axis_almost_empty,
|
||||
output [ADDRESS_WIDTH-1:0] m_axis_raddr,
|
||||
output [ADDRESS_WIDTH-1:0] m_axis_level,
|
||||
|
||||
// Write interface - Source side
|
||||
|
||||
input s_axis_aclk,
|
||||
input s_axis_aresetn,
|
||||
output s_axis_ready,
|
||||
input s_axis_valid,
|
||||
output s_axis_full,
|
||||
output s_axis_almost_full,
|
||||
output [ADDRESS_WIDTH-1:0] s_axis_waddr,
|
||||
output [ADDRESS_WIDTH-1:0] s_axis_room
|
||||
);
|
||||
|
||||
localparam FIFO_DEPTH = {ADDRESS_WIDTH{1'b1}};
|
||||
|
||||
// Definition of address counters
|
||||
// All the counters are wider with one bit to indicate wraparounds
|
||||
reg [ADDRESS_WIDTH:0] s_axis_waddr_reg = 'h0;
|
||||
reg [ADDRESS_WIDTH:0] m_axis_raddr_reg = 'h0;
|
||||
|
||||
wire [ADDRESS_WIDTH:0] s_axis_raddr_reg;
|
||||
wire [ADDRESS_WIDTH:0] m_axis_waddr_reg;
|
||||
|
||||
wire s_axis_write_s;
|
||||
wire s_axis_ready_s;
|
||||
|
||||
wire m_axis_read_s;
|
||||
wire m_axis_valid_s;
|
||||
wire [ADDRESS_WIDTH-1:0] m_axis_level_s;
|
||||
|
||||
// Write address counter
|
||||
|
||||
assign s_axis_write_s = s_axis_ready && s_axis_valid && ~s_axis_full;
|
||||
always @(posedge s_axis_aclk)
|
||||
begin
|
||||
if (!s_axis_aresetn)
|
||||
s_axis_waddr_reg <= 'h0;
|
||||
else
|
||||
if (s_axis_write_s)
|
||||
s_axis_waddr_reg <= s_axis_waddr_reg + 1'b1;
|
||||
end
|
||||
|
||||
// Read address counter
|
||||
|
||||
assign m_axis_read_s = m_axis_ready && m_axis_valid && ~m_axis_empty;
|
||||
always @(posedge m_axis_aclk)
|
||||
begin
|
||||
if (!m_axis_aresetn)
|
||||
m_axis_raddr_reg <= 'h0;
|
||||
else
|
||||
if (m_axis_read_s)
|
||||
m_axis_raddr_reg <= m_axis_raddr_reg + 1'b1;
|
||||
end
|
||||
|
||||
// Output assignments
|
||||
|
||||
assign s_axis_waddr = s_axis_waddr_reg[ADDRESS_WIDTH-1:0];
|
||||
assign m_axis_raddr = m_axis_raddr_reg[ADDRESS_WIDTH-1:0];
|
||||
|
||||
// CDC circuits for double clock configuration
|
||||
|
||||
generate if (ASYNC_CLK == 1) begin : g_async_clock
|
||||
// CDC transfer of the write pointer to the read clock domain
|
||||
sync_gray #(
|
||||
.DATA_WIDTH(ADDRESS_WIDTH + 1)
|
||||
) i_waddr_sync_gray (
|
||||
.in_clk(s_axis_aclk),
|
||||
.in_resetn(s_axis_aresetn),
|
||||
.out_clk(m_axis_aclk),
|
||||
.out_resetn(m_axis_aresetn),
|
||||
.in_count(s_axis_waddr_reg),
|
||||
.out_count(m_axis_waddr_reg));
|
||||
|
||||
// CDC transfer of the read pointer to the write clock domain
|
||||
sync_gray #(
|
||||
.DATA_WIDTH(ADDRESS_WIDTH + 1)
|
||||
) i_raddr_sync_gray (
|
||||
.in_clk(m_axis_aclk),
|
||||
.in_resetn(m_axis_aresetn),
|
||||
.out_clk(s_axis_aclk),
|
||||
.out_resetn(s_axis_aresetn),
|
||||
.in_count(m_axis_raddr_reg),
|
||||
.out_count(s_axis_raddr_reg));
|
||||
end else begin
|
||||
assign m_axis_waddr_reg = s_axis_waddr_reg;
|
||||
assign s_axis_raddr_reg = m_axis_raddr_reg;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
// FIFO write logic - upstream
|
||||
//
|
||||
// s_axis_full - FIFO is full if next write pointer equal to read pointer
|
||||
// s_axis_ready - FIFO is always ready, unless it's full
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
wire [ADDRESS_WIDTH:0] s_axis_fifo_fill = s_axis_waddr_reg - s_axis_raddr_reg;
|
||||
assign s_axis_full = (s_axis_fifo_fill == {ADDRESS_WIDTH{1'b1}});
|
||||
assign s_axis_almost_full = s_axis_fifo_fill > {1'b0, ~ALMOST_FULL_THRESHOLD};
|
||||
assign s_axis_ready = ~s_axis_full;
|
||||
assign s_axis_room = ~s_axis_fifo_fill;
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
// FIFO read logic - downstream
|
||||
//
|
||||
// m_axis_empty - FIFO is empty if read pointer equal to write pointer
|
||||
// m_axis_valid - FIFO has a valid output data, if it's not empty
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
wire [ADDRESS_WIDTH:0] m_axis_fifo_fill = m_axis_waddr_reg - m_axis_raddr_reg;
|
||||
assign m_axis_empty = m_axis_fifo_fill == 0;
|
||||
assign m_axis_almost_empty = (m_axis_fifo_fill < ALMOST_EMPTY_THRESHOLD);
|
||||
assign m_axis_valid = ~m_axis_empty;
|
||||
assign m_axis_level = m_axis_fifo_fill;
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,176 @@
|
||||
|
||||
# Loading additional proc with user specified bodies to compute parameter values.
|
||||
source [file join [file dirname [file dirname [info script]]] gui/util_axis_fifo_v1_0.gtcl]
|
||||
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set AXI_Stream_FIFO [ipgui::add_page $IPINST -name "AXI Stream FIFO"]
|
||||
#Adding Group
|
||||
set Clock_Configuration [ipgui::add_group $IPINST -name "Clock Configuration" -parent ${AXI_Stream_FIFO}]
|
||||
set ASYNC_CLK [ipgui::add_param $IPINST -name "ASYNC_CLK" -parent ${Clock_Configuration} -widget comboBox]
|
||||
set_property tooltip {[ASYNC_CLK] If enabled the readn and write interface of the FIFO is asynchronous (its clocks are from different clock domain).} ${ASYNC_CLK}
|
||||
|
||||
#Adding Group
|
||||
set Interface_Configuration [ipgui::add_group $IPINST -name "Interface Configuration" -parent ${AXI_Stream_FIFO}]
|
||||
set DATA_WIDTH [ipgui::add_param $IPINST -name "DATA_WIDTH" -parent ${Interface_Configuration} -widget comboBox]
|
||||
set_property tooltip {[DATA_WIDTH] Data width of the AXI stream interfaces.} ${DATA_WIDTH}
|
||||
set ADDRESS_WIDTH [ipgui::add_param $IPINST -name "ADDRESS_WIDTH" -parent ${Interface_Configuration}]
|
||||
set_property tooltip {[ADDRESS_WIDTH] Address width of the read and write address pointers. It defines the depth of the FIFO : DATA_WIDTH/8 * (2 ^ ADDRESS_WIDTH)} ${ADDRESS_WIDTH}
|
||||
set ALMOST_FULL_THRESHOLD [ipgui::add_param $IPINST -name "ALMOST_FULL_THRESHOLD" -parent ${Interface_Configuration}]
|
||||
set_property tooltip {[ALMOST_FULL_THRESHOLD] The offset between the almost full assertion and full assertion in number of FIFO words.} ${ALMOST_FULL_THRESHOLD}
|
||||
set ALMOST_EMPTY_THRESHOLD [ipgui::add_param $IPINST -name "ALMOST_EMPTY_THRESHOLD" -parent ${Interface_Configuration}]
|
||||
set_property tooltip {[ALMOST_EMPTY_THRESHOLD] The offset between the almost empty assertion and empty assertion in number of FIFO words.} ${ALMOST_EMPTY_THRESHOLD}
|
||||
set TLAST_EN [ipgui::add_param $IPINST -name "TLAST_EN" -parent ${Interface_Configuration}]
|
||||
set_property tooltip {[TLAST_EN] Enable the TLAST for the AXI stream interface, signaling packet boundaries.} ${TLAST_EN}
|
||||
set TKEEP_EN [ipgui::add_param $IPINST -name "TKEEP_EN" -parent ${Interface_Configuration}]
|
||||
set_property tooltip {[TKEEP_EN] Enable the TKEEP for the AXI stream interface, for data byte qualification for each AXIS beat.} ${TKEEP_EN}
|
||||
|
||||
#Adding Group
|
||||
set Other_Features [ipgui::add_group $IPINST -name "Other Features" -parent ${AXI_Stream_FIFO}]
|
||||
set M_AXIS_REGISTERED [ipgui::add_param $IPINST -name "M_AXIS_REGISTERED" -parent ${Other_Features}]
|
||||
set_property tooltip {[M_AXIS_REGISTERED] Add an additional register stage to the master AXI stream data output.} ${M_AXIS_REGISTERED}
|
||||
set REMOVE_NULL_BEAT_EN [ipgui::add_param $IPINST -name "REMOVE_NULL_BEAT_EN" -parent ${Other_Features}]
|
||||
set_property tooltip {[REMOVE_NULL_BEAT_EN] Filteres out all the beats with a null TKEEP qualifier.} ${REMOVE_NULL_BEAT_EN}
|
||||
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.REMOVE_NULL_BEAT_EN { PARAM_VALUE.REMOVE_NULL_BEAT_EN PARAM_VALUE.TKEEP_EN } {
|
||||
# Procedure called to update REMOVE_NULL_BEAT_EN when any of the dependent parameters in the arguments change
|
||||
|
||||
set REMOVE_NULL_BEAT_EN ${PARAM_VALUE.REMOVE_NULL_BEAT_EN}
|
||||
set TKEEP_EN ${PARAM_VALUE.TKEEP_EN}
|
||||
set values(TKEEP_EN) [get_property value $TKEEP_EN]
|
||||
if { [gen_USERPARAMETER_REMOVE_NULL_BEAT_EN_ENABLEMENT $values(TKEEP_EN)] } {
|
||||
set_property enabled true $REMOVE_NULL_BEAT_EN
|
||||
} else {
|
||||
set_property enabled false $REMOVE_NULL_BEAT_EN
|
||||
}
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.REMOVE_NULL_BEAT_EN { PARAM_VALUE.REMOVE_NULL_BEAT_EN } {
|
||||
# Procedure called to validate REMOVE_NULL_BEAT_EN
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.ADDRESS_WIDTH { PARAM_VALUE.ADDRESS_WIDTH } {
|
||||
# Procedure called to update ADDRESS_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.ADDRESS_WIDTH { PARAM_VALUE.ADDRESS_WIDTH } {
|
||||
# Procedure called to validate ADDRESS_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.ALMOST_EMPTY_THRESHOLD { PARAM_VALUE.ALMOST_EMPTY_THRESHOLD } {
|
||||
# Procedure called to update ALMOST_EMPTY_THRESHOLD when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.ALMOST_EMPTY_THRESHOLD { PARAM_VALUE.ALMOST_EMPTY_THRESHOLD } {
|
||||
# Procedure called to validate ALMOST_EMPTY_THRESHOLD
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.ALMOST_FULL_THRESHOLD { PARAM_VALUE.ALMOST_FULL_THRESHOLD } {
|
||||
# Procedure called to update ALMOST_FULL_THRESHOLD when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.ALMOST_FULL_THRESHOLD { PARAM_VALUE.ALMOST_FULL_THRESHOLD } {
|
||||
# Procedure called to validate ALMOST_FULL_THRESHOLD
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.ASYNC_CLK { PARAM_VALUE.ASYNC_CLK } {
|
||||
# Procedure called to update ASYNC_CLK when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.ASYNC_CLK { PARAM_VALUE.ASYNC_CLK } {
|
||||
# Procedure called to validate ASYNC_CLK
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } {
|
||||
# Procedure called to update DATA_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } {
|
||||
# Procedure called to validate DATA_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.M_AXIS_REGISTERED { PARAM_VALUE.M_AXIS_REGISTERED } {
|
||||
# Procedure called to update M_AXIS_REGISTERED when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.M_AXIS_REGISTERED { PARAM_VALUE.M_AXIS_REGISTERED } {
|
||||
# Procedure called to validate M_AXIS_REGISTERED
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.TKEEP_EN { PARAM_VALUE.TKEEP_EN } {
|
||||
# Procedure called to update TKEEP_EN when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.TKEEP_EN { PARAM_VALUE.TKEEP_EN } {
|
||||
# Procedure called to validate TKEEP_EN
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.TLAST_EN { PARAM_VALUE.TLAST_EN } {
|
||||
# Procedure called to update TLAST_EN when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.TLAST_EN { PARAM_VALUE.TLAST_EN } {
|
||||
# Procedure called to validate TLAST_EN
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.DATA_WIDTH { MODELPARAM_VALUE.DATA_WIDTH PARAM_VALUE.DATA_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DATA_WIDTH}] ${MODELPARAM_VALUE.DATA_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.ADDRESS_WIDTH { MODELPARAM_VALUE.ADDRESS_WIDTH PARAM_VALUE.ADDRESS_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.ADDRESS_WIDTH}] ${MODELPARAM_VALUE.ADDRESS_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.ASYNC_CLK { MODELPARAM_VALUE.ASYNC_CLK PARAM_VALUE.ASYNC_CLK } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.ASYNC_CLK}] ${MODELPARAM_VALUE.ASYNC_CLK}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.M_AXIS_REGISTERED { MODELPARAM_VALUE.M_AXIS_REGISTERED PARAM_VALUE.M_AXIS_REGISTERED } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.M_AXIS_REGISTERED}] ${MODELPARAM_VALUE.M_AXIS_REGISTERED}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.ALMOST_EMPTY_THRESHOLD { MODELPARAM_VALUE.ALMOST_EMPTY_THRESHOLD PARAM_VALUE.ALMOST_EMPTY_THRESHOLD } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.ALMOST_EMPTY_THRESHOLD}] ${MODELPARAM_VALUE.ALMOST_EMPTY_THRESHOLD}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.ALMOST_FULL_THRESHOLD { MODELPARAM_VALUE.ALMOST_FULL_THRESHOLD PARAM_VALUE.ALMOST_FULL_THRESHOLD } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.ALMOST_FULL_THRESHOLD}] ${MODELPARAM_VALUE.ALMOST_FULL_THRESHOLD}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.TLAST_EN { MODELPARAM_VALUE.TLAST_EN PARAM_VALUE.TLAST_EN } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.TLAST_EN}] ${MODELPARAM_VALUE.TLAST_EN}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.TKEEP_EN { MODELPARAM_VALUE.TKEEP_EN PARAM_VALUE.TKEEP_EN } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.TKEEP_EN}] ${MODELPARAM_VALUE.TKEEP_EN}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.REMOVE_NULL_BEAT_EN { MODELPARAM_VALUE.REMOVE_NULL_BEAT_EN PARAM_VALUE.REMOVE_NULL_BEAT_EN } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.REMOVE_NULL_BEAT_EN}] ${MODELPARAM_VALUE.REMOVE_NULL_BEAT_EN}
|
||||
}
|
||||
|
||||
@@ -0,0 +1,247 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>analog.com</spirit:vendor>
|
||||
<spirit:library>user</spirit:library>
|
||||
<spirit:name>util_cdc</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
|
||||
<spirit:displayName>Synthesis</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
|
||||
<spirit:language>Verilog</spirit:language>
|
||||
<spirit:modelName>sync_event</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>c325f2fc</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:language>Verilog</spirit:language>
|
||||
<spirit:modelName>sync_event</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>c325f2fc</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_xpgui</spirit:name>
|
||||
<spirit:displayName>UI Layout</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>3416f698</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
</spirit:views>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:name>in_clk</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>in_event</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_EVENTS')) - 1)">0</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>out_clk</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>out_event</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_EVENTS')) - 1)">0</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>reg</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
</spirit:ports>
|
||||
<spirit:modelParameters>
|
||||
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
|
||||
<spirit:name>NUM_OF_EVENTS</spirit:name>
|
||||
<spirit:displayName>Num Of Events</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.NUM_OF_EVENTS">1</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>ASYNC_CLK</spirit:name>
|
||||
<spirit:displayName>Async Clk</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.ASYNC_CLK">1</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
</spirit:modelParameters>
|
||||
</spirit:model>
|
||||
<spirit:fileSets>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>sync_gray.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>sync_bits.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>sync_data.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>sync_event.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
<spirit:userFileType>CHECKSUM_fece0fbd</spirit:userFileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>sync_gray.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>sync_bits.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>sync_data.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>sync_event.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_xpgui_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>xgui/sync_event_v1_0.tcl</spirit:name>
|
||||
<spirit:fileType>tclSource</spirit:fileType>
|
||||
<spirit:userFileType>CHECKSUM_3416f698</spirit:userFileType>
|
||||
<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
</spirit:fileSets>
|
||||
<spirit:description>ADI Clock-Domain-Crossing Utils</spirit:description>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>NUM_OF_EVENTS</spirit:name>
|
||||
<spirit:displayName>Num Of Events</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.NUM_OF_EVENTS">1</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASYNC_CLK</spirit:name>
|
||||
<spirit:displayName>Async Clk</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.ASYNC_CLK">1</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>Component_Name</spirit:name>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">sync_event_v1_0</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:coreExtensions>
|
||||
<xilinx:supportedFamilies>
|
||||
<xilinx:family xilinx:lifeCycle="Production">virtex7</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">qvirtex7</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">versal</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">kintex7</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">kintex7l</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">qkintex7</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">qkintex7l</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">akintex7</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">artix7</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">artix7l</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">aartix7</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">qartix7</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">qzynq</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">azynq</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">spartan7</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">aspartan7</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">virtexu</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">zynquplus</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">virtexuplus</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">virtexuplusHBM</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">virtexuplus58g</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">kintexuplus</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">artixuplus</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">kintexu</xilinx:family>
|
||||
</xilinx:supportedFamilies>
|
||||
<xilinx:taxonomies>
|
||||
<xilinx:taxonomy>/Analog_Devices</xilinx:taxonomy>
|
||||
</xilinx:taxonomies>
|
||||
<xilinx:displayName>ADI Clock-Domain-Crossing Utils</xilinx:displayName>
|
||||
<xilinx:hideInCatalogGUI>true</xilinx:hideInCatalogGUI>
|
||||
<xilinx:autoFamilySupportLevel>level_2</xilinx:autoFamilySupportLevel>
|
||||
<xilinx:definitionSource>package_project</xilinx:definitionSource>
|
||||
<xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
|
||||
<xilinx:vendorURL>http://www.analog.com</xilinx:vendorURL>
|
||||
<xilinx:coreRevision>1</xilinx:coreRevision>
|
||||
<xilinx:coreCreationDateTime>2025-04-30T13:49:16Z</xilinx:coreCreationDateTime>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2024.1.2</xilinx:xilinxVersion>
|
||||
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="977245ef"/>
|
||||
<xilinx:checksum xilinx:scope="ports" xilinx:value="c5b57d4d"/>
|
||||
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="1f4d93c9"/>
|
||||
<xilinx:checksum xilinx:scope="parameters" xilinx:value="c38123f1"/>
|
||||
</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
@@ -0,0 +1,80 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
/*
|
||||
* Helper module for synchronizing bit signals from one clock domain to another.
|
||||
* It uses the standard approach of 2 FF in series.
|
||||
* Note, that while the module allows to synchronize multiple bits at once it is
|
||||
* only able to synchronize multi-bit signals where at max one bit changes per
|
||||
* clock cycle (e.g. a gray counter).
|
||||
*/
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module sync_bits #(
|
||||
|
||||
// Number of bits to synchronize
|
||||
parameter NUM_OF_BITS = 1,
|
||||
// Whether input and output clocks are asynchronous, if 0 the synchronizer will
|
||||
// be bypassed and the output signal equals the input signal.
|
||||
parameter ASYNC_CLK = 1
|
||||
) (
|
||||
input [NUM_OF_BITS-1:0] in_bits,
|
||||
input out_resetn,
|
||||
input out_clk,
|
||||
output [NUM_OF_BITS-1:0] out_bits
|
||||
);
|
||||
|
||||
generate if (ASYNC_CLK == 1) begin
|
||||
reg [NUM_OF_BITS-1:0] cdc_sync_stage1 = 'h0;
|
||||
reg [NUM_OF_BITS-1:0] cdc_sync_stage2 = 'h0;
|
||||
|
||||
always @(posedge out_clk)
|
||||
begin
|
||||
if (out_resetn == 1'b0) begin
|
||||
cdc_sync_stage1 <= 'b0;
|
||||
cdc_sync_stage2 <= 'b0;
|
||||
end else begin
|
||||
cdc_sync_stage1 <= in_bits;
|
||||
cdc_sync_stage2 <= cdc_sync_stage1;
|
||||
end
|
||||
end
|
||||
|
||||
assign out_bits = cdc_sync_stage2;
|
||||
end else begin
|
||||
assign out_bits = in_bits;
|
||||
end endgenerate
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,95 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module sync_data #(
|
||||
parameter NUM_OF_BITS = 1,
|
||||
parameter ASYNC_CLK = 1
|
||||
) (
|
||||
input in_clk,
|
||||
input [NUM_OF_BITS-1:0] in_data,
|
||||
input out_clk,
|
||||
output reg [NUM_OF_BITS-1:0] out_data
|
||||
);
|
||||
|
||||
generate
|
||||
if (ASYNC_CLK == 1) begin
|
||||
|
||||
wire out_toggle;
|
||||
wire in_toggle;
|
||||
|
||||
reg out_toggle_d1 = 1'b0;
|
||||
reg in_toggle_d1 = 1'b0;
|
||||
|
||||
reg [NUM_OF_BITS-1:0] cdc_hold;
|
||||
|
||||
sync_bits i_sync_out (
|
||||
.in_bits(in_toggle_d1),
|
||||
.out_clk(out_clk),
|
||||
.out_resetn(1'b1),
|
||||
.out_bits(out_toggle));
|
||||
|
||||
sync_bits i_sync_in (
|
||||
.in_bits(out_toggle_d1),
|
||||
.out_clk(in_clk),
|
||||
.out_resetn(1'b1),
|
||||
.out_bits(in_toggle));
|
||||
|
||||
wire in_load = in_toggle == in_toggle_d1;
|
||||
wire out_load = out_toggle ^ out_toggle_d1;
|
||||
|
||||
always @(posedge in_clk) begin
|
||||
if (in_load == 1'b1) begin
|
||||
cdc_hold <= in_data;
|
||||
in_toggle_d1 <= ~in_toggle_d1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge out_clk) begin
|
||||
if (out_load == 1'b1) begin
|
||||
out_data <= cdc_hold;
|
||||
end
|
||||
out_toggle_d1 <= out_toggle;
|
||||
end
|
||||
|
||||
end else begin
|
||||
always @(*) begin
|
||||
out_data <= in_data;
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,118 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module sync_event #(
|
||||
parameter NUM_OF_EVENTS = 1,
|
||||
parameter ASYNC_CLK = 1
|
||||
) (
|
||||
input in_clk,
|
||||
input [NUM_OF_EVENTS-1:0] in_event,
|
||||
input out_clk,
|
||||
output reg [NUM_OF_EVENTS-1:0] out_event
|
||||
);
|
||||
|
||||
generate
|
||||
if (ASYNC_CLK == 1) begin
|
||||
|
||||
wire out_toggle;
|
||||
wire in_toggle;
|
||||
|
||||
reg out_toggle_d1 = 1'b0;
|
||||
reg in_toggle_d1 = 1'b0;
|
||||
|
||||
sync_bits i_sync_out (
|
||||
.in_bits(in_toggle_d1),
|
||||
.out_clk(out_clk),
|
||||
.out_resetn(1'b1),
|
||||
.out_bits(out_toggle));
|
||||
|
||||
sync_bits i_sync_in (
|
||||
.in_bits(out_toggle_d1),
|
||||
.out_clk(in_clk),
|
||||
.out_resetn(1'b1),
|
||||
.out_bits(in_toggle));
|
||||
|
||||
wire in_ready = in_toggle == in_toggle_d1;
|
||||
wire load_out = out_toggle ^ out_toggle_d1;
|
||||
|
||||
reg [NUM_OF_EVENTS-1:0] in_event_sticky = 'h00;
|
||||
wire [NUM_OF_EVENTS-1:0] pending_events = in_event_sticky | in_event;
|
||||
wire [NUM_OF_EVENTS-1:0] out_event_s;
|
||||
|
||||
always @(posedge in_clk) begin
|
||||
if (in_ready == 1'b1) begin
|
||||
in_event_sticky <= {NUM_OF_EVENTS{1'b0}};
|
||||
if (|pending_events == 1'b1) begin
|
||||
in_toggle_d1 <= ~in_toggle_d1;
|
||||
end
|
||||
end else begin
|
||||
in_event_sticky <= pending_events;
|
||||
end
|
||||
end
|
||||
|
||||
if (NUM_OF_EVENTS > 1) begin
|
||||
reg [NUM_OF_EVENTS-1:0] cdc_hold = 'h00;
|
||||
|
||||
always @(posedge in_clk) begin
|
||||
if (in_ready == 1'b1) begin
|
||||
cdc_hold <= pending_events;
|
||||
end
|
||||
end
|
||||
|
||||
assign out_event_s = cdc_hold;
|
||||
end else begin
|
||||
// When there is only one event, we know that it is set.
|
||||
assign out_event_s = 1'b1;
|
||||
end
|
||||
|
||||
always @(posedge out_clk) begin
|
||||
if (load_out == 1'b1) begin
|
||||
out_event <= out_event_s;
|
||||
end else begin
|
||||
out_event <= {NUM_OF_EVENTS{1'b0}};
|
||||
end
|
||||
out_toggle_d1 <= out_toggle;
|
||||
end
|
||||
|
||||
end else begin
|
||||
always @(*) begin
|
||||
out_event <= in_event;
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,116 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
/*
|
||||
* Helper module for synchronizing a counter from one clock domain to another
|
||||
* using gray code. To work correctly the counter must not change its value by
|
||||
* more than one in one clock cycle in the source domain. I.e. the value may
|
||||
* change by either -1, 0 or +1.
|
||||
*/
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module sync_gray #(
|
||||
|
||||
// Bit-width of the counter
|
||||
parameter DATA_WIDTH = 1,
|
||||
// Whether the input and output clock are asynchronous, if set to 0 the
|
||||
// synchronizer will be bypassed and out_count will be in_count.
|
||||
parameter ASYNC_CLK = 1
|
||||
) (
|
||||
input in_clk,
|
||||
input in_resetn,
|
||||
input [DATA_WIDTH-1:0] in_count,
|
||||
input out_resetn,
|
||||
input out_clk,
|
||||
output [DATA_WIDTH-1:0] out_count
|
||||
);
|
||||
|
||||
generate if (ASYNC_CLK == 1) begin
|
||||
reg [DATA_WIDTH-1:0] cdc_sync_stage0 = 'h0;
|
||||
reg [DATA_WIDTH-1:0] cdc_sync_stage1 = 'h0;
|
||||
reg [DATA_WIDTH-1:0] cdc_sync_stage2 = 'h0;
|
||||
reg [DATA_WIDTH-1:0] out_count_m = 'h0;
|
||||
|
||||
function [DATA_WIDTH-1:0] g2b;
|
||||
input [DATA_WIDTH-1:0] g;
|
||||
reg [DATA_WIDTH-1:0] b;
|
||||
integer i;
|
||||
begin
|
||||
b[DATA_WIDTH-1] = g[DATA_WIDTH-1];
|
||||
for (i = DATA_WIDTH - 2; i >= 0; i = i - 1)
|
||||
b[i] = b[i + 1] ^ g[i];
|
||||
g2b = b;
|
||||
end
|
||||
endfunction
|
||||
|
||||
function [DATA_WIDTH-1:0] b2g;
|
||||
input [DATA_WIDTH-1:0] b;
|
||||
reg [DATA_WIDTH-1:0] g;
|
||||
integer i;
|
||||
begin
|
||||
g[DATA_WIDTH-1] = b[DATA_WIDTH-1];
|
||||
for (i = DATA_WIDTH - 2; i >= 0; i = i -1)
|
||||
g[i] = b[i + 1] ^ b[i];
|
||||
b2g = g;
|
||||
end
|
||||
endfunction
|
||||
|
||||
always @(posedge in_clk) begin
|
||||
if (in_resetn == 1'b0) begin
|
||||
cdc_sync_stage0 <= 'h00;
|
||||
end else begin
|
||||
cdc_sync_stage0 <= b2g(in_count);
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge out_clk) begin
|
||||
if (out_resetn == 1'b0) begin
|
||||
cdc_sync_stage1 <= 'h00;
|
||||
cdc_sync_stage2 <= 'h00;
|
||||
out_count_m <= 'h00;
|
||||
end else begin
|
||||
cdc_sync_stage1 <= cdc_sync_stage0;
|
||||
cdc_sync_stage2 <= cdc_sync_stage1;
|
||||
out_count_m <= g2b(cdc_sync_stage2);
|
||||
end
|
||||
end
|
||||
|
||||
assign out_count = out_count_m;
|
||||
end else begin
|
||||
assign out_count = in_count;
|
||||
end endgenerate
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,40 @@
|
||||
###############################################################################
|
||||
## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIBSD
|
||||
###############################################################################
|
||||
|
||||
proc util_cdc_sync_bits_constr {inst {from {}}} {
|
||||
if {$from != {}} {
|
||||
set_false_path \
|
||||
-from [get_registers $from] \
|
||||
-to [get_registers [format "%s%s" ${inst} {|cdc_sync_stage1[0]}]]
|
||||
} else {
|
||||
set_false_path \
|
||||
-to [get_registers [format "%s%s" ${inst} {|cdc_sync_stage1[0]}]]
|
||||
}
|
||||
}
|
||||
|
||||
proc util_cdc_sync_data_constr {inst} {
|
||||
util_cdc_sync_bits_constr ${inst}|sync_bits:i_sync_out ${inst}|in_toggle_d1
|
||||
util_cdc_sync_bits_constr ${inst}|sync_bits:i_sync_in ${inst}|out_toggle_d1
|
||||
|
||||
# set_max_skew
|
||||
set_false_path \
|
||||
-from [get_registers [format "%s%s" ${inst} {|cdc_hold[*]}]] \
|
||||
-to [get_registers [format "%s%s" ${inst} {|out_data[*]}]]
|
||||
}
|
||||
|
||||
proc util_cdc_sync_event_constr {inst} {
|
||||
util_cdc_sync_bits_constr ${inst}|sync_bits:i_sync_out ${inst}|in_toggle_d1
|
||||
util_cdc_sync_bits_constr ${inst}|sync_bits:i_sync_in ${inst}|out_toggle_d1
|
||||
|
||||
set cdc_hold_reg [get_registers -nowarn [format "%s%s" ${inst} {|cdc_hold[*]}]]
|
||||
|
||||
# For a event synchronizer with one event there is no hold register
|
||||
if {[get_collection_size ${cdc_hold_reg}] != 0} {
|
||||
# set_max_skew
|
||||
set_false_path \
|
||||
-from ${cdc_hold_reg} \
|
||||
-to [get_registers [format "%s%s" ${inst} {|out_event[*]}]]
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,40 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
|
||||
ipgui::add_param $IPINST -name "ASYNC_CLK" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "NUM_OF_EVENTS" -parent ${Page_0}
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.ASYNC_CLK { PARAM_VALUE.ASYNC_CLK } {
|
||||
# Procedure called to update ASYNC_CLK when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.ASYNC_CLK { PARAM_VALUE.ASYNC_CLK } {
|
||||
# Procedure called to validate ASYNC_CLK
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.NUM_OF_EVENTS { PARAM_VALUE.NUM_OF_EVENTS } {
|
||||
# Procedure called to update NUM_OF_EVENTS when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.NUM_OF_EVENTS { PARAM_VALUE.NUM_OF_EVENTS } {
|
||||
# Procedure called to validate NUM_OF_EVENTS
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.NUM_OF_EVENTS { MODELPARAM_VALUE.NUM_OF_EVENTS PARAM_VALUE.NUM_OF_EVENTS } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.NUM_OF_EVENTS}] ${MODELPARAM_VALUE.NUM_OF_EVENTS}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.ASYNC_CLK { MODELPARAM_VALUE.ASYNC_CLK PARAM_VALUE.ASYNC_CLK } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.ASYNC_CLK}] ${MODELPARAM_VALUE.ASYNC_CLK}
|
||||
}
|
||||
|
||||
@@ -0,0 +1,14 @@
|
||||
###############################################################################
|
||||
## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIBSD
|
||||
###############################################################################
|
||||
|
||||
# the "-quiet" option is added for the axi_spi_engine ip where the ad_rst.v
|
||||
# module is not always inferred and this causes critical warnings
|
||||
|
||||
set_property -quiet ASYNC_REG TRUE [get_cells -hierarchical -filter {name =~ *rst_async_d*_reg}]
|
||||
set_property -quiet ASYNC_REG TRUE [get_cells -hierarchical -filter {name =~ *rst_sync_reg}]
|
||||
|
||||
set_false_path -quiet -to [get_pins -hierarchical *rst_sync_reg/PRE]
|
||||
set_false_path -quiet -to [get_pins -hierarchical *rst_async_d1_reg/PRE]
|
||||
set_false_path -quiet -to [get_pins -hierarchical *rst_async_d2_reg/PRE]
|
||||
Reference in New Issue
Block a user