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feat: 新增9371地检驱动工程, 9371自收发正常

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library/common/ad_mem.v
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// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_mem #(
parameter DATA_WIDTH = 16,
parameter ADDRESS_WIDTH = 5
) (
input clka,
input wea,
input [(ADDRESS_WIDTH-1):0] addra,
input [(DATA_WIDTH-1):0] dina,
input clkb,
input reb,
input [(ADDRESS_WIDTH-1):0] addrb,
output reg [(DATA_WIDTH-1):0] doutb
);
(* ram_style = "block" *)
reg [(DATA_WIDTH-1):0] m_ram[0:((2**ADDRESS_WIDTH)-1)];
always @(posedge clka) begin
if (wea == 1'b1) begin
m_ram[addra] <= dina;
end
end
always @(posedge clkb) begin
if (reb == 1'b1) begin
doutb <= m_ram[addrb];
end
end
endmodule
library/common/ad_mem_asym.v
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// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
// A simple asymetric memory. The write and read memory space must have the same size.
// 2^A_ADDRESS_WIDTH * A_DATA_WIDTH == 2^B_ADDRESS_WIDTH * B_DATA_WIDTH
`timescale 1ns/100ps
module ad_mem_asym #(
parameter A_ADDRESS_WIDTH = 8,
parameter A_DATA_WIDTH = 256,
parameter B_ADDRESS_WIDTH = 10,
parameter B_DATA_WIDTH = 64,
parameter CASCADE_HEIGHT = -1
) (
input clka,
input wea,
input [A_ADDRESS_WIDTH-1:0] addra,
input [A_DATA_WIDTH-1:0] dina,
input clkb,
input reb,
input [B_ADDRESS_WIDTH-1:0] addrb,
output reg [B_DATA_WIDTH-1:0] doutb
);
`define max(a,b) {(a) > (b) ? (a) : (b)}
`define min(a,b) {(a) < (b) ? (a) : (b)}
function integer clog2;
input integer value;
begin
if (value < 2)
clog2 = value;
else begin
value = value - 1;
for (clog2 = 0; value > 0; clog2 = clog2 + 1)
value = value >> 1;
end
end
endfunction
localparam MEM_ADDRESS_WIDTH = `max(A_ADDRESS_WIDTH, B_ADDRESS_WIDTH);
localparam MIN_WIDTH = `min(A_DATA_WIDTH, B_DATA_WIDTH);
localparam MAX_WIDTH = `max(A_DATA_WIDTH, B_DATA_WIDTH);
localparam MEM_DATA_WIDTH = MIN_WIDTH;
localparam MEM_SIZE = 2 ** MEM_ADDRESS_WIDTH;
localparam MEM_RATIO = MAX_WIDTH / MIN_WIDTH;
localparam MEM_RATIO_LOG2 = clog2(MEM_RATIO);
// internal registers
(* ram_style = "block", cascade_height = CASCADE_HEIGHT *)
reg [MEM_DATA_WIDTH-1:0] m_ram[0:MEM_SIZE-1];
//---------------------------------------------------------------------------
// write interface
//---------------------------------------------------------------------------
// write data width is narrower than read data width
generate if (A_DATA_WIDTH <= B_DATA_WIDTH) begin
always @(posedge clka) begin
if (wea == 1'b1) begin
m_ram[addra] <= dina;
end
end
end
endgenerate
// write data width is wider than read data width
generate if (A_DATA_WIDTH > B_DATA_WIDTH) begin
always @(posedge clka) begin : memwrite
integer i;
reg [MEM_RATIO_LOG2-1:0] lsb;
for (i = 0; i < MEM_RATIO; i = i + 1) begin : awrite
lsb = i;
if (wea) begin
m_ram[{addra, lsb}] <= dina[i * MIN_WIDTH +: MIN_WIDTH];
end
end
end
end
endgenerate
//---------------------------------------------------------------------------
// read interface
//---------------------------------------------------------------------------
// read data width is narrower than write data width
generate if (A_DATA_WIDTH >= B_DATA_WIDTH) begin
always @(posedge clkb) begin
if (reb == 1'b1) begin
doutb <= m_ram[addrb];
end
end
end
endgenerate
// read data width is wider than write data width
generate if (A_DATA_WIDTH < B_DATA_WIDTH) begin
always @(posedge clkb) begin : memread
integer i;
reg [MEM_RATIO_LOG2-1:0] lsb;
for (i = 0; i < MEM_RATIO; i = i + 1) begin : aread
lsb = i;
if (reb == 1'b1) begin
doutb[i*MIN_WIDTH +: MIN_WIDTH] <= m_ram[{addrb, lsb}];
end
end
end
end
endgenerate
endmodule
library/common/ad_rst.v
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// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_rst (
// clock reset
input rst_async,
input clk,
output rstn,
output reg rst
);
// internal registers
reg rst_async_d1 = 1'd1;
reg rst_async_d2 = 1'd1;
reg rst_sync = 1'd1;
reg rst_sync_d = 1'd1;
// simple reset synchronizer
always @(posedge clk or posedge rst_async) begin
if (rst_async) begin
rst_async_d1 <= 1'b1;
rst_async_d2 <= 1'b1;
rst_sync <= 1'b1;
end else begin
rst_async_d1 <= 1'b0;
rst_async_d2 <= rst_async_d1;
rst_sync <= rst_async_d2;
end
end
// two-stage synchronizer to prevent metastability on the falling edge
always @(posedge clk) begin
rst_sync_d <= rst_sync;
rst <= rst_sync_d;
end
assign rstn = ~rst;
endmodule
library/common/up_axi.v
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// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module up_axi #(
parameter AXI_ADDRESS_WIDTH = 16
) (
// reset and clocks
input up_rstn,
input up_clk,
// axi4 interface
input up_axi_awvalid,
input [(AXI_ADDRESS_WIDTH-1):0] up_axi_awaddr,
output up_axi_awready,
input up_axi_wvalid,
input [31:0] up_axi_wdata,
input [ 3:0] up_axi_wstrb,
output up_axi_wready,
output up_axi_bvalid,
output [ 1:0] up_axi_bresp,
input up_axi_bready,
input up_axi_arvalid,
input [(AXI_ADDRESS_WIDTH-1):0] up_axi_araddr,
output up_axi_arready,
output up_axi_rvalid,
output [ 1:0] up_axi_rresp,
output [31:0] up_axi_rdata,
input up_axi_rready,
// pcore interface
output up_wreq,
output [(AXI_ADDRESS_WIDTH-3):0] up_waddr,
output [31:0] up_wdata,
input up_wack,
output up_rreq,
output [(AXI_ADDRESS_WIDTH-3):0] up_raddr,
input [31:0] up_rdata,
input up_rack
);
// internal registers
reg up_axi_awready_int = 'd0;
reg up_axi_wready_int = 'd0;
reg up_axi_bvalid_int = 'd0;
reg up_wack_d = 'd0;
reg up_wsel = 'd0;
reg up_wreq_int = 'd0;
reg [(AXI_ADDRESS_WIDTH-3):0] up_waddr_int = 'd0;
reg [31:0] up_wdata_int = 'd0;
reg [ 4:0] up_wcount = 'd0;
reg up_axi_arready_int = 'd0;
reg up_axi_rvalid_int = 'd0;
reg [31:0] up_axi_rdata_int = 'd0;
reg up_rack_d = 'd0;
reg [31:0] up_rdata_d = 'd0;
reg up_rsel = 'd0;
reg up_rreq_int = 'd0;
reg [(AXI_ADDRESS_WIDTH-3):0] up_raddr_int = 'd0;
reg [ 4:0] up_rcount = 'd0;
// internal signals
wire up_wack_s;
wire up_rack_s;
wire [31:0] up_rdata_s;
// write channel interface
assign up_axi_awready = up_axi_awready_int;
assign up_axi_wready = up_axi_wready_int;
assign up_axi_bvalid = up_axi_bvalid_int;
assign up_axi_bresp = 2'd0;
always @(posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_axi_awready_int <= 'd0;
up_axi_wready_int <= 'd0;
up_axi_bvalid_int <= 'd0;
end else begin
if (up_axi_awready_int == 1'b1) begin
up_axi_awready_int <= 1'b0;
end else if (up_wack_s == 1'b1) begin
up_axi_awready_int <= 1'b1;
end
if (up_axi_wready_int == 1'b1) begin
up_axi_wready_int <= 1'b0;
end else if (up_wack_s == 1'b1) begin
up_axi_wready_int <= 1'b1;
end
if ((up_axi_bready == 1'b1) && (up_axi_bvalid_int == 1'b1)) begin
up_axi_bvalid_int <= 1'b0;
end else if (up_wack_d == 1'b1) begin
up_axi_bvalid_int <= 1'b1;
end
end
end
assign up_wreq = up_wreq_int;
assign up_waddr = up_waddr_int;
assign up_wdata = up_wdata_int;
assign up_wack_s = (up_wcount == 5'h1f) ? 1'b1 : (up_wcount[4] & up_wack);
always @(posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_wack_d <= 'd0;
up_wsel <= 'd0;
up_wreq_int <= 'd0;
up_waddr_int <= 'd0;
up_wdata_int <= 'd0;
up_wcount <= 'd0;
end else begin
up_wack_d <= up_wack_s;
if (up_wsel == 1'b1) begin
if ((up_axi_bready == 1'b1) && (up_axi_bvalid_int == 1'b1)) begin
up_wsel <= 1'b0;
end
up_wreq_int <= 1'b0;
end else begin
up_wsel <= up_axi_awvalid & up_axi_wvalid;
up_wreq_int <= up_axi_awvalid & up_axi_wvalid;
up_waddr_int <= up_axi_awaddr[(AXI_ADDRESS_WIDTH-1):2];
up_wdata_int <= up_axi_wdata;
end
if (up_wack_s == 1'b1) begin
up_wcount <= 5'h00;
end else if (up_wcount[4] == 1'b1) begin
up_wcount <= up_wcount + 1'b1;
end else if (up_wreq_int == 1'b1) begin
up_wcount <= 5'h10;
end
end
end
// read channel interface
assign up_axi_arready = up_axi_arready_int;
assign up_axi_rvalid = up_axi_rvalid_int;
assign up_axi_rdata = up_axi_rdata_int;
assign up_axi_rresp = 2'd0;
always @(posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_axi_arready_int <= 'd0;
up_axi_rvalid_int <= 'd0;
up_axi_rdata_int <= 'd0;
end else begin
if (up_axi_arready_int == 1'b1) begin
up_axi_arready_int <= 1'b0;
end else if (up_rack_s == 1'b1) begin
up_axi_arready_int <= 1'b1;
end
if ((up_axi_rready == 1'b1) && (up_axi_rvalid_int == 1'b1)) begin
up_axi_rvalid_int <= 1'b0;
up_axi_rdata_int <= 32'd0;
end else if (up_rack_d == 1'b1) begin
up_axi_rvalid_int <= 1'b1;
up_axi_rdata_int <= up_rdata_d;
end
end
end
assign up_rreq = up_rreq_int;
assign up_raddr = up_raddr_int;
assign up_rack_s = (up_rcount == 5'h1f) ? 1'b1 : (up_rcount[4] & up_rack);
assign up_rdata_s = (up_rcount == 5'h1f) ? {2{16'hdead}} : up_rdata;
always @(posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_rack_d <= 'd0;
up_rdata_d <= 'd0;
up_rsel <= 'd0;
up_rreq_int <= 'd0;
up_raddr_int <= 'd0;
up_rcount <= 'd0;
end else begin
up_rack_d <= up_rack_s;
up_rdata_d <= up_rdata_s;
if (up_rsel == 1'b1) begin
if ((up_axi_rready == 1'b1) && (up_axi_rvalid_int == 1'b1)) begin
up_rsel <= 1'b0;
end
up_rreq_int <= 1'b0;
end else begin
up_rsel <= up_axi_arvalid;
up_rreq_int <= up_axi_arvalid;
up_raddr_int <= up_axi_araddr[(AXI_ADDRESS_WIDTH-1):2];
end
if (up_rack_s == 1'b1) begin
up_rcount <= 5'h00;
end else if (up_rcount[4] == 1'b1) begin
up_rcount <= up_rcount + 1'b1;
end else if (up_rreq_int == 1'b1) begin
up_rcount <= 5'h10;
end
end
end
endmodule