feat: 新增9371地检驱动工程, 9371自收发正常

library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v

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+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved.
+//
+// In this HDL repository, there are many different and unique modules, consisting
+// of various HDL (Verilog or VHDL) components. The individual modules are
+// developed independently, and may be accompanied by separate and unique license
+// terms.
+//
+// The user should read each of these license terms, and understand the
+// freedoms and responsibilities that he or she has by using this source/core.
+//
+// This core is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+// A PARTICULAR PURPOSE.
+//
+// Redistribution and use of source or resulting binaries, with or without modification
+// of this file, are permitted under one of the following two license terms:
+//
+//   1. The GNU General Public License version 2 as published by the
+//      Free Software Foundation, which can be found in the top level directory
+//      of this repository (LICENSE_GPL2), and also online at:
+//      <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
+//
+// OR
+//
+//   2. An ADI specific BSD license, which can be found in the top level directory
+//      of this repository (LICENSE_ADIBSD), and also on-line at:
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
+//      This will allow to generate bit files and not release the source code,
+//      as long as it attaches to an ADI device.
+//
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module spi_engine_interconnect #(
+
+  parameter DATA_WIDTH = 8, // Valid data widths values are 8/16/24/32
+  parameter NUM_OF_SDI = 1
+) (
+  input clk,
+  input resetn,
+
+  output m_cmd_valid,
+  input m_cmd_ready,
+  output [15:0] m_cmd_data,
+
+  output m_sdo_valid,
+  input m_sdo_ready,
+  output [(DATA_WIDTH-1):0] m_sdo_data,
+
+  input m_sdi_valid,
+  output m_sdi_ready,
+  input [(NUM_OF_SDI * DATA_WIDTH-1):0] m_sdi_data,
+
+  input m_sync_valid,
+  output m_sync_ready,
+  input [7:0] m_sync,
+
+  input s0_cmd_valid,
+  output s0_cmd_ready,
+  input [15:0] s0_cmd_data,
+
+  input s0_sdo_valid,
+  output s0_sdo_ready,
+  input [(DATA_WIDTH-1):0] s0_sdo_data,
+
+  output s0_sdi_valid,
+  input s0_sdi_ready,
+  output [(NUM_OF_SDI * DATA_WIDTH-1):0] s0_sdi_data,
+
+  output s0_sync_valid,
+  input s0_sync_ready,
+  output [7:0] s0_sync,
+
+  input s1_cmd_valid,
+  output s1_cmd_ready,
+  input [15:0] s1_cmd_data,
+
+  input s1_sdo_valid,
+  output s1_sdo_ready,
+  input [(DATA_WIDTH-1):0] s1_sdo_data,
+
+  output s1_sdi_valid,
+  input s1_sdi_ready,
+  output [(NUM_OF_SDI * DATA_WIDTH-1):0] s1_sdi_data,
+
+  output s1_sync_valid,
+  input s1_sync_ready,
+  output [7:0] s1_sync
+);
+
+  reg s_active = 1'b0;
+
+  reg idle = 1'b1;
+
+  `define spi_engine_interconnect_mux(s0, s1) (idle == 1'b1 ? 1'b0 : (s_active == 1'b0 ? s0 : s1))
+
+  assign m_cmd_data   = s_active == 1'b0 ? s0_cmd_data : s1_cmd_data;
+  assign m_cmd_valid  = `spi_engine_interconnect_mux(s0_cmd_valid, s1_cmd_valid);
+  assign s0_cmd_ready = `spi_engine_interconnect_mux(m_cmd_ready, 1'b0);
+  assign s1_cmd_ready = `spi_engine_interconnect_mux(1'b0, m_cmd_ready);
+
+  assign m_sdo_data   = s_active == 1'b0 ? s0_sdo_data : s1_sdo_data;
+  assign m_sdo_valid  = `spi_engine_interconnect_mux(s0_sdo_valid, s1_sdo_valid);
+  assign s0_sdo_ready = `spi_engine_interconnect_mux(m_sdo_ready, 1'b0);
+  assign s1_sdo_ready = `spi_engine_interconnect_mux(1'b0, m_sdo_ready);
+
+  assign s0_sdi_data  = m_sdi_data;
+  assign s1_sdi_data  = m_sdi_data;
+  assign m_sdi_ready  = `spi_engine_interconnect_mux(s0_sdi_ready, s1_sdi_ready);
+  assign s0_sdi_valid = `spi_engine_interconnect_mux(m_sdi_valid, 1'b0);
+  assign s1_sdi_valid = `spi_engine_interconnect_mux(1'b0, m_sdi_valid);
+
+  assign s0_sync       = m_sync;
+  assign s1_sync       = m_sync;
+  assign m_sync_ready  = `spi_engine_interconnect_mux(s0_sync_ready, s1_sync_ready);
+  assign s0_sync_valid = `spi_engine_interconnect_mux(m_sync_valid, 1'b0);
+  assign s1_sync_valid = `spi_engine_interconnect_mux(1'b0, m_sync_valid);
+
+  always @(posedge clk) begin
+    if (idle == 1'b1) begin
+      if (s0_cmd_valid)
+        s_active <= 1'b0;
+      else if (s1_cmd_valid)
+        s_active <= 1'b1;
+    end
+  end
+
+  always @(posedge clk) begin
+    if (resetn == 1'b0) begin
+      idle <= 1'b1;
+    end else begin
+      if (m_sync_valid == 1'b1 && m_sync_ready == 1'b1) begin
+        idle <= 1'b1;
+      end else if (s0_cmd_valid == 1'b1 || s1_cmd_valid == 1'b1) begin
+        idle <= 1'b0;
+      end
+    end
+  end
+
+endmodule

library/spi_engine/spi_engine_interconnect/xgui/spi_engine_interconnect_v1_0.tcl

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+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+  ipgui::add_param $IPINST -name "Component_Name"
+  #Adding Page
+  set SPI_Engine_interconnect [ipgui::add_page $IPINST -name "SPI Engine interconnect"]
+  #Adding Group
+  set General_Configuration [ipgui::add_group $IPINST -name "General Configuration" -parent ${SPI_Engine_interconnect}]
+  set DATA_WIDTH [ipgui::add_param $IPINST -name "DATA_WIDTH" -parent ${General_Configuration}]
+  set_property tooltip {[DATA_WIDTH] Define the data interface width} ${DATA_WIDTH}
+  set NUM_OF_SDI [ipgui::add_param $IPINST -name "NUM_OF_SDI" -parent ${General_Configuration}]
+  set_property tooltip {[NUM_OF_SDI] Define the number of MISO lines} ${NUM_OF_SDI}
+
+
+
+}
+
+proc update_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } {
+	# Procedure called to update DATA_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } {
+	# Procedure called to validate DATA_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.NUM_OF_SDI { PARAM_VALUE.NUM_OF_SDI } {
+	# Procedure called to update NUM_OF_SDI when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.NUM_OF_SDI { PARAM_VALUE.NUM_OF_SDI } {
+	# Procedure called to validate NUM_OF_SDI
+	return true
+}
+
+
+proc update_MODELPARAM_VALUE.DATA_WIDTH { MODELPARAM_VALUE.DATA_WIDTH PARAM_VALUE.DATA_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.DATA_WIDTH}] ${MODELPARAM_VALUE.DATA_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.NUM_OF_SDI { MODELPARAM_VALUE.NUM_OF_SDI PARAM_VALUE.NUM_OF_SDI } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.NUM_OF_SDI}] ${MODELPARAM_VALUE.NUM_OF_SDI}
+}
+