feat: 新增9371地检驱动工程, 9371自收发正常
This commit is contained in:
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<?xml version="1.0" encoding="UTF-8"?>
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<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
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<spirit:vendor>analog.com</spirit:vendor>
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||||
<spirit:library>user</spirit:library>
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<spirit:name>spi_engine_offload</spirit:name>
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||||
<spirit:version>1.0</spirit:version>
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||||
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||||
<spirit:busInterface>
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||||
<spirit:name>spi_engine_ctrl</spirit:name>
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<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="spi_engine_ctrl" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="spi_engine_ctrl_rtl" spirit:version="1.0"/>
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||||
<spirit:master/>
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||||
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||||
<spirit:portMap>
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||||
<spirit:logicalPort>
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<spirit:name>cmd_ready</spirit:name>
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||||
</spirit:logicalPort>
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||||
<spirit:physicalPort>
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||||
<spirit:name>cmd_ready</spirit:name>
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||||
</spirit:physicalPort>
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||||
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||||
<spirit:portMap>
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||||
<spirit:logicalPort>
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||||
<spirit:name>cmd_valid</spirit:name>
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||||
</spirit:logicalPort>
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||||
<spirit:physicalPort>
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<spirit:name>cmd_valid</spirit:name>
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</spirit:physicalPort>
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<spirit:portMap>
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||||
<spirit:logicalPort>
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<spirit:name>cmd_data</spirit:name>
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||||
</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>cmd</spirit:name>
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</spirit:physicalPort>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>sdo_ready</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>sdo_data_ready</spirit:name>
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<spirit:portMap>
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||||
<spirit:logicalPort>
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<spirit:name>sdo_valid</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>sdo_data_valid</spirit:name>
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</spirit:physicalPort>
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<spirit:portMap>
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||||
<spirit:logicalPort>
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<spirit:name>sdo_data</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>sdo_data</spirit:name>
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</spirit:physicalPort>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>sdi_ready</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>sdi_data_ready</spirit:name>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>sdi_valid</spirit:name>
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<spirit:physicalPort>
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<spirit:name>sdi_data_valid</spirit:name>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>sdi_data</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>sdi_data</spirit:name>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>sync_ready</spirit:name>
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<spirit:physicalPort>
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<spirit:name>sync_ready</spirit:name>
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<spirit:portMap>
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||||
<spirit:logicalPort>
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<spirit:name>sync_valid</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>sync_valid</spirit:name>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>sync_data</spirit:name>
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<spirit:physicalPort>
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<spirit:name>sync_data</spirit:name>
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||||
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||||
<spirit:name>spi_engine_offload_ctrl</spirit:name>
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<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="spi_engine_offload_ctrl" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="spi_engine_offload_ctrl_rtl" spirit:version="1.0"/>
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<spirit:slave/>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>cmd_wr_en</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>ctrl_cmd_wr_en</spirit:name>
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</spirit:physicalPort>
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||||
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<spirit:portMap>
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||||
<spirit:logicalPort>
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<spirit:name>cmd_wr_data</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>ctrl_cmd_wr_data</spirit:name>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>sdo_wr_en</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>ctrl_sdo_wr_en</spirit:name>
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</spirit:physicalPort>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>sdo_wr_data</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>ctrl_sdo_wr_data</spirit:name>
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</spirit:physicalPort>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>enable</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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||||
<spirit:name>ctrl_enable</spirit:name>
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</spirit:physicalPort>
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||||
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>enabled</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>ctrl_enabled</spirit:name>
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</spirit:physicalPort>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>mem_reset</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>ctrl_mem_reset</spirit:name>
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<spirit:portMap>
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||||
<spirit:logicalPort>
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||||
<spirit:name>sync_ready</spirit:name>
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<spirit:physicalPort>
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<spirit:name>status_sync_ready</spirit:name>
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<spirit:portMap>
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||||
<spirit:logicalPort>
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||||
<spirit:name>sync_valid</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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||||
<spirit:name>status_sync_valid</spirit:name>
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||||
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<spirit:portMap>
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||||
<spirit:logicalPort>
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<spirit:name>sync_data</spirit:name>
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<spirit:physicalPort>
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||||
<spirit:name>status_sync_data</spirit:name>
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||||
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||||
</spirit:busInterface>
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||||
<spirit:busInterface>
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||||
<spirit:name>offload_sdi</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
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||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
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<spirit:master/>
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||||
<spirit:portMaps>
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||||
<spirit:portMap>
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||||
<spirit:logicalPort>
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<spirit:name>TVALID</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>offload_sdi_valid</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>TREADY</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>offload_sdi_ready</spirit:name>
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</spirit:physicalPort>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>TDATA</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>offload_sdi_data</spirit:name>
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</spirit:physicalPort>
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</spirit:portMaps>
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</spirit:busInterface>
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<spirit:busInterface>
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||||
<spirit:name>spi_engine_ctrl_offload_sdi_signal_clock</spirit:name>
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||||
<spirit:displayName>spi_engine_ctrl_offload_sdi_signal_clock</spirit:displayName>
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||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
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||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
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<spirit:slave/>
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||||
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<spirit:portMap>
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||||
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||||
<spirit:name>CLK</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>spi_clk</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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</spirit:portMaps>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>ASSOCIATED_BUSIF</spirit:name>
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||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.SPI_ENGINE_CTRL_OFFLOAD_SDI_SIGNAL_CLOCK.ASSOCIATED_BUSIF">spi_engine_ctrl:offload_sdi</spirit:value>
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||||
</spirit:parameter>
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<spirit:parameter>
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||||
<spirit:name>ASSOCIATED_RESET</spirit:name>
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||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.SPI_ENGINE_CTRL_OFFLOAD_SDI_SIGNAL_CLOCK.ASSOCIATED_RESET">spi_resetn</spirit:value>
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</spirit:parameter>
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||||
</spirit:parameters>
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||||
</spirit:busInterface>
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||||
<spirit:busInterface>
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||||
<spirit:name>spi_engine_ctrl_offload_sdi_signal_reset</spirit:name>
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||||
<spirit:displayName>spi_engine_ctrl_offload_sdi_signal_reset</spirit:displayName>
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||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
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||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
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||||
<spirit:slave/>
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||||
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||||
<spirit:portMap>
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||||
<spirit:logicalPort>
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||||
<spirit:name>RST</spirit:name>
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||||
</spirit:logicalPort>
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||||
<spirit:physicalPort>
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||||
<spirit:name>spi_resetn</spirit:name>
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||||
</spirit:physicalPort>
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||||
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||||
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|
||||
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|
||||
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|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.SPI_ENGINE_CTRL_OFFLOAD_SDI_SIGNAL_RESET.POLARITY">ACTIVE_LOW</spirit:value>
|
||||
</spirit:parameter>
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||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>spi_engine_offload_ctrl_signal_clock</spirit:name>
|
||||
<spirit:displayName>spi_engine_offload_ctrl_signal_clock</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
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||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
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||||
<spirit:slave/>
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<spirit:portMaps>
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||||
<spirit:portMap>
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||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>ctrl_clk</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.SPI_ENGINE_OFFLOAD_CTRL_SIGNAL_CLOCK.ASSOCIATED_BUSIF">spi_engine_offload_ctrl</spirit:value>
|
||||
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|
||||
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||||
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||||
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<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
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||||
<spirit:displayName>Synthesis</spirit:displayName>
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<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
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<spirit:language>Verilog</spirit:language>
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<spirit:modelName>spi_engine_offload</spirit:modelName>
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<spirit:fileSetRef>
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<spirit:localName>xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset</spirit:localName>
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</spirit:fileSetRef>
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<spirit:fileSetRef>
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<spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>viewChecksum</spirit:name>
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<spirit:value>415947b9</spirit:value>
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<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
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||||
<spirit:displayName>Simulation</spirit:displayName>
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<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:language>Verilog</spirit:language>
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||||
<spirit:modelName>spi_engine_offload</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset</spirit:localName>
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</spirit:fileSetRef>
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<spirit:fileSetRef>
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<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>viewChecksum</spirit:name>
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<spirit:value>415947b9</spirit:value>
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<spirit:view>
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<spirit:name>xilinx_xpgui</spirit:name>
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<spirit:displayName>UI Layout</spirit:displayName>
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<spirit:fileSetRef>
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<spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
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<spirit:parameter>
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<spirit:name>viewChecksum</spirit:name>
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<spirit:value>9caa5391</spirit:value>
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||||
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<spirit:name>ctrl_clk</spirit:name>
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||||
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<spirit:direction>in</spirit:direction>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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||||
</spirit:wireTypeDef>
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||||
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||||
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||||
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||||
<spirit:name>ctrl_cmd_wr_en</spirit:name>
|
||||
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<spirit:direction>in</spirit:direction>
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<spirit:typeName>std_logic</spirit:typeName>
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||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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||||
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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<spirit:port>
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||||
<spirit:name>ctrl_cmd_wr_data</spirit:name>
|
||||
<spirit:wire>
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<spirit:direction>in</spirit:direction>
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<spirit:vector>
|
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<spirit:left spirit:format="long">15</spirit:left>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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||||
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<spirit:driver>
|
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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||||
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||||
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|
||||
<spirit:name>ctrl_sdo_wr_en</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>ctrl_sdo_wr_data</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.DATA_WIDTH')) - 1)">7</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>ctrl_enable</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>ctrl_enabled</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>ctrl_mem_reset</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>status_sync_valid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>status_sync_ready</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>status_sync_data</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">7</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>spi_clk</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>spi_resetn</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>trigger</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>cmd_valid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>cmd_ready</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>cmd</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">15</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>sdo_data_valid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>sdo_data_ready</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>sdo_data</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.DATA_WIDTH')) - 1)">7</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>sdi_data_valid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>sdi_data_ready</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>sdi_data</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.NUM_OF_SDI')) * spirit:decode(id('MODELPARAM_VALUE.DATA_WIDTH'))) - 1)">7</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>sync_valid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>sync_ready</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>sync_data</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">7</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>offload_sdi_valid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>offload_sdi_ready</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>offload_sdi_data</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.NUM_OF_SDI')) * spirit:decode(id('MODELPARAM_VALUE.DATA_WIDTH'))) - 1)">7</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
</spirit:ports>
|
||||
<spirit:modelParameters>
|
||||
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
|
||||
<spirit:name>ASYNC_SPI_CLK</spirit:name>
|
||||
<spirit:displayName>Async Spi Clk</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.ASYNC_SPI_CLK">false</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>ASYNC_TRIG</spirit:name>
|
||||
<spirit:displayName>Async Trig</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.ASYNC_TRIG">false</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>CMD_MEM_ADDRESS_WIDTH</spirit:name>
|
||||
<spirit:displayName>Cmd Mem Address Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CMD_MEM_ADDRESS_WIDTH">4</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>SDO_MEM_ADDRESS_WIDTH</spirit:name>
|
||||
<spirit:displayName>Sdo Mem Address Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SDO_MEM_ADDRESS_WIDTH">4</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>DATA_WIDTH</spirit:name>
|
||||
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|
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|
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|
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<spirit:description>spi_engine_offload_v1_0</spirit:description>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASYNC_SPI_CLK</spirit:name>
|
||||
<spirit:displayName>Asynchronous core clock</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.ASYNC_SPI_CLK">false</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASYNC_TRIG</spirit:name>
|
||||
<spirit:displayName>Asynchronous trigger</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.ASYNC_TRIG">false</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CMD_MEM_ADDRESS_WIDTH</spirit:name>
|
||||
<spirit:displayName>Command FIFO address width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CMD_MEM_ADDRESS_WIDTH" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>SDO_MEM_ADDRESS_WIDTH</spirit:name>
|
||||
<spirit:displayName>MOSI FIFO address width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.SDO_MEM_ADDRESS_WIDTH" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>DATA_WIDTH</spirit:name>
|
||||
<spirit:displayName>Shift register's data width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DATA_WIDTH" spirit:minimum="8" spirit:maximum="256" spirit:rangeType="long">8</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>NUM_OF_SDI</spirit:name>
|
||||
<spirit:displayName>Number of MISO lines</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.NUM_OF_SDI" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
|
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</spirit:parameter>
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<spirit:parameter>
|
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<spirit:name>Component_Name</spirit:name>
|
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<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">spi_engine_offload_v1_0</spirit:value>
|
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</spirit:parameter>
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</xilinx:supportedFamilies>
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<xilinx:taxonomies>
|
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<xilinx:taxonomy>/Analog_Devices</xilinx:taxonomy>
|
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</xilinx:taxonomies>
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<xilinx:displayName>spi_engine_offload_v1_0</xilinx:displayName>
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<xilinx:autoFamilySupportLevel>level_2</xilinx:autoFamilySupportLevel>
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<xilinx:definitionSource>package_project</xilinx:definitionSource>
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<xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
|
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<xilinx:vendorURL>https://wiki.analog.com/resources/fpga/peripherals/spi_engine/offload</xilinx:vendorURL>
|
||||
<xilinx:coreRevision>1</xilinx:coreRevision>
|
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<xilinx:coreCreationDateTime>2025-04-30T13:54:08Z</xilinx:coreCreationDateTime>
|
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</xilinx:coreExtensions>
|
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<xilinx:packagingInfo>
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<xilinx:xilinxVersion>2024.1.2</xilinx:xilinxVersion>
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<xilinx:checksum xilinx:scope="ports" xilinx:value="2756ddd5"/>
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</spirit:component>
|
||||
@@ -0,0 +1,317 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2015-2024 Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module spi_engine_offload #(
|
||||
|
||||
parameter ASYNC_SPI_CLK = 0,
|
||||
parameter ASYNC_TRIG = 0,
|
||||
parameter CMD_MEM_ADDRESS_WIDTH = 4,
|
||||
parameter SDO_MEM_ADDRESS_WIDTH = 4,
|
||||
parameter DATA_WIDTH = 8, // Valid data widths values are 8/16/24/32
|
||||
parameter NUM_OF_SDI = 1
|
||||
) (
|
||||
input ctrl_clk,
|
||||
|
||||
input ctrl_cmd_wr_en,
|
||||
input [15:0] ctrl_cmd_wr_data,
|
||||
|
||||
input ctrl_sdo_wr_en,
|
||||
input [(DATA_WIDTH-1):0] ctrl_sdo_wr_data,
|
||||
|
||||
input ctrl_enable,
|
||||
output ctrl_enabled,
|
||||
input ctrl_mem_reset,
|
||||
|
||||
output status_sync_valid,
|
||||
input status_sync_ready,
|
||||
output [7:0] status_sync_data,
|
||||
|
||||
input spi_clk,
|
||||
input spi_resetn,
|
||||
|
||||
input trigger,
|
||||
|
||||
output cmd_valid,
|
||||
input cmd_ready,
|
||||
output [15:0] cmd,
|
||||
|
||||
output sdo_data_valid,
|
||||
input sdo_data_ready,
|
||||
output [(DATA_WIDTH-1):0] sdo_data,
|
||||
|
||||
input sdi_data_valid,
|
||||
output sdi_data_ready,
|
||||
input [(NUM_OF_SDI * DATA_WIDTH-1):0] sdi_data,
|
||||
|
||||
input sync_valid,
|
||||
output sync_ready,
|
||||
input [7:0] sync_data,
|
||||
|
||||
output offload_sdi_valid,
|
||||
input offload_sdi_ready,
|
||||
output [(NUM_OF_SDI * DATA_WIDTH-1):0] offload_sdi_data
|
||||
);
|
||||
|
||||
reg spi_active = 1'b0;
|
||||
|
||||
reg [CMD_MEM_ADDRESS_WIDTH-1:0] ctrl_cmd_wr_addr = 'h00;
|
||||
reg [CMD_MEM_ADDRESS_WIDTH-1:0] spi_cmd_rd_addr = 'h00;
|
||||
reg [SDO_MEM_ADDRESS_WIDTH-1:0] ctrl_sdo_wr_addr = 'h00;
|
||||
reg [SDO_MEM_ADDRESS_WIDTH-1:0] spi_sdo_rd_addr = 'h00;
|
||||
|
||||
reg [15:0] cmd_mem[0:2**CMD_MEM_ADDRESS_WIDTH-1];
|
||||
reg [(DATA_WIDTH-1):0] sdo_mem[0:2**SDO_MEM_ADDRESS_WIDTH-1];
|
||||
|
||||
reg trigger_last_reg;
|
||||
|
||||
wire [15:0] cmd_int_s;
|
||||
wire [CMD_MEM_ADDRESS_WIDTH-1:0] spi_cmd_rd_addr_next;
|
||||
wire spi_enable;
|
||||
wire trigger_posedge;
|
||||
|
||||
assign cmd_valid = spi_active;
|
||||
assign sdo_data_valid = spi_active;
|
||||
|
||||
assign offload_sdi_valid = sdi_data_valid;
|
||||
|
||||
// we don't want to block the SDI interface after disabling the module
|
||||
// so just assert the SDI_READY if the sink module (DMA) is disabled
|
||||
assign sdi_data_ready = (spi_enable) ? offload_sdi_ready : 1'b1;
|
||||
|
||||
assign offload_sdi_data = sdi_data;
|
||||
|
||||
assign cmd_int_s = cmd_mem[spi_cmd_rd_addr];
|
||||
assign sdo_data = sdo_mem[spi_sdo_rd_addr];
|
||||
|
||||
/* SYNC ID counter. The offload module increments the sync_id on each
|
||||
* transaction. The initial value of the sync_id is the value of the last
|
||||
* sync_id command loaded into the command buffer.
|
||||
*/
|
||||
|
||||
reg [ 7:0] ctrl_sync_id_init = 8'b0;
|
||||
reg ctrl_sync_id_load = 1'b0;
|
||||
reg [ 7:0] spi_sync_id_counter = 8'b0;
|
||||
|
||||
wire [ 7:0] spi_sync_id_init_s;
|
||||
|
||||
always @(posedge ctrl_clk) begin
|
||||
if (ctrl_mem_reset) begin
|
||||
ctrl_sync_id_init <= 8'b0;
|
||||
ctrl_sync_id_load <= 1'b0;
|
||||
end else begin
|
||||
if (ctrl_cmd_wr_en && (ctrl_cmd_wr_data[15:8] == 8'h30)) begin
|
||||
ctrl_sync_id_init <= ctrl_cmd_wr_data;
|
||||
ctrl_sync_id_load <= 1'b1;
|
||||
end else begin
|
||||
ctrl_sync_id_load <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
wire spi_sync_id_load_s;
|
||||
|
||||
sync_event #(
|
||||
.NUM_OF_EVENTS(1),
|
||||
.ASYNC_CLK(1)
|
||||
) i_sync_sync_id_load (
|
||||
.in_clk (ctrl_clk),
|
||||
.in_event(ctrl_sync_id_load),
|
||||
.out_clk(spi_clk),
|
||||
.out_event(spi_sync_id_load_s));
|
||||
|
||||
sync_bits #(
|
||||
.NUM_OF_BITS(8),
|
||||
.ASYNC_CLK(1)
|
||||
) i_sync_sync_id (
|
||||
.in_bits(ctrl_sync_id_init),
|
||||
.out_clk(spi_clk),
|
||||
.out_resetn(1'b1),
|
||||
.out_bits(spi_sync_id_init_s));
|
||||
|
||||
always @(posedge spi_clk) begin
|
||||
if (!spi_resetn) begin
|
||||
spi_sync_id_counter <= 8'b0;
|
||||
end else begin
|
||||
if (spi_sync_id_load_s) begin
|
||||
spi_sync_id_counter <= spi_sync_id_init_s;
|
||||
end else if(cmd_valid && cmd_ready && (cmd[15:8] == 8'h30)) begin
|
||||
spi_sync_id_counter <= spi_sync_id_counter + 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign cmd = (cmd_int_s[15:8] == 8'h30) ? {cmd_int_s[15:8], spi_sync_id_counter} : cmd_int_s;
|
||||
|
||||
/*
|
||||
* Forwarded SYNC interface, this can be used to monitor the state of the
|
||||
* offload command sequence through SPI Engine regmap
|
||||
*/
|
||||
|
||||
assign status_sync_data = sync_data;
|
||||
assign status_sync_valid = sync_valid;
|
||||
assign sync_ready = status_sync_ready;
|
||||
|
||||
generate if (ASYNC_SPI_CLK) begin
|
||||
|
||||
/*
|
||||
* The synchronization circuit takes care that there are no glitches on the
|
||||
* ctrl_enabled signal. ctrl_do_enable is asserted whenever ctrl_enable is
|
||||
* asserted, but only deasserted once the signal has been synchronized back from
|
||||
* the SPI domain. This makes sure that we can't end up in a state where the
|
||||
* enable signal in the SPI domain is asserted, but neither enable nor enabled
|
||||
* is asserted in the control domain.
|
||||
*/
|
||||
|
||||
reg ctrl_do_enable = 1'b0;
|
||||
wire ctrl_is_enabled;
|
||||
reg spi_enabled = 1'b0;
|
||||
|
||||
always @(posedge ctrl_clk) begin
|
||||
if (ctrl_enable) begin
|
||||
ctrl_do_enable <= 1'b1;
|
||||
end else if (ctrl_is_enabled) begin
|
||||
ctrl_do_enable <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
assign ctrl_enabled = ctrl_is_enabled | ctrl_do_enable;
|
||||
|
||||
always @(posedge spi_clk) begin
|
||||
spi_enabled <= spi_enable | spi_active;
|
||||
end
|
||||
|
||||
sync_bits #(
|
||||
.NUM_OF_BITS(1),
|
||||
.ASYNC_CLK(1)
|
||||
) i_sync_enable (
|
||||
.in_bits(ctrl_do_enable),
|
||||
.out_clk(spi_clk),
|
||||
.out_resetn(1'b1),
|
||||
.out_bits(spi_enable));
|
||||
|
||||
sync_bits #(
|
||||
.NUM_OF_BITS(1),
|
||||
.ASYNC_CLK(1)
|
||||
) i_sync_enabled (
|
||||
.in_bits(spi_enabled),
|
||||
.out_clk(ctrl_clk),
|
||||
.out_resetn(1'b1),
|
||||
.out_bits(ctrl_is_enabled));
|
||||
|
||||
end else begin
|
||||
assign spi_enable = ctrl_enable;
|
||||
assign ctrl_enabled = spi_enable | spi_active;
|
||||
end endgenerate
|
||||
|
||||
assign spi_cmd_rd_addr_next = spi_cmd_rd_addr + 1;
|
||||
|
||||
wire trigger_s;
|
||||
sync_bits #(
|
||||
.NUM_OF_BITS(1),
|
||||
.ASYNC_CLK(ASYNC_TRIG)
|
||||
) i_sync_trigger (
|
||||
.in_bits(trigger),
|
||||
.out_clk(spi_clk),
|
||||
.out_resetn(1'b1),
|
||||
.out_bits(trigger_s));
|
||||
|
||||
always @(posedge spi_clk) begin
|
||||
if (!spi_resetn) begin
|
||||
trigger_last_reg <= 1'b0;
|
||||
end else begin
|
||||
trigger_last_reg <= trigger_s;
|
||||
end
|
||||
end
|
||||
|
||||
assign trigger_posedge = trigger_s && !trigger_last_reg;
|
||||
|
||||
always @(posedge spi_clk) begin
|
||||
if (!spi_resetn) begin
|
||||
spi_active <= 1'b0;
|
||||
end else begin
|
||||
if (!spi_active) begin
|
||||
// start offload when we have a valid trigger, offload is enabled and
|
||||
// the DMA is enabled
|
||||
if (trigger_posedge && spi_enable && offload_sdi_ready)
|
||||
spi_active <= 1'b1;
|
||||
end else if (cmd_ready && (spi_cmd_rd_addr_next == ctrl_cmd_wr_addr)) begin
|
||||
spi_active <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge spi_clk) begin
|
||||
if (!cmd_valid) begin
|
||||
spi_cmd_rd_addr <= 'h00;
|
||||
end else if (cmd_ready) begin
|
||||
spi_cmd_rd_addr <= spi_cmd_rd_addr_next;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge spi_clk) begin
|
||||
if (!spi_active) begin
|
||||
spi_sdo_rd_addr <= 'h00;
|
||||
end else if (sdo_data_ready) begin
|
||||
spi_sdo_rd_addr <= spi_sdo_rd_addr + 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge ctrl_clk) begin
|
||||
if (ctrl_mem_reset)
|
||||
ctrl_cmd_wr_addr <= 'h00;
|
||||
else if (ctrl_cmd_wr_en)
|
||||
ctrl_cmd_wr_addr <= ctrl_cmd_wr_addr + 1'b1;
|
||||
end
|
||||
|
||||
always @(posedge ctrl_clk) begin
|
||||
if (ctrl_cmd_wr_en)
|
||||
cmd_mem[ctrl_cmd_wr_addr] <= ctrl_cmd_wr_data;
|
||||
end
|
||||
|
||||
always @(posedge ctrl_clk) begin
|
||||
if (ctrl_mem_reset)
|
||||
ctrl_sdo_wr_addr <= 'h00;
|
||||
else if (ctrl_sdo_wr_en)
|
||||
ctrl_sdo_wr_addr <= ctrl_sdo_wr_addr + 1'b1;
|
||||
end
|
||||
|
||||
always @(posedge ctrl_clk) begin
|
||||
if (ctrl_sdo_wr_en)
|
||||
sdo_mem[ctrl_sdo_wr_addr] <= ctrl_sdo_wr_data;
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,17 @@
|
||||
###############################################################################
|
||||
## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIBSD
|
||||
###############################################################################
|
||||
|
||||
<: set ComponentName [getComponentNameString] :>
|
||||
<: setOutputDirectory "./" :>
|
||||
<: setFileName [ttcl_add $ComponentName "_constr"] :>
|
||||
<: setFileExtension ".xdc" :>
|
||||
<: setFileProcessingOrder late :>
|
||||
|
||||
<: set async_trigger [getBooleanValue "ASYNC_TRIG"] :>
|
||||
<: if { $async_trigger } { :>
|
||||
set_false_path -quiet \
|
||||
-to [get_cells -quiet -hierarchical -filter {NAME =~ *i_sync_trigger/cdc_sync_stage1_reg* && IS_SEQUENTIAL}]
|
||||
|
||||
<: } :>
|
||||
@@ -0,0 +1,112 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set SPI_Engine_RX_offload [ipgui::add_page $IPINST -name "SPI Engine RX offload"]
|
||||
#Adding Group
|
||||
set General_Configuration [ipgui::add_group $IPINST -name "General Configuration" -parent ${SPI_Engine_RX_offload}]
|
||||
set DATA_WIDTH [ipgui::add_param $IPINST -name "DATA_WIDTH" -parent ${General_Configuration}]
|
||||
set_property tooltip {[DATA_WIDTH] Define the data interface width} ${DATA_WIDTH}
|
||||
set NUM_OF_SDI [ipgui::add_param $IPINST -name "NUM_OF_SDI" -parent ${General_Configuration}]
|
||||
set_property tooltip {[NUM_OF_SDI] Define the number of MISO lines} ${NUM_OF_SDI}
|
||||
set ASYNC_SPI_CLK [ipgui::add_param $IPINST -name "ASYNC_SPI_CLK" -parent ${General_Configuration}]
|
||||
set_property tooltip {[ASYNC_SPI_CLK] Define the relationship between the core clock and the memory mapped interface clock} ${ASYNC_SPI_CLK}
|
||||
set ASYNC_TRIG [ipgui::add_param $IPINST -name "ASYNC_TRIG" -parent ${General_Configuration}]
|
||||
set_property tooltip {[ASYNC_TRIG] Set if the external trigger is asynchronous to the core clk} ${ASYNC_TRIG}
|
||||
|
||||
#Adding Group
|
||||
set Command_stream_FIFO_configuration [ipgui::add_group $IPINST -name "Command stream FIFO configuration" -parent ${SPI_Engine_RX_offload}]
|
||||
set CMD_MEM_ADDRESS_WIDTH [ipgui::add_param $IPINST -name "CMD_MEM_ADDRESS_WIDTH" -parent ${Command_stream_FIFO_configuration}]
|
||||
set_property tooltip {[CMD_MEM_ADDRESS_WIDTH] Define the depth of the FIFO} ${CMD_MEM_ADDRESS_WIDTH}
|
||||
set SDO_MEM_ADDRESS_WIDTH [ipgui::add_param $IPINST -name "SDO_MEM_ADDRESS_WIDTH" -parent ${Command_stream_FIFO_configuration}]
|
||||
set_property tooltip {[SDO_MEM_ADDRESS_WIDTH] Define the depth of the FIFO} ${SDO_MEM_ADDRESS_WIDTH}
|
||||
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.ASYNC_SPI_CLK { PARAM_VALUE.ASYNC_SPI_CLK } {
|
||||
# Procedure called to update ASYNC_SPI_CLK when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.ASYNC_SPI_CLK { PARAM_VALUE.ASYNC_SPI_CLK } {
|
||||
# Procedure called to validate ASYNC_SPI_CLK
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.ASYNC_TRIG { PARAM_VALUE.ASYNC_TRIG } {
|
||||
# Procedure called to update ASYNC_TRIG when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.ASYNC_TRIG { PARAM_VALUE.ASYNC_TRIG } {
|
||||
# Procedure called to validate ASYNC_TRIG
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.CMD_MEM_ADDRESS_WIDTH { PARAM_VALUE.CMD_MEM_ADDRESS_WIDTH } {
|
||||
# Procedure called to update CMD_MEM_ADDRESS_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.CMD_MEM_ADDRESS_WIDTH { PARAM_VALUE.CMD_MEM_ADDRESS_WIDTH } {
|
||||
# Procedure called to validate CMD_MEM_ADDRESS_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } {
|
||||
# Procedure called to update DATA_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } {
|
||||
# Procedure called to validate DATA_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.NUM_OF_SDI { PARAM_VALUE.NUM_OF_SDI } {
|
||||
# Procedure called to update NUM_OF_SDI when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.NUM_OF_SDI { PARAM_VALUE.NUM_OF_SDI } {
|
||||
# Procedure called to validate NUM_OF_SDI
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.SDO_MEM_ADDRESS_WIDTH { PARAM_VALUE.SDO_MEM_ADDRESS_WIDTH } {
|
||||
# Procedure called to update SDO_MEM_ADDRESS_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.SDO_MEM_ADDRESS_WIDTH { PARAM_VALUE.SDO_MEM_ADDRESS_WIDTH } {
|
||||
# Procedure called to validate SDO_MEM_ADDRESS_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.ASYNC_SPI_CLK { MODELPARAM_VALUE.ASYNC_SPI_CLK PARAM_VALUE.ASYNC_SPI_CLK } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.ASYNC_SPI_CLK}] ${MODELPARAM_VALUE.ASYNC_SPI_CLK}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.ASYNC_TRIG { MODELPARAM_VALUE.ASYNC_TRIG PARAM_VALUE.ASYNC_TRIG } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.ASYNC_TRIG}] ${MODELPARAM_VALUE.ASYNC_TRIG}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.CMD_MEM_ADDRESS_WIDTH { MODELPARAM_VALUE.CMD_MEM_ADDRESS_WIDTH PARAM_VALUE.CMD_MEM_ADDRESS_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.CMD_MEM_ADDRESS_WIDTH}] ${MODELPARAM_VALUE.CMD_MEM_ADDRESS_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.SDO_MEM_ADDRESS_WIDTH { MODELPARAM_VALUE.SDO_MEM_ADDRESS_WIDTH PARAM_VALUE.SDO_MEM_ADDRESS_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.SDO_MEM_ADDRESS_WIDTH}] ${MODELPARAM_VALUE.SDO_MEM_ADDRESS_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DATA_WIDTH { MODELPARAM_VALUE.DATA_WIDTH PARAM_VALUE.DATA_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DATA_WIDTH}] ${MODELPARAM_VALUE.DATA_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.NUM_OF_SDI { MODELPARAM_VALUE.NUM_OF_SDI PARAM_VALUE.NUM_OF_SDI } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.NUM_OF_SDI}] ${MODELPARAM_VALUE.NUM_OF_SDI}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user