166 lines
8.3 KiB
Tcl
166 lines
8.3 KiB
Tcl
proc getPresetInfo {} {
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return [dict create name {dj_f1_preset} description {dj_f1_preset} vlnv xilinx.com:ip:processing_system7:5.5 display_name {dj_f1_preset} ]
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}
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proc validate_preset {IPINST} { return true }
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proc apply_preset {IPINST} {
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return [dict create \
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CONFIG.PCW_DDR_RAM_HIGHADDR {0x1FFFFFFF} \
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CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT {3} \
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CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT {15} \
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CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT {10} \
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CONFIG.PCW_UIPARAM_DDR_CL {7} \
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CONFIG.PCW_UIPARAM_DDR_CWL {6} \
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CONFIG.PCW_UIPARAM_DDR_T_RCD {7} \
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CONFIG.PCW_UIPARAM_DDR_T_RP {7} \
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CONFIG.PCW_UIPARAM_DDR_T_RC {49.5} \
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CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN {36.0} \
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CONFIG.PCW_UIPARAM_DDR_T_FAW {30.0} \
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CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ {200} \
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CONFIG.PCW_UART_PERIPHERAL_FREQMHZ {100} \
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CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {25} \
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CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100} \
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CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {666.666687} \
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CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {533.333374} \
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CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.158730} \
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CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {200.000000} \
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CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \
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CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {10.000000} \
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CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} \
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CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {10.000000} \
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CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {100.000000} \
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CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {10.000000} \
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CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000} \
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CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {111.111115} \
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CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000} \
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CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \
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CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {100.000000} \
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CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {10.000000} \
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CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {10.000000} \
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CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {10.000000} \
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CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {111.111115} \
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CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {111.111115} \
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CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {111.111115} \
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CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {111.111115} \
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CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {111.111115} \
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CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {111.111115} \
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CONFIG.PCW_CLK0_FREQ {100000000} \
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CONFIG.PCW_CLK1_FREQ {10000000} \
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CONFIG.PCW_CLK2_FREQ {10000000} \
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CONFIG.PCW_CLK3_FREQ {10000000} \
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CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {2} \
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CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0 {2} \
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CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0 {1} \
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CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0 {9} \
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CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0 {1} \
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CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {18} \
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CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0 {1} \
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CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {1} \
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CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {1} \
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CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {6} \
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CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {1} \
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CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {1} \
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CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {1} \
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CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {3} \
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CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {1} \
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CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {1} \
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CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {1} \
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CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {1} \
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CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0 {1} \
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CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1 {1} \
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CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1 {1} \
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CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0 {1} \
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CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {15} \
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CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {7} \
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CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {9} \
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CONFIG.PCW_ARMPLL_CTRL_FBDIV {40} \
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CONFIG.PCW_IOPLL_CTRL_FBDIV {54} \
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CONFIG.PCW_DDRPLL_CTRL_FBDIV {32} \
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CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1333.333} \
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CONFIG.PCW_IO_IO_PLL_FREQMHZ {1800.000} \
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CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1066.667} \
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CONFIG.PCW_UART_PERIPHERAL_VALID {1} \
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CONFIG.PCW_EN_EMIO_GPIO {1} \
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CONFIG.PCW_EN_EMIO_PJTAG {0} \
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CONFIG.PCW_USE_FABRIC_INTERRUPT {1} \
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CONFIG.PCW_GPIO_EMIO_GPIO_WIDTH {16} \
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CONFIG.PCW_EN_QSPI {1} \
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CONFIG.PCW_EN_PJTAG {0} \
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CONFIG.PCW_EN_UART1 {1} \
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CONFIG.PCW_IRQ_F2P_INTR {1} \
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CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 1.8V} \
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CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} \
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CONFIG.PCW_UIPARAM_DDR_ECC {Disabled} \
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CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {16 Bit} \
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CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41J256M8 HX-15E} \
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CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {8 Bits} \
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CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {2048 MBits} \
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CONFIG.PCW_UIPARAM_DDR_SPEED_BIN {DDR3_1066F} \
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CONFIG.PCW_NAND_PERIPHERAL_ENABLE {0} \
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CONFIG.PCW_NAND_GRP_D8_ENABLE {0} \
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CONFIG.PCW_NOR_PERIPHERAL_ENABLE {0} \
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CONFIG.PCW_NOR_GRP_A25_ENABLE {0} \
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CONFIG.PCW_NOR_GRP_CS0_ENABLE {0} \
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CONFIG.PCW_NOR_GRP_SRAM_CS0_ENABLE {0} \
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CONFIG.PCW_NOR_GRP_CS1_ENABLE {0} \
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CONFIG.PCW_NOR_GRP_SRAM_CS1_ENABLE {0} \
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CONFIG.PCW_NOR_GRP_SRAM_INT_ENABLE {0} \
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CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1} \
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CONFIG.PCW_QSPI_QSPI_IO {MIO 1 .. 6} \
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CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1} \
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CONFIG.PCW_QSPI_GRP_SINGLE_SS_IO {MIO 1 .. 6} \
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CONFIG.PCW_QSPI_GRP_SS1_ENABLE {0} \
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CONFIG.PCW_SINGLE_QSPI_DATA_MODE {x4} \
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CONFIG.PCW_QSPI_GRP_IO1_ENABLE {0} \
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CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE {0} \
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CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1} \
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CONFIG.PCW_UART1_UART1_IO {MIO 48 .. 49} \
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CONFIG.PCW_UART1_GRP_FULL_ENABLE {0} \
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CONFIG.PCW_PJTAG_PERIPHERAL_ENABLE {0} \
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CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1} \
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CONFIG.PCW_GPIO_EMIO_GPIO_IO {16} \
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CONFIG.PCW_MIO_1_PULLUP {enabled} \
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CONFIG.PCW_MIO_1_IOTYPE {LVCMOS 1.8V} \
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CONFIG.PCW_MIO_1_DIRECTION {out} \
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CONFIG.PCW_MIO_1_SLEW {slow} \
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CONFIG.PCW_MIO_2_PULLUP {disabled} \
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CONFIG.PCW_MIO_2_IOTYPE {LVCMOS 1.8V} \
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CONFIG.PCW_MIO_2_DIRECTION {inout} \
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CONFIG.PCW_MIO_2_SLEW {slow} \
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CONFIG.PCW_MIO_3_PULLUP {disabled} \
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CONFIG.PCW_MIO_3_IOTYPE {LVCMOS 1.8V} \
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CONFIG.PCW_MIO_3_DIRECTION {inout} \
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CONFIG.PCW_MIO_3_SLEW {slow} \
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CONFIG.PCW_MIO_4_PULLUP {disabled} \
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CONFIG.PCW_MIO_4_IOTYPE {LVCMOS 1.8V} \
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CONFIG.PCW_MIO_4_DIRECTION {inout} \
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CONFIG.PCW_MIO_4_SLEW {slow} \
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CONFIG.PCW_MIO_5_PULLUP {disabled} \
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CONFIG.PCW_MIO_5_IOTYPE {LVCMOS 1.8V} \
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CONFIG.PCW_MIO_5_DIRECTION {inout} \
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CONFIG.PCW_MIO_5_SLEW {slow} \
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CONFIG.PCW_MIO_6_PULLUP {disabled} \
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CONFIG.PCW_MIO_6_IOTYPE {LVCMOS 1.8V} \
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CONFIG.PCW_MIO_6_DIRECTION {out} \
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CONFIG.PCW_MIO_6_SLEW {slow} \
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CONFIG.PCW_MIO_48_PULLUP {enabled} \
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CONFIG.PCW_MIO_48_IOTYPE {LVCMOS 1.8V} \
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CONFIG.PCW_MIO_48_DIRECTION {out} \
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CONFIG.PCW_MIO_48_SLEW {slow} \
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CONFIG.PCW_MIO_49_PULLUP {enabled} \
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CONFIG.PCW_MIO_49_IOTYPE {LVCMOS 1.8V} \
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CONFIG.PCW_MIO_49_DIRECTION {in} \
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CONFIG.PCW_MIO_49_SLEW {slow} \
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CONFIG.PCW_MIO_TREE_PERIPHERALS {unassigned#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#UART 1#UART 1#unassigned#unassigned#unassigned#unassigned} \
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CONFIG.PCW_MIO_TREE_SIGNALS {unassigned#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#tx#rx#unassigned#unassigned#unassigned#unassigned} \
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CONFIG.PCW_FPGA_FCLK0_ENABLE {1} \
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CONFIG.PCW_FPGA_FCLK1_ENABLE {0} \
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CONFIG.PCW_FPGA_FCLK2_ENABLE {0} \
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CONFIG.PCW_FPGA_FCLK3_ENABLE {0} \
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]
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}
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