From b56c7ad3be9679b31a0ea66c5bcc72dcfe573e6d Mon Sep 17 00:00:00 2001 From: Josh Gao Date: Thu, 14 Nov 2024 21:06:09 +0800 Subject: [PATCH] =?UTF-8?q?feat:=20=E5=A2=9E=E5=8A=A0=E8=B7=A8=E5=9F=9F?= =?UTF-8?q?=E7=94=B5=E6=BA=90=E6=8E=A5=E5=8F=A3=E6=9D=BF=E5=B7=A5=E7=A8=8B?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- dx_pwr_basic/.gitignore | 119 + .../dx_pwr_basic.runs/impl_1/debug_nets.ltx | 148 + .../dx_pwr_basic.runs/impl_1/system_top.bit | 3 + .../dx_pwr_basic.runs/impl_1/system_top.ltx | 148 + .../new/dx_z7100_pwr_inter_physical.xdc | 179 + .../system_bd_processing_system7_0_0.xci | 1259 ++++ .../sources_1/bd/system_bd/system_bd.bd | 390 + .../sources_1/bd/system_bd/system_bd.bda | 203 + .../sources_1/bd/system_bd/ui/bd_c6d0cb12.ui | 20 + .../sources_1/ip/ila_cnt/ila_cnt.xci | 6299 +++++++++++++++++ .../ip/lvds_clk_gen/lvds_clk_gen.xci | 657 ++ .../sources_1/new/system_top.v | 243 + dx_pwr_basic/dx_pwr_basic.xpr | 356 + dx_pwr_basic/system_top.xsa | 3 + .../vitis_classic_autobuild/.gitignore | 35 + dx_pwr_basic/vitis_classic_autobuild/Makefile | 8 + .../vitis_classic_autobuild/autobuild.bat | 32 + .../vitis_classic_autobuild/config.json | 6 + dx_pwr_preset.tcl | 178 + 19 files changed, 10286 insertions(+) create mode 100644 dx_pwr_basic/.gitignore create mode 100644 dx_pwr_basic/dx_pwr_basic.runs/impl_1/debug_nets.ltx create mode 100644 dx_pwr_basic/dx_pwr_basic.runs/impl_1/system_top.bit create mode 100644 dx_pwr_basic/dx_pwr_basic.runs/impl_1/system_top.ltx create mode 100644 dx_pwr_basic/dx_pwr_basic.srcs/constrs_1/new/dx_z7100_pwr_inter_physical.xdc create mode 100644 dx_pwr_basic/dx_pwr_basic.srcs/sources_1/bd/system_bd/ip/system_bd_processing_system7_0_0/system_bd_processing_system7_0_0.xci create mode 100644 dx_pwr_basic/dx_pwr_basic.srcs/sources_1/bd/system_bd/system_bd.bd create mode 100644 dx_pwr_basic/dx_pwr_basic.srcs/sources_1/bd/system_bd/system_bd.bda create mode 100644 dx_pwr_basic/dx_pwr_basic.srcs/sources_1/bd/system_bd/ui/bd_c6d0cb12.ui create mode 100644 dx_pwr_basic/dx_pwr_basic.srcs/sources_1/ip/ila_cnt/ila_cnt.xci create mode 100644 dx_pwr_basic/dx_pwr_basic.srcs/sources_1/ip/lvds_clk_gen/lvds_clk_gen.xci create mode 100644 dx_pwr_basic/dx_pwr_basic.srcs/sources_1/new/system_top.v create mode 100644 dx_pwr_basic/dx_pwr_basic.xpr create mode 100644 dx_pwr_basic/system_top.xsa create mode 100644 dx_pwr_basic/vitis_classic_autobuild/.gitignore create mode 100644 dx_pwr_basic/vitis_classic_autobuild/Makefile create mode 100644 dx_pwr_basic/vitis_classic_autobuild/autobuild.bat create mode 100644 dx_pwr_basic/vitis_classic_autobuild/config.json create mode 100644 dx_pwr_preset.tcl diff --git a/dx_pwr_basic/.gitignore b/dx_pwr_basic/.gitignore new file mode 100644 index 0000000..15117b5 --- /dev/null +++ b/dx_pwr_basic/.gitignore @@ -0,0 +1,119 @@ +################################################################################ +############################### Project Specific ############################### +################################################################################ +# everything +* + +# git related +!/.gitignore +!/.gitattributes + +# project documents +!/*.md +!/*.txt + +################################################################################ +############################### Vivado Specific ################################ +################################################################################ + +# xpr: needed for recreating design +!/*.xpr + +# source: include everything +!/*.srcs/ +!/*.srcs/**/* + +# runs: exclude everything but design run results +!/*.runs/ +!/*.runs/impl_*/ +!/*.runs/impl_*/*.bit +!/*.runs/impl_*/*.ltx + +# xsa (Xilinx support archive): include for ps +!/*.xsa + +################################################################################ +################################ Vitis Specific ################################ +################################################################################ + +# include sdk directory and everything in it +!/vitis*/ +!/vitis*/** +/vitis*/**.log +/vitis*/.analytics + +# exclude some obscure hidden SDK folders +/vitis*/.metadata/ +/vitis*/.sdk/ +/vitis*/RemoteSystemsTempFiles/ +/vitis*/webtalk/ + +# hw_platform: exclude the entire hw_platform folder, as everything can be +# generated from the .hdf file. Make sure to include the bitstream in the .hdf +# file when exporting from Vivado! +/vitis*/*_hw_platform_*/ + +# BSP: only keep `.cproject`, `.project`, `.sdkproject`, `.system.mss` and +# Makefile, ps lib files are regenerated automatically +/vitis*/*_bsp/* +!/vitis*/*_bsp/*.cproject +!/vitis*/*_bsp/*.project +!/vitis*/*_bsp/*.sdkproject +!/vitis*/*_bsp/system.mss +!/vitis*/*_bsp/Makefile + +# Application: ignored file patterns, exclude Debug & Release folders +/vitis*/**/*.o +/vitis*/**/*.d +/vitis*/**/*.a +/vitis*/*/Debug/ +/vitis*/*/Release/ + +################################################################################ +############################ Vivado & Vitis Common ############################# +################################################################################ + +# file patterns that should always be ignored (journal files, log files, dump +# files that are created upon Vivado/SDK errors) +*.jou +*.log +*.backup.jou +*.backup.log +*.upgrade_log +*.dmp +*.debug +vivado_pid* + +# vivado workspace files +xsim.dir/ +xvlog.pb + +# Xilinx tools generated files +.metadata/ +.settings/ +.wsdata/ +.Xil/ +logs/ +Packages/ +*.log* + +# System generated files +# -- macOS +.DS_Store +.AppleDouble +.LSOverride +._* + +# -- Windows +Thumbs.db +ehthumbs.db +Desktop.ini + +# -- Linux +*~ + +# IDEs and editors' files +*.idea +*.vscode +*.sublime-workspace +*.sublime-project diff --git a/dx_pwr_basic/dx_pwr_basic.runs/impl_1/debug_nets.ltx b/dx_pwr_basic/dx_pwr_basic.runs/impl_1/debug_nets.ltx new file mode 100644 index 0000000..cea9550 --- /dev/null +++ b/dx_pwr_basic/dx_pwr_basic.runs/impl_1/debug_nets.ltx @@ -0,0 +1,148 @@ +{ + "ltx_root": { + "version": 4, + "minor": 0, + "ltx_data": [ + { + "name": "EDA_PROBESET", + "active": true, + "debug_cores": [ + { + "type": "XSDB_V3", + "name": "dbg_hub", + "spec": "labtools_xsdbm_v3", + "clk_input_freq_hz": "30000301" + }, + { + "type": "ILA_V3", + "name": "u_ila_cnt", + "spec": "labtools_ila_v6", + "ipName": "ila", + "core_location": { + "user_chain": 1, + "slave_index": 0, + "bscan_switch_index": 0 + }, + "uuid": "E055752C10485C0D9D7994B1C888EC3A", + "pins": [ + { + "name": "probe0", + "id": 0, + "type": "DATA_TRIGGER", + "direction": "IN", + "isVector": true, + "leftIndex": 0, + "rightIndex": 31, + "portIndex": 0, + "nets": [ + { + "name": "cnt", + "isBus": true, + "subnets": [ + { + "name": "cnt[31]" + }, + { + "name": "cnt[30]" + }, + { + "name": "cnt[29]" + }, + { + "name": "cnt[28]" + }, + { + "name": "cnt[27]" + }, + { + "name": "cnt[26]" + }, + { + "name": "cnt[25]" + }, + { + "name": "cnt[24]" + }, + { + "name": "cnt[23]" + }, + { + "name": "cnt[22]" + }, + { + "name": "cnt[21]" + }, + { + "name": "cnt[20]" + }, + { + "name": "cnt[19]" + }, + { + "name": "cnt[18]" + }, + { + "name": "cnt[17]" + }, + { + "name": "cnt[16]" + }, + { + "name": "cnt[15]" + }, + { + "name": "cnt[14]" + }, + { + "name": "cnt[13]" + }, + { + "name": "cnt[12]" + }, + { + "name": "cnt[11]" + }, + { + "name": "cnt[10]" + }, + { + "name": "cnt[9]" + }, + { + "name": "cnt[8]" + }, + { + "name": "cnt[7]" + }, + { + "name": "cnt[6]" + }, + { + "name": "cnt[5]" + }, + { + "name": "cnt[4]" + }, + { + "name": "cnt[3]" + }, + { + "name": "cnt[2]" + }, + { + "name": "cnt[1]" + }, + { + "name": "cnt[0]" + } + ] + } + ] + } + ] + } + ] + } + ] + } +} \ No newline at end of file diff --git a/dx_pwr_basic/dx_pwr_basic.runs/impl_1/system_top.bit b/dx_pwr_basic/dx_pwr_basic.runs/impl_1/system_top.bit new file mode 100644 index 0000000..4a478b2 --- /dev/null +++ b/dx_pwr_basic/dx_pwr_basic.runs/impl_1/system_top.bit @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:dbf9fc296d853e248b7d294fdf9f38f9ceeecbb8c5d0b414a9c262808f58c669 +size 17416456 diff --git a/dx_pwr_basic/dx_pwr_basic.runs/impl_1/system_top.ltx b/dx_pwr_basic/dx_pwr_basic.runs/impl_1/system_top.ltx new file mode 100644 index 0000000..cea9550 --- /dev/null +++ b/dx_pwr_basic/dx_pwr_basic.runs/impl_1/system_top.ltx @@ -0,0 +1,148 @@ +{ + "ltx_root": { + "version": 4, + "minor": 0, + "ltx_data": [ + { + "name": "EDA_PROBESET", + "active": true, + "debug_cores": [ + { + "type": "XSDB_V3", + "name": "dbg_hub", + "spec": "labtools_xsdbm_v3", + "clk_input_freq_hz": "30000301" + }, + { + "type": "ILA_V3", + "name": "u_ila_cnt", + "spec": "labtools_ila_v6", + "ipName": "ila", + "core_location": { + "user_chain": 1, + "slave_index": 0, + "bscan_switch_index": 0 + }, + "uuid": "E055752C10485C0D9D7994B1C888EC3A", + "pins": [ + { + "name": "probe0", + "id": 0, + "type": "DATA_TRIGGER", + "direction": "IN", + "isVector": true, + "leftIndex": 0, + "rightIndex": 31, + "portIndex": 0, + "nets": [ + { + "name": "cnt", + "isBus": true, + "subnets": [ + { + "name": "cnt[31]" + }, + { + "name": "cnt[30]" + }, + { + "name": "cnt[29]" + }, + { + "name": "cnt[28]" + }, + { + "name": "cnt[27]" + }, + { + "name": "cnt[26]" + }, + { + "name": "cnt[25]" + }, + { + "name": "cnt[24]" + }, + { + "name": "cnt[23]" + }, + { + "name": "cnt[22]" + }, + { + "name": "cnt[21]" + }, + { + "name": "cnt[20]" + }, + { + "name": "cnt[19]" + }, + { + "name": "cnt[18]" + }, + { + "name": "cnt[17]" + }, + { + "name": "cnt[16]" + }, + { + "name": "cnt[15]" + }, + { + "name": "cnt[14]" + }, + { + "name": "cnt[13]" + }, + { + "name": "cnt[12]" + }, + { + "name": "cnt[11]" + }, + { + "name": "cnt[10]" + }, + { + "name": "cnt[9]" + }, + { + "name": "cnt[8]" + }, + { + "name": "cnt[7]" + }, + { + "name": "cnt[6]" + }, + { + "name": "cnt[5]" + }, + { + "name": "cnt[4]" + }, + { + "name": "cnt[3]" + }, + { + "name": "cnt[2]" + }, + { + "name": "cnt[1]" + }, + { + "name": "cnt[0]" + } + ] + } + ] + } + ] + } + ] + } + ] + } +} \ No newline at end of file diff --git a/dx_pwr_basic/dx_pwr_basic.srcs/constrs_1/new/dx_z7100_pwr_inter_physical.xdc b/dx_pwr_basic/dx_pwr_basic.srcs/constrs_1/new/dx_z7100_pwr_inter_physical.xdc new file mode 100644 index 0000000..c3aa715 --- /dev/null +++ b/dx_pwr_basic/dx_pwr_basic.srcs/constrs_1/new/dx_z7100_pwr_inter_physical.xdc @@ -0,0 +1,179 @@ +# dx_z7100_power_interface + +## Timing Assertions Section + +## Physical Constraints Section + +# GLINK +set_property -dict {PACKAGE_PIN AG21 IOSTANDARD LVCMOS33} [get_ports clk_glink_25m ] ;# GLNIK_25M +set_property -dict {PACKAGE_PIN N8 } [get_ports clk_glink_125m_p ] ;# GLINK_REFCLK_P + +set_property -dict {PACKAGE_PIN V6 } [get_ports {glink_rx_p[0]} ] ;# GLINK_BUF_RX1_P +set_property -dict {PACKAGE_PIN U4 } [get_ports {glink_rx_p[1]} ] ;# GLINK_BUF_RX2_P +# set_property -dict {PACKAGE_PIN T2 } [get_ports {glink_tx_p[0]} ] ;# GLINK_BUF_TX1_P +# set_property -dict {PACKAGE_PIN R4 } [get_ports {glink_tx_p[1]} ] ;# GLINK_BUF_TX2_P + +# KK LVDS +set_property -dict {PACKAGE_PIN Y25 IOSTANDARD LVCMOS33} [get_ports kk_rx_rf ] ;# KK_RX_RF +set_property -dict {PACKAGE_PIN Y30 IOSTANDARD LVCMOS33} [get_ports kk_rx_ss ] ;# KK_RX_SS +set_property -dict {PACKAGE_PIN AA30 IOSTANDARD LVCMOS33} [get_ports kk_rx_rng[0] ] ;# KK_RX_PNG0 +set_property -dict {PACKAGE_PIN AB29 IOSTANDARD LVCMOS33} [get_ports kk_rx_rng[1] ] ;# KK_RX_PNG1 +set_property -dict {PACKAGE_PIN AB30 IOSTANDARD LVCMOS33} [get_ports kk_rx_pwdnb ] ;# KK_RX_PWDNB + +set_property -dict {PACKAGE_PIN AC28 IOSTANDARD LVCMOS33} [get_ports kk_rx_pclk ] ;# KK_RX_PCLK_OUT +set_property -dict {PACKAGE_PIN AB26 IOSTANDARD LVCMOS33} [get_ports kk_rx_lock ] ;# KK_RX_LOCK +set_property -dict {PACKAGE_PIN AC26 IOSTANDARD LVCMOS33} [get_ports kk_rx_de ] ;# KK_RX_DE_OUT + +set_property -dict {PACKAGE_PIN AD26 IOSTANDARD LVCMOS33} [get_ports kk_rx_cntl[0] ] ;# KK_RX_CNTL_OUT0 +set_property -dict {PACKAGE_PIN AD30 IOSTANDARD LVCMOS33} [get_ports kk_rx_cntl[1] ] ;# KK_RX_CNTL_OUT1 +set_property -dict {PACKAGE_PIN AE30 IOSTANDARD LVCMOS33} [get_ports kk_rx_cntl[2] ] ;# KK_RX_CNTL_OUT2 +set_property -dict {PACKAGE_PIN AC29 IOSTANDARD LVCMOS33} [get_ports kk_rx_cntl[3] ] ;# KK_RX_CNTL_OUT3 +set_property -dict {PACKAGE_PIN AD29 IOSTANDARD LVCMOS33} [get_ports kk_rx_cntl[4] ] ;# KK_RX_CNTL_OUT4 +set_property -dict {PACKAGE_PIN AD25 IOSTANDARD LVCMOS33} [get_ports kk_rx_cntl[5] ] ;# KK_RX_CNTL_OUT5 +set_property -dict {PACKAGE_PIN AE26 IOSTANDARD LVCMOS33} [get_ports kk_rx_cntl[6] ] ;# KK_RX_CNTL_OUT6 +set_property -dict {PACKAGE_PIN AB27 IOSTANDARD LVCMOS33} [get_ports kk_rx_cntl[7] ] ;# KK_RX_CNTL_OUT7 +set_property -dict {PACKAGE_PIN AC27 IOSTANDARD LVCMOS33} [get_ports kk_rx_cntl[8] ] ;# KK_RX_CNTL_OUT8 + +set_property -dict {PACKAGE_PIN AE28 IOSTANDARD LVCMOS33} [get_ports kk_rx_rgb[0] ] ;# KK_RX_RGB_OUT0 +set_property -dict {PACKAGE_PIN AF28 IOSTANDARD LVCMOS33} [get_ports kk_rx_rgb[1] ] ;# KK_RX_RGB_OUT1 +set_property -dict {PACKAGE_PIN AE27 IOSTANDARD LVCMOS33} [get_ports kk_rx_rgb[2] ] ;# KK_RX_RGB_OUT2 +set_property -dict {PACKAGE_PIN AF27 IOSTANDARD LVCMOS33} [get_ports kk_rx_rgb[3] ] ;# KK_RX_RGB_OUT3 +set_property -dict {PACKAGE_PIN AF29 IOSTANDARD LVCMOS33} [get_ports kk_rx_rgb[4] ] ;# KK_RX_RGB_OUT4 +set_property -dict {PACKAGE_PIN AG29 IOSTANDARD LVCMOS33} [get_ports kk_rx_rgb[5] ] ;# KK_RX_RGB_OUT5 +set_property -dict {PACKAGE_PIN AF30 IOSTANDARD LVCMOS33} [get_ports kk_rx_rgb[6] ] ;# KK_RX_RGB_OUT6 +set_property -dict {PACKAGE_PIN AG30 IOSTANDARD LVCMOS33} [get_ports kk_rx_rgb[7] ] ;# KK_RX_RGB_OUT7 +set_property -dict {PACKAGE_PIN AG26 IOSTANDARD LVCMOS33} [get_ports kk_rx_rgb[8] ] ;# KK_RX_RGB_OUT8 +set_property -dict {PACKAGE_PIN AG27 IOSTANDARD LVCMOS33} [get_ports kk_rx_rgb[9] ] ;# KK_RX_RGB_OUT9 +set_property -dict {PACKAGE_PIN AE25 IOSTANDARD LVCMOS33} [get_ports kk_rx_rgb[10] ] ;# KK_RX_RGB_OUT10 +set_property -dict {PACKAGE_PIN AF25 IOSTANDARD LVCMOS33} [get_ports kk_rx_rgb[11] ] ;# KK_RX_RGB_OUT11 +set_property -dict {PACKAGE_PIN AH28 IOSTANDARD LVCMOS33} [get_ports kk_rx_rgb[12] ] ;# KK_RX_RGB_OUT12 +set_property -dict {PACKAGE_PIN AH29 IOSTANDARD LVCMOS33} [get_ports kk_rx_rgb[13] ] ;# KK_RX_RGB_OUT13 +set_property -dict {PACKAGE_PIN AJ30 IOSTANDARD LVCMOS33} [get_ports kk_rx_rgb[14] ] ;# KK_RX_RGB_OUT14 +set_property -dict {PACKAGE_PIN AK30 IOSTANDARD LVCMOS33} [get_ports kk_rx_rgb[15] ] ;# KK_RX_RGB_OUT15 +set_property -dict {PACKAGE_PIN AJ28 IOSTANDARD LVCMOS33} [get_ports kk_rx_rgb[16] ] ;# KK_RX_RGB_OUT16 +set_property -dict {PACKAGE_PIN AJ29 IOSTANDARD LVCMOS33} [get_ports kk_rx_rgb[17] ] ;# KK_RX_RGB_OUT17 + +set_property -dict {PACKAGE_PIN U21 IOSTANDARD LVCMOS33} [get_ports kk_tx_pre ] ;# KK_TX_PRE +set_property -dict {PACKAGE_PIN P30 IOSTANDARD LVCMOS33} [get_ports kk_tx_rng[0] ] ;# KK_TX_RNG0 +set_property -dict {PACKAGE_PIN R30 IOSTANDARD LVCMOS33} [get_ports kk_tx_rng[1] ] ;# KK_TX_RNG1 +set_property -dict {PACKAGE_PIN T30 IOSTANDARD LVCMOS33} [get_ports kk_tx_pwdnb ] ;# KK_TX_PWDNB + +set_property -dict {PACKAGE_PIN U26 IOSTANDARD LVCMOS33} [get_ports clk_lvds_30m ] ;# LVDS_30M +set_property -dict {PACKAGE_PIN R25 IOSTANDARD LVCMOS33} [get_ports kk_tx_pclk_in ] ;# KK_TX_PCLK_IN +set_property -dict {PACKAGE_PIN V28 IOSTANDARD LVCMOS33} [get_ports kk_tx_de_in ] ;# KK_TX_DE_IN + +set_property -dict {PACKAGE_PIN V29 IOSTANDARD LVCMOS33} [get_ports kk_tx_cntl[0] ] ;# KK_TX_CNTL_OUT0 +set_property -dict {PACKAGE_PIN W29 IOSTANDARD LVCMOS33} [get_ports kk_tx_cntl[1] ] ;# KK_TX_CNTL_OUT1 +set_property -dict {PACKAGE_PIN W30 IOSTANDARD LVCMOS33} [get_ports kk_tx_cntl[2] ] ;# KK_TX_CNTL_OUT2 +set_property -dict {PACKAGE_PIN V27 IOSTANDARD LVCMOS33} [get_ports kk_tx_cntl[3] ] ;# KK_TX_CNTL_OUT3 +set_property -dict {PACKAGE_PIN W28 IOSTANDARD LVCMOS33} [get_ports kk_tx_cntl[4] ] ;# KK_TX_CNTL_OUT4 +set_property -dict {PACKAGE_PIN W25 IOSTANDARD LVCMOS33} [get_ports kk_tx_cntl[5] ] ;# KK_TX_CNTL_OUT5 +set_property -dict {PACKAGE_PIN W26 IOSTANDARD LVCMOS33} [get_ports kk_tx_cntl[6] ] ;# KK_TX_CNTL_OUT6 +set_property -dict {PACKAGE_PIN U25 IOSTANDARD LVCMOS33} [get_ports kk_tx_cntl[7] ] ;# KK_TX_CNTL_OUT7 +set_property -dict {PACKAGE_PIN V26 IOSTANDARD LVCMOS33} [get_ports kk_tx_cntl[8] ] ;# KK_TX_CNTL_OUT8 + +set_property -dict {PACKAGE_PIN R27 IOSTANDARD LVCMOS33} [get_ports kk_tx_rgb[0] ] ;# KK_TX_RGB_OUT0 +set_property -dict {PACKAGE_PIN T27 IOSTANDARD LVCMOS33} [get_ports kk_tx_rgb[1] ] ;# KK_TX_RGB_OUT1 +set_property -dict {PACKAGE_PIN N26 IOSTANDARD LVCMOS33} [get_ports kk_tx_rgb[2] ] ;# KK_TX_RGB_OUT2 +set_property -dict {PACKAGE_PIN N27 IOSTANDARD LVCMOS33} [get_ports kk_tx_rgb[3] ] ;# KK_TX_RGB_OUT3 +set_property -dict {PACKAGE_PIN P25 IOSTANDARD LVCMOS33} [get_ports kk_tx_rgb[4] ] ;# KK_TX_RGB_OUT4 +set_property -dict {PACKAGE_PIN P26 IOSTANDARD LVCMOS33} [get_ports kk_tx_rgb[5] ] ;# KK_TX_RGB_OUT5 +set_property -dict {PACKAGE_PIN T24 IOSTANDARD LVCMOS33} [get_ports kk_tx_rgb[6] ] ;# KK_TX_RGB_OUT6 +set_property -dict {PACKAGE_PIN T25 IOSTANDARD LVCMOS33} [get_ports kk_tx_rgb[7] ] ;# KK_TX_RGB_OUT7 +set_property -dict {PACKAGE_PIN P23 IOSTANDARD LVCMOS33} [get_ports kk_tx_rgb[8] ] ;# KK_TX_RGB_OUT8 +set_property -dict {PACKAGE_PIN P24 IOSTANDARD LVCMOS33} [get_ports kk_tx_rgb[9] ] ;# KK_TX_RGB_OUT9 +set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS33} [get_ports kk_tx_rgb[10] ] ;# KK_TX_RGB_OUT10 +set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVCMOS33} [get_ports kk_tx_rgb[11] ] ;# KK_TX_RGB_OUT11 +set_property -dict {PACKAGE_PIN T22 IOSTANDARD LVCMOS33} [get_ports kk_tx_rgb[12] ] ;# KK_TX_RGB_OUT12 +set_property -dict {PACKAGE_PIN T23 IOSTANDARD LVCMOS33} [get_ports kk_tx_rgb[13] ] ;# KK_TX_RGB_OUT13 +set_property -dict {PACKAGE_PIN R22 IOSTANDARD LVCMOS33} [get_ports kk_tx_rgb[14] ] ;# KK_TX_RGB_OUT14 +set_property -dict {PACKAGE_PIN R23 IOSTANDARD LVCMOS33} [get_ports kk_tx_rgb[15] ] ;# KK_TX_RGB_OUT15 +set_property -dict {PACKAGE_PIN U22 IOSTANDARD LVCMOS33} [get_ports kk_tx_rgb[16] ] ;# KK_TX_RGB_OUT16 +set_property -dict {PACKAGE_PIN V22 IOSTANDARD LVCMOS33} [get_ports kk_tx_rgb[17] ] ;# KK_TX_RGB_OUT17 + +# YC LVDS +set_property -dict {PACKAGE_PIN AH19 IOSTANDARD LVCMOS33} [get_ports yc_rx ] ;# LVDS_YC_RX +set_property -dict {PACKAGE_PIN AK18 IOSTANDARD LVCMOS33} [get_ports yc_tx ] ;# LVDS_YC_TX + +# RS422/RS485 +set_property -dict {PACKAGE_PIN W23 IOSTANDARD LVCMOS33} [get_ports rs422_gg_rxd ] ;# RS422_GG_RXD +set_property -dict {PACKAGE_PIN AJ25 IOSTANDARD LVCMOS33} [get_ports rs422_gg_reb ] ;# RS422_GG_REB +set_property -dict {PACKAGE_PIN AK25 IOSTANDARD LVCMOS33} [get_ports rs422_gg_de ] ;# RS422_GG_DE +set_property -dict {PACKAGE_PIN AK22 IOSTANDARD LVCMOS33} [get_ports rs422_gg_txd ] ;# RS422_GG_TXD + +set_property -dict {PACKAGE_PIN AJ21 IOSTANDARD LVCMOS33} [get_ports rs422_dg_rxd ] ;# RS422_DG_RXD +set_property -dict {PACKAGE_PIN AK21 IOSTANDARD LVCMOS33} [get_ports rs422_dg_reb ] ;# RS422_DG_REB +set_property -dict {PACKAGE_PIN AJ23 IOSTANDARD LVCMOS33} [get_ports rs422_dg_de ] ;# RS422_DG_DE +set_property -dict {PACKAGE_PIN AJ24 IOSTANDARD LVCMOS33} [get_ports rs422_dg_txd ] ;# RS422_DG_TXD + +set_property -dict {PACKAGE_PIN AH24 IOSTANDARD LVCMOS33} [get_ports rs422_ts_rxd ] ;# RS422_TS_RXD +set_property -dict {PACKAGE_PIN AG22 IOSTANDARD LVCMOS33} [get_ports rs422_ts_reb ] ;# RS422_TS_REB +set_property -dict {PACKAGE_PIN AH22 IOSTANDARD LVCMOS33} [get_ports rs422_ts_de ] ;# RS422_TS_DE +set_property -dict {PACKAGE_PIN AC24 IOSTANDARD LVCMOS33} [get_ports rs422_ts_txd ] ;# RS422_TS_TXD + +set_property -dict {PACKAGE_PIN AG24 IOSTANDARD LVCMOS33} [get_ports rs485_by_rxd ] ;# RS485_BY_RXD +set_property -dict {PACKAGE_PIN AG25 IOSTANDARD LVCMOS33} [get_ports rs485_by_reb ] ;# RS485_BY_REB +set_property -dict {PACKAGE_PIN AF23 IOSTANDARD LVCMOS33} [get_ports rs485_by_de ] ;# RS485_BY_DE +set_property -dict {PACKAGE_PIN AF24 IOSTANDARD LVCMOS33} [get_ports rs485_by_txd ] ;# RS485_BY_TXD + +set_property -dict {PACKAGE_PIN AE21 IOSTANDARD LVCMOS33} [get_ports rs422_int_mc_rxd ] ;# RS422_INT_MC_RXD +set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVCMOS33} [get_ports rs422_int_mc_reb ] ;# RS422_INT_MC_REB +set_property -dict {PACKAGE_PIN AE23 IOSTANDARD LVCMOS33} [get_ports rs422_int_mc_de ] ;# RS422_INT_MC_DE +set_property -dict {PACKAGE_PIN AE22 IOSTANDARD LVCMOS33} [get_ports rs422_int_mc_txd ] ;# RS422_INT_MC_TXD + +set_property -dict {PACKAGE_PIN AF20 IOSTANDARD LVCMOS33} [get_ports rs422_int_dh_rxd ] ;# RS422_INT_DH_RXD +set_property -dict {PACKAGE_PIN AG20 IOSTANDARD LVCMOS33} [get_ports rs422_int_dh_reb ] ;# RS422_INT_DH_REB +set_property -dict {PACKAGE_PIN AJ20 IOSTANDARD LVCMOS33} [get_ports rs422_int_dh_de ] ;# RS422_INT_DH_DE +set_property -dict {PACKAGE_PIN AK20 IOSTANDARD LVCMOS33} [get_ports rs422_int_dh_txd ] ;# RS422_INT_DH_TXD + +# Inter-board Ports +set_property -dict {PACKAGE_PIN AD10 } [get_ports clk_s2p_0_p ] ;# GTCLK0_S2P_P +set_property -dict {PACKAGE_PIN U8 } [get_ports clk_s2p_1_p ] ;# GTCLK1_S2P_P + +set_property -dict {PACKAGE_PIN AJ14 IOSTANDARD LVDS_25 } [get_ports f1_lvds_io_p[0] ] ;# F1_LVDS_IO1P +set_property -dict {PACKAGE_PIN AK13 IOSTANDARD LVDS_25 } [get_ports f1_lvds_io_p[1] ] ;# F1_LVDS_IO2P +set_property -dict {PACKAGE_PIN AJ15 IOSTANDARD LVDS_25 } [get_ports f1_lvds_io_p[2] ] ;# F1_LVDS_IO3P +set_property -dict {PACKAGE_PIN AJ16 IOSTANDARD LVDS_25 } [get_ports f1_lvds_io_p[3] ] ;# F1_LVDS_IO4P +set_property -dict {PACKAGE_PIN AH18 IOSTANDARD LVDS_25 } [get_ports f1_lvds_io_p[4] ] ;# F1_LVDS_IO5P + +set_property -dict {PACKAGE_PIN AF14 IOSTANDARD LVDS_25 } [get_ports f2_lvds_io_p[0] ] ;# F2_LVDS_IO1P +set_property -dict {PACKAGE_PIN AH14 IOSTANDARD LVDS_25 } [get_ports f2_lvds_io_p[1] ] ;# F2_LVDS_IO2P +set_property -dict {PACKAGE_PIN AG12 IOSTANDARD LVDS_25 } [get_ports f2_lvds_io_p[2] ] ;# F2_LVDS_IO3P +set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVDS_25 } [get_ports f2_lvds_io_p[3] ] ;# F2_LVDS_IO4P +set_property -dict {PACKAGE_PIN AD14 IOSTANDARD LVDS_25 } [get_ports f2_lvds_io_p[4] ] ;# F2_LVDS_IO5P + +set_property -dict {PACKAGE_PIN AH10 } [get_ports f1_gtx_s2p_p[0] ] ;# F1_GTX0_S2P_P +set_property -dict {PACKAGE_PIN AJ8 } [get_ports f1_gtx_s2p_p[1] ] ;# F1_GTX1_S2P_P +set_property -dict {PACKAGE_PIN AG8 } [get_ports f1_gtx_s2p_p[2] ] ;# F1_GTX2_S2P_P +set_property -dict {PACKAGE_PIN AE8 } [get_ports f1_gtx_s2p_p[3] ] ;# F1_GTX3_S2P_P + +# set_property -dict {PACKAGE_PIN AK10 } [get_ports f1_gtx_p2s_p[0] ] ;# F1_GTX0_P2S_P +# set_property -dict {PACKAGE_PIN AK6 } [get_ports f1_gtx_p2s_p[1] ] ;# F1_GTX1_P2S_P +# set_property -dict {PACKAGE_PIN AJ4 } [get_ports f1_gtx_p2s_p[2] ] ;# F1_GTX2_P2S_P +# set_property -dict {PACKAGE_PIN AK2 } [get_ports f1_gtx_p2s_p[3] ] ;# F1_GTX3_P2S_P + +set_property -dict {PACKAGE_PIN AC4 } [get_ports f2_gtx_s2p_p[0] ] ;# F2_GTX0_S2P_P +set_property -dict {PACKAGE_PIN AB6 } [get_ports f2_gtx_s2p_p[1] ] ;# F2_GTX1_S2P_P +set_property -dict {PACKAGE_PIN Y6 } [get_ports f2_gtx_s2p_p[2] ] ;# F2_GTX2_S2P_P +set_property -dict {PACKAGE_PIN AA4 } [get_ports f2_gtx_s2p_p[3] ] ;# F2_GTX3_S2P_P + +# set_property -dict {PACKAGE_PIN AB2 } [get_ports f2_gtx_p2s_p[0] ] ;# F2_GTX0_P2S_P +# set_property -dict {PACKAGE_PIN Y2 } [get_ports f2_gtx_p2s_p[1] ] ;# F2_GTX1_P2S_P +# set_property -dict {PACKAGE_PIN W4 } [get_ports f2_gtx_p2s_p[2] ] ;# F2_GTX2_P2S_P +# set_property -dict {PACKAGE_PIN V2 } [get_ports f2_gtx_p2s_p[3] ] ;# F2_GTX3_P2S_P + +# 3.3V Debug IO +set_property -dict {PACKAGE_PIN Y20 IOSTANDARD LVCMOS33} [get_ports uart1_txd ] ;# UART_1_TXD +set_property -dict {PACKAGE_PIN AA20 IOSTANDARD LVCMOS33} [get_ports uart1_rxd ] ;# UART_1_RXD +set_property -dict {PACKAGE_PIN AC18 IOSTANDARD LVCMOS33} [get_ports uart2_txd ] ;# UART_2_TXD +set_property -dict {PACKAGE_PIN AC19 IOSTANDARD LVCMOS33} [get_ports uart2_rxd ] ;# UART_2_RXD +set_property -dict {PACKAGE_PIN AD18 IOSTANDARD LVCMOS33} [get_ports uart3_txd ] ;# UART_3_TXD +set_property -dict {PACKAGE_PIN AD19 IOSTANDARD LVCMOS33} [get_ports uart3_rxd ] ;# UART_3_RXD + +set_property -dict {PACKAGE_PIN AB24 IOSTANDARD LVCMOS33} [get_ports debug_io_1 ] ;# DEBUG_IO_1 +set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVCMOS33} [get_ports debug_io_2 ] ;# DEBUG_IO_2 +set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVCMOS33} [get_ports debug_io_3 ] ;# DEBUG_IO_3 +set_property -dict {PACKAGE_PIN AC22 IOSTANDARD LVCMOS33} [get_ports debug_io_4 ] ;# DEBUG_IO_4 +set_property -dict {PACKAGE_PIN AC23 IOSTANDARD LVCMOS33} [get_ports debug_io_5 ] ;# DEBUG_IO_5 +set_property -dict {PACKAGE_PIN AC21 IOSTANDARD LVCMOS33} [get_ports debug_io_6 ] ;# DEBUG_IO_6 + diff --git a/dx_pwr_basic/dx_pwr_basic.srcs/sources_1/bd/system_bd/ip/system_bd_processing_system7_0_0/system_bd_processing_system7_0_0.xci b/dx_pwr_basic/dx_pwr_basic.srcs/sources_1/bd/system_bd/ip/system_bd_processing_system7_0_0/system_bd_processing_system7_0_0.xci new file mode 100644 index 0000000..5b54d06 --- /dev/null +++ b/dx_pwr_basic/dx_pwr_basic.srcs/sources_1/bd/system_bd/ip/system_bd_processing_system7_0_0/system_bd_processing_system7_0_0.xci @@ -0,0 +1,1259 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "system_bd_processing_system7_0_0", + "cell_name": "processing_system7", + "component_reference": "xilinx.com:ip:processing_system7:5.5", + "ip_revision": "6", + "gen_directory": "../../../../../../dx_pwr_basic.gen/sources_1/bd/system_bd/ip/system_bd_processing_system7_0_0", + "parameters": { + "component_parameters": { + "PCW_DDR_RAM_BASEADDR": [ { "value": "0x00100000", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "PCW_DDR_RAM_HIGHADDR": [ { "value": "0x1FFFFFFF", "value_src": "user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "PCW_UART0_BASEADDR": [ { "value": "0xE0000000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_UART0_HIGHADDR": [ { "value": "0xE0000FFF", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_UART1_BASEADDR": [ { "value": "0xE0001000", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "PCW_UART1_HIGHADDR": [ { "value": "0xE0001FFF", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "PCW_I2C0_BASEADDR": [ { "value": "0xE0004000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_I2C0_HIGHADDR": [ { "value": "0xE0004FFF", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_I2C1_BASEADDR": [ { "value": "0xE0005000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_I2C1_HIGHADDR": [ { "value": "0xE0005FFF", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_SPI0_BASEADDR": [ { "value": "0xE0006000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_SPI0_HIGHADDR": [ { "value": "0xE0006FFF", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_SPI1_BASEADDR": [ { "value": "0xE0007000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_SPI1_HIGHADDR": [ { "value": "0xE0007FFF", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_CAN0_BASEADDR": [ { "value": "0xE0008000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_CAN0_HIGHADDR": [ { "value": "0xE0008FFF", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_CAN1_BASEADDR": [ { "value": "0xE0009000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_CAN1_HIGHADDR": [ { "value": "0xE0009FFF", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_GPIO_BASEADDR": [ { "value": "0xE000A000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_GPIO_HIGHADDR": [ { "value": "0xE000AFFF", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_ENET0_BASEADDR": [ { "value": "0xE000B000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_ENET0_HIGHADDR": [ { "value": "0xE000BFFF", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_ENET1_BASEADDR": [ { "value": "0xE000C000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_ENET1_HIGHADDR": [ { "value": "0xE000CFFF", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_SDIO0_BASEADDR": [ { "value": "0xE0100000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_SDIO0_HIGHADDR": [ { "value": "0xE0100FFF", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_SDIO1_BASEADDR": [ { "value": "0xE0101000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_SDIO1_HIGHADDR": [ { "value": "0xE0101FFF", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_USB0_BASEADDR": [ { "value": "0xE0102000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_USB0_HIGHADDR": [ { "value": "0xE0102fff", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_USB1_BASEADDR": [ { "value": "0xE0103000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_USB1_HIGHADDR": [ { "value": "0xE0103fff", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_TTC0_BASEADDR": [ { "value": "0xE0104000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_TTC0_HIGHADDR": [ { "value": "0xE0104fff", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_TTC1_BASEADDR": [ { "value": "0xE0105000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_TTC1_HIGHADDR": [ { "value": "0xE0105fff", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_FCLK_CLK0_BUF": [ { "value": "TRUE", "resolve_type": "user", "usage": "all" } ], + "PCW_FCLK_CLK1_BUF": [ { "value": "FALSE", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_FCLK_CLK2_BUF": [ { "value": "FALSE", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_FCLK_CLK3_BUF": [ { "value": "FALSE", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_UIPARAM_DDR_FREQ_MHZ": [ { "value": "533.333333", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_BANK_ADDR_COUNT": [ { "value": "3", "value_src": "user", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], + "PCW_UIPARAM_DDR_ROW_ADDR_COUNT": [ { "value": "15", "value_src": "user", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], + "PCW_UIPARAM_DDR_COL_ADDR_COUNT": [ { "value": "10", "value_src": "user", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], + "PCW_UIPARAM_DDR_CL": [ { "value": "7", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_UIPARAM_DDR_CWL": [ { "value": "6", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_UIPARAM_DDR_T_RCD": [ { "value": "7", "value_src": "user", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], + "PCW_UIPARAM_DDR_T_RP": [ { "value": "7", "value_src": "user", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], + "PCW_UIPARAM_DDR_T_RC": [ { "value": "48.91", "value_src": "user", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], + "PCW_UIPARAM_DDR_T_RAS_MIN": [ { "value": "35.0", "value_src": "user", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], + "PCW_UIPARAM_DDR_T_FAW": [ { "value": "40.0", "value_src": "user", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], + "PCW_UIPARAM_DDR_AL": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_BOARD_DELAY0": [ { "value": "0.25", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_BOARD_DELAY1": [ { "value": "0.25", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_BOARD_DELAY2": [ { "value": "0.25", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_BOARD_DELAY3": [ { "value": "0.25", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_DQS_0_LENGTH_MM": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_DQS_1_LENGTH_MM": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_DQS_2_LENGTH_MM": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_DQS_3_LENGTH_MM": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_DQ_0_LENGTH_MM": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_DQ_1_LENGTH_MM": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_DQ_2_LENGTH_MM": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_DQ_3_LENGTH_MM": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH": [ { "value": "133.8645", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH": [ { "value": "119.997", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH": [ { "value": "121.146", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH": [ { "value": "90.125", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH": [ { "value": "111.7605", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH": [ { "value": "123.5525", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH": [ { "value": "120.714", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH": [ { "value": "100.836", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH": [ { "value": "80.0515", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH": [ { "value": "80.0515", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH": [ { 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false, "usage": "all" } ], + "PCW_TRACE_INTERNAL_WIDTH": [ { "value": "2", "resolve_type": "user", "usage": "all" } ], + "PCW_WDT_PERIPHERAL_ENABLE": [ { "value": "0", "resolve_type": "user", "usage": "all" } ], + "PCW_WDT_WDT_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_TTC1_PERIPHERAL_ENABLE": [ { "value": "0", "resolve_type": "user", "usage": "all" } ], + "PCW_TTC1_TTC1_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_USB0_PERIPHERAL_ENABLE": [ { "value": "0", "resolve_type": "user", "usage": "all" } ], + "PCW_USB0_USB0_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_USB0_RESET_ENABLE": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_USB0_RESET_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_USB1_RESET_ENABLE": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_USB1_RESET_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_I2C0_GRP_INT_ENABLE": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_I2C0_GRP_INT_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_I2C1_PERIPHERAL_ENABLE": [ { "value": "0", "resolve_type": "user", "usage": "all" } ], + "PCW_I2C1_I2C1_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_I2C_RESET_ENABLE": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_I2C_RESET_SELECT": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_GPIO_PERIPHERAL_ENABLE": [ { "value": "0", "resolve_type": "user", "usage": "all" } ], + "PCW_GPIO_MIO_GPIO_ENABLE": [ { "value": "0", "resolve_type": "user", "usage": "all" } ], + "PCW_GPIO_MIO_GPIO_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_APU_CLK_RATIO_ENABLE": [ { "value": "6:2:1", "resolve_type": "user", "usage": "all" } ], + "PCW_ENET0_PERIPHERAL_FREQMHZ": [ { "value": "1000 Mbps", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_ENET1_PERIPHERAL_FREQMHZ": [ { "value": "1000 Mbps", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_CPU_PERIPHERAL_CLKSRC": [ { "value": "ARM PLL", "resolve_type": "user", "usage": "all" } ], + "PCW_DDR_PERIPHERAL_CLKSRC": [ { "value": "DDR PLL", "resolve_type": "user", "usage": "all" } ], + "PCW_SMC_PERIPHERAL_CLKSRC": [ { "value": "IO PLL", "resolve_type": "user", "usage": "all" } ], + "PCW_QSPI_PERIPHERAL_CLKSRC": [ { "value": "IO PLL", "resolve_type": "user", "usage": "all" } ], + "PCW_SDIO_PERIPHERAL_CLKSRC": [ { "value": "IO PLL", "resolve_type": "user", "usage": "all" } ], + "PCW_UART_PERIPHERAL_CLKSRC": [ { "value": "IO PLL", "resolve_type": "user", "usage": "all" } ], + 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"slow" + }, + "PCW_MIO_TREE_PERIPHERALS": { + "value": "Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#unassigned#unassigned#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#UART 1#UART 1#unassigned#unassigned#unassigned#unassigned" + }, + "PCW_MIO_TREE_SIGNALS": { + "value": "qspi1_ss_b#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#unassigned#unassigned#qspi1_sclk#qspi1_io[0]#qspi1_io[1]#qspi1_io[2]#qspi1_io[3]#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#tx#rx#unassigned#unassigned#unassigned#unassigned" + }, + "PCW_QSPI_GRP_FBCLK_ENABLE": { + "value": "0" + }, + "PCW_QSPI_GRP_IO1_ENABLE": { + "value": "1" + }, + "PCW_QSPI_GRP_IO1_IO": { + "value": "MIO 0 9 .. 13" + }, + "PCW_QSPI_GRP_SINGLE_SS_ENABLE": { + "value": "0" + }, + "PCW_QSPI_GRP_SS1_ENABLE": { + "value": "0" + }, + "PCW_QSPI_INTERNAL_HIGHADDRESS": { + "value": "0xFDFFFFFF" + }, + "PCW_QSPI_PERIPHERAL_ENABLE": { + "value": "1" + }, + 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"resolve_type": "user", "usage": "all" } ], + "CLKFB_IN_P_PORT": [ { "value": "clkfb_in_p", "resolve_type": "user", "usage": "all" } ], + "CLKFB_IN_N_PORT": [ { "value": "clkfb_in_n", "resolve_type": "user", "usage": "all" } ], + "CLKFB_OUT_PORT": [ { "value": "clkfb_out", "resolve_type": "user", "usage": "all" } ], + "CLKFB_OUT_P_PORT": [ { "value": "clkfb_out_p", "resolve_type": "user", "usage": "all" } ], + "CLKFB_OUT_N_PORT": [ { "value": "clkfb_out_n", "resolve_type": "user", "usage": "all" } ], + "PLATFORM": [ { "value": "UNKNOWN", "resolve_type": "user", "usage": "all" } ], + "SUMMARY_STRINGS": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ], + "USE_LOCKED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CALC_DONE": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ], + "USE_RESET": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_POWER_DOWN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_STATUS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_FREEZE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_CLK_VALID": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_INCLK_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_CLKFB_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "RESET_PORT": [ { "value": "reset", "resolve_type": "user", "usage": "all" } ], + "LOCKED_PORT": [ { "value": "locked", "resolve_type": "user", "usage": "all" } ], + "POWER_DOWN_PORT": [ { "value": "power_down", "resolve_type": "user", "usage": "all" } ], + "CLK_VALID_PORT": [ { "value": "CLK_VALID", "resolve_type": "user", "usage": "all" } ], + "STATUS_PORT": [ { "value": "STATUS", "resolve_type": "user", "usage": "all" } ], + "CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "user", "usage": "all" } ], + "INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "user", "usage": "all" } ], + "CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "user", "usage": "all" } ], + "SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "user", "usage": "all" } ], + "SS_MOD_FREQ": [ { "value": "250", "resolve_type": "user", "format": "float", "usage": "all" } ], + "SS_MOD_TIME": [ { "value": "0.004", "resolve_type": "user", "format": "float", "usage": "all" } ], + "OVERRIDE_MMCM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ], + "MMCM_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ], + "MMCM_CLKFBOUT_MULT_F": [ { "value": "32.500", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKIN1_PERIOD": [ { "value": "33.333", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKIN2_PERIOD": [ { "value": "10.0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT4_CASCADE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLOCK_HOLD": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_COMPENSATION": [ { "value": "ZHOLD", "resolve_type": "user", "usage": "all" } ], + "MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_STARTUP_WAIT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT0_DIVIDE_F": [ { "value": "32.500", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT2_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT3_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT4_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT5_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT6_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT6_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT6_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "OVERRIDE_PLL": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "PLL_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ], + "PLL_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ], + "PLL_CLKFBOUT_MULT": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLK_FEEDBACK": [ { "value": "CLKFBOUT", "resolve_type": "user", "usage": "all" } ], + "PLL_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKIN_PERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_COMPENSATION": [ { "value": "SYSTEM_SYNCHRONOUS", "resolve_type": "user", "usage": "all" } ], + "PLL_REF_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT0_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "RESET_TYPE": [ { "value": "ACTIVE_HIGH", "resolve_type": "user", "usage": "all" } ], + "USE_SAFE_CLOCK_STARTUP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_CLOCK_SEQUENCING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT1_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "CLKOUT2_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "CLKOUT3_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "CLKOUT4_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "CLKOUT5_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "CLKOUT6_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "CLKOUT7_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "USE_BOARD_FLOW": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_IN1_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ], + "CLK_IN2_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ], + "DIFF_CLK_IN1_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ], + "DIFF_CLK_IN2_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ], + "AUTO_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "user", "usage": "all" } ], + "RESET_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ], + "ENABLE_CDDC": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CDDCDONE_PORT": [ { "value": "cddcdone", "resolve_type": "user", "usage": "all" } ], + "CDDCREQ_PORT": [ { "value": "cddcreq", "resolve_type": "user", "usage": "all" } ], + "ENABLE_CLKOUTPHY": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUTPHY_REQUESTED_FREQ": [ { "value": "600.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT1_JITTER": [ { "value": "317.943", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT1_PHASE_ERROR": [ { "value": "210.329", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT2_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT2_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT3_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT3_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT4_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT4_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT5_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT5_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT6_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT6_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT7_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT7_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "INPUT_MODE": [ { "value": "frequency", "resolve_type": "user", "usage": "all" } ], + "INTERFACE_SELECTION": [ { "value": "Enable_AXI", "resolve_type": "user", "usage": "all" } ], + "AXI_DRP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "PHASE_DUTY_CONFIG": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ] + }, + "model_parameters": { + "C_CLKOUT2_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_USER_CLK_FREQ0": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_AUTO_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "generated", "usage": "all" } ], + "C_USER_CLK_FREQ1": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_USER_CLK_FREQ2": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_USER_CLK_FREQ3": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_ENABLE_CLOCK_MONITOR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_ENABLE_USER_CLOCK0": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_ENABLE_USER_CLOCK1": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_ENABLE_USER_CLOCK2": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_ENABLE_USER_CLOCK3": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_Enable_PLL0": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_Enable_PLL1": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_REF_CLK_FREQ": [ { "value": "100.0", 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"all" } ], + "C_PLL_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_PLL_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_PLL_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_PLL_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_PLL_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_PLL_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_PLL_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_PLL_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_PLL_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": 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"C_PLL_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLOCK_MGR_TYPE": [ { "value": "NA", "resolve_type": "generated", "usage": "all" } ], + "C_OVERRIDE_MMCM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_OVERRIDE_PLL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_PRIMARY_PORT": [ { "value": "clk_in1", "resolve_type": "generated", "usage": "all" } ], + "C_SECONDARY_PORT": [ { "value": "clk_in2", "resolve_type": "generated", "usage": "all" } ], + "C_CLK_OUT1_PORT": [ { "value": "clk_out1", "resolve_type": "generated", "usage": "all" } ], + "C_CLK_OUT2_PORT": [ { "value": "clk_out2", "resolve_type": "generated", "usage": "all" } ], + "C_CLK_OUT3_PORT": [ { "value": "clk_out3", "resolve_type": "generated", "usage": "all" } ], + "C_CLK_OUT4_PORT": [ { "value": "clk_out4", "resolve_type": "generated", "usage": "all" } ], + "C_CLK_OUT5_PORT": [ { "value": "clk_out5", "resolve_type": "generated", "usage": "all" } ], + "C_CLK_OUT6_PORT": [ { "value": "clk_out6", "resolve_type": "generated", "usage": "all" } ], + "C_CLK_OUT7_PORT": [ { "value": "clk_out7", "resolve_type": "generated", "usage": "all" } ], + "C_RESET_PORT": [ { "value": "reset", "resolve_type": "generated", "usage": "all" } ], + "C_LOCKED_PORT": [ { "value": "locked", "resolve_type": "generated", "usage": "all" } ], + "C_CLKFB_IN_PORT": [ { "value": "clkfb_in", "resolve_type": "generated", "usage": "all" } ], + "C_CLKFB_IN_P_PORT": [ { "value": "clkfb_in_p", "resolve_type": "generated", "usage": "all" } ], + "C_CLKFB_IN_N_PORT": [ { "value": "clkfb_in_n", "resolve_type": "generated", "usage": "all" } ], + "C_CLKFB_OUT_PORT": [ { "value": "clkfb_out", "resolve_type": "generated", "usage": "all" } ], + "C_CLKFB_OUT_P_PORT": [ { "value": "clkfb_out_p", "resolve_type": "generated", "usage": "all" } ], + "C_CLKFB_OUT_N_PORT": [ { "value": "clkfb_out_n", "resolve_type": "generated", "usage": "all" } ], + "C_POWER_DOWN_PORT": [ { "value": "power_down", "resolve_type": "generated", "usage": "all" } ], + "C_DADDR_PORT": [ { "value": "daddr", "resolve_type": "generated", "usage": "all" } ], + "C_DCLK_PORT": [ { "value": "dclk", "resolve_type": "generated", "usage": "all" } ], + "C_DRDY_PORT": [ { "value": "drdy", "resolve_type": "generated", "usage": "all" } ], + "C_DWE_PORT": [ { "value": "dwe", "resolve_type": "generated", "usage": "all" } ], + "C_DIN_PORT": [ { "value": "din", "resolve_type": "generated", "usage": "all" } ], + "C_DOUT_PORT": [ { "value": "dout", "resolve_type": "generated", "usage": "all" } ], + "C_DEN_PORT": [ { "value": "den", "resolve_type": "generated", "usage": "all" } ], + "C_PSCLK_PORT": [ { "value": "psclk", "resolve_type": "generated", "usage": "all" } ], + "C_PSEN_PORT": [ { "value": "psen", "resolve_type": "generated", "usage": "all" } ], + "C_PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "generated", "usage": "all" } ], + "C_PSDONE_PORT": [ { "value": "psdone", "resolve_type": "generated", "usage": "all" } ], + "C_CLK_VALID_PORT": [ { "value": "CLK_VALID", "resolve_type": "generated", "usage": "all" } ], + "C_STATUS_PORT": [ { "value": "STATUS", "resolve_type": "generated", "usage": "all" } ], + "C_CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "generated", "usage": "all" } ], + "C_INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "generated", "usage": "all" } ], + "C_CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "generated", "usage": "all" } ], + "C_CLKIN1_JITTER_PS": [ { "value": "333.33000000000004", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "generated", "usage": "all" } ], + "C_SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "generated", "usage": "all" } ], + "C_SS_MOD_PERIOD": [ { "value": "4000", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_SS_MOD_TIME": [ { "value": "0.004", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_HAS_CDDC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_CDDCDONE_PORT": [ { "value": "cddcdone", "resolve_type": "generated", "usage": "all" } ], + "C_CDDCREQ_PORT": [ { "value": "cddcreq", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUTPHY_MODE": [ { "value": "VCO", "resolve_type": "generated", "usage": "all" } ], + "C_ENABLE_CLKOUTPHY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_INTERFACE_SELECTION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_S_AXI_ADDR_WIDTH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_S_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_POWER_REG": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT0_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT0_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT1_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT1_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT2_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT2_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT3_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT3_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT4_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT4_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT5_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT5_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT6_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT6_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKFBOUT_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKFBOUT_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_DIVCLK": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_LOCK_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_LOCK_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_LOCK_3": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_FILTER_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_FILTER_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_DIVIDE1_AUTO": [ { "value": "1", "resolve_type": "generated", "usage": "all" } ], + "C_DIVIDE2_AUTO": [ { "value": "0.03076923076923077", "resolve_type": "generated", "usage": "all" } ], + "C_DIVIDE3_AUTO": [ { "value": "0.03076923076923077", "resolve_type": "generated", "usage": "all" } ], + "C_DIVIDE4_AUTO": [ { "value": "0.03076923076923077", "resolve_type": "generated", "usage": "all" } ], + "C_DIVIDE5_AUTO": [ { "value": "0.03076923076923077", "resolve_type": "generated", "usage": "all" } ], + "C_DIVIDE6_AUTO": [ { "value": "0.03076923076923077", "resolve_type": "generated", "usage": "all" } ], + "C_DIVIDE7_AUTO": [ { "value": "0.03076923076923077", "resolve_type": "generated", "usage": "all" } ], + "C_PLLBUFGCEDIV": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_MMCMBUFGCEDIV": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_PLLBUFGCEDIV1": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_PLLBUFGCEDIV2": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_PLLBUFGCEDIV3": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_PLLBUFGCEDIV4": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_MMCMBUFGCEDIV1": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_MMCMBUFGCEDIV2": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_MMCMBUFGCEDIV3": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_MMCMBUFGCEDIV4": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_MMCMBUFGCEDIV5": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_MMCMBUFGCEDIV6": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_MMCMBUFGCEDIV7": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT1_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT2_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT3_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT4_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT0_ACTUAL_FREQ": [ { "value": "30.00000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT1_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT2_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT3_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT4_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT5_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT6_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ], + "C_M_MAX": [ { "value": "64.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_M_MIN": [ { "value": "2.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_D_MAX": [ { "value": "93.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_D_MIN": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_O_MAX": [ { "value": "128.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_O_MIN": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_VCO_MIN": [ { "value": "600.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_VCO_MAX": [ { "value": "1440.000", "resolve_type": "generated", "format": "float", "usage": "all" } ] + }, + "project_parameters": { + "ARCHITECTURE": [ { "value": "zynq" } ], + "BASE_BOARD_PART": [ { "value": "" } ], + "BOARD_CONNECTIONS": [ { "value": "" } ], + "DEVICE": [ { "value": "xc7z100" } ], + "NEXTGEN_VERSAL": [ { "value": "0" } ], + "PACKAGE": [ { "value": "ffg900" } ], + "PREFHDL": [ { "value": "VERILOG" } ], + "SILICON_REVISION": [ { "value": "" } ], + "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], + "SPEEDGRADE": [ { "value": "-2" } ], + "STATIC_POWER": [ { "value": "" } ], + "TEMPERATURE_GRADE": [ { "value": "" } ] + }, + "runtime_parameters": { + "IPCONTEXT": [ { "value": "IP_Flow" } ], + "IPREVISION": [ { "value": "14" } ], + "MANAGED": [ { "value": "TRUE" } ], + "OUTPUTDIR": [ { "value": "../../../../dx_pwr_basic.gen/sources_1/ip/lvds_clk_gen" } ], + "SELECTEDSIMMODEL": [ { "value": "" } ], + "SHAREDDIR": [ { "value": "." } ], + "SWVERSION": [ { "value": "2024.1" } ], + "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ] + } + }, + "boundary": { + "ports": { + "clk_in1": [ { "direction": "in" } ], + "clk_out1": [ { "direction": "out" } ], + "locked": [ { "direction": "out" } ] + }, + "interfaces": { + "clock_CLK_IN1": { + "vlnv": "xilinx.com:signal:clock:1.0", + "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", + "mode": "slave", + "parameters": { + "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ], + "BOARD.ASSOCIATED_PARAM": [ { "value": "CLK_IN1_BOARD_INTERFACE", "usage": "all", "is_static_object": false } ] + }, + "port_maps": { + "CLK_IN1": [ { "physical_name": "clk_in1" } ] + } + }, + "clock_CLK_OUT1": { + "vlnv": "xilinx.com:signal:clock:1.0", + "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", + "mode": "master", + "parameters": { + "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "CLK_OUT1": [ { "physical_name": "clk_out1" } ] + } + } + } + } + } +} \ No newline at end of file diff --git a/dx_pwr_basic/dx_pwr_basic.srcs/sources_1/new/system_top.v b/dx_pwr_basic/dx_pwr_basic.srcs/sources_1/new/system_top.v new file mode 100644 index 0000000..83e6305 --- /dev/null +++ b/dx_pwr_basic/dx_pwr_basic.srcs/sources_1/new/system_top.v @@ -0,0 +1,243 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 09/09/2024 04:20:47 PM +// Design Name: +// Module Name: system_top +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module system_top +( + /*************************************************************************** + * Contents + * 01. Clocks + * 02. HMC7044 Interface + * 03. AD9361-1 Interface + * 04. AD9361-2 Interface + * 05. Phased-Array Control + * 06. RF Synthesizer Control + * 07. Debug IO + * 08. DDR and Fixed-io (Do NOT Modify) + **************************************************************************/ + + // ************************************************************************* + // ********************************* GLINK ********************************* + // ************************************************************************* + // clocks + input clk_glink_25m , + input clk_glink_125m_p, + input clk_glink_125m_n, + // data + input [1:0] glink_rx_p , + input [1:0] glink_rx_n , + // output [1:0] glink_tx_p , + // output [1:0] glink_tx_n , + // ************************************************************************* + // ******************************** KK LVDS ******************************** + // ************************************************************************* + // kk rx lvds (control) + output kk_rx_rf , + output kk_rx_ss , + output [1:0] kk_rx_rng , + output kk_rx_pwdnb , + // kk rx lvds (data) + input kk_rx_pclk , + input kk_rx_lock , + input kk_rx_de , + input [8:0] kk_rx_cntl , + input [17:0] kk_rx_rgb , + // kk tx lvds (control) + output kk_tx_pre , + output [1:0] kk_tx_rng , + output kk_tx_pwdnb , + // kk tx lvds (data) + input clk_lvds_30m , + output kk_tx_pclk_in , + output kk_tx_de_in , + output [8:0] kk_tx_cntl , + output [17:0] kk_tx_rgb , + // ************************************************************************* + // ******************************** YC LVDS ******************************** + // ************************************************************************* + input yc_rx , + output yc_tx , + // ************************************************************************* + // ****************************** RS422/RS485 ****************************** + // ************************************************************************* + // gg - high orbit + input rs422_gg_rxd , + output rs422_gg_reb , + output rs422_gg_de , + output rs422_gg_txd , + // dg - low orbit + input rs422_dg_rxd , + output rs422_dg_reb , + output rs422_dg_de , + output rs422_dg_txd , + // ts - test + input rs422_ts_rxd , + output rs422_ts_reb , + output rs422_ts_de , + output rs422_ts_txd , + // by - backup + input rs485_by_rxd , + output rs485_by_reb , + output rs485_by_de , + output rs485_by_txd , + // int_mc - internal bus timing pulse + input rs422_int_mc_rxd, + output rs422_int_mc_reb, + output rs422_int_mc_de , + output rs422_int_mc_txd, + // int_dh - internal bus navigation + input rs422_int_dh_rxd, + output rs422_int_dh_reb, + output rs422_int_dh_de , + output rs422_int_dh_txd, + // ************************************************************************* + // *************************** Inter-board Ports *************************** + // ************************************************************************* + // clocks + input clk_s2p_0_p , + input clk_s2p_0_n , + input clk_s2p_1_p , + input clk_s2p_1_n , + // low speed + inout [4:0] f1_lvds_io_p , + inout [4:0] f1_lvds_io_n , + inout [4:0] f2_lvds_io_p , + inout [4:0] f2_lvds_io_n , + // high speed + input [3:0] f1_gtx_s2p_p , + input [3:0] f1_gtx_s2p_n , + // output [3:0] f1_gtx_p2s_p , + // output [3:0] f1_gtx_p2s_n , + input [3:0] f2_gtx_s2p_p , + // input [3:0] f2_gtx_s2p_n , + // output [3:0] f2_gtx_p2s_p , + // output [3:0] f2_gtx_p2s_n , + // ************************************************************************* + // ***************************** 3.3V Debug IO ***************************** + // ************************************************************************* + // uart + output uart1_txd , + input uart1_rxd , + output uart2_txd , + input uart2_rxd , + output uart3_txd , + input uart3_rxd , + // gpio + inout debug_io_1 , + inout debug_io_2 , + inout debug_io_3 , + inout debug_io_4 , + inout debug_io_5 , + inout debug_io_6 , + // ************************************************************************* + // ******************* DDR and Fixed-io (Do NOT Modify) ******************** + // ************************************************************************* + // ddr + inout [14:0] ddr_addr , + inout [ 2:0] ddr_ba , + inout ddr_cas_n , + inout ddr_ck_n , + inout ddr_ck_p , + inout ddr_cke , + inout ddr_cs_n , + inout [ 3:0] ddr_dm , + inout [31:0] ddr_dq , + inout [ 3:0] ddr_dqs_n , + inout [ 3:0] ddr_dqs_p , + inout ddr_odt , + inout ddr_ras_n , + inout ddr_reset_n , + inout ddr_we_n , + // fixed-io + inout fixed_io_ddr_vrn , + inout fixed_io_ddr_vrp , + inout [53:0] fixed_io_mio , + inout fixed_io_ps_clk , + inout fixed_io_ps_porb , + inout fixed_io_ps_srstb +); + +//////////////////////////////////////////////////////////////////////////////// +//////////////////////////// Block Design Interface //////////////////////////// +//////////////////////////////////////////////////////////////////////////////// + +system_bd_wrapper system_bd +( + // ddr + .ddr_addr (ddr_addr ), // inout [14:0]ddr_addr + .ddr_ba (ddr_ba ), // inout [2:0]ddr_ba + .ddr_cas_n (ddr_cas_n ), // inout ddr_cas_n + .ddr_ck_n (ddr_ck_n ), // inout ddr_ck_n + .ddr_ck_p (ddr_ck_p ), // inout ddr_ck_p + .ddr_cke (ddr_cke ), // inout ddr_cke + .ddr_cs_n (ddr_cs_n ), // inout ddr_cs_n + .ddr_dm (ddr_dm ), // inout [3:0]ddr_dm + .ddr_dq (ddr_dq ), // inout [31:0]ddr_dq + .ddr_dqs_n (ddr_dqs_n ), // inout [3:0]ddr_dqs_n + .ddr_dqs_p (ddr_dqs_p ), // inout [3:0]ddr_dqs_p + .ddr_odt (ddr_odt ), // inout ddr_odt + .ddr_ras_n (ddr_ras_n ), // inout ddr_ras_n + .ddr_reset_n (ddr_reset_n ), // inout ddr_reset_n + .ddr_we_n (ddr_we_n ), // inout ddr_we_n + + // fixed-io + .fixed_io_ddr_vrn (fixed_io_ddr_vrn ), // inout fixed_io_ddr_vrn + .fixed_io_ddr_vrp (fixed_io_ddr_vrp ), // inout fixed_io_ddr_vrp + .fixed_io_mio (fixed_io_mio ), // inout [53:0]fixed_io_mio + .fixed_io_ps_clk (fixed_io_ps_clk ), // inout fixed_io_ps_clk + .fixed_io_ps_porb (fixed_io_ps_porb ), // inout fixed_io_ps_porb + .fixed_io_ps_srstb (fixed_io_ps_srstb ) // inout fixed_io_ps_srstb +); + +//////////////////////////////////////////////////////////////////////////////// +/////////////////////////////////// KK LVDS //////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +wire clk_30m; +wire clk_30m_rst; + +lvds_clk_gen lvds_clk_gen +( + // Clock out ports + .clk_out1 (clk_30m ), // output clk_out1 + // Status and control signals + .locked (~clk_30m_rst ), // output locked + // Clock in ports + .clk_in1 (clk_lvds_30m ) // input clk_in1 +); + +reg [31:0] cnt = 'b0; + +always @(posedge clk_30m) begin + if (clk_30m_rst) begin + cnt <= 'b0; + end + else begin + cnt <= cnt + 1'b1; + end +end + +ila_cnt u_ila_cnt +( + .clk (clk_30m ), // input wire clk + .probe0 (cnt ) // input wire [31:0] probe0 +); + +endmodule diff --git a/dx_pwr_basic/dx_pwr_basic.xpr b/dx_pwr_basic/dx_pwr_basic.xpr new file mode 100644 index 0000000..a85d994 --- /dev/null +++ b/dx_pwr_basic/dx_pwr_basic.xpr @@ -0,0 +1,356 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/dx_pwr_basic/system_top.xsa b/dx_pwr_basic/system_top.xsa new file mode 100644 index 0000000..5f4f20b --- /dev/null +++ b/dx_pwr_basic/system_top.xsa @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:8b2f412c1f36e9f86ba8b99ba0f304df0414f24b2a2d842d84f6965f36908973 +size 399346 diff --git a/dx_pwr_basic/vitis_classic_autobuild/.gitignore b/dx_pwr_basic/vitis_classic_autobuild/.gitignore new file mode 100644 index 0000000..3ce08f3 --- /dev/null +++ b/dx_pwr_basic/vitis_classic_autobuild/.gitignore @@ -0,0 +1,35 @@ +# keep compiled libs +!*.a + +# Buid folder +build/ + +# Xilinx tools generated files +.metadata/ +.settings/ +.wsdata/ +.Xil/ +logs/ +Packages/ +*.log* + +# System generated files +# -- macOS +.DS_Store +.AppleDouble +.LSOverride +._* + +# -- Windows +Thumbs.db +ehthumbs.db +Desktop.ini + +# -- Linux +*~ + +# IDEs and editors' files +*.idea +*.vscode +*.sublime-workspace +*.sublime-project diff --git a/dx_pwr_basic/vitis_classic_autobuild/Makefile b/dx_pwr_basic/vitis_classic_autobuild/Makefile new file mode 100644 index 0000000..e7b8a91 --- /dev/null +++ b/dx_pwr_basic/vitis_classic_autobuild/Makefile @@ -0,0 +1,8 @@ +include ../../scripts/generic_variables.mk + +PLATFORM := xilinx +CONFIG_FILE := $(PROJECT)/config.json +XILINX_VITIS_CLASSIC = y +SCRIPT_DIR = ../../scripts + +include ../../scripts/generic.mk \ No newline at end of file diff --git a/dx_pwr_basic/vitis_classic_autobuild/autobuild.bat b/dx_pwr_basic/vitis_classic_autobuild/autobuild.bat new file mode 100644 index 0000000..cf85261 --- /dev/null +++ b/dx_pwr_basic/vitis_classic_autobuild/autobuild.bat @@ -0,0 +1,32 @@ +@echo off +set "platform=xilinx" +set "pltform_ver=2024.1" +set "work_dir=%~dp0build" +set "config=%~dp0config.json" +set "tools_dir=%~dp0..\..\scripts\platform\%platform%" + +REM Set up enviroment +call "%tools_dir%\setenv.bat" "%pltform_ver%" +if "%ERRORLEVEL%" neq "0" ( + echo Error: Failed to installize enviroment. + pause >nul + exit /b 1 +) + +REM Build project +call "%tools_dir%\build.bat" "%config%" "%work_dir%" +if "%ERRORLEVEL%" neq "0" ( + echo Error: Failed to build project. + pause >nul + exit /b 1 +) + +REM Lauch SDK +call "%tools_dir%\launch.bat" "%pltform_ver%" "%work_dir%" +if "%ERRORLEVEL%" neq "0" ( + echo Error: Failed to launch SDK. + pause >nul + exit /b 1 +) + +exit /b 0 \ No newline at end of file diff --git a/dx_pwr_basic/vitis_classic_autobuild/config.json b/dx_pwr_basic/vitis_classic_autobuild/config.json new file mode 100644 index 0000000..5459b9a --- /dev/null +++ b/dx_pwr_basic/vitis_classic_autobuild/config.json @@ -0,0 +1,6 @@ +{ + "project_name": "dx_sig", + "version": "1.1.0", + "hw_design": "../system_top.xsa", + "hw_version": "dx_sig-HW-1.1.0" +} diff --git a/dx_pwr_preset.tcl b/dx_pwr_preset.tcl new file mode 100644 index 0000000..0535abd --- /dev/null +++ b/dx_pwr_preset.tcl @@ -0,0 +1,178 @@ +proc getPresetInfo {} { + return [dict create name {dx_pwr_preset} description {dx_pwr_preset} vlnv xilinx.com:ip:processing_system7:5.5 display_name {dx_pwr_preset} ] +} + +proc validate_preset {IPINST} { return true } + + +proc apply_preset {IPINST} { + return [dict create \ + CONFIG.PCW_DDR_RAM_HIGHADDR {0x1FFFFFFF} \ + CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT {3} \ + CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT {15} \ + CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT {10} \ + CONFIG.PCW_UIPARAM_DDR_CL {7} \ + CONFIG.PCW_UIPARAM_DDR_CWL {6} \ + CONFIG.PCW_UIPARAM_DDR_T_RCD {7} \ + CONFIG.PCW_UIPARAM_DDR_T_RP {7} \ + CONFIG.PCW_UIPARAM_DDR_T_RC {48.91} \ + CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN {35.0} \ + CONFIG.PCW_UIPARAM_DDR_T_FAW {40.0} \ + CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ {200} \ + CONFIG.PCW_UART_PERIPHERAL_FREQMHZ {100} \ + CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {25} \ + CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {666.666687} \ + CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {533.333374} \ + CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.158730} \ + CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {200.000000} \ + CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {100.000000} \ + CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {111.111115} \ + CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000} \ + CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \ + CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {50.000000} \ + CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {111.111115} \ + CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {111.111115} \ + CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {111.111115} \ + CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {111.111115} \ + CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {111.111115} \ + CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {111.111115} \ + CONFIG.PCW_CLK0_FREQ {50000000} \ + CONFIG.PCW_CLK1_FREQ {10000000} \ + CONFIG.PCW_CLK2_FREQ {10000000} \ + CONFIG.PCW_CLK3_FREQ {10000000} \ + CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {2} \ + CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0 {2} \ + CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0 {9} \ + CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {18} \ + CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {1} \ + CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {6} \ + CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {6} \ + CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {1} \ + CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {1} \ + CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {1} \ + CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1 {1} \ + CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1 {1} \ + CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {15} \ + CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {7} \ + CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {9} \ + CONFIG.PCW_ARMPLL_CTRL_FBDIV {40} \ + CONFIG.PCW_IOPLL_CTRL_FBDIV {54} \ + CONFIG.PCW_DDRPLL_CTRL_FBDIV {32} \ + CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1333.333} \ + CONFIG.PCW_IO_IO_PLL_FREQMHZ {1800.000} \ + CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1066.667} \ + CONFIG.PCW_UART_PERIPHERAL_VALID {1} \ + CONFIG.PCW_EN_QSPI {1} \ + CONFIG.PCW_EN_UART1 {1} \ + CONFIG.PCW_UIPARAM_DDR_ECC {Disabled} \ + CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {16 Bit} \ + CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41J256M16 RE-125} \ + CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {16 Bits} \ + CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {4096 MBits} \ + CONFIG.PCW_UIPARAM_DDR_SPEED_BIN {DDR3_1066F} \ + CONFIG.PCW_NAND_PERIPHERAL_ENABLE {0} \ + CONFIG.PCW_NAND_GRP_D8_ENABLE {0} \ + CONFIG.PCW_NOR_PERIPHERAL_ENABLE {0} \ + CONFIG.PCW_NOR_GRP_A25_ENABLE {0} \ + CONFIG.PCW_NOR_GRP_CS0_ENABLE {0} \ + CONFIG.PCW_NOR_GRP_SRAM_CS0_ENABLE {0} \ + CONFIG.PCW_NOR_GRP_CS1_ENABLE {0} \ + CONFIG.PCW_NOR_GRP_SRAM_CS1_ENABLE {0} \ + CONFIG.PCW_NOR_GRP_SRAM_INT_ENABLE {0} \ + CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1} \ + CONFIG.PCW_QSPI_QSPI_IO {MIO 1 .. 6} \ + CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {0} \ + CONFIG.PCW_QSPI_GRP_SS1_ENABLE {0} \ + CONFIG.PCW_DUAL_PARALLEL_QSPI_DATA_MODE {x8} \ + CONFIG.PCW_QSPI_GRP_IO1_ENABLE {1} \ + CONFIG.PCW_QSPI_GRP_IO1_IO {MIO 0 9 .. 13} \ + CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE {0} \ + CONFIG.PCW_QSPI_INTERNAL_HIGHADDRESS {0xFDFFFFFF} \ + CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1} \ + CONFIG.PCW_UART1_UART1_IO {MIO 48 .. 49} \ + CONFIG.PCW_UART1_GRP_FULL_ENABLE {0} \ + CONFIG.PCW_MIO_0_PULLUP {enabled} \ + CONFIG.PCW_MIO_0_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_0_DIRECTION {out} \ + CONFIG.PCW_MIO_0_SLEW {slow} \ + CONFIG.PCW_MIO_1_PULLUP {enabled} \ + CONFIG.PCW_MIO_1_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_1_DIRECTION {out} \ + CONFIG.PCW_MIO_1_SLEW {slow} \ + CONFIG.PCW_MIO_2_PULLUP {disabled} \ + CONFIG.PCW_MIO_2_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_2_DIRECTION {inout} \ + CONFIG.PCW_MIO_2_SLEW {slow} \ + CONFIG.PCW_MIO_3_PULLUP {disabled} \ + CONFIG.PCW_MIO_3_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_3_DIRECTION {inout} \ + CONFIG.PCW_MIO_3_SLEW {slow} \ + CONFIG.PCW_MIO_4_PULLUP {disabled} \ + CONFIG.PCW_MIO_4_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_4_DIRECTION {inout} \ + CONFIG.PCW_MIO_4_SLEW {slow} \ + CONFIG.PCW_MIO_5_PULLUP {disabled} \ + CONFIG.PCW_MIO_5_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_5_DIRECTION {inout} \ + CONFIG.PCW_MIO_5_SLEW {slow} \ + CONFIG.PCW_MIO_6_PULLUP {disabled} \ + CONFIG.PCW_MIO_6_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_6_DIRECTION {out} \ + CONFIG.PCW_MIO_6_SLEW {slow} \ + CONFIG.PCW_MIO_9_PULLUP {enabled} \ + CONFIG.PCW_MIO_9_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_9_DIRECTION {out} \ + CONFIG.PCW_MIO_9_SLEW {slow} \ + CONFIG.PCW_MIO_10_PULLUP {enabled} \ + CONFIG.PCW_MIO_10_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_10_DIRECTION {inout} \ + CONFIG.PCW_MIO_10_SLEW {slow} \ + CONFIG.PCW_MIO_11_PULLUP {enabled} \ + CONFIG.PCW_MIO_11_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_11_DIRECTION {inout} \ + CONFIG.PCW_MIO_11_SLEW {slow} \ + CONFIG.PCW_MIO_12_PULLUP {enabled} \ + CONFIG.PCW_MIO_12_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_12_DIRECTION {inout} \ + CONFIG.PCW_MIO_12_SLEW {slow} \ + CONFIG.PCW_MIO_13_PULLUP {enabled} \ + CONFIG.PCW_MIO_13_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_13_DIRECTION {inout} \ + CONFIG.PCW_MIO_13_SLEW {slow} \ + CONFIG.PCW_MIO_48_PULLUP {enabled} \ + CONFIG.PCW_MIO_48_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_48_DIRECTION {out} \ + CONFIG.PCW_MIO_48_SLEW {slow} \ + CONFIG.PCW_MIO_49_PULLUP {enabled} \ + CONFIG.PCW_MIO_49_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_49_DIRECTION {in} \ + CONFIG.PCW_MIO_49_SLEW {slow} \ + CONFIG.PCW_MIO_TREE_PERIPHERALS {Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#unassigned#unassigned#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#UART 1#UART 1#unassigned#unassigned#unassigned#unassigned} \ + CONFIG.PCW_MIO_TREE_SIGNALS {qspi1_ss_b#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#unassigned#unassigned#qspi1_sclk#qspi1_io[0]#qspi1_io[1]#qspi1_io[2]#qspi1_io[3]#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#tx#rx#unassigned#unassigned#unassigned#unassigned} \ + CONFIG.PCW_FPGA_FCLK0_ENABLE {1} \ + CONFIG.PCW_FPGA_FCLK1_ENABLE {0} \ + CONFIG.PCW_FPGA_FCLK2_ENABLE {0} \ + CONFIG.PCW_FPGA_FCLK3_ENABLE {0} \ + ] +} + +