feat: PS修改为演示验证版本
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/*****************************************************************************/
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/**
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* Description: Global configurations.
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*
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* Date: 2021-04-28 13:19
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* Last Editors: Fan Hao
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* Last Edit Time: [2022-05-23 20:32]
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*
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* Revisions: Rev 0.0
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* History:
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* [2021-04-28]: Initial edition.
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*
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* Copyright(c) 2024 Beijing Institute of Technology.
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* Lab of Communication and Networking
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*
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******************************************************************************/
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#ifndef __APP_CONFIG_H_
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#define __APP_CONFIG_H_
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#include "xparameters.h"
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#ifdef PLATFORM_ZYNQMP // Zynq MPSoC (Zynq UltraScale+)
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#define HSJL_GE
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#elif defined(PLATFORM_ZYNQ)
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#define HSJL_NODE
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#else
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#error Unsupported hardware...
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#endif
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/******** Software Version ********/
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#define _APP_VER 0x00010008
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#define _APP_VER_MAIN ((_APP_VER & 0xFF000000) >> 24)
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#define _APP_VER_MINOR ((_APP_VER & 0x00FF0000) >> 16)
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#define _APP_VER_PATCH (_APP_VER & 0x0000FFFF)
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/*********** Debug Info Level ************/
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// #define _DEBUG_LEVEL 1
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// 3 - print all debug info
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// 2 - print warnings and errors
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// 1 - print only errors
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// other - print nothing
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#define DATALINK_ENABLE_AUTORECONNECT
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#define DATALINK_ENABLE_AUTOTIMESYNC
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// #define DATALINK_ENABLE_BERTEST
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/************ Hardware Configs ************/
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#ifdef HSJL_GE // Zynq MPSoC (Zynq UltraScale+)
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#define CPU_CLK_HZ XPAR_CPU_CORTEXA53_0_CPU_CLK_FREQ_HZ
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#define FCLK_CLK0_HZ 100000000
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#define APP_TIMER_CLK_HZ FCLK_CLK0_HZ
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#else // Zynq-7000
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#define CPU_CLK_HZ XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
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#define APP_TIMER_CLK_HZ (CPU_CLK_HZ / 2)
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#define FCLK_CLK0_HZ 100000000
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#endif
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/********* Zynq Platform Configs **********/
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// APP Timer (for logging)
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#ifdef HSJL_GE // Zynq MPSoC (Zynq UltraScale+)
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#define APPTIMER_DEVICE_ID XPAR_AXI_TIMER_DEVICE_ID
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#define APPTIMER_INTR_ID XPAR_FABRIC_AXI_TIMER_INTERRUPT_INTR
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#else
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#define APPTIMER_DEVICE_ID XPAR_PS7_SCUTIMER_0_DEVICE_ID
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#define APPTIMER_INTR_ID XPAR_SCUTIMER_INTR
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#endif
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// Physical Layer Configs
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#define PHY_DEVICE_ID (0x01 | 0x00)
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#define PHY_BASEADDR XPAR_PHYC_BASEADDR
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#define PHY_BEAM_FORMING_ENABLE
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// -- Antenna Bram Configs
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#define PHY_ANTCONFIG_BRAM_DEVICE_ID XPAR_PHY_DATA_INTERFACE_ANT_CONFIG_BRAM_CTRL_DEVICE_ID
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#define PHY_ANTINFO_BRAM_DEVICE_ID XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_DEVICE_ID
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// -- Buffers
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#define PHY_TXBUFF_BRAM_DEVICE_ID XPAR_PHY_DATA_INTERFACE_TX_FRAME_BRAM_CTRL_DEVICE_ID
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#define PHY_RXBUFF_BRAM_DEVICE_ID XPAR_PHY_DATA_INTERFACE_RX_FRAME_BRAM_CTRL_DEVICE_ID
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// -- Xadc
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#define PHY_HW_SYSMON_DEVICE_ID XPAR_SYSTEM_MANAGEMENT_DEVICE_ID
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// -- Interrupt id
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#define PHY_INTR_ID XPAR_FABRIC_PHY_IRQ_INTR
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#define PERIODIC_5MS_INTR_ID XPAR_FABRIC_PHY_5MS_DELAY_2MS_INTR
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// Time Controller Configs
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#define TIME_CONTROLLER_BASEADDR XPAR_TMC_BASEADDR
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// System Bus Configs
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#define SYSBUS_BASE_ADDR XPAR_SYSTEMBUS_BASEADDR
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#define SYSBUS_TX_INTR_ID XPAR_FABRIC_SYSTEMBUS_TX_DONE_INTR
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#define SYSBUS_RX_INTR_ID XPAR_FABRIC_SYSTEMBUS_RX_DONE_INTR
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// INTC configis
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#define INTC_DEVICE_ID XPAR_SCUGIC_0_DEVICE_ID
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/********* Hardware Configurations **********/
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#ifdef HSJL_GE // Zynq MPSoC (Zynq UltraScale+)
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#define RFSOC
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#define LMK04828
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//#define LMX2594_ADC
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//#define LMX2594_DAC
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#define RFDC_DEVICE_ID XPAR_XRFDC_0_DEVICE_ID
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#else
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#define AD9361_REG
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//#define AD9361_API
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#define AD9528
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//#define AD9653
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//#define AD9694
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#endif
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// AD9361 Configuration
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#define SPI_INTERFACE_SPI_ENGINE
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#define HAVE_SPLIT_GAIN_TABLE 1 /* only set to 0 in case split_gain_table_mode_enable = 0*/
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#define HAVE_TDD_SYNTH_TABLE 1 /* only set to 0 in case split_gain_table_mode_enable = 0*/
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#define AD9361_DEVICE 1 /* set it 1 if AD9361 device is used, 0 otherwise */
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#define AD9364_DEVICE 0 /* set it 1 if AD9364 device is used, 0 otherwise */
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#define AD9363A_DEVICE 0 /* set it 1 if AD9363A device is used, 0 otherwise */
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#define HAVE_VERBOSE_MESSAGES /* Recommended during development prints errors and warnings */
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// #define HAVE_DEBUG_MESSAGES /* For Debug purposes only */
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// AD9361 GPIO Configurations
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#define AD9361_GPIO_DEVICE_ID 0
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#define AD9361_GPIO_OFFSET 54
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#define AD9361_GPIO_INPUT 0
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#define AD9361_GPIO_OUTPUT 1
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#define AD9361_GPIO_DISABLE 0
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#define AD9361_GPIO_ENABLE 1
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// -- AD9361-1 SPI Engine Configuration
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#define AD9361_SPI_DEVICE_ID 0
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#define AD9361_SPI_ENGINE_REF_CLK FCLK_CLK0_HZ
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#define AD9361_SPI_ENGINE_MAX_SPEED 5000000
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#define AD9361_SPI_ENGINE_BASEADDR XPAR_AXI_SPI_ENGINE_AXI_SPI_ENGINE_BASEADDR
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#define AD9361_SPI_ENGINE_DATA_WIDTH 8
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#define AD9361_SPI_ENGINE_CS_DELAY 3
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#define AD9361_TIMEOUT_TH 2000
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#define AD9361_1_SPI_CS 0x01
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#define AD9361_2_SPI_CS 0x02
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#define AD9361_2_TIMEOUT_TH 2000
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// -- AD9361-1 GPIO
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#define AD9361_1_TXNRX (AD9361_GPIO_OFFSET + 6)
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#define AD9361_1_ENABLE (AD9361_GPIO_OFFSET + 7)
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#define AD9361_1_EN_AGC (AD9361_GPIO_OFFSET + 8)
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#define AD9361_1_RESET_B (AD9361_GPIO_OFFSET + 9)
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#define AD9361_1_CTRL_OUT0 (AD9361_GPIO_OFFSET + 10)
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#define AD9361_1_CTRL_OUT1 (AD9361_GPIO_OFFSET + 11)
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#define AD9361_1_CTRL_OUT2 (AD9361_GPIO_OFFSET + 12)
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#define AD9361_1_CTRL_OUT3 (AD9361_GPIO_OFFSET + 13)
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#define AD9361_1_CTRL_OUT4 (AD9361_GPIO_OFFSET + 14)
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#define AD9361_1_CTRL_OUT5 (AD9361_GPIO_OFFSET + 15)
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#define AD9361_1_CTRL_OUT6 (AD9361_GPIO_OFFSET + 16)
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#define AD9361_1_CTRL_OUT7 (AD9361_GPIO_OFFSET + 17)
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#define AD9361_1_CTRL_IN0 (AD9361_GPIO_OFFSET + 18)
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#define AD9361_1_CTRL_IN1 (AD9361_GPIO_OFFSET + 19)
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#define AD9361_1_CTRL_IN2 (AD9361_GPIO_OFFSET + 20)
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#define AD9361_1_CTRL_IN3 (AD9361_GPIO_OFFSET + 21)
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// -- AD9361-2 GPIO
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#define AD9361_2_TXNRX (AD9361_GPIO_OFFSET + 22)
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#define AD9361_2_ENABLE (AD9361_GPIO_OFFSET + 23)
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#define AD9361_2_EN_AGC (AD9361_GPIO_OFFSET + 24)
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#define AD9361_2_RESET_B (AD9361_GPIO_OFFSET + 25)
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#define AD9361_2_CTRL_OUT0 (AD9361_GPIO_OFFSET + 26)
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#define AD9361_2_CTRL_OUT1 (AD9361_GPIO_OFFSET + 27)
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#define AD9361_2_CTRL_OUT2 (AD9361_GPIO_OFFSET + 28)
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#define AD9361_2_CTRL_OUT3 (AD9361_GPIO_OFFSET + 29)
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#define AD9361_2_CTRL_OUT4 (AD9361_GPIO_OFFSET + 30)
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#define AD9361_2_CTRL_OUT5 (AD9361_GPIO_OFFSET + 31)
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#define AD9361_2_CTRL_OUT6 (AD9361_GPIO_OFFSET + 32)
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#define AD9361_2_CTRL_OUT7 (AD9361_GPIO_OFFSET + 33)
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#define AD9361_2_CTRL_IN0 (AD9361_GPIO_OFFSET + 34)
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#define AD9361_2_CTRL_IN1 (AD9361_GPIO_OFFSET + 35)
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#define AD9361_2_CTRL_IN2 (AD9361_GPIO_OFFSET + 36)
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#define AD9361_2_CTRL_IN3 (AD9361_GPIO_OFFSET + 37)
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// AD9361-Status Code
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#define AD9361_SYNC (AD9361_GPIO_OFFSET + 38)
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#define AD9361_RX_FIFO_RST (AD9361_GPIO_OFFSET + 39)
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#define AD9361_1_CAL_START (AD9361_GPIO_OFFSET + 40)
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#define AD9361_2_CAL_START (AD9361_GPIO_OFFSET + 41)
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#define AD9361_RECAL (AD9361_GPIO_OFFSET + 42)
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#define AD9361_TX_SWITCH (AD9361_GPIO_OFFSET + 43)
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#define AD9361_1_CAL_DONE (AD9361_GPIO_OFFSET + 44)
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#define AD9361_2_CAL_DONE (AD9361_GPIO_OFFSET + 45)
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#define AD9361_CAL_RESULT (AD9361_GPIO_OFFSET + 46)
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typedef enum
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{
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TX_FREQ_125,
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TX_FREQ_126,
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TX_FREQ_4125
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} ad9361TxFreq;
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// HMC7044 Configurations
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#define HMC7044_GPIO_DEVICE_ID 0
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#define HMC7044_GPIO_OFFSET 54
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#define HMC7044_RESET (HMC7044_GPIO_OFFSET + 0)
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#define HMC7044_SYNC (HMC7044_GPIO_OFFSET + 1)
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#define HMC7044_GPIO_0 (HMC7044_GPIO_OFFSET + 2)
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#define HMC7044_GPIO_1 (HMC7044_GPIO_OFFSET + 3)
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#define HMC7044_GPIO_2 (HMC7044_GPIO_OFFSET + 4)
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#define HMC7044_GPIO_3 (HMC7044_GPIO_OFFSET + 5)
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// -- HMC7044 SPI Engine Configuration
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#define HMC7044_SPI_DEVICE_ID 0
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#define HMC7044_SPI_ENGINE_REF_CLK FCLK_CLK0_HZ
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#define HMC7044_SPI_ENGINE_MAX_SPEED 5000000
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#define HMC7044_SPI_ENGINE_BASEADDR XPAR_AXI_SPI_ENGINE_AXI_SPI_ENGINE_BASEADDR
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#define HMC7044_SPI_ENGINE_DATA_WIDTH 8
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#define HMC7044_SPI_ENGINE_CS_DELAY 3
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#define HMC7044_SPI_CS_HMC7044 0x00
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// AD9528 Configurations
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#define AD9528_GPIO_DEVICE_ID 0
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#define AD9528_GPIO_OFFSET 54
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#define AD9528_RESETB (AD9528_GPIO_OFFSET+0)
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#define AD9528_SYSREF_REQ (AD9528_GPIO_OFFSET+1)
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#define AD9528_STATUS_0 (AD9528_GPIO_OFFSET+2)
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#define AD9528_STATUS_1 (AD9528_GPIO_OFFSET+3)
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// -- AD9528 SPI Engine Configuration
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#define AD9528_SPI_DEVICE_ID 0
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#define AD9528_SPI_ENGINE_REF_CLK FCLK_CLK0_HZ
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#define AD9528_SPI_ENGINE_MAX_SPEED 5000000
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#define AD9528_SPI_ENGINE_BASEADDR XPAR_AXI_SPI_ENGINE_AXI_SPI_ENGINE_BASEADDR
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#define AD9528_SPI_ENGINE_DATA_WIDTH 8
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#define AD9528_SPI_ENGINE_CS_DELAY 3
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#define AD9528_SPI_CS 0x00
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// LMK04828 Configurations
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#define LMK04828_GPIO_DEVICE_ID 0
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#define LMK04828_GPIO_OFFSET 54
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// -- LMK04828 SPI Engine Configuration
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#define LMK04828_SPI_DEVICE_ID 0
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#define LMK04828_SPI_ENGINE_REF_CLK FCLK_CLK0_HZ
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#define LMK04828_SPI_ENGINE_MAX_SPEED 5000000
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#define LMK04828_SPI_ENGINE_BASEADDR XPAR_AXI_SPI_ENGINE_AXI_SPI_ENGINE_BASEADDR
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#define LMK04828_SPI_ENGINE_DATA_WIDTH 8
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#define LMK04828_SPI_ENGINE_CS_DELAY 3
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#define LMK04828_SPI_CS 0x00
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// LMX2594_ADC Configurations
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#define LMX2594_ADC_GPIO_DEVICE_ID 0
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#define LMX2594_ADC_GPIO_OFFSET 54
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// -- LMX2594_ADC SPI Engine Configuration
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#define LMX2594_ADC_SPI_DEVICE_ID 0
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#define LMX2594_ADC_SPI_ENGINE_REF_CLK FCLK_CLK0_HZ
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#define LMX2594_ADC_SPI_ENGINE_MAX_SPEED 5000000
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#define LMX2594_ADC_SPI_ENGINE_BASEADDR XPAR_AXI_SPI_ENGINE_AXI_SPI_ENGINE_BASEADDR
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#define LMX2594_ADC_SPI_ENGINE_DATA_WIDTH 8
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#define LMX2594_ADC_SPI_ENGINE_CS_DELAY 3
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#define LMX2594_ADC_SPI_CS 0x01
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// LMX2594_DAC Configurations
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#define LMX2594_DAC_GPIO_DEVICE_ID 0
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#define LMX2594_DAC_GPIO_OFFSET 54
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// -- LMX2594_DAC SPI Engine Configuration
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#define LMX2594_DAC_SPI_DEVICE_ID 0
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#define LMX2594_DAC_SPI_ENGINE_REF_CLK FCLK_CLK0_HZ
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#define LMX2594_DAC_SPI_ENGINE_MAX_SPEED 5000000
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#define LMX2594_DAC_SPI_ENGINE_BASEADDR XPAR_AXI_SPI_ENGINE_AXI_SPI_ENGINE_BASEADDR
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#define LMX2594_DAC_SPI_ENGINE_DATA_WIDTH 8
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#define LMX2594_DAC_SPI_ENGINE_CS_DELAY 3
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#define LMX2594_DAC_SPI_CS 0x02
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// AD9653 Configurations
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#define AD9653_GPIO_DEVICE_ID 0
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#define AD9653_GPIO_OFFSET 54
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#define AD9653_POWR_DOWN (AD9653_GPIO_OFFSET+0)
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// -- AD9653 SPI Engine Configuration
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#define AD9653_SPI_DEVICE_ID 0
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#define AD9653_SPI_ENGINE_REF_CLK FCLK_CLK0_HZ
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#define AD9653_SPI_ENGINE_MAX_SPEED 5000000
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#define AD9653_SPI_ENGINE_BASEADDR XPAR_AXI_SPI_ENGINE_AXI_SPI_ENGINE_BASEADDR
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#define AD9653_SPI_ENGINE_DATA_WIDTH 8
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#define AD9653_SPI_ENGINE_CS_DELAY 3
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#define AD9653_SPI_CS 0x03
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// AD9694 Configurations
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#define AD9694_GPIO_DEVICE_ID 0
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#define AD9694_GPIO_OFFSET 54
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// -- AD9694 SPI Engine Configuration
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#define AD9694_SPI_DEVICE_ID 0
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#define AD9694_SPI_ENGINE_REF_CLK FCLK_CLK0_HZ
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#define AD9694_SPI_ENGINE_MAX_SPEED 5000000
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#define AD9694_SPI_ENGINE_BASEADDR XPAR_AXI_SPI_ENGINE_AXI_SPI_ENGINE_BASEADDR
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#define AD9694_SPI_ENGINE_DATA_WIDTH 8
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#define AD9694_SPI_ENGINE_CS_DELAY 3
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#define AD9694_SPI_CS 0x03
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// Configuration Check
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#if defined(PHY_BEAM_SET_PRESET) && !defined(PHY_BEAM_FORMING_ENABLE)
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#define PHY_BEAM_FORMING_ENABLE
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#warning To impliment beam scan must enable beam forming...
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#endif
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#if defined(DATALINK_ENABLE_BERTEST)
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#if !defined(DATALINK_ENABLE_AUTOTIMESYNC)
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#warning To enbale bit error rate test, auto time-sync should be enabled...
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#endif
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#endif
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#endif //__APP_CONFIG_H_
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