feat: 更新软件版本至2024.1
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# sjl_2z7100_ad9528_2ad9361
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## Timing Assertions Section
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## Physical Constraints Section
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# Clocks
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set_property -dict {PACKAGE_PIN AC28 IOSTANDARD LVDS_25 } [get_ports refclk_1_p ] ;# F1_REFCLK1_P
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set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVDS } [get_ports refclk_2_p ] ;# F1_REFCLK2_P
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set_property -dict {PACKAGE_PIN AD10 } [get_ports gtclk_109_p ] ;# F1_GTCLK0_P
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set_property -dict {PACKAGE_PIN AA8 } [get_ports gtclk_110_p ] ;# F1_GTCLK1_P
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set_property -dict {PACKAGE_PIN N8 } [get_ports gtclk_112_p ] ;# F1_GTCLK2_P
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set_property -dict {PACKAGE_PIN F5 IOSTANDARD LVCMOS18} [get_ports ad9361_1_buffer_clk ] ;# AD9361_1_CLK_OUT
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set_property -dict {PACKAGE_PIN H9 IOSTANDARD LVCMOS18} [get_ports ad9361_2_buffer_clk ] ;# AD9361_2_CLK_OUT
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# AD9528 Interface
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set_property -dict {PACKAGE_PIN AG21 IOSTANDARD LVCMOS33} [get_ports ad9528_spi_csn ] ;# AD9528_SPI_CSB
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set_property -dict {PACKAGE_PIN AJ25 IOSTANDARD LVCMOS33} [get_ports ad9528_spi_clk ] ;# AD9528_SPI_SCLK
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set_property -dict {PACKAGE_PIN AK25 IOSTANDARD LVCMOS33} [get_ports ad9528_spi_mosi ] ;# AD9528_SPI_SDI
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set_property -dict {PACKAGE_PIN AK22 IOSTANDARD LVCMOS33} [get_ports ad9528_spi_miso ] ;# AD9528_SPI_SDO
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set_property -dict {PACKAGE_PIN AJ23 IOSTANDARD LVCMOS33} [get_ports ad9528_status[0] ] ;# AD9528_STATUS0
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set_property -dict {PACKAGE_PIN AJ24 IOSTANDARD LVCMOS33} [get_ports ad9528_status[1] ] ;# AD9528_STATUS1
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set_property -dict {PACKAGE_PIN AH23 IOSTANDARD LVCMOS33} [get_ports ad9528_reset_b ] ;# AD9528_RESETB
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set_property -dict {PACKAGE_PIN AH24 IOSTANDARD LVCMOS33} [get_ports ad9528_sysref_req ] ;# AD9528_SYSREF_REQ
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# AD9361-1 Interface
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set_property -dict {PACKAGE_PIN G5 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data_clk ] ;# AD9361_1_DATA_CLK_P
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set_property -dict {PACKAGE_PIN F4 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_frame ] ;# AD9361_1_RX_FRAME_P
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set_property -dict {PACKAGE_PIN E2 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[0] ] ;# AD9361_1_P0D00_TXD0_N
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set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[1] ] ;# AD9361_1_P0D01_TXD0_P
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set_property -dict {PACKAGE_PIN D3 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[2] ] ;# AD9361_1_P0D02_TXD1_N
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set_property -dict {PACKAGE_PIN D4 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[3] ] ;# AD9361_1_P0D03_TXD1_P
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set_property -dict {PACKAGE_PIN C3 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[4] ] ;# AD9361_1_P0D04_TXD2_N
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set_property -dict {PACKAGE_PIN C4 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[5] ] ;# AD9361_1_P0D05_TXD2_P
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set_property -dict {PACKAGE_PIN B4 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[6] ] ;# AD9361_1_P0D06_TXD3_N
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set_property -dict {PACKAGE_PIN B5 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[7] ] ;# AD9361_1_P0D07_TXD3_P
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set_property -dict {PACKAGE_PIN A4 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[8] ] ;# AD9361_1_P0D08_TXD4_N
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set_property -dict {PACKAGE_PIN A5 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[9] ] ;# AD9361_1_P0D09_TXD4_P
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set_property -dict {PACKAGE_PIN D1 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[10] ] ;# AD9361_1_P0D10_TXD5_N
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set_property -dict {PACKAGE_PIN E1 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[11] ] ;# AD9361_1_P0D11_TXD5_P
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set_property -dict {PACKAGE_PIN H4 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_fb_clk ] ;# AD9361_1_FB_CLK_P
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set_property -dict {PACKAGE_PIN E6 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_frame ] ;# AD9361_1_TX_FRAME_P
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set_property -dict {PACKAGE_PIN K2 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[0] ] ;# AD9361_1_P1D00_RXD0_N
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set_property -dict {PACKAGE_PIN K3 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[1] ] ;# AD9361_1_P1D01_RXD0_P
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set_property -dict {PACKAGE_PIN K1 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[2] ] ;# AD9361_1_P1D02_RXD1_N
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set_property -dict {PACKAGE_PIN L1 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[3] ] ;# AD9361_1_P1D03_RXD1_P
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set_property -dict {PACKAGE_PIN L2 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[4] ] ;# AD9361_1_P1D04_RXD2_N
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set_property -dict {PACKAGE_PIN L3 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[5] ] ;# AD9361_1_P1D05_RXD2_P
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set_property -dict {PACKAGE_PIN J3 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[6] ] ;# AD9361_1_P1D06_RXD3_N
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set_property -dict {PACKAGE_PIN J4 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[7] ] ;# AD9361_1_P1D07_RXD3_P
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set_property -dict {PACKAGE_PIN J5 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[8] ] ;# AD9361_1_P1D08_RXD4_N
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set_property -dict {PACKAGE_PIN K5 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[9] ] ;# AD9361_1_P1D09_RXD4_P
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set_property -dict {PACKAGE_PIN J6 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[10] ] ;# AD9361_1_P1D10_RXD5_N
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set_property -dict {PACKAGE_PIN K6 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[11] ] ;# AD9361_1_P1D11_RXD5_P
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set_property -dict {PACKAGE_PIN A13 IOSTANDARD LVCMOS18} [get_ports ad9361_1_spi_clk ] ;# AD9361_1_SPI_CLK
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set_property -dict {PACKAGE_PIN A12 IOSTANDARD LVCMOS18} [get_ports ad9361_1_spi_csn ] ;# AD9361_1_SPI_ENB
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set_property -dict {PACKAGE_PIN F17 IOSTANDARD LVCMOS18} [get_ports ad9361_1_spi_mosi ] ;# AD9361_1_SPI_DI
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set_property -dict {PACKAGE_PIN G16 IOSTANDARD LVCMOS18} [get_ports ad9361_1_spi_miso ] ;# AD9361_1_SPI_DO
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set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVCMOS18} [get_ports ad9361_1_reset_b ] ;# AD9361_1_RESETB
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set_property -dict {PACKAGE_PIN B15 IOSTANDARD LVCMOS18} [get_ports ad9361_1_en_agc ] ;# AD9361_1_EN_AGC
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set_property -dict {PACKAGE_PIN A14 IOSTANDARD LVCMOS18} [get_ports ad9361_1_enable ] ;# AD9361_1_ENABLE
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set_property -dict {PACKAGE_PIN H6 IOSTANDARD LVCMOS18} [get_ports ad9361_1_txnrx ] ;# AD9361_1_TXNRX
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set_property -dict {PACKAGE_PIN C16 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_in[0] ] ;# AD9361_1_CTRL_IN0
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set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_in[1] ] ;# AD9361_1_CTRL_IN1
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set_property -dict {PACKAGE_PIN B14 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_in[2] ] ;# AD9361_1_CTRL_IN2
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set_property -dict {PACKAGE_PIN B12 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_in[3] ] ;# AD9361_1_CTRL_IN3
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set_property -dict {PACKAGE_PIN B11 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[0] ] ;# AD9361_1_CTRL_OUT0
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set_property -dict {PACKAGE_PIN C14 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[1] ] ;# AD9361_1_CTRL_OUT1
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set_property -dict {PACKAGE_PIN C13 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[2] ] ;# AD9361_1_CTRL_OUT2
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set_property -dict {PACKAGE_PIN C12 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[3] ] ;# AD9361_1_CTRL_OUT3
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set_property -dict {PACKAGE_PIN A15 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[4] ] ;# AD9361_1_CTRL_OUT4
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set_property -dict {PACKAGE_PIN D16 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[5] ] ;# AD9361_1_CTRL_OUT5
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set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[6] ] ;# AD9361_1_CTRL_OUT6
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set_property -dict {PACKAGE_PIN E17 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[7] ] ;# AD9361_1_CTRL_OUT7
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# AD9361-2 Interface
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set_property -dict {PACKAGE_PIN D9 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data_clk ] ;# AD9361_2_DATA_CLK_P
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set_property -dict {PACKAGE_PIN E7 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_frame ] ;# AD9361_2_RX_FRAME_P
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set_property -dict {PACKAGE_PIN B6 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[0] ] ;# AD9361_2_P0D00_TXD0_N
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set_property -dict {PACKAGE_PIN C6 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[1] ] ;# AD9361_2_P0D01_TXD0_P
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set_property -dict {PACKAGE_PIN B7 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[2] ] ;# AD9361_2_P0D02_TXD1_N
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set_property -dict {PACKAGE_PIN C7 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[3] ] ;# AD9361_2_P0D03_TXD1_P
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set_property -dict {PACKAGE_PIN A9 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[4] ] ;# AD9361_2_P0D04_TXD2_N
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set_property -dict {PACKAGE_PIN B9 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[5] ] ;# AD9361_2_P0D05_TXD2_P
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set_property -dict {PACKAGE_PIN A10 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[6] ] ;# AD9361_2_P0D06_TXD3_N
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set_property -dict {PACKAGE_PIN B10 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[7] ] ;# AD9361_2_P0D07_TXD3_P
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set_property -dict {PACKAGE_PIN D11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[8] ] ;# AD9361_2_P0D08_TXD4_N
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set_property -dict {PACKAGE_PIN E11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[9] ] ;# AD9361_2_P0D09_TXD4_P
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set_property -dict {PACKAGE_PIN C8 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[10] ] ;# AD9361_2_P0D10_TXD5_N
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set_property -dict {PACKAGE_PIN C9 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[11] ] ;# AD9361_2_P0D11_TXD5_P
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set_property -dict {PACKAGE_PIN G10 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_fb_clk ] ;# AD9361_2_FB_CLK_P
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set_property -dict {PACKAGE_PIN F8 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_frame ] ;# AD9361_2_TX_FRAME_P
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set_property -dict {PACKAGE_PIN G7 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[0] ] ;# AD9361_2_P1D00_RXD0_N
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set_property -dict {PACKAGE_PIN H7 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[1] ] ;# AD9361_2_P1D01_RXD0_P
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set_property -dict {PACKAGE_PIN H8 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[2] ] ;# AD9361_2_P1D02_RXD1_N
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set_property -dict {PACKAGE_PIN J8 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[3] ] ;# AD9361_2_P1D03_RXD1_P
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set_property -dict {PACKAGE_PIN J9 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[4] ] ;# AD9361_2_P1D04_RXD2_N
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set_property -dict {PACKAGE_PIN J10 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[5] ] ;# AD9361_2_P1D05_RXD2_P
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set_property -dict {PACKAGE_PIN K7 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[6] ] ;# AD9361_2_P1D06_RXD3_N
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set_property -dict {PACKAGE_PIN L7 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[7] ] ;# AD9361_2_P1D07_RXD3_P
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set_property -dict {PACKAGE_PIN K8 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[8] ] ;# AD9361_2_P1D08_RXD4_N
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set_property -dict {PACKAGE_PIN L8 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[9] ] ;# AD9361_2_P1D09_RXD4_P
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set_property -dict {PACKAGE_PIN H11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[10] ] ;# AD9361_2_P1D10_RXD5_N
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set_property -dict {PACKAGE_PIN J11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[11] ] ;# AD9361_2_P1D11_RXD5_P
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set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS18} [get_ports ad9361_2_spi_clk ] ;# AD9361_2_SPI_CLK
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set_property -dict {PACKAGE_PIN M16 IOSTANDARD LVCMOS18} [get_ports ad9361_2_spi_csn ] ;# AD9361_2_SPI_ENB
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set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS18} [get_ports ad9361_2_spi_mosi ] ;# AD9361_2_SPI_DI
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set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVCMOS18} [get_ports ad9361_2_spi_miso ] ;# AD9361_2_SPI_DO
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set_property -dict {PACKAGE_PIN H16 IOSTANDARD LVCMOS18} [get_ports ad9361_2_reset_b ] ;# AD9361_2_RESETB
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set_property -dict {PACKAGE_PIN J13 IOSTANDARD LVCMOS18} [get_ports ad9361_2_en_agc ] ;# AD9361_2_EN_AGC
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set_property -dict {PACKAGE_PIN H13 IOSTANDARD LVCMOS18} [get_ports ad9361_2_enable ] ;# AD9361_2_ENABLE
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set_property -dict {PACKAGE_PIN H12 IOSTANDARD LVCMOS18} [get_ports ad9361_2_txnrx ] ;# AD9361_2_TXNRX
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set_property -dict {PACKAGE_PIN E13 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_in[0] ] ;# AD9361_2_CTRL_IN0
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set_property -dict {PACKAGE_PIN E12 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_in[1] ] ;# AD9361_2_CTRL_IN1
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set_property -dict {PACKAGE_PIN F12 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_in[2] ] ;# AD9361_2_CTRL_IN2
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set_property -dict {PACKAGE_PIN G14 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_in[3] ] ;# AD9361_2_CTRL_IN3
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set_property -dict {PACKAGE_PIN C11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[0] ] ;# AD9361_2_CTRL_OUT0
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set_property -dict {PACKAGE_PIN L14 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[1] ] ;# AD9361_2_CTRL_OUT1
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set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[2] ] ;# AD9361_2_CTRL_OUT2
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set_property -dict {PACKAGE_PIN G12 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[3] ] ;# AD9361_2_CTRL_OUT3
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set_property -dict {PACKAGE_PIN F13 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[4] ] ;# AD9361_2_CTRL_OUT4
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set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[5] ] ;# AD9361_2_CTRL_OUT5
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set_property -dict {PACKAGE_PIN L15 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[6] ] ;# AD9361_2_CTRL_OUT6
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set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[7] ] ;# AD9361_2_CTRL_OUT7
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# Inter-FPGA Ports
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set_property -dict {PACKAGE_PIN Y30 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[0] ] ;# LVDS_IO_GRP0_00P
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set_property -dict {PACKAGE_PIN AC29 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[1] ] ;# LVDS_IO_GRP0_01P
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set_property -dict {PACKAGE_PIN AA27 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[2] ] ;# LVDS_IO_GRP0_02P
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set_property -dict {PACKAGE_PIN Y28 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[3] ] ;# LVDS_IO_GRP0_03P
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set_property -dict {PACKAGE_PIN AB29 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[4] ] ;# LVDS_IO_GRP0_04P
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set_property -dict {PACKAGE_PIN AE27 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[5] ] ;# LVDS_IO_GRP0_05P
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set_property -dict {PACKAGE_PIN AB27 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[6] ] ;# LVDS_IO_GRP0_06P
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set_property -dict {PACKAGE_PIN Y26 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[7] ] ;# LVDS_IO_GRP0_07P
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set_property -dict {PACKAGE_PIN AE25 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[8] ] ;# LVDS_IO_GRP0_08P
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set_property -dict {PACKAGE_PIN AK27 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[9] ] ;# LVDS_IO_GRP0_09P
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set_property -dict {PACKAGE_PIN AF29 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[10] ] ;# LVDS_IO_GRP0_10P
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set_property -dict {PACKAGE_PIN AJ28 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[11] ] ;# LVDS_IO_GRP0_11P
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set_property -dict {PACKAGE_PIN AJ26 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[12] ] ;# LVDS_IO_GRP0_12P
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set_property -dict {PACKAGE_PIN AJ30 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[13] ] ;# LVDS_IO_GRP0_13P
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set_property -dict {PACKAGE_PIN AB25 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[14] ] ;# LVDS_IO_GRP0_14P
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set_property -dict {PACKAGE_PIN AG26 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[15] ] ;# LVDS_IO_GRP0_15P
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set_property -dict {PACKAGE_PIN AH26 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[16] ] ;# LVDS_IO_GRP0_16P
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set_property -dict {PACKAGE_PIN AF30 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[17] ] ;# LVDS_IO_GRP0_17P
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set_property -dict {PACKAGE_PIN AD30 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[18] ] ;# LVDS_IO_GRP0_18P
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set_property -dict {PACKAGE_PIN AH28 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[19] ] ;# LVDS_IO_GRP0_19P
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set_property -dict {PACKAGE_PIN AD25 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[20] ] ;# LVDS_IO_GRP0_20P
|
||||
set_property -dict {PACKAGE_PIN AE28 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[21] ] ;# LVDS_IO_GRP0_21P
|
||||
set_property -dict {PACKAGE_PIN AC26 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[22] ] ;# LVDS_IO_GRP0_22P
|
||||
|
||||
set_property -dict {PACKAGE_PIN T30 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[0] ] ;# LVDS_IO_GRP1_00P
|
||||
set_property -dict {PACKAGE_PIN R28 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[1] ] ;# LVDS_IO_GRP1_01P
|
||||
set_property -dict {PACKAGE_PIN U22 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[2] ] ;# LVDS_IO_GRP1_02P
|
||||
set_property -dict {PACKAGE_PIN T29 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[3] ] ;# LVDS_IO_GRP1_03P
|
||||
set_property -dict {PACKAGE_PIN P30 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[4] ] ;# LVDS_IO_GRP1_04P
|
||||
set_property -dict {PACKAGE_PIN N26 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[5] ] ;# LVDS_IO_GRP1_05P
|
||||
set_property -dict {PACKAGE_PIN N28 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[6] ] ;# LVDS_IO_GRP1_06P
|
||||
set_property -dict {PACKAGE_PIN N29 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[7] ] ;# LVDS_IO_GRP1_07P
|
||||
set_property -dict {PACKAGE_PIN V27 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[8] ] ;# LVDS_IO_GRP1_08P
|
||||
set_property -dict {PACKAGE_PIN P25 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[9] ] ;# LVDS_IO_GRP1_09P
|
||||
set_property -dict {PACKAGE_PIN R25 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[10] ] ;# LVDS_IO_GRP1_10P
|
||||
set_property -dict {PACKAGE_PIN W29 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[11] ] ;# LVDS_IO_GRP1_11P
|
||||
set_property -dict {PACKAGE_PIN R27 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[12] ] ;# LVDS_IO_GRP1_12P
|
||||
set_property -dict {PACKAGE_PIN V23 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[13] ] ;# LVDS_IO_GRP1_13P
|
||||
set_property -dict {PACKAGE_PIN T24 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[14] ] ;# LVDS_IO_GRP1_14P
|
||||
set_property -dict {PACKAGE_PIN U24 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[15] ] ;# LVDS_IO_GRP1_15P
|
||||
set_property -dict {PACKAGE_PIN T22 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[16] ] ;# LVDS_IO_GRP1_16P
|
||||
set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[17] ] ;# LVDS_IO_GRP1_17P
|
||||
set_property -dict {PACKAGE_PIN V28 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[18] ] ;# LVDS_IO_GRP1_18P
|
||||
set_property -dict {PACKAGE_PIN W25 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[19] ] ;# LVDS_IO_GRP1_19P
|
||||
set_property -dict {PACKAGE_PIN P23 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[20] ] ;# LVDS_IO_GRP1_20P
|
||||
set_property -dict {PACKAGE_PIN U25 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[21] ] ;# LVDS_IO_GRP1_21P
|
||||
set_property -dict {PACKAGE_PIN R22 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[22] ] ;# LVDS_IO_GRP1_22P
|
||||
|
||||
set_property -dict {PACKAGE_PIN AH10 } [get_ports if_gtx_rxp[0] ] ;# GTX_F1R_F2T_00P
|
||||
set_property -dict {PACKAGE_PIN AJ8 } [get_ports if_gtx_rxp[1] ] ;# GTX_F1R_F2T_01P
|
||||
set_property -dict {PACKAGE_PIN AG8 } [get_ports if_gtx_rxp[2] ] ;# GTX_F1R_F2T_02P
|
||||
set_property -dict {PACKAGE_PIN AE8 } [get_ports if_gtx_rxp[3] ] ;# GTX_F1R_F2T_03P
|
||||
set_property -dict {PACKAGE_PIN AH6 } [get_ports if_gtx_rxp[4] ] ;# GTX_F1R_F2T_04P
|
||||
set_property -dict {PACKAGE_PIN AG4 } [get_ports if_gtx_rxp[5] ] ;# GTX_F1R_F2T_05P
|
||||
set_property -dict {PACKAGE_PIN AF6 } [get_ports if_gtx_rxp[6] ] ;# GTX_F1R_F2T_06P
|
||||
set_property -dict {PACKAGE_PIN AD6 } [get_ports if_gtx_rxp[7] ] ;# GTX_F1R_F2T_07P
|
||||
|
||||
# set_property -dict {PACKAGE_PIN AK10 } [get_ports if_gtx_txp[0] ] ;# GTX_F1T_F2R_00P
|
||||
# set_property -dict {PACKAGE_PIN AK6 } [get_ports if_gtx_txp[1] ] ;# GTX_F1T_F2R_01P
|
||||
# set_property -dict {PACKAGE_PIN AJ4 } [get_ports if_gtx_txp[2] ] ;# GTX_F1T_F2R_02P
|
||||
# set_property -dict {PACKAGE_PIN AK2 } [get_ports if_gtx_txp[3] ] ;# GTX_F1T_F2R_03P
|
||||
# set_property -dict {PACKAGE_PIN AH2 } [get_ports if_gtx_txp[4] ] ;# GTX_F1T_F2R_04P
|
||||
# set_property -dict {PACKAGE_PIN AF2 } [get_ports if_gtx_txp[5] ] ;# GTX_F1T_F2R_05P
|
||||
# set_property -dict {PACKAGE_PIN AE4 } [get_ports if_gtx_txp[6] ] ;# GTX_F1T_F2R_06P
|
||||
# set_property -dict {PACKAGE_PIN AD2 } [get_ports if_gtx_txp[7] ] ;# GTX_F1T_F2R_07P
|
||||
|
||||
# Inter-board Ports
|
||||
set_property -dict {PACKAGE_PIN V6 } [get_ports ib_gtx_tt2zw_p[0] ] ;# SRIO_1_TT2ZW_P
|
||||
set_property -dict {PACKAGE_PIN U4 } [get_ports ib_gtx_tt2zw_p[1] ] ;# SRIO_2_TT2ZW_P
|
||||
|
||||
# set_property -dict {PACKAGE_PIN T2 } [get_ports ib_gtx_zw2tt_p[0] ] ;# SRIO_1_ZW2TT_P
|
||||
# set_property -dict {PACKAGE_PIN R4 } [get_ports ib_gtx_zw2tt_p[1] ] ;# SRIO_2_ZW2TT_P
|
||||
|
||||
set_property -dict {PACKAGE_PIN AH12 IOSTANDARD LVCMOS33} [get_ports rs422_tt2zw ] ;# RS422_TT2ZW
|
||||
set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVCMOS33} [get_ports rs422_zw2tt ] ;# RS422_ZW2TT
|
||||
|
||||
# UTC RS422
|
||||
set_property -dict {PACKAGE_PIN AA13 IOSTANDARD LVCMOS33} [get_ports rs422_utc_rxd ] ;# RS422_UTC_RXD
|
||||
set_property -dict {PACKAGE_PIN AK13 IOSTANDARD LVCMOS33} [get_ports rs422_utc_reb ] ;# RS422_UTC_REB
|
||||
set_property -dict {PACKAGE_PIN AK12 IOSTANDARD LVCMOS33} [get_ports rs422_utc_de ] ;# RS422_UTC_DE
|
||||
set_property -dict {PACKAGE_PIN AH18 IOSTANDARD LVCMOS33} [get_ports rs422_utc_txd ] ;# RS422_UTC_TXD
|
||||
|
||||
# RF Control
|
||||
set_property -dict {PACKAGE_PIN AK15 IOSTANDARD LVCMOS33} [get_ports rf_spi_clk ] ;# RF_SPI_CLK
|
||||
set_property -dict {PACKAGE_PIN AD14 IOSTANDARD LVCMOS33} [get_ports rf_spi_mosi1 ] ;# RF_SPI_MOSI1
|
||||
set_property -dict {PACKAGE_PIN AJ16 IOSTANDARD LVCMOS33} [get_ports rf_spi_mosi2 ] ;# RF_SPI_MOSI2
|
||||
set_property -dict {PACKAGE_PIN AK16 IOSTANDARD LVCMOS33} [get_ports rf_spi_mosi3 ] ;# RF_SPI_MOSI3
|
||||
set_property -dict {PACKAGE_PIN AD13 IOSTANDARD LVCMOS33} [get_ports rf_spi_mosi4 ] ;# RF_SPI_MOSI4
|
||||
set_property -dict {PACKAGE_PIN AJ15 IOSTANDARD LVCMOS33} [get_ports rf_spi_sen ] ;# RF_SPI_SEN
|
||||
set_property -dict {PACKAGE_PIN AE12 IOSTANDARD LVCMOS33} [get_ports rf_spi_miso ] ;# RF_SPI_MISO
|
||||
|
||||
# PS PJTAG
|
||||
set_property -dict {PACKAGE_PIN AD24 IOSTANDARD LVCMOS33} [get_ports pjtag_tdi ] ;# PS1_TDI
|
||||
set_property -dict {PACKAGE_PIN AG24 IOSTANDARD LVCMOS33} [get_ports pjtag_tms ] ;# PS1_TMS
|
||||
set_property -dict {PACKAGE_PIN AG25 IOSTANDARD LVCMOS33} [get_ports pjtag_tck ] ;# PS1_TCK
|
||||
set_property -dict {PACKAGE_PIN AF23 IOSTANDARD LVCMOS33} [get_ports pjtag_tdo ] ;# PS1_TDO
|
||||
|
||||
# 3.3V Debug IO
|
||||
set_property -dict {PACKAGE_PIN AA20 IOSTANDARD LVCMOS33} [get_ports uart_rxd ] ;# PL1_UART_RXD
|
||||
set_property -dict {PACKAGE_PIN Y20 IOSTANDARD LVCMOS33} [get_ports uart_txd ] ;# PL1_UART_TXD
|
||||
|
||||
set_property -dict {PACKAGE_PIN AB24 IOSTANDARD LVCMOS33} [get_ports debug_io_1 ] ;# PL1_DEBUG_IO_1
|
||||
set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVCMOS33} [get_ports debug_io_2 ] ;# PL1_DEBUG_IO_2
|
||||
set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVCMOS33} [get_ports debug_io_3 ] ;# PL1_DEBUG_IO_3
|
||||
set_property -dict {PACKAGE_PIN AC22 IOSTANDARD LVCMOS33} [get_ports debug_io_4 ] ;# PL1_DEBUG_IO_4
|
||||
set_property -dict {PACKAGE_PIN AC23 IOSTANDARD LVCMOS33} [get_ports debug_io_5 ] ;# PL1_DEBUG_IO_5
|
||||
Reference in New Issue
Block a user