feat: 更新软件版本至2024.1
This commit is contained in:
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`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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// _ _ ____
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// | | ___ ___| |__ / ___| __ _ ___
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// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
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// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
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// \___/ \___/|___/_| |_| \____|\__,_|\___/
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//
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// Create Date: 2022/07/01 17:37:27
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// Last Modified Date: 2023/03/06 11:26
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// Design Name:
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// Module Name: ad9361_rx_map_cmos_dual
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module ad9361_rx_map_cmos_dual
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(
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input clk_2x_in ,
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input clk_in_rst ,
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input rx_data_clk , // sync to output data
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input rx_data_clk_rst ,
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input rx_fifo_rst , // async fifo reset
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input rx_frame ,
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input [11:0] rx_data ,
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output [11:0] rx_ch1_i ,
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output [11:0] rx_ch1_q ,
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output [11:0] rx_ch2_i ,
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output [11:0] rx_ch2_q
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);
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genvar mm;
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// rx data
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wire [11:0] rx_data_pos;
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wire [11:0] rx_data_neg;
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generate
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for (mm = 0; mm < 12; mm = mm + 1) begin
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IDDR #(
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.DDR_CLK_EDGE ("SAME_EDGE" ),
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.INIT_Q1 (1'b0 ),
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.INIT_Q2 (1'b0 ),
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.SRTYPE ("ASYNC" )
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) i_rx_data_iddr (
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.CE (1'b1 ),
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.R (1'b0 ),
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.S (1'b0 ),
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.C (clk_2x_in ),
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.D (rx_data[mm] ),
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.Q1 (rx_data_pos[mm]),
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.Q2 (rx_data_neg[mm])
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);
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end
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endgenerate
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// rx frame
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wire rx_frame_pos;
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wire rx_frame_neg;
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IDDR #(
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.DDR_CLK_EDGE ("SAME_EDGE" ),
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.INIT_Q1 (1'b0 ),
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.INIT_Q2 (1'b0 ),
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.SRTYPE ("ASYNC" )
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) i_rx_frame_iddr (
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.CE (1'b1 ),
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.R (1'b0 ),
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.S (1'b0 ),
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.C (clk_2x_in ),
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.D (rx_frame ),
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.Q1 (rx_frame_pos ),
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.Q2 (rx_frame_neg )
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);
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// divide rx_data to dual channel
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reg [11:0] rx1_data_i = 'b0;
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reg [11:0] rx1_data_q = 'b0;
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reg [11:0] rx2_data_i = 'b0;
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reg [11:0] rx2_data_q = 'b0;
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reg rx_fifo_wr_en = 'b0;
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reg rx_fifo_rd_en = 'b0;
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wire rx_fifo_empty_1;
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wire rx_fifo_empty_2;
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wire rx_fifo_empty_3;
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wire rx_fifo_empty_4;
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always @ (posedge clk_2x_in) begin
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if (clk_in_rst) begin
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rx1_data_i <= 'b0;
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rx1_data_q <= 'b0;
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rx2_data_i <= 'b0;
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rx2_data_q <= 'b0;
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rx_fifo_wr_en <= 'b0;
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end
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else if({rx_frame_neg,rx_frame_pos} == 2'b11) begin
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rx1_data_i <= rx_data_neg;
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rx1_data_q <= rx_data_pos;
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rx2_data_i <= rx2_data_i;
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rx2_data_q <= rx2_data_q;
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rx_fifo_wr_en <= 'b0;
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end
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else if({rx_frame_neg,rx_frame_pos} == 2'b00) begin
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rx1_data_i <= rx1_data_i;
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rx1_data_q <= rx1_data_q;
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rx2_data_i <= rx_data_neg;
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rx2_data_q <= rx_data_pos;
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rx_fifo_wr_en <= 'b1;
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end
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else begin
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rx1_data_i <= 'd1234; // error
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rx1_data_q <= 'd4321; // error
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rx2_data_i <= 'd5678; // error
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rx2_data_q <= 'd8765; // error
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rx_fifo_wr_en <= 'b0;
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end
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end
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always @(posedge rx_data_clk) begin
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if (rx_data_clk_rst) begin
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rx_fifo_rd_en <= 'b0;
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end
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else begin
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rx_fifo_rd_en <= &{~rx_fifo_empty_1, ~rx_fifo_empty_2, ~rx_fifo_empty_3, ~rx_fifo_empty_4};
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end
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end
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ad9361_fifo u_rx_fifo_ch1_i
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(
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.rst (clk_in_rst || rx_fifo_rst ), // input wire rst
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.wr_clk (clk_2x_in ), // input wire wr_clk
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.rd_clk (rx_data_clk ), // input wire rd_clk
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.din (rx1_data_i ), // input wire [11 : 0] din
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.wr_en (rx_fifo_wr_en ), // input wire wr_en
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.rd_en (rx_fifo_rd_en ), // input wire rd_en
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.dout (rx_ch1_i ), // output wire [11 : 0] dout
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.full ( ), // output wire full
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.empty (rx_fifo_empty_1 ) // output wire empty
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);
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ad9361_fifo u_rx_fifo_ch1_q
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(
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.rst (clk_in_rst || rx_fifo_rst ), // input wire rst
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.wr_clk (clk_2x_in ), // input wire wr_clk
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.rd_clk (rx_data_clk ), // input wire rd_clk
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.din (rx1_data_q ), // input wire [11 : 0] din
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.wr_en (rx_fifo_wr_en ), // input wire wr_en
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.rd_en (rx_fifo_rd_en ), // input wire rd_en
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.dout (rx_ch1_q ), // output wire [11 : 0] dout
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.full ( ), // output wire full
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.empty (rx_fifo_empty_2 ) // output wire empty
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);
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ad9361_fifo u_rx_fifo_ch2_i
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(
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.rst (clk_in_rst || rx_fifo_rst ), // input wire rst
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.wr_clk (clk_2x_in ), // input wire wr_clk
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.rd_clk (rx_data_clk ), // input wire rd_clk
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.din (rx2_data_i ), // input wire [11 : 0] din
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.wr_en (rx_fifo_wr_en ), // input wire wr_en
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.rd_en (rx_fifo_rd_en ), // input wire rd_en
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.dout (rx_ch2_i ), // output wire [11 : 0] dout
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.full ( ), // output wire full
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.empty (rx_fifo_empty_3 ) // output wire empty
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);
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ad9361_fifo u_rx_fifo_ch2_q
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(
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.rst (clk_in_rst || rx_fifo_rst ), // input wire rst
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.wr_clk (clk_2x_in ), // input wire wr_clk
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.rd_clk (rx_data_clk ), // input wire rd_clk
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.din (rx2_data_q ), // input wire [11 : 0] din
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.wr_en (rx_fifo_wr_en ), // input wire wr_en
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.rd_en (rx_fifo_rd_en ), // input wire rd_en
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.dout (rx_ch2_q ), // output wire [11 : 0] dout
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.full ( ), // output wire full
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.empty (rx_fifo_empty_4 ) // output wire empty
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);
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endmodule
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@@ -0,0 +1,163 @@
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`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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// _ _ ____
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||||
// | | ___ ___| |__ / ___| __ _ ___
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||||
// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
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||||
// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
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||||
// \___/ \___/|___/_| |_| \____|\__,_|\___/
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//
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// Create Date: 2022/07/01 17:37:27
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// Last Modified Date: 2023/03/03 13:01
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// Design Name:
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// Module Name: ad9361_rx_map_cmos_single
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module ad9361_rx_map_cmos_single
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(
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input clk_in ,
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input clk_in_rst ,
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input rx_data_clk ,
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input rx_data_clk_rst ,
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input rx_fifo_rst ,
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input rx_frame ,
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input [11:0] rx_data ,
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output [11:0] rx_data_i ,
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output [11:0] rx_data_q
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);
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genvar mm;
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// rx data from port
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wire [11:0] rx_data_pos;
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wire [11:0] rx_data_neg;
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generate
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for (mm = 0; mm < 12; mm = mm + 1) begin : rx_data_iddr
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IDDR #(
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.DDR_CLK_EDGE ("SAME_EDGE" ), // "OPPOSITE_EDGE", "SAME_EDGE" or "SAME_EDGE_PIPELINED"
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.INIT_Q1 (1'b0 ), // Initial value of Q1: 1'b0 or 1'b1
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.INIT_Q2 (1'b0 ), // Initial value of Q2: 1'b0 or 1'b1
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.SRTYPE ("ASYNC" ) // Set/Reset type: "SYNC" or "ASYNC"
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) i_rx_data_iddr (
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.CE (1'b1 ), // 1-bit clock enable input
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.R (1'b0 ), // 1-bit reset
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.S (1'b0 ), // 1-bit set
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.C (clk_in ), // 1-bit clock input
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.D (rx_data[mm] ), // 1-bit DDR data input
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.Q1 (rx_data_pos[mm]), // 1-bit output for positive edge of clock
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.Q2 (rx_data_neg[mm]) // 1-bit output for negative edge of clock
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);
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end
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endgenerate
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// rx frame from port
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wire rx_frame_pos;
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wire rx_frame_neg;
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IDDR #(
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.DDR_CLK_EDGE ("SAME_EDGE" ), // "OPPOSITE_EDGE", "SAME_EDGE" or "SAME_EDGE_PIPELINED"
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.INIT_Q1 (1'b0 ), // Initial value of Q1: 1'b0 or 1'b1
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.INIT_Q2 (1'b0 ), // Initial value of Q2: 1'b0 or 1'b1
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.SRTYPE ("ASYNC" ) // Set/Reset type: "SYNC" or "ASYNC"
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) i_rx_frame_iddr (
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.CE (1'b1 ), // 1-bit clock enable input
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.R (1'b0 ), // 1-bit reset
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.S (1'b0 ), // 1-bit set
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.C (clk_in ), // 1-bit clock input
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.D (rx_frame ), // 1-bit DDR data input
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.Q1 (rx_frame_pos ), // 1-bit output for positive edge of clock
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.Q2 (rx_frame_neg ) // 1-bit output for negative edge of clock
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);
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// rx data
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reg [11:0] rx_fifo_i = 'b0;
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reg [11:0] rx_fifo_q = 'b0;
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always @(posedge clk_in) begin
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if (clk_in_rst) begin
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rx_fifo_i <= 'b0;
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rx_fifo_q <= 'b0;
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end
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else begin
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if ({rx_frame_neg,rx_frame_pos} == 2'b10) begin
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rx_fifo_i <= rx_data_neg;
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rx_fifo_q <= rx_data_pos;
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end
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else begin
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rx_fifo_i <= 'd1234; // error
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rx_fifo_q <= 'd4321; // error
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end
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end
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end
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// divide rx_data to dual channel
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reg rx_fifo_wr_en = 1'b0;
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reg rx_fifo_rd_en = 'b0;
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wire rx_fifo_empty_1;
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wire rx_fifo_empty_2;
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always @(posedge clk_in) begin
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if (clk_in_rst) begin
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rx_fifo_wr_en <= 1'b0;
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end
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else begin
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rx_fifo_wr_en <= 1'b1;
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end
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end
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always @(posedge rx_data_clk) begin
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if (rx_data_clk_rst) begin
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rx_fifo_rd_en <= 'b0;
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end
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else begin
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rx_fifo_rd_en <= &{~rx_fifo_empty_1, ~rx_fifo_empty_2};
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end
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end
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ad9361_fifo u_rx_fifo_i
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(
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.rst (clk_in_rst || rx_fifo_rst ), // input wire rst
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.wr_clk (clk_in ), // input wire wr_clk
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.rd_clk (rx_data_clk ), // input wire rd_clk
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.din (rx_fifo_i ), // input wire [11 : 0] din
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.wr_en (rx_fifo_wr_en ), // input wire wr_en
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.rd_en (rx_fifo_rd_en ), // input wire rd_en
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.dout (rx_data_i ), // output wire [11 : 0] dout
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.full ( ), // output wire full
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.empty (rx_fifo_empty_1 ) // output wire empty
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);
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ad9361_fifo u_rx_fifo_q
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(
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.rst (clk_in_rst || rx_fifo_rst ), // input wire rst
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.wr_clk (clk_in ), // input wire wr_clk
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.rd_clk (rx_data_clk ), // input wire rd_clk
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.din (rx_fifo_q ), // input wire [11 : 0] din
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.wr_en (rx_fifo_wr_en ), // input wire wr_en
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.rd_en (rx_fifo_rd_en ), // input wire rd_en
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.dout (rx_data_q ), // output wire [11 : 0] dout
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.full ( ), // output wire full
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.empty (rx_fifo_empty_2 ) // output wire empty
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);
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endmodule
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@@ -0,0 +1,193 @@
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`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
// _ _ ____
|
||||
// | | ___ ___| |__ / ___| __ _ ___
|
||||
// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
|
||||
// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
|
||||
// \___/ \___/|___/_| |_| \____|\__,_|\___/
|
||||
//
|
||||
// Create Date: 2022/07/01 16:39:19
|
||||
// Last Modified Date: 2024/09/27 16:22
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||||
// Design Name:
|
||||
// Module Name: ad9361_tx_map_cmos_dual
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
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||||
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module ad9361_tx_map_cmos_dual
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(
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input clk_2x_in ,
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input clk_in_rst ,
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input tx_data_clk ,
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input tx_data_clk_rst ,
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input [11:0] tx_ch1_i ,
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input [11:0] tx_ch1_q ,
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input [11:0] tx_ch2_i ,
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input [11:0] tx_ch2_q ,
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output clk_out ,
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output tx_frame ,
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output [11:0] tx_data
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);
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genvar mm;
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// input data fifo
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reg tx_fifo_rd_en = 'b0;
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wire [11:0] tx_fifo_ch1_i;
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wire [11:0] tx_fifo_ch1_q;
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wire [11:0] tx_fifo_ch2_i;
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wire [11:0] tx_fifo_ch2_q;
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wire rx_fifo_empty_1;
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wire rx_fifo_empty_2;
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wire rx_fifo_empty_3;
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wire rx_fifo_empty_4;
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always @(posedge clk_2x_in) begin
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if (clk_in_rst) begin
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tx_fifo_rd_en <= 'b0;
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||||
end
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||||
else begin
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if (&{~rx_fifo_empty_1, ~rx_fifo_empty_2, ~rx_fifo_empty_3, ~rx_fifo_empty_4}) begin
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tx_fifo_rd_en <= ~tx_fifo_rd_en;
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||||
end
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else begin
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tx_fifo_rd_en <= 'b0;
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||||
end
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||||
end
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||||
end
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||||
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||||
ad9361_fifo u_tx_fifo_ch1_i
|
||||
(
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||||
.rst (clk_in_rst ), // input wire rst
|
||||
.wr_clk (tx_data_clk ), // input wire wr_clk
|
||||
.rd_clk (clk_2x_in ), // input wire rd_clk
|
||||
.din (tx_ch1_i ), // input wire [11 : 0] din
|
||||
.wr_en (1'b1 ), // input wire wr_en
|
||||
.rd_en (tx_fifo_rd_en ), // input wire rd_en
|
||||
.dout (tx_fifo_ch1_i ), // output wire [11 : 0] dout
|
||||
.full ( ), // output wire full
|
||||
.empty (rx_fifo_empty_1) // output wire empty
|
||||
);
|
||||
|
||||
ad9361_fifo u_tx_fifo_ch1_q
|
||||
(
|
||||
.rst (clk_in_rst ), // input wire rst
|
||||
.wr_clk (tx_data_clk ), // input wire wr_clk
|
||||
.rd_clk (clk_2x_in ), // input wire rd_clk
|
||||
.din (tx_ch1_q ), // input wire [11 : 0] din
|
||||
.wr_en (1'b1 ), // input wire wr_en
|
||||
.rd_en (tx_fifo_rd_en ), // input wire rd_en
|
||||
.dout (tx_fifo_ch1_q ), // output wire [11 : 0] dout
|
||||
.full ( ), // output wire full
|
||||
.empty (rx_fifo_empty_2) // output wire empty
|
||||
);
|
||||
|
||||
ad9361_fifo u_tx_fifo_ch2_i
|
||||
(
|
||||
.rst (clk_in_rst ), // input wire rst
|
||||
.wr_clk (tx_data_clk ), // input wire wr_clk
|
||||
.rd_clk (clk_2x_in ), // input wire rd_clk
|
||||
.din (tx_ch2_i ), // input wire [11 : 0] din
|
||||
.wr_en (1'b1 ), // input wire wr_en
|
||||
.rd_en (tx_fifo_rd_en ), // input wire rd_en
|
||||
.dout (tx_fifo_ch2_i ), // output wire [11 : 0] dout
|
||||
.full ( ), // output wire full
|
||||
.empty (rx_fifo_empty_3) // output wire empty
|
||||
);
|
||||
|
||||
ad9361_fifo u_tx_fifo_ch2_q
|
||||
(
|
||||
.rst (clk_in_rst ), // input wire rst
|
||||
.wr_clk (tx_data_clk ), // input wire wr_clk
|
||||
.rd_clk (clk_2x_in ), // input wire rd_clk
|
||||
.din (tx_ch2_q ), // input wire [11 : 0] din
|
||||
.wr_en (1'b1 ), // input wire wr_en
|
||||
.rd_en (tx_fifo_rd_en ), // input wire rd_en
|
||||
.dout (tx_fifo_ch2_q ), // output wire [11 : 0] dout
|
||||
.full ( ), // output wire full
|
||||
.empty (rx_fifo_empty_4) // output wire empty
|
||||
);
|
||||
|
||||
// frame and data control
|
||||
reg tx_frame_i = 'b0;
|
||||
reg tx_frame_q = 'b0;
|
||||
reg [11:0] tx_data_i = 'b0;
|
||||
reg [11:0] tx_data_q = 'b0;
|
||||
|
||||
always @(posedge clk_2x_in) begin
|
||||
if (clk_in_rst) begin
|
||||
tx_frame_i <= 'b0;
|
||||
tx_frame_q <= 'b0;
|
||||
tx_data_i <= 'b0;
|
||||
tx_data_q <= 'b0;
|
||||
end
|
||||
else if (tx_fifo_rd_en == 1'b0) begin
|
||||
tx_frame_i <= 1'b1;
|
||||
tx_frame_q <= 1'b1;
|
||||
tx_data_i <= tx_fifo_ch1_i;
|
||||
tx_data_q <= tx_fifo_ch1_q;
|
||||
end
|
||||
else begin
|
||||
tx_frame_i <= 1'b0;
|
||||
tx_frame_q <= 1'b0;
|
||||
tx_data_i <= tx_fifo_ch2_i;
|
||||
tx_data_q <= tx_fifo_ch2_q;
|
||||
end
|
||||
end
|
||||
|
||||
// output clock to port
|
||||
assign clk_out = clk_2x_in;
|
||||
|
||||
// output tx frame to port
|
||||
ODDR #(
|
||||
.DDR_CLK_EDGE ("SAME_EDGE" ),
|
||||
.INIT (1'b0 ),
|
||||
.SRTYPE ("ASYNC" )
|
||||
) u_tx_frame_oddr (
|
||||
.CE (1'b1 ),
|
||||
.R (1'b0 ),
|
||||
.S (1'b0 ),
|
||||
.C (clk_2x_in ),
|
||||
.D1 (tx_frame_i ),
|
||||
.D2 (tx_frame_q ),
|
||||
.Q (tx_frame )
|
||||
);
|
||||
|
||||
generate
|
||||
for (mm = 0; mm < 12; mm = mm + 1) begin
|
||||
|
||||
// output tx data to port
|
||||
ODDR #(
|
||||
.DDR_CLK_EDGE ("SAME_EDGE" ),
|
||||
.INIT (1'b0 ),
|
||||
.SRTYPE ("ASYNC" )
|
||||
) u_tx_data_oddr (
|
||||
.CE (1'b1 ),
|
||||
.R (1'b0 ),
|
||||
.S (1'b0 ),
|
||||
.C (clk_2x_in ),
|
||||
.D1 (tx_data_i[mm] ),
|
||||
.D2 (tx_data_q[mm] ),
|
||||
.Q (tx_data[mm] )
|
||||
);
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,119 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
// _ _ ____
|
||||
// | | ___ ___| |__ / ___| __ _ ___
|
||||
// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
|
||||
// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
|
||||
// \___/ \___/|___/_| |_| \____|\__,_|\___/
|
||||
//
|
||||
// Create Date: 2022/07/01 16:39:19
|
||||
// Design Name:
|
||||
// Module Name: ad9361_tx_mapping_single
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module ad9361_tx_map_cmos_single
|
||||
(
|
||||
input clk_in ,
|
||||
input clk_in_rst ,
|
||||
|
||||
input tx_data_clk ,
|
||||
input tx_data_clk_rst ,
|
||||
|
||||
input [11:0] tx_data_i ,
|
||||
input [11:0] tx_data_q ,
|
||||
|
||||
output clk_out ,
|
||||
output tx_frame ,
|
||||
output [11:0] tx_data
|
||||
);
|
||||
|
||||
genvar mm;
|
||||
|
||||
// inout data fifo
|
||||
wire [11:0] tx_fifo_i;
|
||||
wire [11:0] tx_fifo_q;
|
||||
|
||||
ad9361_fifo u_tx_fifo_i
|
||||
(
|
||||
.rst (clk_in_rst ), // input wire rst
|
||||
.wr_clk (tx_data_clk ), // input wire wr_clk
|
||||
.rd_clk (clk_in ), // input wire rd_clk
|
||||
.din (tx_data_i ), // input wire [11 : 0] din
|
||||
.wr_en (1'b1 ), // input wire wr_en
|
||||
.rd_en (1'b1 ), // input wire rd_en
|
||||
.dout (tx_fifo_i ), // output wire [11 : 0] dout
|
||||
.full ( ), // output wire full
|
||||
.empty ( ) // output wire empty
|
||||
);
|
||||
|
||||
ad9361_fifo u_tx_fifo_q
|
||||
(
|
||||
.rst (clk_in_rst ), // input wire rst
|
||||
.wr_clk (tx_data_clk ), // input wire wr_clk
|
||||
.rd_clk (clk_in ), // input wire rd_clk
|
||||
.din (tx_data_q ), // input wire [11 : 0] din
|
||||
.wr_en (1'b1 ), // input wire wr_en
|
||||
.rd_en (1'b1 ), // input wire rd_en
|
||||
.dout (tx_fifo_q ), // output wire [11 : 0] dout
|
||||
.full ( ), // output wire full
|
||||
.empty ( ) // output wire empty
|
||||
);
|
||||
|
||||
// frame and data control
|
||||
assign tx_frame_i = 1'b1;
|
||||
assign tx_frame_q = 1'b0;
|
||||
|
||||
// output clock to port
|
||||
assign clk_out = clk_in;
|
||||
|
||||
// output tx frame to port
|
||||
ODDR #(
|
||||
.DDR_CLK_EDGE ("SAME_EDGE" ), // "OPPOSITE_EDGE" or "SAME_EDGE"
|
||||
.INIT (1'b0 ), // Initial value of Q: 1'b0 or 1'b1
|
||||
.SRTYPE ("ASYNC" ) // Set/Reset type: "SYNC" or "ASYNC"
|
||||
) u_tx_frame_oddr (
|
||||
.CE (1'b1 ), // 1-bit clock enable input
|
||||
.R (1'b0 ), // 1-bit reset
|
||||
.S (1'b0 ), // 1-bit set
|
||||
.C (clk_in ), // 1-bit clock input
|
||||
.D1 (tx_frame_i ), // 1-bit data input (positive edge)
|
||||
.D2 (tx_frame_q ), // 1-bit data input (negative edge)
|
||||
.Q (tx_frame ) // 1-bit DDR output
|
||||
);
|
||||
|
||||
// output tx data to port
|
||||
generate
|
||||
for (mm = 0; mm < 12; mm = mm + 1) begin: tx_data_oddr
|
||||
|
||||
ODDR #(
|
||||
.DDR_CLK_EDGE ("SAME_EDGE" ), // "OPPOSITE_EDGE" or "SAME_EDGE"
|
||||
.INIT (1'b0 ), // Initial value of Q: 1'b0 or 1'b1
|
||||
.SRTYPE ("ASYNC" ) // Set/Reset type: "SYNC" or "ASYNC"
|
||||
) u_tx_data_oddr (
|
||||
.CE (1'b1 ), // 1-bit clock enable input
|
||||
.R (1'b0 ), // 1-bit reset
|
||||
.S (1'b0 ), // 1-bit set
|
||||
.C (clk_in ), // 1-bit clock input
|
||||
.D1 (tx_fifo_i[mm] ), // 1-bit data input (positive edge)
|
||||
.D2 (tx_fifo_q[mm] ), // 1-bit data input (negative edge)
|
||||
.Q (tx_data[mm] ) // 1-bit DDR output
|
||||
);
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,118 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 09/09/2024 07:43:16 PM
|
||||
// Design Name:
|
||||
// Module Name: clk_dist
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "defines.v"
|
||||
|
||||
module clk_dist
|
||||
(
|
||||
// input clocks
|
||||
input ad9361_1_rx_data_clk, // ad9361 rx data clock, 83.3333mhz
|
||||
input ad9361_2_rx_data_clk, // ad9361 rx data clock, 83.3333mhz
|
||||
|
||||
// output clocks & reset
|
||||
// pl signal processing clock
|
||||
output sys_rst , // global reset signal, active high
|
||||
output sys_clk , // 41.6667mhz
|
||||
output sys_clk_2x , // 83.3333mhz
|
||||
output sys_clk_3x , // 125mhz
|
||||
output sys_clk_4x , // 166.6667mhz
|
||||
output sys_clk_ld , // system main clock locked indicator
|
||||
|
||||
// ad9361-1 clocks
|
||||
output ad9361_1_clk , // 41.6667mhz
|
||||
output ad9361_1_clk_2x , // 83.3333mhz
|
||||
output ad9361_1_clk_3x , // 125mhz
|
||||
output ad9361_1_clk_4x , // 166.6667mhz
|
||||
output ad9361_1_clk_ld , // ad9361-1 clock group locked indicator
|
||||
|
||||
// ad9361-2 clocks
|
||||
output ad9361_2_clk , // 41.6667mhz
|
||||
output ad9361_2_clk_2x , // 83.3333mhz
|
||||
output ad9361_2_clk_3x , // 125mhz
|
||||
output ad9361_2_clk_4x , // 166.6667mhz
|
||||
output ad9361_2_clk_ld // ad9361-2 clock group locked indicator
|
||||
);
|
||||
|
||||
assign sys_clk = ad9361_1_clk ;
|
||||
assign sys_clk_2x = ad9361_1_clk_2x;
|
||||
assign sys_clk_3x = ad9361_1_clk_3x;
|
||||
assign sys_clk_4x = ad9361_1_clk_4x;
|
||||
assign sys_clk_ld = ad9361_1_clk_ld;
|
||||
|
||||
assign sys_rst = ~sys_clk_ld;
|
||||
|
||||
`ifdef AD9361_1_CMOS_2T2R // define AD9361_1_2T2R at top of system_top.v if 2t2r is required
|
||||
ad9361_clk_gen_cmos_2t2r u_ad9361_1_clk_gen
|
||||
(
|
||||
// Clock out ports
|
||||
.clk_out1 (ad9361_1_clk ), // output clk_out1
|
||||
.clk_out2 (ad9361_1_clk_2x ), // output clk_out2
|
||||
.clk_out3 (ad9361_1_clk_3x ), // output clk_out3
|
||||
.clk_out4 (ad9361_1_clk_4x ), // output clk_out4
|
||||
// Status and control signals
|
||||
.locked (ad9361_1_clk_ld ), // output locked
|
||||
// Clock in ports
|
||||
.clk_in1 (ad9361_1_rx_data_clk ) // input clk_in1
|
||||
);
|
||||
`else
|
||||
ad9361_clk_gen_cmos_1t1r u_ad9361_1_clk_gen
|
||||
(
|
||||
// Clock out ports
|
||||
.clk_out1 (ad9361_1_clk ), // output clk_out1
|
||||
.clk_out2 (ad9361_1_clk_2x ), // output clk_out2
|
||||
.clk_out3 (ad9361_1_clk_3x ), // output clk_out3
|
||||
.clk_out4 (ad9361_1_clk_4x ), // output clk_out4
|
||||
// Status and control signals
|
||||
.locked (ad9361_1_clk_ld ), // output locked
|
||||
// Clock in ports
|
||||
.clk_in1 (ad9361_1_rx_data_clk ) // input clk_in1
|
||||
);
|
||||
`endif
|
||||
|
||||
`ifdef AD9361_2_CMOS_2T2R // define AD9361_1_2T2R at top of system_top.v if 2t2r is required
|
||||
ad9361_clk_gen_cmos_2t2r u_ad9361_2_clk_gen
|
||||
(
|
||||
// Clock out ports
|
||||
.clk_out1 (ad9361_2_clk ), // output clk_out1
|
||||
.clk_out2 (ad9361_2_clk_2x ), // output clk_out2
|
||||
.clk_out3 (ad9361_2_clk_3x ), // output clk_out3
|
||||
.clk_out4 (ad9361_2_clk_4x ), // output clk_out4
|
||||
// Status and control signals
|
||||
.locked (ad9361_2_clk_ld ), // output locked
|
||||
// Clock in ports
|
||||
.clk_in1 (ad9361_2_rx_data_clk ) // input clk_in1
|
||||
);
|
||||
`else
|
||||
ad9361_clk_gen_cmos_1t1r u_ad9361_2_clk_gen
|
||||
(
|
||||
// Clock out ports
|
||||
.clk_out1 (ad9361_2_clk ), // output clk_out1
|
||||
.clk_out2 (ad9361_2_clk_2x ), // output clk_out2
|
||||
.clk_out3 (ad9361_2_clk_3x ), // output clk_out3
|
||||
.clk_out4 (ad9361_2_clk_4x ), // output clk_out4
|
||||
// Status and control signals
|
||||
.locked (ad9361_2_clk_ld ), // output locked
|
||||
// Clock in ports
|
||||
.clk_in1 (ad9361_2_rx_data_clk ) // input clk_in1
|
||||
);
|
||||
`endif
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,2 @@
|
||||
`define AD9361_1_CMOS_2T2R
|
||||
`define AD9361_2_CMOS_2T2R
|
||||
@@ -0,0 +1,616 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 09/09/2024 07:16:39 PM
|
||||
// Design Name:
|
||||
// Module Name: system_top
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "defines.v"
|
||||
|
||||
module system_top
|
||||
(
|
||||
/***************************************************************************
|
||||
* Contents
|
||||
* 01. Clocks
|
||||
* 02. AD9528 Interface
|
||||
* 03. AD9361-1 Interface
|
||||
* 04. AD9361-2 Interface
|
||||
* 05. Inter-FPGA Ports
|
||||
* 06. Inter-board Ports
|
||||
* 07. 3.3V Debug IO
|
||||
* 08. DDR and Fixed-io (Do NOT Modify)
|
||||
**************************************************************************/
|
||||
|
||||
// *************************************************************************
|
||||
// ******************************** Clocks *********************************
|
||||
// *************************************************************************
|
||||
// ad9528 clock
|
||||
input refclk_1_p , // 200MHz
|
||||
input refclk_1_n ,
|
||||
input refclk_2_p , // 200MHz
|
||||
input refclk_2_n ,
|
||||
input gtclk_109_p , // 200MHz
|
||||
input gtclk_109_n ,
|
||||
input gtclk_110_p , // 200MHz
|
||||
input gtclk_110_n ,
|
||||
input gtclk_112_p , // 200MHz
|
||||
input gtclk_112_n ,
|
||||
// ad9361 buffered clock
|
||||
input ad9361_1_buffer_clk , // derived from ad9361 input clock
|
||||
input ad9361_2_buffer_clk , // derived from ad9361 input clock
|
||||
// *************************************************************************
|
||||
// *************************** AD9528 Interface ****************************
|
||||
// *************************************************************************
|
||||
output ad9528_spi_csn ,
|
||||
output ad9528_spi_clk ,
|
||||
output ad9528_spi_mosi ,
|
||||
input ad9528_spi_miso ,
|
||||
// control signals
|
||||
input [ 1:0] ad9528_status ,
|
||||
output ad9528_reset_b ,
|
||||
output ad9528_sysref_req ,
|
||||
// *************************************************************************
|
||||
// ************************** AD9361-1 Interface ***************************
|
||||
// *************************************************************************
|
||||
// rx data (rx channels are tied to ground physically)
|
||||
input ad9361_1_rx_data_clk, // ad9361 rx data clock, 96mhz
|
||||
input ad9361_1_rx_frame ,
|
||||
input [11:0] ad9361_1_rx_data ,
|
||||
// tx data
|
||||
output ad9361_1_tx_fb_clk ,
|
||||
output ad9361_1_tx_frame ,
|
||||
output [11:0] ad9361_1_tx_data ,
|
||||
// spi interface
|
||||
output ad9361_1_spi_clk ,
|
||||
output ad9361_1_spi_csn ,
|
||||
output ad9361_1_spi_mosi ,
|
||||
input ad9361_1_spi_miso ,
|
||||
// control signals
|
||||
output ad9361_1_reset_b , // ad9361 active-low reset control
|
||||
output ad9361_1_en_agc , // ad9361 manual agc control
|
||||
output ad9361_1_enable , // ad9361 enable state machine pin control (spi control is also allowed)
|
||||
output ad9361_1_txnrx , // ad9361 enable state machine pin control (spi control is also allowed)
|
||||
input [ 3:0] ad9361_1_ctrl_in ,
|
||||
output [ 7:0] ad9361_1_ctrl_out ,
|
||||
// *************************************************************************
|
||||
// ************************** AD9361-2 Interface ***************************
|
||||
// *************************************************************************
|
||||
// rx data (rx channels are tied to ground physically)
|
||||
input ad9361_2_rx_data_clk,
|
||||
input ad9361_2_rx_frame ,
|
||||
input [11:0] ad9361_2_rx_data ,
|
||||
// tx data
|
||||
output ad9361_2_tx_fb_clk ,
|
||||
output ad9361_2_tx_frame ,
|
||||
output [11:0] ad9361_2_tx_data ,
|
||||
// spi interface
|
||||
output ad9361_2_spi_clk ,
|
||||
output ad9361_2_spi_csn ,
|
||||
output ad9361_2_spi_mosi ,
|
||||
input ad9361_2_spi_miso ,
|
||||
// control signals
|
||||
output ad9361_2_reset_b , // ad9361 active-low reset control
|
||||
output ad9361_2_en_agc , // ad9361 manual agc control
|
||||
output ad9361_2_enable , // ad9361 enable state machine pin control (spi control is also allowed)
|
||||
output ad9361_2_txnrx , // ad9361 enable state machine pin control (spi control is also allowed)
|
||||
input [ 3:0] ad9361_2_ctrl_in ,
|
||||
output [ 7:0] ad9361_2_ctrl_out ,
|
||||
// *************************************************************************
|
||||
// *************************** Inter-FPGA Ports ****************************
|
||||
// *************************************************************************
|
||||
// low speed
|
||||
inout [22:0] if_lvds_io_1_p ,
|
||||
inout [22:0] if_lvds_io_1_n ,
|
||||
inout [22:0] if_lvds_io_2_p ,
|
||||
inout [22:0] if_lvds_io_2_n ,
|
||||
// high speed
|
||||
input [ 7:0] if_gtx_rxp ,
|
||||
input [ 7:0] if_gtx_rxn ,
|
||||
// output [ 7:0] if_gtx_txp ,
|
||||
// output [ 7:0] if_gtx_txn ,
|
||||
// *************************************************************************
|
||||
// *************************** Inter-board Ports ***************************
|
||||
// *************************************************************************
|
||||
// high speed
|
||||
input [ 1:0] ib_gtx_tt2zw_p ,
|
||||
input [ 1:0] ib_gtx_tt2zw_n ,
|
||||
// output [ 1:0] ib_gtx_zw2tt_p ,
|
||||
// output [ 1:0] ib_gtx_zw2tt_n ,
|
||||
// low speed
|
||||
input rs422_tt2zw ,
|
||||
output rs422_zw2tt ,
|
||||
// *************************************************************************
|
||||
// ******************************* UTC RS422 *******************************
|
||||
// *************************************************************************
|
||||
input rs422_utc_rxd ,
|
||||
input rs422_utc_reb ,
|
||||
input rs422_utc_de ,
|
||||
output rs422_utc_txd ,
|
||||
// *************************************************************************
|
||||
// ****************************** RF Control *******************************
|
||||
// *************************************************************************
|
||||
output rf_spi_clk ,
|
||||
output rf_spi_mosi1 ,
|
||||
output rf_spi_mosi2 ,
|
||||
output rf_spi_mosi3 ,
|
||||
output rf_spi_mosi4 ,
|
||||
output rf_spi_sen ,
|
||||
input rf_spi_miso ,
|
||||
// *************************************************************************
|
||||
// ****************************** PS PJTAG *******************************
|
||||
// *************************************************************************
|
||||
input pjtag_tdi ,
|
||||
input pjtag_tms ,
|
||||
input pjtag_tck ,
|
||||
output pjtag_tdo ,
|
||||
// *************************************************************************
|
||||
// ***************************** 3.3V Debug IO *****************************
|
||||
// *************************************************************************
|
||||
// uart
|
||||
input uart_rxd ,
|
||||
output uart_txd ,
|
||||
// gpio
|
||||
inout debug_io_1 ,
|
||||
inout debug_io_2 ,
|
||||
inout debug_io_3 ,
|
||||
inout debug_io_4 ,
|
||||
inout debug_io_5 ,
|
||||
// *************************************************************************
|
||||
// ******************* DDR and Fixed-io (Do NOT Modify) ********************
|
||||
// *************************************************************************
|
||||
// ddr
|
||||
inout [14:0] ddr_addr ,
|
||||
inout [ 2:0] ddr_ba ,
|
||||
inout ddr_cas_n ,
|
||||
inout ddr_ck_n ,
|
||||
inout ddr_ck_p ,
|
||||
inout ddr_cke ,
|
||||
inout ddr_cs_n ,
|
||||
inout [ 3:0] ddr_dm ,
|
||||
inout [31:0] ddr_dq ,
|
||||
inout [ 3:0] ddr_dqs_n ,
|
||||
inout [ 3:0] ddr_dqs_p ,
|
||||
inout ddr_odt ,
|
||||
inout ddr_ras_n ,
|
||||
inout ddr_reset_n ,
|
||||
inout ddr_we_n ,
|
||||
// fixed-io
|
||||
inout fixed_io_ddr_vrn ,
|
||||
inout fixed_io_ddr_vrp ,
|
||||
inout [53:0] fixed_io_mio ,
|
||||
inout fixed_io_ps_clk ,
|
||||
inout fixed_io_ps_porb ,
|
||||
inout fixed_io_ps_srstb ,
|
||||
// system monitor
|
||||
input sysmon_vp ,
|
||||
input sysmon_vn
|
||||
);
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/////////////////////////// System Clock Generation ////////////////////////////
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// global reset
|
||||
wire sys_rst ; // global reset signal, active high
|
||||
|
||||
// pl signal processing clock (copies of ad9361-1 clocks)
|
||||
wire sys_clk ; // 48MHz 41.6667MHz
|
||||
wire sys_clk_2x ; // 96MHz 83.3333MHz
|
||||
wire sys_clk_3x ; // 144MHz 125MHz
|
||||
wire sys_clk_4x ; // 192MHz 166.6667MHz
|
||||
wire sys_clk_ld ; // system main clock locked indicator
|
||||
|
||||
// ad9361-1 clocks
|
||||
wire ad9361_1_clk ; // 48MHz 41.6667MHz
|
||||
wire ad9361_1_clk_2x ; // 96MHz 83.3333MHz
|
||||
wire ad9361_1_clk_3x ; // 144MHz 125MHz
|
||||
wire ad9361_1_clk_4x ; // 192MHz 166.6667MHz
|
||||
wire ad9361_1_clk_ld ; // ad9361-1 clock group locked indicator
|
||||
|
||||
// ad9361-2 clocks
|
||||
wire ad9361_2_clk ; // 48MHz 41.6667MHz
|
||||
wire ad9361_2_clk_2x ; // 96MHz 83.3333MHz
|
||||
wire ad9361_2_clk_3x ; // 144MHz 125MHz
|
||||
wire ad9361_2_clk_4x ; // 192MHz 166.6667MHz
|
||||
wire ad9361_2_clk_ld ; // ad9361-2 clock group locked indicator
|
||||
|
||||
clk_dist u_clk_dist
|
||||
(
|
||||
// input clocks
|
||||
.ad9361_1_rx_data_clk(ad9361_1_rx_data_clk), // ad9361 rx data clock, 83.3333mhz
|
||||
.ad9361_2_rx_data_clk(ad9361_2_rx_data_clk), // ad9361 rx data clock, 83.3333mhz
|
||||
|
||||
// output clocks & reset
|
||||
// global reset
|
||||
.sys_rst (sys_rst ), // global reset signal, active high
|
||||
|
||||
// pl signal processing clock
|
||||
.sys_clk (sys_clk ), // 48MHz 41.6667MHz
|
||||
.sys_clk_2x (sys_clk_2x ), // 96MHz 83.3333MHz
|
||||
.sys_clk_3x (sys_clk_3x ), // 144MHz 125MHz
|
||||
.sys_clk_4x (sys_clk_4x ), // 192MHz 166.6667MHz
|
||||
.sys_clk_ld (sys_clk_ld ), // system main clock locked indicator
|
||||
|
||||
// ad9361-1 clocks
|
||||
.ad9361_1_clk (ad9361_1_clk ), // 48MHz 41.6667MHz
|
||||
.ad9361_1_clk_2x (ad9361_1_clk_2x ), // 96MHz 83.3333MHz
|
||||
.ad9361_1_clk_3x (ad9361_1_clk_3x ), // 144MHz 125MHz
|
||||
.ad9361_1_clk_4x (ad9361_1_clk_4x ), // 192MHz 166.6667MHz
|
||||
.ad9361_1_clk_ld (ad9361_1_clk_ld ), // ad9361-1 clock group locked indicator
|
||||
|
||||
// ad9361-2 clocks
|
||||
.ad9361_2_clk (ad9361_2_clk ), // 48MHz 41.6667MHz
|
||||
.ad9361_2_clk_2x (ad9361_2_clk_2x ), // 96MHz 83.3333MHz
|
||||
.ad9361_2_clk_3x (ad9361_2_clk_3x ), // 144MHz 125MHz
|
||||
.ad9361_2_clk_4x (ad9361_2_clk_4x ), // 192MHz 166.6667MHz
|
||||
.ad9361_2_clk_ld (ad9361_2_clk_ld ) // ad9361-2 clock group locked indicator
|
||||
);
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
//////////////////////////// Block Design Interface ////////////////////////////
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// gpio
|
||||
wire [47:0] gpio_i;
|
||||
wire [47:0] gpio_o;
|
||||
wire [47:0] gpio_t;
|
||||
|
||||
assign gpio_i[47:36] = gpio_o[47:36];
|
||||
|
||||
// hmc7044
|
||||
assign ad9528_reset_b = gpio_o[ 0]; // ad9528 reset
|
||||
assign ad9528_sysref_req = gpio_o[ 1]; // ad9528 sysref request
|
||||
assign gpio_i[3:2] = ad9528_status;
|
||||
// ad9361-1
|
||||
assign ad9361_1_txnrx = gpio_o[ 4]; // ad9361 enable state machine control
|
||||
assign ad9361_1_enable = gpio_o[ 5]; // ad9361 enable state machine control
|
||||
assign ad9361_1_en_agc = gpio_o[ 6]; // ad9361 agc control
|
||||
assign ad9361_1_reset_b = gpio_o[ 7]; // ad9361 reset
|
||||
assign ad9361_1_ctrl_out = gpio_o[15:8];
|
||||
assign gpio_i[19:16] = ad9361_1_ctrl_in;
|
||||
// ad9361-2
|
||||
assign ad9361_2_txnrx = gpio_o[20]; // ad9361 enable state machine control
|
||||
assign ad9361_2_enable = gpio_o[21]; // ad9361 enable state machine control
|
||||
assign ad9361_2_en_agc = gpio_o[22]; // ad9361 agc control
|
||||
assign ad9361_2_reset_b = gpio_o[23]; // ad9361 reset
|
||||
assign ad9361_2_ctrl_out = gpio_o[31:24];
|
||||
assign gpio_i[35:32] = ad9361_2_ctrl_in;
|
||||
|
||||
// spi interface
|
||||
wire spi_sclk ;
|
||||
wire [ 2:0] spi_cs ;
|
||||
reg spi_sdi ;
|
||||
wire spi_sdo ;
|
||||
wire spi_sdo_t ;
|
||||
wire spi_three_wire;
|
||||
wire spi_active ;
|
||||
|
||||
// hmc7044 - three-wire spi
|
||||
assign ad9528_spi_clk = spi_sclk;
|
||||
assign ad9528_spi_csn = spi_cs[0];
|
||||
assign ad9528_spi_mosi = spi_sdo_t ? 1'bz : spi_sdo;
|
||||
// ad9361-1 - three-wire spi or four-wire spi
|
||||
assign ad9361_1_spi_clk = spi_sclk;
|
||||
assign ad9361_1_spi_csn = spi_cs[1];
|
||||
assign ad9361_1_spi_mosi = spi_sdo_t ? 1'bz : spi_sdo;
|
||||
// ad9361-2 - three-wire spi or four-wire spi
|
||||
assign ad9361_2_spi_clk = spi_sclk;
|
||||
assign ad9361_2_spi_csn = spi_cs[2];
|
||||
assign ad9361_2_spi_mosi = spi_sdo_t ? 1'bz : spi_sdo;
|
||||
// select sdi signal
|
||||
always @(*) begin
|
||||
case ({ad9528_spi_csn,ad9361_1_spi_csn,ad9361_2_spi_csn})
|
||||
3'b011 : spi_sdi = spi_three_wire ? ad9528_spi_mosi : ad9528_spi_miso;
|
||||
3'b101 : spi_sdi = spi_three_wire ? ad9361_1_spi_mosi : ad9361_1_spi_miso;
|
||||
3'b110 : spi_sdi = spi_three_wire ? ad9361_2_spi_mosi : ad9361_2_spi_miso;
|
||||
default: spi_sdi = 1'bz;
|
||||
endcase
|
||||
end
|
||||
|
||||
// ps clock
|
||||
wire ps_clk_50m;
|
||||
wire ps_clk_100m;
|
||||
|
||||
system_bd_wrapper system_bd
|
||||
(
|
||||
// ddr
|
||||
.ddr_addr (ddr_addr ), // inout [14:0]ddr_addr
|
||||
.ddr_ba (ddr_ba ), // inout [2:0]ddr_ba
|
||||
.ddr_cas_n (ddr_cas_n ), // inout ddr_cas_n
|
||||
.ddr_ck_n (ddr_ck_n ), // inout ddr_ck_n
|
||||
.ddr_ck_p (ddr_ck_p ), // inout ddr_ck_p
|
||||
.ddr_cke (ddr_cke ), // inout ddr_cke
|
||||
.ddr_cs_n (ddr_cs_n ), // inout ddr_cs_n
|
||||
.ddr_dm (ddr_dm ), // inout [3:0]ddr_dm
|
||||
.ddr_dq (ddr_dq ), // inout [31:0]ddr_dq
|
||||
.ddr_dqs_n (ddr_dqs_n ), // inout [3:0]ddr_dqs_n
|
||||
.ddr_dqs_p (ddr_dqs_p ), // inout [3:0]ddr_dqs_p
|
||||
.ddr_odt (ddr_odt ), // inout ddr_odt
|
||||
.ddr_ras_n (ddr_ras_n ), // inout ddr_ras_n
|
||||
.ddr_reset_n (ddr_reset_n ), // inout ddr_reset_n
|
||||
.ddr_we_n (ddr_we_n ), // inout ddr_we_n
|
||||
|
||||
// fixed-io
|
||||
.fixed_io_ddr_vrn (fixed_io_ddr_vrn ), // inout fixed_io_ddr_vrn
|
||||
.fixed_io_ddr_vrp (fixed_io_ddr_vrp ), // inout fixed_io_ddr_vrp
|
||||
.fixed_io_mio (fixed_io_mio ), // inout [53:0]fixed_io_mio
|
||||
.fixed_io_ps_clk (fixed_io_ps_clk ), // inout fixed_io_ps_clk
|
||||
.fixed_io_ps_porb (fixed_io_ps_porb ), // inout fixed_io_ps_porb
|
||||
.fixed_io_ps_srstb (fixed_io_ps_srstb ), // inout fixed_io_ps_srstb
|
||||
|
||||
// system monitor
|
||||
.vp_vn_v_p (sysmon_vp ), // input vp_vn_v_p
|
||||
.vp_vn_v_n (sysmon_vn ), // input vp_vn_v_n
|
||||
|
||||
// pjtag
|
||||
.pjtag_tck (pjtag_tck ), // input pjtag_tck
|
||||
.pjtag_tdi (pjtag_tdi ), // input pjtag_tdi
|
||||
.pjtag_tdo (pjtag_tdo ), // output pjtag_tdo
|
||||
.pjtag_tms (pjtag_tms ), // input pjtag_tms
|
||||
|
||||
// gpio, for control signals
|
||||
.gpio_i (gpio_i ), // input [47:0]gpio_i
|
||||
.gpio_o (gpio_o ), // output [47:0]gpio_o
|
||||
.gpio_t (gpio_t ), // output [47:0]gpio_t
|
||||
|
||||
// spi interface
|
||||
.spi_sclk (spi_sclk ), // output spi_sclk
|
||||
.spi_cs (spi_cs ), // output [2:0]spi_cs
|
||||
.spi_sdi (spi_sdi ), // input [0:0]spi_sdi
|
||||
.spi_sdo (spi_sdo ), // output spi_sdo
|
||||
.spi_sdo_t (spi_sdo_t ), // output spi_sdo_t
|
||||
.spi_three_wire (spi_three_wire ), // output spi_three_wire
|
||||
.spi_active (spi_active ), // output spi_active
|
||||
|
||||
// ps clock
|
||||
.ps_clk_50m (ps_clk_50m ), // output ps_clk_50m
|
||||
.ps_clk_100m (ps_clk_100m ) // output ps_clk_100m
|
||||
);
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
////////////////////////////////// Tx Signal ///////////////////////////////////
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// baseband signal
|
||||
wire [11:0] tx1_ch1_i, tx1_ch1_q;
|
||||
wire [11:0] tx1_ch2_i, tx1_ch2_q; // nc when 1t1r is selected
|
||||
wire [11:0] tx2_ch1_i, tx2_ch1_q;
|
||||
wire [11:0] tx2_ch2_i, tx2_ch2_q; // nc when 1t1r is selected
|
||||
|
||||
`ifdef AD9361_1_CMOS_2T2R // define AD9361_1_CMOS_2T2R at top of this file if 2t2r is required
|
||||
ad9361_tx_map_cmos_dual u_ad9361_1_tx_map
|
||||
(
|
||||
.clk_2x_in (ad9361_1_clk_2x ), // input clk_2x_in
|
||||
.clk_in_rst (~ad9361_1_clk_ld ), // input clk_in_rst
|
||||
|
||||
.tx_data_clk (sys_clk ), // input tx_data_clk
|
||||
.tx_data_clk_rst(sys_rst ), // input tx_data_clk_rst
|
||||
|
||||
.tx_ch1_i (tx1_ch1_i ), // input [11:0] tx_ch1_i
|
||||
.tx_ch1_q (tx1_ch1_q ), // input [11:0] tx_ch1_q
|
||||
.tx_ch2_i (tx1_ch2_i ), // input [11:0] tx_ch2_i
|
||||
.tx_ch2_q (tx1_ch2_q ), // input [11:0] tx_ch2_q
|
||||
.clk_out (ad9361_1_tx_fb_clk ), // output clk_out
|
||||
.tx_frame (ad9361_1_tx_frame ), // output tx_frame
|
||||
.tx_data (ad9361_1_tx_data ) // output [11:0] tx_data
|
||||
);
|
||||
`else
|
||||
ad9361_tx_map_cmos_single u_ad9361_1_tx_map
|
||||
(
|
||||
.clk_in (ad9361_1_clk ), // input clk_in
|
||||
.clk_in_rst (~ad9361_1_clk_ld ), // input clk_in_rst
|
||||
|
||||
.tx_data_clk (sys_clk ), // input tx_data_clk
|
||||
.tx_data_clk_rst(sys_rst ), // input tx_data_clk_rst
|
||||
|
||||
.tx_data_i (tx1_ch1_i ), // input [11:0] tx_data_i
|
||||
.tx_data_q (tx1_ch1_q ), // input [11:0] tx_data_q
|
||||
.clk_out (ad9361_1_tx_fb_clk ), // output clk_out
|
||||
.tx_frame (ad9361_1_tx_frame ), // output tx_frame
|
||||
.tx_data (ad9361_1_tx_data ) // output [11:0] tx_data
|
||||
);
|
||||
`endif
|
||||
|
||||
`ifdef AD9361_2_CMOS_2T2R // define AD9361_2_CMOS_2T2R at top of this file if 2t2r is required
|
||||
ad9361_tx_map_cmos_dual u_ad9361_2_tx_map
|
||||
(
|
||||
.clk_2x_in (ad9361_2_clk_2x ), // input clk_2x_in
|
||||
.clk_in_rst (~ad9361_2_clk_ld ), // input clk_in_rst
|
||||
|
||||
.tx_data_clk (sys_clk ), // input tx_data_clk
|
||||
.tx_data_clk_rst(sys_rst ), // input tx_data_clk_rst
|
||||
|
||||
.tx_ch1_i (tx2_ch1_i ), // input [11:0] tx_ch1_i
|
||||
.tx_ch1_q (tx2_ch1_q ), // input [11:0] tx_ch1_q
|
||||
.tx_ch2_i (tx2_ch2_i ), // input [11:0] tx_ch2_i
|
||||
.tx_ch2_q (tx2_ch2_q ), // input [11:0] tx_ch2_q
|
||||
.clk_out (ad9361_2_tx_fb_clk ), // output clk_out
|
||||
.tx_frame (ad9361_2_tx_frame ), // output tx_frame
|
||||
.tx_data (ad9361_2_tx_data ) // output [11:0] tx_data
|
||||
);
|
||||
`else
|
||||
ad9361_tx_map_cmos_single u_ad9361_2_tx_map
|
||||
(
|
||||
.clk_in (ad9361_2_clk ), // input clk_in
|
||||
.clk_in_rst (~ad9361_2_clk_ld ), // input clk_in_rst
|
||||
|
||||
.tx_data_clk (sys_clk ), // input tx_data_clk
|
||||
.tx_data_clk_rst(sys_rst ), // input tx_data_clk_rst
|
||||
|
||||
.tx_data_i (tx2_ch1_i ), // input [11:0] tx_data_i
|
||||
.tx_data_q (tx2_ch1_q ), // input [11:0] tx_data_q
|
||||
.clk_out (ad9361_2_tx_fb_clk ), // output clk_out
|
||||
.tx_frame (ad9361_2_tx_frame ), // output tx_frame
|
||||
.tx_data (ad9361_2_tx_data ) // output [11:0] tx_data
|
||||
);
|
||||
`endif
|
||||
|
||||
// <--------------------------------------------------------------------------->
|
||||
// <--------------------- insert transmitter logic below ---------------------->
|
||||
// <--------------------------------------------------------------------------->
|
||||
wire [11:0] tx_data_i, tx_data_q;
|
||||
wire [ 1:0] waveform_sel;
|
||||
wire sweep_on ;
|
||||
wire [31:0] freq_set ;
|
||||
wire [ 1:0] iq_sel ;
|
||||
wire [ 3:0] bb_rshift ;
|
||||
|
||||
// ad9361-1
|
||||
assign tx1_ch1_i = tx_data_i;
|
||||
assign tx1_ch1_q = tx_data_q;
|
||||
assign tx1_ch2_i = tx_data_i;
|
||||
assign tx1_ch2_q = tx_data_q;
|
||||
// ad9361-2
|
||||
assign tx2_ch1_i = tx_data_i;
|
||||
assign tx2_ch1_q = tx_data_q;
|
||||
assign tx2_ch2_i = tx_data_i;
|
||||
assign tx2_ch2_q = tx_data_q;
|
||||
|
||||
tx_qpsk #(
|
||||
.BIT_DATA (1024'b0000000100100010000011001001101000010010101000011110101110101101101100000000110000011011001100001010110101110001101111110001000111100111101101101000000010100001011010101000111110111100100101100000100110010001010001101101110000001111000111011111110010000110001011011101000011010101100111100101101100100000100010010011000000101100010100111011001110001011111101010001011101101011000011001101101010000011101001111010011010100100111000001111100111001101111010001010101101111100001001110100011101011111011010010000100001010010101100011100111111101100001000110100111001001111000011011101100011000111101111101001001010000001101000110010111010010110100010001011001101001010010001100001110110111100000101110010101110011101110111001100111010101110111101100101000100110110001000011100101111100101001100110010101010011111100110001101011110011010110100110001001011100001011110101010101111111101000001010100101111000101011110111010100110111001000111000111111111100000001110000111111011100010011111000110011111010110010110010010010000000001),
|
||||
.BIT_DATA_LEN (1024),
|
||||
.CLK_FREQ (48000000)
|
||||
) u_tx_qpsk
|
||||
(
|
||||
.clk (sys_clk ), // input clk
|
||||
.rst (sys_rst ), // input rst
|
||||
.tx_data_i (tx_data_i ), // output [11:0] tx_data_i
|
||||
.tx_data_q (tx_data_q ), // output [11:0] tx_data_q
|
||||
// debug ports
|
||||
.waveform_sel (waveform_sel[1:0] ), // input [ 1:0] waveform_sel
|
||||
.sweep_on (sweep_on ), // input sweep_on
|
||||
.freq_set (freq_set ), // input [31:0] freq_set
|
||||
.iq_sel (iq_sel ), // input [ 1:0] iq_sel
|
||||
.bb_rshift (bb_rshift ) // input [ 3:0] bb_rshift
|
||||
);
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
////////////////////////////////// Rx Signals //////////////////////////////////
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
wire [11:0] rx1_ch1_i, rx1_ch1_q;
|
||||
wire [11:0] rx1_ch2_i, rx1_ch2_q; // nc when 1t1r is selected
|
||||
wire [11:0] rx2_ch1_i, rx2_ch1_q;
|
||||
wire [11:0] rx2_ch2_i, rx2_ch2_q; // nc when 1t1r is selected
|
||||
|
||||
`ifdef AD9361_1_CMOS_2T2R // define AD9361_1_CMOS_2T2R at top of this file if 2t2r is required
|
||||
ad9361_rx_map_cmos_dual u_ad9361_1_rx_map
|
||||
(
|
||||
.clk_2x_in (ad9361_1_clk_2x ), // input clk_2x_in
|
||||
.clk_in_rst (~ad9361_1_clk_ld ), // input clk_in_rst
|
||||
|
||||
.rx_data_clk (sys_clk ), // input rx_data_clk
|
||||
.rx_data_clk_rst(sys_rst ), // input rx_data_clk_rst
|
||||
|
||||
.rx_fifo_rst (1'b0 ), // input rx_fifo_rst
|
||||
|
||||
.rx_frame (ad9361_1_rx_frame ), // input rx_frame
|
||||
.rx_data (ad9361_1_rx_data ), // input [11:0] rx_data
|
||||
.rx_ch1_i (rx1_ch1_i ), // output [11:0] rx_ch1_i
|
||||
.rx_ch1_q (rx1_ch1_q ), // output [11:0] rx_ch1_q
|
||||
.rx_ch2_i (rx1_ch2_i ), // output [11:0] rx_ch2_i
|
||||
.rx_ch2_q (rx1_ch2_q ) // output [11:0] rx_ch2_q
|
||||
);
|
||||
`else
|
||||
ad9361_rx_map_cmos_single u_ad9361_1_rx_map
|
||||
(
|
||||
.clk_in (ad9361_1_clk ), // input clk_in
|
||||
.clk_in_rst (~ad9361_1_clk_ld ), // input clk_in_rst
|
||||
|
||||
.rx_data_clk (sys_clk ), // input rx_data_clk
|
||||
.rx_data_clk_rst(sys_rst ), // input rx_data_clk_rst
|
||||
|
||||
.rx_fifo_rst (1'b0 ), // input rx_fifo_rst
|
||||
|
||||
.rx_frame (ad9361_1_rx_frame ), // input rx_frame
|
||||
.rx_data (ad9361_1_rx_data ), // input [11:0] rx_data
|
||||
.rx_data_i (rx1_ch1_i ), // output [11:0] rx_data_i
|
||||
.rx_data_q (rx1_ch1_q ) // output [11:0] rx_data_q
|
||||
);
|
||||
`endif
|
||||
|
||||
`ifdef AD9361_2_CMOS_2T2R // define AD9361_2_CMOS_2T2R at top of this file if 2t2r is required
|
||||
ad9361_rx_map_cmos_dual u_ad9361_2_rx_map
|
||||
(
|
||||
.clk_2x_in (ad9361_2_clk_2x ), // input clk_2x_in
|
||||
.clk_in_rst (~ad9361_2_clk_ld ), // input clk_in_rst
|
||||
|
||||
.rx_data_clk (sys_clk ), // input rx_data_clk
|
||||
.rx_data_clk_rst(sys_rst ), // input rx_data_clk_rst
|
||||
|
||||
.rx_fifo_rst (1'b0 ), // input rx_fifo_rst
|
||||
|
||||
.rx_frame (ad9361_2_rx_frame ), // input rx_frame
|
||||
.rx_data (ad9361_2_rx_data ), // input [11:0] rx_data
|
||||
.rx_ch1_i (rx2_ch1_i ), // output [11:0] rx_ch1_i
|
||||
.rx_ch1_q (rx2_ch1_q ), // output [11:0] rx_ch1_q
|
||||
.rx_ch2_i (rx2_ch2_i ), // output [11:0] rx_ch2_i
|
||||
.rx_ch2_q (rx2_ch2_q ) // output [11:0] rx_ch2_q
|
||||
);
|
||||
`else
|
||||
ad9361_rx_map_cmos_single u_ad9361_2_rx_map
|
||||
(
|
||||
.clk_in (ad9361_2_clk ), // input clk_in
|
||||
.clk_in_rst (~ad9361_2_clk_ld ), // input clk_in_rst
|
||||
|
||||
.rx_data_clk (sys_clk ), // input rx_data_clk
|
||||
.rx_data_clk_rst(sys_rst ), // input rx_data_clk_rst
|
||||
|
||||
.rx_fifo_rst (1'b0 ), // input rx_fifo_rst
|
||||
|
||||
.rx_frame (ad9361_2_rx_frame ), // input rx_frame
|
||||
.rx_data (ad9361_2_rx_data ), // input [11:0] rx_data
|
||||
.rx_data_i (rx2_ch1_i ), // output [11:0] rx_data_i
|
||||
.rx_data_q (rx2_ch1_q ) // output [11:0] rx_data_q
|
||||
);
|
||||
`endif
|
||||
|
||||
// <--------------------------------------------------------------------------->
|
||||
// <----------------------- insert receiver logic below ----------------------->
|
||||
// <--------------------------------------------------------------------------->
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
//////////////////////////////// ILAs and VIOs /////////////////////////////////
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
ila_trx u_ila_trx
|
||||
(
|
||||
.clk (sys_clk ), // input wire clk
|
||||
.probe0 (tx_data_i ), // input wire [11:0] probe0
|
||||
.probe1 (tx_data_q ), // input wire [11:0] probe1
|
||||
.probe2 (rx1_ch1_i ), // input wire [11:0] probe2
|
||||
.probe3 (rx1_ch1_q ), // input wire [11:0] probe3
|
||||
.probe4 (rx1_ch2_i ), // input wire [11:0] probe4
|
||||
.probe5 (rx1_ch2_q ), // input wire [11:0] probe5
|
||||
.probe6 (rx2_ch1_i ), // input wire [11:0] probe6
|
||||
.probe7 (rx2_ch1_q ), // input wire [11:0] probe7
|
||||
.probe8 (rx2_ch2_i ), // input wire [11:0] probe8
|
||||
.probe9 (rx2_ch2_q ) // input wire [11:0] probe9
|
||||
);
|
||||
|
||||
vio_manual_ctrl u_vio_manual_ctrl
|
||||
(
|
||||
.clk (sys_clk ), // input wire clk
|
||||
.probe_out0 (waveform_sel[1:0] ), // output wire [1 : 0] probe_out0
|
||||
.probe_out1 (sweep_on ), // output wire [0 : 0] probe_out1
|
||||
.probe_out2 (freq_set[31:0] ), // output wire [31 : 0] probe_out2
|
||||
.probe_out3 (iq_sel[1:0] ), // output wire [1 : 0] probe_out3
|
||||
.probe_out4 (bb_rshift[3:0] ) // output wire [3 : 0] probe_out4
|
||||
);
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,539 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
// _ _ ____
|
||||
// | | ___ ___| |__ / ___| __ _ ___
|
||||
// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
|
||||
// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
|
||||
// \___/ \___/|___/_| |_| \____|\__,_|\___/
|
||||
//
|
||||
// Create Date: 2022/03/23 20:17:56
|
||||
// Last Modified Date: 2023/03/10 15:41
|
||||
// Design Name:
|
||||
// Module Name: tx_qpsk
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// 20230228-1541 - 修改不扫频、无基带频偏时 [baseband_i/q] 的数据输出，原来从
|
||||
// 乘法器引出，会导致频率为 0 时输出数据错误，现在直接从基带数据引出。
|
||||
// 20230310-1542 - 增加输入参数，发送数据更改为直接由参数输入，发送方波改为 8
|
||||
// 倍过采样，发送双音信号中 1MHz 信号的频率控制字可以根据参数中的时钟频率计
|
||||
// 算得出。
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module tx_qpsk
|
||||
#(
|
||||
parameter DATA_WIDTH = 12, // need to be <= 16
|
||||
parameter BIT_DATA = 128'b00000011000010100011110010001011001110101001111101000011100010010011011010110111101100011010010111011100110010101011111110000001, // inverse pseudorandom bit sequence, [0,flip(PRSB7)]
|
||||
parameter BIT_DATA_LEN = 128,
|
||||
parameter SQUARE_INTERP = 8,
|
||||
parameter CLK_FREQ = 245760000 // in Hertz
|
||||
)
|
||||
(
|
||||
input clk ,
|
||||
input rst ,
|
||||
output [DATA_WIDTH-1:0] tx_data_i ,
|
||||
output [DATA_WIDTH-1:0] tx_data_q ,
|
||||
// debug ports
|
||||
input [ 1:0] waveform_sel ,
|
||||
input sweep_on ,
|
||||
input [31:0] freq_set ,
|
||||
input [ 1:0] iq_sel ,
|
||||
input [ 3:0] bb_rshift
|
||||
);
|
||||
|
||||
localparam RCOS_INTERP = 64;
|
||||
localparam INTERP = (RCOS_INTERP > SQUARE_INTERP) ? RCOS_INTERP : SQUARE_INTERP;
|
||||
localparam FREQ_WORD_1M = 64'd2**64'd32*64'd1000000/CLK_FREQ;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
///////////////////////////////// Data Counter /////////////////////////////////
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// symbol & interpolation counter
|
||||
reg [$clog2(INTERP*BIT_DATA_LEN)-1 : 0] cnt = 'b0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
cnt <= 'b0;
|
||||
end
|
||||
else begin
|
||||
cnt <= (cnt == INTERP*BIT_DATA_LEN - 1) ? 'b0 : cnt + 16'b1;
|
||||
end
|
||||
end
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
////////////////////// Root-Rasied Cosine Shaping Filter ///////////////////////
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// address
|
||||
reg [$clog2(BIT_DATA_LEN)-1 : 0] hrc_data_addr_i = 'b0;
|
||||
reg [$clog2(BIT_DATA_LEN)-1 : 0] hrc_data_addr_q = 'b1;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
hrc_data_addr_i <= 'b0;
|
||||
hrc_data_addr_q <= 'b1;
|
||||
end
|
||||
else begin
|
||||
hrc_data_addr_i <= {cnt[$clog2(RCOS_INTERP) +: ($clog2(BIT_DATA_LEN)-1)],1'b0};
|
||||
hrc_data_addr_q <= {cnt[$clog2(RCOS_INTERP) +: ($clog2(BIT_DATA_LEN)-1)],1'b1};
|
||||
end
|
||||
end
|
||||
|
||||
// bit data
|
||||
reg hrc_data_i = 'b0;
|
||||
reg hrc_data_q = 'b0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
hrc_data_i <= 'b0;
|
||||
hrc_data_q <= 'b0;
|
||||
end
|
||||
else begin
|
||||
hrc_data_i <= BIT_DATA[hrc_data_addr_i];
|
||||
hrc_data_q <= BIT_DATA[hrc_data_addr_q];
|
||||
end
|
||||
end
|
||||
|
||||
// polarization
|
||||
wire [ 7:0] hrc_data_polar_i;
|
||||
wire [ 7:0] hrc_data_polar_q;
|
||||
|
||||
assign hrc_data_polar_i = {{7{hrc_data_i}},1'b1};
|
||||
assign hrc_data_polar_q = {{7{hrc_data_q}},1'b1};
|
||||
|
||||
// root raised cosine shaping-filter
|
||||
wire [23:0] hrc_wave_i;
|
||||
wire [23:0] hrc_wave_q;
|
||||
|
||||
hrc_64_12_025 u_hrc_i (
|
||||
.aclk (clk ), // input wire aclk
|
||||
.s_axis_data_tvalid (~rst ), // input wire s_axis_data_tvalid
|
||||
.s_axis_data_tready ( ), // output wire s_axis_data_tready
|
||||
.s_axis_data_tdata (hrc_data_polar_i ), // input wire [7 : 0] s_axis_data_tdata
|
||||
.m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid
|
||||
.m_axis_data_tdata (hrc_wave_i ) // output wire [23 : 0] m_axis_data_tdata
|
||||
);
|
||||
|
||||
hrc_64_12_025 u_hrc_q (
|
||||
.aclk (clk ), // input wire aclk
|
||||
.s_axis_data_tvalid (~rst ), // input wire s_axis_data_tvalid
|
||||
.s_axis_data_tready ( ), // output wire s_axis_data_tready
|
||||
.s_axis_data_tdata (hrc_data_polar_q ), // input wire [7 : 0] s_axis_data_tdata
|
||||
.m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid
|
||||
.m_axis_data_tdata (hrc_wave_q ) // output wire [23 : 0] m_axis_data_tdata
|
||||
);
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
//////////////////////////// Square Shaping Filter /////////////////////////////
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// address
|
||||
reg [$clog2(BIT_DATA_LEN)-1 : 0] hsq_data_addr = 'b0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
hsq_data_addr <= 'b0;
|
||||
end
|
||||
else
|
||||
hsq_data_addr <= {cnt[$clog2(SQUARE_INTERP) +: $clog2(BIT_DATA_LEN)]};
|
||||
end
|
||||
|
||||
// bit data
|
||||
reg hsq_data = 'b0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
hsq_data <= 'b0;
|
||||
end
|
||||
else begin
|
||||
hsq_data <= BIT_DATA[hsq_data_addr];
|
||||
end
|
||||
end
|
||||
|
||||
// square shaping-filter
|
||||
reg [17:0] hsq_wave_i ='b0;
|
||||
reg [17:0] hsq_wave_q ='b0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
hsq_wave_i <= 'b0;
|
||||
hsq_wave_q <= 'b0;
|
||||
end
|
||||
else begin
|
||||
hsq_wave_i <= hsq_data ? 18'b01_1111_1111_1111_1111 : 18'b10_0000_0000_0000_0001;
|
||||
hsq_wave_q <= hsq_data ? 18'b10_0000_0000_0000_0001 : 18'b01_1111_1111_1111_1111;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/////////////////////////////// Two Tone Siganl ////////////////////////////////
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// cosine wave with freq of 1 MHz
|
||||
wire signed [7:0] cos_1m;
|
||||
wire signed [7:0] sin_1m;
|
||||
|
||||
dds_32b_8b u_dds_1m
|
||||
(
|
||||
.aclk (clk ), // input wire aclk
|
||||
.s_axis_config_tvalid (1'b1 ), // input wire s_axis_config_tvalid
|
||||
.s_axis_config_tdata (FREQ_WORD_1M[31:0] ), // input wire [31 : 0] s_axis_config_tdata
|
||||
.m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid
|
||||
.m_axis_data_tdata ({sin_1m,cos_1m} ) // output wire [15 : 0] m_axis_data_tdata
|
||||
);
|
||||
|
||||
// two-tone signal
|
||||
reg signed [16:0] two_tone_wave_i = 'b0;
|
||||
reg signed [16:0] two_tone_wave_q = 'b0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
two_tone_wave_i <= 'b0;
|
||||
two_tone_wave_q <= 'b0;
|
||||
end
|
||||
else begin
|
||||
two_tone_wave_i <= 17'b0_0111_1111_1111_1111 + {cos_1m[7],cos_1m,8'd0};
|
||||
two_tone_wave_q <= 17'b0 + {sin_1m[7],sin_1m,8'd0};
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
///////////////////// Waveform Selection & Hopping Control /////////////////////
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// baseband signal select
|
||||
reg [17:0] baseband_sel_i = 'b0;
|
||||
reg [17:0] baseband_sel_q = 'b0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
baseband_sel_i <= 'b0;
|
||||
baseband_sel_q <= 'b0;
|
||||
end
|
||||
else begin
|
||||
case (waveform_sel[1:0])
|
||||
2'd0: begin
|
||||
baseband_sel_i <= {hrc_wave_i[16:0],1'b0};
|
||||
baseband_sel_q <= {hrc_wave_q[16:0],1'b0};
|
||||
end
|
||||
2'd1: begin
|
||||
baseband_sel_i <= hsq_wave_i[17:0];
|
||||
baseband_sel_q <= hsq_wave_q[17:0];
|
||||
end
|
||||
2'd2: begin
|
||||
baseband_sel_i <= 18'b01_1111_1111_1111_1111;
|
||||
baseband_sel_q <= 18'b0;
|
||||
end
|
||||
2'd3: begin
|
||||
baseband_sel_i <= {two_tone_wave_i[16:0],1'b0};
|
||||
baseband_sel_q <= {two_tone_wave_q[16:0],1'b0};
|
||||
end
|
||||
default: begin
|
||||
baseband_sel_i <= {hrc_wave_i[16:0],1'b0};
|
||||
baseband_sel_q <= {hrc_wave_q[16:0],1'b0};
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
// hopping control, 3750hop/s
|
||||
reg [23:0] sweep_rom_addr = 'b0;
|
||||
wire [31:0] freq_sweep;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
sweep_rom_addr <= 'b0;
|
||||
end
|
||||
else if (sweep_on) begin
|
||||
sweep_rom_addr <= sweep_rom_addr + 24'b1;
|
||||
end
|
||||
else begin
|
||||
sweep_rom_addr <= 'b0;
|
||||
end
|
||||
end
|
||||
|
||||
hop_rom u_sweep_rom
|
||||
(
|
||||
.clka (clk ), // input wire clka
|
||||
.addra (sweep_rom_addr[23:16] ), // input wire [7 : 0] addra
|
||||
.douta (freq_sweep ) // output wire [31 : 0] douta
|
||||
);
|
||||
|
||||
// choose the actual frequency word
|
||||
reg [31:0] freq_word = 'b0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
freq_word <= 'b0;
|
||||
end
|
||||
else if (sweep_on) begin
|
||||
// frequency sweep
|
||||
freq_word <= freq_sweep;
|
||||
end
|
||||
else begin
|
||||
// normal operation
|
||||
freq_word <= freq_set;
|
||||
end
|
||||
end
|
||||
|
||||
// baseband frequency shift carrier generation
|
||||
wire [ 7:0] cos_dds;
|
||||
wire [ 7:0] sin_dds;
|
||||
reg [ 7:0] cos = 'b0;
|
||||
reg [ 7:0] sin = 'b0;
|
||||
|
||||
dds_32b_8b u_dds_bb_shift (
|
||||
.aclk (clk ), // input wire aclk
|
||||
.s_axis_config_tvalid (~rst ), // input wire s_axis_config_tvalid
|
||||
.s_axis_config_tdata (freq_word ), // input wire [31 : 0] s_axis_config_tdata
|
||||
.m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid
|
||||
.m_axis_data_tdata ({sin_dds,cos_dds}) // output wire [31 : 0] m_axis_data_tdata
|
||||
);
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
cos <= 'b0;
|
||||
sin <= 'b0;
|
||||
end
|
||||
else if (freq_word == 'b0) begin
|
||||
// to make sure the carriers stay at the right position when freq = 0
|
||||
cos <= 8'b0111_1111;
|
||||
sin <= 8'b0111_1111;
|
||||
end
|
||||
else begin
|
||||
cos <= cos_dds;
|
||||
sin <= sin_dds;
|
||||
end
|
||||
end
|
||||
|
||||
// baseband frequency shift modulation
|
||||
wire [47:0] mod_cmpy_a;
|
||||
wire [15:0] mod_cmpy_b;
|
||||
wire [63:0] mod_cmpy_out;
|
||||
|
||||
wire [26:0] baseband_mult_i;
|
||||
wire [26:0] baseband_mult_q;
|
||||
|
||||
assign mod_cmpy_a = {6'b0,baseband_sel_q,6'b0,baseband_sel_i};
|
||||
assign mod_cmpy_b = {-sin,cos};
|
||||
|
||||
assign baseband_mult_i = mod_cmpy_out[58:32];
|
||||
assign baseband_mult_q = mod_cmpy_out[26: 0];
|
||||
|
||||
cmpy_18x8 u_cmpy_18x8
|
||||
(
|
||||
.aclk (clk ), // input wire aclk
|
||||
.s_axis_a_tvalid (1'b1 ), // input wire s_axis_a_tvalid
|
||||
.s_axis_a_tdata (mod_cmpy_a ), // input wire [47 : 0] s_axis_a_tdata
|
||||
.s_axis_b_tvalid (1'b1 ), // input wire s_axis_b_tvalid
|
||||
.s_axis_b_tdata (mod_cmpy_b ), // input wire [15 : 0] s_axis_b_tdata
|
||||
.m_axis_dout_tvalid ( ), // output wire m_axis_dout_tvalid
|
||||
.m_axis_dout_tdata (mod_cmpy_out ) // output wire [63 : 0] m_axis_dout_tdata
|
||||
);
|
||||
|
||||
// truncate to 16-bit
|
||||
reg signed [15:0] baseband_i = 'b0;
|
||||
reg signed [15:0] baseband_q = 'b0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
baseband_i <= 'b0;
|
||||
baseband_q <= 'b0;
|
||||
end
|
||||
else begin
|
||||
case (waveform_sel[1:0])
|
||||
2'd0: begin
|
||||
// scale rasied-cosine-shaped bpsk signal by 1.125 or 1.625
|
||||
baseband_i <= (sweep_on == 0 && freq_set == 0) ? (baseband_sel_i[17 -: 16] + {{3{baseband_sel_i[17]}},baseband_sel_i[17 -: 13]}) : (baseband_mult_i[25:10] + {baseband_mult_i[25],baseband_mult_i[25:11]} + {{3{baseband_mult_i[25]}},baseband_mult_i[25:13]});
|
||||
baseband_q <= (sweep_on == 0 && freq_set == 0) ? (baseband_sel_q[17 -: 16] + {{3{baseband_sel_q[17]}},baseband_sel_q[17 -: 13]}) : (baseband_mult_q[25:10] + {baseband_mult_q[25],baseband_mult_q[25:11]} + {{3{baseband_mult_q[25]}},baseband_mult_q[25:13]});
|
||||
end
|
||||
2'd1: begin
|
||||
baseband_i <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_i[17 -: 16] : (baseband_mult_i[25:10] + {{2{baseband_mult_i[25]}},baseband_mult_i[25:12]});
|
||||
baseband_q <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_q[17 -: 16] : (baseband_mult_q[25:10] + {{2{baseband_mult_q[25]}},baseband_mult_q[25:12]});
|
||||
end
|
||||
2'd2: begin
|
||||
baseband_i <= baseband_mult_i[24:9];
|
||||
baseband_q <= baseband_mult_q[24:9];
|
||||
end
|
||||
2'd3: begin
|
||||
baseband_i <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_i[17 -: 16] : baseband_mult_i[24:9];
|
||||
baseband_q <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_q[17 -: 16] : baseband_mult_q[24:9];
|
||||
end
|
||||
default: begin
|
||||
// scale rasied-cosine-shaped bpsk signal by 1.125
|
||||
baseband_i <= baseband_mult_i[25:10] + {{3{baseband_mult_i[25]}},baseband_mult_i[25:13]};
|
||||
baseband_q <= baseband_mult_q[25:10] + {{3{baseband_mult_q[25]}},baseband_mult_q[25:13]};
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
// iq selection & baseband right shift
|
||||
reg signed [15:0] baseband_data_i = 'b0;
|
||||
reg signed [15:0] baseband_data_q = 'b0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
baseband_data_i <= 'b0;
|
||||
baseband_data_q <= 'b0;
|
||||
end
|
||||
else begin
|
||||
// inphase selection
|
||||
if (iq_sel[1]) begin
|
||||
baseband_data_i <= baseband_i >>> bb_rshift;
|
||||
end
|
||||
else begin
|
||||
baseband_data_i <= 'b0;
|
||||
end
|
||||
// quadrature selection
|
||||
if (iq_sel[0]) begin
|
||||
baseband_data_q <= baseband_q >>> bb_rshift;
|
||||
end
|
||||
else begin
|
||||
baseband_data_q <= 'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// output data to ports
|
||||
assign tx_data_i = baseband_data_i[15 -: DATA_WIDTH];
|
||||
assign tx_data_q = baseband_data_q[15 -: DATA_WIDTH];
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2020/12/08 12:43:46
|
||||
// Design Name:
|
||||
// Module Name: tb_tx_qpsk
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
// module tb_tx_qpsk;
|
||||
|
||||
// reg clk = 1'b0 ;
|
||||
// reg rst = 1'b1 ;
|
||||
// reg tx_on = 1'b1 ;
|
||||
// reg [31:0] freq_set ;
|
||||
// reg [ 1:0] waveform_sel = 2'b00;
|
||||
// reg [ 1:0] iq_sel = 2'b11 ;
|
||||
// wire [11:0] tx_data_i ;
|
||||
// wire [11:0] tx_data_q ;
|
||||
// reg [ 3:0] bb_rshift = 5'b0 ;
|
||||
|
||||
// tx_qpsk u_tx_qpsk
|
||||
// (
|
||||
// .clk (clk ),
|
||||
// .rst (rst ),
|
||||
// .tx_data_i (tx_data_i ),
|
||||
// .tx_data_q (tx_data_q ),
|
||||
// .waveform_sel (waveform_sel ),
|
||||
// .sweep_on (1'b0 ),
|
||||
// // .freq_set (32'd447392426 ),
|
||||
// .freq_set (32'd0 ),
|
||||
// .iq_sel (iq_sel ),
|
||||
// .bb_rshift (bb_rshift )
|
||||
// );
|
||||
|
||||
// initial begin
|
||||
// #102
|
||||
// rst = 1'b0;
|
||||
// // freq_set = 32'd873813333;
|
||||
// // waveform_sel = 2'b00;
|
||||
// // bb_rshift = 5'd0;
|
||||
// // #5000
|
||||
// // bb_rshift = 5'd1;
|
||||
// // #5000
|
||||
// // bb_rshift = 5'd2;
|
||||
// // #5000
|
||||
// // bb_rshift = 5'd3;
|
||||
// // #5000
|
||||
// // bb_rshift = 5'd4;
|
||||
// // #5000
|
||||
// // bb_rshift = 5'd5;
|
||||
// // #5000
|
||||
// // bb_rshift = 5'd6;
|
||||
// // #5000
|
||||
// // bb_rshift = 5'd7;
|
||||
// // #5000
|
||||
// // bb_rshift = 5'd8;
|
||||
// // #5000
|
||||
// // bb_rshift = 5'd9;
|
||||
// // #5000
|
||||
// // bb_rshift = 5'd14;
|
||||
// // #5000
|
||||
// // bb_rshift = 5'd15;
|
||||
// // #5000
|
||||
// // bb_rshift = 5'd16;
|
||||
// // freq_set = 32'd0;
|
||||
// // func_sel = 3'b010;
|
||||
// // #7777
|
||||
// // freq_set = 32'd536870912;
|
||||
// // func_sel = 3'b100;
|
||||
// // #7777
|
||||
// // freq_set = 32'd0;
|
||||
// // func_sel = 3'b100;
|
||||
// // #7777
|
||||
// // freq_set = 32'd536870912;
|
||||
// // func_sel = 3'b010;
|
||||
// // #7777
|
||||
// // freq_set = 32'd0;
|
||||
// // func_sel = 3'b010;
|
||||
// // freq_set = 32'd536870912;
|
||||
// // iq_sel = 2'b00;
|
||||
// // #7777
|
||||
// // freq_set = 32'd536870912;
|
||||
// // iq_sel = 2'b01;
|
||||
// // #7777
|
||||
// // freq_set = 32'd536870912;
|
||||
// // iq_sel = 2'b10;
|
||||
// // #7777
|
||||
// // freq_set = 32'd536870912;
|
||||
// // iq_sel = 2'b11;
|
||||
// end
|
||||
|
||||
// always #5 clk = ~clk;
|
||||
|
||||
// // integer i;
|
||||
// // integer w_file;
|
||||
|
||||
// // initial begin
|
||||
// // w_file = $fopen("D:\\qpsk_josh.txt","w");
|
||||
// // for (i = 0; i <= 35000; i = i + 1) begin
|
||||
// // wait(clk);
|
||||
// // #10;
|
||||
// // $fdisplay(w_file,"%d %d",$signed(tx_data_i),
|
||||
// // $signed(tx_data_q));
|
||||
// // if (i == 35000) begin
|
||||
// // $fclose(w_file);
|
||||
// // $stop;
|
||||
// // end
|
||||
// // end
|
||||
// // end
|
||||
|
||||
// endmodule
|
||||
Reference in New Issue
Block a user