feat: 更新软件版本至2024.1
This commit is contained in:
@@ -0,0 +1,19 @@
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# Xilinx files
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||||
*.xsa filter=lfs diff=lfs merge=lfs -text
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||||
*.bit filter=lfs diff=lfs merge=lfs -text
|
||||
*.bin filter=lfs diff=lfs merge=lfs -text
|
||||
*.dcp filter=lfs diff=lfs merge=lfs -text
|
||||
# data files
|
||||
*.csv filter=lfs diff=lfs merge=lfs -text
|
||||
# board files
|
||||
*.brd filter=lfs diff=lfs merge=lfs -text
|
||||
*.dsn filter=lfs diff=lfs merge=lfs -text
|
||||
# archive files
|
||||
*.zip filter=lfs diff=lfs merge=lfs -text
|
||||
*.rar filter=lfs diff=lfs merge=lfs -text
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||||
*.tar filter=lfs diff=lfs merge=lfs -text
|
||||
*.gz filter=lfs diff=lfs merge=lfs -text
|
||||
*.xz filter=lfs diff=lfs merge=lfs -text
|
||||
*.7z filter=lfs diff=lfs merge=lfs -text
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||||
# others
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||||
*.pdf filter=lfs diff=lfs merge=lfs -text
|
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@@ -0,0 +1,3 @@
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[submodule "scripts"]
|
||||
path = scripts
|
||||
url = https://git.gatsby.icu/gatsby/embedded-autobuild
|
||||
Submodule
+1
Submodule scripts added at af260c1610
@@ -0,0 +1,119 @@
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################################################################################
|
||||
############################### Project Specific ###############################
|
||||
################################################################################
|
||||
# everything
|
||||
*
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||||
|
||||
# git related
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||||
!/.gitignore
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||||
!/.gitattributes
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||||
|
||||
# project documents
|
||||
!/*.md
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||||
!/*.txt
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||||
|
||||
################################################################################
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||||
############################### Vivado Specific ################################
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||||
################################################################################
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||||
|
||||
# xpr: needed for recreating design
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||||
!/*.xpr
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||||
|
||||
# source: include everything
|
||||
!/*.srcs/
|
||||
!/*.srcs/**/*
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||||
|
||||
# runs: exclude everything but design run results
|
||||
!/*.runs/
|
||||
!/*.runs/impl_*/
|
||||
!/*.runs/impl_*/*.bit
|
||||
!/*.runs/impl_*/*.ltx
|
||||
|
||||
# xsa (Xilinx support archive): include for ps
|
||||
!/*.xsa
|
||||
|
||||
################################################################################
|
||||
################################ Vitis Specific ################################
|
||||
################################################################################
|
||||
|
||||
# include sdk directory and everything in it
|
||||
!/vitis*/
|
||||
!/vitis*/**
|
||||
/vitis*/**.log
|
||||
/vitis*/.analytics
|
||||
|
||||
# exclude some obscure hidden SDK folders
|
||||
/vitis*/.metadata/
|
||||
/vitis*/.sdk/
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||||
/vitis*/RemoteSystemsTempFiles/
|
||||
/vitis*/webtalk/
|
||||
|
||||
# hw_platform: exclude the entire hw_platform folder, as everything can be
|
||||
# generated from the .hdf file. Make sure to include the bitstream in the .hdf
|
||||
# file when exporting from Vivado!
|
||||
/vitis*/*_hw_platform_*/
|
||||
|
||||
# BSP: only keep `.cproject`, `.project`, `.sdkproject`, `.system.mss` and
|
||||
# Makefile, ps lib files are regenerated automatically
|
||||
/vitis*/*_bsp/*
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||||
!/vitis*/*_bsp/*.cproject
|
||||
!/vitis*/*_bsp/*.project
|
||||
!/vitis*/*_bsp/*.sdkproject
|
||||
!/vitis*/*_bsp/system.mss
|
||||
!/vitis*/*_bsp/Makefile
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||||
|
||||
# Application: ignored file patterns, exclude Debug & Release folders
|
||||
/vitis*/**/*.o
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||||
/vitis*/**/*.d
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||||
/vitis*/**/*.a
|
||||
/vitis*/*/Debug/
|
||||
/vitis*/*/Release/
|
||||
|
||||
################################################################################
|
||||
############################ Vivado & Vitis Common #############################
|
||||
################################################################################
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||||
|
||||
# file patterns that should always be ignored (journal files, log files, dump
|
||||
# files that are created upon Vivado/SDK errors)
|
||||
*.jou
|
||||
*.log
|
||||
*.backup.jou
|
||||
*.backup.log
|
||||
*.upgrade_log
|
||||
*.dmp
|
||||
*.debug
|
||||
vivado_pid*
|
||||
|
||||
# vivado workspace files
|
||||
xsim.dir/
|
||||
xvlog.pb
|
||||
|
||||
# Xilinx tools generated files
|
||||
.metadata/
|
||||
.settings/
|
||||
.wsdata/
|
||||
.Xil/
|
||||
logs/
|
||||
Packages/
|
||||
*.log*
|
||||
|
||||
# System generated files
|
||||
# -- macOS
|
||||
.DS_Store
|
||||
.AppleDouble
|
||||
.LSOverride
|
||||
._*
|
||||
|
||||
# -- Windows
|
||||
Thumbs.db
|
||||
ehthumbs.db
|
||||
Desktop.ini
|
||||
|
||||
# -- Linux
|
||||
*~
|
||||
|
||||
# IDEs and editors' files
|
||||
*.idea
|
||||
*.vscode
|
||||
*.sublime-workspace
|
||||
*.sublime-project
|
||||
@@ -0,0 +1,37 @@
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# README.md
|
||||
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||||
> Board: SJL_2Z7100-V1_0
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||||
>
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||||
> Device: xc7z100ffg900-2 (U1), ad9528 (U7), ad9361 (u8), ad9361 (u9), ad9653 (u10)
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||||
>
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||||
> Archiver: Josh Gao
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||||
|
||||
## 2024/11/07
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||||
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||||
- 更新软件版本至 `2024.1.2`。
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||||
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||||
- PS 程序改为 HSJL 演示验证版本。
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||||
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||||
## 2024/09/30
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||||
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||||
- PS 增加了 AD9653 的驱动。
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||||
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||||
## 2024/09/29
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||||
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||||
1. 使用 PS 配置 AD9528 和两片 AD9361。
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||||
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||||
2. AD9528 相关
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||||
|
||||
- 使用板上 50 MHz 晶振同时供给 VCO 和 REFA。
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||||
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||||
- AD9661 参考时钟为 40 MHz，其他时钟均为 200 MHz。
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||||
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||||
3. AD9361 配置相关
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||||
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||||
- 第一片默认启用 Rx2A 和 Tx2A，第二片默认启用 RX1A 和 RX2A，因此接收通道仅 `rx_ch2_i/q`、`rx_ch3_i/q` 和 `rx_ch4_i/q` 有数据，具体请结合原理图。
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||||
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||||
- 使用 40 MHz 时钟输入，采样率为 48 Msps，发送频率为 1525 MHz，接收频率为 1525 MHz。
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||||
|
||||
4. PL 相关
|
||||
|
||||
- PL 信号处理时钟 `sys_clk` 在 Clock Wizard 中为 50 MHz，但实际由 AD9361 输入随路时钟生成，频率为 48 MHz。
|
||||
@@ -0,0 +1,796 @@
|
||||
{
|
||||
"ltx_root": {
|
||||
"version": 4,
|
||||
"minor": 0,
|
||||
"ltx_data": [
|
||||
{
|
||||
"name": "EDA_PROBESET",
|
||||
"active": true,
|
||||
"debug_cores": [
|
||||
{
|
||||
"type": "XSDB_V3",
|
||||
"name": "dbg_hub",
|
||||
"spec": "labtools_xsdbm_v3",
|
||||
"clk_input_freq_hz": "50000000"
|
||||
},
|
||||
{
|
||||
"type": "ILA_V3",
|
||||
"name": "u_ila_trx",
|
||||
"spec": "labtools_ila_v6",
|
||||
"ipName": "ila",
|
||||
"core_location": {
|
||||
"user_chain": 1,
|
||||
"slave_index": 0,
|
||||
"bscan_switch_index": 0
|
||||
},
|
||||
"uuid": "B4AD3E48EFE85668933E662B3D102FF2",
|
||||
"pins": [
|
||||
{
|
||||
"name": "probe0",
|
||||
"id": 0,
|
||||
"type": "DATA_TRIGGER",
|
||||
"direction": "IN",
|
||||
"isVector": true,
|
||||
"leftIndex": 0,
|
||||
"rightIndex": 11,
|
||||
"portIndex": 0,
|
||||
"nets": [
|
||||
{
|
||||
"name": "tx_data_i",
|
||||
"isBus": true,
|
||||
"subnets": [
|
||||
{
|
||||
"name": "tx_data_i[11]"
|
||||
},
|
||||
{
|
||||
"name": "tx_data_i[10]"
|
||||
},
|
||||
{
|
||||
"name": "tx_data_i[9]"
|
||||
},
|
||||
{
|
||||
"name": "tx_data_i[8]"
|
||||
},
|
||||
{
|
||||
"name": "tx_data_i[7]"
|
||||
},
|
||||
{
|
||||
"name": "tx_data_i[6]"
|
||||
},
|
||||
{
|
||||
"name": "tx_data_i[5]"
|
||||
},
|
||||
{
|
||||
"name": "tx_data_i[4]"
|
||||
},
|
||||
{
|
||||
"name": "tx_data_i[3]"
|
||||
},
|
||||
{
|
||||
"name": "tx_data_i[2]"
|
||||
},
|
||||
{
|
||||
"name": "tx_data_i[1]"
|
||||
},
|
||||
{
|
||||
"name": "tx_data_i[0]"
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
},
|
||||
{
|
||||
"name": "probe1",
|
||||
"id": 1,
|
||||
"type": "DATA_TRIGGER",
|
||||
"direction": "IN",
|
||||
"isVector": true,
|
||||
"leftIndex": 0,
|
||||
"rightIndex": 11,
|
||||
"portIndex": 1,
|
||||
"nets": [
|
||||
{
|
||||
"name": "tx_data_q",
|
||||
"isBus": true,
|
||||
"subnets": [
|
||||
{
|
||||
"name": "tx_data_q[11]"
|
||||
},
|
||||
{
|
||||
"name": "tx_data_q[10]"
|
||||
},
|
||||
{
|
||||
"name": "tx_data_q[9]"
|
||||
},
|
||||
{
|
||||
"name": "tx_data_q[8]"
|
||||
},
|
||||
{
|
||||
"name": "tx_data_q[7]"
|
||||
},
|
||||
{
|
||||
"name": "tx_data_q[6]"
|
||||
},
|
||||
{
|
||||
"name": "tx_data_q[5]"
|
||||
},
|
||||
{
|
||||
"name": "tx_data_q[4]"
|
||||
},
|
||||
{
|
||||
"name": "tx_data_q[3]"
|
||||
},
|
||||
{
|
||||
"name": "tx_data_q[2]"
|
||||
},
|
||||
{
|
||||
"name": "tx_data_q[1]"
|
||||
},
|
||||
{
|
||||
"name": "tx_data_q[0]"
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
},
|
||||
{
|
||||
"name": "probe2",
|
||||
"id": 2,
|
||||
"type": "DATA_TRIGGER",
|
||||
"direction": "IN",
|
||||
"isVector": true,
|
||||
"leftIndex": 0,
|
||||
"rightIndex": 11,
|
||||
"portIndex": 2,
|
||||
"nets": [
|
||||
{
|
||||
"name": "rx1_ch1_i",
|
||||
"isBus": true,
|
||||
"subnets": [
|
||||
{
|
||||
"name": "rx1_ch1_i[11]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch1_i[10]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch1_i[9]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch1_i[8]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch1_i[7]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch1_i[6]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch1_i[5]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch1_i[4]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch1_i[3]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch1_i[2]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch1_i[1]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch1_i[0]"
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
},
|
||||
{
|
||||
"name": "probe3",
|
||||
"id": 3,
|
||||
"type": "DATA_TRIGGER",
|
||||
"direction": "IN",
|
||||
"isVector": true,
|
||||
"leftIndex": 0,
|
||||
"rightIndex": 11,
|
||||
"portIndex": 3,
|
||||
"nets": [
|
||||
{
|
||||
"name": "rx1_ch1_q",
|
||||
"isBus": true,
|
||||
"subnets": [
|
||||
{
|
||||
"name": "rx1_ch1_q[11]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch1_q[10]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch1_q[9]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch1_q[8]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch1_q[7]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch1_q[6]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch1_q[5]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch1_q[4]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch1_q[3]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch1_q[2]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch1_q[1]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch1_q[0]"
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
},
|
||||
{
|
||||
"name": "probe4",
|
||||
"id": 4,
|
||||
"type": "DATA_TRIGGER",
|
||||
"direction": "IN",
|
||||
"isVector": true,
|
||||
"leftIndex": 0,
|
||||
"rightIndex": 11,
|
||||
"portIndex": 4,
|
||||
"nets": [
|
||||
{
|
||||
"name": "rx1_ch2_i",
|
||||
"isBus": true,
|
||||
"subnets": [
|
||||
{
|
||||
"name": "rx1_ch2_i[11]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch2_i[10]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch2_i[9]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch2_i[8]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch2_i[7]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch2_i[6]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch2_i[5]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch2_i[4]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch2_i[3]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch2_i[2]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch2_i[1]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch2_i[0]"
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
},
|
||||
{
|
||||
"name": "probe5",
|
||||
"id": 5,
|
||||
"type": "DATA_TRIGGER",
|
||||
"direction": "IN",
|
||||
"isVector": true,
|
||||
"leftIndex": 0,
|
||||
"rightIndex": 11,
|
||||
"portIndex": 5,
|
||||
"nets": [
|
||||
{
|
||||
"name": "rx1_ch2_q",
|
||||
"isBus": true,
|
||||
"subnets": [
|
||||
{
|
||||
"name": "rx1_ch2_q[11]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch2_q[10]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch2_q[9]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch2_q[8]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch2_q[7]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch2_q[6]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch2_q[5]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch2_q[4]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch2_q[3]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch2_q[2]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch2_q[1]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch2_q[0]"
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
},
|
||||
{
|
||||
"name": "probe6",
|
||||
"id": 6,
|
||||
"type": "DATA_TRIGGER",
|
||||
"direction": "IN",
|
||||
"isVector": true,
|
||||
"leftIndex": 0,
|
||||
"rightIndex": 11,
|
||||
"portIndex": 6,
|
||||
"nets": [
|
||||
{
|
||||
"name": "rx2_ch1_i",
|
||||
"isBus": true,
|
||||
"subnets": [
|
||||
{
|
||||
"name": "rx2_ch1_i[11]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch1_i[10]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch1_i[9]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch1_i[8]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch1_i[7]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch1_i[6]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch1_i[5]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch1_i[4]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch1_i[3]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch1_i[2]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch1_i[1]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch1_i[0]"
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
},
|
||||
{
|
||||
"name": "probe7",
|
||||
"id": 7,
|
||||
"type": "DATA_TRIGGER",
|
||||
"direction": "IN",
|
||||
"isVector": true,
|
||||
"leftIndex": 0,
|
||||
"rightIndex": 11,
|
||||
"portIndex": 7,
|
||||
"nets": [
|
||||
{
|
||||
"name": "rx2_ch1_q",
|
||||
"isBus": true,
|
||||
"subnets": [
|
||||
{
|
||||
"name": "rx2_ch1_q[11]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch1_q[10]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch1_q[9]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch1_q[8]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch1_q[7]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch1_q[6]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch1_q[5]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch1_q[4]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch1_q[3]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch1_q[2]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch1_q[1]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch1_q[0]"
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
},
|
||||
{
|
||||
"name": "probe8",
|
||||
"id": 8,
|
||||
"type": "DATA_TRIGGER",
|
||||
"direction": "IN",
|
||||
"isVector": true,
|
||||
"leftIndex": 0,
|
||||
"rightIndex": 11,
|
||||
"portIndex": 8,
|
||||
"nets": [
|
||||
{
|
||||
"name": "rx2_ch2_i",
|
||||
"isBus": true,
|
||||
"subnets": [
|
||||
{
|
||||
"name": "rx2_ch2_i[11]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch2_i[10]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch2_i[9]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch2_i[8]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch2_i[7]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch2_i[6]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch2_i[5]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch2_i[4]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch2_i[3]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch2_i[2]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch2_i[1]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch2_i[0]"
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
},
|
||||
{
|
||||
"name": "probe9",
|
||||
"id": 9,
|
||||
"type": "DATA_TRIGGER",
|
||||
"direction": "IN",
|
||||
"isVector": true,
|
||||
"leftIndex": 0,
|
||||
"rightIndex": 11,
|
||||
"portIndex": 9,
|
||||
"nets": [
|
||||
{
|
||||
"name": "rx2_ch2_q",
|
||||
"isBus": true,
|
||||
"subnets": [
|
||||
{
|
||||
"name": "rx2_ch2_q[11]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch2_q[10]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch2_q[9]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch2_q[8]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch2_q[7]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch2_q[6]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch2_q[5]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch2_q[4]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch2_q[3]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch2_q[2]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch2_q[1]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch2_q[0]"
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
},
|
||||
{
|
||||
"type": "VIO_V2",
|
||||
"name": "u_vio_manual_ctrl",
|
||||
"spec": "labtools_vio_v3",
|
||||
"ipName": "vio",
|
||||
"core_location": {
|
||||
"user_chain": 1,
|
||||
"slave_index": 1,
|
||||
"bscan_switch_index": 0
|
||||
},
|
||||
"uuid": "6DFBBD640CB857419C054C66C7EA7B27",
|
||||
"pins": [
|
||||
{
|
||||
"name": "probe_out0",
|
||||
"id": 10,
|
||||
"type": "DATA",
|
||||
"direction": "OUT",
|
||||
"isVector": true,
|
||||
"leftIndex": 0,
|
||||
"rightIndex": 1,
|
||||
"portIndex": 0,
|
||||
"nets": [
|
||||
{
|
||||
"name": "waveform_sel",
|
||||
"isBus": true,
|
||||
"subnets": [
|
||||
{
|
||||
"name": "waveform_sel[1]"
|
||||
},
|
||||
{
|
||||
"name": "waveform_sel[0]"
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
},
|
||||
{
|
||||
"name": "probe_out1",
|
||||
"id": 11,
|
||||
"type": "DATA",
|
||||
"direction": "OUT",
|
||||
"isVector": false,
|
||||
"leftIndex": 0,
|
||||
"rightIndex": 0,
|
||||
"portIndex": 1,
|
||||
"nets": [
|
||||
{
|
||||
"name": "sweep_on",
|
||||
"isBus": false
|
||||
}
|
||||
]
|
||||
},
|
||||
{
|
||||
"name": "probe_out2",
|
||||
"id": 12,
|
||||
"type": "DATA",
|
||||
"direction": "OUT",
|
||||
"isVector": true,
|
||||
"leftIndex": 0,
|
||||
"rightIndex": 31,
|
||||
"portIndex": 2,
|
||||
"nets": [
|
||||
{
|
||||
"name": "freq_set",
|
||||
"isBus": true,
|
||||
"subnets": [
|
||||
{
|
||||
"name": "freq_set[31]"
|
||||
},
|
||||
{
|
||||
"name": "freq_set[30]"
|
||||
},
|
||||
{
|
||||
"name": "freq_set[29]"
|
||||
},
|
||||
{
|
||||
"name": "freq_set[28]"
|
||||
},
|
||||
{
|
||||
"name": "freq_set[27]"
|
||||
},
|
||||
{
|
||||
"name": "freq_set[26]"
|
||||
},
|
||||
{
|
||||
"name": "freq_set[25]"
|
||||
},
|
||||
{
|
||||
"name": "freq_set[24]"
|
||||
},
|
||||
{
|
||||
"name": "freq_set[23]"
|
||||
},
|
||||
{
|
||||
"name": "freq_set[22]"
|
||||
},
|
||||
{
|
||||
"name": "freq_set[21]"
|
||||
},
|
||||
{
|
||||
"name": "freq_set[20]"
|
||||
},
|
||||
{
|
||||
"name": "freq_set[19]"
|
||||
},
|
||||
{
|
||||
"name": "freq_set[18]"
|
||||
},
|
||||
{
|
||||
"name": "freq_set[17]"
|
||||
},
|
||||
{
|
||||
"name": "freq_set[16]"
|
||||
},
|
||||
{
|
||||
"name": "freq_set[15]"
|
||||
},
|
||||
{
|
||||
"name": "freq_set[14]"
|
||||
},
|
||||
{
|
||||
"name": "freq_set[13]"
|
||||
},
|
||||
{
|
||||
"name": "freq_set[12]"
|
||||
},
|
||||
{
|
||||
"name": "freq_set[11]"
|
||||
},
|
||||
{
|
||||
"name": "freq_set[10]"
|
||||
},
|
||||
{
|
||||
"name": "freq_set[9]"
|
||||
},
|
||||
{
|
||||
"name": "freq_set[8]"
|
||||
},
|
||||
{
|
||||
"name": "freq_set[7]"
|
||||
},
|
||||
{
|
||||
"name": "freq_set[6]"
|
||||
},
|
||||
{
|
||||
"name": "freq_set[5]"
|
||||
},
|
||||
{
|
||||
"name": "freq_set[4]"
|
||||
},
|
||||
{
|
||||
"name": "freq_set[3]"
|
||||
},
|
||||
{
|
||||
"name": "freq_set[2]"
|
||||
},
|
||||
{
|
||||
"name": "freq_set[1]"
|
||||
},
|
||||
{
|
||||
"name": "freq_set[0]"
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
},
|
||||
{
|
||||
"name": "probe_out3",
|
||||
"id": 13,
|
||||
"type": "DATA",
|
||||
"direction": "OUT",
|
||||
"isVector": true,
|
||||
"leftIndex": 0,
|
||||
"rightIndex": 1,
|
||||
"portIndex": 3,
|
||||
"nets": [
|
||||
{
|
||||
"name": "iq_sel",
|
||||
"isBus": true,
|
||||
"subnets": [
|
||||
{
|
||||
"name": "iq_sel[1]"
|
||||
},
|
||||
{
|
||||
"name": "iq_sel[0]"
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
},
|
||||
{
|
||||
"name": "probe_out4",
|
||||
"id": 14,
|
||||
"type": "DATA",
|
||||
"direction": "OUT",
|
||||
"isVector": true,
|
||||
"leftIndex": 0,
|
||||
"rightIndex": 3,
|
||||
"portIndex": 4,
|
||||
"nets": [
|
||||
{
|
||||
"name": "bb_rshift",
|
||||
"isBus": true,
|
||||
"subnets": [
|
||||
{
|
||||
"name": "bb_rshift[3]"
|
||||
},
|
||||
{
|
||||
"name": "bb_rshift[2]"
|
||||
},
|
||||
{
|
||||
"name": "bb_rshift[1]"
|
||||
},
|
||||
{
|
||||
"name": "bb_rshift[0]"
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
}
|
||||
}
|
||||
Binary file not shown.
@@ -0,0 +1,796 @@
|
||||
{
|
||||
"ltx_root": {
|
||||
"version": 4,
|
||||
"minor": 0,
|
||||
"ltx_data": [
|
||||
{
|
||||
"name": "EDA_PROBESET",
|
||||
"active": true,
|
||||
"debug_cores": [
|
||||
{
|
||||
"type": "XSDB_V3",
|
||||
"name": "dbg_hub",
|
||||
"spec": "labtools_xsdbm_v3",
|
||||
"clk_input_freq_hz": "50000000"
|
||||
},
|
||||
{
|
||||
"type": "ILA_V3",
|
||||
"name": "u_ila_trx",
|
||||
"spec": "labtools_ila_v6",
|
||||
"ipName": "ila",
|
||||
"core_location": {
|
||||
"user_chain": 1,
|
||||
"slave_index": 0,
|
||||
"bscan_switch_index": 0
|
||||
},
|
||||
"uuid": "B4AD3E48EFE85668933E662B3D102FF2",
|
||||
"pins": [
|
||||
{
|
||||
"name": "probe0",
|
||||
"id": 0,
|
||||
"type": "DATA_TRIGGER",
|
||||
"direction": "IN",
|
||||
"isVector": true,
|
||||
"leftIndex": 0,
|
||||
"rightIndex": 11,
|
||||
"portIndex": 0,
|
||||
"nets": [
|
||||
{
|
||||
"name": "tx_data_i",
|
||||
"isBus": true,
|
||||
"subnets": [
|
||||
{
|
||||
"name": "tx_data_i[11]"
|
||||
},
|
||||
{
|
||||
"name": "tx_data_i[10]"
|
||||
},
|
||||
{
|
||||
"name": "tx_data_i[9]"
|
||||
},
|
||||
{
|
||||
"name": "tx_data_i[8]"
|
||||
},
|
||||
{
|
||||
"name": "tx_data_i[7]"
|
||||
},
|
||||
{
|
||||
"name": "tx_data_i[6]"
|
||||
},
|
||||
{
|
||||
"name": "tx_data_i[5]"
|
||||
},
|
||||
{
|
||||
"name": "tx_data_i[4]"
|
||||
},
|
||||
{
|
||||
"name": "tx_data_i[3]"
|
||||
},
|
||||
{
|
||||
"name": "tx_data_i[2]"
|
||||
},
|
||||
{
|
||||
"name": "tx_data_i[1]"
|
||||
},
|
||||
{
|
||||
"name": "tx_data_i[0]"
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
},
|
||||
{
|
||||
"name": "probe1",
|
||||
"id": 1,
|
||||
"type": "DATA_TRIGGER",
|
||||
"direction": "IN",
|
||||
"isVector": true,
|
||||
"leftIndex": 0,
|
||||
"rightIndex": 11,
|
||||
"portIndex": 1,
|
||||
"nets": [
|
||||
{
|
||||
"name": "tx_data_q",
|
||||
"isBus": true,
|
||||
"subnets": [
|
||||
{
|
||||
"name": "tx_data_q[11]"
|
||||
},
|
||||
{
|
||||
"name": "tx_data_q[10]"
|
||||
},
|
||||
{
|
||||
"name": "tx_data_q[9]"
|
||||
},
|
||||
{
|
||||
"name": "tx_data_q[8]"
|
||||
},
|
||||
{
|
||||
"name": "tx_data_q[7]"
|
||||
},
|
||||
{
|
||||
"name": "tx_data_q[6]"
|
||||
},
|
||||
{
|
||||
"name": "tx_data_q[5]"
|
||||
},
|
||||
{
|
||||
"name": "tx_data_q[4]"
|
||||
},
|
||||
{
|
||||
"name": "tx_data_q[3]"
|
||||
},
|
||||
{
|
||||
"name": "tx_data_q[2]"
|
||||
},
|
||||
{
|
||||
"name": "tx_data_q[1]"
|
||||
},
|
||||
{
|
||||
"name": "tx_data_q[0]"
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
},
|
||||
{
|
||||
"name": "probe2",
|
||||
"id": 2,
|
||||
"type": "DATA_TRIGGER",
|
||||
"direction": "IN",
|
||||
"isVector": true,
|
||||
"leftIndex": 0,
|
||||
"rightIndex": 11,
|
||||
"portIndex": 2,
|
||||
"nets": [
|
||||
{
|
||||
"name": "rx1_ch1_i",
|
||||
"isBus": true,
|
||||
"subnets": [
|
||||
{
|
||||
"name": "rx1_ch1_i[11]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch1_i[10]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch1_i[9]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch1_i[8]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch1_i[7]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch1_i[6]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch1_i[5]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch1_i[4]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch1_i[3]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch1_i[2]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch1_i[1]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch1_i[0]"
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
},
|
||||
{
|
||||
"name": "probe3",
|
||||
"id": 3,
|
||||
"type": "DATA_TRIGGER",
|
||||
"direction": "IN",
|
||||
"isVector": true,
|
||||
"leftIndex": 0,
|
||||
"rightIndex": 11,
|
||||
"portIndex": 3,
|
||||
"nets": [
|
||||
{
|
||||
"name": "rx1_ch1_q",
|
||||
"isBus": true,
|
||||
"subnets": [
|
||||
{
|
||||
"name": "rx1_ch1_q[11]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch1_q[10]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch1_q[9]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch1_q[8]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch1_q[7]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch1_q[6]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch1_q[5]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch1_q[4]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch1_q[3]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch1_q[2]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch1_q[1]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch1_q[0]"
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
},
|
||||
{
|
||||
"name": "probe4",
|
||||
"id": 4,
|
||||
"type": "DATA_TRIGGER",
|
||||
"direction": "IN",
|
||||
"isVector": true,
|
||||
"leftIndex": 0,
|
||||
"rightIndex": 11,
|
||||
"portIndex": 4,
|
||||
"nets": [
|
||||
{
|
||||
"name": "rx1_ch2_i",
|
||||
"isBus": true,
|
||||
"subnets": [
|
||||
{
|
||||
"name": "rx1_ch2_i[11]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch2_i[10]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch2_i[9]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch2_i[8]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch2_i[7]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch2_i[6]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch2_i[5]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch2_i[4]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch2_i[3]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch2_i[2]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch2_i[1]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch2_i[0]"
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
},
|
||||
{
|
||||
"name": "probe5",
|
||||
"id": 5,
|
||||
"type": "DATA_TRIGGER",
|
||||
"direction": "IN",
|
||||
"isVector": true,
|
||||
"leftIndex": 0,
|
||||
"rightIndex": 11,
|
||||
"portIndex": 5,
|
||||
"nets": [
|
||||
{
|
||||
"name": "rx1_ch2_q",
|
||||
"isBus": true,
|
||||
"subnets": [
|
||||
{
|
||||
"name": "rx1_ch2_q[11]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch2_q[10]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch2_q[9]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch2_q[8]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch2_q[7]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch2_q[6]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch2_q[5]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch2_q[4]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch2_q[3]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch2_q[2]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch2_q[1]"
|
||||
},
|
||||
{
|
||||
"name": "rx1_ch2_q[0]"
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
},
|
||||
{
|
||||
"name": "probe6",
|
||||
"id": 6,
|
||||
"type": "DATA_TRIGGER",
|
||||
"direction": "IN",
|
||||
"isVector": true,
|
||||
"leftIndex": 0,
|
||||
"rightIndex": 11,
|
||||
"portIndex": 6,
|
||||
"nets": [
|
||||
{
|
||||
"name": "rx2_ch1_i",
|
||||
"isBus": true,
|
||||
"subnets": [
|
||||
{
|
||||
"name": "rx2_ch1_i[11]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch1_i[10]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch1_i[9]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch1_i[8]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch1_i[7]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch1_i[6]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch1_i[5]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch1_i[4]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch1_i[3]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch1_i[2]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch1_i[1]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch1_i[0]"
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
},
|
||||
{
|
||||
"name": "probe7",
|
||||
"id": 7,
|
||||
"type": "DATA_TRIGGER",
|
||||
"direction": "IN",
|
||||
"isVector": true,
|
||||
"leftIndex": 0,
|
||||
"rightIndex": 11,
|
||||
"portIndex": 7,
|
||||
"nets": [
|
||||
{
|
||||
"name": "rx2_ch1_q",
|
||||
"isBus": true,
|
||||
"subnets": [
|
||||
{
|
||||
"name": "rx2_ch1_q[11]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch1_q[10]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch1_q[9]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch1_q[8]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch1_q[7]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch1_q[6]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch1_q[5]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch1_q[4]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch1_q[3]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch1_q[2]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch1_q[1]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch1_q[0]"
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
},
|
||||
{
|
||||
"name": "probe8",
|
||||
"id": 8,
|
||||
"type": "DATA_TRIGGER",
|
||||
"direction": "IN",
|
||||
"isVector": true,
|
||||
"leftIndex": 0,
|
||||
"rightIndex": 11,
|
||||
"portIndex": 8,
|
||||
"nets": [
|
||||
{
|
||||
"name": "rx2_ch2_i",
|
||||
"isBus": true,
|
||||
"subnets": [
|
||||
{
|
||||
"name": "rx2_ch2_i[11]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch2_i[10]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch2_i[9]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch2_i[8]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch2_i[7]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch2_i[6]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch2_i[5]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch2_i[4]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch2_i[3]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch2_i[2]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch2_i[1]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch2_i[0]"
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
},
|
||||
{
|
||||
"name": "probe9",
|
||||
"id": 9,
|
||||
"type": "DATA_TRIGGER",
|
||||
"direction": "IN",
|
||||
"isVector": true,
|
||||
"leftIndex": 0,
|
||||
"rightIndex": 11,
|
||||
"portIndex": 9,
|
||||
"nets": [
|
||||
{
|
||||
"name": "rx2_ch2_q",
|
||||
"isBus": true,
|
||||
"subnets": [
|
||||
{
|
||||
"name": "rx2_ch2_q[11]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch2_q[10]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch2_q[9]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch2_q[8]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch2_q[7]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch2_q[6]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch2_q[5]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch2_q[4]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch2_q[3]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch2_q[2]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch2_q[1]"
|
||||
},
|
||||
{
|
||||
"name": "rx2_ch2_q[0]"
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
},
|
||||
{
|
||||
"type": "VIO_V2",
|
||||
"name": "u_vio_manual_ctrl",
|
||||
"spec": "labtools_vio_v3",
|
||||
"ipName": "vio",
|
||||
"core_location": {
|
||||
"user_chain": 1,
|
||||
"slave_index": 1,
|
||||
"bscan_switch_index": 0
|
||||
},
|
||||
"uuid": "6DFBBD640CB857419C054C66C7EA7B27",
|
||||
"pins": [
|
||||
{
|
||||
"name": "probe_out0",
|
||||
"id": 10,
|
||||
"type": "DATA",
|
||||
"direction": "OUT",
|
||||
"isVector": true,
|
||||
"leftIndex": 0,
|
||||
"rightIndex": 1,
|
||||
"portIndex": 0,
|
||||
"nets": [
|
||||
{
|
||||
"name": "waveform_sel",
|
||||
"isBus": true,
|
||||
"subnets": [
|
||||
{
|
||||
"name": "waveform_sel[1]"
|
||||
},
|
||||
{
|
||||
"name": "waveform_sel[0]"
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
},
|
||||
{
|
||||
"name": "probe_out1",
|
||||
"id": 11,
|
||||
"type": "DATA",
|
||||
"direction": "OUT",
|
||||
"isVector": false,
|
||||
"leftIndex": 0,
|
||||
"rightIndex": 0,
|
||||
"portIndex": 1,
|
||||
"nets": [
|
||||
{
|
||||
"name": "sweep_on",
|
||||
"isBus": false
|
||||
}
|
||||
]
|
||||
},
|
||||
{
|
||||
"name": "probe_out2",
|
||||
"id": 12,
|
||||
"type": "DATA",
|
||||
"direction": "OUT",
|
||||
"isVector": true,
|
||||
"leftIndex": 0,
|
||||
"rightIndex": 31,
|
||||
"portIndex": 2,
|
||||
"nets": [
|
||||
{
|
||||
"name": "freq_set",
|
||||
"isBus": true,
|
||||
"subnets": [
|
||||
{
|
||||
"name": "freq_set[31]"
|
||||
},
|
||||
{
|
||||
"name": "freq_set[30]"
|
||||
},
|
||||
{
|
||||
"name": "freq_set[29]"
|
||||
},
|
||||
{
|
||||
"name": "freq_set[28]"
|
||||
},
|
||||
{
|
||||
"name": "freq_set[27]"
|
||||
},
|
||||
{
|
||||
"name": "freq_set[26]"
|
||||
},
|
||||
{
|
||||
"name": "freq_set[25]"
|
||||
},
|
||||
{
|
||||
"name": "freq_set[24]"
|
||||
},
|
||||
{
|
||||
"name": "freq_set[23]"
|
||||
},
|
||||
{
|
||||
"name": "freq_set[22]"
|
||||
},
|
||||
{
|
||||
"name": "freq_set[21]"
|
||||
},
|
||||
{
|
||||
"name": "freq_set[20]"
|
||||
},
|
||||
{
|
||||
"name": "freq_set[19]"
|
||||
},
|
||||
{
|
||||
"name": "freq_set[18]"
|
||||
},
|
||||
{
|
||||
"name": "freq_set[17]"
|
||||
},
|
||||
{
|
||||
"name": "freq_set[16]"
|
||||
},
|
||||
{
|
||||
"name": "freq_set[15]"
|
||||
},
|
||||
{
|
||||
"name": "freq_set[14]"
|
||||
},
|
||||
{
|
||||
"name": "freq_set[13]"
|
||||
},
|
||||
{
|
||||
"name": "freq_set[12]"
|
||||
},
|
||||
{
|
||||
"name": "freq_set[11]"
|
||||
},
|
||||
{
|
||||
"name": "freq_set[10]"
|
||||
},
|
||||
{
|
||||
"name": "freq_set[9]"
|
||||
},
|
||||
{
|
||||
"name": "freq_set[8]"
|
||||
},
|
||||
{
|
||||
"name": "freq_set[7]"
|
||||
},
|
||||
{
|
||||
"name": "freq_set[6]"
|
||||
},
|
||||
{
|
||||
"name": "freq_set[5]"
|
||||
},
|
||||
{
|
||||
"name": "freq_set[4]"
|
||||
},
|
||||
{
|
||||
"name": "freq_set[3]"
|
||||
},
|
||||
{
|
||||
"name": "freq_set[2]"
|
||||
},
|
||||
{
|
||||
"name": "freq_set[1]"
|
||||
},
|
||||
{
|
||||
"name": "freq_set[0]"
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
},
|
||||
{
|
||||
"name": "probe_out3",
|
||||
"id": 13,
|
||||
"type": "DATA",
|
||||
"direction": "OUT",
|
||||
"isVector": true,
|
||||
"leftIndex": 0,
|
||||
"rightIndex": 1,
|
||||
"portIndex": 3,
|
||||
"nets": [
|
||||
{
|
||||
"name": "iq_sel",
|
||||
"isBus": true,
|
||||
"subnets": [
|
||||
{
|
||||
"name": "iq_sel[1]"
|
||||
},
|
||||
{
|
||||
"name": "iq_sel[0]"
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
},
|
||||
{
|
||||
"name": "probe_out4",
|
||||
"id": 14,
|
||||
"type": "DATA",
|
||||
"direction": "OUT",
|
||||
"isVector": true,
|
||||
"leftIndex": 0,
|
||||
"rightIndex": 3,
|
||||
"portIndex": 4,
|
||||
"nets": [
|
||||
{
|
||||
"name": "bb_rshift",
|
||||
"isBus": true,
|
||||
"subnets": [
|
||||
{
|
||||
"name": "bb_rshift[3]"
|
||||
},
|
||||
{
|
||||
"name": "bb_rshift[2]"
|
||||
},
|
||||
{
|
||||
"name": "bb_rshift[1]"
|
||||
},
|
||||
{
|
||||
"name": "bb_rshift[0]"
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,243 @@
|
||||
# sjl_2z7100_ad9528_2ad9361
|
||||
|
||||
## Timing Assertions Section
|
||||
|
||||
## Physical Constraints Section
|
||||
|
||||
# Clocks
|
||||
set_property -dict {PACKAGE_PIN AC28 IOSTANDARD LVDS_25 } [get_ports refclk_1_p ] ;# F1_REFCLK1_P
|
||||
set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVDS } [get_ports refclk_2_p ] ;# F1_REFCLK2_P
|
||||
set_property -dict {PACKAGE_PIN AD10 } [get_ports gtclk_109_p ] ;# F1_GTCLK0_P
|
||||
set_property -dict {PACKAGE_PIN AA8 } [get_ports gtclk_110_p ] ;# F1_GTCLK1_P
|
||||
set_property -dict {PACKAGE_PIN N8 } [get_ports gtclk_112_p ] ;# F1_GTCLK2_P
|
||||
set_property -dict {PACKAGE_PIN F5 IOSTANDARD LVCMOS18} [get_ports ad9361_1_buffer_clk ] ;# AD9361_1_CLK_OUT
|
||||
set_property -dict {PACKAGE_PIN H9 IOSTANDARD LVCMOS18} [get_ports ad9361_2_buffer_clk ] ;# AD9361_2_CLK_OUT
|
||||
|
||||
# AD9528 Interface
|
||||
set_property -dict {PACKAGE_PIN AG21 IOSTANDARD LVCMOS33} [get_ports ad9528_spi_csn ] ;# AD9528_SPI_CSB
|
||||
set_property -dict {PACKAGE_PIN AJ25 IOSTANDARD LVCMOS33} [get_ports ad9528_spi_clk ] ;# AD9528_SPI_SCLK
|
||||
set_property -dict {PACKAGE_PIN AK25 IOSTANDARD LVCMOS33} [get_ports ad9528_spi_mosi ] ;# AD9528_SPI_SDI
|
||||
set_property -dict {PACKAGE_PIN AK22 IOSTANDARD LVCMOS33} [get_ports ad9528_spi_miso ] ;# AD9528_SPI_SDO
|
||||
|
||||
set_property -dict {PACKAGE_PIN AJ23 IOSTANDARD LVCMOS33} [get_ports ad9528_status[0] ] ;# AD9528_STATUS0
|
||||
set_property -dict {PACKAGE_PIN AJ24 IOSTANDARD LVCMOS33} [get_ports ad9528_status[1] ] ;# AD9528_STATUS1
|
||||
set_property -dict {PACKAGE_PIN AH23 IOSTANDARD LVCMOS33} [get_ports ad9528_reset_b ] ;# AD9528_RESETB
|
||||
set_property -dict {PACKAGE_PIN AH24 IOSTANDARD LVCMOS33} [get_ports ad9528_sysref_req ] ;# AD9528_SYSREF_REQ
|
||||
|
||||
# AD9361-1 Interface
|
||||
set_property -dict {PACKAGE_PIN G5 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data_clk ] ;# AD9361_1_DATA_CLK_P
|
||||
set_property -dict {PACKAGE_PIN F4 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_frame ] ;# AD9361_1_RX_FRAME_P
|
||||
set_property -dict {PACKAGE_PIN E2 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[0] ] ;# AD9361_1_P0D00_TXD0_N
|
||||
set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[1] ] ;# AD9361_1_P0D01_TXD0_P
|
||||
set_property -dict {PACKAGE_PIN D3 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[2] ] ;# AD9361_1_P0D02_TXD1_N
|
||||
set_property -dict {PACKAGE_PIN D4 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[3] ] ;# AD9361_1_P0D03_TXD1_P
|
||||
set_property -dict {PACKAGE_PIN C3 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[4] ] ;# AD9361_1_P0D04_TXD2_N
|
||||
set_property -dict {PACKAGE_PIN C4 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[5] ] ;# AD9361_1_P0D05_TXD2_P
|
||||
set_property -dict {PACKAGE_PIN B4 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[6] ] ;# AD9361_1_P0D06_TXD3_N
|
||||
set_property -dict {PACKAGE_PIN B5 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[7] ] ;# AD9361_1_P0D07_TXD3_P
|
||||
set_property -dict {PACKAGE_PIN A4 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[8] ] ;# AD9361_1_P0D08_TXD4_N
|
||||
set_property -dict {PACKAGE_PIN A5 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[9] ] ;# AD9361_1_P0D09_TXD4_P
|
||||
set_property -dict {PACKAGE_PIN D1 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[10] ] ;# AD9361_1_P0D10_TXD5_N
|
||||
set_property -dict {PACKAGE_PIN E1 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[11] ] ;# AD9361_1_P0D11_TXD5_P
|
||||
|
||||
set_property -dict {PACKAGE_PIN H4 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_fb_clk ] ;# AD9361_1_FB_CLK_P
|
||||
set_property -dict {PACKAGE_PIN E6 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_frame ] ;# AD9361_1_TX_FRAME_P
|
||||
set_property -dict {PACKAGE_PIN K2 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[0] ] ;# AD9361_1_P1D00_RXD0_N
|
||||
set_property -dict {PACKAGE_PIN K3 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[1] ] ;# AD9361_1_P1D01_RXD0_P
|
||||
set_property -dict {PACKAGE_PIN K1 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[2] ] ;# AD9361_1_P1D02_RXD1_N
|
||||
set_property -dict {PACKAGE_PIN L1 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[3] ] ;# AD9361_1_P1D03_RXD1_P
|
||||
set_property -dict {PACKAGE_PIN L2 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[4] ] ;# AD9361_1_P1D04_RXD2_N
|
||||
set_property -dict {PACKAGE_PIN L3 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[5] ] ;# AD9361_1_P1D05_RXD2_P
|
||||
set_property -dict {PACKAGE_PIN J3 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[6] ] ;# AD9361_1_P1D06_RXD3_N
|
||||
set_property -dict {PACKAGE_PIN J4 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[7] ] ;# AD9361_1_P1D07_RXD3_P
|
||||
set_property -dict {PACKAGE_PIN J5 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[8] ] ;# AD9361_1_P1D08_RXD4_N
|
||||
set_property -dict {PACKAGE_PIN K5 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[9] ] ;# AD9361_1_P1D09_RXD4_P
|
||||
set_property -dict {PACKAGE_PIN J6 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[10] ] ;# AD9361_1_P1D10_RXD5_N
|
||||
set_property -dict {PACKAGE_PIN K6 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[11] ] ;# AD9361_1_P1D11_RXD5_P
|
||||
|
||||
set_property -dict {PACKAGE_PIN A13 IOSTANDARD LVCMOS18} [get_ports ad9361_1_spi_clk ] ;# AD9361_1_SPI_CLK
|
||||
set_property -dict {PACKAGE_PIN A12 IOSTANDARD LVCMOS18} [get_ports ad9361_1_spi_csn ] ;# AD9361_1_SPI_ENB
|
||||
set_property -dict {PACKAGE_PIN F17 IOSTANDARD LVCMOS18} [get_ports ad9361_1_spi_mosi ] ;# AD9361_1_SPI_DI
|
||||
set_property -dict {PACKAGE_PIN G16 IOSTANDARD LVCMOS18} [get_ports ad9361_1_spi_miso ] ;# AD9361_1_SPI_DO
|
||||
|
||||
set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVCMOS18} [get_ports ad9361_1_reset_b ] ;# AD9361_1_RESETB
|
||||
set_property -dict {PACKAGE_PIN B15 IOSTANDARD LVCMOS18} [get_ports ad9361_1_en_agc ] ;# AD9361_1_EN_AGC
|
||||
set_property -dict {PACKAGE_PIN A14 IOSTANDARD LVCMOS18} [get_ports ad9361_1_enable ] ;# AD9361_1_ENABLE
|
||||
set_property -dict {PACKAGE_PIN H6 IOSTANDARD LVCMOS18} [get_ports ad9361_1_txnrx ] ;# AD9361_1_TXNRX
|
||||
|
||||
set_property -dict {PACKAGE_PIN C16 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_in[0] ] ;# AD9361_1_CTRL_IN0
|
||||
set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_in[1] ] ;# AD9361_1_CTRL_IN1
|
||||
set_property -dict {PACKAGE_PIN B14 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_in[2] ] ;# AD9361_1_CTRL_IN2
|
||||
set_property -dict {PACKAGE_PIN B12 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_in[3] ] ;# AD9361_1_CTRL_IN3
|
||||
|
||||
set_property -dict {PACKAGE_PIN B11 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[0] ] ;# AD9361_1_CTRL_OUT0
|
||||
set_property -dict {PACKAGE_PIN C14 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[1] ] ;# AD9361_1_CTRL_OUT1
|
||||
set_property -dict {PACKAGE_PIN C13 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[2] ] ;# AD9361_1_CTRL_OUT2
|
||||
set_property -dict {PACKAGE_PIN C12 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[3] ] ;# AD9361_1_CTRL_OUT3
|
||||
set_property -dict {PACKAGE_PIN A15 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[4] ] ;# AD9361_1_CTRL_OUT4
|
||||
set_property -dict {PACKAGE_PIN D16 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[5] ] ;# AD9361_1_CTRL_OUT5
|
||||
set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[6] ] ;# AD9361_1_CTRL_OUT6
|
||||
set_property -dict {PACKAGE_PIN E17 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[7] ] ;# AD9361_1_CTRL_OUT7
|
||||
|
||||
# AD9361-2 Interface
|
||||
set_property -dict {PACKAGE_PIN D9 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data_clk ] ;# AD9361_2_DATA_CLK_P
|
||||
set_property -dict {PACKAGE_PIN E7 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_frame ] ;# AD9361_2_RX_FRAME_P
|
||||
set_property -dict {PACKAGE_PIN B6 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[0] ] ;# AD9361_2_P0D00_TXD0_N
|
||||
set_property -dict {PACKAGE_PIN C6 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[1] ] ;# AD9361_2_P0D01_TXD0_P
|
||||
set_property -dict {PACKAGE_PIN B7 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[2] ] ;# AD9361_2_P0D02_TXD1_N
|
||||
set_property -dict {PACKAGE_PIN C7 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[3] ] ;# AD9361_2_P0D03_TXD1_P
|
||||
set_property -dict {PACKAGE_PIN A9 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[4] ] ;# AD9361_2_P0D04_TXD2_N
|
||||
set_property -dict {PACKAGE_PIN B9 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[5] ] ;# AD9361_2_P0D05_TXD2_P
|
||||
set_property -dict {PACKAGE_PIN A10 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[6] ] ;# AD9361_2_P0D06_TXD3_N
|
||||
set_property -dict {PACKAGE_PIN B10 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[7] ] ;# AD9361_2_P0D07_TXD3_P
|
||||
set_property -dict {PACKAGE_PIN D11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[8] ] ;# AD9361_2_P0D08_TXD4_N
|
||||
set_property -dict {PACKAGE_PIN E11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[9] ] ;# AD9361_2_P0D09_TXD4_P
|
||||
set_property -dict {PACKAGE_PIN C8 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[10] ] ;# AD9361_2_P0D10_TXD5_N
|
||||
set_property -dict {PACKAGE_PIN C9 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[11] ] ;# AD9361_2_P0D11_TXD5_P
|
||||
|
||||
set_property -dict {PACKAGE_PIN G10 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_fb_clk ] ;# AD9361_2_FB_CLK_P
|
||||
set_property -dict {PACKAGE_PIN F8 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_frame ] ;# AD9361_2_TX_FRAME_P
|
||||
set_property -dict {PACKAGE_PIN G7 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[0] ] ;# AD9361_2_P1D00_RXD0_N
|
||||
set_property -dict {PACKAGE_PIN H7 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[1] ] ;# AD9361_2_P1D01_RXD0_P
|
||||
set_property -dict {PACKAGE_PIN H8 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[2] ] ;# AD9361_2_P1D02_RXD1_N
|
||||
set_property -dict {PACKAGE_PIN J8 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[3] ] ;# AD9361_2_P1D03_RXD1_P
|
||||
set_property -dict {PACKAGE_PIN J9 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[4] ] ;# AD9361_2_P1D04_RXD2_N
|
||||
set_property -dict {PACKAGE_PIN J10 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[5] ] ;# AD9361_2_P1D05_RXD2_P
|
||||
set_property -dict {PACKAGE_PIN K7 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[6] ] ;# AD9361_2_P1D06_RXD3_N
|
||||
set_property -dict {PACKAGE_PIN L7 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[7] ] ;# AD9361_2_P1D07_RXD3_P
|
||||
set_property -dict {PACKAGE_PIN K8 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[8] ] ;# AD9361_2_P1D08_RXD4_N
|
||||
set_property -dict {PACKAGE_PIN L8 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[9] ] ;# AD9361_2_P1D09_RXD4_P
|
||||
set_property -dict {PACKAGE_PIN H11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[10] ] ;# AD9361_2_P1D10_RXD5_N
|
||||
set_property -dict {PACKAGE_PIN J11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[11] ] ;# AD9361_2_P1D11_RXD5_P
|
||||
|
||||
set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS18} [get_ports ad9361_2_spi_clk ] ;# AD9361_2_SPI_CLK
|
||||
set_property -dict {PACKAGE_PIN M16 IOSTANDARD LVCMOS18} [get_ports ad9361_2_spi_csn ] ;# AD9361_2_SPI_ENB
|
||||
set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS18} [get_ports ad9361_2_spi_mosi ] ;# AD9361_2_SPI_DI
|
||||
set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVCMOS18} [get_ports ad9361_2_spi_miso ] ;# AD9361_2_SPI_DO
|
||||
|
||||
set_property -dict {PACKAGE_PIN H16 IOSTANDARD LVCMOS18} [get_ports ad9361_2_reset_b ] ;# AD9361_2_RESETB
|
||||
set_property -dict {PACKAGE_PIN J13 IOSTANDARD LVCMOS18} [get_ports ad9361_2_en_agc ] ;# AD9361_2_EN_AGC
|
||||
set_property -dict {PACKAGE_PIN H13 IOSTANDARD LVCMOS18} [get_ports ad9361_2_enable ] ;# AD9361_2_ENABLE
|
||||
set_property -dict {PACKAGE_PIN H12 IOSTANDARD LVCMOS18} [get_ports ad9361_2_txnrx ] ;# AD9361_2_TXNRX
|
||||
|
||||
set_property -dict {PACKAGE_PIN E13 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_in[0] ] ;# AD9361_2_CTRL_IN0
|
||||
set_property -dict {PACKAGE_PIN E12 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_in[1] ] ;# AD9361_2_CTRL_IN1
|
||||
set_property -dict {PACKAGE_PIN F12 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_in[2] ] ;# AD9361_2_CTRL_IN2
|
||||
set_property -dict {PACKAGE_PIN G14 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_in[3] ] ;# AD9361_2_CTRL_IN3
|
||||
|
||||
set_property -dict {PACKAGE_PIN C11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[0] ] ;# AD9361_2_CTRL_OUT0
|
||||
set_property -dict {PACKAGE_PIN L14 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[1] ] ;# AD9361_2_CTRL_OUT1
|
||||
set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[2] ] ;# AD9361_2_CTRL_OUT2
|
||||
set_property -dict {PACKAGE_PIN G12 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[3] ] ;# AD9361_2_CTRL_OUT3
|
||||
set_property -dict {PACKAGE_PIN F13 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[4] ] ;# AD9361_2_CTRL_OUT4
|
||||
set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[5] ] ;# AD9361_2_CTRL_OUT5
|
||||
set_property -dict {PACKAGE_PIN L15 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[6] ] ;# AD9361_2_CTRL_OUT6
|
||||
set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[7] ] ;# AD9361_2_CTRL_OUT7
|
||||
|
||||
# Inter-FPGA Ports
|
||||
set_property -dict {PACKAGE_PIN Y30 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[0] ] ;# LVDS_IO_GRP0_00P
|
||||
set_property -dict {PACKAGE_PIN AC29 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[1] ] ;# LVDS_IO_GRP0_01P
|
||||
set_property -dict {PACKAGE_PIN AA27 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[2] ] ;# LVDS_IO_GRP0_02P
|
||||
set_property -dict {PACKAGE_PIN Y28 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[3] ] ;# LVDS_IO_GRP0_03P
|
||||
set_property -dict {PACKAGE_PIN AB29 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[4] ] ;# LVDS_IO_GRP0_04P
|
||||
set_property -dict {PACKAGE_PIN AE27 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[5] ] ;# LVDS_IO_GRP0_05P
|
||||
set_property -dict {PACKAGE_PIN AB27 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[6] ] ;# LVDS_IO_GRP0_06P
|
||||
set_property -dict {PACKAGE_PIN Y26 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[7] ] ;# LVDS_IO_GRP0_07P
|
||||
set_property -dict {PACKAGE_PIN AE25 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[8] ] ;# LVDS_IO_GRP0_08P
|
||||
set_property -dict {PACKAGE_PIN AK27 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[9] ] ;# LVDS_IO_GRP0_09P
|
||||
set_property -dict {PACKAGE_PIN AF29 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[10] ] ;# LVDS_IO_GRP0_10P
|
||||
set_property -dict {PACKAGE_PIN AJ28 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[11] ] ;# LVDS_IO_GRP0_11P
|
||||
set_property -dict {PACKAGE_PIN AJ26 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[12] ] ;# LVDS_IO_GRP0_12P
|
||||
set_property -dict {PACKAGE_PIN AJ30 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[13] ] ;# LVDS_IO_GRP0_13P
|
||||
set_property -dict {PACKAGE_PIN AB25 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[14] ] ;# LVDS_IO_GRP0_14P
|
||||
set_property -dict {PACKAGE_PIN AG26 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[15] ] ;# LVDS_IO_GRP0_15P
|
||||
set_property -dict {PACKAGE_PIN AH26 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[16] ] ;# LVDS_IO_GRP0_16P
|
||||
set_property -dict {PACKAGE_PIN AF30 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[17] ] ;# LVDS_IO_GRP0_17P
|
||||
set_property -dict {PACKAGE_PIN AD30 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[18] ] ;# LVDS_IO_GRP0_18P
|
||||
set_property -dict {PACKAGE_PIN AH28 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[19] ] ;# LVDS_IO_GRP0_19P
|
||||
set_property -dict {PACKAGE_PIN AD25 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[20] ] ;# LVDS_IO_GRP0_20P
|
||||
set_property -dict {PACKAGE_PIN AE28 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[21] ] ;# LVDS_IO_GRP0_21P
|
||||
set_property -dict {PACKAGE_PIN AC26 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[22] ] ;# LVDS_IO_GRP0_22P
|
||||
|
||||
set_property -dict {PACKAGE_PIN T30 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[0] ] ;# LVDS_IO_GRP1_00P
|
||||
set_property -dict {PACKAGE_PIN R28 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[1] ] ;# LVDS_IO_GRP1_01P
|
||||
set_property -dict {PACKAGE_PIN U22 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[2] ] ;# LVDS_IO_GRP1_02P
|
||||
set_property -dict {PACKAGE_PIN T29 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[3] ] ;# LVDS_IO_GRP1_03P
|
||||
set_property -dict {PACKAGE_PIN P30 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[4] ] ;# LVDS_IO_GRP1_04P
|
||||
set_property -dict {PACKAGE_PIN N26 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[5] ] ;# LVDS_IO_GRP1_05P
|
||||
set_property -dict {PACKAGE_PIN N28 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[6] ] ;# LVDS_IO_GRP1_06P
|
||||
set_property -dict {PACKAGE_PIN N29 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[7] ] ;# LVDS_IO_GRP1_07P
|
||||
set_property -dict {PACKAGE_PIN V27 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[8] ] ;# LVDS_IO_GRP1_08P
|
||||
set_property -dict {PACKAGE_PIN P25 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[9] ] ;# LVDS_IO_GRP1_09P
|
||||
set_property -dict {PACKAGE_PIN R25 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[10] ] ;# LVDS_IO_GRP1_10P
|
||||
set_property -dict {PACKAGE_PIN W29 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[11] ] ;# LVDS_IO_GRP1_11P
|
||||
set_property -dict {PACKAGE_PIN R27 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[12] ] ;# LVDS_IO_GRP1_12P
|
||||
set_property -dict {PACKAGE_PIN V23 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[13] ] ;# LVDS_IO_GRP1_13P
|
||||
set_property -dict {PACKAGE_PIN T24 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[14] ] ;# LVDS_IO_GRP1_14P
|
||||
set_property -dict {PACKAGE_PIN U24 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[15] ] ;# LVDS_IO_GRP1_15P
|
||||
set_property -dict {PACKAGE_PIN T22 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[16] ] ;# LVDS_IO_GRP1_16P
|
||||
set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[17] ] ;# LVDS_IO_GRP1_17P
|
||||
set_property -dict {PACKAGE_PIN V28 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[18] ] ;# LVDS_IO_GRP1_18P
|
||||
set_property -dict {PACKAGE_PIN W25 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[19] ] ;# LVDS_IO_GRP1_19P
|
||||
set_property -dict {PACKAGE_PIN P23 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[20] ] ;# LVDS_IO_GRP1_20P
|
||||
set_property -dict {PACKAGE_PIN U25 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[21] ] ;# LVDS_IO_GRP1_21P
|
||||
set_property -dict {PACKAGE_PIN R22 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[22] ] ;# LVDS_IO_GRP1_22P
|
||||
|
||||
set_property -dict {PACKAGE_PIN AH10 } [get_ports if_gtx_rxp[0] ] ;# GTX_F1R_F2T_00P
|
||||
set_property -dict {PACKAGE_PIN AJ8 } [get_ports if_gtx_rxp[1] ] ;# GTX_F1R_F2T_01P
|
||||
set_property -dict {PACKAGE_PIN AG8 } [get_ports if_gtx_rxp[2] ] ;# GTX_F1R_F2T_02P
|
||||
set_property -dict {PACKAGE_PIN AE8 } [get_ports if_gtx_rxp[3] ] ;# GTX_F1R_F2T_03P
|
||||
set_property -dict {PACKAGE_PIN AH6 } [get_ports if_gtx_rxp[4] ] ;# GTX_F1R_F2T_04P
|
||||
set_property -dict {PACKAGE_PIN AG4 } [get_ports if_gtx_rxp[5] ] ;# GTX_F1R_F2T_05P
|
||||
set_property -dict {PACKAGE_PIN AF6 } [get_ports if_gtx_rxp[6] ] ;# GTX_F1R_F2T_06P
|
||||
set_property -dict {PACKAGE_PIN AD6 } [get_ports if_gtx_rxp[7] ] ;# GTX_F1R_F2T_07P
|
||||
|
||||
# set_property -dict {PACKAGE_PIN AK10 } [get_ports if_gtx_txp[0] ] ;# GTX_F1T_F2R_00P
|
||||
# set_property -dict {PACKAGE_PIN AK6 } [get_ports if_gtx_txp[1] ] ;# GTX_F1T_F2R_01P
|
||||
# set_property -dict {PACKAGE_PIN AJ4 } [get_ports if_gtx_txp[2] ] ;# GTX_F1T_F2R_02P
|
||||
# set_property -dict {PACKAGE_PIN AK2 } [get_ports if_gtx_txp[3] ] ;# GTX_F1T_F2R_03P
|
||||
# set_property -dict {PACKAGE_PIN AH2 } [get_ports if_gtx_txp[4] ] ;# GTX_F1T_F2R_04P
|
||||
# set_property -dict {PACKAGE_PIN AF2 } [get_ports if_gtx_txp[5] ] ;# GTX_F1T_F2R_05P
|
||||
# set_property -dict {PACKAGE_PIN AE4 } [get_ports if_gtx_txp[6] ] ;# GTX_F1T_F2R_06P
|
||||
# set_property -dict {PACKAGE_PIN AD2 } [get_ports if_gtx_txp[7] ] ;# GTX_F1T_F2R_07P
|
||||
|
||||
# Inter-board Ports
|
||||
set_property -dict {PACKAGE_PIN V6 } [get_ports ib_gtx_tt2zw_p[0] ] ;# SRIO_1_TT2ZW_P
|
||||
set_property -dict {PACKAGE_PIN U4 } [get_ports ib_gtx_tt2zw_p[1] ] ;# SRIO_2_TT2ZW_P
|
||||
|
||||
# set_property -dict {PACKAGE_PIN T2 } [get_ports ib_gtx_zw2tt_p[0] ] ;# SRIO_1_ZW2TT_P
|
||||
# set_property -dict {PACKAGE_PIN R4 } [get_ports ib_gtx_zw2tt_p[1] ] ;# SRIO_2_ZW2TT_P
|
||||
|
||||
set_property -dict {PACKAGE_PIN AH12 IOSTANDARD LVCMOS33} [get_ports rs422_tt2zw ] ;# RS422_TT2ZW
|
||||
set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVCMOS33} [get_ports rs422_zw2tt ] ;# RS422_ZW2TT
|
||||
|
||||
# UTC RS422
|
||||
set_property -dict {PACKAGE_PIN AA13 IOSTANDARD LVCMOS33} [get_ports rs422_utc_rxd ] ;# RS422_UTC_RXD
|
||||
set_property -dict {PACKAGE_PIN AK13 IOSTANDARD LVCMOS33} [get_ports rs422_utc_reb ] ;# RS422_UTC_REB
|
||||
set_property -dict {PACKAGE_PIN AK12 IOSTANDARD LVCMOS33} [get_ports rs422_utc_de ] ;# RS422_UTC_DE
|
||||
set_property -dict {PACKAGE_PIN AH18 IOSTANDARD LVCMOS33} [get_ports rs422_utc_txd ] ;# RS422_UTC_TXD
|
||||
|
||||
# RF Control
|
||||
set_property -dict {PACKAGE_PIN AK15 IOSTANDARD LVCMOS33} [get_ports rf_spi_clk ] ;# RF_SPI_CLK
|
||||
set_property -dict {PACKAGE_PIN AD14 IOSTANDARD LVCMOS33} [get_ports rf_spi_mosi1 ] ;# RF_SPI_MOSI1
|
||||
set_property -dict {PACKAGE_PIN AJ16 IOSTANDARD LVCMOS33} [get_ports rf_spi_mosi2 ] ;# RF_SPI_MOSI2
|
||||
set_property -dict {PACKAGE_PIN AK16 IOSTANDARD LVCMOS33} [get_ports rf_spi_mosi3 ] ;# RF_SPI_MOSI3
|
||||
set_property -dict {PACKAGE_PIN AD13 IOSTANDARD LVCMOS33} [get_ports rf_spi_mosi4 ] ;# RF_SPI_MOSI4
|
||||
set_property -dict {PACKAGE_PIN AJ15 IOSTANDARD LVCMOS33} [get_ports rf_spi_sen ] ;# RF_SPI_SEN
|
||||
set_property -dict {PACKAGE_PIN AE12 IOSTANDARD LVCMOS33} [get_ports rf_spi_miso ] ;# RF_SPI_MISO
|
||||
|
||||
# PS PJTAG
|
||||
set_property -dict {PACKAGE_PIN AD24 IOSTANDARD LVCMOS33} [get_ports pjtag_tdi ] ;# PS1_TDI
|
||||
set_property -dict {PACKAGE_PIN AG24 IOSTANDARD LVCMOS33} [get_ports pjtag_tms ] ;# PS1_TMS
|
||||
set_property -dict {PACKAGE_PIN AG25 IOSTANDARD LVCMOS33} [get_ports pjtag_tck ] ;# PS1_TCK
|
||||
set_property -dict {PACKAGE_PIN AF23 IOSTANDARD LVCMOS33} [get_ports pjtag_tdo ] ;# PS1_TDO
|
||||
|
||||
# 3.3V Debug IO
|
||||
set_property -dict {PACKAGE_PIN AA20 IOSTANDARD LVCMOS33} [get_ports uart_rxd ] ;# PL1_UART_RXD
|
||||
set_property -dict {PACKAGE_PIN Y20 IOSTANDARD LVCMOS33} [get_ports uart_txd ] ;# PL1_UART_TXD
|
||||
|
||||
set_property -dict {PACKAGE_PIN AB24 IOSTANDARD LVCMOS33} [get_ports debug_io_1 ] ;# PL1_DEBUG_IO_1
|
||||
set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVCMOS33} [get_ports debug_io_2 ] ;# PL1_DEBUG_IO_2
|
||||
set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVCMOS33} [get_ports debug_io_3 ] ;# PL1_DEBUG_IO_3
|
||||
set_property -dict {PACKAGE_PIN AC22 IOSTANDARD LVCMOS33} [get_ports debug_io_4 ] ;# PL1_DEBUG_IO_4
|
||||
set_property -dict {PACKAGE_PIN AC23 IOSTANDARD LVCMOS33} [get_ports debug_io_5 ] ;# PL1_DEBUG_IO_5
|
||||
@@ -0,0 +1,77 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module ad_rst (
|
||||
|
||||
// clock reset
|
||||
|
||||
input rst_async,
|
||||
input clk,
|
||||
output rstn,
|
||||
output reg rst);
|
||||
|
||||
// internal registers
|
||||
reg rst_async_d1 = 1'd1;
|
||||
reg rst_async_d2 = 1'd1;
|
||||
reg rst_sync = 1'd1;
|
||||
reg rst_sync_d = 1'd1;
|
||||
|
||||
// simple reset synchronizer
|
||||
always @(posedge clk or posedge rst_async) begin
|
||||
if (rst_async) begin
|
||||
rst_async_d1 <= 1'b1;
|
||||
rst_async_d2 <= 1'b1;
|
||||
rst_sync <= 1'b1;
|
||||
end else begin
|
||||
rst_async_d1 <= 1'b0;
|
||||
rst_async_d2 <= rst_async_d1;
|
||||
rst_sync <= rst_async_d2;
|
||||
end
|
||||
end
|
||||
|
||||
// two-stage synchronizer to prevent metastability on the falling edge
|
||||
always @(posedge clk) begin
|
||||
rst_sync_d <= rst_sync;
|
||||
rst <= rst_sync_d;
|
||||
end
|
||||
|
||||
assign rstn = ~rst;
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
@@ -0,0 +1,239 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module up_axi #(
|
||||
|
||||
parameter AXI_ADDRESS_WIDTH = 16) (
|
||||
|
||||
// reset and clocks
|
||||
|
||||
input up_rstn,
|
||||
input up_clk,
|
||||
|
||||
// axi4 interface
|
||||
|
||||
input up_axi_awvalid,
|
||||
input [(AXI_ADDRESS_WIDTH-1):0] up_axi_awaddr,
|
||||
output up_axi_awready,
|
||||
input up_axi_wvalid,
|
||||
input [31:0] up_axi_wdata,
|
||||
input [ 3:0] up_axi_wstrb,
|
||||
output up_axi_wready,
|
||||
output up_axi_bvalid,
|
||||
output [ 1:0] up_axi_bresp,
|
||||
input up_axi_bready,
|
||||
input up_axi_arvalid,
|
||||
input [(AXI_ADDRESS_WIDTH-1):0] up_axi_araddr,
|
||||
output up_axi_arready,
|
||||
output up_axi_rvalid,
|
||||
output [ 1:0] up_axi_rresp,
|
||||
output [31:0] up_axi_rdata,
|
||||
input up_axi_rready,
|
||||
|
||||
// pcore interface
|
||||
|
||||
output up_wreq,
|
||||
output [(AXI_ADDRESS_WIDTH-3):0] up_waddr,
|
||||
output [31:0] up_wdata,
|
||||
input up_wack,
|
||||
output up_rreq,
|
||||
output [(AXI_ADDRESS_WIDTH-3):0] up_raddr,
|
||||
input [31:0] up_rdata,
|
||||
input up_rack);
|
||||
|
||||
// internal registers
|
||||
|
||||
reg up_axi_awready_int = 'd0;
|
||||
reg up_axi_wready_int = 'd0;
|
||||
reg up_axi_bvalid_int = 'd0;
|
||||
reg up_wack_d = 'd0;
|
||||
reg up_wsel = 'd0;
|
||||
reg up_wreq_int = 'd0;
|
||||
reg [(AXI_ADDRESS_WIDTH-3):0] up_waddr_int = 'd0;
|
||||
reg [31:0] up_wdata_int = 'd0;
|
||||
reg [ 4:0] up_wcount = 'd0;
|
||||
reg up_axi_arready_int = 'd0;
|
||||
reg up_axi_rvalid_int = 'd0;
|
||||
reg [31:0] up_axi_rdata_int = 'd0;
|
||||
reg up_rack_d = 'd0;
|
||||
reg [31:0] up_rdata_d = 'd0;
|
||||
reg up_rsel = 'd0;
|
||||
reg up_rreq_int = 'd0;
|
||||
reg [(AXI_ADDRESS_WIDTH-3):0] up_raddr_int = 'd0;
|
||||
reg [ 4:0] up_rcount = 'd0;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire up_wack_s;
|
||||
wire up_rack_s;
|
||||
wire [31:0] up_rdata_s;
|
||||
|
||||
// write channel interface
|
||||
|
||||
assign up_axi_awready = up_axi_awready_int;
|
||||
assign up_axi_wready = up_axi_wready_int;
|
||||
assign up_axi_bvalid = up_axi_bvalid_int;
|
||||
assign up_axi_bresp = 2'd0;
|
||||
|
||||
always @(posedge up_clk) begin
|
||||
if (up_rstn == 1'b0) begin
|
||||
up_axi_awready_int <= 'd0;
|
||||
up_axi_wready_int <= 'd0;
|
||||
up_axi_bvalid_int <= 'd0;
|
||||
end else begin
|
||||
if (up_axi_awready_int == 1'b1) begin
|
||||
up_axi_awready_int <= 1'b0;
|
||||
end else if (up_wack_s == 1'b1) begin
|
||||
up_axi_awready_int <= 1'b1;
|
||||
end
|
||||
if (up_axi_wready_int == 1'b1) begin
|
||||
up_axi_wready_int <= 1'b0;
|
||||
end else if (up_wack_s == 1'b1) begin
|
||||
up_axi_wready_int <= 1'b1;
|
||||
end
|
||||
if ((up_axi_bready == 1'b1) && (up_axi_bvalid_int == 1'b1)) begin
|
||||
up_axi_bvalid_int <= 1'b0;
|
||||
end else if (up_wack_d == 1'b1) begin
|
||||
up_axi_bvalid_int <= 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign up_wreq = up_wreq_int;
|
||||
assign up_waddr = up_waddr_int;
|
||||
assign up_wdata = up_wdata_int;
|
||||
assign up_wack_s = (up_wcount == 5'h1f) ? 1'b1 : (up_wcount[4] & up_wack);
|
||||
|
||||
always @(posedge up_clk) begin
|
||||
if (up_rstn == 1'b0) begin
|
||||
up_wack_d <= 'd0;
|
||||
up_wsel <= 'd0;
|
||||
up_wreq_int <= 'd0;
|
||||
up_waddr_int <= 'd0;
|
||||
up_wdata_int <= 'd0;
|
||||
up_wcount <= 'd0;
|
||||
end else begin
|
||||
up_wack_d <= up_wack_s;
|
||||
if (up_wsel == 1'b1) begin
|
||||
if ((up_axi_bready == 1'b1) && (up_axi_bvalid_int == 1'b1)) begin
|
||||
up_wsel <= 1'b0;
|
||||
end
|
||||
up_wreq_int <= 1'b0;
|
||||
end else begin
|
||||
up_wsel <= up_axi_awvalid & up_axi_wvalid;
|
||||
up_wreq_int <= up_axi_awvalid & up_axi_wvalid;
|
||||
up_waddr_int <= up_axi_awaddr[(AXI_ADDRESS_WIDTH-1):2];
|
||||
up_wdata_int <= up_axi_wdata;
|
||||
end
|
||||
if (up_wack_s == 1'b1) begin
|
||||
up_wcount <= 5'h00;
|
||||
end else if (up_wcount[4] == 1'b1) begin
|
||||
up_wcount <= up_wcount + 1'b1;
|
||||
end else if (up_wreq_int == 1'b1) begin
|
||||
up_wcount <= 5'h10;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// read channel interface
|
||||
|
||||
assign up_axi_arready = up_axi_arready_int;
|
||||
assign up_axi_rvalid = up_axi_rvalid_int;
|
||||
assign up_axi_rdata = up_axi_rdata_int;
|
||||
assign up_axi_rresp = 2'd0;
|
||||
|
||||
always @(posedge up_clk) begin
|
||||
if (up_rstn == 1'b0) begin
|
||||
up_axi_arready_int <= 'd0;
|
||||
up_axi_rvalid_int <= 'd0;
|
||||
up_axi_rdata_int <= 'd0;
|
||||
end else begin
|
||||
if (up_axi_arready_int == 1'b1) begin
|
||||
up_axi_arready_int <= 1'b0;
|
||||
end else if (up_rack_s == 1'b1) begin
|
||||
up_axi_arready_int <= 1'b1;
|
||||
end
|
||||
if ((up_axi_rready == 1'b1) && (up_axi_rvalid_int == 1'b1)) begin
|
||||
up_axi_rvalid_int <= 1'b0;
|
||||
up_axi_rdata_int <= 32'd0;
|
||||
end else if (up_rack_d == 1'b1) begin
|
||||
up_axi_rvalid_int <= 1'b1;
|
||||
up_axi_rdata_int <= up_rdata_d;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign up_rreq = up_rreq_int;
|
||||
assign up_raddr = up_raddr_int;
|
||||
assign up_rack_s = (up_rcount == 5'h1f) ? 1'b1 : (up_rcount[4] & up_rack);
|
||||
assign up_rdata_s = (up_rcount == 5'h1f) ? {2{16'hdead}} : up_rdata;
|
||||
|
||||
always @(posedge up_clk) begin
|
||||
if (up_rstn == 1'b0) begin
|
||||
up_rack_d <= 'd0;
|
||||
up_rdata_d <= 'd0;
|
||||
up_rsel <= 'd0;
|
||||
up_rreq_int <= 'd0;
|
||||
up_raddr_int <= 'd0;
|
||||
up_rcount <= 'd0;
|
||||
end else begin
|
||||
up_rack_d <= up_rack_s;
|
||||
up_rdata_d <= up_rdata_s;
|
||||
if (up_rsel == 1'b1) begin
|
||||
if ((up_axi_rready == 1'b1) && (up_axi_rvalid_int == 1'b1)) begin
|
||||
up_rsel <= 1'b0;
|
||||
end
|
||||
up_rreq_int <= 1'b0;
|
||||
end else begin
|
||||
up_rsel <= up_axi_arvalid;
|
||||
up_rreq_int <= up_axi_arvalid;
|
||||
up_raddr_int <= up_axi_araddr[(AXI_ADDRESS_WIDTH-1):2];
|
||||
end
|
||||
if (up_rack_s == 1'b1) begin
|
||||
up_rcount <= 5'h00;
|
||||
end else if (up_rcount[4] == 1'b1) begin
|
||||
up_rcount <= up_rcount + 1'b1;
|
||||
end else if (up_rreq_int == 1'b1) begin
|
||||
up_rcount <= 5'h10;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
+302
@@ -0,0 +1,302 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "system_bd_auto_pc_0",
|
||||
"cell_name": "axi_interconnect/s00_couplers/auto_pc",
|
||||
"component_reference": "xilinx.com:ip:axi_protocol_converter:2.1",
|
||||
"ip_revision": "32",
|
||||
"gen_directory": "../../../../../../sjl_basic.gen/sources_1/bd/system_bd/ip/system_bd_auto_pc_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"SI_PROTOCOL": [ { "value": "AXI3", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
|
||||
"MI_PROTOCOL": [ { "value": "AXI4LITE", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
|
||||
"TRANSLATION_MODE": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ID_WIDTH": [ { "value": "12", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "system_bd_auto_pc_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_FAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_M_AXI_PROTOCOL": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_PROTOCOL": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_IGNORE_ID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_ID_WIDTH": [ { "value": "12", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_SUPPORTS_WRITE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_SUPPORTS_READ": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_SUPPORTS_USER_SIGNALS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_AWUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_ARUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_WUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_RUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_BUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_TRANSLATION_MODE": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z100" } ],
|
||||
"NEXTGEN_VERSAL": [ { "value": "0" } ],
|
||||
"PACKAGE": [ { "value": "ffg900" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "32" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../sjl_basic.gen/sources_1/bd/system_bd/ip/system_bd_auto_pc_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "rtl" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2024.1.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"aclk": [ { "direction": "in" } ],
|
||||
"aresetn": [ { "direction": "in" } ],
|
||||
"s_axi_awid": [ { "direction": "in", "size_left": "11", "size_right": "0", "driver_value": "0x000" } ],
|
||||
"s_axi_awaddr": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0x00000000" } ],
|
||||
"s_axi_awlen": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"s_axi_awsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"s_axi_awburst": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x1" } ],
|
||||
"s_axi_awlock": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"s_axi_awcache": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"s_axi_awprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"s_axi_awqos": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"s_axi_awvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axi_awready": [ { "direction": "out" } ],
|
||||
"s_axi_wid": [ { "direction": "in", "size_left": "11", "size_right": "0", "driver_value": "0x000" } ],
|
||||
"s_axi_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0x00000000" } ],
|
||||
"s_axi_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0xF" } ],
|
||||
"s_axi_wlast": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"s_axi_wvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axi_wready": [ { "direction": "out" } ],
|
||||
"s_axi_bid": [ { "direction": "out", "size_left": "11", "size_right": "0" } ],
|
||||
"s_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s_axi_bvalid": [ { "direction": "out" } ],
|
||||
"s_axi_bready": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axi_arid": [ { "direction": "in", "size_left": "11", "size_right": "0", "driver_value": "0x000" } ],
|
||||
"s_axi_araddr": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0x00000000" } ],
|
||||
"s_axi_arlen": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"s_axi_arsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"s_axi_arburst": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x1" } ],
|
||||
"s_axi_arlock": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"s_axi_arcache": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"s_axi_arprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"s_axi_arqos": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"s_axi_arvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axi_arready": [ { "direction": "out" } ],
|
||||
"s_axi_rid": [ { "direction": "out", "size_left": "11", "size_right": "0" } ],
|
||||
"s_axi_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"s_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s_axi_rlast": [ { "direction": "out" } ],
|
||||
"s_axi_rvalid": [ { "direction": "out" } ],
|
||||
"s_axi_rready": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"m_axi_awaddr": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"m_axi_awprot": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||
"m_axi_awvalid": [ { "direction": "out" } ],
|
||||
"m_axi_awready": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"m_axi_wdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"m_axi_wstrb": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||
"m_axi_wvalid": [ { "direction": "out" } ],
|
||||
"m_axi_wready": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"m_axi_bresp": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"m_axi_bvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"m_axi_bready": [ { "direction": "out" } ],
|
||||
"m_axi_araddr": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"m_axi_arprot": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||
"m_axi_arvalid": [ { "direction": "out" } ],
|
||||
"m_axi_arready": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"m_axi_rdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0x00000000" } ],
|
||||
"m_axi_rresp": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"m_axi_rvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"m_axi_rready": [ { "direction": "out" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"S_AXI": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI3", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "5e+07", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "12", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "16", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "4", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "4", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"AWID": [ { "physical_name": "s_axi_awid" } ],
|
||||
"AWADDR": [ { "physical_name": "s_axi_awaddr" } ],
|
||||
"AWLEN": [ { "physical_name": "s_axi_awlen" } ],
|
||||
"AWSIZE": [ { "physical_name": "s_axi_awsize" } ],
|
||||
"AWBURST": [ { "physical_name": "s_axi_awburst" } ],
|
||||
"AWLOCK": [ { "physical_name": "s_axi_awlock" } ],
|
||||
"AWCACHE": [ { "physical_name": "s_axi_awcache" } ],
|
||||
"AWPROT": [ { "physical_name": "s_axi_awprot" } ],
|
||||
"AWQOS": [ { "physical_name": "s_axi_awqos" } ],
|
||||
"AWVALID": [ { "physical_name": "s_axi_awvalid" } ],
|
||||
"AWREADY": [ { "physical_name": "s_axi_awready" } ],
|
||||
"WID": [ { "physical_name": "s_axi_wid" } ],
|
||||
"WDATA": [ { "physical_name": "s_axi_wdata" } ],
|
||||
"WSTRB": [ { "physical_name": "s_axi_wstrb" } ],
|
||||
"WLAST": [ { "physical_name": "s_axi_wlast" } ],
|
||||
"WVALID": [ { "physical_name": "s_axi_wvalid" } ],
|
||||
"WREADY": [ { "physical_name": "s_axi_wready" } ],
|
||||
"BID": [ { "physical_name": "s_axi_bid" } ],
|
||||
"BRESP": [ { "physical_name": "s_axi_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "s_axi_bvalid" } ],
|
||||
"BREADY": [ { "physical_name": "s_axi_bready" } ],
|
||||
"ARID": [ { "physical_name": "s_axi_arid" } ],
|
||||
"ARADDR": [ { "physical_name": "s_axi_araddr" } ],
|
||||
"ARLEN": [ { "physical_name": "s_axi_arlen" } ],
|
||||
"ARSIZE": [ { "physical_name": "s_axi_arsize" } ],
|
||||
"ARBURST": [ { "physical_name": "s_axi_arburst" } ],
|
||||
"ARLOCK": [ { "physical_name": "s_axi_arlock" } ],
|
||||
"ARCACHE": [ { "physical_name": "s_axi_arcache" } ],
|
||||
"ARPROT": [ { "physical_name": "s_axi_arprot" } ],
|
||||
"ARQOS": [ { "physical_name": "s_axi_arqos" } ],
|
||||
"ARVALID": [ { "physical_name": "s_axi_arvalid" } ],
|
||||
"ARREADY": [ { "physical_name": "s_axi_arready" } ],
|
||||
"RID": [ { "physical_name": "s_axi_rid" } ],
|
||||
"RDATA": [ { "physical_name": "s_axi_rdata" } ],
|
||||
"RRESP": [ { "physical_name": "s_axi_rresp" } ],
|
||||
"RLAST": [ { "physical_name": "s_axi_rlast" } ],
|
||||
"RVALID": [ { "physical_name": "s_axi_rvalid" } ],
|
||||
"RREADY": [ { "physical_name": "s_axi_rready" } ]
|
||||
}
|
||||
},
|
||||
"M_AXI": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "5e+07", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "4", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "4", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"AWADDR": [ { "physical_name": "m_axi_awaddr" } ],
|
||||
"AWPROT": [ { "physical_name": "m_axi_awprot" } ],
|
||||
"AWVALID": [ { "physical_name": "m_axi_awvalid" } ],
|
||||
"AWREADY": [ { "physical_name": "m_axi_awready" } ],
|
||||
"WDATA": [ { "physical_name": "m_axi_wdata" } ],
|
||||
"WSTRB": [ { "physical_name": "m_axi_wstrb" } ],
|
||||
"WVALID": [ { "physical_name": "m_axi_wvalid" } ],
|
||||
"WREADY": [ { "physical_name": "m_axi_wready" } ],
|
||||
"BRESP": [ { "physical_name": "m_axi_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "m_axi_bvalid" } ],
|
||||
"BREADY": [ { "physical_name": "m_axi_bready" } ],
|
||||
"ARADDR": [ { "physical_name": "m_axi_araddr" } ],
|
||||
"ARPROT": [ { "physical_name": "m_axi_arprot" } ],
|
||||
"ARVALID": [ { "physical_name": "m_axi_arvalid" } ],
|
||||
"ARREADY": [ { "physical_name": "m_axi_arready" } ],
|
||||
"RDATA": [ { "physical_name": "m_axi_rdata" } ],
|
||||
"RRESP": [ { "physical_name": "m_axi_rresp" } ],
|
||||
"RVALID": [ { "physical_name": "m_axi_rvalid" } ],
|
||||
"RREADY": [ { "physical_name": "m_axi_rready" } ]
|
||||
}
|
||||
},
|
||||
"CLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S_AXI:M_AXI", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "5e+07", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "aclk" } ]
|
||||
}
|
||||
},
|
||||
"RST": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TYPE": [ { "value": "INTERCONNECT", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "aresetn" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+353
@@ -0,0 +1,353 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "system_bd_axi_interconnect_0_0",
|
||||
"cell_name": "axi_interconnect",
|
||||
"component_reference": "xilinx.com:ip:axi_interconnect:2.1",
|
||||
"ip_revision": "33",
|
||||
"gen_directory": "../../../../../../sjl_basic.gen/sources_1/bd/system_bd/ip/system_bd_axi_interconnect_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"NUM_SI": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"NUM_MI": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"STRATEGY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ENABLE_ADVANCED_OPTIONS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ENABLE_PROTOCOL_CHECKERS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"XBAR_DATA_WIDTH": [ { "value": "32", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCHK_WAITS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCHK_MAX_RD_BURSTS": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCHK_MAX_WR_BURSTS": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SYNCHRONIZATION_STAGES": [ { "value": "3", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M00_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M01_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M02_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M03_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M04_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M05_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M06_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M07_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M08_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M09_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M10_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M11_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M12_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M13_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M14_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M15_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M16_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M17_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M18_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M19_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M20_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M21_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M22_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M23_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M24_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M25_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M26_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M27_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M28_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M29_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M30_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M31_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M32_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M33_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M34_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M35_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M36_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M37_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M38_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M39_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M40_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M41_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M42_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M43_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M44_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M45_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M46_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M47_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M48_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M49_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M50_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M51_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M52_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M53_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M54_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M55_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M56_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M57_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M58_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M59_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M60_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M61_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M62_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M63_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M00_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M01_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M02_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M03_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M04_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M05_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M06_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M07_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M08_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M09_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M10_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M11_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M12_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M13_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M14_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M15_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M16_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M17_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M18_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M19_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M20_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M21_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M22_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M23_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M24_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M25_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M26_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M27_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M28_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M29_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M30_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M31_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M32_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M33_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M34_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M35_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M36_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M37_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M38_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M39_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M40_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M41_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M42_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M43_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M44_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M45_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M46_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M47_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M48_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M49_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M50_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M51_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M52_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M53_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M54_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M55_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M56_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M57_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M58_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M59_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M60_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M61_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M62_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M63_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S00_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S01_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S02_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S03_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S04_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S05_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S06_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S07_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S08_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S09_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S10_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S11_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S12_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S13_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S14_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S15_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S00_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S01_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S02_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S03_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S04_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S05_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S06_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S07_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S08_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S09_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S10_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S11_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S12_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S13_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S14_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S15_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M00_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M01_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M02_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M03_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M04_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M05_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M06_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M07_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M08_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M09_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M10_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M11_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M12_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M13_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M14_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M15_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M16_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M17_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M18_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M19_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M20_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M21_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M22_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M23_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M24_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M25_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M26_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M27_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M28_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M29_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M30_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M31_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M32_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M33_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M34_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M35_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M36_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M37_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M38_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M39_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M40_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M41_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M42_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M43_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M44_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M45_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M46_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M47_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M48_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M49_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M50_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M51_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M52_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M53_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M54_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M55_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M56_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M57_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M58_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M59_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M60_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M61_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M62_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M63_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M00_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M01_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M02_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M03_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M04_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M05_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M06_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M07_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M08_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M09_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M10_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M11_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M12_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M13_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M14_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M15_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M16_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M17_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M18_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M19_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M20_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M21_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M22_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M23_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M24_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M25_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M26_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M27_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M28_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M29_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M30_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M31_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M32_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M33_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M34_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M35_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M36_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M37_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M38_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M39_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M40_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M41_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M42_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M43_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M44_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M45_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M46_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M47_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M48_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M49_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M50_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M51_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M52_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M53_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M54_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M55_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M56_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M57_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M58_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M59_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M60_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M61_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M62_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M63_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S00_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S01_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S02_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S03_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S04_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S05_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S06_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S07_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S08_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S09_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S10_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S11_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S12_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S13_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S14_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S15_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "system_bd_axi_interconnect_0_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z100" } ],
|
||||
"NEXTGEN_VERSAL": [ { "value": "0" } ],
|
||||
"PACKAGE": [ { "value": "ffg900" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator_AppCore" } ],
|
||||
"IPREVISION": [ { "value": "33" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../sjl_basic.gen/sources_1/bd/system_bd/ip/system_bd_axi_interconnect_0_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2024.1.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+294
@@ -0,0 +1,294 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "system_bd_axi_spi_engine_0_0",
|
||||
"cell_name": "axi_spi_engine",
|
||||
"component_reference": "analog.com:user:axi_spi_engine:1.0",
|
||||
"ip_revision": "1",
|
||||
"gen_directory": "../../../../../../sjl_basic.gen/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"CMD_FIFO_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SYNC_FIFO_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SDO_FIFO_ADDRESS_WIDTH": [ { "value": "5", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SDI_FIFO_ADDRESS_WIDTH": [ { "value": "5", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MM_IF_TYPE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ASYNC_SPI_CLK": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"NUM_OFFLOAD": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"OFFLOAD0_CMD_MEM_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"OFFLOAD0_SDO_MEM_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"ID": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"DATA_WIDTH": [ { "value": "8", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"NUM_OF_SDI": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CFG_INFO_0": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CFG_INFO_1": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CFG_INFO_2": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CFG_INFO_3": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "system_bd_axi_spi_engine_0_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"CMD_FIFO_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"SYNC_FIFO_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"SDO_FIFO_ADDRESS_WIDTH": [ { "value": "5", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"SDI_FIFO_ADDRESS_WIDTH": [ { "value": "5", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"MM_IF_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"ASYNC_SPI_CLK": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"NUM_OFFLOAD": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"OFFLOAD0_CMD_MEM_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"OFFLOAD0_SDO_MEM_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"ID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"DATA_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"NUM_OF_SDI": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"CFG_INFO_0": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"CFG_INFO_1": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"CFG_INFO_2": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"CFG_INFO_3": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z100" } ],
|
||||
"NEXTGEN_VERSAL": [ { "value": "0" } ],
|
||||
"PACKAGE": [ { "value": "ffg900" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "1" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../sjl_basic.gen/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2024.1.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"s_axi_aclk": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_aresetn": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_awvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_awaddr": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_awready": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"s_axi_awprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_wvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_wready": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"s_axi_bvalid": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"s_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_bready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_arvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_araddr": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_arready": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"s_axi_arprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_rvalid": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"s_axi_rready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"irq": [ { "direction": "out" } ],
|
||||
"spi_clk": [ { "direction": "in" } ],
|
||||
"spi_resetn": [ { "direction": "out" } ],
|
||||
"cmd_ready": [ { "direction": "in" } ],
|
||||
"cmd_valid": [ { "direction": "out" } ],
|
||||
"cmd_data": [ { "direction": "out", "size_left": "15", "size_right": "0" } ],
|
||||
"sdo_data_ready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"sdo_data_valid": [ { "direction": "out" } ],
|
||||
"sdo_data": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
|
||||
"sdi_data_ready": [ { "direction": "out" } ],
|
||||
"sdi_data_valid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"sdi_data": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
|
||||
"sync_ready": [ { "direction": "out" } ],
|
||||
"sync_valid": [ { "direction": "in" } ],
|
||||
"sync_data": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"s_axi": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"memory_map_ref": "s_axi",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "5e+07", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "16", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"AWADDR": [ { "physical_name": "s_axi_awaddr" } ],
|
||||
"AWPROT": [ { "physical_name": "s_axi_awprot" } ],
|
||||
"AWVALID": [ { "physical_name": "s_axi_awvalid" } ],
|
||||
"AWREADY": [ { "physical_name": "s_axi_awready" } ],
|
||||
"WDATA": [ { "physical_name": "s_axi_wdata" } ],
|
||||
"WSTRB": [ { "physical_name": "s_axi_wstrb" } ],
|
||||
"WVALID": [ { "physical_name": "s_axi_wvalid" } ],
|
||||
"WREADY": [ { "physical_name": "s_axi_wready" } ],
|
||||
"BRESP": [ { "physical_name": "s_axi_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "s_axi_bvalid" } ],
|
||||
"BREADY": [ { "physical_name": "s_axi_bready" } ],
|
||||
"ARADDR": [ { "physical_name": "s_axi_araddr" } ],
|
||||
"ARPROT": [ { "physical_name": "s_axi_arprot" } ],
|
||||
"ARVALID": [ { "physical_name": "s_axi_arvalid" } ],
|
||||
"ARREADY": [ { "physical_name": "s_axi_arready" } ],
|
||||
"RDATA": [ { "physical_name": "s_axi_rdata" } ],
|
||||
"RRESP": [ { "physical_name": "s_axi_rresp" } ],
|
||||
"RVALID": [ { "physical_name": "s_axi_rvalid" } ],
|
||||
"RREADY": [ { "physical_name": "s_axi_rready" } ]
|
||||
}
|
||||
},
|
||||
"s_axi_aclk": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "s_axi", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "s_axi_aresetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "s_axi_aclk" } ]
|
||||
}
|
||||
},
|
||||
"s_axi_aresetn": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "s_axi_aresetn" } ]
|
||||
}
|
||||
},
|
||||
"spi_engine_ctrl": {
|
||||
"vlnv": "analog.com:interface:spi_engine_ctrl:1.0",
|
||||
"abstraction_type": "analog.com:interface:spi_engine_ctrl_rtl:1.0",
|
||||
"mode": "master",
|
||||
"port_maps": {
|
||||
"cmd_ready": [ { "physical_name": "cmd_ready" } ],
|
||||
"cmd_valid": [ { "physical_name": "cmd_valid" } ],
|
||||
"cmd_data": [ { "physical_name": "cmd_data" } ],
|
||||
"sdo_ready": [ { "physical_name": "sdo_data_ready" } ],
|
||||
"sdo_valid": [ { "physical_name": "sdo_data_valid" } ],
|
||||
"sdo_data": [ { "physical_name": "sdo_data" } ],
|
||||
"sdi_ready": [ { "physical_name": "sdi_data_ready" } ],
|
||||
"sdi_valid": [ { "physical_name": "sdi_data_valid" } ],
|
||||
"sdi_data": [ { "physical_name": "sdi_data" } ],
|
||||
"sync_ready": [ { "physical_name": "sync_ready" } ],
|
||||
"sync_valid": [ { "physical_name": "sync_valid" } ],
|
||||
"sync_data": [ { "physical_name": "sync_data" } ]
|
||||
}
|
||||
},
|
||||
"spi_engine_ctrl_signal_clock": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "spi_engine_ctrl", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "spi_resetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "5e+07", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "spi_clk" } ]
|
||||
}
|
||||
},
|
||||
"spi_engine_ctrl_signal_reset": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "spi_resetn" } ]
|
||||
}
|
||||
},
|
||||
"spi_engine_offload_ctrl0_s_axi_signal_clock": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "spi_engine_offload_ctrl0:s_axi", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "s_axi_aresetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "5e+07", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "s_axi_aclk" } ]
|
||||
}
|
||||
},
|
||||
"spi_engine_offload_ctrl0_s_axi_signal_reset": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "s_axi_aresetn" } ]
|
||||
}
|
||||
}
|
||||
},
|
||||
"memory_maps": {
|
||||
"s_axi": {
|
||||
"address_blocks": {
|
||||
"axi_lite": {
|
||||
"base_address": "0",
|
||||
"range": "65536"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+643
@@ -0,0 +1,643 @@
|
||||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<!DOCTYPE designInfo PUBLIC "designInfo" "designInfo.dtd" >
|
||||
<designInfo version="1.0" >
|
||||
<MODULE IP_TYPE="SOC" MOD_CLASS="CONFIGURABLE" MODTYPE="processing_system7" >
|
||||
<PARAMETERS >
|
||||
<PARAMETER NAME="PCW_APU_CLK_RATIO_ENABLE" VALUE="6:2:1" />
|
||||
<PARAMETER NAME="PCW_APU_PERIPHERAL_FREQMHZ" VALUE="666.666666" />
|
||||
<PARAMETER NAME="PCW_ARMPLL_CTRL_FBDIV" VALUE="40" />
|
||||
<PARAMETER NAME="PCW_CAN0_CAN0_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_CAN0_GRP_CLK_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_CAN0_GRP_CLK_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_CAN0_PERIPHERAL_CLKSRC" VALUE="External" />
|
||||
<PARAMETER NAME="PCW_CAN0_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_CAN0_PERIPHERAL_FREQMHZ" VALUE="" />
|
||||
<PARAMETER NAME="PCW_CAN1_CAN1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_CAN1_GRP_CLK_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_CAN1_GRP_CLK_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_CAN1_PERIPHERAL_CLKSRC" VALUE="External" />
|
||||
<PARAMETER NAME="PCW_CAN1_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_CAN1_PERIPHERAL_FREQMHZ" VALUE="" />
|
||||
<PARAMETER NAME="PCW_CAN_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_CAN_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_CAN_PERIPHERAL_DIVISOR1" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_CAN_PERIPHERAL_FREQMHZ" VALUE="100" />
|
||||
<PARAMETER NAME="PCW_CPU_CPU_PLL_FREQMHZ" VALUE="1333.333" />
|
||||
<PARAMETER NAME="PCW_CPU_PERIPHERAL_CLKSRC" VALUE="ARM PLL" />
|
||||
<PARAMETER NAME="PCW_CPU_PERIPHERAL_DIVISOR0" VALUE="2" />
|
||||
<PARAMETER NAME="PCW_CRYSTAL_PERIPHERAL_FREQMHZ" VALUE="33.333333" />
|
||||
<PARAMETER NAME="PCW_DCI_PERIPHERAL_CLKSRC" VALUE="DDR PLL" />
|
||||
<PARAMETER NAME="PCW_DCI_PERIPHERAL_DIVISOR0" VALUE="15" />
|
||||
<PARAMETER NAME="PCW_DCI_PERIPHERAL_DIVISOR1" VALUE="7" />
|
||||
<PARAMETER NAME="PCW_DCI_PERIPHERAL_FREQMHZ" VALUE="10.159" />
|
||||
<PARAMETER NAME="PCW_DDRPLL_CTRL_FBDIV" VALUE="32" />
|
||||
<PARAMETER NAME="PCW_DDR_DDR_PLL_FREQMHZ" VALUE="1066.667" />
|
||||
<PARAMETER NAME="PCW_DDR_HPRLPR_QUEUE_PARTITION" VALUE="HPR(0)/LPR(32)" />
|
||||
<PARAMETER NAME="PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL" VALUE="15" />
|
||||
<PARAMETER NAME="PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL" VALUE="2" />
|
||||
<PARAMETER NAME="PCW_DDR_PERIPHERAL_CLKSRC" VALUE="DDR PLL" />
|
||||
<PARAMETER NAME="PCW_DDR_PERIPHERAL_DIVISOR0" VALUE="2" />
|
||||
<PARAMETER NAME="PCW_DDR_PORT0_HPR_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PORT1_HPR_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PORT2_HPR_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PORT3_HPR_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_0" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_1" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_2" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_3" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_0" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_1" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_2" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_3" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL" VALUE="2" />
|
||||
<PARAMETER NAME="PCW_DUAL_PARALLEL_QSPI_DATA_MODE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DUAL_STACK_QSPI_DATA_MODE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET0_ENET0_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET0_GRP_MDIO_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET0_GRP_MDIO_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET0_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_ENET0_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_ENET0_PERIPHERAL_DIVISOR1" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_ENET0_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_ENET0_PERIPHERAL_FREQMHZ" VALUE="1000 Mbps" />
|
||||
<PARAMETER NAME="PCW_ENET0_RESET_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET0_RESET_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET1_ENET1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET1_GRP_MDIO_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET1_GRP_MDIO_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET1_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_ENET1_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_ENET1_PERIPHERAL_DIVISOR1" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_ENET1_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_ENET1_PERIPHERAL_FREQMHZ" VALUE="1000 Mbps" />
|
||||
<PARAMETER NAME="PCW_ENET1_RESET_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET1_RESET_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET_RESET_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET_RESET_POLARITY" VALUE="Active Low" />
|
||||
<PARAMETER NAME="PCW_ENET_RESET_SELECT" VALUE="" />
|
||||
<PARAMETER NAME="PCW_EN_4K_TIMER" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_EN_CLK0_PORT" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_EN_CLK1_PORT" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_EN_CLK2_PORT" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_EN_CLK3_PORT" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_FCLK0_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_FCLK0_PERIPHERAL_DIVISOR0" VALUE="6" />
|
||||
<PARAMETER NAME="PCW_FCLK0_PERIPHERAL_DIVISOR1" VALUE="6" />
|
||||
<PARAMETER NAME="PCW_FCLK1_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_FCLK1_PERIPHERAL_DIVISOR0" VALUE="6" />
|
||||
<PARAMETER NAME="PCW_FCLK1_PERIPHERAL_DIVISOR1" VALUE="3" />
|
||||
<PARAMETER NAME="PCW_FCLK2_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_FCLK2_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_FCLK2_PERIPHERAL_DIVISOR1" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_FCLK3_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_FCLK3_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_FCLK3_PERIPHERAL_DIVISOR1" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_FCLK_CLK0_BUF" VALUE="TRUE" />
|
||||
<PARAMETER NAME="PCW_FCLK_CLK1_BUF" VALUE="FALSE" />
|
||||
<PARAMETER NAME="PCW_FCLK_CLK2_BUF" VALUE="FALSE" />
|
||||
<PARAMETER NAME="PCW_FCLK_CLK3_BUF" VALUE="FALSE" />
|
||||
<PARAMETER NAME="PCW_FPGA0_PERIPHERAL_FREQMHZ" VALUE="50" />
|
||||
<PARAMETER NAME="PCW_FPGA1_PERIPHERAL_FREQMHZ" VALUE="100" />
|
||||
<PARAMETER NAME="PCW_FPGA2_PERIPHERAL_FREQMHZ" VALUE="50" />
|
||||
<PARAMETER NAME="PCW_FPGA3_PERIPHERAL_FREQMHZ" VALUE="50" />
|
||||
<PARAMETER NAME="PCW_FTM_CTI_IN0" VALUE="" />
|
||||
<PARAMETER NAME="PCW_FTM_CTI_IN1" VALUE="" />
|
||||
<PARAMETER NAME="PCW_FTM_CTI_IN2" VALUE="" />
|
||||
<PARAMETER NAME="PCW_FTM_CTI_IN3" VALUE="" />
|
||||
<PARAMETER NAME="PCW_FTM_CTI_OUT0" VALUE="" />
|
||||
<PARAMETER NAME="PCW_FTM_CTI_OUT1" VALUE="" />
|
||||
<PARAMETER NAME="PCW_FTM_CTI_OUT2" VALUE="" />
|
||||
<PARAMETER NAME="PCW_FTM_CTI_OUT3" VALUE="" />
|
||||
<PARAMETER NAME="PCW_GPIO_EMIO_GPIO_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_GPIO_EMIO_GPIO_IO" VALUE="48" />
|
||||
<PARAMETER NAME="PCW_GPIO_MIO_GPIO_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_GPIO_MIO_GPIO_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_GPIO_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_I2C0_GRP_INT_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_I2C0_GRP_INT_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_I2C0_I2C0_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_I2C0_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_I2C0_RESET_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_I2C0_RESET_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_I2C1_GRP_INT_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_I2C1_GRP_INT_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_I2C1_I2C1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_I2C1_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_I2C1_RESET_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_I2C1_RESET_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_I2C_RESET_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_I2C_RESET_POLARITY" VALUE="Active Low" />
|
||||
<PARAMETER NAME="PCW_I2C_RESET_SELECT" VALUE="" />
|
||||
<PARAMETER NAME="PCW_IOPLL_CTRL_FBDIV" VALUE="54" />
|
||||
<PARAMETER NAME="PCW_IO_IO_PLL_FREQMHZ" VALUE="1800.000" />
|
||||
<PARAMETER NAME="PCW_IRQ_F2P_MODE" VALUE="DIRECT" />
|
||||
<PARAMETER NAME="PCW_MIO_0_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_0_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_0_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_0_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_10_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_10_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_10_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_10_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_11_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_11_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_11_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_11_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_12_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_12_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_12_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_12_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_13_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_13_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_13_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_13_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_14_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_14_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_14_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_14_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_15_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_15_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_15_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_15_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_16_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_16_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_16_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_16_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_17_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_17_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_17_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_17_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_18_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_18_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_18_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_18_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_19_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_19_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_19_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_19_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_1_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_1_IOTYPE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_MIO_1_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_1_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_20_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_20_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_20_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_20_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_21_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_21_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_21_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_21_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_22_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_22_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_22_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_22_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_23_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_23_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_23_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_23_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_24_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_24_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_24_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_24_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_25_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_25_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_25_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_25_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_26_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_26_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_26_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_26_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_27_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_27_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_27_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_27_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_28_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_28_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_28_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_28_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_29_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_29_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_29_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_29_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_2_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_2_IOTYPE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_MIO_2_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_2_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_30_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_30_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_30_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_30_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_31_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_31_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_31_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_31_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_32_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_32_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_32_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_32_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_33_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_33_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_33_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_33_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_34_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_34_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_34_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_34_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_35_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_35_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_35_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_35_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_36_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_36_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_36_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_36_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_37_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_37_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_37_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_37_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_38_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_38_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_38_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_38_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_39_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_39_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_39_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_39_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_3_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_3_IOTYPE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_MIO_3_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_3_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_40_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_40_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_40_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_40_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_41_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_41_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_41_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_41_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_42_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_42_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_42_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_42_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_43_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_43_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_43_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_43_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_44_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_44_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_44_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_44_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_45_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_45_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_45_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_45_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_46_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_46_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_46_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_46_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_47_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_47_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_47_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_47_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_48_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_48_IOTYPE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_MIO_48_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_48_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_49_DIRECTION" VALUE="in" />
|
||||
<PARAMETER NAME="PCW_MIO_49_IOTYPE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_MIO_49_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_49_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_4_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_4_IOTYPE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_MIO_4_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_4_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_50_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_50_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_50_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_50_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_51_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_51_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_51_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_51_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_52_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_52_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_52_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_52_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_53_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_53_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_53_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_53_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_5_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_5_IOTYPE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_MIO_5_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_5_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_6_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_6_IOTYPE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_MIO_6_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_6_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_7_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_7_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_7_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_7_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_8_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_8_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_8_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_8_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_9_DIRECTION" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_9_IOTYPE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_9_PULLUP" VALUE="" />
|
||||
<PARAMETER NAME="PCW_MIO_9_SLEW" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NAND_CYCLES_T_AR" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NAND_CYCLES_T_CLR" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NAND_CYCLES_T_RC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NAND_CYCLES_T_REA" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NAND_CYCLES_T_RR" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NAND_CYCLES_T_WC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NAND_CYCLES_T_WP" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NAND_GRP_D8_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NAND_GRP_D8_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NAND_NAND_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NAND_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_NOR_CS0_T_CEOE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_CS0_T_PC" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_CS0_T_RC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NOR_CS0_T_TR" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_CS0_T_WC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NOR_CS0_T_WP" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_CS0_WE_TIME" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_NOR_CS1_T_CEOE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_CS1_T_PC" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_CS1_T_RC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NOR_CS1_T_TR" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_CS1_T_WC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NOR_CS1_T_WP" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_CS1_WE_TIME" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_A25_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_A25_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_CS0_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_CS0_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_CS1_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_CS1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_SRAM_CS0_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_SRAM_CS0_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_SRAM_CS1_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_SRAM_CS1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_SRAM_INT_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_SRAM_INT_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_NOR_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS0_T_CEOE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS0_T_PC" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS0_T_RC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS0_T_TR" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS0_T_WC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS0_T_WP" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS0_WE_TIME" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_CEOE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_PC" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_RC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_TR" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_WC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_WP" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS1_WE_TIME" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_OVERRIDE_BASIC_CLOCK" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_PCAP_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_PCAP_PERIPHERAL_DIVISOR0" VALUE="9" />
|
||||
<PARAMETER NAME="PCW_PCAP_PERIPHERAL_FREQMHZ" VALUE="200" />
|
||||
<PARAMETER NAME="PCW_PJTAG_PERIPHERAL_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_PJTAG_PJTAG_IO" VALUE="EMIO" />
|
||||
<PARAMETER NAME="PCW_PLL_BYPASSMODE_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_PRESET_BANK0_VOLTAGE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_PRESET_BANK1_VOLTAGE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_QSPI_GRP_FBCLK_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_QSPI_GRP_FBCLK_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_QSPI_GRP_IO1_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_QSPI_GRP_IO1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_QSPI_GRP_SINGLE_SS_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_QSPI_GRP_SINGLE_SS_IO" VALUE="MIO 1 .. 6" />
|
||||
<PARAMETER NAME="PCW_QSPI_GRP_SS1_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_QSPI_GRP_SS1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_QSPI_INTERNAL_HIGHADDRESS" VALUE="0xFDFFFFFF" />
|
||||
<PARAMETER NAME="PCW_QSPI_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_QSPI_PERIPHERAL_DIVISOR0" VALUE="9" />
|
||||
<PARAMETER NAME="PCW_QSPI_PERIPHERAL_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_QSPI_PERIPHERAL_FREQMHZ" VALUE="200" />
|
||||
<PARAMETER NAME="PCW_QSPI_QSPI_IO" VALUE="MIO 1 .. 6" />
|
||||
<PARAMETER NAME="PCW_SD0_GRP_CD_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD0_GRP_CD_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD0_GRP_POW_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD0_GRP_POW_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD0_GRP_WP_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD0_GRP_WP_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD0_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_SD0_SD0_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD1_GRP_CD_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD1_GRP_CD_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD1_GRP_POW_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD1_GRP_POW_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD1_GRP_WP_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD1_GRP_WP_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD1_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_SD1_SD1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SDIO_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_SDIO_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_SDIO_PERIPHERAL_FREQMHZ" VALUE="100" />
|
||||
<PARAMETER NAME="PCW_SINGLE_QSPI_DATA_MODE" VALUE="x4" />
|
||||
<PARAMETER NAME="PCW_SMC_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_SMC_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_SMC_PERIPHERAL_FREQMHZ" VALUE="100" />
|
||||
<PARAMETER NAME="PCW_SPI0_GRP_SS0_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI0_GRP_SS0_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI0_GRP_SS1_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI0_GRP_SS1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI0_GRP_SS2_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI0_GRP_SS2_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI0_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_SPI0_SPI0_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI1_GRP_SS0_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI1_GRP_SS0_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI1_GRP_SS1_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI1_GRP_SS1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI1_GRP_SS2_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI1_GRP_SS2_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI1_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_SPI1_SPI1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_SPI_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_SPI_PERIPHERAL_FREQMHZ" VALUE="166.666666" />
|
||||
<PARAMETER NAME="PCW_S_AXI_HP0_DATA_WIDTH" VALUE="64" />
|
||||
<PARAMETER NAME="PCW_S_AXI_HP1_DATA_WIDTH" VALUE="64" />
|
||||
<PARAMETER NAME="PCW_S_AXI_HP2_DATA_WIDTH" VALUE="64" />
|
||||
<PARAMETER NAME="PCW_S_AXI_HP3_DATA_WIDTH" VALUE="64" />
|
||||
<PARAMETER NAME="PCW_TPIU_PERIPHERAL_CLKSRC" VALUE="External" />
|
||||
<PARAMETER NAME="PCW_TPIU_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_TPIU_PERIPHERAL_FREQMHZ" VALUE="200" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_16BIT_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_16BIT_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_2BIT_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_2BIT_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_32BIT_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_32BIT_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_4BIT_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_4BIT_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_8BIT_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_8BIT_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_INTERNAL_WIDTH" VALUE="2" />
|
||||
<PARAMETER NAME="PCW_TRACE_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_TRACE_TRACE_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TTC0_CLK0_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
|
||||
<PARAMETER NAME="PCW_TTC0_CLK0_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
|
||||
<PARAMETER NAME="PCW_TTC0_CLK1_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
|
||||
<PARAMETER NAME="PCW_TTC0_CLK1_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
|
||||
<PARAMETER NAME="PCW_TTC0_CLK2_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
|
||||
<PARAMETER NAME="PCW_TTC0_CLK2_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
|
||||
<PARAMETER NAME="PCW_TTC0_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_TTC0_TTC0_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TTC1_CLK0_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
|
||||
<PARAMETER NAME="PCW_TTC1_CLK0_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
|
||||
<PARAMETER NAME="PCW_TTC1_CLK1_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
|
||||
<PARAMETER NAME="PCW_TTC1_CLK1_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
|
||||
<PARAMETER NAME="PCW_TTC1_CLK2_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
|
||||
<PARAMETER NAME="PCW_TTC1_CLK2_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
|
||||
<PARAMETER NAME="PCW_TTC1_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_TTC1_TTC1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TTC_PERIPHERAL_FREQMHZ" VALUE="50" />
|
||||
<PARAMETER NAME="PCW_UART0_BAUD_RATE" VALUE="115200" />
|
||||
<PARAMETER NAME="PCW_UART0_GRP_FULL_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_UART0_GRP_FULL_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_UART0_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UART0_UART0_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_UART1_BAUD_RATE" VALUE="115200" />
|
||||
<PARAMETER NAME="PCW_UART1_GRP_FULL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UART1_GRP_FULL_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_UART1_PERIPHERAL_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_UART1_UART1_IO" VALUE="MIO 48 .. 49" />
|
||||
<PARAMETER NAME="PCW_UART_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_UART_PERIPHERAL_DIVISOR0" VALUE="18" />
|
||||
<PARAMETER NAME="PCW_UART_PERIPHERAL_FREQMHZ" VALUE="100" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_ADV_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_AL" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_BANK_ADDR_COUNT" VALUE="3" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_BL" VALUE="8" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY0" VALUE="0.25" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY1" VALUE="0.25" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY2" VALUE="0.25" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY3" VALUE="0.25" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_BUS_WIDTH" VALUE="16 Bit" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CL" VALUE="7" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH" VALUE="80.0515" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH" VALUE="80.0515" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH" VALUE="80.0515" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH" VALUE="80.0515" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_STOP_EN" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_COL_ADDR_COUNT" VALUE="10" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CWL" VALUE="6" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DEVICE_CAPACITY" VALUE="4096 MBits" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_0_LENGTH_MM" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH" VALUE="133.8645" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_1_LENGTH_MM" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH" VALUE="119.997" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_2_LENGTH_MM" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH" VALUE="121.146" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_3_LENGTH_MM" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH" VALUE="90.125" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0" VALUE="0.0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1" VALUE="0.0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2" VALUE="0.0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3" VALUE="0.0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_0_LENGTH_MM" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH" VALUE="111.7605" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_1_LENGTH_MM" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH" VALUE="123.5525" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_2_LENGTH_MM" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH" VALUE="120.714" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_3_LENGTH_MM" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH" VALUE="100.836" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DRAM_WIDTH" VALUE="16 Bits" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_ECC" VALUE="Disabled" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_FREQ_MHZ" VALUE="533.333333" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_HIGH_TEMP" VALUE="Normal (0-85)" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_MEMORY_TYPE" VALUE="DDR 3" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_PARTNO" VALUE="MT41J256M16 RE-125" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_ROW_ADDR_COUNT" VALUE="15" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_SPEED_BIN" VALUE="DDR3_1066F" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_TRAIN_DATA_EYE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_TRAIN_READ_GATE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_T_FAW" VALUE="40.0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_T_RAS_MIN" VALUE="35.0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_T_RC" VALUE="48.91" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_T_RCD" VALUE="7" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_T_RP" VALUE="7" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_USE_INTERNAL_VREF" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USB0_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USB0_PERIPHERAL_FREQMHZ" VALUE="60" />
|
||||
<PARAMETER NAME="PCW_USB0_RESET_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_USB0_RESET_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_USB0_USB0_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_USB1_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USB1_PERIPHERAL_FREQMHZ" VALUE="60" />
|
||||
<PARAMETER NAME="PCW_USB1_RESET_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_USB1_RESET_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_USB1_USB1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_USB_RESET_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_USB_RESET_POLARITY" VALUE="Active Low" />
|
||||
<PARAMETER NAME="PCW_USB_RESET_SELECT" VALUE="" />
|
||||
<PARAMETER NAME="PCW_USE_AXI_NONSECURE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USE_CROSS_TRIGGER" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USE_M_AXI_GP0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_USE_M_AXI_GP1" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USE_S_AXI_ACP" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USE_S_AXI_GP0" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USE_S_AXI_GP1" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USE_S_AXI_HP0" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USE_S_AXI_HP1" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USE_S_AXI_HP2" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USE_S_AXI_HP3" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_WDT_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
|
||||
<PARAMETER NAME="PCW_WDT_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_WDT_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_WDT_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
|
||||
<PARAMETER NAME="PCW_WDT_WDT_IO" VALUE="" />
|
||||
</PARAMETERS>
|
||||
<BUSINTERFACES >
|
||||
<BUSINTERFACE NAME="M_AXI_GP0" TYPE="MASTER" WIDTH="32" PARAMTOENABLE="PCW_USE_M_AXI_GP0" VALUE="1" />
|
||||
<BUSINTERFACE NAME="M_AXI_GP1" TYPE="MASTER" WIDTH="32" PARAMTOENABLE="PCW_USE_M_AXI_GP1" VALUE="0" />
|
||||
<BUSINTERFACE NAME="S_AXI_GP0" TYPE="TARGET" WIDTH="32" PARAMTOENABLE="PCW_USE_S_AXI_GP0" VALUE="0" />
|
||||
<BUSINTERFACE NAME="S_AXI_GP0" TYPE="TARGET" WIDTH="32" PARAMTOENABLE="PCW_USE_S_AXI_GP1" VALUE="0" />
|
||||
<BUSINTERFACE NAME="S_AXI_HP0" TYPE="TARGET" WIDTH="64" PARAMTOENABLE="PCW_USE_S_AXI_HP0" VALUE="0" />
|
||||
<BUSINTERFACE NAME="S_AXI_HP1" TYPE="TARGET" WIDTH="64" PARAMTOENABLE="PCW_USE_S_AXI_HP1" VALUE="0" />
|
||||
<BUSINTERFACE NAME="S_AXI_HP2" TYPE="TARGET" WIDTH="64" PARAMTOENABLE="PCW_USE_S_AXI_HP2" VALUE="0" />
|
||||
<BUSINTERFACE NAME="S_AXI_HP3" TYPE="TARGET" WIDTH="64" PARAMTOENABLE="PCW_USE_S_AXI_HP1" VALUE="0" />
|
||||
</BUSINTERFACES>
|
||||
<CLOCKOUTS >
|
||||
<CLOCKOUT NAME="FCLK_CLK0" FREQUENCY="50.000000" />
|
||||
<CLOCKOUT NAME="FCLK_CLK1" FREQUENCY="100.000000" />
|
||||
<CLOCKOUT NAME="FCLK_CLK2" FREQUENCY="10.000000" />
|
||||
<CLOCKOUT NAME="FCLK_CLK3" FREQUENCY="10.000000" />
|
||||
</CLOCKOUTS>
|
||||
</MODULE>
|
||||
</designInfo>
|
||||
+1317
File diff suppressed because it is too large
Load Diff
+196
@@ -0,0 +1,196 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "system_bd_rst_ps7_0_50M_0",
|
||||
"cell_name": "rst_ps7_0_50M",
|
||||
"component_reference": "xilinx.com:ip:proc_sys_reset:5.0",
|
||||
"ip_revision": "15",
|
||||
"gen_directory": "../../../../../../sjl_basic.gen/sources_1/bd/system_bd/ip/system_bd_rst_ps7_0_50M_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"C_NUM_PERP_ARESETN": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_INTERCONNECT_ARESETN": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_PERP_RST": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_BUS_RST": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_AUX_RESET_HIGH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_EXT_RESET_HIGH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_AUX_RST_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_EXT_RST_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "system_bd_rst_ps7_0_50M_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"USE_BOARD_FLOW": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"RESET_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_FAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_EXT_RST_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AUX_RST_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_EXT_RESET_HIGH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AUX_RESET_HIGH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_BUS_RST": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_PERP_RST": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_INTERCONNECT_ARESETN": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_PERP_ARESETN": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z100" } ],
|
||||
"NEXTGEN_VERSAL": [ { "value": "0" } ],
|
||||
"PACKAGE": [ { "value": "ffg900" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "15" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../sjl_basic.gen/sources_1/bd/system_bd/ip/system_bd_rst_ps7_0_50M_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2024.1.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"slowest_sync_clk": [ { "direction": "in" } ],
|
||||
"ext_reset_in": [ { "direction": "in" } ],
|
||||
"aux_reset_in": [ { "direction": "in", "driver_value": "1" } ],
|
||||
"mb_debug_sys_rst": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"dcm_locked": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"mb_reset": [ { "direction": "out", "driver_value": "0x0" } ],
|
||||
"bus_struct_reset": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"peripheral_reset": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"interconnect_aresetn": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "1" } ],
|
||||
"peripheral_aresetn": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "1" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"clock": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_RESET": [ { "value": "mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "5e+07", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "slowest_sync_clk" } ]
|
||||
}
|
||||
},
|
||||
"ext_reset": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"BOARD.ASSOCIATED_PARAM": [ { "value": "RESET_BOARD_INTERFACE", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "ext_reset_in" } ]
|
||||
}
|
||||
},
|
||||
"aux_reset": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "aux_reset_in" } ]
|
||||
}
|
||||
},
|
||||
"dbg_reset": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "mb_debug_sys_rst" } ]
|
||||
}
|
||||
},
|
||||
"mb_rst": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"TYPE": [ { "value": "PROCESSOR", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "mb_reset" } ]
|
||||
}
|
||||
},
|
||||
"bus_struct_reset": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"TYPE": [ { "value": "INTERCONNECT", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "bus_struct_reset" } ]
|
||||
}
|
||||
},
|
||||
"interconnect_low_rst": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"TYPE": [ { "value": "INTERCONNECT", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "interconnect_aresetn" } ]
|
||||
}
|
||||
},
|
||||
"peripheral_high_rst": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"TYPE": [ { "value": "PERIPHERAL", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "peripheral_reset" } ]
|
||||
}
|
||||
},
|
||||
"peripheral_low_rst": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"TYPE": [ { "value": "PERIPHERAL", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "peripheral_aresetn" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+176
@@ -0,0 +1,176 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "system_bd_spi_engine_execution_0_0",
|
||||
"cell_name": "spi_engine_execution",
|
||||
"component_reference": "analog.com:user:spi_engine_execution:1.0",
|
||||
"ip_revision": "1",
|
||||
"gen_directory": "../../../../../../sjl_basic.gen/sources_1/bd/system_bd/ip/system_bd_spi_engine_execution_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"NUM_OF_CS": [ { "value": "3", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"DEFAULT_SPI_CFG": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"DEFAULT_CLK_DIV": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"DATA_WIDTH": [ { "value": "8", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"NUM_OF_SDI": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SDO_DEFAULT": [ { "value": "\"0\"", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||
"ECHO_SCLK": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"SDI_DELAY": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "system_bd_spi_engine_execution_0_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"NUM_OF_CS": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"DEFAULT_SPI_CFG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"DEFAULT_CLK_DIV": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"DATA_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"NUM_OF_SDI": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"SDO_DEFAULT": [ { "value": "\"0\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"ECHO_SCLK": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"SDI_DELAY": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z100" } ],
|
||||
"NEXTGEN_VERSAL": [ { "value": "0" } ],
|
||||
"PACKAGE": [ { "value": "ffg900" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "1" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../sjl_basic.gen/sources_1/bd/system_bd/ip/system_bd_spi_engine_execution_0_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2024.1.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"clk": [ { "direction": "in" } ],
|
||||
"resetn": [ { "direction": "in" } ],
|
||||
"active": [ { "direction": "out" } ],
|
||||
"cmd_ready": [ { "direction": "out" } ],
|
||||
"cmd_valid": [ { "direction": "in" } ],
|
||||
"cmd": [ { "direction": "in", "size_left": "15", "size_right": "0" } ],
|
||||
"sdo_data_valid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"sdo_data_ready": [ { "direction": "out" } ],
|
||||
"sdo_data": [ { "direction": "in", "size_left": "7", "size_right": "0" } ],
|
||||
"sdi_data_ready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"sdi_data_valid": [ { "direction": "out" } ],
|
||||
"sdi_data": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
|
||||
"sync_ready": [ { "direction": "in" } ],
|
||||
"sync_valid": [ { "direction": "out" } ],
|
||||
"sync": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
|
||||
"sclk": [ { "direction": "out" } ],
|
||||
"sdo": [ { "direction": "out" } ],
|
||||
"sdo_t": [ { "direction": "out" } ],
|
||||
"sdi": [ { "direction": "in", "size_left": "0", "size_right": "0" } ],
|
||||
"cs": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||
"three_wire": [ { "direction": "out" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"ctrl": {
|
||||
"vlnv": "analog.com:interface:spi_engine_ctrl:1.0",
|
||||
"abstraction_type": "analog.com:interface:spi_engine_ctrl_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"port_maps": {
|
||||
"cmd_ready": [ { "physical_name": "cmd_ready" } ],
|
||||
"cmd_valid": [ { "physical_name": "cmd_valid" } ],
|
||||
"cmd_data": [ { "physical_name": "cmd" } ],
|
||||
"sdo_ready": [ { "physical_name": "sdo_data_ready" } ],
|
||||
"sdo_valid": [ { "physical_name": "sdo_data_valid" } ],
|
||||
"sdo_data": [ { "physical_name": "sdo_data" } ],
|
||||
"sdi_ready": [ { "physical_name": "sdi_data_ready" } ],
|
||||
"sdi_valid": [ { "physical_name": "sdi_data_valid" } ],
|
||||
"sdi_data": [ { "physical_name": "sdi_data" } ],
|
||||
"sync_ready": [ { "physical_name": "sync_ready" } ],
|
||||
"sync_valid": [ { "physical_name": "sync_valid" } ],
|
||||
"sync_data": [ { "physical_name": "sync" } ]
|
||||
}
|
||||
},
|
||||
"ctrl_signal_clock": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "ctrl", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "resetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "clk" } ]
|
||||
}
|
||||
},
|
||||
"ctrl_signal_reset": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "resetn" } ]
|
||||
}
|
||||
},
|
||||
"spi": {
|
||||
"vlnv": "analog.com:interface:spi_engine:1.0",
|
||||
"abstraction_type": "analog.com:interface:spi_engine_rtl:1.0",
|
||||
"mode": "master",
|
||||
"port_maps": {
|
||||
"sclk": [ { "physical_name": "sclk" } ],
|
||||
"sdi": [ { "physical_name": "sdi" } ],
|
||||
"sdo": [ { "physical_name": "sdo" } ],
|
||||
"sdo_t": [ { "physical_name": "sdo_t" } ],
|
||||
"three_wire": [ { "physical_name": "three_wire" } ],
|
||||
"cs": [ { "physical_name": "cs" } ]
|
||||
}
|
||||
},
|
||||
"spi_signal_clock": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "spi", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "resetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "5e+07", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "clk" } ]
|
||||
}
|
||||
},
|
||||
"spi_signal_reset": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "resetn" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+419
@@ -0,0 +1,419 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "system_bd_xadc_wiz_0_0",
|
||||
"cell_name": "system_management",
|
||||
"component_reference": "xilinx.com:ip:xadc_wiz:3.3",
|
||||
"ip_revision": "10",
|
||||
"gen_directory": "../../../../../../sjl_basic.gen/sources_1/bd/system_bd/ip/system_bd_xadc_wiz_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "system_bd_xadc_wiz_0_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"INTERFACE_SELECTION": [ { "value": "Enable_AXI", "resolve_type": "user", "usage": "all" } ],
|
||||
"SIM_FILE_SEL": [ { "value": "Default", "resolve_type": "user", "usage": "all" } ],
|
||||
"SIM_FILE_REL_PATH": [ { "value": "./", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"NUM_WAVE": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"SIM_FILE_NAME": [ { "value": "design", "resolve_type": "user", "usage": "all" } ],
|
||||
"WAVEFORM_TYPE": [ { "value": "CONSTANT", "resolve_type": "user", "usage": "all" } ],
|
||||
"STIMULUS_FREQ": [ { "value": "1.0", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ],
|
||||
"TIMING_MODE": [ { "value": "Continuous", "resolve_type": "user", "usage": "all" } ],
|
||||
"STARTUP_CHANNEL_SELECTION": [ { "value": "single_channel", "resolve_type": "user", "usage": "all" } ],
|
||||
"XADC_STARUP_SELECTION": [ { "value": "single_channel", "resolve_type": "user", "usage": "all" } ],
|
||||
"ENABLE_DCLK": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"INCREASE_ACQUISITION_TIME": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"DCLK_FREQUENCY": [ { "value": "100", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"ADC_CONVERSION_RATE": [ { "value": "1000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"SEQUENCER_MODE": [ { "value": "Off", "resolve_type": "user", "usage": "all" } ],
|
||||
"ENABLE_CALIBRATION_AVERAGING": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ENABLE_DRP": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ENABLE_RESET": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ENABLE_CONVST": [ { "value": "true", "resolve_type": "user", "usage": "all" } ],
|
||||
"ENABLE_CONVSTCLK": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ENABLE_CHANNEL": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ENABLE_EOC": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ENABLE_EOS": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ENABLE_BUSY": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ENABLE_JTAGLOCKED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ENABLE_JTAGMODIFIED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ENABLE_JTAGBUSY": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"OT_ALARM": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USER_TEMP_ALARM": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"VCCINT_ALARM": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"VCCAUX_ALARM": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ENABLE_VBRAM_ALARM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"TEMPERATURE_ALARM_TRIGGER": [ { "value": "85.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"TEMPERATURE_ALARM_RESET": [ { "value": "60.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"TEMPERATURE_ALARM_OT_TRIGGER": [ { "value": "125.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"TEMPERATURE_ALARM_OT_RESET": [ { "value": "70.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"VCCINT_ALARM_LOWER": [ { "value": "0.97", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"VCCINT_ALARM_UPPER": [ { "value": "1.03", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"VCCAUX_ALARM_LOWER": [ { "value": "1.75", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"VCCAUX_ALARM_UPPER": [ { "value": "1.89", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"VBRAM_ALARM_LOWER": [ { "value": "0.95", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"VBRAM_ALARM_UPPER": [ { "value": "1.05", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"ENABLE_VCCPINT_ALARM": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ENABLE_VCCPAUX_ALARM": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ENABLE_VCCDDRO_ALARM": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"VCCDDRO_VOLT": [ { "value": "1_2", "resolve_type": "user", "usage": "all" } ],
|
||||
"VCCPINT_ALARM_LOWER": [ { "value": "0.95", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"VCCPINT_ALARM_UPPER": [ { "value": "1.00", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"VCCPAUX_ALARM_LOWER": [ { "value": "1.71", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"VCCPAUX_ALARM_UPPER": [ { "value": "1.8", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"VCCDDRO_ALARM_LOWER": [ { "value": "1.2", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"VCCDDRO_ALARM_UPPER": [ { "value": "1.25", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"SINGLE_CHANNEL_SELECTION": [ { "value": "TEMPERATURE", "resolve_type": "user", "usage": "all" } ],
|
||||
"SINGLE_CHANNEL_ENABLE_CALIBRATION": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"BIPOLAR_OPERATION": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"SINGLE_CHANNEL_ACQUISITION_TIME": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CHANNEL_AVERAGING": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
|
||||
"ADC_OFFSET_CALIBRATION": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ADC_OFFSET_AND_GAIN_CALIBRATION": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"SENSOR_OFFSET_CALIBRATION": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"SENSOR_OFFSET_AND_GAIN_CALIBRATION": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ENABLE_EXTERNAL_MUX": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"EXTERNAL_MUX_CHANNEL": [ { "value": "VP_VN", "resolve_type": "user", "usage": "all" } ],
|
||||
"EXTERNAL_MUXADDR_ENABLE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CHANNEL_ENABLE_CALIBRATION": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CHANNEL_ENABLE_TEMPERATURE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CHANNEL_ENABLE_VCCINT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CHANNEL_ENABLE_VCCAUX": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CHANNEL_ENABLE_VP_VN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CHANNEL_ENABLE_VREFP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CHANNEL_ENABLE_VREFN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CHANNEL_ENABLE_VBRAM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"AVERAGE_ENABLE_VBRAM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CHANNEL_ENABLE_VCCPINT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"AVERAGE_ENABLE_VCCPINT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CHANNEL_ENABLE_VCCPAUX": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"AVERAGE_ENABLE_VCCPAUX": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CHANNEL_ENABLE_VCCDDRO": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"AVERAGE_ENABLE_VCCDDRO": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CHANNEL_ENABLE_VAUXP0_VAUXN0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CHANNEL_ENABLE_VAUXP1_VAUXN1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CHANNEL_ENABLE_VAUXP2_VAUXN2": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CHANNEL_ENABLE_VAUXP3_VAUXN3": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CHANNEL_ENABLE_VAUXP4_VAUXN4": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CHANNEL_ENABLE_VAUXP5_VAUXN5": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CHANNEL_ENABLE_VAUXP6_VAUXN6": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CHANNEL_ENABLE_VAUXP7_VAUXN7": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CHANNEL_ENABLE_VAUXP8_VAUXN8": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CHANNEL_ENABLE_VAUXP9_VAUXN9": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CHANNEL_ENABLE_VAUXP10_VAUXN10": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CHANNEL_ENABLE_VAUXP11_VAUXN11": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CHANNEL_ENABLE_VAUXP12_VAUXN12": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CHANNEL_ENABLE_VAUXP13_VAUXN13": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CHANNEL_ENABLE_VAUXP14_VAUXN14": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CHANNEL_ENABLE_VAUXP15_VAUXN15": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"AVERAGE_ENABLE_VP_VN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"AVERAGE_ENABLE_VAUXP0_VAUXN0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"AVERAGE_ENABLE_VAUXP1_VAUXN1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"AVERAGE_ENABLE_VAUXP2_VAUXN2": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"AVERAGE_ENABLE_VAUXP3_VAUXN3": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"AVERAGE_ENABLE_VAUXP4_VAUXN4": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"AVERAGE_ENABLE_VAUXP5_VAUXN5": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"AVERAGE_ENABLE_VAUXP6_VAUXN6": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"AVERAGE_ENABLE_VAUXP7_VAUXN7": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"AVERAGE_ENABLE_VAUXP8_VAUXN8": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"AVERAGE_ENABLE_VAUXP9_VAUXN9": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"AVERAGE_ENABLE_VAUXP10_VAUXN10": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"AVERAGE_ENABLE_VAUXP11_VAUXN11": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"AVERAGE_ENABLE_VAUXP12_VAUXN12": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"AVERAGE_ENABLE_VAUXP13_VAUXN13": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"AVERAGE_ENABLE_VAUXP14_VAUXN14": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"AVERAGE_ENABLE_VAUXP15_VAUXN15": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"AVERAGE_ENABLE_TEMPERATURE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"AVERAGE_ENABLE_VCCINT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"AVERAGE_ENABLE_VCCAUX": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"BIPOLAR_VP_VN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"BIPOLAR_VAUXP0_VAUXN0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"BIPOLAR_VAUXP1_VAUXN1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"BIPOLAR_VAUXP2_VAUXN2": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"BIPOLAR_VAUXP3_VAUXN3": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"BIPOLAR_VAUXP4_VAUXN4": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"BIPOLAR_VAUXP5_VAUXN5": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"BIPOLAR_VAUXP6_VAUXN6": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"BIPOLAR_VAUXP7_VAUXN7": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"BIPOLAR_VAUXP8_VAUXN8": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"BIPOLAR_VAUXP9_VAUXN9": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"BIPOLAR_VAUXP10_VAUXN10": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"BIPOLAR_VAUXP11_VAUXN11": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"BIPOLAR_VAUXP12_VAUXN12": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"BIPOLAR_VAUXP13_VAUXN13": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"BIPOLAR_VAUXP14_VAUXN14": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"BIPOLAR_VAUXP15_VAUXN15": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ACQUISITION_TIME_VP_VN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ACQUISITION_TIME_VAUXP0_VAUXN0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ACQUISITION_TIME_VAUXP1_VAUXN1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ACQUISITION_TIME_VAUXP2_VAUXN2": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ACQUISITION_TIME_VAUXP3_VAUXN3": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ACQUISITION_TIME_VAUXP4_VAUXN4": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ACQUISITION_TIME_VAUXP5_VAUXN5": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ACQUISITION_TIME_VAUXP6_VAUXN6": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ACQUISITION_TIME_VAUXP7_VAUXN7": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ACQUISITION_TIME_VAUXP8_VAUXN8": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ACQUISITION_TIME_VAUXP9_VAUXN9": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ACQUISITION_TIME_VAUXP10_VAUXN10": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ACQUISITION_TIME_VAUXP11_VAUXN11": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ACQUISITION_TIME_VAUXP12_VAUXN12": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ACQUISITION_TIME_VAUXP13_VAUXN13": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ACQUISITION_TIME_VAUXP14_VAUXN14": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ACQUISITION_TIME_VAUXP15_VAUXN15": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ENABLE_JTAG_ARBITER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ACQUISITION_TIME": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ENABLE_TEMP_BUS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ENABLE_AXI4STREAM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"FIFO_DEPTH": [ { "value": "7", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"POWER_DOWN_ADCA": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"POWER_DOWN_ADCB": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"c_component_name": [ { "value": "system_bd_xadc_wiz_0_0", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_SIM_FILE_SEL": [ { "value": "Default", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_SIM_FILE_REL_PATH": [ { "value": "./", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_SIM_FILE_NAME": [ { "value": "design", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_HAS_DCLK": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_DRP": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_RESET": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_CONVST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_CONVSTCLK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_VP": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_VN": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_CHANNEL": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_EOC": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_EOS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_BUSY": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_JTAGLOCKED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_JTAGMODIFIED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_JTAGBUSY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_EXTERNAL_MUX": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_EXTERNAL_MUX_CHANNEL": [ { "value": "VP_VN", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_EXTERNAL_MUXADDR_ENABLE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DCLK_FREQUENCY": [ { "value": "100", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SAMPLING_RATE": [ { "value": "961538.4615384615", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_HAS_OT_ALARM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_USER_TEMP_ALARM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_VCCINT_ALARM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_VCCAUX_ALARM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_VBRAM_ALARM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_VCCPINT_ALARM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_VCCPAUX_ALARM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_VCCDDRO_ALARM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CONFIGURATION_R0": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CONFIGURATION_R1": [ { "value": "12719", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CONFIGURATION_R2": [ { "value": "1024", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ALARM_LIMIT_R0": [ { "value": "46573", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ALARM_LIMIT_R1": [ { "value": "22500", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ALARM_LIMIT_R2": [ { "value": "41287", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ALARM_LIMIT_R3": [ { "value": "51763", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ALARM_LIMIT_R4": [ { "value": "43322", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ALARM_LIMIT_R5": [ { "value": "21190", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ALARM_LIMIT_R6": [ { "value": "38229", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ALARM_LIMIT_R7": [ { "value": "44622", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ALARM_LIMIT_R8": [ { "value": "22937", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ALARM_LIMIT_R9": [ { "value": "20753", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ALARM_LIMIT_R10": [ { "value": "21845", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ALARM_LIMIT_R11": [ { "value": "20753", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ALARM_LIMIT_R12": [ { "value": "39321", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ALARM_LIMIT_R13": [ { "value": "37355", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ALARM_LIMIT_R14": [ { "value": "27306", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ALARM_LIMIT_R15": [ { "value": "26214", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SEQUENCE_R0": [ { "value": "256", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SEQUENCE_R1": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SEQUENCE_R2": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SEQUENCE_R3": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SEQUENCE_R4": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SEQUENCE_R5": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SEQUENCE_R6": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SEQUENCE_R7": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_VAUX0": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_VAUX1": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_VAUX2": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_VAUX3": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_VAUX4": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_VAUX5": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_VAUX6": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_VAUX7": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_VAUX8": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_VAUX9": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_VAUX10": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_VAUX11": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_VAUX12": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_VAUX13": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_VAUX14": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_VAUX15": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_AXI": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_AXI4STREAM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_TEMP_BUS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_FIFO_DEPTH": [ { "value": "7", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INCLUDE_INTR": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z100" } ],
|
||||
"NEXTGEN_VERSAL": [ { "value": "0" } ],
|
||||
"PACKAGE": [ { "value": "ffg900" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "10" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../sjl_basic.gen/sources_1/bd/system_bd/ip/system_bd_xadc_wiz_0_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2024.1.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"s_axi_aclk": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_aresetn": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_awaddr": [ { "direction": "in", "size_left": "10", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_awvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_awready": [ { "direction": "out" } ],
|
||||
"s_axi_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_wvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_wready": [ { "direction": "out" } ],
|
||||
"s_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s_axi_bvalid": [ { "direction": "out" } ],
|
||||
"s_axi_bready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_araddr": [ { "direction": "in", "size_left": "10", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_arvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_arready": [ { "direction": "out" } ],
|
||||
"s_axi_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"s_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s_axi_rvalid": [ { "direction": "out" } ],
|
||||
"s_axi_rready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"ip2intc_irpt": [ { "direction": "out" } ],
|
||||
"vp_in": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"vn_in": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"channel_out": [ { "direction": "out", "size_left": "4", "size_right": "0" } ],
|
||||
"eoc_out": [ { "direction": "out" } ],
|
||||
"alarm_out": [ { "direction": "out" } ],
|
||||
"eos_out": [ { "direction": "out" } ],
|
||||
"busy_out": [ { "direction": "out" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"s_axi_lite": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "5e+07", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "11", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"ARADDR": [ { "physical_name": "s_axi_araddr" } ],
|
||||
"ARREADY": [ { "physical_name": "s_axi_arready" } ],
|
||||
"ARVALID": [ { "physical_name": "s_axi_arvalid" } ],
|
||||
"AWADDR": [ { "physical_name": "s_axi_awaddr" } ],
|
||||
"AWREADY": [ { "physical_name": "s_axi_awready" } ],
|
||||
"AWVALID": [ { "physical_name": "s_axi_awvalid" } ],
|
||||
"BREADY": [ { "physical_name": "s_axi_bready" } ],
|
||||
"BRESP": [ { "physical_name": "s_axi_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "s_axi_bvalid" } ],
|
||||
"RDATA": [ { "physical_name": "s_axi_rdata" } ],
|
||||
"RREADY": [ { "physical_name": "s_axi_rready" } ],
|
||||
"RRESP": [ { "physical_name": "s_axi_rresp" } ],
|
||||
"RVALID": [ { "physical_name": "s_axi_rvalid" } ],
|
||||
"WDATA": [ { "physical_name": "s_axi_wdata" } ],
|
||||
"WREADY": [ { "physical_name": "s_axi_wready" } ],
|
||||
"WSTRB": [ { "physical_name": "s_axi_wstrb" } ],
|
||||
"WVALID": [ { "physical_name": "s_axi_wvalid" } ]
|
||||
}
|
||||
},
|
||||
"s_axi_aclk": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "s_axi_lite:M_AXIS", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "s_axi_aresetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "5e+07", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "s_axi_aclk" } ]
|
||||
}
|
||||
},
|
||||
"s_axi_aresetn": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "s_axi_aresetn" } ]
|
||||
}
|
||||
},
|
||||
"intr": {
|
||||
"vlnv": "xilinx.com:signal:interrupt:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"SENSITIVITY": [ { "value": "LEVEL_HIGH", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"PortWidth": [ { "value": "1", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"INTERRUPT": [ { "physical_name": "ip2intc_irpt" } ]
|
||||
}
|
||||
},
|
||||
"Vp_Vn": {
|
||||
"vlnv": "xilinx.com:interface:diff_analog_io:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:diff_analog_io_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"port_maps": {
|
||||
"V_N": [ { "physical_name": "vn_in" } ],
|
||||
"V_P": [ { "physical_name": "vp_in" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+1523
File diff suppressed because it is too large
Load Diff
+308
@@ -0,0 +1,308 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "system_bd_xlconcat_0_0",
|
||||
"cell_name": "xlconcat_irq",
|
||||
"component_reference": "xilinx.com:ip:xlconcat:2.1",
|
||||
"ip_revision": "6",
|
||||
"gen_directory": "../../../../../../sjl_basic.gen/sources_1/bd/system_bd/ip/system_bd_xlconcat_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "system_bd_xlconcat_0_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"NUM_PORTS": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN0_WIDTH": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN1_WIDTH": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN2_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN3_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN4_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN5_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN6_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN7_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN8_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN9_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN10_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN11_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN12_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN13_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN14_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN15_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN16_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN17_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN18_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN19_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN20_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN21_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN22_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN23_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN24_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN25_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN26_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN27_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN28_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN29_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN30_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN31_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN32_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN33_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN34_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN35_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN36_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN37_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN38_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN39_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN40_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN41_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN42_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN43_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN44_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN45_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN46_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN47_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN48_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN49_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN50_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN51_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN52_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN53_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN54_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN55_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN56_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN57_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN58_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN59_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN60_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN61_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN62_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN63_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN64_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN65_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN66_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN67_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN68_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN69_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN70_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN71_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN72_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN73_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN74_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN75_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN76_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN77_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN78_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN79_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN80_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN81_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN82_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN83_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN84_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN85_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN86_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN87_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN88_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN89_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN90_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN91_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN92_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN93_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN94_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN95_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN96_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN97_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN98_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN99_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN100_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN101_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN102_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN103_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN104_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN105_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN106_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN107_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN108_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN109_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN110_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN111_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN112_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN113_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN114_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN115_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN116_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN117_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN118_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN119_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN120_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN121_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN122_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN123_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN124_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN125_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN126_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN127_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"dout_width": [ { "value": "2", "value_src": "user", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"IN0_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN1_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN2_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN3_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN4_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN5_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN6_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN7_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN8_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN9_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN10_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN11_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN12_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN13_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN14_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN15_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN16_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN17_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN18_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN19_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN20_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN21_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN22_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN23_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN24_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN25_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN26_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN27_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN28_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN29_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN30_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN31_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN32_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN33_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN34_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN35_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN36_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN37_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN38_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN39_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN40_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN41_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN42_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN43_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN44_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN45_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN46_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN47_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN48_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN49_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN50_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN51_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN52_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN53_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN54_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN55_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN56_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN57_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN58_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN59_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN60_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN61_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN62_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN63_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN64_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN65_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN66_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN67_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN68_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN69_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN70_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN71_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN72_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN73_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN74_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN75_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN76_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN77_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN78_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN79_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN80_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN81_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN82_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN83_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN84_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN85_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN86_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN87_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN88_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN89_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN90_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN91_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN92_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN93_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN94_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN95_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN96_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN97_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN98_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN99_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN100_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN101_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN102_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN103_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN104_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN105_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN106_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN107_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN108_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN109_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN110_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN111_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN112_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN113_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN114_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN115_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN116_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN117_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN118_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN119_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN120_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN121_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN122_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN123_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN124_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN125_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN126_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN127_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"dout_width": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"NUM_PORTS": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z100" } ],
|
||||
"NEXTGEN_VERSAL": [ { "value": "0" } ],
|
||||
"PACKAGE": [ { "value": "ffg900" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "6" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../sjl_basic.gen/sources_1/bd/system_bd/ip/system_bd_xlconcat_0_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2024.1.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"In0": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"In1": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"dout": [ { "direction": "out", "size_left": "1", "size_right": "0" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,249 @@
|
||||
{
|
||||
"graphjs": {
|
||||
"version": "1.0",
|
||||
"keys": [
|
||||
{
|
||||
"abrv": "VH",
|
||||
"name": "vert_hid",
|
||||
"type": "int",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "VM",
|
||||
"name": "vert_name",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "VT",
|
||||
"name": "vert_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "BA",
|
||||
"name": "base_addr",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "HA",
|
||||
"name": "high_addr",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "BP",
|
||||
"name": "base_param",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "HP",
|
||||
"name": "high_param",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MA",
|
||||
"name": "master_addrspace",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MX",
|
||||
"name": "master_instance",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MI",
|
||||
"name": "master_interface",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MS",
|
||||
"name": "master_segment",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MV",
|
||||
"name": "master_vlnv",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "SX",
|
||||
"name": "slave_instance",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "SI",
|
||||
"name": "slave_interface",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MM",
|
||||
"name": "slave_memmap",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "SS",
|
||||
"name": "slave_segment",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "SV",
|
||||
"name": "slave_vlnv",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "TM",
|
||||
"name": "memory_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "TU",
|
||||
"name": "usage_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "LT",
|
||||
"name": "lock_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "BT",
|
||||
"name": "boot_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "EH",
|
||||
"name": "edge_hid",
|
||||
"type": "int",
|
||||
"for": "edge"
|
||||
}
|
||||
],
|
||||
"vertice_type_order": [
|
||||
{
|
||||
"abrv": "BC",
|
||||
"desc": "Block Container"
|
||||
},
|
||||
{
|
||||
"abrv": "PR",
|
||||
"desc": "Parital Reference"
|
||||
},
|
||||
{
|
||||
"abrv": "VR",
|
||||
"desc": "Variant"
|
||||
},
|
||||
{
|
||||
"abrv": "PM",
|
||||
"desc": "Variant Permutations"
|
||||
},
|
||||
{
|
||||
"abrv": "CX",
|
||||
"desc": "Boundary Connection"
|
||||
},
|
||||
{
|
||||
"abrv": "AC",
|
||||
"desc": "Assignment Coordinate"
|
||||
},
|
||||
{
|
||||
"abrv": "ACE",
|
||||
"desc": "Excluded Assign Coordinate"
|
||||
},
|
||||
{
|
||||
"abrv": "APX",
|
||||
"desc": "Boundary Aperture"
|
||||
},
|
||||
{
|
||||
"abrv": "CIP",
|
||||
"desc": "High level Processing System"
|
||||
}
|
||||
],
|
||||
"vertices": {
|
||||
"V0": {
|
||||
"VM": "system_bd",
|
||||
"VT": "BC"
|
||||
},
|
||||
"V1": {
|
||||
"VH": "2",
|
||||
"VM": "system_bd",
|
||||
"VT": "VR"
|
||||
},
|
||||
"V2": {
|
||||
"VH": "2",
|
||||
"VT": "PM",
|
||||
"TU": "active"
|
||||
},
|
||||
"V3": {
|
||||
"VT": "AC",
|
||||
"BA": "0x43C00000",
|
||||
"HA": "0x43C0FFFF",
|
||||
"BP": "C_BASEADDR",
|
||||
"HP": "C_HIGHADDR",
|
||||
"MA": "Data",
|
||||
"MX": "/processing_system7_0",
|
||||
"MI": "M_AXI_GP0",
|
||||
"MS": "SEG_axi_spi_engine_axi_lite",
|
||||
"MV": "xilinx.com:ip:processing_system7:5.5",
|
||||
"SX": "/axi_spi_engine/axi_spi_engine",
|
||||
"SI": "s_axi",
|
||||
"SS": "axi_lite",
|
||||
"SV": "analog.com:user:axi_spi_engine:1.0",
|
||||
"TM": "both",
|
||||
"TU": "register"
|
||||
},
|
||||
"V4": {
|
||||
"VT": "AC",
|
||||
"BA": "0x43C10000",
|
||||
"HA": "0x43C1FFFF",
|
||||
"BP": "C_BASEADDR",
|
||||
"HP": "C_HIGHADDR",
|
||||
"MA": "Data",
|
||||
"MX": "/processing_system7_0",
|
||||
"MI": "M_AXI_GP0",
|
||||
"MS": "SEG_system_management_Reg",
|
||||
"MV": "xilinx.com:ip:processing_system7:5.5",
|
||||
"SX": "/system_management",
|
||||
"SI": "s_axi_lite",
|
||||
"SS": "Reg",
|
||||
"SV": "xilinx.com:ip:xadc_wiz:3.3",
|
||||
"TM": "both",
|
||||
"TU": "register"
|
||||
}
|
||||
},
|
||||
"edges": [
|
||||
{
|
||||
"src": "V0",
|
||||
"trg": "V1"
|
||||
},
|
||||
{
|
||||
"src": "V1",
|
||||
"trg": "V2"
|
||||
},
|
||||
{
|
||||
"src": "V3",
|
||||
"trg": "V2",
|
||||
"EH": "2"
|
||||
},
|
||||
{
|
||||
"src": "V4",
|
||||
"trg": "V2",
|
||||
"EH": "2"
|
||||
}
|
||||
]
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,51 @@
|
||||
{
|
||||
"ActiveEmotionalView":"Default View",
|
||||
"Default View_ScaleFactor":"0.946943",
|
||||
"Default View_TopLeft":"-508,3",
|
||||
"ExpandedHierarchyInLayout":"",
|
||||
"guistr":"# # String gsaved with Nlview 7.7.1 2023-07-26 3bc4126617 VDI=43 GEI=38 GUI=JA:21.0 TLS
|
||||
# -string -flagsOSRD
|
||||
preplace port ddr -pg 1 -lvl 3 -x 870 -y 280 -defaultsOSRD
|
||||
preplace port fixed_io -pg 1 -lvl 3 -x 870 -y 300 -defaultsOSRD
|
||||
preplace port pjtag -pg 1 -lvl 0 -x 0 -y 270 -defaultsOSRD
|
||||
preplace port spi -pg 1 -lvl 3 -x 870 -y 750 -defaultsOSRD
|
||||
preplace port port-id_spi_active -pg 1 -lvl 3 -x 870 -y 770 -defaultsOSRD
|
||||
preplace port port-id_ps_clk_100m -pg 1 -lvl 3 -x 870 -y 360 -defaultsOSRD
|
||||
preplace port port-id_ps_clk_50m -pg 1 -lvl 3 -x 870 -y 320 -defaultsOSRD
|
||||
preplace port vp_vn -pg 1 -lvl 0 -x 0 -y 100 -defaultsOSRD
|
||||
preplace portBus gpio_i -pg 1 -lvl 3 -x 870 -y 220 -defaultsOSRD -right
|
||||
preplace portBus gpio_o -pg 1 -lvl 3 -x 870 -y 240 -defaultsOSRD
|
||||
preplace portBus gpio_t -pg 1 -lvl 3 -x 870 -y 260 -defaultsOSRD
|
||||
preplace inst processing_system7_0 -pg 1 -lvl 1 -x 250 -y 290 -defaultsOSRD
|
||||
preplace inst axi_spi_engine -pg 1 -lvl 1 -x 250 -y 770 -defaultsOSRD
|
||||
preplace inst rst_ps7_0_50M -pg 1 -lvl 2 -x 660 -y 460 -defaultsOSRD
|
||||
preplace inst axi_interconnect -pg 1 -lvl 1 -x 250 -y 560 -defaultsOSRD
|
||||
preplace inst xlconcat_irq -pg 1 -lvl 2 -x 660 -y 680 -defaultsOSRD -orient R180
|
||||
preplace inst system_management -pg 1 -lvl 2 -x 660 -y 110 -defaultsOSRD
|
||||
preplace netloc processing_system7_0_FCLK_CLK0 1 0 3 20 120 480 320 N
|
||||
preplace netloc processing_system7_0_FCLK_RESET0_N 1 1 1 450 380n
|
||||
preplace netloc rst_ps7_0_50M_peripheral_aresetn 1 0 3 40 130 470J 310 840
|
||||
preplace netloc axi_spi_engine_active 1 1 2 NJ 770 NJ
|
||||
preplace netloc axi_spi_engine_irq 1 1 2 N 790 840
|
||||
preplace netloc xlconcat_0_dout 1 0 2 30 860 480
|
||||
preplace netloc processing_system7_0_FCLK_CLK1 1 1 2 NJ 360 NJ
|
||||
preplace netloc GPIO_I_0_1 1 1 2 N 220 N
|
||||
preplace netloc processing_system7_0_GPIO_O 1 1 2 NJ 240 NJ
|
||||
preplace netloc processing_system7_0_GPIO_T 1 1 2 NJ 260 NJ
|
||||
preplace netloc system_management_ip2intc_irpt 1 2 1 850 60n
|
||||
preplace netloc axi_interconnect_0_M00_AXI 1 0 2 50 850 450
|
||||
preplace netloc processing_system7_0_FIXED_IO 1 1 2 NJ 300 N
|
||||
preplace netloc processing_system7_0_M_AXI_GP0 1 0 2 50 140 450
|
||||
preplace netloc processing_system7_0_DDR 1 1 2 NJ 280 N
|
||||
preplace netloc PJTAG_0_1 1 0 1 N 270
|
||||
preplace netloc axi_spi_engine_spi_0 1 1 2 NJ 750 NJ
|
||||
preplace netloc axi_interconnect_M01_AXI 1 1 1 460 80n
|
||||
preplace netloc Vp_Vn_0_1 1 0 2 NJ 100 NJ
|
||||
levelinfo -pg 1 0 250 660 870
|
||||
pagesize -pg 1 -db -bbox -sgen -100 0 1020 870
|
||||
"
|
||||
}
|
||||
{
|
||||
"da_axi4_cnt":"3",
|
||||
"da_ps7_cnt":"1"
|
||||
}
|
||||
@@ -0,0 +1,28 @@
|
||||
{
|
||||
"ActiveEmotionalView":"Default View",
|
||||
"Default View_ScaleFactor":"1.0",
|
||||
"Default View_TopLeft":"-578,-716",
|
||||
"ExpandedHierarchyInLayout":"",
|
||||
"guistr":"# # String gsaved with Nlview 7.7.1 2023-07-26 3bc4126617 VDI=43 GEI=38 GUI=JA:21.0 TLS
|
||||
# -string -flagsOSRD
|
||||
preplace port s_axi -pg 1 -lvl 0 -x 0 -y -320 -defaultsOSRD
|
||||
preplace port port-id_s_axi_aclk -pg 1 -lvl 0 -x 0 -y -300 -defaultsOSRD
|
||||
preplace port port-id_s_axi_aresetn -pg 1 -lvl 0 -x 0 -y -340 -defaultsOSRD
|
||||
preplace port port-id_spi_clk -pg 1 -lvl 0 -x 0 -y -280 -defaultsOSRD
|
||||
preplace port port-id_active -pg 1 -lvl 3 -x 730 -y -280 -defaultsOSRD
|
||||
preplace port port-id_irq -pg 1 -lvl 3 -x 730 -y -370 -defaultsOSRD
|
||||
preplace inst axi_spi_engine -pg 1 -lvl 1 -x 320 -y -290 -defaultsOSRD
|
||||
preplace inst spi_engine_execution -pg 1 -lvl 2 -x 590 -y -290 -defaultsOSRD
|
||||
preplace netloc s_axi_aclk_0_1 1 0 1 N -300
|
||||
preplace netloc s_axi_aresetn_0_1 1 0 1 180 -340n
|
||||
preplace netloc spi_clk_0_1 1 0 2 170 -380 470
|
||||
preplace netloc axi_spi_engine_spi_resetn 1 1 1 N -270
|
||||
preplace netloc spi_engine_execution_active 1 2 1 N -280
|
||||
preplace netloc axi_spi_engine_irq 1 1 2 460J -370 NJ
|
||||
preplace netloc axi_spi_engine_0_spi_engine_ctrl 1 1 1 N -310
|
||||
preplace netloc Conn1 1 0 1 N -320
|
||||
levelinfo -pg 1 0 320 590 730
|
||||
pagesize -pg 1 -db -bbox -sgen -150 -670 830 180
|
||||
"
|
||||
}
|
||||
0
|
||||
+9
@@ -0,0 +1,9 @@
|
||||
# the "-quiet" option is added for the axi_spi_engine ip where the ad_rst.v
|
||||
# module is not always inferred and this causes critical warnings
|
||||
|
||||
set_property -quiet ASYNC_REG TRUE [get_cells -hierarchical -filter {name =~ *rst_async_d*_reg}]
|
||||
set_property -quiet ASYNC_REG TRUE [get_cells -hierarchical -filter {name =~ *rst_sync_reg}]
|
||||
|
||||
set_false_path -quiet -to [get_pins -hierarchical *rst_sync_reg/PRE]
|
||||
set_false_path -quiet -to [get_pins -hierarchical *rst_async_d1_reg/PRE]
|
||||
set_false_path -quiet -to [get_pins -hierarchical *rst_async_d2_reg/PRE]
|
||||
+714
@@ -0,0 +1,714 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "ad9361_clk_gen_cmos_1t1r",
|
||||
"component_reference": "xilinx.com:ip:clk_wiz:6.0",
|
||||
"ip_revision": "14",
|
||||
"gen_directory": "../../../../sjl_basic.gen/sources_1/ip/ad9361_clk_gen_cmos_1t1r",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "ad9361_clk_gen_cmos_1t1r", "resolve_type": "user", "usage": "all" } ],
|
||||
"USER_CLK_FREQ0": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"USER_CLK_FREQ1": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"USER_CLK_FREQ2": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"USER_CLK_FREQ3": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"ENABLE_CLOCK_MONITOR": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"OPTIMIZE_CLOCKING_STRUCTURE_EN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ENABLE_USER_CLOCK0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ENABLE_USER_CLOCK1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ENABLE_USER_CLOCK2": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ENABLE_USER_CLOCK3": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Enable_PLL0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Enable_PLL1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"REF_CLK_FREQ": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PRECISION": [ { "value": "1", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PRIMITIVE": [ { "value": "MMCM", "resolve_type": "user", "usage": "all" } ],
|
||||
"PRIMTYPE_SEL": [ { "value": "mmcm_adv", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLOCK_MGR_TYPE": [ { "value": "auto", "resolve_type": "user", "usage": "all" } ],
|
||||
"USE_FREQ_SYNTH": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_SPREAD_SPECTRUM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_PHASE_ALIGNMENT": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_MIN_POWER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_DYN_PHASE_SHIFT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_DYN_RECONFIG": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"JITTER_SEL": [ { "value": "No_Jitter", "resolve_type": "user", "usage": "all" } ],
|
||||
"PRIM_IN_FREQ": [ { "value": "50", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PRIM_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"IN_FREQ_UNITS": [ { "value": "Units_MHz", "resolve_type": "user", "usage": "all" } ],
|
||||
"PHASESHIFT_MODE": [ { "value": "WAVEFORM", "resolve_type": "user", "usage": "all" } ],
|
||||
"IN_JITTER_UNITS": [ { "value": "Units_UI", "resolve_type": "user", "usage": "all" } ],
|
||||
"RELATIVE_INCLK": [ { "value": "REL_PRIMARY", "resolve_type": "user", "usage": "all" } ],
|
||||
"USE_INCLK_SWITCHOVER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"SECONDARY_IN_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"SECONDARY_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"SECONDARY_PORT": [ { "value": "clk_in2", "resolve_type": "user", "usage": "all" } ],
|
||||
"SECONDARY_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "user", "usage": "all" } ],
|
||||
"JITTER_OPTIONS": [ { "value": "UI", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKIN1_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKIN2_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PRIM_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"SECONDARY_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKIN1_JITTER_PS": [ { "value": "200.0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT1_USED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT2_USED": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT3_USED": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT4_USED": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT5_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT6_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT7_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"NUM_OUT_CLKS": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CLK_OUT1_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLK_OUT2_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLK_OUT3_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLK_OUT4_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLK_OUT5_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLK_OUT6_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLK_OUT7_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"PRIMARY_PORT": [ { "value": "clk_in1", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLK_OUT1_PORT": [ { "value": "clk_out1", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLK_OUT2_PORT": [ { "value": "clk_out2", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLK_OUT3_PORT": [ { "value": "clk_out3", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLK_OUT4_PORT": [ { "value": "clk_out4", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLK_OUT5_PORT": [ { "value": "clk_out5", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLK_OUT6_PORT": [ { "value": "clk_out6", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLK_OUT7_PORT": [ { "value": "clk_out7", "resolve_type": "user", "usage": "all" } ],
|
||||
"DADDR_PORT": [ { "value": "daddr", "resolve_type": "user", "usage": "all" } ],
|
||||
"DCLK_PORT": [ { "value": "dclk", "resolve_type": "user", "usage": "all" } ],
|
||||
"DRDY_PORT": [ { "value": "drdy", "resolve_type": "user", "usage": "all" } ],
|
||||
"DWE_PORT": [ { "value": "dwe", "resolve_type": "user", "usage": "all" } ],
|
||||
"DIN_PORT": [ { "value": "din", "resolve_type": "user", "usage": "all" } ],
|
||||
"DOUT_PORT": [ { "value": "dout", "resolve_type": "user", "usage": "all" } ],
|
||||
"DEN_PORT": [ { "value": "den", "resolve_type": "user", "usage": "all" } ],
|
||||
"PSCLK_PORT": [ { "value": "psclk", "resolve_type": "user", "usage": "all" } ],
|
||||
"PSEN_PORT": [ { "value": "psen", "resolve_type": "user", "usage": "all" } ],
|
||||
"PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "user", "usage": "all" } ],
|
||||
"PSDONE_PORT": [ { "value": "psdone", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "50", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "100", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT2_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "150", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT3_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT3_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "200", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT4_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT4_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT5_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT5_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT5_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT6_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT6_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT7_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT7_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"USE_MAX_I_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_MIN_O_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT1_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT2_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT3_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT4_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"PRIM_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKOUT1_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKOUT2_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKOUT3_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKOUT4_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKOUT5_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKOUT6_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKOUT7_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
|
||||
"FEEDBACK_SOURCE": [ { "value": "FDBK_AUTO", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKFB_IN_SIGNALING": [ { "value": "SINGLE", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKFB_IN_PORT": [ { "value": "clkfb_in", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKFB_IN_P_PORT": [ { "value": "clkfb_in_p", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKFB_IN_N_PORT": [ { "value": "clkfb_in_n", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKFB_OUT_PORT": [ { "value": "clkfb_out", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKFB_OUT_P_PORT": [ { "value": "clkfb_out_p", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKFB_OUT_N_PORT": [ { "value": "clkfb_out_n", "resolve_type": "user", "usage": "all" } ],
|
||||
"PLATFORM": [ { "value": "UNKNOWN", "resolve_type": "user", "usage": "all" } ],
|
||||
"SUMMARY_STRINGS": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ],
|
||||
"USE_LOCKED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CALC_DONE": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ],
|
||||
"USE_RESET": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_POWER_DOWN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_STATUS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_FREEZE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_CLK_VALID": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_INCLK_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_CLKFB_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"RESET_PORT": [ { "value": "reset", "resolve_type": "user", "usage": "all" } ],
|
||||
"LOCKED_PORT": [ { "value": "locked", "resolve_type": "user", "usage": "all" } ],
|
||||
"POWER_DOWN_PORT": [ { "value": "power_down", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLK_VALID_PORT": [ { "value": "CLK_VALID", "resolve_type": "user", "usage": "all" } ],
|
||||
"STATUS_PORT": [ { "value": "STATUS", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "user", "usage": "all" } ],
|
||||
"INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "user", "usage": "all" } ],
|
||||
"SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "user", "usage": "all" } ],
|
||||
"SS_MOD_FREQ": [ { "value": "250", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"SS_MOD_TIME": [ { "value": "0.004", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"OVERRIDE_MMCM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
|
||||
"MMCM_DIVCLK_DIVIDE": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ],
|
||||
"MMCM_CLKFBOUT_MULT_F": [ { "value": "24.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_CLKIN1_PERIOD": [ { "value": "20.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKIN2_PERIOD": [ { "value": "10.0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT4_CASCADE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_CLOCK_HOLD": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_COMPENSATION": [ { "value": "ZHOLD", "resolve_type": "user", "usage": "all" } ],
|
||||
"MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_STARTUP_WAIT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_CLKOUT0_DIVIDE_F": [ { "value": "24.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_CLKOUT1_DIVIDE": [ { "value": "12", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_CLKOUT2_DIVIDE": [ { "value": "8", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MMCM_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT2_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_CLKOUT3_DIVIDE": [ { "value": "6", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MMCM_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT3_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MMCM_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT4_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MMCM_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT5_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_CLKOUT6_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MMCM_CLKOUT6_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT6_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"OVERRIDE_PLL": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"PLL_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
|
||||
"PLL_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ],
|
||||
"PLL_CLKFBOUT_MULT": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PLL_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLK_FEEDBACK": [ { "value": "CLKFBOUT", "resolve_type": "user", "usage": "all" } ],
|
||||
"PLL_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PLL_CLKIN_PERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_COMPENSATION": [ { "value": "SYSTEM_SYNCHRONOUS", "resolve_type": "user", "usage": "all" } ],
|
||||
"PLL_REF_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT0_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PLL_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PLL_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PLL_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PLL_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PLL_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PLL_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"RESET_TYPE": [ { "value": "ACTIVE_HIGH", "resolve_type": "user", "usage": "all" } ],
|
||||
"USE_SAFE_CLOCK_STARTUP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_CLOCK_SEQUENCING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT1_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CLKOUT2_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CLKOUT3_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CLKOUT4_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CLKOUT5_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CLKOUT6_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CLKOUT7_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"USE_BOARD_FLOW": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLK_IN1_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLK_IN2_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
|
||||
"DIFF_CLK_IN1_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
|
||||
"DIFF_CLK_IN2_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
|
||||
"AUTO_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "user", "usage": "all" } ],
|
||||
"RESET_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
|
||||
"ENABLE_CDDC": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CDDCDONE_PORT": [ { "value": "cddcdone", "resolve_type": "user", "usage": "all" } ],
|
||||
"CDDCREQ_PORT": [ { "value": "cddcreq", "resolve_type": "user", "usage": "all" } ],
|
||||
"ENABLE_CLKOUTPHY": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUTPHY_REQUESTED_FREQ": [ { "value": "600.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT1_JITTER": [ { "value": "163.696", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT1_PHASE_ERROR": [ { "value": "154.678", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT2_JITTER": [ { "value": "139.128", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT2_PHASE_ERROR": [ { "value": "154.678", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT3_JITTER": [ { "value": "129.923", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT3_PHASE_ERROR": [ { "value": "154.678", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT4_JITTER": [ { "value": "124.134", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT4_PHASE_ERROR": [ { "value": "154.678", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT5_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT5_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT6_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT6_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT7_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT7_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"INPUT_MODE": [ { "value": "frequency", "resolve_type": "user", "usage": "all" } ],
|
||||
"INTERFACE_SELECTION": [ { "value": "Enable_AXI", "resolve_type": "user", "usage": "all" } ],
|
||||
"AXI_DRP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"PHASE_DUTY_CONFIG": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_CLKOUT2_USED": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USER_CLK_FREQ0": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_AUTO_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_USER_CLK_FREQ1": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_USER_CLK_FREQ2": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_USER_CLK_FREQ3": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_ENABLE_CLOCK_MONITOR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ENABLE_USER_CLOCK0": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ENABLE_USER_CLOCK1": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ENABLE_USER_CLOCK2": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ENABLE_USER_CLOCK3": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_Enable_PLL0": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_Enable_PLL1": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_REF_CLK_FREQ": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PRECISION": [ { "value": "1", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT3_USED": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT4_USED": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT5_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT6_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT7_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_CLKOUT1_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_CLKOUT2_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_CLKOUT3_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_CLKOUT4_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"c_component_name": [ { "value": "ad9361_clk_gen_cmos_1t1r", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLATFORM": [ { "value": "UNKNOWN", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_USE_FREQ_SYNTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_PHASE_ALIGNMENT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PRIM_IN_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_SECONDARY_IN_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_JITTER_SEL": [ { "value": "No_Jitter", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_USE_MIN_POWER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_MIN_O_JITTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_MAX_I_JITTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_DYN_PHASE_SHIFT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_OPTIMIZE_CLOCKING_STRUCTURE_EN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_INCLK_SWITCHOVER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_DYN_RECONFIG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_SPREAD_SPECTRUM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_FAST_SIMULATION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PRIMTYPE_SEL": [ { "value": "AUTO", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_USE_CLK_VALID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PRIM_IN_FREQ": [ { "value": "50", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PRIM_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_IN_FREQ_UNITS": [ { "value": "Units_MHz", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_SECONDARY_IN_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_SECONDARY_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_FEEDBACK_SOURCE": [ { "value": "FDBK_AUTO", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PRIM_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PHASESHIFT_MODE": [ { "value": "WAVEFORM", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_SECONDARY_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKFB_IN_SIGNALING": [ { "value": "SINGLE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_USE_RESET": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_RESET_LOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_LOCKED": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_INCLK_STOPPED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_CLKFB_STOPPED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_POWER_DOWN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_STATUS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_FREEZE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_OUT_CLKS": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT1_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT2_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT3_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT4_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT5_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT6_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT7_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_INCLK_SUM_ROW0": [ { "value": "Input Clock Freq (MHz) Input Jitter (UI)", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_INCLK_SUM_ROW1": [ { "value": "__primary______________50____________0.010", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_INCLK_SUM_ROW2": [ { "value": "no_secondary_input_clock ", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW0A": [ { "value": " Output Output Phase Duty Cycle Pk-to-Pk Phase", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW0B": [ { "value": " Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW1": [ { "value": "clk_out1__50.00000______0.000______50.0______163.696____154.678", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW2": [ { "value": "clk_out2__100.00000______0.000______50.0______139.128____154.678", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW3": [ { "value": "clk_out3__150.00000______0.000______50.0______129.923____154.678", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW4": [ { "value": "clk_out4__200.00000______0.000______50.0______124.134____154.678", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW5": [ { "value": "no_CLK_OUT5_output", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW6": [ { "value": "no_CLK_OUT6_output", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW7": [ { "value": "no_CLK_OUT7_output", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "50", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "100", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "150", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "200", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT5_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT6_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT7_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT3_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT4_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT5_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT6_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT7_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT2_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT3_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT4_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT5_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT1_OUT_FREQ": [ { "value": "50.00000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT2_OUT_FREQ": [ { "value": "100.00000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT3_OUT_FREQ": [ { "value": "150.00000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT4_OUT_FREQ": [ { "value": "200.00000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT5_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT6_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT7_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT7_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT1_DUTY_CYCLE": [ { "value": "50.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT2_DUTY_CYCLE": [ { "value": "50.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT3_DUTY_CYCLE": [ { "value": "50.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT4_DUTY_CYCLE": [ { "value": "50.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT5_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT6_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT7_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_USE_SAFE_CLOCK_STARTUP": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_CLOCK_SEQUENCING": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT1_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT2_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT3_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT4_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT5_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT6_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT7_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MMCM_NOTES": [ { "value": "None", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_CLKFBOUT_MULT_F": [ { "value": "24.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKIN1_PERIOD": [ { "value": "20.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKIN2_PERIOD": [ { "value": "10.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT4_CASCADE": [ { "value": "FALSE", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"C_MMCM_CLOCK_HOLD": [ { "value": "FALSE", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"C_MMCM_COMPENSATION": [ { "value": "ZHOLD", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_STARTUP_WAIT": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT0_DIVIDE_F": [ { "value": "24.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT1_DIVIDE": [ { "value": "12", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT2_DIVIDE": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT3_DIVIDE": [ { "value": "6", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT6_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT6_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT2_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT3_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT4_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT5_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT6_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLL_NOTES": [ { "value": "No notes", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLL_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLL_CLK_FEEDBACK": [ { "value": "CLKFBOUT", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLL_CLKFBOUT_MULT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PLL_CLKIN_PERIOD": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_COMPENSATION": [ { "value": "SYSTEM_SYNCHRONOUS", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLL_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PLL_REF_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT0_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLOCK_MGR_TYPE": [ { "value": "NA", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OVERRIDE_MMCM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_OVERRIDE_PLL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PRIMARY_PORT": [ { "value": "clk_in1", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_SECONDARY_PORT": [ { "value": "clk_in2", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLK_OUT1_PORT": [ { "value": "clk_out1", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLK_OUT2_PORT": [ { "value": "clk_out2", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLK_OUT3_PORT": [ { "value": "clk_out3", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLK_OUT4_PORT": [ { "value": "clk_out4", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLK_OUT5_PORT": [ { "value": "clk_out5", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLK_OUT6_PORT": [ { "value": "clk_out6", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLK_OUT7_PORT": [ { "value": "clk_out7", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_RESET_PORT": [ { "value": "reset", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_LOCKED_PORT": [ { "value": "locked", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKFB_IN_PORT": [ { "value": "clkfb_in", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKFB_IN_P_PORT": [ { "value": "clkfb_in_p", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKFB_IN_N_PORT": [ { "value": "clkfb_in_n", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKFB_OUT_PORT": [ { "value": "clkfb_out", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKFB_OUT_P_PORT": [ { "value": "clkfb_out_p", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKFB_OUT_N_PORT": [ { "value": "clkfb_out_n", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_POWER_DOWN_PORT": [ { "value": "power_down", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DADDR_PORT": [ { "value": "daddr", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DCLK_PORT": [ { "value": "dclk", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DRDY_PORT": [ { "value": "drdy", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DWE_PORT": [ { "value": "dwe", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIN_PORT": [ { "value": "din", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DOUT_PORT": [ { "value": "dout", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DEN_PORT": [ { "value": "den", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PSCLK_PORT": [ { "value": "psclk", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PSEN_PORT": [ { "value": "psen", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PSDONE_PORT": [ { "value": "psdone", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLK_VALID_PORT": [ { "value": "CLK_VALID", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_STATUS_PORT": [ { "value": "STATUS", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKIN1_JITTER_PS": [ { "value": "200.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_SS_MOD_PERIOD": [ { "value": "4000", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SS_MOD_TIME": [ { "value": "0.004", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_HAS_CDDC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CDDCDONE_PORT": [ { "value": "cddcdone", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CDDCREQ_PORT": [ { "value": "cddcreq", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUTPHY_MODE": [ { "value": "VCO", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_ENABLE_CLKOUTPHY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INTERFACE_SELECTION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_ADDR_WIDTH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_POWER_REG": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT0_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT0_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT1_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT1_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT2_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT2_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT3_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT3_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT4_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT4_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT5_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT5_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT6_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT6_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKFBOUT_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKFBOUT_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVCLK": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_LOCK_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_LOCK_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_LOCK_3": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_FILTER_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_FILTER_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE1_AUTO": [ { "value": "1", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE2_AUTO": [ { "value": "0.5", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE3_AUTO": [ { "value": "0.3333333333333333", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE4_AUTO": [ { "value": "0.25", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE5_AUTO": [ { "value": "0.041666666666666664", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE6_AUTO": [ { "value": "0.041666666666666664", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE7_AUTO": [ { "value": "0.041666666666666664", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLLBUFGCEDIV": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCMBUFGCEDIV": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLLBUFGCEDIV1": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLLBUFGCEDIV2": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLLBUFGCEDIV3": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLLBUFGCEDIV4": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCMBUFGCEDIV1": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCMBUFGCEDIV2": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCMBUFGCEDIV3": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCMBUFGCEDIV4": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCMBUFGCEDIV5": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCMBUFGCEDIV6": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCMBUFGCEDIV7": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT1_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT2_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT3_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT4_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT0_ACTUAL_FREQ": [ { "value": "50.00000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT1_ACTUAL_FREQ": [ { "value": "100.00000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT2_ACTUAL_FREQ": [ { "value": "150.00000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT3_ACTUAL_FREQ": [ { "value": "200.00000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT4_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT5_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT6_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_M_MAX": [ { "value": "64.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_M_MIN": [ { "value": "2.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_D_MAX": [ { "value": "93.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_D_MIN": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_O_MAX": [ { "value": "128.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_O_MIN": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_VCO_MIN": [ { "value": "600.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_VCO_MAX": [ { "value": "1440.000", "resolve_type": "generated", "format": "float", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z100" } ],
|
||||
"NEXTGEN_VERSAL": [ { "value": "0" } ],
|
||||
"PACKAGE": [ { "value": "ffg900" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Flow" } ],
|
||||
"IPREVISION": [ { "value": "14" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../sjl_basic.gen/sources_1/ip/ad9361_clk_gen_cmos_1t1r" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2024.1.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"clk_in1": [ { "direction": "in" } ],
|
||||
"clk_out1": [ { "direction": "out" } ],
|
||||
"clk_out2": [ { "direction": "out" } ],
|
||||
"clk_out3": [ { "direction": "out" } ],
|
||||
"clk_out4": [ { "direction": "out" } ],
|
||||
"locked": [ { "direction": "out" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"clock_CLK_IN1": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BOARD.ASSOCIATED_PARAM": [ { "value": "CLK_IN1_BOARD_INTERFACE", "usage": "all", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK_IN1": [ { "physical_name": "clk_in1" } ]
|
||||
}
|
||||
},
|
||||
"clock_CLK_OUT1": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK_OUT1": [ { "physical_name": "clk_out1" } ]
|
||||
}
|
||||
},
|
||||
"clock_CLK_OUT2": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK_OUT2": [ { "physical_name": "clk_out2" } ]
|
||||
}
|
||||
},
|
||||
"clock_CLK_OUT3": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK_OUT3": [ { "physical_name": "clk_out3" } ]
|
||||
}
|
||||
},
|
||||
"clock_CLK_OUT4": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK_OUT4": [ { "physical_name": "clk_out4" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+714
@@ -0,0 +1,714 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "ad9361_clk_gen_cmos_2t2r",
|
||||
"component_reference": "xilinx.com:ip:clk_wiz:6.0",
|
||||
"ip_revision": "14",
|
||||
"gen_directory": "../../../../sjl_basic.gen/sources_1/ip/ad9361_clk_gen_cmos_2t2r",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "ad9361_clk_gen_cmos_2t2r", "resolve_type": "user", "usage": "all" } ],
|
||||
"USER_CLK_FREQ0": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"USER_CLK_FREQ1": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"USER_CLK_FREQ2": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"USER_CLK_FREQ3": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"ENABLE_CLOCK_MONITOR": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"OPTIMIZE_CLOCKING_STRUCTURE_EN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ENABLE_USER_CLOCK0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ENABLE_USER_CLOCK1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ENABLE_USER_CLOCK2": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ENABLE_USER_CLOCK3": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Enable_PLL0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Enable_PLL1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"REF_CLK_FREQ": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PRECISION": [ { "value": "1", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PRIMITIVE": [ { "value": "MMCM", "resolve_type": "user", "usage": "all" } ],
|
||||
"PRIMTYPE_SEL": [ { "value": "mmcm_adv", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLOCK_MGR_TYPE": [ { "value": "auto", "resolve_type": "user", "usage": "all" } ],
|
||||
"USE_FREQ_SYNTH": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_SPREAD_SPECTRUM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_PHASE_ALIGNMENT": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_MIN_POWER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_DYN_PHASE_SHIFT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_DYN_RECONFIG": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"JITTER_SEL": [ { "value": "No_Jitter", "resolve_type": "user", "usage": "all" } ],
|
||||
"PRIM_IN_FREQ": [ { "value": "100", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PRIM_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"IN_FREQ_UNITS": [ { "value": "Units_MHz", "resolve_type": "user", "usage": "all" } ],
|
||||
"PHASESHIFT_MODE": [ { "value": "WAVEFORM", "resolve_type": "user", "usage": "all" } ],
|
||||
"IN_JITTER_UNITS": [ { "value": "Units_UI", "resolve_type": "user", "usage": "all" } ],
|
||||
"RELATIVE_INCLK": [ { "value": "REL_PRIMARY", "resolve_type": "user", "usage": "all" } ],
|
||||
"USE_INCLK_SWITCHOVER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"SECONDARY_IN_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"SECONDARY_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"SECONDARY_PORT": [ { "value": "clk_in2", "resolve_type": "user", "usage": "all" } ],
|
||||
"SECONDARY_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "user", "usage": "all" } ],
|
||||
"JITTER_OPTIONS": [ { "value": "UI", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKIN1_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKIN2_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PRIM_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"SECONDARY_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKIN1_JITTER_PS": [ { "value": "100.0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT1_USED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT2_USED": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT3_USED": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT4_USED": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT5_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT6_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT7_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"NUM_OUT_CLKS": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CLK_OUT1_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLK_OUT2_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLK_OUT3_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLK_OUT4_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLK_OUT5_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLK_OUT6_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLK_OUT7_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"PRIMARY_PORT": [ { "value": "clk_in1", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLK_OUT1_PORT": [ { "value": "clk_out1", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLK_OUT2_PORT": [ { "value": "clk_out2", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLK_OUT3_PORT": [ { "value": "clk_out3", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLK_OUT4_PORT": [ { "value": "clk_out4", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLK_OUT5_PORT": [ { "value": "clk_out5", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLK_OUT6_PORT": [ { "value": "clk_out6", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLK_OUT7_PORT": [ { "value": "clk_out7", "resolve_type": "user", "usage": "all" } ],
|
||||
"DADDR_PORT": [ { "value": "daddr", "resolve_type": "user", "usage": "all" } ],
|
||||
"DCLK_PORT": [ { "value": "dclk", "resolve_type": "user", "usage": "all" } ],
|
||||
"DRDY_PORT": [ { "value": "drdy", "resolve_type": "user", "usage": "all" } ],
|
||||
"DWE_PORT": [ { "value": "dwe", "resolve_type": "user", "usage": "all" } ],
|
||||
"DIN_PORT": [ { "value": "din", "resolve_type": "user", "usage": "all" } ],
|
||||
"DOUT_PORT": [ { "value": "dout", "resolve_type": "user", "usage": "all" } ],
|
||||
"DEN_PORT": [ { "value": "den", "resolve_type": "user", "usage": "all" } ],
|
||||
"PSCLK_PORT": [ { "value": "psclk", "resolve_type": "user", "usage": "all" } ],
|
||||
"PSEN_PORT": [ { "value": "psen", "resolve_type": "user", "usage": "all" } ],
|
||||
"PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "user", "usage": "all" } ],
|
||||
"PSDONE_PORT": [ { "value": "psdone", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "50.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT2_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "150.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT3_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT3_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "200.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT4_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT4_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT5_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT5_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT5_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT6_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT6_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT7_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT7_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"USE_MAX_I_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_MIN_O_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT1_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT2_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT3_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT4_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"PRIM_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKOUT1_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKOUT2_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKOUT3_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKOUT4_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKOUT5_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKOUT6_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKOUT7_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
|
||||
"FEEDBACK_SOURCE": [ { "value": "FDBK_AUTO", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKFB_IN_SIGNALING": [ { "value": "SINGLE", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKFB_IN_PORT": [ { "value": "clkfb_in", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKFB_IN_P_PORT": [ { "value": "clkfb_in_p", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKFB_IN_N_PORT": [ { "value": "clkfb_in_n", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKFB_OUT_PORT": [ { "value": "clkfb_out", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKFB_OUT_P_PORT": [ { "value": "clkfb_out_p", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKFB_OUT_N_PORT": [ { "value": "clkfb_out_n", "resolve_type": "user", "usage": "all" } ],
|
||||
"PLATFORM": [ { "value": "UNKNOWN", "resolve_type": "user", "usage": "all" } ],
|
||||
"SUMMARY_STRINGS": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ],
|
||||
"USE_LOCKED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CALC_DONE": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ],
|
||||
"USE_RESET": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_POWER_DOWN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_STATUS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_FREEZE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_CLK_VALID": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_INCLK_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_CLKFB_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"RESET_PORT": [ { "value": "reset", "resolve_type": "user", "usage": "all" } ],
|
||||
"LOCKED_PORT": [ { "value": "locked", "resolve_type": "user", "usage": "all" } ],
|
||||
"POWER_DOWN_PORT": [ { "value": "power_down", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLK_VALID_PORT": [ { "value": "CLK_VALID", "resolve_type": "user", "usage": "all" } ],
|
||||
"STATUS_PORT": [ { "value": "STATUS", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "user", "usage": "all" } ],
|
||||
"INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "user", "usage": "all" } ],
|
||||
"SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "user", "usage": "all" } ],
|
||||
"SS_MOD_FREQ": [ { "value": "250", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"SS_MOD_TIME": [ { "value": "0.004", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"OVERRIDE_MMCM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
|
||||
"MMCM_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ],
|
||||
"MMCM_CLKFBOUT_MULT_F": [ { "value": "12.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_CLKIN1_PERIOD": [ { "value": "10.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKIN2_PERIOD": [ { "value": "10.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT4_CASCADE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_CLOCK_HOLD": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_COMPENSATION": [ { "value": "ZHOLD", "resolve_type": "user", "usage": "all" } ],
|
||||
"MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_STARTUP_WAIT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_CLKOUT0_DIVIDE_F": [ { "value": "24.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_CLKOUT1_DIVIDE": [ { "value": "12", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_CLKOUT2_DIVIDE": [ { "value": "8", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MMCM_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT2_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_CLKOUT3_DIVIDE": [ { "value": "6", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MMCM_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT3_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MMCM_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT4_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MMCM_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT5_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_CLKOUT6_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MMCM_CLKOUT6_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT6_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"OVERRIDE_PLL": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"PLL_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
|
||||
"PLL_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ],
|
||||
"PLL_CLKFBOUT_MULT": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PLL_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLK_FEEDBACK": [ { "value": "CLKFBOUT", "resolve_type": "user", "usage": "all" } ],
|
||||
"PLL_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PLL_CLKIN_PERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_COMPENSATION": [ { "value": "SYSTEM_SYNCHRONOUS", "resolve_type": "user", "usage": "all" } ],
|
||||
"PLL_REF_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT0_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PLL_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PLL_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PLL_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PLL_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PLL_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PLL_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"RESET_TYPE": [ { "value": "ACTIVE_HIGH", "resolve_type": "user", "usage": "all" } ],
|
||||
"USE_SAFE_CLOCK_STARTUP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_CLOCK_SEQUENCING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT1_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CLKOUT2_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CLKOUT3_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CLKOUT4_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CLKOUT5_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CLKOUT6_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CLKOUT7_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"USE_BOARD_FLOW": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLK_IN1_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLK_IN2_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
|
||||
"DIFF_CLK_IN1_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
|
||||
"DIFF_CLK_IN2_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
|
||||
"AUTO_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "user", "usage": "all" } ],
|
||||
"RESET_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
|
||||
"ENABLE_CDDC": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CDDCDONE_PORT": [ { "value": "cddcdone", "resolve_type": "user", "usage": "all" } ],
|
||||
"CDDCREQ_PORT": [ { "value": "cddcreq", "resolve_type": "user", "usage": "all" } ],
|
||||
"ENABLE_CLKOUTPHY": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUTPHY_REQUESTED_FREQ": [ { "value": "600.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT1_JITTER": [ { "value": "132.683", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT1_PHASE_ERROR": [ { "value": "87.180", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT2_JITTER": [ { "value": "115.831", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT2_PHASE_ERROR": [ { "value": "87.180", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT3_JITTER": [ { "value": "107.567", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT3_PHASE_ERROR": [ { "value": "87.180", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT4_JITTER": [ { "value": "102.086", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT4_PHASE_ERROR": [ { "value": "87.180", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT5_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT5_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT6_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT6_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT7_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT7_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"INPUT_MODE": [ { "value": "frequency", "resolve_type": "user", "usage": "all" } ],
|
||||
"INTERFACE_SELECTION": [ { "value": "Enable_AXI", "resolve_type": "user", "usage": "all" } ],
|
||||
"AXI_DRP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"PHASE_DUTY_CONFIG": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_CLKOUT2_USED": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USER_CLK_FREQ0": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_AUTO_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_USER_CLK_FREQ1": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_USER_CLK_FREQ2": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_USER_CLK_FREQ3": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_ENABLE_CLOCK_MONITOR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ENABLE_USER_CLOCK0": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ENABLE_USER_CLOCK1": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ENABLE_USER_CLOCK2": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ENABLE_USER_CLOCK3": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_Enable_PLL0": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_Enable_PLL1": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_REF_CLK_FREQ": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PRECISION": [ { "value": "1", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT3_USED": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT4_USED": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT5_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT6_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT7_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_CLKOUT1_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_CLKOUT2_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_CLKOUT3_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_CLKOUT4_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"c_component_name": [ { "value": "ad9361_clk_gen_cmos_2t2r", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLATFORM": [ { "value": "UNKNOWN", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_USE_FREQ_SYNTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_PHASE_ALIGNMENT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PRIM_IN_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_SECONDARY_IN_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_JITTER_SEL": [ { "value": "No_Jitter", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_USE_MIN_POWER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_MIN_O_JITTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_MAX_I_JITTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_DYN_PHASE_SHIFT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_OPTIMIZE_CLOCKING_STRUCTURE_EN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_INCLK_SWITCHOVER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_DYN_RECONFIG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_SPREAD_SPECTRUM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_FAST_SIMULATION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PRIMTYPE_SEL": [ { "value": "AUTO", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_USE_CLK_VALID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PRIM_IN_FREQ": [ { "value": "100", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PRIM_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_IN_FREQ_UNITS": [ { "value": "Units_MHz", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_SECONDARY_IN_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_SECONDARY_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_FEEDBACK_SOURCE": [ { "value": "FDBK_AUTO", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PRIM_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PHASESHIFT_MODE": [ { "value": "WAVEFORM", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_SECONDARY_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKFB_IN_SIGNALING": [ { "value": "SINGLE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_USE_RESET": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_RESET_LOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_LOCKED": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_INCLK_STOPPED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_CLKFB_STOPPED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_POWER_DOWN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_STATUS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_FREEZE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_OUT_CLKS": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT1_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT2_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT3_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT4_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT5_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT6_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT7_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_INCLK_SUM_ROW0": [ { "value": "Input Clock Freq (MHz) Input Jitter (UI)", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_INCLK_SUM_ROW1": [ { "value": "__primary_____________100____________0.010", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_INCLK_SUM_ROW2": [ { "value": "no_secondary_input_clock ", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW0A": [ { "value": " Output Output Phase Duty Cycle Pk-to-Pk Phase", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW0B": [ { "value": " Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW1": [ { "value": "clk_out1__50.00000______0.000______50.0______132.683_____87.180", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW2": [ { "value": "clk_out2__100.00000______0.000______50.0______115.831_____87.180", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW3": [ { "value": "clk_out3__150.00000______0.000______50.0______107.567_____87.180", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW4": [ { "value": "clk_out4__200.00000______0.000______50.0______102.086_____87.180", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW5": [ { "value": "no_CLK_OUT5_output", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW6": [ { "value": "no_CLK_OUT6_output", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW7": [ { "value": "no_CLK_OUT7_output", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "150.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "200.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT5_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT6_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT7_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT3_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT4_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT5_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT6_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT7_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT2_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT3_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT4_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT5_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT1_OUT_FREQ": [ { "value": "50.00000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT2_OUT_FREQ": [ { "value": "100.00000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT3_OUT_FREQ": [ { "value": "150.00000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT4_OUT_FREQ": [ { "value": "200.00000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT5_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT6_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT7_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT7_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT1_DUTY_CYCLE": [ { "value": "50.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT2_DUTY_CYCLE": [ { "value": "50.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT3_DUTY_CYCLE": [ { "value": "50.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT4_DUTY_CYCLE": [ { "value": "50.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT5_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT6_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT7_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_USE_SAFE_CLOCK_STARTUP": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_CLOCK_SEQUENCING": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT1_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT2_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT3_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT4_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT5_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT6_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT7_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MMCM_NOTES": [ { "value": "None", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_CLKFBOUT_MULT_F": [ { "value": "12.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKIN1_PERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKIN2_PERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT4_CASCADE": [ { "value": "FALSE", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"C_MMCM_CLOCK_HOLD": [ { "value": "FALSE", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"C_MMCM_COMPENSATION": [ { "value": "ZHOLD", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_STARTUP_WAIT": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT0_DIVIDE_F": [ { "value": "24.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT1_DIVIDE": [ { "value": "12", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT2_DIVIDE": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT3_DIVIDE": [ { "value": "6", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT6_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT6_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT2_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT3_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT4_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT5_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT6_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLL_NOTES": [ { "value": "No notes", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLL_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLL_CLK_FEEDBACK": [ { "value": "CLKFBOUT", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLL_CLKFBOUT_MULT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PLL_CLKIN_PERIOD": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_COMPENSATION": [ { "value": "SYSTEM_SYNCHRONOUS", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLL_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PLL_REF_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT0_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLOCK_MGR_TYPE": [ { "value": "NA", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OVERRIDE_MMCM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_OVERRIDE_PLL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PRIMARY_PORT": [ { "value": "clk_in1", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_SECONDARY_PORT": [ { "value": "clk_in2", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLK_OUT1_PORT": [ { "value": "clk_out1", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLK_OUT2_PORT": [ { "value": "clk_out2", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLK_OUT3_PORT": [ { "value": "clk_out3", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLK_OUT4_PORT": [ { "value": "clk_out4", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLK_OUT5_PORT": [ { "value": "clk_out5", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLK_OUT6_PORT": [ { "value": "clk_out6", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLK_OUT7_PORT": [ { "value": "clk_out7", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_RESET_PORT": [ { "value": "reset", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_LOCKED_PORT": [ { "value": "locked", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKFB_IN_PORT": [ { "value": "clkfb_in", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKFB_IN_P_PORT": [ { "value": "clkfb_in_p", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKFB_IN_N_PORT": [ { "value": "clkfb_in_n", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKFB_OUT_PORT": [ { "value": "clkfb_out", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKFB_OUT_P_PORT": [ { "value": "clkfb_out_p", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKFB_OUT_N_PORT": [ { "value": "clkfb_out_n", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_POWER_DOWN_PORT": [ { "value": "power_down", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DADDR_PORT": [ { "value": "daddr", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DCLK_PORT": [ { "value": "dclk", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DRDY_PORT": [ { "value": "drdy", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DWE_PORT": [ { "value": "dwe", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIN_PORT": [ { "value": "din", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DOUT_PORT": [ { "value": "dout", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DEN_PORT": [ { "value": "den", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PSCLK_PORT": [ { "value": "psclk", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PSEN_PORT": [ { "value": "psen", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PSDONE_PORT": [ { "value": "psdone", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLK_VALID_PORT": [ { "value": "CLK_VALID", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_STATUS_PORT": [ { "value": "STATUS", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKIN1_JITTER_PS": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_SS_MOD_PERIOD": [ { "value": "4000", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SS_MOD_TIME": [ { "value": "0.004", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_HAS_CDDC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CDDCDONE_PORT": [ { "value": "cddcdone", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CDDCREQ_PORT": [ { "value": "cddcreq", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUTPHY_MODE": [ { "value": "VCO", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_ENABLE_CLKOUTPHY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INTERFACE_SELECTION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_ADDR_WIDTH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_POWER_REG": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT0_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT0_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT1_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT1_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT2_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT2_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT3_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT3_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT4_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT4_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT5_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT5_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT6_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT6_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKFBOUT_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKFBOUT_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVCLK": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_LOCK_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_LOCK_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_LOCK_3": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_FILTER_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_FILTER_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE1_AUTO": [ { "value": "1", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE2_AUTO": [ { "value": "0.5", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE3_AUTO": [ { "value": "0.3333333333333333", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE4_AUTO": [ { "value": "0.25", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE5_AUTO": [ { "value": "0.041666666666666664", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE6_AUTO": [ { "value": "0.041666666666666664", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE7_AUTO": [ { "value": "0.041666666666666664", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLLBUFGCEDIV": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCMBUFGCEDIV": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLLBUFGCEDIV1": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLLBUFGCEDIV2": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLLBUFGCEDIV3": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLLBUFGCEDIV4": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCMBUFGCEDIV1": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCMBUFGCEDIV2": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCMBUFGCEDIV3": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCMBUFGCEDIV4": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCMBUFGCEDIV5": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCMBUFGCEDIV6": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCMBUFGCEDIV7": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT1_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT2_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT3_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT4_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT0_ACTUAL_FREQ": [ { "value": "50.00000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT1_ACTUAL_FREQ": [ { "value": "100.00000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT2_ACTUAL_FREQ": [ { "value": "150.00000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT3_ACTUAL_FREQ": [ { "value": "200.00000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT4_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT5_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT6_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_M_MAX": [ { "value": "64.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_M_MIN": [ { "value": "2.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_D_MAX": [ { "value": "93.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_D_MIN": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_O_MAX": [ { "value": "128.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_O_MIN": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_VCO_MIN": [ { "value": "600.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_VCO_MAX": [ { "value": "1440.000", "resolve_type": "generated", "format": "float", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z100" } ],
|
||||
"NEXTGEN_VERSAL": [ { "value": "0" } ],
|
||||
"PACKAGE": [ { "value": "ffg900" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Flow" } ],
|
||||
"IPREVISION": [ { "value": "14" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../sjl_basic.gen/sources_1/ip/ad9361_clk_gen_cmos_2t2r" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2024.1.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"clk_in1": [ { "direction": "in" } ],
|
||||
"clk_out1": [ { "direction": "out" } ],
|
||||
"clk_out2": [ { "direction": "out" } ],
|
||||
"clk_out3": [ { "direction": "out" } ],
|
||||
"clk_out4": [ { "direction": "out" } ],
|
||||
"locked": [ { "direction": "out" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"clock_CLK_IN1": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BOARD.ASSOCIATED_PARAM": [ { "value": "CLK_IN1_BOARD_INTERFACE", "usage": "all", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK_IN1": [ { "physical_name": "clk_in1" } ]
|
||||
}
|
||||
},
|
||||
"clock_CLK_OUT1": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK_OUT1": [ { "physical_name": "clk_out1" } ]
|
||||
}
|
||||
},
|
||||
"clock_CLK_OUT2": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK_OUT2": [ { "physical_name": "clk_out2" } ]
|
||||
}
|
||||
},
|
||||
"clock_CLK_OUT3": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK_OUT3": [ { "physical_name": "clk_out3" } ]
|
||||
}
|
||||
},
|
||||
"clock_CLK_OUT4": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK_OUT4": [ { "physical_name": "clk_out4" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,480 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "ad9361_fifo",
|
||||
"component_reference": "xilinx.com:ip:fifo_generator:13.2",
|
||||
"ip_revision": "10",
|
||||
"gen_directory": "../../../../sjl_basic.gen/sources_1/ip/ad9361_fifo",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "ad9361_fifo", "resolve_type": "user", "usage": "all" } ],
|
||||
"Fifo_Implementation": [ { "value": "Independent_Clocks_Distributed_RAM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"synchronization_stages": [ { "value": "3", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"synchronization_stages_axi": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"INTERFACE_TYPE": [ { "value": "Native", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Performance_Options": [ { "value": "Standard_FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"asymmetric_port_width": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Data_Width": [ { "value": "12", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Input_Depth": [ { "value": "16", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Output_Data_Width": [ { "value": "12", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Output_Depth": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Use_Embedded_Registers": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Reset_Pin": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Enable_Reset_Synchronization": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Reset_Type": [ { "value": "Asynchronous_Reset", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Flags_Reset_Value": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Use_Dout_Reset": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Dout_Reset_Value": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"dynamic_power_saving": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Almost_Full_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Almost_Empty_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Valid_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Valid_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Underflow_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Underflow_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Write_Acknowledge_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Write_Acknowledge_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Overflow_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Overflow_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"ecc_pipeline_reg": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Use_Extra_Logic": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Data_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Data_Count_Width": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Write_Data_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Write_Data_Count_Width": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Read_Data_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Read_Data_Count_Width": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Disable_Timing_Violations": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Read_Clock_Frequency": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Write_Clock_Frequency": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value": [ { "value": "13", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Negate_Value": [ { "value": "12", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value": [ { "value": "2", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Negate_Value": [ { "value": "3", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PROTOCOL": [ { "value": "AXI4", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Clock_Type_AXI": [ { "value": "Common_Clock", "resolve_type": "user", "usage": "all" } ],
|
||||
"HAS_ACLKEN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Clock_Enable_Type": [ { "value": "Slave_Interface_Clock_Enable", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "resolve_type": "user", "usage": "all" } ],
|
||||
"ID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"ADDRESS_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"DATA_WIDTH": [ { "value": "64", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"AWUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"WUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"BUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"ARUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"RUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"TDATA_NUM_BYTES": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"TUSER_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Enable_TREADY": [ { "value": "true", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Enable_TLAST": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"HAS_TSTRB": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"TSTRB_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_TKEEP": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"TKEEP_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"wach_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_wach": [ { "value": "Common_Clock_Distributed_RAM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_wach": [ { "value": "Data_FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_ECC_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_wach": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_wach": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_wach": [ { "value": "1023", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_wach": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_wach": [ { "value": "1022", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"wdch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_wdch": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_wdch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_wdch": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_wdch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_wdch": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_wdch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_wdch": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"wrch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_wrch": [ { "value": "Common_Clock_Distributed_RAM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_wrch": [ { "value": "Data_FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_ECC_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_wrch": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_wrch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_wrch": [ { "value": "1023", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_wrch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_wrch": [ { "value": "1022", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"rach_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_rach": [ { "value": "Common_Clock_Distributed_RAM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_rach": [ { "value": "Data_FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_ECC_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_rach": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_rach": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_rach": [ { "value": "1023", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_rach": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_rach": [ { "value": "1022", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"rdch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_rdch": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_rdch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_rdch": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_rdch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_rdch": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_rdch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_rdch": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"axis_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_axis": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_axis": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_axis": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_axis": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_axis": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_axis": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_axis": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Register_Slice_Mode_wach": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Register_Slice_Mode_wdch": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Register_Slice_Mode_wrch": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Register_Slice_Mode_rach": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Register_Slice_Mode_rdch": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Register_Slice_Mode_axis": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Underflow_Flag_AXI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Underflow_Sense_AXI": [ { "value": "Active_High", "resolve_type": "user", "usage": "all" } ],
|
||||
"Overflow_Flag_AXI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Overflow_Sense_AXI": [ { "value": "Active_High", "resolve_type": "user", "usage": "all" } ],
|
||||
"Disable_Timing_Violations_AXI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Add_NGC_Constraint_AXI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Enable_Common_Underflow": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Enable_Common_Overflow": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"enable_read_pointer_increment_by2": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Use_Embedded_Registers_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"enable_low_latency": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"use_dout_register": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Master_interface_Clock_enable_memory_mapped": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Slave_interface_Clock_enable_memory_mapped": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Output_Register_Type": [ { "value": "Embedded_Reg", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_Safety_Circuit": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_Type": [ { "value": "Hard_ECC", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"C_SELECT_XPM": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_COMMON_CLOCK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SELECT_XPM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_COUNT_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DATA_COUNT_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DEFAULT_VALUE": [ { "value": "BlankString", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIN_WIDTH": [ { "value": "12", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DOUT_RST_VAL": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DOUT_WIDTH": [ { "value": "12", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ENABLE_RLOCS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_FAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_FULL_FLAGS_RST_VAL": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_ALMOST_EMPTY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_ALMOST_FULL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_BACKUP": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_DATA_COUNT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_INT_CLK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_MEMINIT_FILE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_OVERFLOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_RD_DATA_COUNT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_RD_RST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_RST": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_SRST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_UNDERFLOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_VALID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_WR_ACK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_WR_DATA_COUNT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_WR_RST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_IMPLEMENTATION_TYPE": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INIT_WR_PNTR_VAL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MEMORY_TYPE": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MIF_FILE_NAME": [ { "value": "BlankString", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OPTIMIZATION_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_OVERFLOW_LOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PRELOAD_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PRELOAD_REGS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PRIM_FIFO_TYPE": [ { "value": "512x36", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PROG_EMPTY_THRESH_ASSERT_VAL": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_EMPTY_THRESH_NEGATE_VAL": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_EMPTY_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_FULL_THRESH_ASSERT_VAL": [ { "value": "13", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_FULL_THRESH_NEGATE_VAL": [ { "value": "12", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_FULL_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_RD_DATA_COUNT_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_RD_DEPTH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_RD_FREQ": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_RD_PNTR_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_UNDERFLOW_LOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_DOUT_RST": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_ECC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_EMBEDDED_REG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_PIPELINE_REG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_POWER_SAVING_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_FIFO16_FLAGS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_FWFT_DATA_COUNT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_VALID_LOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WR_ACK_LOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WR_DATA_COUNT_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WR_DEPTH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WR_FREQ": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WR_PNTR_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WR_RESPONSE_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MSGON_VAL": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ENABLE_RST_SYNC": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_EN_SAFETY_CKT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ERROR_INJECTION_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SYNCHRONIZER_STAGE": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INTERFACE_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_AXI_WR_CHANNEL": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_AXI_RD_CHANNEL": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_SLAVE_CE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_MASTER_CE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ADD_NGC_CONSTRAINT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_COMMON_OVERFLOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_COMMON_UNDERFLOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_DEFAULT_SETTINGS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_ID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_DATA_WIDTH": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_LEN_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_LOCK_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_AXI_ID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_AXI_AWUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_AXI_WUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_AXI_BUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_AXI_ARUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_AXI_RUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_ARUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_AWUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_WUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_BUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_RUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_AXIS_TDATA": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_AXIS_TID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_AXIS_TDEST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_AXIS_TUSER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_AXIS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_AXIS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_AXIS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_AXIS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TDATA_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TDEST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TUSER_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TSTRB_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TKEEP_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WACH_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WDCH_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WRCH_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_RACH_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_RDCH_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_IMPLEMENTATION_TYPE_WACH": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_IMPLEMENTATION_TYPE_WDCH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_IMPLEMENTATION_TYPE_WRCH": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_IMPLEMENTATION_TYPE_RACH": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_IMPLEMENTATION_TYPE_RDCH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_IMPLEMENTATION_TYPE_AXIS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_APPLICATION_TYPE_WACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_APPLICATION_TYPE_WDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_APPLICATION_TYPE_WRCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_APPLICATION_TYPE_RACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_APPLICATION_TYPE_RDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_APPLICATION_TYPE_AXIS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PRIM_FIFO_TYPE_WACH": [ { "value": "512x36", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PRIM_FIFO_TYPE_WDCH": [ { "value": "1kx36", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PRIM_FIFO_TYPE_WRCH": [ { "value": "512x36", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PRIM_FIFO_TYPE_RACH": [ { "value": "512x36", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PRIM_FIFO_TYPE_RDCH": [ { "value": "1kx36", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PRIM_FIFO_TYPE_AXIS": [ { "value": "1kx18", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_USE_ECC_WACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_ECC_WDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_ECC_WRCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_ECC_RACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_ECC_RDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_ECC_AXIS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ERROR_INJECTION_TYPE_WACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ERROR_INJECTION_TYPE_WDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ERROR_INJECTION_TYPE_WRCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ERROR_INJECTION_TYPE_RACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ERROR_INJECTION_TYPE_RDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ERROR_INJECTION_TYPE_AXIS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DIN_WIDTH_WACH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DIN_WIDTH_WDCH": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DIN_WIDTH_WRCH": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DIN_WIDTH_RACH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DIN_WIDTH_RDCH": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DIN_WIDTH_AXIS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WR_DEPTH_WACH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WR_DEPTH_WDCH": [ { "value": "1024", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WR_DEPTH_WRCH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WR_DEPTH_RACH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WR_DEPTH_RDCH": [ { "value": "1024", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WR_DEPTH_AXIS": [ { "value": "1024", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WR_PNTR_WIDTH_WACH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WR_PNTR_WIDTH_WDCH": [ { "value": "10", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WR_PNTR_WIDTH_WRCH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WR_PNTR_WIDTH_RACH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WR_PNTR_WIDTH_RDCH": [ { "value": "10", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WR_PNTR_WIDTH_AXIS": [ { "value": "10", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_DATA_COUNTS_WACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_DATA_COUNTS_WDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_DATA_COUNTS_WRCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_DATA_COUNTS_RACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_DATA_COUNTS_RDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_DATA_COUNTS_AXIS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_PROG_FLAGS_WACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_PROG_FLAGS_WDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_PROG_FLAGS_WRCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_PROG_FLAGS_RACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_PROG_FLAGS_RDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_PROG_FLAGS_AXIS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_FULL_TYPE_WACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_FULL_TYPE_WDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_FULL_TYPE_WRCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_FULL_TYPE_RACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_FULL_TYPE_RDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_FULL_TYPE_AXIS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_FULL_THRESH_ASSERT_VAL_WACH": [ { "value": "1023", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_FULL_THRESH_ASSERT_VAL_WDCH": [ { "value": "1023", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_FULL_THRESH_ASSERT_VAL_WRCH": [ { "value": "1023", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_FULL_THRESH_ASSERT_VAL_RACH": [ { "value": "1023", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_FULL_THRESH_ASSERT_VAL_RDCH": [ { "value": "1023", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_FULL_THRESH_ASSERT_VAL_AXIS": [ { "value": "1023", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_EMPTY_TYPE_WACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_EMPTY_TYPE_WDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_EMPTY_TYPE_WRCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_EMPTY_TYPE_RACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_EMPTY_TYPE_RDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_EMPTY_TYPE_AXIS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH": [ { "value": "1022", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH": [ { "value": "1022", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH": [ { "value": "1022", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH": [ { "value": "1022", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH": [ { "value": "1022", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS": [ { "value": "1022", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_REG_SLICE_MODE_WACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_REG_SLICE_MODE_WDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_REG_SLICE_MODE_WRCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_REG_SLICE_MODE_RACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_REG_SLICE_MODE_RDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_REG_SLICE_MODE_AXIS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z100" } ],
|
||||
"NEXTGEN_VERSAL": [ { "value": "0" } ],
|
||||
"PACKAGE": [ { "value": "ffg900" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Flow" } ],
|
||||
"IPREVISION": [ { "value": "10" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../sjl_basic.gen/sources_1/ip/ad9361_fifo" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2024.1.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"rst": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"wr_clk": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"rd_clk": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"din": [ { "direction": "in", "size_left": "11", "size_right": "0", "driver_value": "0" } ],
|
||||
"wr_en": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"rd_en": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"dout": [ { "direction": "out", "size_left": "11", "size_right": "0", "driver_value": "0" } ],
|
||||
"full": [ { "direction": "out", "driver_value": "0x0" } ],
|
||||
"empty": [ { "direction": "out", "driver_value": "0x1" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"write_clk": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "wr_clk" } ]
|
||||
}
|
||||
},
|
||||
"read_clk": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "rd_clk" } ]
|
||||
}
|
||||
},
|
||||
"FIFO_WRITE": {
|
||||
"vlnv": "xilinx.com:interface:fifo_write:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:fifo_write_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"port_maps": {
|
||||
"FULL": [ { "physical_name": "full" } ],
|
||||
"WR_DATA": [ { "physical_name": "din" } ],
|
||||
"WR_EN": [ { "physical_name": "wr_en" } ]
|
||||
}
|
||||
},
|
||||
"FIFO_READ": {
|
||||
"vlnv": "xilinx.com:interface:fifo_read:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:fifo_read_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"port_maps": {
|
||||
"EMPTY": [ { "physical_name": "empty" } ],
|
||||
"RD_DATA": [ { "physical_name": "dout" } ],
|
||||
"RD_EN": [ { "physical_name": "rd_en" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,213 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "cmpy_18x8",
|
||||
"component_reference": "xilinx.com:ip:cmpy:6.0",
|
||||
"ip_revision": "24",
|
||||
"gen_directory": "../../../../sjl_basic.gen/sources_1/ip/cmpy_18x8",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "cmpy_18x8", "resolve_type": "user", "usage": "all" } ],
|
||||
"APortWidth": [ { "value": "18", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HasATLAST": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"HasATUSER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ATUSERWidth": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"BPortWidth": [ { "value": "8", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HasBTLAST": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"HasBTUSER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"BTUSERWidth": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MultType": [ { "value": "Use_LUTs", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"OptimizeGoal": [ { "value": "Resources", "resolve_type": "user", "usage": "all" } ],
|
||||
"FlowControl": [ { "value": "NonBlocking", "resolve_type": "user", "usage": "all" } ],
|
||||
"RoundMode": [ { "value": "Truncate", "resolve_type": "user", "usage": "all" } ],
|
||||
"OutputWidth": [ { "value": "27", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HasCTRLTLAST": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"HasCTRLTUSER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CTRLTUSERWidth": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"OutTLASTBehv": [ { "value": "Null", "resolve_type": "user", "usage": "all" } ],
|
||||
"LatencyConfig": [ { "value": "Automatic", "resolve_type": "user", "usage": "all" } ],
|
||||
"MinimumLatency": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ACLKEN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ARESETN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_VERBOSITY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_XDEVICEFAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_XDEVICE": [ { "value": "xc7z100", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_A_WIDTH": [ { "value": "18", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_B_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_OUT_WIDTH": [ { "value": "27", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_LATENCY": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MULT_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_OPTIMIZE_GOAL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"HAS_NEGATE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"SINGLE_OUTPUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"ROUND": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"USE_DSP_CASCADES": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_THROTTLE_SCHEME": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_ACLKEN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_ARESETN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_S_AXIS_A_TUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_S_AXIS_A_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_S_AXIS_B_TUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_S_AXIS_B_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_S_AXIS_CTRL_TUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_S_AXIS_CTRL_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_TLAST_RESOLUTION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXIS_A_TDATA_WIDTH": [ { "value": "48", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXIS_A_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXIS_B_TDATA_WIDTH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXIS_B_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXIS_CTRL_TDATA_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXIS_CTRL_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_AXIS_DOUT_TDATA_WIDTH": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_AXIS_DOUT_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z100" } ],
|
||||
"NEXTGEN_VERSAL": [ { "value": "0" } ],
|
||||
"PACKAGE": [ { "value": "ffg900" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Flow" } ],
|
||||
"IPREVISION": [ { "value": "24" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../sjl_basic.gen/sources_1/ip/cmpy_18x8" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2024.1.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"aclk": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_a_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_a_tdata": [ { "direction": "in", "size_left": "47", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axis_b_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_b_tdata": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
|
||||
"m_axis_dout_tvalid": [ { "direction": "out", "driver_value": "0x0" } ],
|
||||
"m_axis_dout_tdata": [ { "direction": "out", "size_left": "63", "size_right": "0", "driver_value": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"M_AXIS_DOUT": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "8", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "m_axis_dout_tdata" } ],
|
||||
"TVALID": [ { "physical_name": "m_axis_dout_tvalid" } ]
|
||||
}
|
||||
},
|
||||
"aclk_intf": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S_AXIS_CTRL:S_AXIS_B:S_AXIS_A:M_AXIS_DOUT", "value_src": "constant", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "usage": "all" } ],
|
||||
"ASSOCIATED_CLKEN": [ { "value": "aclken", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "10000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "aclk" } ]
|
||||
}
|
||||
},
|
||||
"aresetn_intf": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"aclken_intf": {
|
||||
"vlnv": "xilinx.com:signal:clockenable:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ]
|
||||
}
|
||||
},
|
||||
"S_AXIS_A": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "6", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "s_axis_a_tdata" } ],
|
||||
"TVALID": [ { "physical_name": "s_axis_a_tvalid" } ]
|
||||
}
|
||||
},
|
||||
"S_AXIS_B": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "2", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "s_axis_b_tdata" } ],
|
||||
"TVALID": [ { "physical_name": "s_axis_b_tvalid" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,771 @@
|
||||
RADIX = 10;
|
||||
COEFDATA =
|
||||
-47,
|
||||
-30,
|
||||
-13,
|
||||
4,
|
||||
21,
|
||||
38,
|
||||
56,
|
||||
73,
|
||||
89,
|
||||
106,
|
||||
122,
|
||||
138,
|
||||
153,
|
||||
168,
|
||||
182,
|
||||
196,
|
||||
209,
|
||||
221,
|
||||
232,
|
||||
243,
|
||||
252,
|
||||
261,
|
||||
268,
|
||||
275,
|
||||
281,
|
||||
285,
|
||||
289,
|
||||
291,
|
||||
292,
|
||||
292,
|
||||
291,
|
||||
288,
|
||||
285,
|
||||
280,
|
||||
274,
|
||||
267,
|
||||
259,
|
||||
249,
|
||||
239,
|
||||
228,
|
||||
215,
|
||||
202,
|
||||
187,
|
||||
172,
|
||||
156,
|
||||
139,
|
||||
122,
|
||||
104,
|
||||
85,
|
||||
66,
|
||||
46,
|
||||
26,
|
||||
5,
|
||||
-15,
|
||||
-36,
|
||||
-56,
|
||||
-77,
|
||||
-98,
|
||||
-118,
|
||||
-138,
|
||||
-158,
|
||||
-177,
|
||||
-195,
|
||||
-213,
|
||||
-231,
|
||||
-247,
|
||||
-263,
|
||||
-277,
|
||||
-291,
|
||||
-303,
|
||||
-314,
|
||||
-325,
|
||||
-333,
|
||||
-341,
|
||||
-347,
|
||||
-351,
|
||||
-354,
|
||||
-356,
|
||||
-356,
|
||||
-354,
|
||||
-351,
|
||||
-346,
|
||||
-340,
|
||||
-332,
|
||||
-322,
|
||||
-311,
|
||||
-298,
|
||||
-284,
|
||||
-268,
|
||||
-250,
|
||||
-231,
|
||||
-211,
|
||||
-189,
|
||||
-166,
|
||||
-142,
|
||||
-117,
|
||||
-90,
|
||||
-63,
|
||||
-35,
|
||||
-6,
|
||||
24,
|
||||
54,
|
||||
85,
|
||||
116,
|
||||
147,
|
||||
179,
|
||||
210,
|
||||
242,
|
||||
273,
|
||||
304,
|
||||
334,
|
||||
363,
|
||||
392,
|
||||
420,
|
||||
447,
|
||||
473,
|
||||
497,
|
||||
520,
|
||||
542,
|
||||
562,
|
||||
580,
|
||||
596,
|
||||
611,
|
||||
623,
|
||||
633,
|
||||
641,
|
||||
647,
|
||||
650,
|
||||
650,
|
||||
649,
|
||||
644,
|
||||
637,
|
||||
627,
|
||||
615,
|
||||
600,
|
||||
582,
|
||||
562,
|
||||
538,
|
||||
513,
|
||||
484,
|
||||
453,
|
||||
419,
|
||||
383,
|
||||
345,
|
||||
304,
|
||||
261,
|
||||
216,
|
||||
169,
|
||||
119,
|
||||
69,
|
||||
16,
|
||||
-38,
|
||||
-93,
|
||||
-150,
|
||||
-207,
|
||||
-265,
|
||||
-324,
|
||||
-383,
|
||||
-443,
|
||||
-502,
|
||||
-562,
|
||||
-621,
|
||||
-679,
|
||||
-736,
|
||||
-793,
|
||||
-848,
|
||||
-902,
|
||||
-954,
|
||||
-1004,
|
||||
-1052,
|
||||
-1097,
|
||||
-1140,
|
||||
-1181,
|
||||
-1218,
|
||||
-1252,
|
||||
-1283,
|
||||
-1310,
|
||||
-1333,
|
||||
-1353,
|
||||
-1369,
|
||||
-1380,
|
||||
-1387,
|
||||
-1389,
|
||||
-1387,
|
||||
-1381,
|
||||
-1369,
|
||||
-1353,
|
||||
-1332,
|
||||
-1306,
|
||||
-1274,
|
||||
-1238,
|
||||
-1197,
|
||||
-1151,
|
||||
-1100,
|
||||
-1044,
|
||||
-983,
|
||||
-918,
|
||||
-848,
|
||||
-773,
|
||||
-694,
|
||||
-611,
|
||||
-524,
|
||||
-432,
|
||||
-337,
|
||||
-239,
|
||||
-137,
|
||||
-33,
|
||||
74,
|
||||
184,
|
||||
296,
|
||||
410,
|
||||
525,
|
||||
642,
|
||||
759,
|
||||
877,
|
||||
995,
|
||||
1113,
|
||||
1230,
|
||||
1346,
|
||||
1461,
|
||||
1575,
|
||||
1686,
|
||||
1794,
|
||||
1900,
|
||||
2002,
|
||||
2101,
|
||||
2195,
|
||||
2285,
|
||||
2371,
|
||||
2451,
|
||||
2525,
|
||||
2593,
|
||||
2655,
|
||||
2711,
|
||||
2759,
|
||||
2800,
|
||||
2833,
|
||||
2859,
|
||||
2876,
|
||||
2885,
|
||||
2886,
|
||||
2877,
|
||||
2860,
|
||||
2833,
|
||||
2798,
|
||||
2752,
|
||||
2698,
|
||||
2633,
|
||||
2559,
|
||||
2476,
|
||||
2382,
|
||||
2280,
|
||||
2168,
|
||||
2046,
|
||||
1915,
|
||||
1775,
|
||||
1627,
|
||||
1469,
|
||||
1304,
|
||||
1130,
|
||||
948,
|
||||
759,
|
||||
563,
|
||||
360,
|
||||
151,
|
||||
-64,
|
||||
-284,
|
||||
-509,
|
||||
-739,
|
||||
-972,
|
||||
-1208,
|
||||
-1447,
|
||||
-1687,
|
||||
-1929,
|
||||
-2172,
|
||||
-2414,
|
||||
-2656,
|
||||
-2896,
|
||||
-3133,
|
||||
-3368,
|
||||
-3600,
|
||||
-3826,
|
||||
-4048,
|
||||
-4263,
|
||||
-4472,
|
||||
-4673,
|
||||
-4866,
|
||||
-5050,
|
||||
-5224,
|
||||
-5387,
|
||||
-5539,
|
||||
-5679,
|
||||
-5807,
|
||||
-5920,
|
||||
-6020,
|
||||
-6104,
|
||||
-6173,
|
||||
-6226,
|
||||
-6262,
|
||||
-6281,
|
||||
-6282,
|
||||
-6264,
|
||||
-6228,
|
||||
-6171,
|
||||
-6096,
|
||||
-5999,
|
||||
-5882,
|
||||
-5745,
|
||||
-5585,
|
||||
-5405,
|
||||
-5203,
|
||||
-4978,
|
||||
-4732,
|
||||
-4464,
|
||||
-4174,
|
||||
-3861,
|
||||
-3527,
|
||||
-3170,
|
||||
-2792,
|
||||
-2392,
|
||||
-1971,
|
||||
-1529,
|
||||
-1066,
|
||||
-582,
|
||||
-79,
|
||||
444,
|
||||
985,
|
||||
1545,
|
||||
2123,
|
||||
2717,
|
||||
3328,
|
||||
3955,
|
||||
4597,
|
||||
5253,
|
||||
5921,
|
||||
6603,
|
||||
7295,
|
||||
7998,
|
||||
8711,
|
||||
9432,
|
||||
10160,
|
||||
10895,
|
||||
11635,
|
||||
12379,
|
||||
13126,
|
||||
13875,
|
||||
14624,
|
||||
15374,
|
||||
16121,
|
||||
16866,
|
||||
17607,
|
||||
18342,
|
||||
19071,
|
||||
19793,
|
||||
20505,
|
||||
21208,
|
||||
21900,
|
||||
22579,
|
||||
23245,
|
||||
23896,
|
||||
24532,
|
||||
25151,
|
||||
25752,
|
||||
26334,
|
||||
26896,
|
||||
27438,
|
||||
27957,
|
||||
28455,
|
||||
28928,
|
||||
29377,
|
||||
29801,
|
||||
30200,
|
||||
30571,
|
||||
30915,
|
||||
31232,
|
||||
31520,
|
||||
31779,
|
||||
32009,
|
||||
32209,
|
||||
32379,
|
||||
32518,
|
||||
32627,
|
||||
32704,
|
||||
32751,
|
||||
32767,
|
||||
32751,
|
||||
32704,
|
||||
32627,
|
||||
32518,
|
||||
32379,
|
||||
32209,
|
||||
32009,
|
||||
31779,
|
||||
31520,
|
||||
31232,
|
||||
30915,
|
||||
30571,
|
||||
30200,
|
||||
29801,
|
||||
29377,
|
||||
28928,
|
||||
28455,
|
||||
27957,
|
||||
27438,
|
||||
26896,
|
||||
26334,
|
||||
25752,
|
||||
25151,
|
||||
24532,
|
||||
23896,
|
||||
23245,
|
||||
22579,
|
||||
21900,
|
||||
21208,
|
||||
20505,
|
||||
19793,
|
||||
19071,
|
||||
18342,
|
||||
17607,
|
||||
16866,
|
||||
16121,
|
||||
15374,
|
||||
14624,
|
||||
13875,
|
||||
13126,
|
||||
12379,
|
||||
11635,
|
||||
10895,
|
||||
10160,
|
||||
9432,
|
||||
8711,
|
||||
7998,
|
||||
7295,
|
||||
6603,
|
||||
5921,
|
||||
5253,
|
||||
4597,
|
||||
3955,
|
||||
3328,
|
||||
2717,
|
||||
2123,
|
||||
1545,
|
||||
985,
|
||||
444,
|
||||
-79,
|
||||
-582,
|
||||
-1066,
|
||||
-1529,
|
||||
-1971,
|
||||
-2392,
|
||||
-2792,
|
||||
-3170,
|
||||
-3527,
|
||||
-3861,
|
||||
-4174,
|
||||
-4464,
|
||||
-4732,
|
||||
-4978,
|
||||
-5203,
|
||||
-5405,
|
||||
-5585,
|
||||
-5745,
|
||||
-5882,
|
||||
-5999,
|
||||
-6096,
|
||||
-6171,
|
||||
-6228,
|
||||
-6264,
|
||||
-6282,
|
||||
-6281,
|
||||
-6262,
|
||||
-6226,
|
||||
-6173,
|
||||
-6104,
|
||||
-6020,
|
||||
-5920,
|
||||
-5807,
|
||||
-5679,
|
||||
-5539,
|
||||
-5387,
|
||||
-5224,
|
||||
-5050,
|
||||
-4866,
|
||||
-4673,
|
||||
-4472,
|
||||
-4263,
|
||||
-4048,
|
||||
-3826,
|
||||
-3600,
|
||||
-3368,
|
||||
-3133,
|
||||
-2896,
|
||||
-2656,
|
||||
-2414,
|
||||
-2172,
|
||||
-1929,
|
||||
-1687,
|
||||
-1447,
|
||||
-1208,
|
||||
-972,
|
||||
-739,
|
||||
-509,
|
||||
-284,
|
||||
-64,
|
||||
151,
|
||||
360,
|
||||
563,
|
||||
759,
|
||||
948,
|
||||
1130,
|
||||
1304,
|
||||
1469,
|
||||
1627,
|
||||
1775,
|
||||
1915,
|
||||
2046,
|
||||
2168,
|
||||
2280,
|
||||
2382,
|
||||
2476,
|
||||
2559,
|
||||
2633,
|
||||
2698,
|
||||
2752,
|
||||
2798,
|
||||
2833,
|
||||
2860,
|
||||
2877,
|
||||
2886,
|
||||
2885,
|
||||
2876,
|
||||
2859,
|
||||
2833,
|
||||
2800,
|
||||
2759,
|
||||
2711,
|
||||
2655,
|
||||
2593,
|
||||
2525,
|
||||
2451,
|
||||
2371,
|
||||
2285,
|
||||
2195,
|
||||
2101,
|
||||
2002,
|
||||
1900,
|
||||
1794,
|
||||
1686,
|
||||
1575,
|
||||
1461,
|
||||
1346,
|
||||
1230,
|
||||
1113,
|
||||
995,
|
||||
877,
|
||||
759,
|
||||
642,
|
||||
525,
|
||||
410,
|
||||
296,
|
||||
184,
|
||||
74,
|
||||
-33,
|
||||
-137,
|
||||
-239,
|
||||
-337,
|
||||
-432,
|
||||
-524,
|
||||
-611,
|
||||
-694,
|
||||
-773,
|
||||
-848,
|
||||
-918,
|
||||
-983,
|
||||
-1044,
|
||||
-1100,
|
||||
-1151,
|
||||
-1197,
|
||||
-1238,
|
||||
-1274,
|
||||
-1306,
|
||||
-1332,
|
||||
-1353,
|
||||
-1369,
|
||||
-1381,
|
||||
-1387,
|
||||
-1389,
|
||||
-1387,
|
||||
-1380,
|
||||
-1369,
|
||||
-1353,
|
||||
-1333,
|
||||
-1310,
|
||||
-1283,
|
||||
-1252,
|
||||
-1218,
|
||||
-1181,
|
||||
-1140,
|
||||
-1097,
|
||||
-1052,
|
||||
-1004,
|
||||
-954,
|
||||
-902,
|
||||
-848,
|
||||
-793,
|
||||
-736,
|
||||
-679,
|
||||
-621,
|
||||
-562,
|
||||
-502,
|
||||
-443,
|
||||
-383,
|
||||
-324,
|
||||
-265,
|
||||
-207,
|
||||
-150,
|
||||
-93,
|
||||
-38,
|
||||
16,
|
||||
69,
|
||||
119,
|
||||
169,
|
||||
216,
|
||||
261,
|
||||
304,
|
||||
345,
|
||||
383,
|
||||
419,
|
||||
453,
|
||||
484,
|
||||
513,
|
||||
538,
|
||||
562,
|
||||
582,
|
||||
600,
|
||||
615,
|
||||
627,
|
||||
637,
|
||||
644,
|
||||
649,
|
||||
650,
|
||||
650,
|
||||
647,
|
||||
641,
|
||||
633,
|
||||
623,
|
||||
611,
|
||||
596,
|
||||
580,
|
||||
562,
|
||||
542,
|
||||
520,
|
||||
497,
|
||||
473,
|
||||
447,
|
||||
420,
|
||||
392,
|
||||
363,
|
||||
334,
|
||||
304,
|
||||
273,
|
||||
242,
|
||||
210,
|
||||
179,
|
||||
147,
|
||||
116,
|
||||
85,
|
||||
54,
|
||||
24,
|
||||
-6,
|
||||
-35,
|
||||
-63,
|
||||
-90,
|
||||
-117,
|
||||
-142,
|
||||
-166,
|
||||
-189,
|
||||
-211,
|
||||
-231,
|
||||
-250,
|
||||
-268,
|
||||
-284,
|
||||
-298,
|
||||
-311,
|
||||
-322,
|
||||
-332,
|
||||
-340,
|
||||
-346,
|
||||
-351,
|
||||
-354,
|
||||
-356,
|
||||
-356,
|
||||
-354,
|
||||
-351,
|
||||
-347,
|
||||
-341,
|
||||
-333,
|
||||
-325,
|
||||
-314,
|
||||
-303,
|
||||
-291,
|
||||
-277,
|
||||
-263,
|
||||
-247,
|
||||
-231,
|
||||
-213,
|
||||
-195,
|
||||
-177,
|
||||
-158,
|
||||
-138,
|
||||
-118,
|
||||
-98,
|
||||
-77,
|
||||
-56,
|
||||
-36,
|
||||
-15,
|
||||
5,
|
||||
26,
|
||||
46,
|
||||
66,
|
||||
85,
|
||||
104,
|
||||
122,
|
||||
139,
|
||||
156,
|
||||
172,
|
||||
187,
|
||||
202,
|
||||
215,
|
||||
228,
|
||||
239,
|
||||
249,
|
||||
259,
|
||||
267,
|
||||
274,
|
||||
280,
|
||||
285,
|
||||
288,
|
||||
291,
|
||||
292,
|
||||
292,
|
||||
291,
|
||||
289,
|
||||
285,
|
||||
281,
|
||||
275,
|
||||
268,
|
||||
261,
|
||||
252,
|
||||
243,
|
||||
232,
|
||||
221,
|
||||
209,
|
||||
196,
|
||||
182,
|
||||
168,
|
||||
153,
|
||||
138,
|
||||
122,
|
||||
106,
|
||||
89,
|
||||
73,
|
||||
56,
|
||||
38,
|
||||
21,
|
||||
4,
|
||||
-13,
|
||||
-30,
|
||||
-47;
|
||||
@@ -0,0 +1,258 @@
|
||||
MEMORY_INITIALIZATION_RADIX = 10;
|
||||
MEMORY_INITIALIZATION_VECTOR =
|
||||
-2147483647,
|
||||
-2130640638,
|
||||
-2113797629,
|
||||
-2096954620,
|
||||
-2080111611,
|
||||
-2063268602,
|
||||
-2046425593,
|
||||
-2029582584,
|
||||
-2012739575,
|
||||
-1995896566,
|
||||
-1979053557,
|
||||
-1962210548,
|
||||
-1945367539,
|
||||
-1928524530,
|
||||
-1911681521,
|
||||
-1894838512,
|
||||
-1877995503,
|
||||
-1861152494,
|
||||
-1844309485,
|
||||
-1827466476,
|
||||
-1810623467,
|
||||
-1793780458,
|
||||
-1776937449,
|
||||
-1760094440,
|
||||
-1743251431,
|
||||
-1726408422,
|
||||
-1709565413,
|
||||
-1692722404,
|
||||
-1675879395,
|
||||
-1659036386,
|
||||
-1642193377,
|
||||
-1625350368,
|
||||
-1608507359,
|
||||
-1591664350,
|
||||
-1574821341,
|
||||
-1557978332,
|
||||
-1541135323,
|
||||
-1524292314,
|
||||
-1507449305,
|
||||
-1490606296,
|
||||
-1473763287,
|
||||
-1456920278,
|
||||
-1440077269,
|
||||
-1423234260,
|
||||
-1406391251,
|
||||
-1389548242,
|
||||
-1372705233,
|
||||
-1355862224,
|
||||
-1339019215,
|
||||
-1322176206,
|
||||
-1305333197,
|
||||
-1288490188,
|
||||
-1271647179,
|
||||
-1254804170,
|
||||
-1237961161,
|
||||
-1221118152,
|
||||
-1204275143,
|
||||
-1187432134,
|
||||
-1170589125,
|
||||
-1153746116,
|
||||
-1136903107,
|
||||
-1120060098,
|
||||
-1103217089,
|
||||
-1086374080,
|
||||
-1069531071,
|
||||
-1052688062,
|
||||
-1035845053,
|
||||
-1019002044,
|
||||
-1002159035,
|
||||
-985316026,
|
||||
-968473017,
|
||||
-951630008,
|
||||
-934786999,
|
||||
-917943990,
|
||||
-901100981,
|
||||
-884257972,
|
||||
-867414963,
|
||||
-850571954,
|
||||
-833728945,
|
||||
-816885936,
|
||||
-800042927,
|
||||
-783199918,
|
||||
-766356909,
|
||||
-749513900,
|
||||
-732670891,
|
||||
-715827882,
|
||||
-698984873,
|
||||
-682141864,
|
||||
-665298855,
|
||||
-648455846,
|
||||
-631612837,
|
||||
-614769828,
|
||||
-597926819,
|
||||
-581083810,
|
||||
-564240801,
|
||||
-547397792,
|
||||
-530554783,
|
||||
-513711774,
|
||||
-496868765,
|
||||
-480025756,
|
||||
-463182747,
|
||||
-446339738,
|
||||
-429496729,
|
||||
-412653720,
|
||||
-395810711,
|
||||
-378967702,
|
||||
-362124693,
|
||||
-345281684,
|
||||
-328438675,
|
||||
-311595666,
|
||||
-294752657,
|
||||
-277909648,
|
||||
-261066639,
|
||||
-244223630,
|
||||
-227380621,
|
||||
-210537612,
|
||||
-193694603,
|
||||
-176851594,
|
||||
-160008585,
|
||||
-143165576,
|
||||
-126322567,
|
||||
-109479558,
|
||||
-92636549,
|
||||
-75793540,
|
||||
-58950531,
|
||||
-42107522,
|
||||
-25264513,
|
||||
-8421504,
|
||||
8421504,
|
||||
25264513,
|
||||
42107522,
|
||||
58950531,
|
||||
75793540,
|
||||
92636549,
|
||||
109479558,
|
||||
126322567,
|
||||
143165576,
|
||||
160008585,
|
||||
176851594,
|
||||
193694603,
|
||||
210537612,
|
||||
227380621,
|
||||
244223630,
|
||||
261066639,
|
||||
277909648,
|
||||
294752657,
|
||||
311595666,
|
||||
328438675,
|
||||
345281684,
|
||||
362124693,
|
||||
378967702,
|
||||
395810711,
|
||||
412653720,
|
||||
429496729,
|
||||
446339738,
|
||||
463182747,
|
||||
480025756,
|
||||
496868765,
|
||||
513711774,
|
||||
530554783,
|
||||
547397792,
|
||||
564240801,
|
||||
581083810,
|
||||
597926819,
|
||||
614769828,
|
||||
631612837,
|
||||
648455846,
|
||||
665298855,
|
||||
682141864,
|
||||
698984873,
|
||||
715827882,
|
||||
732670891,
|
||||
749513900,
|
||||
766356909,
|
||||
783199918,
|
||||
800042927,
|
||||
816885936,
|
||||
833728945,
|
||||
850571954,
|
||||
867414963,
|
||||
884257972,
|
||||
901100981,
|
||||
917943990,
|
||||
934786999,
|
||||
951630008,
|
||||
968473017,
|
||||
985316026,
|
||||
1002159035,
|
||||
1019002044,
|
||||
1035845053,
|
||||
1052688062,
|
||||
1069531071,
|
||||
1086374080,
|
||||
1103217089,
|
||||
1120060098,
|
||||
1136903107,
|
||||
1153746116,
|
||||
1170589125,
|
||||
1187432134,
|
||||
1204275143,
|
||||
1221118152,
|
||||
1237961161,
|
||||
1254804170,
|
||||
1271647179,
|
||||
1288490188,
|
||||
1305333197,
|
||||
1322176206,
|
||||
1339019215,
|
||||
1355862224,
|
||||
1372705233,
|
||||
1389548242,
|
||||
1406391251,
|
||||
1423234260,
|
||||
1440077269,
|
||||
1456920278,
|
||||
1473763287,
|
||||
1490606296,
|
||||
1507449305,
|
||||
1524292314,
|
||||
1541135323,
|
||||
1557978332,
|
||||
1574821341,
|
||||
1591664350,
|
||||
1608507359,
|
||||
1625350368,
|
||||
1642193377,
|
||||
1659036386,
|
||||
1675879395,
|
||||
1692722404,
|
||||
1709565413,
|
||||
1726408422,
|
||||
1743251431,
|
||||
1760094440,
|
||||
1776937449,
|
||||
1793780458,
|
||||
1810623467,
|
||||
1827466476,
|
||||
1844309485,
|
||||
1861152494,
|
||||
1877995503,
|
||||
1894838512,
|
||||
1911681521,
|
||||
1928524530,
|
||||
1945367539,
|
||||
1962210548,
|
||||
1979053557,
|
||||
1995896566,
|
||||
2012739575,
|
||||
2029582584,
|
||||
2046425593,
|
||||
2063268602,
|
||||
2080111611,
|
||||
2096954620,
|
||||
2113797629,
|
||||
2130640638,
|
||||
2147483647;
|
||||
@@ -0,0 +1,358 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "dds_32b_8b",
|
||||
"component_reference": "xilinx.com:ip:dds_compiler:6.0",
|
||||
"ip_revision": "25",
|
||||
"gen_directory": "../../../../sjl_basic.gen/sources_1/ip/dds_32b_8b",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "dds_32b_8b", "resolve_type": "user", "usage": "all" } ],
|
||||
"PartsPresent": [ { "value": "Phase_Generator_and_SIN_COS_LUT", "resolve_type": "user", "usage": "all" } ],
|
||||
"DDS_Clock_Rate": [ { "value": "48", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"Channels": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
|
||||
"Mode_of_Operation": [ { "value": "Standard", "resolve_type": "user", "usage": "all" } ],
|
||||
"Modulus": [ { "value": "9", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Output_Type": [ { "value": "Integer", "resolve_type": "user", "usage": "all" } ],
|
||||
"Parameter_Entry": [ { "value": "Hardware_Parameters", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Spurious_Free_Dynamic_Range": [ { "value": "45", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"Frequency_Resolution": [ { "value": "0.4", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"Noise_Shaping": [ { "value": "None", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Phase_Width": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Output_Width": [ { "value": "8", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Phase_Increment": [ { "value": "Programmable", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Resync": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Phase_offset": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
|
||||
"Output_Selection": [ { "value": "Sine_and_Cosine", "resolve_type": "user", "usage": "all" } ],
|
||||
"Negative_Sine": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Negative_Cosine": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Amplitude_Mode": [ { "value": "Full_Range", "resolve_type": "user", "usage": "all" } ],
|
||||
"Memory_Type": [ { "value": "Auto", "resolve_type": "user", "usage": "all" } ],
|
||||
"Optimization_Goal": [ { "value": "Auto", "resolve_type": "user", "usage": "all" } ],
|
||||
"DSP48_Use": [ { "value": "Minimal", "resolve_type": "user", "usage": "all" } ],
|
||||
"Has_Phase_Out": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"DATA_Has_TLAST": [ { "value": "Not_Required", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Has_TREADY": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"S_PHASE_Has_TUSER": [ { "value": "Not_Required", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"S_PHASE_TUSER_Width": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M_DATA_Has_TUSER": [ { "value": "Not_Required", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"M_PHASE_Has_TUSER": [ { "value": "Not_Required", "resolve_type": "user", "usage": "all" } ],
|
||||
"S_CONFIG_Sync_Mode": [ { "value": "On_Vector", "resolve_type": "user", "usage": "all" } ],
|
||||
"OUTPUT_FORM": [ { "value": "Twos_Complement", "resolve_type": "user", "usage": "all" } ],
|
||||
"Latency_Configuration": [ { "value": "Auto", "resolve_type": "user", "usage": "all" } ],
|
||||
"Latency": [ { "value": "3", "resolve_type": "user", "usage": "all" } ],
|
||||
"Has_ARESETn": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Has_ACLKEN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Output_Frequency1": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PINC1": [ { "value": "1101101001110100", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Phase_Offset_Angles1": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"POFF1": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Output_Frequency2": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PINC2": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Phase_Offset_Angles2": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"POFF2": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Output_Frequency3": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PINC3": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Phase_Offset_Angles3": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"POFF3": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Output_Frequency4": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PINC4": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Phase_Offset_Angles4": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"POFF4": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Output_Frequency5": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PINC5": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Phase_Offset_Angles5": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"POFF5": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Output_Frequency6": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PINC6": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Phase_Offset_Angles6": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"POFF6": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Output_Frequency7": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PINC7": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Phase_Offset_Angles7": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"POFF7": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Output_Frequency8": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PINC8": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Phase_Offset_Angles8": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"POFF8": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Output_Frequency9": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PINC9": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Phase_Offset_Angles9": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"POFF9": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Output_Frequency10": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PINC10": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Phase_Offset_Angles10": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"POFF10": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Output_Frequency11": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PINC11": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Phase_Offset_Angles11": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"POFF11": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Output_Frequency12": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PINC12": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Phase_Offset_Angles12": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"POFF12": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Output_Frequency13": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PINC13": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Phase_Offset_Angles13": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"POFF13": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Output_Frequency14": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PINC14": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Phase_Offset_Angles14": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"POFF14": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Output_Frequency15": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PINC15": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Phase_Offset_Angles15": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"POFF15": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Output_Frequency16": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PINC16": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Phase_Offset_Angles16": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"POFF16": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"POR_mode": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"GUI_Behaviour": [ { "value": "Coregen", "resolve_type": "user", "usage": "all" } ],
|
||||
"explicit_period": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"period": [ { "value": "1", "resolve_type": "user", "format": "float", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_XDEVICEFAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MODE_OF_OPERATION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MODULUS": [ { "value": "9", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ACCUMULATOR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CHANNELS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_PHASE_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_PHASEGEN": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_SINCOS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_LATENCY": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MEM_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NEGATIVE_COSINE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NEGATIVE_SINE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NOISE_SHAPING": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_OUTPUTS_REQUIRED": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_OUTPUT_FORM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_OUTPUT_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_OUTPUT_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PHASE_ANGLE_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PHASE_INCREMENT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PHASE_INCREMENT_VALUE": [ { "value": "1101101001110100,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_RESYNC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PHASE_OFFSET": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PHASE_OFFSET_VALUE": [ { "value": "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OPTIMISE_GOAL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_DSP48": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_POR_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AMPLITUDE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_ACLKEN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_ARESETN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_TREADY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_S_PHASE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_PHASE_TDATA_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_PHASE_HAS_TUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_PHASE_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_S_CONFIG": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_CONFIG_SYNC_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_CONFIG_TDATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_M_DATA": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_DATA_TDATA_WIDTH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_DATA_HAS_TUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_DATA_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_M_PHASE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_PHASE_TDATA_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_PHASE_HAS_TUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_PHASE_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DEBUG_INTERFACE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CHAN_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z100" } ],
|
||||
"NEXTGEN_VERSAL": [ { "value": "0" } ],
|
||||
"PACKAGE": [ { "value": "ffg900" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Flow" } ],
|
||||
"IPREVISION": [ { "value": "25" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../sjl_basic.gen/sources_1/ip/dds_32b_8b" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2024.1.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"aclk": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_config_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_config_tdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"m_axis_data_tvalid": [ { "direction": "out", "driver_value": "0x0" } ],
|
||||
"m_axis_data_tdata": [ { "direction": "out", "size_left": "15", "size_right": "0", "driver_value": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"event_pinc_invalid_intf": {
|
||||
"vlnv": "xilinx.com:signal:interrupt:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
|
||||
"PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"event_poff_invalid_intf": {
|
||||
"vlnv": "xilinx.com:signal:interrupt:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
|
||||
"PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"event_phase_in_invalid_intf": {
|
||||
"vlnv": "xilinx.com:signal:interrupt:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
|
||||
"PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"event_s_phase_tlast_missing_intf": {
|
||||
"vlnv": "xilinx.com:signal:interrupt:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
|
||||
"PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"event_s_phase_tlast_unexpected_intf": {
|
||||
"vlnv": "xilinx.com:signal:interrupt:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
|
||||
"PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"event_s_phase_chanid_incorrect_intf": {
|
||||
"vlnv": "xilinx.com:signal:interrupt:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
|
||||
"PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"event_s_config_tlast_missing_intf": {
|
||||
"vlnv": "xilinx.com:signal:interrupt:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
|
||||
"PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"event_s_config_tlast_unexpected_intf": {
|
||||
"vlnv": "xilinx.com:signal:interrupt:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
|
||||
"PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"aclk_intf": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "M_AXIS_PHASE:S_AXIS_CONFIG:M_AXIS_DATA:S_AXIS_PHASE", "value_src": "constant", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "usage": "all" } ],
|
||||
"ASSOCIATED_CLKEN": [ { "value": "aclken", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "aclk" } ]
|
||||
}
|
||||
},
|
||||
"aresetn_intf": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"aclken_intf": {
|
||||
"vlnv": "xilinx.com:signal:clockenable:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ]
|
||||
}
|
||||
},
|
||||
"M_AXIS_DATA": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "2", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "m_axis_data_tdata" } ],
|
||||
"TVALID": [ { "physical_name": "m_axis_data_tvalid" } ]
|
||||
}
|
||||
},
|
||||
"S_AXIS_CONFIG": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "4", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "s_axis_config_tdata" } ],
|
||||
"TVALID": [ { "physical_name": "s_axis_config_tvalid" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,254 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "hop_rom",
|
||||
"component_reference": "xilinx.com:ip:blk_mem_gen:8.4",
|
||||
"ip_revision": "8",
|
||||
"gen_directory": "../../../../sjl_basic.gen/sources_1/ip/hop_rom",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "hop_rom", "resolve_type": "user", "usage": "all" } ],
|
||||
"Interface_Type": [ { "value": "Native", "resolve_type": "user", "usage": "all" } ],
|
||||
"AXI_Type": [ { "value": "AXI4_Full", "resolve_type": "user", "usage": "all" } ],
|
||||
"AXI_Slave_Type": [ { "value": "Memory_Slave", "resolve_type": "user", "usage": "all" } ],
|
||||
"Use_AXI_ID": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"AXI_ID_Width": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Memory_Type": [ { "value": "Single_Port_ROM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PRIM_type_to_Implement": [ { "value": "BRAM", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_32bit_Address": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ecctype": [ { "value": "No_ECC", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"ECC": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"EN_SLEEP_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"EN_DEEPSLEEP_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"EN_SHUTDOWN_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"EN_ECC_PIPE": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"RD_ADDR_CHNG_A": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"RD_ADDR_CHNG_B": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Use_Error_Injection_Pins": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Error_Injection_Type": [ { "value": "Single_Bit_Error_Injection", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Use_Byte_Write_Enable": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Byte_Size": [ { "value": "9", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Algorithm": [ { "value": "Minimum_Area", "resolve_type": "user", "usage": "all" } ],
|
||||
"Primitive": [ { "value": "8kx2", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Assume_Synchronous_Clk": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Write_Width_A": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Write_Depth_A": [ { "value": "256", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Read_Width_A": [ { "value": "32", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Operating_Mode_A": [ { "value": "WRITE_FIRST", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_A": [ { "value": "Always_Enabled", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Write_Width_B": [ { "value": "32", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Read_Width_B": [ { "value": "32", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Operating_Mode_B": [ { "value": "WRITE_FIRST", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_B": [ { "value": "Always_Enabled", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Register_PortA_Output_of_Memory_Primitives": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Register_PortA_Output_of_Memory_Core": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Use_REGCEA_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Register_PortB_Output_of_Memory_Primitives": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Register_PortB_Output_of_Memory_Core": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Use_REGCEB_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"register_porta_input_of_softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"register_portb_output_of_softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Pipeline_Stages": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Load_Init_File": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Coe_File": [ { "value": "../coe/sweep_freq.coe", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Fill_Remaining_Memory_Locations": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Remaining_Memory_Locations": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Use_RSTA_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Reset_Memory_Latch_A": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Reset_Priority_A": [ { "value": "CE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Output_Reset_Value_A": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Use_RSTB_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Reset_Memory_Latch_B": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Reset_Priority_B": [ { "value": "CE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Output_Reset_Value_B": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Reset_Type": [ { "value": "SYNC", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Additional_Inputs_for_Power_Estimation": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Port_A_Clock": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Port_A_Write_Rate": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Port_B_Clock": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Port_B_Write_Rate": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Port_A_Enable_Rate": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Port_B_Enable_Rate": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Collision_Warnings": [ { "value": "ALL", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Disable_Collision_Warnings": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Disable_Out_of_Range_Warnings": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"use_bram_block": [ { "value": "Stand_Alone", "resolve_type": "user", "usage": "all" } ],
|
||||
"MEM_FILE": [ { "value": "no_mem_loaded", "resolve_type": "user", "usage": "all" } ],
|
||||
"CTRL_ECC_ALGO": [ { "value": "NONE", "resolve_type": "user", "usage": "all" } ],
|
||||
"EN_SAFETY_CKT": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"READ_LATENCY_A": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"READ_LATENCY_B": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_FAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_XDEVICEFAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_ELABORATION_DIR": [ { "value": "./", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_INTERFACE_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_SLAVE_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_BRAM_BLOCK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ENABLE_32BIT_ADDRESS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CTRL_ECC_ALGO": [ { "value": "NONE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_HAS_AXI_ID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_ID_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MEM_TYPE": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_BYTE_SIZE": [ { "value": "9", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ALGORITHM": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PRIM_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_LOAD_INIT_FILE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INIT_FILE_NAME": [ { "value": "hop_rom.mif", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_INIT_FILE": [ { "value": "hop_rom.mem", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_USE_DEFAULT_DATA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DEFAULT_DATA": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_HAS_RSTA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_RST_PRIORITY_A": [ { "value": "CE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_RSTRAM_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INITA_VAL": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_HAS_ENA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_REGCEA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_BYTE_WEA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WEA_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WRITE_MODE_A": [ { "value": "WRITE_FIRST", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_WRITE_WIDTH_A": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_READ_WIDTH_A": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WRITE_DEPTH_A": [ { "value": "256", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_READ_DEPTH_A": [ { "value": "256", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ADDRA_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_RSTB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_RST_PRIORITY_B": [ { "value": "CE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_RSTRAM_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INITB_VAL": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_HAS_ENB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_REGCEB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_BYTE_WEB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WEB_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WRITE_MODE_B": [ { "value": "WRITE_FIRST", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_WRITE_WIDTH_B": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_READ_WIDTH_B": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WRITE_DEPTH_B": [ { "value": "256", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_READ_DEPTH_B": [ { "value": "256", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ADDRB_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_MEM_OUTPUT_REGS_A": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_MEM_OUTPUT_REGS_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_MUX_OUTPUT_REGS_A": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_MUX_OUTPUT_REGS_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MUX_PIPELINE_STAGES": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_SOFTECC_INPUT_REGS_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_SOFTECC_OUTPUT_REGS_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_SOFTECC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_ECC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_EN_ECC_PIPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_READ_LATENCY_A": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_READ_LATENCY_B": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_INJECTERR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SIM_COLLISION_CHECK": [ { "value": "ALL", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_COMMON_CLK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DISABLE_WARN_BHV_COLL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_EN_SLEEP_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_URAM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_EN_RDADDRA_CHG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_EN_RDADDRB_CHG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_EN_DEEPSLEEP_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_EN_SHUTDOWN_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_EN_SAFETY_CKT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DISABLE_WARN_BHV_RANGE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_COUNT_36K_BRAM": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_COUNT_18K_BRAM": [ { "value": "1", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_EST_POWER_SUMMARY": [ { "value": "Estimated Power for IP : 3.375199 mW", "resolve_type": "generated", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z100" } ],
|
||||
"NEXTGEN_VERSAL": [ { "value": "0" } ],
|
||||
"PACKAGE": [ { "value": "ffg900" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Flow" } ],
|
||||
"IPREVISION": [ { "value": "8" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../sjl_basic.gen/sources_1/ip/hop_rom" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2024.1.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"clka": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"addra": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
|
||||
"douta": [ { "direction": "out", "size_left": "31", "size_right": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"CLK.ACLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "AXI_SLAVE_S_AXI:AXILite_SLAVE_S_AXI", "value_src": "constant", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "s_aresetn", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"RST.ARESETN": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"BRAM_PORTA": {
|
||||
"vlnv": "xilinx.com:interface:bram:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:bram_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"MEM_ADDRESS_MODE": [ { "value": "BYTE_ADDRESS", "resolve_type": "user", "usage": "all" } ],
|
||||
"MEM_SIZE": [ { "value": "8192", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MEM_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MEM_ECC": [ { "value": "NONE", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MASTER_TYPE": [ { "value": "OTHER", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"ADDR": [ { "physical_name": "addra" } ],
|
||||
"CLK": [ { "physical_name": "clka" } ],
|
||||
"DOUT": [ { "physical_name": "douta" } ]
|
||||
}
|
||||
}
|
||||
},
|
||||
"memory_maps": {
|
||||
"S_1": {
|
||||
"address_blocks": {
|
||||
"Mem0": {
|
||||
"base_address": "0",
|
||||
"range": "4096",
|
||||
"usage": "memory",
|
||||
"access": "read-write",
|
||||
"parameters": {
|
||||
"OFFSET_BASE_PARAM": [ { "value": "C_BASEADDR" } ],
|
||||
"OFFSET_HIGH_PARAM": [ { "value": "C_HIGHADDR" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,350 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "hrc_64_12_025",
|
||||
"component_reference": "xilinx.com:ip:fir_compiler:7.2",
|
||||
"ip_revision": "22",
|
||||
"gen_directory": "../../../../sjl_basic.gen/sources_1/ip/hrc_64_12_025",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "hrc_64_12_025", "resolve_type": "user", "usage": "all" } ],
|
||||
"GUI_Behaviour": [ { "value": "Coregen", "resolve_type": "user", "usage": "all" } ],
|
||||
"CoefficientSource": [ { "value": "COE_File", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"CoefficientVector": [ { "value": "6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6", "resolve_type": "user", "usage": "all" } ],
|
||||
"Coefficient_File": [ { "value": "../coe/hrc_64_12_025.coe", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Coefficient_Sets": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Coefficient_Reload": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Filter_Type": [ { "value": "Interpolation", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Rate_Change_Type": [ { "value": "Integer", "resolve_type": "user", "usage": "all" } ],
|
||||
"Interpolation_Rate": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Decimation_Rate": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Zero_Pack_Factor": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Channel_Sequence": [ { "value": "Basic", "resolve_type": "user", "usage": "all" } ],
|
||||
"Number_Channels": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Select_Pattern": [ { "value": "All", "resolve_type": "user", "usage": "all" } ],
|
||||
"Pattern_List": [ { "value": "P4-0,P4-1,P4-2,P4-3,P4-4", "resolve_type": "user", "usage": "all" } ],
|
||||
"Number_Paths": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"RateSpecification": [ { "value": "Input_Sample_Period", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"HardwareOversamplingRate": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SamplePeriod": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"Sample_Frequency": [ { "value": "0.001", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"Clock_Frequency": [ { "value": "300.0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"Coefficient_Sign": [ { "value": "Signed", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Quantization": [ { "value": "Integer_Coefficients", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Coefficient_Width": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"BestPrecision": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Coefficient_Fractional_Bits": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Coefficient_Structure": [ { "value": "Inferred", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Data_Sign": [ { "value": "Signed", "resolve_type": "user", "usage": "all" } ],
|
||||
"Data_Width": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Data_Fractional_Bits": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Output_Rounding_Mode": [ { "value": "Full_Precision", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Output_Width": [ { "value": "18", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Filter_Architecture": [ { "value": "Systolic_Multiply_Accumulate", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Optimization_Goal": [ { "value": "Area", "resolve_type": "user", "usage": "all" } ],
|
||||
"Optimization_Selection": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
|
||||
"Data_Path_Fanout": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Pre_Adder_Pipeline": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Coefficient_Fanout": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Control_Path_Fanout": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Control_Column_Fanout": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Control_Broadcast_Fanout": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Control_LUT_Pipeline": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"No_BRAM_Read_First_Mode": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Optimal_Column_Lengths": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Data_Path_Broadcast": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Disable_Half_Band_Centre_Tap": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"No_SRL_Attributes": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Other": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Optimization_List": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
|
||||
"Data_Buffer_Type": [ { "value": "Automatic", "resolve_type": "user", "usage": "all" } ],
|
||||
"Coefficient_Buffer_Type": [ { "value": "Automatic", "resolve_type": "user", "usage": "all" } ],
|
||||
"Input_Buffer_Type": [ { "value": "Automatic", "resolve_type": "user", "usage": "all" } ],
|
||||
"Output_Buffer_Type": [ { "value": "Automatic", "resolve_type": "user", "usage": "all" } ],
|
||||
"Preference_For_Other_Storage": [ { "value": "Automatic", "resolve_type": "user", "usage": "all" } ],
|
||||
"Multi_Column_Support": [ { "value": "Automatic", "resolve_type": "user", "usage": "all" } ],
|
||||
"Inter_Column_Pipe_Length": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ColumnConfig": [ { "value": "7", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"DATA_Has_TLAST": [ { "value": "Not_Required", "resolve_type": "user", "usage": "all" } ],
|
||||
"M_DATA_Has_TREADY": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"S_DATA_Has_FIFO": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"S_DATA_Has_TUSER": [ { "value": "Not_Required", "resolve_type": "user", "usage": "all" } ],
|
||||
"M_DATA_Has_TUSER": [ { "value": "Not_Required", "resolve_type": "user", "usage": "all" } ],
|
||||
"DATA_TUSER_Width": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S_CONFIG_Sync_Mode": [ { "value": "On_Vector", "resolve_type": "user", "usage": "all" } ],
|
||||
"S_CONFIG_Method": [ { "value": "Single", "resolve_type": "user", "usage": "all" } ],
|
||||
"Num_Reload_Slots": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Has_ACLKEN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Has_ARESETn": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Reset_Data_Vector": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Blank_Output": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Gen_MIF_from_Spec": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Gen_MIF_from_COE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Reload_File": [ { "value": "no_coe_file_loaded", "resolve_type": "user", "usage": "all" } ],
|
||||
"Gen_MIF_Files": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"DisplayReloadOrder": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Passband_Min": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"Passband_Max": [ { "value": "0.5", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"Stopband_Min": [ { "value": "0.5", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"Stopband_Max": [ { "value": "1.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"Filter_Selection": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_XDEVICEFAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_ELABORATION_DIR": [ { "value": "./", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_COMPONENT_NAME": [ { "value": "hrc_64_12_025", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_COEF_FILE": [ { "value": "hrc_64_12_025.mif", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_COEF_FILE_LINES": [ { "value": "448", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_FILTER_TYPE": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INTERP_RATE": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DECIM_RATE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ZERO_PACKING_FACTOR": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SYMMETRY": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_FILTS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_TAPS": [ { "value": "769", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_CHANNELS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CHANNEL_PATTERN": [ { "value": "fixed", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_ROUND_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_COEF_RELOAD": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_RELOAD_SLOTS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_COL_MODE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_COL_PIPE_LEN": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_COL_CONFIG": [ { "value": "7", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OPTIMIZATION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DATA_PATH_WIDTHS": [ { "value": "2", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DATA_IP_PATH_WIDTHS": [ { "value": "2", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DATA_PX_PATH_WIDTHS": [ { "value": "2", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DATA_WIDTH": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_COEF_PATH_WIDTHS": [ { "value": "17", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_COEF_WIDTH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DATA_PATH_SRC": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_COEF_PATH_SRC": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PX_PATH_SRC": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DATA_PATH_SIGN": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_COEF_PATH_SIGN": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_ACCUM_PATH_WIDTHS": [ { "value": "19", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTPUT_WIDTH": [ { "value": "18", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_OUTPUT_PATH_WIDTHS": [ { "value": "18", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_ACCUM_OP_PATH_WIDTHS": [ { "value": "18", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_EXT_MULT_CNFG": [ { "value": "none", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DATA_PATH_PSAMP_SRC": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OP_PATH_PSAMP_SRC": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_NUM_MADDS": [ { "value": "7", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_OPT_MADDS": [ { "value": "none", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OVERSAMPLING_RATE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INPUT_RATE": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_OUTPUT_RATE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DATA_MEMTYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_COEF_MEMTYPE": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_IPBUFF_MEMTYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_OPBUFF_MEMTYPE": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DATAPATH_MEMTYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MEM_ARRANGEMENT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DATA_MEM_PACKING": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_COEF_MEM_PACKING": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_FILTS_PACKED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_LATENCY": [ { "value": "17", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_ARESETn": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_ACLKEN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DATA_HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_DATA_HAS_FIFO": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_DATA_HAS_TUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_DATA_TDATA_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_DATA_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_DATA_HAS_TREADY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_DATA_HAS_TUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_DATA_TDATA_WIDTH": [ { "value": "24", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_DATA_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_CONFIG_CHANNEL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CONFIG_SYNC_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CONFIG_PACKET_SIZE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CONFIG_TDATA_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_RELOAD_TDATA_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z100" } ],
|
||||
"NEXTGEN_VERSAL": [ { "value": "0" } ],
|
||||
"PACKAGE": [ { "value": "ffg900" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Flow" } ],
|
||||
"IPREVISION": [ { "value": "22" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../sjl_basic.gen/sources_1/ip/hrc_64_12_025" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2024.1.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"aclk": [ { "direction": "in" } ],
|
||||
"s_axis_data_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_data_tready": [ { "direction": "out", "driver_value": "0x1" } ],
|
||||
"s_axis_data_tdata": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
|
||||
"m_axis_data_tvalid": [ { "direction": "out", "driver_value": "0x0" } ],
|
||||
"m_axis_data_tdata": [ { "direction": "out", "size_left": "23", "size_right": "0", "driver_value": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"event_s_data_tlast_missing_intf": {
|
||||
"vlnv": "xilinx.com:signal:interrupt:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
|
||||
"PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"event_s_data_tlast_unexpected_intf": {
|
||||
"vlnv": "xilinx.com:signal:interrupt:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
|
||||
"PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"event_s_data_chanid_incorrect_intf": {
|
||||
"vlnv": "xilinx.com:signal:interrupt:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
|
||||
"PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"event_s_config_tlast_missing_intf": {
|
||||
"vlnv": "xilinx.com:signal:interrupt:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
|
||||
"PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"event_s_config_tlast_unexpected_intf": {
|
||||
"vlnv": "xilinx.com:signal:interrupt:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
|
||||
"PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"event_s_reload_tlast_missing_intf": {
|
||||
"vlnv": "xilinx.com:signal:interrupt:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
|
||||
"PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"event_s_reload_tlast_unexpected_intf": {
|
||||
"vlnv": "xilinx.com:signal:interrupt:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
|
||||
"PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"aclk_intf": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S_AXIS_CONFIG:M_AXIS_DATA:S_AXIS_DATA:S_AXIS_RELOAD", "value_src": "constant", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "usage": "all" } ],
|
||||
"ASSOCIATED_CLKEN": [ { "value": "aclken", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "aclk" } ]
|
||||
}
|
||||
},
|
||||
"aresetn_intf": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"aclken_intf": {
|
||||
"vlnv": "xilinx.com:signal:clockenable:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ]
|
||||
}
|
||||
},
|
||||
"S_AXIS_DATA": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "s_axis_data_tdata" } ],
|
||||
"TREADY": [ { "physical_name": "s_axis_data_tready" } ],
|
||||
"TVALID": [ { "physical_name": "s_axis_data_tvalid" } ]
|
||||
}
|
||||
},
|
||||
"M_AXIS_DATA": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "3", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "m_axis_data_tdata" } ],
|
||||
"TVALID": [ { "physical_name": "m_axis_data_tvalid" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,200 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
// _ _ ____
|
||||
// | | ___ ___| |__ / ___| __ _ ___
|
||||
// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
|
||||
// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
|
||||
// \___/ \___/|___/_| |_| \____|\__,_|\___/
|
||||
//
|
||||
// Create Date: 2022/07/01 17:37:27
|
||||
// Last Modified Date: 2023/03/06 11:26
|
||||
// Design Name:
|
||||
// Module Name: ad9361_rx_map_cmos_dual
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module ad9361_rx_map_cmos_dual
|
||||
(
|
||||
input clk_2x_in ,
|
||||
input clk_in_rst ,
|
||||
|
||||
input rx_data_clk , // sync to output data
|
||||
input rx_data_clk_rst ,
|
||||
|
||||
input rx_fifo_rst , // async fifo reset
|
||||
|
||||
input rx_frame ,
|
||||
input [11:0] rx_data ,
|
||||
|
||||
output [11:0] rx_ch1_i ,
|
||||
output [11:0] rx_ch1_q ,
|
||||
output [11:0] rx_ch2_i ,
|
||||
output [11:0] rx_ch2_q
|
||||
);
|
||||
|
||||
genvar mm;
|
||||
|
||||
// rx data
|
||||
wire [11:0] rx_data_pos;
|
||||
wire [11:0] rx_data_neg;
|
||||
|
||||
generate
|
||||
for (mm = 0; mm < 12; mm = mm + 1) begin
|
||||
|
||||
IDDR #(
|
||||
.DDR_CLK_EDGE ("SAME_EDGE" ),
|
||||
.INIT_Q1 (1'b0 ),
|
||||
.INIT_Q2 (1'b0 ),
|
||||
.SRTYPE ("ASYNC" )
|
||||
) i_rx_data_iddr (
|
||||
.CE (1'b1 ),
|
||||
.R (1'b0 ),
|
||||
.S (1'b0 ),
|
||||
.C (clk_2x_in ),
|
||||
.D (rx_data[mm] ),
|
||||
.Q1 (rx_data_pos[mm]),
|
||||
.Q2 (rx_data_neg[mm])
|
||||
);
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// rx frame
|
||||
wire rx_frame_pos;
|
||||
wire rx_frame_neg;
|
||||
|
||||
IDDR #(
|
||||
.DDR_CLK_EDGE ("SAME_EDGE" ),
|
||||
.INIT_Q1 (1'b0 ),
|
||||
.INIT_Q2 (1'b0 ),
|
||||
.SRTYPE ("ASYNC" )
|
||||
) i_rx_frame_iddr (
|
||||
.CE (1'b1 ),
|
||||
.R (1'b0 ),
|
||||
.S (1'b0 ),
|
||||
.C (clk_2x_in ),
|
||||
.D (rx_frame ),
|
||||
.Q1 (rx_frame_pos ),
|
||||
.Q2 (rx_frame_neg )
|
||||
);
|
||||
|
||||
// divide rx_data to dual channel
|
||||
reg [11:0] rx1_data_i = 'b0;
|
||||
reg [11:0] rx1_data_q = 'b0;
|
||||
reg [11:0] rx2_data_i = 'b0;
|
||||
reg [11:0] rx2_data_q = 'b0;
|
||||
|
||||
reg rx_fifo_wr_en = 'b0;
|
||||
reg rx_fifo_rd_en = 'b0;
|
||||
|
||||
wire rx_fifo_empty_1;
|
||||
wire rx_fifo_empty_2;
|
||||
wire rx_fifo_empty_3;
|
||||
wire rx_fifo_empty_4;
|
||||
|
||||
always @ (posedge clk_2x_in) begin
|
||||
if (clk_in_rst) begin
|
||||
rx1_data_i <= 'b0;
|
||||
rx1_data_q <= 'b0;
|
||||
rx2_data_i <= 'b0;
|
||||
rx2_data_q <= 'b0;
|
||||
rx_fifo_wr_en <= 'b0;
|
||||
end
|
||||
else if({rx_frame_neg,rx_frame_pos} == 2'b11) begin
|
||||
rx1_data_i <= rx_data_neg;
|
||||
rx1_data_q <= rx_data_pos;
|
||||
rx2_data_i <= rx2_data_i;
|
||||
rx2_data_q <= rx2_data_q;
|
||||
rx_fifo_wr_en <= 'b0;
|
||||
end
|
||||
else if({rx_frame_neg,rx_frame_pos} == 2'b00) begin
|
||||
rx1_data_i <= rx1_data_i;
|
||||
rx1_data_q <= rx1_data_q;
|
||||
rx2_data_i <= rx_data_neg;
|
||||
rx2_data_q <= rx_data_pos;
|
||||
rx_fifo_wr_en <= 'b1;
|
||||
end
|
||||
else begin
|
||||
rx1_data_i <= 'd1234; // error
|
||||
rx1_data_q <= 'd4321; // error
|
||||
rx2_data_i <= 'd5678; // error
|
||||
rx2_data_q <= 'd8765; // error
|
||||
rx_fifo_wr_en <= 'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge rx_data_clk) begin
|
||||
if (rx_data_clk_rst) begin
|
||||
rx_fifo_rd_en <= 'b0;
|
||||
end
|
||||
else begin
|
||||
rx_fifo_rd_en <= &{~rx_fifo_empty_1, ~rx_fifo_empty_2, ~rx_fifo_empty_3, ~rx_fifo_empty_4};
|
||||
end
|
||||
end
|
||||
|
||||
ad9361_fifo u_rx_fifo_ch1_i
|
||||
(
|
||||
.rst (clk_in_rst || rx_fifo_rst ), // input wire rst
|
||||
.wr_clk (clk_2x_in ), // input wire wr_clk
|
||||
.rd_clk (rx_data_clk ), // input wire rd_clk
|
||||
.din (rx1_data_i ), // input wire [11 : 0] din
|
||||
.wr_en (rx_fifo_wr_en ), // input wire wr_en
|
||||
.rd_en (rx_fifo_rd_en ), // input wire rd_en
|
||||
.dout (rx_ch1_i ), // output wire [11 : 0] dout
|
||||
.full ( ), // output wire full
|
||||
.empty (rx_fifo_empty_1 ) // output wire empty
|
||||
);
|
||||
|
||||
ad9361_fifo u_rx_fifo_ch1_q
|
||||
(
|
||||
.rst (clk_in_rst || rx_fifo_rst ), // input wire rst
|
||||
.wr_clk (clk_2x_in ), // input wire wr_clk
|
||||
.rd_clk (rx_data_clk ), // input wire rd_clk
|
||||
.din (rx1_data_q ), // input wire [11 : 0] din
|
||||
.wr_en (rx_fifo_wr_en ), // input wire wr_en
|
||||
.rd_en (rx_fifo_rd_en ), // input wire rd_en
|
||||
.dout (rx_ch1_q ), // output wire [11 : 0] dout
|
||||
.full ( ), // output wire full
|
||||
.empty (rx_fifo_empty_2 ) // output wire empty
|
||||
);
|
||||
|
||||
ad9361_fifo u_rx_fifo_ch2_i
|
||||
(
|
||||
.rst (clk_in_rst || rx_fifo_rst ), // input wire rst
|
||||
.wr_clk (clk_2x_in ), // input wire wr_clk
|
||||
.rd_clk (rx_data_clk ), // input wire rd_clk
|
||||
.din (rx2_data_i ), // input wire [11 : 0] din
|
||||
.wr_en (rx_fifo_wr_en ), // input wire wr_en
|
||||
.rd_en (rx_fifo_rd_en ), // input wire rd_en
|
||||
.dout (rx_ch2_i ), // output wire [11 : 0] dout
|
||||
.full ( ), // output wire full
|
||||
.empty (rx_fifo_empty_3 ) // output wire empty
|
||||
);
|
||||
|
||||
ad9361_fifo u_rx_fifo_ch2_q
|
||||
(
|
||||
.rst (clk_in_rst || rx_fifo_rst ), // input wire rst
|
||||
.wr_clk (clk_2x_in ), // input wire wr_clk
|
||||
.rd_clk (rx_data_clk ), // input wire rd_clk
|
||||
.din (rx2_data_q ), // input wire [11 : 0] din
|
||||
.wr_en (rx_fifo_wr_en ), // input wire wr_en
|
||||
.rd_en (rx_fifo_rd_en ), // input wire rd_en
|
||||
.dout (rx_ch2_q ), // output wire [11 : 0] dout
|
||||
.full ( ), // output wire full
|
||||
.empty (rx_fifo_empty_4 ) // output wire empty
|
||||
);
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,163 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
// _ _ ____
|
||||
// | | ___ ___| |__ / ___| __ _ ___
|
||||
// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
|
||||
// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
|
||||
// \___/ \___/|___/_| |_| \____|\__,_|\___/
|
||||
//
|
||||
// Create Date: 2022/07/01 17:37:27
|
||||
// Last Modified Date: 2023/03/03 13:01
|
||||
// Design Name:
|
||||
// Module Name: ad9361_rx_map_cmos_single
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module ad9361_rx_map_cmos_single
|
||||
(
|
||||
input clk_in ,
|
||||
input clk_in_rst ,
|
||||
|
||||
input rx_data_clk ,
|
||||
input rx_data_clk_rst ,
|
||||
|
||||
input rx_fifo_rst ,
|
||||
|
||||
input rx_frame ,
|
||||
input [11:0] rx_data ,
|
||||
|
||||
output [11:0] rx_data_i ,
|
||||
output [11:0] rx_data_q
|
||||
);
|
||||
|
||||
genvar mm;
|
||||
|
||||
// rx data from port
|
||||
wire [11:0] rx_data_pos;
|
||||
wire [11:0] rx_data_neg;
|
||||
|
||||
generate
|
||||
for (mm = 0; mm < 12; mm = mm + 1) begin : rx_data_iddr
|
||||
IDDR #(
|
||||
.DDR_CLK_EDGE ("SAME_EDGE" ), // "OPPOSITE_EDGE", "SAME_EDGE" or "SAME_EDGE_PIPELINED"
|
||||
.INIT_Q1 (1'b0 ), // Initial value of Q1: 1'b0 or 1'b1
|
||||
.INIT_Q2 (1'b0 ), // Initial value of Q2: 1'b0 or 1'b1
|
||||
.SRTYPE ("ASYNC" ) // Set/Reset type: "SYNC" or "ASYNC"
|
||||
) i_rx_data_iddr (
|
||||
.CE (1'b1 ), // 1-bit clock enable input
|
||||
.R (1'b0 ), // 1-bit reset
|
||||
.S (1'b0 ), // 1-bit set
|
||||
.C (clk_in ), // 1-bit clock input
|
||||
.D (rx_data[mm] ), // 1-bit DDR data input
|
||||
.Q1 (rx_data_pos[mm]), // 1-bit output for positive edge of clock
|
||||
.Q2 (rx_data_neg[mm]) // 1-bit output for negative edge of clock
|
||||
);
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// rx frame from port
|
||||
wire rx_frame_pos;
|
||||
wire rx_frame_neg;
|
||||
|
||||
IDDR #(
|
||||
.DDR_CLK_EDGE ("SAME_EDGE" ), // "OPPOSITE_EDGE", "SAME_EDGE" or "SAME_EDGE_PIPELINED"
|
||||
.INIT_Q1 (1'b0 ), // Initial value of Q1: 1'b0 or 1'b1
|
||||
.INIT_Q2 (1'b0 ), // Initial value of Q2: 1'b0 or 1'b1
|
||||
.SRTYPE ("ASYNC" ) // Set/Reset type: "SYNC" or "ASYNC"
|
||||
) i_rx_frame_iddr (
|
||||
.CE (1'b1 ), // 1-bit clock enable input
|
||||
.R (1'b0 ), // 1-bit reset
|
||||
.S (1'b0 ), // 1-bit set
|
||||
.C (clk_in ), // 1-bit clock input
|
||||
.D (rx_frame ), // 1-bit DDR data input
|
||||
.Q1 (rx_frame_pos ), // 1-bit output for positive edge of clock
|
||||
.Q2 (rx_frame_neg ) // 1-bit output for negative edge of clock
|
||||
);
|
||||
|
||||
// rx data
|
||||
reg [11:0] rx_fifo_i = 'b0;
|
||||
reg [11:0] rx_fifo_q = 'b0;
|
||||
|
||||
always @(posedge clk_in) begin
|
||||
if (clk_in_rst) begin
|
||||
rx_fifo_i <= 'b0;
|
||||
rx_fifo_q <= 'b0;
|
||||
end
|
||||
else begin
|
||||
if ({rx_frame_neg,rx_frame_pos} == 2'b10) begin
|
||||
rx_fifo_i <= rx_data_neg;
|
||||
rx_fifo_q <= rx_data_pos;
|
||||
end
|
||||
else begin
|
||||
rx_fifo_i <= 'd1234; // error
|
||||
rx_fifo_q <= 'd4321; // error
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// divide rx_data to dual channel
|
||||
reg rx_fifo_wr_en = 1'b0;
|
||||
reg rx_fifo_rd_en = 'b0;
|
||||
|
||||
wire rx_fifo_empty_1;
|
||||
wire rx_fifo_empty_2;
|
||||
|
||||
always @(posedge clk_in) begin
|
||||
if (clk_in_rst) begin
|
||||
rx_fifo_wr_en <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
rx_fifo_wr_en <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge rx_data_clk) begin
|
||||
if (rx_data_clk_rst) begin
|
||||
rx_fifo_rd_en <= 'b0;
|
||||
end
|
||||
else begin
|
||||
rx_fifo_rd_en <= &{~rx_fifo_empty_1, ~rx_fifo_empty_2};
|
||||
end
|
||||
end
|
||||
|
||||
ad9361_fifo u_rx_fifo_i
|
||||
(
|
||||
.rst (clk_in_rst || rx_fifo_rst ), // input wire rst
|
||||
.wr_clk (clk_in ), // input wire wr_clk
|
||||
.rd_clk (rx_data_clk ), // input wire rd_clk
|
||||
.din (rx_fifo_i ), // input wire [11 : 0] din
|
||||
.wr_en (rx_fifo_wr_en ), // input wire wr_en
|
||||
.rd_en (rx_fifo_rd_en ), // input wire rd_en
|
||||
.dout (rx_data_i ), // output wire [11 : 0] dout
|
||||
.full ( ), // output wire full
|
||||
.empty (rx_fifo_empty_1 ) // output wire empty
|
||||
);
|
||||
|
||||
ad9361_fifo u_rx_fifo_q
|
||||
(
|
||||
.rst (clk_in_rst || rx_fifo_rst ), // input wire rst
|
||||
.wr_clk (clk_in ), // input wire wr_clk
|
||||
.rd_clk (rx_data_clk ), // input wire rd_clk
|
||||
.din (rx_fifo_q ), // input wire [11 : 0] din
|
||||
.wr_en (rx_fifo_wr_en ), // input wire wr_en
|
||||
.rd_en (rx_fifo_rd_en ), // input wire rd_en
|
||||
.dout (rx_data_q ), // output wire [11 : 0] dout
|
||||
.full ( ), // output wire full
|
||||
.empty (rx_fifo_empty_2 ) // output wire empty
|
||||
);
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,193 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
// _ _ ____
|
||||
// | | ___ ___| |__ / ___| __ _ ___
|
||||
// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
|
||||
// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
|
||||
// \___/ \___/|___/_| |_| \____|\__,_|\___/
|
||||
//
|
||||
// Create Date: 2022/07/01 16:39:19
|
||||
// Last Modified Date: 2024/09/27 16:22
|
||||
// Design Name:
|
||||
// Module Name: ad9361_tx_map_cmos_dual
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module ad9361_tx_map_cmos_dual
|
||||
(
|
||||
input clk_2x_in ,
|
||||
input clk_in_rst ,
|
||||
|
||||
input tx_data_clk ,
|
||||
input tx_data_clk_rst ,
|
||||
|
||||
input [11:0] tx_ch1_i ,
|
||||
input [11:0] tx_ch1_q ,
|
||||
input [11:0] tx_ch2_i ,
|
||||
input [11:0] tx_ch2_q ,
|
||||
|
||||
output clk_out ,
|
||||
output tx_frame ,
|
||||
output [11:0] tx_data
|
||||
);
|
||||
|
||||
genvar mm;
|
||||
|
||||
// input data fifo
|
||||
reg tx_fifo_rd_en = 'b0;
|
||||
wire [11:0] tx_fifo_ch1_i;
|
||||
wire [11:0] tx_fifo_ch1_q;
|
||||
wire [11:0] tx_fifo_ch2_i;
|
||||
wire [11:0] tx_fifo_ch2_q;
|
||||
|
||||
wire rx_fifo_empty_1;
|
||||
wire rx_fifo_empty_2;
|
||||
wire rx_fifo_empty_3;
|
||||
wire rx_fifo_empty_4;
|
||||
|
||||
always @(posedge clk_2x_in) begin
|
||||
if (clk_in_rst) begin
|
||||
tx_fifo_rd_en <= 'b0;
|
||||
end
|
||||
else begin
|
||||
if (&{~rx_fifo_empty_1, ~rx_fifo_empty_2, ~rx_fifo_empty_3, ~rx_fifo_empty_4}) begin
|
||||
tx_fifo_rd_en <= ~tx_fifo_rd_en;
|
||||
end
|
||||
else begin
|
||||
tx_fifo_rd_en <= 'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
ad9361_fifo u_tx_fifo_ch1_i
|
||||
(
|
||||
.rst (clk_in_rst ), // input wire rst
|
||||
.wr_clk (tx_data_clk ), // input wire wr_clk
|
||||
.rd_clk (clk_2x_in ), // input wire rd_clk
|
||||
.din (tx_ch1_i ), // input wire [11 : 0] din
|
||||
.wr_en (1'b1 ), // input wire wr_en
|
||||
.rd_en (tx_fifo_rd_en ), // input wire rd_en
|
||||
.dout (tx_fifo_ch1_i ), // output wire [11 : 0] dout
|
||||
.full ( ), // output wire full
|
||||
.empty (rx_fifo_empty_1) // output wire empty
|
||||
);
|
||||
|
||||
ad9361_fifo u_tx_fifo_ch1_q
|
||||
(
|
||||
.rst (clk_in_rst ), // input wire rst
|
||||
.wr_clk (tx_data_clk ), // input wire wr_clk
|
||||
.rd_clk (clk_2x_in ), // input wire rd_clk
|
||||
.din (tx_ch1_q ), // input wire [11 : 0] din
|
||||
.wr_en (1'b1 ), // input wire wr_en
|
||||
.rd_en (tx_fifo_rd_en ), // input wire rd_en
|
||||
.dout (tx_fifo_ch1_q ), // output wire [11 : 0] dout
|
||||
.full ( ), // output wire full
|
||||
.empty (rx_fifo_empty_2) // output wire empty
|
||||
);
|
||||
|
||||
ad9361_fifo u_tx_fifo_ch2_i
|
||||
(
|
||||
.rst (clk_in_rst ), // input wire rst
|
||||
.wr_clk (tx_data_clk ), // input wire wr_clk
|
||||
.rd_clk (clk_2x_in ), // input wire rd_clk
|
||||
.din (tx_ch2_i ), // input wire [11 : 0] din
|
||||
.wr_en (1'b1 ), // input wire wr_en
|
||||
.rd_en (tx_fifo_rd_en ), // input wire rd_en
|
||||
.dout (tx_fifo_ch2_i ), // output wire [11 : 0] dout
|
||||
.full ( ), // output wire full
|
||||
.empty (rx_fifo_empty_3) // output wire empty
|
||||
);
|
||||
|
||||
ad9361_fifo u_tx_fifo_ch2_q
|
||||
(
|
||||
.rst (clk_in_rst ), // input wire rst
|
||||
.wr_clk (tx_data_clk ), // input wire wr_clk
|
||||
.rd_clk (clk_2x_in ), // input wire rd_clk
|
||||
.din (tx_ch2_q ), // input wire [11 : 0] din
|
||||
.wr_en (1'b1 ), // input wire wr_en
|
||||
.rd_en (tx_fifo_rd_en ), // input wire rd_en
|
||||
.dout (tx_fifo_ch2_q ), // output wire [11 : 0] dout
|
||||
.full ( ), // output wire full
|
||||
.empty (rx_fifo_empty_4) // output wire empty
|
||||
);
|
||||
|
||||
// frame and data control
|
||||
reg tx_frame_i = 'b0;
|
||||
reg tx_frame_q = 'b0;
|
||||
reg [11:0] tx_data_i = 'b0;
|
||||
reg [11:0] tx_data_q = 'b0;
|
||||
|
||||
always @(posedge clk_2x_in) begin
|
||||
if (clk_in_rst) begin
|
||||
tx_frame_i <= 'b0;
|
||||
tx_frame_q <= 'b0;
|
||||
tx_data_i <= 'b0;
|
||||
tx_data_q <= 'b0;
|
||||
end
|
||||
else if (tx_fifo_rd_en == 1'b0) begin
|
||||
tx_frame_i <= 1'b1;
|
||||
tx_frame_q <= 1'b1;
|
||||
tx_data_i <= tx_fifo_ch1_i;
|
||||
tx_data_q <= tx_fifo_ch1_q;
|
||||
end
|
||||
else begin
|
||||
tx_frame_i <= 1'b0;
|
||||
tx_frame_q <= 1'b0;
|
||||
tx_data_i <= tx_fifo_ch2_i;
|
||||
tx_data_q <= tx_fifo_ch2_q;
|
||||
end
|
||||
end
|
||||
|
||||
// output clock to port
|
||||
assign clk_out = clk_2x_in;
|
||||
|
||||
// output tx frame to port
|
||||
ODDR #(
|
||||
.DDR_CLK_EDGE ("SAME_EDGE" ),
|
||||
.INIT (1'b0 ),
|
||||
.SRTYPE ("ASYNC" )
|
||||
) u_tx_frame_oddr (
|
||||
.CE (1'b1 ),
|
||||
.R (1'b0 ),
|
||||
.S (1'b0 ),
|
||||
.C (clk_2x_in ),
|
||||
.D1 (tx_frame_i ),
|
||||
.D2 (tx_frame_q ),
|
||||
.Q (tx_frame )
|
||||
);
|
||||
|
||||
generate
|
||||
for (mm = 0; mm < 12; mm = mm + 1) begin
|
||||
|
||||
// output tx data to port
|
||||
ODDR #(
|
||||
.DDR_CLK_EDGE ("SAME_EDGE" ),
|
||||
.INIT (1'b0 ),
|
||||
.SRTYPE ("ASYNC" )
|
||||
) u_tx_data_oddr (
|
||||
.CE (1'b1 ),
|
||||
.R (1'b0 ),
|
||||
.S (1'b0 ),
|
||||
.C (clk_2x_in ),
|
||||
.D1 (tx_data_i[mm] ),
|
||||
.D2 (tx_data_q[mm] ),
|
||||
.Q (tx_data[mm] )
|
||||
);
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,119 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
// _ _ ____
|
||||
// | | ___ ___| |__ / ___| __ _ ___
|
||||
// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
|
||||
// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
|
||||
// \___/ \___/|___/_| |_| \____|\__,_|\___/
|
||||
//
|
||||
// Create Date: 2022/07/01 16:39:19
|
||||
// Design Name:
|
||||
// Module Name: ad9361_tx_mapping_single
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module ad9361_tx_map_cmos_single
|
||||
(
|
||||
input clk_in ,
|
||||
input clk_in_rst ,
|
||||
|
||||
input tx_data_clk ,
|
||||
input tx_data_clk_rst ,
|
||||
|
||||
input [11:0] tx_data_i ,
|
||||
input [11:0] tx_data_q ,
|
||||
|
||||
output clk_out ,
|
||||
output tx_frame ,
|
||||
output [11:0] tx_data
|
||||
);
|
||||
|
||||
genvar mm;
|
||||
|
||||
// inout data fifo
|
||||
wire [11:0] tx_fifo_i;
|
||||
wire [11:0] tx_fifo_q;
|
||||
|
||||
ad9361_fifo u_tx_fifo_i
|
||||
(
|
||||
.rst (clk_in_rst ), // input wire rst
|
||||
.wr_clk (tx_data_clk ), // input wire wr_clk
|
||||
.rd_clk (clk_in ), // input wire rd_clk
|
||||
.din (tx_data_i ), // input wire [11 : 0] din
|
||||
.wr_en (1'b1 ), // input wire wr_en
|
||||
.rd_en (1'b1 ), // input wire rd_en
|
||||
.dout (tx_fifo_i ), // output wire [11 : 0] dout
|
||||
.full ( ), // output wire full
|
||||
.empty ( ) // output wire empty
|
||||
);
|
||||
|
||||
ad9361_fifo u_tx_fifo_q
|
||||
(
|
||||
.rst (clk_in_rst ), // input wire rst
|
||||
.wr_clk (tx_data_clk ), // input wire wr_clk
|
||||
.rd_clk (clk_in ), // input wire rd_clk
|
||||
.din (tx_data_q ), // input wire [11 : 0] din
|
||||
.wr_en (1'b1 ), // input wire wr_en
|
||||
.rd_en (1'b1 ), // input wire rd_en
|
||||
.dout (tx_fifo_q ), // output wire [11 : 0] dout
|
||||
.full ( ), // output wire full
|
||||
.empty ( ) // output wire empty
|
||||
);
|
||||
|
||||
// frame and data control
|
||||
assign tx_frame_i = 1'b1;
|
||||
assign tx_frame_q = 1'b0;
|
||||
|
||||
// output clock to port
|
||||
assign clk_out = clk_in;
|
||||
|
||||
// output tx frame to port
|
||||
ODDR #(
|
||||
.DDR_CLK_EDGE ("SAME_EDGE" ), // "OPPOSITE_EDGE" or "SAME_EDGE"
|
||||
.INIT (1'b0 ), // Initial value of Q: 1'b0 or 1'b1
|
||||
.SRTYPE ("ASYNC" ) // Set/Reset type: "SYNC" or "ASYNC"
|
||||
) u_tx_frame_oddr (
|
||||
.CE (1'b1 ), // 1-bit clock enable input
|
||||
.R (1'b0 ), // 1-bit reset
|
||||
.S (1'b0 ), // 1-bit set
|
||||
.C (clk_in ), // 1-bit clock input
|
||||
.D1 (tx_frame_i ), // 1-bit data input (positive edge)
|
||||
.D2 (tx_frame_q ), // 1-bit data input (negative edge)
|
||||
.Q (tx_frame ) // 1-bit DDR output
|
||||
);
|
||||
|
||||
// output tx data to port
|
||||
generate
|
||||
for (mm = 0; mm < 12; mm = mm + 1) begin: tx_data_oddr
|
||||
|
||||
ODDR #(
|
||||
.DDR_CLK_EDGE ("SAME_EDGE" ), // "OPPOSITE_EDGE" or "SAME_EDGE"
|
||||
.INIT (1'b0 ), // Initial value of Q: 1'b0 or 1'b1
|
||||
.SRTYPE ("ASYNC" ) // Set/Reset type: "SYNC" or "ASYNC"
|
||||
) u_tx_data_oddr (
|
||||
.CE (1'b1 ), // 1-bit clock enable input
|
||||
.R (1'b0 ), // 1-bit reset
|
||||
.S (1'b0 ), // 1-bit set
|
||||
.C (clk_in ), // 1-bit clock input
|
||||
.D1 (tx_fifo_i[mm] ), // 1-bit data input (positive edge)
|
||||
.D2 (tx_fifo_q[mm] ), // 1-bit data input (negative edge)
|
||||
.Q (tx_data[mm] ) // 1-bit DDR output
|
||||
);
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,118 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 09/09/2024 07:43:16 PM
|
||||
// Design Name:
|
||||
// Module Name: clk_dist
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "defines.v"
|
||||
|
||||
module clk_dist
|
||||
(
|
||||
// input clocks
|
||||
input ad9361_1_rx_data_clk, // ad9361 rx data clock, 83.3333mhz
|
||||
input ad9361_2_rx_data_clk, // ad9361 rx data clock, 83.3333mhz
|
||||
|
||||
// output clocks & reset
|
||||
// pl signal processing clock
|
||||
output sys_rst , // global reset signal, active high
|
||||
output sys_clk , // 41.6667mhz
|
||||
output sys_clk_2x , // 83.3333mhz
|
||||
output sys_clk_3x , // 125mhz
|
||||
output sys_clk_4x , // 166.6667mhz
|
||||
output sys_clk_ld , // system main clock locked indicator
|
||||
|
||||
// ad9361-1 clocks
|
||||
output ad9361_1_clk , // 41.6667mhz
|
||||
output ad9361_1_clk_2x , // 83.3333mhz
|
||||
output ad9361_1_clk_3x , // 125mhz
|
||||
output ad9361_1_clk_4x , // 166.6667mhz
|
||||
output ad9361_1_clk_ld , // ad9361-1 clock group locked indicator
|
||||
|
||||
// ad9361-2 clocks
|
||||
output ad9361_2_clk , // 41.6667mhz
|
||||
output ad9361_2_clk_2x , // 83.3333mhz
|
||||
output ad9361_2_clk_3x , // 125mhz
|
||||
output ad9361_2_clk_4x , // 166.6667mhz
|
||||
output ad9361_2_clk_ld // ad9361-2 clock group locked indicator
|
||||
);
|
||||
|
||||
assign sys_clk = ad9361_1_clk ;
|
||||
assign sys_clk_2x = ad9361_1_clk_2x;
|
||||
assign sys_clk_3x = ad9361_1_clk_3x;
|
||||
assign sys_clk_4x = ad9361_1_clk_4x;
|
||||
assign sys_clk_ld = ad9361_1_clk_ld;
|
||||
|
||||
assign sys_rst = ~sys_clk_ld;
|
||||
|
||||
`ifdef AD9361_1_CMOS_2T2R // define AD9361_1_2T2R at top of system_top.v if 2t2r is required
|
||||
ad9361_clk_gen_cmos_2t2r u_ad9361_1_clk_gen
|
||||
(
|
||||
// Clock out ports
|
||||
.clk_out1 (ad9361_1_clk ), // output clk_out1
|
||||
.clk_out2 (ad9361_1_clk_2x ), // output clk_out2
|
||||
.clk_out3 (ad9361_1_clk_3x ), // output clk_out3
|
||||
.clk_out4 (ad9361_1_clk_4x ), // output clk_out4
|
||||
// Status and control signals
|
||||
.locked (ad9361_1_clk_ld ), // output locked
|
||||
// Clock in ports
|
||||
.clk_in1 (ad9361_1_rx_data_clk ) // input clk_in1
|
||||
);
|
||||
`else
|
||||
ad9361_clk_gen_cmos_1t1r u_ad9361_1_clk_gen
|
||||
(
|
||||
// Clock out ports
|
||||
.clk_out1 (ad9361_1_clk ), // output clk_out1
|
||||
.clk_out2 (ad9361_1_clk_2x ), // output clk_out2
|
||||
.clk_out3 (ad9361_1_clk_3x ), // output clk_out3
|
||||
.clk_out4 (ad9361_1_clk_4x ), // output clk_out4
|
||||
// Status and control signals
|
||||
.locked (ad9361_1_clk_ld ), // output locked
|
||||
// Clock in ports
|
||||
.clk_in1 (ad9361_1_rx_data_clk ) // input clk_in1
|
||||
);
|
||||
`endif
|
||||
|
||||
`ifdef AD9361_2_CMOS_2T2R // define AD9361_1_2T2R at top of system_top.v if 2t2r is required
|
||||
ad9361_clk_gen_cmos_2t2r u_ad9361_2_clk_gen
|
||||
(
|
||||
// Clock out ports
|
||||
.clk_out1 (ad9361_2_clk ), // output clk_out1
|
||||
.clk_out2 (ad9361_2_clk_2x ), // output clk_out2
|
||||
.clk_out3 (ad9361_2_clk_3x ), // output clk_out3
|
||||
.clk_out4 (ad9361_2_clk_4x ), // output clk_out4
|
||||
// Status and control signals
|
||||
.locked (ad9361_2_clk_ld ), // output locked
|
||||
// Clock in ports
|
||||
.clk_in1 (ad9361_2_rx_data_clk ) // input clk_in1
|
||||
);
|
||||
`else
|
||||
ad9361_clk_gen_cmos_1t1r u_ad9361_2_clk_gen
|
||||
(
|
||||
// Clock out ports
|
||||
.clk_out1 (ad9361_2_clk ), // output clk_out1
|
||||
.clk_out2 (ad9361_2_clk_2x ), // output clk_out2
|
||||
.clk_out3 (ad9361_2_clk_3x ), // output clk_out3
|
||||
.clk_out4 (ad9361_2_clk_4x ), // output clk_out4
|
||||
// Status and control signals
|
||||
.locked (ad9361_2_clk_ld ), // output locked
|
||||
// Clock in ports
|
||||
.clk_in1 (ad9361_2_rx_data_clk ) // input clk_in1
|
||||
);
|
||||
`endif
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,2 @@
|
||||
`define AD9361_1_CMOS_2T2R
|
||||
`define AD9361_2_CMOS_2T2R
|
||||
@@ -0,0 +1,616 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 09/09/2024 07:16:39 PM
|
||||
// Design Name:
|
||||
// Module Name: system_top
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "defines.v"
|
||||
|
||||
module system_top
|
||||
(
|
||||
/***************************************************************************
|
||||
* Contents
|
||||
* 01. Clocks
|
||||
* 02. AD9528 Interface
|
||||
* 03. AD9361-1 Interface
|
||||
* 04. AD9361-2 Interface
|
||||
* 05. Inter-FPGA Ports
|
||||
* 06. Inter-board Ports
|
||||
* 07. 3.3V Debug IO
|
||||
* 08. DDR and Fixed-io (Do NOT Modify)
|
||||
**************************************************************************/
|
||||
|
||||
// *************************************************************************
|
||||
// ******************************** Clocks *********************************
|
||||
// *************************************************************************
|
||||
// ad9528 clock
|
||||
input refclk_1_p , // 200MHz
|
||||
input refclk_1_n ,
|
||||
input refclk_2_p , // 200MHz
|
||||
input refclk_2_n ,
|
||||
input gtclk_109_p , // 200MHz
|
||||
input gtclk_109_n ,
|
||||
input gtclk_110_p , // 200MHz
|
||||
input gtclk_110_n ,
|
||||
input gtclk_112_p , // 200MHz
|
||||
input gtclk_112_n ,
|
||||
// ad9361 buffered clock
|
||||
input ad9361_1_buffer_clk , // derived from ad9361 input clock
|
||||
input ad9361_2_buffer_clk , // derived from ad9361 input clock
|
||||
// *************************************************************************
|
||||
// *************************** AD9528 Interface ****************************
|
||||
// *************************************************************************
|
||||
output ad9528_spi_csn ,
|
||||
output ad9528_spi_clk ,
|
||||
output ad9528_spi_mosi ,
|
||||
input ad9528_spi_miso ,
|
||||
// control signals
|
||||
input [ 1:0] ad9528_status ,
|
||||
output ad9528_reset_b ,
|
||||
output ad9528_sysref_req ,
|
||||
// *************************************************************************
|
||||
// ************************** AD9361-1 Interface ***************************
|
||||
// *************************************************************************
|
||||
// rx data (rx channels are tied to ground physically)
|
||||
input ad9361_1_rx_data_clk, // ad9361 rx data clock, 96mhz
|
||||
input ad9361_1_rx_frame ,
|
||||
input [11:0] ad9361_1_rx_data ,
|
||||
// tx data
|
||||
output ad9361_1_tx_fb_clk ,
|
||||
output ad9361_1_tx_frame ,
|
||||
output [11:0] ad9361_1_tx_data ,
|
||||
// spi interface
|
||||
output ad9361_1_spi_clk ,
|
||||
output ad9361_1_spi_csn ,
|
||||
output ad9361_1_spi_mosi ,
|
||||
input ad9361_1_spi_miso ,
|
||||
// control signals
|
||||
output ad9361_1_reset_b , // ad9361 active-low reset control
|
||||
output ad9361_1_en_agc , // ad9361 manual agc control
|
||||
output ad9361_1_enable , // ad9361 enable state machine pin control (spi control is also allowed)
|
||||
output ad9361_1_txnrx , // ad9361 enable state machine pin control (spi control is also allowed)
|
||||
input [ 3:0] ad9361_1_ctrl_in ,
|
||||
output [ 7:0] ad9361_1_ctrl_out ,
|
||||
// *************************************************************************
|
||||
// ************************** AD9361-2 Interface ***************************
|
||||
// *************************************************************************
|
||||
// rx data (rx channels are tied to ground physically)
|
||||
input ad9361_2_rx_data_clk,
|
||||
input ad9361_2_rx_frame ,
|
||||
input [11:0] ad9361_2_rx_data ,
|
||||
// tx data
|
||||
output ad9361_2_tx_fb_clk ,
|
||||
output ad9361_2_tx_frame ,
|
||||
output [11:0] ad9361_2_tx_data ,
|
||||
// spi interface
|
||||
output ad9361_2_spi_clk ,
|
||||
output ad9361_2_spi_csn ,
|
||||
output ad9361_2_spi_mosi ,
|
||||
input ad9361_2_spi_miso ,
|
||||
// control signals
|
||||
output ad9361_2_reset_b , // ad9361 active-low reset control
|
||||
output ad9361_2_en_agc , // ad9361 manual agc control
|
||||
output ad9361_2_enable , // ad9361 enable state machine pin control (spi control is also allowed)
|
||||
output ad9361_2_txnrx , // ad9361 enable state machine pin control (spi control is also allowed)
|
||||
input [ 3:0] ad9361_2_ctrl_in ,
|
||||
output [ 7:0] ad9361_2_ctrl_out ,
|
||||
// *************************************************************************
|
||||
// *************************** Inter-FPGA Ports ****************************
|
||||
// *************************************************************************
|
||||
// low speed
|
||||
inout [22:0] if_lvds_io_1_p ,
|
||||
inout [22:0] if_lvds_io_1_n ,
|
||||
inout [22:0] if_lvds_io_2_p ,
|
||||
inout [22:0] if_lvds_io_2_n ,
|
||||
// high speed
|
||||
input [ 7:0] if_gtx_rxp ,
|
||||
input [ 7:0] if_gtx_rxn ,
|
||||
// output [ 7:0] if_gtx_txp ,
|
||||
// output [ 7:0] if_gtx_txn ,
|
||||
// *************************************************************************
|
||||
// *************************** Inter-board Ports ***************************
|
||||
// *************************************************************************
|
||||
// high speed
|
||||
input [ 1:0] ib_gtx_tt2zw_p ,
|
||||
input [ 1:0] ib_gtx_tt2zw_n ,
|
||||
// output [ 1:0] ib_gtx_zw2tt_p ,
|
||||
// output [ 1:0] ib_gtx_zw2tt_n ,
|
||||
// low speed
|
||||
input rs422_tt2zw ,
|
||||
output rs422_zw2tt ,
|
||||
// *************************************************************************
|
||||
// ******************************* UTC RS422 *******************************
|
||||
// *************************************************************************
|
||||
input rs422_utc_rxd ,
|
||||
input rs422_utc_reb ,
|
||||
input rs422_utc_de ,
|
||||
output rs422_utc_txd ,
|
||||
// *************************************************************************
|
||||
// ****************************** RF Control *******************************
|
||||
// *************************************************************************
|
||||
output rf_spi_clk ,
|
||||
output rf_spi_mosi1 ,
|
||||
output rf_spi_mosi2 ,
|
||||
output rf_spi_mosi3 ,
|
||||
output rf_spi_mosi4 ,
|
||||
output rf_spi_sen ,
|
||||
input rf_spi_miso ,
|
||||
// *************************************************************************
|
||||
// ****************************** PS PJTAG *******************************
|
||||
// *************************************************************************
|
||||
input pjtag_tdi ,
|
||||
input pjtag_tms ,
|
||||
input pjtag_tck ,
|
||||
output pjtag_tdo ,
|
||||
// *************************************************************************
|
||||
// ***************************** 3.3V Debug IO *****************************
|
||||
// *************************************************************************
|
||||
// uart
|
||||
input uart_rxd ,
|
||||
output uart_txd ,
|
||||
// gpio
|
||||
inout debug_io_1 ,
|
||||
inout debug_io_2 ,
|
||||
inout debug_io_3 ,
|
||||
inout debug_io_4 ,
|
||||
inout debug_io_5 ,
|
||||
// *************************************************************************
|
||||
// ******************* DDR and Fixed-io (Do NOT Modify) ********************
|
||||
// *************************************************************************
|
||||
// ddr
|
||||
inout [14:0] ddr_addr ,
|
||||
inout [ 2:0] ddr_ba ,
|
||||
inout ddr_cas_n ,
|
||||
inout ddr_ck_n ,
|
||||
inout ddr_ck_p ,
|
||||
inout ddr_cke ,
|
||||
inout ddr_cs_n ,
|
||||
inout [ 3:0] ddr_dm ,
|
||||
inout [31:0] ddr_dq ,
|
||||
inout [ 3:0] ddr_dqs_n ,
|
||||
inout [ 3:0] ddr_dqs_p ,
|
||||
inout ddr_odt ,
|
||||
inout ddr_ras_n ,
|
||||
inout ddr_reset_n ,
|
||||
inout ddr_we_n ,
|
||||
// fixed-io
|
||||
inout fixed_io_ddr_vrn ,
|
||||
inout fixed_io_ddr_vrp ,
|
||||
inout [53:0] fixed_io_mio ,
|
||||
inout fixed_io_ps_clk ,
|
||||
inout fixed_io_ps_porb ,
|
||||
inout fixed_io_ps_srstb ,
|
||||
// system monitor
|
||||
input sysmon_vp ,
|
||||
input sysmon_vn
|
||||
);
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/////////////////////////// System Clock Generation ////////////////////////////
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// global reset
|
||||
wire sys_rst ; // global reset signal, active high
|
||||
|
||||
// pl signal processing clock (copies of ad9361-1 clocks)
|
||||
wire sys_clk ; // 48MHz 41.6667MHz
|
||||
wire sys_clk_2x ; // 96MHz 83.3333MHz
|
||||
wire sys_clk_3x ; // 144MHz 125MHz
|
||||
wire sys_clk_4x ; // 192MHz 166.6667MHz
|
||||
wire sys_clk_ld ; // system main clock locked indicator
|
||||
|
||||
// ad9361-1 clocks
|
||||
wire ad9361_1_clk ; // 48MHz 41.6667MHz
|
||||
wire ad9361_1_clk_2x ; // 96MHz 83.3333MHz
|
||||
wire ad9361_1_clk_3x ; // 144MHz 125MHz
|
||||
wire ad9361_1_clk_4x ; // 192MHz 166.6667MHz
|
||||
wire ad9361_1_clk_ld ; // ad9361-1 clock group locked indicator
|
||||
|
||||
// ad9361-2 clocks
|
||||
wire ad9361_2_clk ; // 48MHz 41.6667MHz
|
||||
wire ad9361_2_clk_2x ; // 96MHz 83.3333MHz
|
||||
wire ad9361_2_clk_3x ; // 144MHz 125MHz
|
||||
wire ad9361_2_clk_4x ; // 192MHz 166.6667MHz
|
||||
wire ad9361_2_clk_ld ; // ad9361-2 clock group locked indicator
|
||||
|
||||
clk_dist u_clk_dist
|
||||
(
|
||||
// input clocks
|
||||
.ad9361_1_rx_data_clk(ad9361_1_rx_data_clk), // ad9361 rx data clock, 83.3333mhz
|
||||
.ad9361_2_rx_data_clk(ad9361_2_rx_data_clk), // ad9361 rx data clock, 83.3333mhz
|
||||
|
||||
// output clocks & reset
|
||||
// global reset
|
||||
.sys_rst (sys_rst ), // global reset signal, active high
|
||||
|
||||
// pl signal processing clock
|
||||
.sys_clk (sys_clk ), // 48MHz 41.6667MHz
|
||||
.sys_clk_2x (sys_clk_2x ), // 96MHz 83.3333MHz
|
||||
.sys_clk_3x (sys_clk_3x ), // 144MHz 125MHz
|
||||
.sys_clk_4x (sys_clk_4x ), // 192MHz 166.6667MHz
|
||||
.sys_clk_ld (sys_clk_ld ), // system main clock locked indicator
|
||||
|
||||
// ad9361-1 clocks
|
||||
.ad9361_1_clk (ad9361_1_clk ), // 48MHz 41.6667MHz
|
||||
.ad9361_1_clk_2x (ad9361_1_clk_2x ), // 96MHz 83.3333MHz
|
||||
.ad9361_1_clk_3x (ad9361_1_clk_3x ), // 144MHz 125MHz
|
||||
.ad9361_1_clk_4x (ad9361_1_clk_4x ), // 192MHz 166.6667MHz
|
||||
.ad9361_1_clk_ld (ad9361_1_clk_ld ), // ad9361-1 clock group locked indicator
|
||||
|
||||
// ad9361-2 clocks
|
||||
.ad9361_2_clk (ad9361_2_clk ), // 48MHz 41.6667MHz
|
||||
.ad9361_2_clk_2x (ad9361_2_clk_2x ), // 96MHz 83.3333MHz
|
||||
.ad9361_2_clk_3x (ad9361_2_clk_3x ), // 144MHz 125MHz
|
||||
.ad9361_2_clk_4x (ad9361_2_clk_4x ), // 192MHz 166.6667MHz
|
||||
.ad9361_2_clk_ld (ad9361_2_clk_ld ) // ad9361-2 clock group locked indicator
|
||||
);
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
//////////////////////////// Block Design Interface ////////////////////////////
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// gpio
|
||||
wire [47:0] gpio_i;
|
||||
wire [47:0] gpio_o;
|
||||
wire [47:0] gpio_t;
|
||||
|
||||
assign gpio_i[47:36] = gpio_o[47:36];
|
||||
|
||||
// hmc7044
|
||||
assign ad9528_reset_b = gpio_o[ 0]; // ad9528 reset
|
||||
assign ad9528_sysref_req = gpio_o[ 1]; // ad9528 sysref request
|
||||
assign gpio_i[3:2] = ad9528_status;
|
||||
// ad9361-1
|
||||
assign ad9361_1_txnrx = gpio_o[ 4]; // ad9361 enable state machine control
|
||||
assign ad9361_1_enable = gpio_o[ 5]; // ad9361 enable state machine control
|
||||
assign ad9361_1_en_agc = gpio_o[ 6]; // ad9361 agc control
|
||||
assign ad9361_1_reset_b = gpio_o[ 7]; // ad9361 reset
|
||||
assign ad9361_1_ctrl_out = gpio_o[15:8];
|
||||
assign gpio_i[19:16] = ad9361_1_ctrl_in;
|
||||
// ad9361-2
|
||||
assign ad9361_2_txnrx = gpio_o[20]; // ad9361 enable state machine control
|
||||
assign ad9361_2_enable = gpio_o[21]; // ad9361 enable state machine control
|
||||
assign ad9361_2_en_agc = gpio_o[22]; // ad9361 agc control
|
||||
assign ad9361_2_reset_b = gpio_o[23]; // ad9361 reset
|
||||
assign ad9361_2_ctrl_out = gpio_o[31:24];
|
||||
assign gpio_i[35:32] = ad9361_2_ctrl_in;
|
||||
|
||||
// spi interface
|
||||
wire spi_sclk ;
|
||||
wire [ 2:0] spi_cs ;
|
||||
reg spi_sdi ;
|
||||
wire spi_sdo ;
|
||||
wire spi_sdo_t ;
|
||||
wire spi_three_wire;
|
||||
wire spi_active ;
|
||||
|
||||
// hmc7044 - three-wire spi
|
||||
assign ad9528_spi_clk = spi_sclk;
|
||||
assign ad9528_spi_csn = spi_cs[0];
|
||||
assign ad9528_spi_mosi = spi_sdo_t ? 1'bz : spi_sdo;
|
||||
// ad9361-1 - three-wire spi or four-wire spi
|
||||
assign ad9361_1_spi_clk = spi_sclk;
|
||||
assign ad9361_1_spi_csn = spi_cs[1];
|
||||
assign ad9361_1_spi_mosi = spi_sdo_t ? 1'bz : spi_sdo;
|
||||
// ad9361-2 - three-wire spi or four-wire spi
|
||||
assign ad9361_2_spi_clk = spi_sclk;
|
||||
assign ad9361_2_spi_csn = spi_cs[2];
|
||||
assign ad9361_2_spi_mosi = spi_sdo_t ? 1'bz : spi_sdo;
|
||||
// select sdi signal
|
||||
always @(*) begin
|
||||
case ({ad9528_spi_csn,ad9361_1_spi_csn,ad9361_2_spi_csn})
|
||||
3'b011 : spi_sdi = spi_three_wire ? ad9528_spi_mosi : ad9528_spi_miso;
|
||||
3'b101 : spi_sdi = spi_three_wire ? ad9361_1_spi_mosi : ad9361_1_spi_miso;
|
||||
3'b110 : spi_sdi = spi_three_wire ? ad9361_2_spi_mosi : ad9361_2_spi_miso;
|
||||
default: spi_sdi = 1'bz;
|
||||
endcase
|
||||
end
|
||||
|
||||
// ps clock
|
||||
wire ps_clk_50m;
|
||||
wire ps_clk_100m;
|
||||
|
||||
system_bd_wrapper system_bd
|
||||
(
|
||||
// ddr
|
||||
.ddr_addr (ddr_addr ), // inout [14:0]ddr_addr
|
||||
.ddr_ba (ddr_ba ), // inout [2:0]ddr_ba
|
||||
.ddr_cas_n (ddr_cas_n ), // inout ddr_cas_n
|
||||
.ddr_ck_n (ddr_ck_n ), // inout ddr_ck_n
|
||||
.ddr_ck_p (ddr_ck_p ), // inout ddr_ck_p
|
||||
.ddr_cke (ddr_cke ), // inout ddr_cke
|
||||
.ddr_cs_n (ddr_cs_n ), // inout ddr_cs_n
|
||||
.ddr_dm (ddr_dm ), // inout [3:0]ddr_dm
|
||||
.ddr_dq (ddr_dq ), // inout [31:0]ddr_dq
|
||||
.ddr_dqs_n (ddr_dqs_n ), // inout [3:0]ddr_dqs_n
|
||||
.ddr_dqs_p (ddr_dqs_p ), // inout [3:0]ddr_dqs_p
|
||||
.ddr_odt (ddr_odt ), // inout ddr_odt
|
||||
.ddr_ras_n (ddr_ras_n ), // inout ddr_ras_n
|
||||
.ddr_reset_n (ddr_reset_n ), // inout ddr_reset_n
|
||||
.ddr_we_n (ddr_we_n ), // inout ddr_we_n
|
||||
|
||||
// fixed-io
|
||||
.fixed_io_ddr_vrn (fixed_io_ddr_vrn ), // inout fixed_io_ddr_vrn
|
||||
.fixed_io_ddr_vrp (fixed_io_ddr_vrp ), // inout fixed_io_ddr_vrp
|
||||
.fixed_io_mio (fixed_io_mio ), // inout [53:0]fixed_io_mio
|
||||
.fixed_io_ps_clk (fixed_io_ps_clk ), // inout fixed_io_ps_clk
|
||||
.fixed_io_ps_porb (fixed_io_ps_porb ), // inout fixed_io_ps_porb
|
||||
.fixed_io_ps_srstb (fixed_io_ps_srstb ), // inout fixed_io_ps_srstb
|
||||
|
||||
// system monitor
|
||||
.vp_vn_v_p (sysmon_vp ), // input vp_vn_v_p
|
||||
.vp_vn_v_n (sysmon_vn ), // input vp_vn_v_n
|
||||
|
||||
// pjtag
|
||||
.pjtag_tck (pjtag_tck ), // input pjtag_tck
|
||||
.pjtag_tdi (pjtag_tdi ), // input pjtag_tdi
|
||||
.pjtag_tdo (pjtag_tdo ), // output pjtag_tdo
|
||||
.pjtag_tms (pjtag_tms ), // input pjtag_tms
|
||||
|
||||
// gpio, for control signals
|
||||
.gpio_i (gpio_i ), // input [47:0]gpio_i
|
||||
.gpio_o (gpio_o ), // output [47:0]gpio_o
|
||||
.gpio_t (gpio_t ), // output [47:0]gpio_t
|
||||
|
||||
// spi interface
|
||||
.spi_sclk (spi_sclk ), // output spi_sclk
|
||||
.spi_cs (spi_cs ), // output [2:0]spi_cs
|
||||
.spi_sdi (spi_sdi ), // input [0:0]spi_sdi
|
||||
.spi_sdo (spi_sdo ), // output spi_sdo
|
||||
.spi_sdo_t (spi_sdo_t ), // output spi_sdo_t
|
||||
.spi_three_wire (spi_three_wire ), // output spi_three_wire
|
||||
.spi_active (spi_active ), // output spi_active
|
||||
|
||||
// ps clock
|
||||
.ps_clk_50m (ps_clk_50m ), // output ps_clk_50m
|
||||
.ps_clk_100m (ps_clk_100m ) // output ps_clk_100m
|
||||
);
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
////////////////////////////////// Tx Signal ///////////////////////////////////
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// baseband signal
|
||||
wire [11:0] tx1_ch1_i, tx1_ch1_q;
|
||||
wire [11:0] tx1_ch2_i, tx1_ch2_q; // nc when 1t1r is selected
|
||||
wire [11:0] tx2_ch1_i, tx2_ch1_q;
|
||||
wire [11:0] tx2_ch2_i, tx2_ch2_q; // nc when 1t1r is selected
|
||||
|
||||
`ifdef AD9361_1_CMOS_2T2R // define AD9361_1_CMOS_2T2R at top of this file if 2t2r is required
|
||||
ad9361_tx_map_cmos_dual u_ad9361_1_tx_map
|
||||
(
|
||||
.clk_2x_in (ad9361_1_clk_2x ), // input clk_2x_in
|
||||
.clk_in_rst (~ad9361_1_clk_ld ), // input clk_in_rst
|
||||
|
||||
.tx_data_clk (sys_clk ), // input tx_data_clk
|
||||
.tx_data_clk_rst(sys_rst ), // input tx_data_clk_rst
|
||||
|
||||
.tx_ch1_i (tx1_ch1_i ), // input [11:0] tx_ch1_i
|
||||
.tx_ch1_q (tx1_ch1_q ), // input [11:0] tx_ch1_q
|
||||
.tx_ch2_i (tx1_ch2_i ), // input [11:0] tx_ch2_i
|
||||
.tx_ch2_q (tx1_ch2_q ), // input [11:0] tx_ch2_q
|
||||
.clk_out (ad9361_1_tx_fb_clk ), // output clk_out
|
||||
.tx_frame (ad9361_1_tx_frame ), // output tx_frame
|
||||
.tx_data (ad9361_1_tx_data ) // output [11:0] tx_data
|
||||
);
|
||||
`else
|
||||
ad9361_tx_map_cmos_single u_ad9361_1_tx_map
|
||||
(
|
||||
.clk_in (ad9361_1_clk ), // input clk_in
|
||||
.clk_in_rst (~ad9361_1_clk_ld ), // input clk_in_rst
|
||||
|
||||
.tx_data_clk (sys_clk ), // input tx_data_clk
|
||||
.tx_data_clk_rst(sys_rst ), // input tx_data_clk_rst
|
||||
|
||||
.tx_data_i (tx1_ch1_i ), // input [11:0] tx_data_i
|
||||
.tx_data_q (tx1_ch1_q ), // input [11:0] tx_data_q
|
||||
.clk_out (ad9361_1_tx_fb_clk ), // output clk_out
|
||||
.tx_frame (ad9361_1_tx_frame ), // output tx_frame
|
||||
.tx_data (ad9361_1_tx_data ) // output [11:0] tx_data
|
||||
);
|
||||
`endif
|
||||
|
||||
`ifdef AD9361_2_CMOS_2T2R // define AD9361_2_CMOS_2T2R at top of this file if 2t2r is required
|
||||
ad9361_tx_map_cmos_dual u_ad9361_2_tx_map
|
||||
(
|
||||
.clk_2x_in (ad9361_2_clk_2x ), // input clk_2x_in
|
||||
.clk_in_rst (~ad9361_2_clk_ld ), // input clk_in_rst
|
||||
|
||||
.tx_data_clk (sys_clk ), // input tx_data_clk
|
||||
.tx_data_clk_rst(sys_rst ), // input tx_data_clk_rst
|
||||
|
||||
.tx_ch1_i (tx2_ch1_i ), // input [11:0] tx_ch1_i
|
||||
.tx_ch1_q (tx2_ch1_q ), // input [11:0] tx_ch1_q
|
||||
.tx_ch2_i (tx2_ch2_i ), // input [11:0] tx_ch2_i
|
||||
.tx_ch2_q (tx2_ch2_q ), // input [11:0] tx_ch2_q
|
||||
.clk_out (ad9361_2_tx_fb_clk ), // output clk_out
|
||||
.tx_frame (ad9361_2_tx_frame ), // output tx_frame
|
||||
.tx_data (ad9361_2_tx_data ) // output [11:0] tx_data
|
||||
);
|
||||
`else
|
||||
ad9361_tx_map_cmos_single u_ad9361_2_tx_map
|
||||
(
|
||||
.clk_in (ad9361_2_clk ), // input clk_in
|
||||
.clk_in_rst (~ad9361_2_clk_ld ), // input clk_in_rst
|
||||
|
||||
.tx_data_clk (sys_clk ), // input tx_data_clk
|
||||
.tx_data_clk_rst(sys_rst ), // input tx_data_clk_rst
|
||||
|
||||
.tx_data_i (tx2_ch1_i ), // input [11:0] tx_data_i
|
||||
.tx_data_q (tx2_ch1_q ), // input [11:0] tx_data_q
|
||||
.clk_out (ad9361_2_tx_fb_clk ), // output clk_out
|
||||
.tx_frame (ad9361_2_tx_frame ), // output tx_frame
|
||||
.tx_data (ad9361_2_tx_data ) // output [11:0] tx_data
|
||||
);
|
||||
`endif
|
||||
|
||||
// <--------------------------------------------------------------------------->
|
||||
// <--------------------- insert transmitter logic below ---------------------->
|
||||
// <--------------------------------------------------------------------------->
|
||||
wire [11:0] tx_data_i, tx_data_q;
|
||||
wire [ 1:0] waveform_sel;
|
||||
wire sweep_on ;
|
||||
wire [31:0] freq_set ;
|
||||
wire [ 1:0] iq_sel ;
|
||||
wire [ 3:0] bb_rshift ;
|
||||
|
||||
// ad9361-1
|
||||
assign tx1_ch1_i = tx_data_i;
|
||||
assign tx1_ch1_q = tx_data_q;
|
||||
assign tx1_ch2_i = tx_data_i;
|
||||
assign tx1_ch2_q = tx_data_q;
|
||||
// ad9361-2
|
||||
assign tx2_ch1_i = tx_data_i;
|
||||
assign tx2_ch1_q = tx_data_q;
|
||||
assign tx2_ch2_i = tx_data_i;
|
||||
assign tx2_ch2_q = tx_data_q;
|
||||
|
||||
tx_qpsk #(
|
||||
.BIT_DATA (1024'b0000000100100010000011001001101000010010101000011110101110101101101100000000110000011011001100001010110101110001101111110001000111100111101101101000000010100001011010101000111110111100100101100000100110010001010001101101110000001111000111011111110010000110001011011101000011010101100111100101101100100000100010010011000000101100010100111011001110001011111101010001011101101011000011001101101010000011101001111010011010100100111000001111100111001101111010001010101101111100001001110100011101011111011010010000100001010010101100011100111111101100001000110100111001001111000011011101100011000111101111101001001010000001101000110010111010010110100010001011001101001010010001100001110110111100000101110010101110011101110111001100111010101110111101100101000100110110001000011100101111100101001100110010101010011111100110001101011110011010110100110001001011100001011110101010101111111101000001010100101111000101011110111010100110111001000111000111111111100000001110000111111011100010011111000110011111010110010110010010010000000001),
|
||||
.BIT_DATA_LEN (1024),
|
||||
.CLK_FREQ (48000000)
|
||||
) u_tx_qpsk
|
||||
(
|
||||
.clk (sys_clk ), // input clk
|
||||
.rst (sys_rst ), // input rst
|
||||
.tx_data_i (tx_data_i ), // output [11:0] tx_data_i
|
||||
.tx_data_q (tx_data_q ), // output [11:0] tx_data_q
|
||||
// debug ports
|
||||
.waveform_sel (waveform_sel[1:0] ), // input [ 1:0] waveform_sel
|
||||
.sweep_on (sweep_on ), // input sweep_on
|
||||
.freq_set (freq_set ), // input [31:0] freq_set
|
||||
.iq_sel (iq_sel ), // input [ 1:0] iq_sel
|
||||
.bb_rshift (bb_rshift ) // input [ 3:0] bb_rshift
|
||||
);
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
////////////////////////////////// Rx Signals //////////////////////////////////
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
wire [11:0] rx1_ch1_i, rx1_ch1_q;
|
||||
wire [11:0] rx1_ch2_i, rx1_ch2_q; // nc when 1t1r is selected
|
||||
wire [11:0] rx2_ch1_i, rx2_ch1_q;
|
||||
wire [11:0] rx2_ch2_i, rx2_ch2_q; // nc when 1t1r is selected
|
||||
|
||||
`ifdef AD9361_1_CMOS_2T2R // define AD9361_1_CMOS_2T2R at top of this file if 2t2r is required
|
||||
ad9361_rx_map_cmos_dual u_ad9361_1_rx_map
|
||||
(
|
||||
.clk_2x_in (ad9361_1_clk_2x ), // input clk_2x_in
|
||||
.clk_in_rst (~ad9361_1_clk_ld ), // input clk_in_rst
|
||||
|
||||
.rx_data_clk (sys_clk ), // input rx_data_clk
|
||||
.rx_data_clk_rst(sys_rst ), // input rx_data_clk_rst
|
||||
|
||||
.rx_fifo_rst (1'b0 ), // input rx_fifo_rst
|
||||
|
||||
.rx_frame (ad9361_1_rx_frame ), // input rx_frame
|
||||
.rx_data (ad9361_1_rx_data ), // input [11:0] rx_data
|
||||
.rx_ch1_i (rx1_ch1_i ), // output [11:0] rx_ch1_i
|
||||
.rx_ch1_q (rx1_ch1_q ), // output [11:0] rx_ch1_q
|
||||
.rx_ch2_i (rx1_ch2_i ), // output [11:0] rx_ch2_i
|
||||
.rx_ch2_q (rx1_ch2_q ) // output [11:0] rx_ch2_q
|
||||
);
|
||||
`else
|
||||
ad9361_rx_map_cmos_single u_ad9361_1_rx_map
|
||||
(
|
||||
.clk_in (ad9361_1_clk ), // input clk_in
|
||||
.clk_in_rst (~ad9361_1_clk_ld ), // input clk_in_rst
|
||||
|
||||
.rx_data_clk (sys_clk ), // input rx_data_clk
|
||||
.rx_data_clk_rst(sys_rst ), // input rx_data_clk_rst
|
||||
|
||||
.rx_fifo_rst (1'b0 ), // input rx_fifo_rst
|
||||
|
||||
.rx_frame (ad9361_1_rx_frame ), // input rx_frame
|
||||
.rx_data (ad9361_1_rx_data ), // input [11:0] rx_data
|
||||
.rx_data_i (rx1_ch1_i ), // output [11:0] rx_data_i
|
||||
.rx_data_q (rx1_ch1_q ) // output [11:0] rx_data_q
|
||||
);
|
||||
`endif
|
||||
|
||||
`ifdef AD9361_2_CMOS_2T2R // define AD9361_2_CMOS_2T2R at top of this file if 2t2r is required
|
||||
ad9361_rx_map_cmos_dual u_ad9361_2_rx_map
|
||||
(
|
||||
.clk_2x_in (ad9361_2_clk_2x ), // input clk_2x_in
|
||||
.clk_in_rst (~ad9361_2_clk_ld ), // input clk_in_rst
|
||||
|
||||
.rx_data_clk (sys_clk ), // input rx_data_clk
|
||||
.rx_data_clk_rst(sys_rst ), // input rx_data_clk_rst
|
||||
|
||||
.rx_fifo_rst (1'b0 ), // input rx_fifo_rst
|
||||
|
||||
.rx_frame (ad9361_2_rx_frame ), // input rx_frame
|
||||
.rx_data (ad9361_2_rx_data ), // input [11:0] rx_data
|
||||
.rx_ch1_i (rx2_ch1_i ), // output [11:0] rx_ch1_i
|
||||
.rx_ch1_q (rx2_ch1_q ), // output [11:0] rx_ch1_q
|
||||
.rx_ch2_i (rx2_ch2_i ), // output [11:0] rx_ch2_i
|
||||
.rx_ch2_q (rx2_ch2_q ) // output [11:0] rx_ch2_q
|
||||
);
|
||||
`else
|
||||
ad9361_rx_map_cmos_single u_ad9361_2_rx_map
|
||||
(
|
||||
.clk_in (ad9361_2_clk ), // input clk_in
|
||||
.clk_in_rst (~ad9361_2_clk_ld ), // input clk_in_rst
|
||||
|
||||
.rx_data_clk (sys_clk ), // input rx_data_clk
|
||||
.rx_data_clk_rst(sys_rst ), // input rx_data_clk_rst
|
||||
|
||||
.rx_fifo_rst (1'b0 ), // input rx_fifo_rst
|
||||
|
||||
.rx_frame (ad9361_2_rx_frame ), // input rx_frame
|
||||
.rx_data (ad9361_2_rx_data ), // input [11:0] rx_data
|
||||
.rx_data_i (rx2_ch1_i ), // output [11:0] rx_data_i
|
||||
.rx_data_q (rx2_ch1_q ) // output [11:0] rx_data_q
|
||||
);
|
||||
`endif
|
||||
|
||||
// <--------------------------------------------------------------------------->
|
||||
// <----------------------- insert receiver logic below ----------------------->
|
||||
// <--------------------------------------------------------------------------->
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
//////////////////////////////// ILAs and VIOs /////////////////////////////////
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
ila_trx u_ila_trx
|
||||
(
|
||||
.clk (sys_clk ), // input wire clk
|
||||
.probe0 (tx_data_i ), // input wire [11:0] probe0
|
||||
.probe1 (tx_data_q ), // input wire [11:0] probe1
|
||||
.probe2 (rx1_ch1_i ), // input wire [11:0] probe2
|
||||
.probe3 (rx1_ch1_q ), // input wire [11:0] probe3
|
||||
.probe4 (rx1_ch2_i ), // input wire [11:0] probe4
|
||||
.probe5 (rx1_ch2_q ), // input wire [11:0] probe5
|
||||
.probe6 (rx2_ch1_i ), // input wire [11:0] probe6
|
||||
.probe7 (rx2_ch1_q ), // input wire [11:0] probe7
|
||||
.probe8 (rx2_ch2_i ), // input wire [11:0] probe8
|
||||
.probe9 (rx2_ch2_q ) // input wire [11:0] probe9
|
||||
);
|
||||
|
||||
vio_manual_ctrl u_vio_manual_ctrl
|
||||
(
|
||||
.clk (sys_clk ), // input wire clk
|
||||
.probe_out0 (waveform_sel[1:0] ), // output wire [1 : 0] probe_out0
|
||||
.probe_out1 (sweep_on ), // output wire [0 : 0] probe_out1
|
||||
.probe_out2 (freq_set[31:0] ), // output wire [31 : 0] probe_out2
|
||||
.probe_out3 (iq_sel[1:0] ), // output wire [1 : 0] probe_out3
|
||||
.probe_out4 (bb_rshift[3:0] ) // output wire [3 : 0] probe_out4
|
||||
);
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,539 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
// _ _ ____
|
||||
// | | ___ ___| |__ / ___| __ _ ___
|
||||
// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
|
||||
// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
|
||||
// \___/ \___/|___/_| |_| \____|\__,_|\___/
|
||||
//
|
||||
// Create Date: 2022/03/23 20:17:56
|
||||
// Last Modified Date: 2023/03/10 15:41
|
||||
// Design Name:
|
||||
// Module Name: tx_qpsk
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// 20230228-1541 - 修改不扫频、无基带频偏时 [baseband_i/q] 的数据输出，原来从
|
||||
// 乘法器引出，会导致频率为 0 时输出数据错误，现在直接从基带数据引出。
|
||||
// 20230310-1542 - 增加输入参数，发送数据更改为直接由参数输入，发送方波改为 8
|
||||
// 倍过采样，发送双音信号中 1MHz 信号的频率控制字可以根据参数中的时钟频率计
|
||||
// 算得出。
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module tx_qpsk
|
||||
#(
|
||||
parameter DATA_WIDTH = 12, // need to be <= 16
|
||||
parameter BIT_DATA = 128'b00000011000010100011110010001011001110101001111101000011100010010011011010110111101100011010010111011100110010101011111110000001, // inverse pseudorandom bit sequence, [0,flip(PRSB7)]
|
||||
parameter BIT_DATA_LEN = 128,
|
||||
parameter SQUARE_INTERP = 8,
|
||||
parameter CLK_FREQ = 245760000 // in Hertz
|
||||
)
|
||||
(
|
||||
input clk ,
|
||||
input rst ,
|
||||
output [DATA_WIDTH-1:0] tx_data_i ,
|
||||
output [DATA_WIDTH-1:0] tx_data_q ,
|
||||
// debug ports
|
||||
input [ 1:0] waveform_sel ,
|
||||
input sweep_on ,
|
||||
input [31:0] freq_set ,
|
||||
input [ 1:0] iq_sel ,
|
||||
input [ 3:0] bb_rshift
|
||||
);
|
||||
|
||||
localparam RCOS_INTERP = 64;
|
||||
localparam INTERP = (RCOS_INTERP > SQUARE_INTERP) ? RCOS_INTERP : SQUARE_INTERP;
|
||||
localparam FREQ_WORD_1M = 64'd2**64'd32*64'd1000000/CLK_FREQ;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
///////////////////////////////// Data Counter /////////////////////////////////
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// symbol & interpolation counter
|
||||
reg [$clog2(INTERP*BIT_DATA_LEN)-1 : 0] cnt = 'b0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
cnt <= 'b0;
|
||||
end
|
||||
else begin
|
||||
cnt <= (cnt == INTERP*BIT_DATA_LEN - 1) ? 'b0 : cnt + 16'b1;
|
||||
end
|
||||
end
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
////////////////////// Root-Rasied Cosine Shaping Filter ///////////////////////
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// address
|
||||
reg [$clog2(BIT_DATA_LEN)-1 : 0] hrc_data_addr_i = 'b0;
|
||||
reg [$clog2(BIT_DATA_LEN)-1 : 0] hrc_data_addr_q = 'b1;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
hrc_data_addr_i <= 'b0;
|
||||
hrc_data_addr_q <= 'b1;
|
||||
end
|
||||
else begin
|
||||
hrc_data_addr_i <= {cnt[$clog2(RCOS_INTERP) +: ($clog2(BIT_DATA_LEN)-1)],1'b0};
|
||||
hrc_data_addr_q <= {cnt[$clog2(RCOS_INTERP) +: ($clog2(BIT_DATA_LEN)-1)],1'b1};
|
||||
end
|
||||
end
|
||||
|
||||
// bit data
|
||||
reg hrc_data_i = 'b0;
|
||||
reg hrc_data_q = 'b0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
hrc_data_i <= 'b0;
|
||||
hrc_data_q <= 'b0;
|
||||
end
|
||||
else begin
|
||||
hrc_data_i <= BIT_DATA[hrc_data_addr_i];
|
||||
hrc_data_q <= BIT_DATA[hrc_data_addr_q];
|
||||
end
|
||||
end
|
||||
|
||||
// polarization
|
||||
wire [ 7:0] hrc_data_polar_i;
|
||||
wire [ 7:0] hrc_data_polar_q;
|
||||
|
||||
assign hrc_data_polar_i = {{7{hrc_data_i}},1'b1};
|
||||
assign hrc_data_polar_q = {{7{hrc_data_q}},1'b1};
|
||||
|
||||
// root raised cosine shaping-filter
|
||||
wire [23:0] hrc_wave_i;
|
||||
wire [23:0] hrc_wave_q;
|
||||
|
||||
hrc_64_12_025 u_hrc_i (
|
||||
.aclk (clk ), // input wire aclk
|
||||
.s_axis_data_tvalid (~rst ), // input wire s_axis_data_tvalid
|
||||
.s_axis_data_tready ( ), // output wire s_axis_data_tready
|
||||
.s_axis_data_tdata (hrc_data_polar_i ), // input wire [7 : 0] s_axis_data_tdata
|
||||
.m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid
|
||||
.m_axis_data_tdata (hrc_wave_i ) // output wire [23 : 0] m_axis_data_tdata
|
||||
);
|
||||
|
||||
hrc_64_12_025 u_hrc_q (
|
||||
.aclk (clk ), // input wire aclk
|
||||
.s_axis_data_tvalid (~rst ), // input wire s_axis_data_tvalid
|
||||
.s_axis_data_tready ( ), // output wire s_axis_data_tready
|
||||
.s_axis_data_tdata (hrc_data_polar_q ), // input wire [7 : 0] s_axis_data_tdata
|
||||
.m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid
|
||||
.m_axis_data_tdata (hrc_wave_q ) // output wire [23 : 0] m_axis_data_tdata
|
||||
);
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
//////////////////////////// Square Shaping Filter /////////////////////////////
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// address
|
||||
reg [$clog2(BIT_DATA_LEN)-1 : 0] hsq_data_addr = 'b0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
hsq_data_addr <= 'b0;
|
||||
end
|
||||
else
|
||||
hsq_data_addr <= {cnt[$clog2(SQUARE_INTERP) +: $clog2(BIT_DATA_LEN)]};
|
||||
end
|
||||
|
||||
// bit data
|
||||
reg hsq_data = 'b0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
hsq_data <= 'b0;
|
||||
end
|
||||
else begin
|
||||
hsq_data <= BIT_DATA[hsq_data_addr];
|
||||
end
|
||||
end
|
||||
|
||||
// square shaping-filter
|
||||
reg [17:0] hsq_wave_i ='b0;
|
||||
reg [17:0] hsq_wave_q ='b0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
hsq_wave_i <= 'b0;
|
||||
hsq_wave_q <= 'b0;
|
||||
end
|
||||
else begin
|
||||
hsq_wave_i <= hsq_data ? 18'b01_1111_1111_1111_1111 : 18'b10_0000_0000_0000_0001;
|
||||
hsq_wave_q <= hsq_data ? 18'b10_0000_0000_0000_0001 : 18'b01_1111_1111_1111_1111;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/////////////////////////////// Two Tone Siganl ////////////////////////////////
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// cosine wave with freq of 1 MHz
|
||||
wire signed [7:0] cos_1m;
|
||||
wire signed [7:0] sin_1m;
|
||||
|
||||
dds_32b_8b u_dds_1m
|
||||
(
|
||||
.aclk (clk ), // input wire aclk
|
||||
.s_axis_config_tvalid (1'b1 ), // input wire s_axis_config_tvalid
|
||||
.s_axis_config_tdata (FREQ_WORD_1M[31:0] ), // input wire [31 : 0] s_axis_config_tdata
|
||||
.m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid
|
||||
.m_axis_data_tdata ({sin_1m,cos_1m} ) // output wire [15 : 0] m_axis_data_tdata
|
||||
);
|
||||
|
||||
// two-tone signal
|
||||
reg signed [16:0] two_tone_wave_i = 'b0;
|
||||
reg signed [16:0] two_tone_wave_q = 'b0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
two_tone_wave_i <= 'b0;
|
||||
two_tone_wave_q <= 'b0;
|
||||
end
|
||||
else begin
|
||||
two_tone_wave_i <= 17'b0_0111_1111_1111_1111 + {cos_1m[7],cos_1m,8'd0};
|
||||
two_tone_wave_q <= 17'b0 + {sin_1m[7],sin_1m,8'd0};
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
///////////////////// Waveform Selection & Hopping Control /////////////////////
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// baseband signal select
|
||||
reg [17:0] baseband_sel_i = 'b0;
|
||||
reg [17:0] baseband_sel_q = 'b0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
baseband_sel_i <= 'b0;
|
||||
baseband_sel_q <= 'b0;
|
||||
end
|
||||
else begin
|
||||
case (waveform_sel[1:0])
|
||||
2'd0: begin
|
||||
baseband_sel_i <= {hrc_wave_i[16:0],1'b0};
|
||||
baseband_sel_q <= {hrc_wave_q[16:0],1'b0};
|
||||
end
|
||||
2'd1: begin
|
||||
baseband_sel_i <= hsq_wave_i[17:0];
|
||||
baseband_sel_q <= hsq_wave_q[17:0];
|
||||
end
|
||||
2'd2: begin
|
||||
baseband_sel_i <= 18'b01_1111_1111_1111_1111;
|
||||
baseband_sel_q <= 18'b0;
|
||||
end
|
||||
2'd3: begin
|
||||
baseband_sel_i <= {two_tone_wave_i[16:0],1'b0};
|
||||
baseband_sel_q <= {two_tone_wave_q[16:0],1'b0};
|
||||
end
|
||||
default: begin
|
||||
baseband_sel_i <= {hrc_wave_i[16:0],1'b0};
|
||||
baseband_sel_q <= {hrc_wave_q[16:0],1'b0};
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
// hopping control, 3750hop/s
|
||||
reg [23:0] sweep_rom_addr = 'b0;
|
||||
wire [31:0] freq_sweep;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
sweep_rom_addr <= 'b0;
|
||||
end
|
||||
else if (sweep_on) begin
|
||||
sweep_rom_addr <= sweep_rom_addr + 24'b1;
|
||||
end
|
||||
else begin
|
||||
sweep_rom_addr <= 'b0;
|
||||
end
|
||||
end
|
||||
|
||||
hop_rom u_sweep_rom
|
||||
(
|
||||
.clka (clk ), // input wire clka
|
||||
.addra (sweep_rom_addr[23:16] ), // input wire [7 : 0] addra
|
||||
.douta (freq_sweep ) // output wire [31 : 0] douta
|
||||
);
|
||||
|
||||
// choose the actual frequency word
|
||||
reg [31:0] freq_word = 'b0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
freq_word <= 'b0;
|
||||
end
|
||||
else if (sweep_on) begin
|
||||
// frequency sweep
|
||||
freq_word <= freq_sweep;
|
||||
end
|
||||
else begin
|
||||
// normal operation
|
||||
freq_word <= freq_set;
|
||||
end
|
||||
end
|
||||
|
||||
// baseband frequency shift carrier generation
|
||||
wire [ 7:0] cos_dds;
|
||||
wire [ 7:0] sin_dds;
|
||||
reg [ 7:0] cos = 'b0;
|
||||
reg [ 7:0] sin = 'b0;
|
||||
|
||||
dds_32b_8b u_dds_bb_shift (
|
||||
.aclk (clk ), // input wire aclk
|
||||
.s_axis_config_tvalid (~rst ), // input wire s_axis_config_tvalid
|
||||
.s_axis_config_tdata (freq_word ), // input wire [31 : 0] s_axis_config_tdata
|
||||
.m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid
|
||||
.m_axis_data_tdata ({sin_dds,cos_dds}) // output wire [31 : 0] m_axis_data_tdata
|
||||
);
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
cos <= 'b0;
|
||||
sin <= 'b0;
|
||||
end
|
||||
else if (freq_word == 'b0) begin
|
||||
// to make sure the carriers stay at the right position when freq = 0
|
||||
cos <= 8'b0111_1111;
|
||||
sin <= 8'b0111_1111;
|
||||
end
|
||||
else begin
|
||||
cos <= cos_dds;
|
||||
sin <= sin_dds;
|
||||
end
|
||||
end
|
||||
|
||||
// baseband frequency shift modulation
|
||||
wire [47:0] mod_cmpy_a;
|
||||
wire [15:0] mod_cmpy_b;
|
||||
wire [63:0] mod_cmpy_out;
|
||||
|
||||
wire [26:0] baseband_mult_i;
|
||||
wire [26:0] baseband_mult_q;
|
||||
|
||||
assign mod_cmpy_a = {6'b0,baseband_sel_q,6'b0,baseband_sel_i};
|
||||
assign mod_cmpy_b = {-sin,cos};
|
||||
|
||||
assign baseband_mult_i = mod_cmpy_out[58:32];
|
||||
assign baseband_mult_q = mod_cmpy_out[26: 0];
|
||||
|
||||
cmpy_18x8 u_cmpy_18x8
|
||||
(
|
||||
.aclk (clk ), // input wire aclk
|
||||
.s_axis_a_tvalid (1'b1 ), // input wire s_axis_a_tvalid
|
||||
.s_axis_a_tdata (mod_cmpy_a ), // input wire [47 : 0] s_axis_a_tdata
|
||||
.s_axis_b_tvalid (1'b1 ), // input wire s_axis_b_tvalid
|
||||
.s_axis_b_tdata (mod_cmpy_b ), // input wire [15 : 0] s_axis_b_tdata
|
||||
.m_axis_dout_tvalid ( ), // output wire m_axis_dout_tvalid
|
||||
.m_axis_dout_tdata (mod_cmpy_out ) // output wire [63 : 0] m_axis_dout_tdata
|
||||
);
|
||||
|
||||
// truncate to 16-bit
|
||||
reg signed [15:0] baseband_i = 'b0;
|
||||
reg signed [15:0] baseband_q = 'b0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
baseband_i <= 'b0;
|
||||
baseband_q <= 'b0;
|
||||
end
|
||||
else begin
|
||||
case (waveform_sel[1:0])
|
||||
2'd0: begin
|
||||
// scale rasied-cosine-shaped bpsk signal by 1.125 or 1.625
|
||||
baseband_i <= (sweep_on == 0 && freq_set == 0) ? (baseband_sel_i[17 -: 16] + {{3{baseband_sel_i[17]}},baseband_sel_i[17 -: 13]}) : (baseband_mult_i[25:10] + {baseband_mult_i[25],baseband_mult_i[25:11]} + {{3{baseband_mult_i[25]}},baseband_mult_i[25:13]});
|
||||
baseband_q <= (sweep_on == 0 && freq_set == 0) ? (baseband_sel_q[17 -: 16] + {{3{baseband_sel_q[17]}},baseband_sel_q[17 -: 13]}) : (baseband_mult_q[25:10] + {baseband_mult_q[25],baseband_mult_q[25:11]} + {{3{baseband_mult_q[25]}},baseband_mult_q[25:13]});
|
||||
end
|
||||
2'd1: begin
|
||||
baseband_i <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_i[17 -: 16] : (baseband_mult_i[25:10] + {{2{baseband_mult_i[25]}},baseband_mult_i[25:12]});
|
||||
baseband_q <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_q[17 -: 16] : (baseband_mult_q[25:10] + {{2{baseband_mult_q[25]}},baseband_mult_q[25:12]});
|
||||
end
|
||||
2'd2: begin
|
||||
baseband_i <= baseband_mult_i[24:9];
|
||||
baseband_q <= baseband_mult_q[24:9];
|
||||
end
|
||||
2'd3: begin
|
||||
baseband_i <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_i[17 -: 16] : baseband_mult_i[24:9];
|
||||
baseband_q <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_q[17 -: 16] : baseband_mult_q[24:9];
|
||||
end
|
||||
default: begin
|
||||
// scale rasied-cosine-shaped bpsk signal by 1.125
|
||||
baseband_i <= baseband_mult_i[25:10] + {{3{baseband_mult_i[25]}},baseband_mult_i[25:13]};
|
||||
baseband_q <= baseband_mult_q[25:10] + {{3{baseband_mult_q[25]}},baseband_mult_q[25:13]};
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
// iq selection & baseband right shift
|
||||
reg signed [15:0] baseband_data_i = 'b0;
|
||||
reg signed [15:0] baseband_data_q = 'b0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
baseband_data_i <= 'b0;
|
||||
baseband_data_q <= 'b0;
|
||||
end
|
||||
else begin
|
||||
// inphase selection
|
||||
if (iq_sel[1]) begin
|
||||
baseband_data_i <= baseband_i >>> bb_rshift;
|
||||
end
|
||||
else begin
|
||||
baseband_data_i <= 'b0;
|
||||
end
|
||||
// quadrature selection
|
||||
if (iq_sel[0]) begin
|
||||
baseband_data_q <= baseband_q >>> bb_rshift;
|
||||
end
|
||||
else begin
|
||||
baseband_data_q <= 'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// output data to ports
|
||||
assign tx_data_i = baseband_data_i[15 -: DATA_WIDTH];
|
||||
assign tx_data_q = baseband_data_q[15 -: DATA_WIDTH];
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2020/12/08 12:43:46
|
||||
// Design Name:
|
||||
// Module Name: tb_tx_qpsk
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
// module tb_tx_qpsk;
|
||||
|
||||
// reg clk = 1'b0 ;
|
||||
// reg rst = 1'b1 ;
|
||||
// reg tx_on = 1'b1 ;
|
||||
// reg [31:0] freq_set ;
|
||||
// reg [ 1:0] waveform_sel = 2'b00;
|
||||
// reg [ 1:0] iq_sel = 2'b11 ;
|
||||
// wire [11:0] tx_data_i ;
|
||||
// wire [11:0] tx_data_q ;
|
||||
// reg [ 3:0] bb_rshift = 5'b0 ;
|
||||
|
||||
// tx_qpsk u_tx_qpsk
|
||||
// (
|
||||
// .clk (clk ),
|
||||
// .rst (rst ),
|
||||
// .tx_data_i (tx_data_i ),
|
||||
// .tx_data_q (tx_data_q ),
|
||||
// .waveform_sel (waveform_sel ),
|
||||
// .sweep_on (1'b0 ),
|
||||
// // .freq_set (32'd447392426 ),
|
||||
// .freq_set (32'd0 ),
|
||||
// .iq_sel (iq_sel ),
|
||||
// .bb_rshift (bb_rshift )
|
||||
// );
|
||||
|
||||
// initial begin
|
||||
// #102
|
||||
// rst = 1'b0;
|
||||
// // freq_set = 32'd873813333;
|
||||
// // waveform_sel = 2'b00;
|
||||
// // bb_rshift = 5'd0;
|
||||
// // #5000
|
||||
// // bb_rshift = 5'd1;
|
||||
// // #5000
|
||||
// // bb_rshift = 5'd2;
|
||||
// // #5000
|
||||
// // bb_rshift = 5'd3;
|
||||
// // #5000
|
||||
// // bb_rshift = 5'd4;
|
||||
// // #5000
|
||||
// // bb_rshift = 5'd5;
|
||||
// // #5000
|
||||
// // bb_rshift = 5'd6;
|
||||
// // #5000
|
||||
// // bb_rshift = 5'd7;
|
||||
// // #5000
|
||||
// // bb_rshift = 5'd8;
|
||||
// // #5000
|
||||
// // bb_rshift = 5'd9;
|
||||
// // #5000
|
||||
// // bb_rshift = 5'd14;
|
||||
// // #5000
|
||||
// // bb_rshift = 5'd15;
|
||||
// // #5000
|
||||
// // bb_rshift = 5'd16;
|
||||
// // freq_set = 32'd0;
|
||||
// // func_sel = 3'b010;
|
||||
// // #7777
|
||||
// // freq_set = 32'd536870912;
|
||||
// // func_sel = 3'b100;
|
||||
// // #7777
|
||||
// // freq_set = 32'd0;
|
||||
// // func_sel = 3'b100;
|
||||
// // #7777
|
||||
// // freq_set = 32'd536870912;
|
||||
// // func_sel = 3'b010;
|
||||
// // #7777
|
||||
// // freq_set = 32'd0;
|
||||
// // func_sel = 3'b010;
|
||||
// // freq_set = 32'd536870912;
|
||||
// // iq_sel = 2'b00;
|
||||
// // #7777
|
||||
// // freq_set = 32'd536870912;
|
||||
// // iq_sel = 2'b01;
|
||||
// // #7777
|
||||
// // freq_set = 32'd536870912;
|
||||
// // iq_sel = 2'b10;
|
||||
// // #7777
|
||||
// // freq_set = 32'd536870912;
|
||||
// // iq_sel = 2'b11;
|
||||
// end
|
||||
|
||||
// always #5 clk = ~clk;
|
||||
|
||||
// // integer i;
|
||||
// // integer w_file;
|
||||
|
||||
// // initial begin
|
||||
// // w_file = $fopen("D:\\qpsk_josh.txt","w");
|
||||
// // for (i = 0; i <= 35000; i = i + 1) begin
|
||||
// // wait(clk);
|
||||
// // #10;
|
||||
// // $fdisplay(w_file,"%d %d",$signed(tx_data_i),
|
||||
// // $signed(tx_data_q));
|
||||
// // if (i == 35000) begin
|
||||
// // $fclose(w_file);
|
||||
// // $stop;
|
||||
// // end
|
||||
// // end
|
||||
// // end
|
||||
|
||||
// endmodule
|
||||
@@ -0,0 +1,926 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2024.1.2 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
|
||||
<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Workspace/vivado/brd_hsjl_hy/sjl_basic/sjl_basic.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="3d0121d054e243e1843e529aca7f88ab"/>
|
||||
<Option Name="Part" Val="xc7z100ffg900-2"/>
|
||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||
<Option Name="SimulatorInstallDirModelSim" Val=""/>
|
||||
<Option Name="SimulatorInstallDirQuesta" Val=""/>
|
||||
<Option Name="SimulatorInstallDirXcelium" Val=""/>
|
||||
<Option Name="SimulatorInstallDirVCS" Val=""/>
|
||||
<Option Name="SimulatorInstallDirRiviera" Val=""/>
|
||||
<Option Name="SimulatorInstallDirActiveHdl" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirModelSim" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirQuesta" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirXcelium" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
|
||||
<Option Name="SimulatorVersionXsim" Val="2024.1"/>
|
||||
<Option Name="SimulatorVersionModelSim" Val="2023.2"/>
|
||||
<Option Name="SimulatorVersionQuesta" Val="2023.2"/>
|
||||
<Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
|
||||
<Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
|
||||
<Option Name="SimulatorVersionRiviera" Val="2023.04"/>
|
||||
<Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
|
||||
<Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
|
||||
<Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
|
||||
<Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
|
||||
<Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
|
||||
<Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
|
||||
<Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
|
||||
<Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
|
||||
<Option Name="BoardPart" Val=""/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
|
||||
<Option Name="IPRepoPath" Val="$PPRDIR/../../adi_library"/>
|
||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||
<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
|
||||
<Option Name="IPCachePermission" Val="read"/>
|
||||
<Option Name="IPCachePermission" Val="write"/>
|
||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||
<Option Name="EnableResourceEstimation" Val="FALSE"/>
|
||||
<Option Name="SimCompileState" Val="TRUE"/>
|
||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="15"/>
|
||||
<Option Name="WTModelSimExportSim" Val="15"/>
|
||||
<Option Name="WTQuestaExportSim" Val="15"/>
|
||||
<Option Name="WTIesExportSim" Val="15"/>
|
||||
<Option Name="WTVcsExportSim" Val="15"/>
|
||||
<Option Name="WTRivieraExportSim" Val="15"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="15"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
<Option Name="SimTypes" Val="rtl"/>
|
||||
<Option Name="SimTypes" Val="bfm"/>
|
||||
<Option Name="SimTypes" Val="tlm"/>
|
||||
<Option Name="SimTypes" Val="tlm_dpi"/>
|
||||
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
||||
<Option Name="DcpsUptoDate" Val="TRUE"/>
|
||||
<Option Name="ClassicSocBoot" Val="FALSE"/>
|
||||
<Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
|
||||
</Configuration>
|
||||
<FileSets Version="1" Minor="32">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PSRCDIR/sources_1/bd/system_bd/system_bd.bd">
|
||||
<FileInfo>
|
||||
<Attr Name="ImportPath" Val="$PPRDIR/../../../dx/dx_sig/dx_sig_basic/dx_sig_basic.srcs/sources_1/bd/system_bd/system_bd.bd"/>
|
||||
<Attr Name="ImportTime" Val="1726045922"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
<CompFileExtendedInfo CompFileName="system_bd.bd" FileRelPathName="ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0.xci">
|
||||
<Proxy FileSetName="system_bd_axi_spi_engine_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="system_bd.bd" FileRelPathName="ip/system_bd_processing_system7_0_0/system_bd_processing_system7_0_0.xci">
|
||||
<Proxy FileSetName="system_bd_processing_system7_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="system_bd.bd" FileRelPathName="ip/system_bd_rst_ps7_0_50M_0/system_bd_rst_ps7_0_50M_0.xci">
|
||||
<Proxy FileSetName="system_bd_rst_ps7_0_50M_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="system_bd.bd" FileRelPathName="ip/system_bd_spi_engine_execution_0_0/system_bd_spi_engine_execution_0_0.xci">
|
||||
<Proxy FileSetName="system_bd_spi_engine_execution_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="system_bd.bd" FileRelPathName="ip/system_bd_xadc_wiz_0_0/system_bd_xadc_wiz_0_0.xci">
|
||||
<Proxy FileSetName="system_bd_xadc_wiz_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="system_bd.bd" FileRelPathName="ip/system_bd_xbar_0/system_bd_xbar_0.xci">
|
||||
<Proxy FileSetName="system_bd_xbar_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/ad9361_rx_map_cmos_dual.v">
|
||||
<FileInfo>
|
||||
<Attr Name="ImportPath" Val="$PPRDIR/../../../dx/dx_sig/dx_sig_basic/dx_sig_basic.srcs/sources_1/new/ad9361_rx_map_cmos_dual.v"/>
|
||||
<Attr Name="ImportTime" Val="1727337245"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/ad9361_tx_map_cmos_dual.v">
|
||||
<FileInfo>
|
||||
<Attr Name="ImportPath" Val="$PPRDIR/../../../dx/dx_sig/dx_sig_basic/dx_sig_basic.srcs/sources_1/new/ad9361_tx_map_cmos_dual.v"/>
|
||||
<Attr Name="ImportTime" Val="1725880682"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/defines.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/clk_dist.v">
|
||||
<FileInfo>
|
||||
<Attr Name="ImportPath" Val="$PPRDIR/../../../dx/dx_sig/dx_sig_basic/dx_sig_basic.srcs/sources_1/new/clk_dist.v"/>
|
||||
<Attr Name="ImportTime" Val="1727338445"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PGENDIR/sources_1/bd/system_bd/hdl/system_bd_wrapper.v">
|
||||
<FileInfo>
|
||||
<Attr Name="ImportPath" Val="$PPRDIR/../../../dx/dx_sig/dx_sig_basic/dx_sig_basic.srcs/sources_1/bd/system_bd/hdl/system_bd_wrapper.v"/>
|
||||
<Attr Name="ImportTime" Val="1726045922"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/tx_qpsk.v">
|
||||
<FileInfo>
|
||||
<Attr Name="ImportPath" Val="$PPRDIR/../../../dx/dx_sig/dx_sig_basic/dx_sig_basic.srcs/sources_1/new/tx_qpsk.v"/>
|
||||
<Attr Name="ImportTime" Val="1725882524"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/system_top.v">
|
||||
<FileInfo>
|
||||
<Attr Name="ImportPath" Val="$PPRDIR/../../../dx/dx_sig/dx_sig_basic/dx_sig_basic.srcs/sources_1/new/system_top.v"/>
|
||||
<Attr Name="ImportTime" Val="1727338838"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/ad9361_rx_map_cmos_single.v">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="ImportPath" Val="$PPRDIR/../../../dx/dx_sig/dx_sig_basic/dx_sig_basic.srcs/sources_1/new/ad9361_rx_map_cmos_single.v"/>
|
||||
<Attr Name="ImportTime" Val="1727337278"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/ad9361_tx_map_cmos_single.v">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="ImportPath" Val="$PPRDIR/../../../dx/dx_sig/dx_sig_basic/dx_sig_basic.srcs/sources_1/new/ad9361_tx_map_cmos_single.v"/>
|
||||
<Attr Name="ImportTime" Val="1727337289"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/ip/coe/hrc_64_12_025.coe">
|
||||
<FileInfo>
|
||||
<Attr Name="ImportPath" Val="$PPRDIR/../../../dx/dx_sig/dx_sig_basic/dx_sig_basic.srcs/sources_1/ip/coe/hrc_64_12_025.coe"/>
|
||||
<Attr Name="ImportTime" Val="1679754236"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/ip/coe/sweep_freq.coe">
|
||||
<FileInfo>
|
||||
<Attr Name="ImportPath" Val="$PPRDIR/../../../dx/dx_sig/dx_sig_basic/dx_sig_basic.srcs/sources_1/ip/coe/sweep_freq.coe"/>
|
||||
<Attr Name="ImportTime" Val="1679754236"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/ip/ad9361_clk_gen_cmos_1t1r/ad9361_clk_gen_cmos_1t1r.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="system_top"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<File Path="$PSRCDIR/constrs_1/new/sjl_2z7100_ad9528_2ad9361_physical.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="system_top"/>
|
||||
<Option Name="TopLib" Val="xil_defaultlib"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SelectedSimModel" Val="rtl"/>
|
||||
<Option Name="PamDesignTestbench" Val=""/>
|
||||
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
|
||||
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
|
||||
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="system_bd_spi_engine_execution_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_spi_engine_execution_0_0" RelGenDir="$PGENDIR/system_bd_spi_engine_execution_0_0">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="system_bd_spi_engine_execution_0_0"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="system_bd_processing_system7_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_processing_system7_0_0" RelGenDir="$PGENDIR/system_bd_processing_system7_0_0">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="system_bd_processing_system7_0_0"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="ad9361_fifo" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ad9361_fifo" RelGenDir="$PGENDIR/ad9361_fifo">
|
||||
<File Path="$PSRCDIR/sources_1/ip/ad9361_fifo/ad9361_fifo.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="ad9361_fifo"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="ila_trx" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ila_trx" RelGenDir="$PGENDIR/ila_trx">
|
||||
<File Path="$PSRCDIR/sources_1/ip/ila_trx/ila_trx.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="ila_trx"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="ad9361_clk_gen_cmos_2t2r" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ad9361_clk_gen_cmos_2t2r" RelGenDir="$PGENDIR/ad9361_clk_gen_cmos_2t2r">
|
||||
<File Path="$PSRCDIR/sources_1/ip/ad9361_clk_gen_cmos_2t2r/ad9361_clk_gen_cmos_2t2r.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="ad9361_clk_gen_cmos_2t2r"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="hrc_64_12_025" Type="BlockSrcs" RelSrcDir="$PSRCDIR/hrc_64_12_025" RelGenDir="$PGENDIR/hrc_64_12_025">
|
||||
<File Path="$PSRCDIR/sources_1/ip/hrc_64_12_025/hrc_64_12_025.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="hrc_64_12_025"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="dds_32b_8b" Type="BlockSrcs" RelSrcDir="$PSRCDIR/dds_32b_8b" RelGenDir="$PGENDIR/dds_32b_8b">
|
||||
<File Path="$PSRCDIR/sources_1/ip/dds_32b_8b/dds_32b_8b.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="dds_32b_8b"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="hop_rom" Type="BlockSrcs" RelSrcDir="$PSRCDIR/hop_rom" RelGenDir="$PGENDIR/hop_rom">
|
||||
<File Path="$PSRCDIR/sources_1/ip/hop_rom/hop_rom.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="hop_rom"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="cmpy_18x8" Type="BlockSrcs" RelSrcDir="$PSRCDIR/cmpy_18x8" RelGenDir="$PGENDIR/cmpy_18x8">
|
||||
<File Path="$PSRCDIR/sources_1/ip/cmpy_18x8/cmpy_18x8.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="cmpy_18x8"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="vio_manual_ctrl" Type="BlockSrcs" RelSrcDir="$PSRCDIR/vio_manual_ctrl" RelGenDir="$PGENDIR/vio_manual_ctrl">
|
||||
<File Path="$PSRCDIR/sources_1/ip/vio_manual_ctrl/vio_manual_ctrl.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="vio_manual_ctrl"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="system_bd_axi_spi_engine_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_axi_spi_engine_0_0" RelGenDir="$PGENDIR/system_bd_axi_spi_engine_0_0">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="system_bd_axi_spi_engine_0_0"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="system_bd_rst_ps7_0_50M_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_rst_ps7_0_50M_0" RelGenDir="$PGENDIR/system_bd_rst_ps7_0_50M_0">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="system_bd_rst_ps7_0_50M_0"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="system_bd_xadc_wiz_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_xadc_wiz_0_0" RelGenDir="$PGENDIR/system_bd_xadc_wiz_0_0">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="system_bd_xadc_wiz_0_0"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="system_bd_xbar_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_xbar_0" RelGenDir="$PGENDIR/system_bd_xbar_0">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="system_bd_xbar_0"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
<Option Name="Description" Val="Vivado Simulator"/>
|
||||
<Option Name="CompiledLib" Val="0"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ModelSim">
|
||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Questa">
|
||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Xcelium">
|
||||
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="VCS">
|
||||
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Riviera">
|
||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="22">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z100ffg900-2" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="system_bd_spi_engine_execution_0_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_spi_engine_execution_0_0" Part="xc7z100ffg900-2" ConstrsSet="system_bd_spi_engine_execution_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_spi_engine_execution_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_spi_engine_execution_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_spi_engine_execution_0_0_synth_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="system_bd_processing_system7_0_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_processing_system7_0_0" Part="xc7z100ffg900-2" ConstrsSet="system_bd_processing_system7_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_processing_system7_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_processing_system7_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_processing_system7_0_0_synth_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="ad9361_fifo_synth_1" Type="Ft3:Synth" SrcSet="ad9361_fifo" Part="xc7z100ffg900-2" ConstrsSet="ad9361_fifo" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ad9361_fifo_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ad9361_fifo_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ad9361_fifo_synth_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="ila_trx_synth_1" Type="Ft3:Synth" SrcSet="ila_trx" Part="xc7z100ffg900-2" ConstrsSet="ila_trx" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ila_trx_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ila_trx_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ila_trx_synth_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="ad9361_clk_gen_cmos_2t2r_synth_1" Type="Ft3:Synth" SrcSet="ad9361_clk_gen_cmos_2t2r" Part="xc7z100ffg900-2" ConstrsSet="ad9361_clk_gen_cmos_2t2r" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ad9361_clk_gen_cmos_2t2r_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ad9361_clk_gen_cmos_2t2r_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ad9361_clk_gen_cmos_2t2r_synth_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="hrc_64_12_025_synth_1" Type="Ft3:Synth" SrcSet="hrc_64_12_025" Part="xc7z100ffg900-2" ConstrsSet="hrc_64_12_025" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/hrc_64_12_025_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/hrc_64_12_025_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/hrc_64_12_025_synth_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="dds_32b_8b_synth_1" Type="Ft3:Synth" SrcSet="dds_32b_8b" Part="xc7z100ffg900-2" ConstrsSet="dds_32b_8b" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/dds_32b_8b_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/dds_32b_8b_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/dds_32b_8b_synth_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="hop_rom_synth_1" Type="Ft3:Synth" SrcSet="hop_rom" Part="xc7z100ffg900-2" ConstrsSet="hop_rom" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/hop_rom_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/hop_rom_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/hop_rom_synth_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="cmpy_18x8_synth_1" Type="Ft3:Synth" SrcSet="cmpy_18x8" Part="xc7z100ffg900-2" ConstrsSet="cmpy_18x8" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/cmpy_18x8_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/cmpy_18x8_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/cmpy_18x8_synth_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="vio_manual_ctrl_synth_1" Type="Ft3:Synth" SrcSet="vio_manual_ctrl" Part="xc7z100ffg900-2" ConstrsSet="vio_manual_ctrl" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/vio_manual_ctrl_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/vio_manual_ctrl_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/vio_manual_ctrl_synth_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="system_bd_axi_spi_engine_0_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_axi_spi_engine_0_0" Part="xc7z100ffg900-2" ConstrsSet="system_bd_axi_spi_engine_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_axi_spi_engine_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_axi_spi_engine_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_axi_spi_engine_0_0_synth_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="system_bd_rst_ps7_0_50M_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_rst_ps7_0_50M_0" Part="xc7z100ffg900-2" ConstrsSet="system_bd_rst_ps7_0_50M_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_rst_ps7_0_50M_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_rst_ps7_0_50M_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_rst_ps7_0_50M_0_synth_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="system_bd_xadc_wiz_0_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_xadc_wiz_0_0" Part="xc7z100ffg900-2" ConstrsSet="system_bd_xadc_wiz_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_xadc_wiz_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_xadc_wiz_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_xadc_wiz_0_0_synth_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="system_bd_xbar_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_xbar_0" Part="xc7z100ffg900-2" ConstrsSet="system_bd_xbar_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_xbar_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_xbar_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_xbar_0_synth_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z100ffg900-2" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 16 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="system_bd_spi_engine_execution_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z100ffg900-2" ConstrsSet="system_bd_spi_engine_execution_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_spi_engine_execution_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_spi_engine_execution_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_spi_engine_execution_0_0_impl_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="system_bd_processing_system7_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z100ffg900-2" ConstrsSet="system_bd_processing_system7_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_processing_system7_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_processing_system7_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_processing_system7_0_0_impl_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="ad9361_fifo_impl_1" Type="Ft2:EntireDesign" Part="xc7z100ffg900-2" ConstrsSet="ad9361_fifo" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ad9361_fifo_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ad9361_fifo_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ad9361_fifo_impl_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="ila_trx_impl_1" Type="Ft2:EntireDesign" Part="xc7z100ffg900-2" ConstrsSet="ila_trx" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ila_trx_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ila_trx_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ila_trx_impl_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="ad9361_clk_gen_cmos_2t2r_impl_1" Type="Ft2:EntireDesign" Part="xc7z100ffg900-2" ConstrsSet="ad9361_clk_gen_cmos_2t2r" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ad9361_clk_gen_cmos_2t2r_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ad9361_clk_gen_cmos_2t2r_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ad9361_clk_gen_cmos_2t2r_impl_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="hrc_64_12_025_impl_1" Type="Ft2:EntireDesign" Part="xc7z100ffg900-2" ConstrsSet="hrc_64_12_025" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="hrc_64_12_025_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/hrc_64_12_025_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/hrc_64_12_025_impl_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="dds_32b_8b_impl_1" Type="Ft2:EntireDesign" Part="xc7z100ffg900-2" ConstrsSet="dds_32b_8b" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="dds_32b_8b_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/dds_32b_8b_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/dds_32b_8b_impl_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="hop_rom_impl_1" Type="Ft2:EntireDesign" Part="xc7z100ffg900-2" ConstrsSet="hop_rom" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="hop_rom_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/hop_rom_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/hop_rom_impl_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="cmpy_18x8_impl_1" Type="Ft2:EntireDesign" Part="xc7z100ffg900-2" ConstrsSet="cmpy_18x8" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="cmpy_18x8_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/cmpy_18x8_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/cmpy_18x8_impl_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="vio_manual_ctrl_impl_1" Type="Ft2:EntireDesign" Part="xc7z100ffg900-2" ConstrsSet="vio_manual_ctrl" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="vio_manual_ctrl_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/vio_manual_ctrl_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/vio_manual_ctrl_impl_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="system_bd_axi_spi_engine_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z100ffg900-2" ConstrsSet="system_bd_axi_spi_engine_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_axi_spi_engine_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_axi_spi_engine_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_axi_spi_engine_0_0_impl_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="system_bd_rst_ps7_0_50M_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z100ffg900-2" ConstrsSet="system_bd_rst_ps7_0_50M_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_rst_ps7_0_50M_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_rst_ps7_0_50M_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_rst_ps7_0_50M_0_impl_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="system_bd_xadc_wiz_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z100ffg900-2" ConstrsSet="system_bd_xadc_wiz_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_xadc_wiz_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_xadc_wiz_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_xadc_wiz_0_0_impl_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="system_bd_xbar_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z100ffg900-2" ConstrsSet="system_bd_xbar_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_xbar_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_xbar_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_xbar_0_impl_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<Board/>
|
||||
<DashboardSummary Version="1" Minor="0">
|
||||
<Dashboards>
|
||||
<Dashboard Name="default_dashboard">
|
||||
<Gadgets>
|
||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||
</Gadget>
|
||||
</Gadgets>
|
||||
</Dashboard>
|
||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||
</Dashboards>
|
||||
</DashboardSummary>
|
||||
</Project>
|
||||
BIN
Binary file not shown.
Reference in New Issue
Block a user